1 /** 2 * @file spimss_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPIMSS_REVA_REGS_H_ 27 #define _SPIMSS_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spimss 65 * @defgroup spimss_registers SPIMSS_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. 67 * @details Serial Peripheral Interface. 68 */ 69 70 /** 71 * @ingroup spimss_registers 72 * Structure type to access the SPIMSS Registers. 73 */ 74 typedef struct { 75 __IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */ 76 __R uint16_t rsv_0x2; 77 __IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */ 78 __IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */ 79 __IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */ 80 __R uint32_t rsv_0x10; 81 __IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */ 82 __IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */ 83 __IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */ 84 } mxc_spimss_reva_regs_t; 85 86 /* Register offsets for module SPIMSS */ 87 /** 88 * @ingroup spimss_registers 89 * @defgroup SPIMSS_Register_Offsets Register Offsets 90 * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_SPIMSS_REVA_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_SPIMSS_REVA_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_SPIMSS_REVA_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_SPIMSS_REVA_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_SPIMSS_REVA_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */ 98 #define MXC_R_SPIMSS_REVA_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */ 99 #define MXC_R_SPIMSS_REVA_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */ 100 /**@} end of group spimss_registers */ 101 102 /** 103 * @ingroup spimss_registers 104 * @defgroup SPIMSS_DATA SPIMSS_DATA 105 * @brief SPI 16-bit Data Access 106 * @{ 107 */ 108 #define MXC_F_SPIMSS_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ 109 #define MXC_F_SPIMSS_REVA_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ 110 111 /**@} end of group SPIMSS_DATA_Register */ 112 113 /** 114 * @ingroup spimss_registers 115 * @defgroup SPIMSS_CTRL SPIMSS_CTRL 116 * @brief SPI Control Register. 117 * @{ 118 */ 119 #define MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ 120 #define MXC_F_SPIMSS_REVA_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ 121 #define MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE ((uint32_t)0x0UL) /**< CTRL_ENABLE_DISABLE Value */ 122 #define MXC_S_SPIMSS_REVA_CTRL_ENABLE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DISABLE Setting */ 123 #define MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE ((uint32_t)0x1UL) /**< CTRL_ENABLE_ENABLE Value */ 124 #define MXC_S_SPIMSS_REVA_CTRL_ENABLE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_ENABLE Setting */ 125 126 #define MXC_F_SPIMSS_REVA_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ 127 #define MXC_F_SPIMSS_REVA_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ 128 #define MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */ 129 #define MXC_S_SPIMSS_REVA_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */ 130 #define MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */ 131 #define MXC_S_SPIMSS_REVA_CTRL_MMEN_MASTER (MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */ 132 133 #define MXC_F_SPIMSS_REVA_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ 134 #define MXC_F_SPIMSS_REVA_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ 135 #define MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */ 136 #define MXC_S_SPIMSS_REVA_CTRL_WOR_DISABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */ 137 #define MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */ 138 #define MXC_S_SPIMSS_REVA_CTRL_WOR_ENABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */ 139 140 #define MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ 141 #define MXC_F_SPIMSS_REVA_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ 142 #define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */ 143 #define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */ 144 #define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */ 145 #define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */ 146 147 #define MXC_F_SPIMSS_REVA_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ 148 #define MXC_F_SPIMSS_REVA_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ 149 #define MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */ 150 #define MXC_S_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */ 151 #define MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */ 152 #define MXC_S_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */ 153 154 #define MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ 155 #define MXC_F_SPIMSS_REVA_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ 156 #define MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */ 157 #define MXC_S_SPIMSS_REVA_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */ 158 #define MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */ 159 #define MXC_S_SPIMSS_REVA_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */ 160 161 #define MXC_F_SPIMSS_REVA_CTRL_STR_POS 6 /**< CTRL_STR Position */ 162 #define MXC_F_SPIMSS_REVA_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_STR_POS)) /**< CTRL_STR Mask */ 163 #define MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */ 164 #define MXC_S_SPIMSS_REVA_CTRL_STR_COMPLETE (MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */ 165 #define MXC_V_SPIMSS_REVA_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */ 166 #define MXC_S_SPIMSS_REVA_CTRL_STR_START (MXC_V_SPIMSS_REVA_CTRL_STR_START << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_START Setting */ 167 168 #define MXC_F_SPIMSS_REVA_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ 169 #define MXC_F_SPIMSS_REVA_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ 170 #define MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */ 171 #define MXC_S_SPIMSS_REVA_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */ 172 #define MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */ 173 #define MXC_S_SPIMSS_REVA_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */ 174 175 /**@} end of group SPIMSS_CTRL_Register */ 176 177 /** 178 * @ingroup spimss_registers 179 * @defgroup SPIMSS_INT_FL SPIMSS_INT_FL 180 * @brief SPI Interrupt Flag Register. 181 * @{ 182 */ 183 #define MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ 184 #define MXC_F_SPIMSS_REVA_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ 185 #define MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED ((uint32_t)0x0UL) /**< INT_FL_SLAS_SELECTED Value */ 186 #define MXC_S_SPIMSS_REVA_INT_FL_SLAS_SELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_SELECTED Setting */ 187 #define MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< INT_FL_SLAS_NOTSELECTED Value */ 188 #define MXC_S_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_NOTSELECTED Setting */ 189 190 #define MXC_F_SPIMSS_REVA_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ 191 #define MXC_F_SPIMSS_REVA_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ 192 #define MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE ((uint32_t)0x0UL) /**< INT_FL_TXST_IDLE Value */ 193 #define MXC_S_SPIMSS_REVA_INT_FL_TXST_IDLE (MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_IDLE Setting */ 194 #define MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY ((uint32_t)0x1UL) /**< INT_FL_TXST_BUSY Value */ 195 #define MXC_S_SPIMSS_REVA_INT_FL_TXST_BUSY (MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_BUSY Setting */ 196 197 #define MXC_F_SPIMSS_REVA_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ 198 #define MXC_F_SPIMSS_REVA_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ 199 #define MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TUND_NOEVENT Value */ 200 #define MXC_S_SPIMSS_REVA_INT_FL_TUND_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_NOEVENT Setting */ 201 #define MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TUND_OCCURRED Value */ 202 #define MXC_S_SPIMSS_REVA_INT_FL_TUND_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_OCCURRED Setting */ 203 204 #define MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ 205 #define MXC_F_SPIMSS_REVA_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ 206 #define MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ROVR_NOEVENT Value */ 207 #define MXC_S_SPIMSS_REVA_INT_FL_ROVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_NOEVENT Setting */ 208 #define MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ROVR_OCCURRED Value */ 209 #define MXC_S_SPIMSS_REVA_INT_FL_ROVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_OCCURRED Setting */ 210 211 #define MXC_F_SPIMSS_REVA_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ 212 #define MXC_F_SPIMSS_REVA_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ 213 #define MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ABT_NOEVENT Value */ 214 #define MXC_S_SPIMSS_REVA_INT_FL_ABT_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_NOEVENT Setting */ 215 #define MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ABT_OCCURRED Value */ 216 #define MXC_S_SPIMSS_REVA_INT_FL_ABT_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_OCCURRED Setting */ 217 218 #define MXC_F_SPIMSS_REVA_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ 219 #define MXC_F_SPIMSS_REVA_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ 220 #define MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_COL_NOEVENT Value */ 221 #define MXC_S_SPIMSS_REVA_INT_FL_COL_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_NOEVENT Setting */ 222 #define MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_COL_OCCURRED Value */ 223 #define MXC_S_SPIMSS_REVA_INT_FL_COL_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_OCCURRED Setting */ 224 225 #define MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ 226 #define MXC_F_SPIMSS_REVA_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ 227 #define MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TOVR_NOEVENT Value */ 228 #define MXC_S_SPIMSS_REVA_INT_FL_TOVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_NOEVENT Setting */ 229 #define MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TOVR_OCCURRED Value */ 230 #define MXC_S_SPIMSS_REVA_INT_FL_TOVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_OCCURRED Setting */ 231 232 #define MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ 233 #define MXC_F_SPIMSS_REVA_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ 234 #define MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IRQ_INACTIVE Value */ 235 #define MXC_S_SPIMSS_REVA_INT_FL_IRQ_INACTIVE (MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_INACTIVE Setting */ 236 #define MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING ((uint32_t)0x1UL) /**< INT_FL_IRQ_PENDING Value */ 237 #define MXC_S_SPIMSS_REVA_INT_FL_IRQ_PENDING (MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_PENDING Setting */ 238 239 /**@} end of group SPIMSS_INT_FL_Register */ 240 241 /** 242 * @ingroup spimss_registers 243 * @defgroup SPIMSS_MODE SPIMSS_MODE 244 * @brief SPI Mode Register. 245 * @{ 246 */ 247 #define MXC_F_SPIMSS_REVA_MODE_SSV_POS 0 /**< MODE_SSV Position */ 248 #define MXC_F_SPIMSS_REVA_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SSV_POS)) /**< MODE_SSV Mask */ 249 #define MXC_V_SPIMSS_REVA_MODE_SSV_LO ((uint32_t)0x0UL) /**< MODE_SSV_LO Value */ 250 #define MXC_S_SPIMSS_REVA_MODE_SSV_LO (MXC_V_SPIMSS_REVA_MODE_SSV_LO << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_LO Setting */ 251 #define MXC_V_SPIMSS_REVA_MODE_SSV_HI ((uint32_t)0x1UL) /**< MODE_SSV_HI Value */ 252 #define MXC_S_SPIMSS_REVA_MODE_SSV_HI (MXC_V_SPIMSS_REVA_MODE_SSV_HI << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_HI Setting */ 253 254 #define MXC_F_SPIMSS_REVA_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */ 255 #define MXC_F_SPIMSS_REVA_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */ 256 #define MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT ((uint32_t)0x0UL) /**< MODE_SS_IO_INPUT Value */ 257 #define MXC_S_SPIMSS_REVA_MODE_SS_IO_INPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_INPUT Setting */ 258 #define MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT ((uint32_t)0x1UL) /**< MODE_SS_IO_OUTPUT Value */ 259 #define MXC_S_SPIMSS_REVA_MODE_SS_IO_OUTPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_OUTPUT Setting */ 260 261 #define MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */ 262 #define MXC_F_SPIMSS_REVA_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */ 263 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */ 264 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */ 265 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */ 266 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */ 267 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */ 268 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */ 269 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */ 270 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */ 271 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */ 272 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */ 273 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */ 274 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */ 275 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */ 276 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */ 277 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */ 278 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */ 279 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */ 280 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */ 281 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */ 282 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */ 283 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */ 284 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */ 285 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */ 286 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */ 287 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */ 288 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */ 289 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */ 290 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */ 291 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */ 292 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */ 293 #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */ 294 #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */ 295 296 #define MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */ 297 #define MXC_F_SPIMSS_REVA_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */ 298 #define MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MODE_TX_LJ_DISABLE Value */ 299 #define MXC_S_SPIMSS_REVA_MODE_TX_LJ_DISABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_DISABLE Setting */ 300 #define MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MODE_TX_LJ_ENABLE Value */ 301 #define MXC_S_SPIMSS_REVA_MODE_TX_LJ_ENABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_ENABLE Setting */ 302 303 /**@} end of group SPIMSS_MODE_Register */ 304 305 /** 306 * @ingroup spimss_registers 307 * @defgroup SPIMSS_BRG SPIMSS_BRG 308 * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for 309 * the SPI Baud Rate Generator. The reload value must be greater than or equal to 310 * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 311 * 4). 312 * @{ 313 */ 314 #define MXC_F_SPIMSS_REVA_BRG_DIV_POS 0 /**< BRG_DIV Position */ 315 #define MXC_F_SPIMSS_REVA_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_BRG_DIV_POS)) /**< BRG_DIV Mask */ 316 317 /**@} end of group SPIMSS_BRG_Register */ 318 319 /** 320 * @ingroup spimss_registers 321 * @defgroup SPIMSS_DMA SPIMSS_DMA 322 * @brief SPI DMA Register. 323 * @{ 324 */ 325 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ 326 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ 327 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */ 328 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */ 329 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */ 330 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */ 331 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */ 332 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */ 333 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */ 334 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */ 335 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */ 336 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */ 337 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */ 338 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */ 339 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */ 340 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */ 341 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */ 342 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */ 343 344 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ 345 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ 346 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLR_COMPLETE Value */ 347 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_COMPLETE Setting */ 348 #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLR_START Value */ 349 #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_START Setting */ 350 351 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 352 #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 353 354 #define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 355 #define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 356 #define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */ 357 #define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */ 358 #define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */ 359 #define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */ 360 361 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ 362 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ 363 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */ 364 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */ 365 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */ 366 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */ 367 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */ 368 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */ 369 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */ 370 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */ 371 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */ 372 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */ 373 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */ 374 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */ 375 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */ 376 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */ 377 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */ 378 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */ 379 380 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ 381 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ 382 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLR_COMPLETE Value */ 383 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_COMPLETE Setting */ 384 #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLR_START Value */ 385 #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_START Setting */ 386 387 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 388 #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 389 390 #define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 391 #define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 392 #define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */ 393 #define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */ 394 #define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */ 395 #define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */ 396 397 /**@} end of group SPIMSS_DMA_Register */ 398 399 /** 400 * @ingroup spimss_registers 401 * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL 402 * @brief I2S Control Register. 403 * @{ 404 */ 405 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ 406 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ 407 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */ 408 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */ 409 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */ 410 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */ 411 412 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ 413 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ 414 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */ 415 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */ 416 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */ 417 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */ 418 419 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ 420 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ 421 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */ 422 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */ 423 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */ 424 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */ 425 426 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ 427 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ 428 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */ 429 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */ 430 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */ 431 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */ 432 433 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ 434 #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ 435 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */ 436 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */ 437 #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */ 438 #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */ 439 440 /**@} end of group SPIMSS_I2S_CTRL_Register */ 441 442 #ifdef __cplusplus 443 } 444 #endif 445 446 #endif /* _SPIMSS_REVA_REGS_H_ */ 447
