1 /** 2 * @file sfe_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SFE_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SFE_REVA_REGS_H_ 27 #define _SFE_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup sfe_reva 65 * @defgroup sfe_reva_registers SFE_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SFE_REVA Peripheral Module. 67 * @details Serial Flash Emulator. 68 */ 69 70 /** 71 * @ingroup sfe_reva_registers 72 * Structure type to access the SFE_REVA Registers. 73 */ 74 typedef struct { 75 __R uint32_t rsv_0x0_0x3ff[256]; 76 __IO uint32_t cfg; /**< <tt>\b 0x0400:</tt> SFE_REVA CFG Register */ 77 __R uint32_t rsv_0x404; 78 __IO uint32_t hfsa; /**< <tt>\b 0x0408:</tt> SFE_REVA HFSA Register */ 79 __IO uint32_t hrsa; /**< <tt>\b 0x040C:</tt> SFE_REVA HRSA Register */ 80 __IO uint32_t sfdp_sba; /**< <tt>\b 0x0410:</tt> SFE_REVA SFDP_SBA Register */ 81 __IO uint32_t flash_sba; /**< <tt>\b 0x0414:</tt> SFE_REVA FLASH_SBA Register */ 82 __IO uint32_t flash_sta; /**< <tt>\b 0x0418:</tt> SFE_REVA FLASH_STA Register */ 83 __IO uint32_t ram_sba; /**< <tt>\b 0x041C:</tt> SFE_REVA RAM_SBA Register */ 84 __IO uint32_t ram_sta; /**< <tt>\b 0x0420:</tt> SFE_REVA RAM_STA Register */ 85 } mxc_sfe_reva_regs_t; 86 87 /* Register offsets for module SFE_REVA */ 88 /** 89 * @ingroup sfe_reva_registers 90 * @defgroup SFE_REVA_Register_Offsets Register Offsets 91 * @brief SFE_REVA Peripheral Register Offsets from the SFE_REVA Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SFE_REVA_CFG ((uint32_t)0x00000400UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0400</tt> */ 95 #define MXC_R_SFE_REVA_HFSA ((uint32_t)0x00000408UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0408</tt> */ 96 #define MXC_R_SFE_REVA_HRSA ((uint32_t)0x0000040CUL) /**< Offset from SFE_REVA Base Address: <tt> 0x040C</tt> */ 97 #define MXC_R_SFE_REVA_SFDP_SBA ((uint32_t)0x00000410UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0410</tt> */ 98 #define MXC_R_SFE_REVA_FLASH_SBA ((uint32_t)0x00000414UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0414</tt> */ 99 #define MXC_R_SFE_REVA_FLASH_STA ((uint32_t)0x00000418UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0418</tt> */ 100 #define MXC_R_SFE_REVA_RAM_SBA ((uint32_t)0x0000041CUL) /**< Offset from SFE_REVA Base Address: <tt> 0x041C</tt> */ 101 #define MXC_R_SFE_REVA_RAM_STA ((uint32_t)0x00000420UL) /**< Offset from SFE_REVA Base Address: <tt> 0x0420</tt> */ 102 /**@} end of group sfe_reva_registers */ 103 104 /** 105 * @ingroup sfe_reva_registers 106 * @defgroup SFE_REVA_CFG SFE_REVA_CFG 107 * @brief SFE Configuration Register. 108 * @{ 109 */ 110 #define MXC_F_SFE_REVA_CFG_DRLE_POS 0 /**< CFG_DRLE Position */ 111 #define MXC_F_SFE_REVA_CFG_DRLE ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_DRLE_POS)) /**< CFG_DRLE Mask */ 112 113 #define MXC_F_SFE_REVA_CFG_FLOCK_POS 15 /**< CFG_FLOCK Position */ 114 #define MXC_F_SFE_REVA_CFG_FLOCK ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_FLOCK_POS)) /**< CFG_FLOCK Mask */ 115 116 #define MXC_F_SFE_REVA_CFG_RD_EN_POS 16 /**< CFG_RD_EN Position */ 117 #define MXC_F_SFE_REVA_CFG_RD_EN ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_RD_EN_POS)) /**< CFG_RD_EN Mask */ 118 119 #define MXC_F_SFE_REVA_CFG_WR_EN_POS 17 /**< CFG_WR_EN Position */ 120 #define MXC_F_SFE_REVA_CFG_WR_EN ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_WR_EN_POS)) /**< CFG_WR_EN Mask */ 121 122 #define MXC_F_SFE_REVA_CFG_RRLOCK_POS 22 /**< CFG_RRLOCK Position */ 123 #define MXC_F_SFE_REVA_CFG_RRLOCK ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_RRLOCK_POS)) /**< CFG_RRLOCK Mask */ 124 125 #define MXC_F_SFE_REVA_CFG_RWLOCK_POS 23 /**< CFG_RWLOCK Position */ 126 #define MXC_F_SFE_REVA_CFG_RWLOCK ((uint32_t)(0x1UL << MXC_F_SFE_REVA_CFG_RWLOCK_POS)) /**< CFG_RWLOCK Mask */ 127 128 /**@} end of group SFE_REVA_CFG_Register */ 129 130 /** 131 * @ingroup sfe_reva_registers 132 * @defgroup SFE_REVA_HFSA SFE_REVA_HFSA 133 * @brief SFE Host Flash Start Address Register. 134 * @{ 135 */ 136 #define MXC_F_SFE_REVA_HFSA_HFSA_POS 10 /**< HFSA_HFSA Position */ 137 #define MXC_F_SFE_REVA_HFSA_HFSA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_HFSA_HFSA_POS)) /**< HFSA_HFSA Mask */ 138 139 /**@} end of group SFE_REVA_HFSA_Register */ 140 141 /** 142 * @ingroup sfe_reva_registers 143 * @defgroup SFE_REVA_HRSA SFE_REVA_HRSA 144 * @brief SFE Host RAM Start Address Register. 145 * @{ 146 */ 147 #define MXC_F_SFE_REVA_HRSA_HRSA_POS 10 /**< HRSA_HRSA Position */ 148 #define MXC_F_SFE_REVA_HRSA_HRSA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_HRSA_HRSA_POS)) /**< HRSA_HRSA Mask */ 149 150 /**@} end of group SFE_REVA_HRSA_Register */ 151 152 /** 153 * @ingroup sfe_reva_registers 154 * @defgroup SFE_REVA_SFDP_SBA SFE_REVA_SFDP_SBA 155 * @brief SFE Discoverable Parameter System Base Register. 156 * @{ 157 */ 158 #define MXC_F_SFE_REVA_SFDP_SBA_SFDP_SBA_POS 8 /**< SFDP_SBA_SFDP_SBA Position */ 159 #define MXC_F_SFE_REVA_SFDP_SBA_SFDP_SBA ((uint32_t)(0xFFFFFFUL << MXC_F_SFE_REVA_SFDP_SBA_SFDP_SBA_POS)) /**< SFDP_SBA_SFDP_SBA Mask */ 160 161 /**@} end of group SFE_REVA_SFDP_SBA_Register */ 162 163 /** 164 * @ingroup sfe_reva_registers 165 * @defgroup SFE_REVA_FLASH_SBA SFE_REVA_FLASH_SBA 166 * @brief Flash System Base Address Register. 167 * @{ 168 */ 169 #define MXC_F_SFE_REVA_FLASH_SBA_FLASH_SBA_POS 10 /**< FLASH_SBA_FLASH_SBA Position */ 170 #define MXC_F_SFE_REVA_FLASH_SBA_FLASH_SBA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_FLASH_SBA_FLASH_SBA_POS)) /**< FLASH_SBA_FLASH_SBA Mask */ 171 172 /**@} end of group SFE_REVA_FLASH_SBA_Register */ 173 174 /** 175 * @ingroup sfe_reva_registers 176 * @defgroup SFE_REVA_FLASH_STA SFE_REVA_FLASH_STA 177 * @brief Flash System Top Address Register. 178 * @{ 179 */ 180 #define MXC_F_SFE_REVA_FLASH_STA_FLASH_STA_POS 10 /**< FLASH_STA_FLASH_STA Position */ 181 #define MXC_F_SFE_REVA_FLASH_STA_FLASH_STA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_FLASH_STA_FLASH_STA_POS)) /**< FLASH_STA_FLASH_STA Mask */ 182 183 /**@} end of group SFE_REVA_FLASH_STA_Register */ 184 185 /** 186 * @ingroup sfe_reva_registers 187 * @defgroup SFE_REVA_RAM_SBA SFE_REVA_RAM_SBA 188 * @brief RAM System Base Address Register. 189 * @{ 190 */ 191 #define MXC_F_SFE_REVA_RAM_SBA_RAM_SBA_POS 10 /**< RAM_SBA_RAM_SBA Position */ 192 #define MXC_F_SFE_REVA_RAM_SBA_RAM_SBA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_RAM_SBA_RAM_SBA_POS)) /**< RAM_SBA_RAM_SBA Mask */ 193 194 /**@} end of group SFE_REVA_RAM_SBA_Register */ 195 196 /** 197 * @ingroup sfe_reva_registers 198 * @defgroup SFE_REVA_RAM_STA SFE_REVA_RAM_STA 199 * @brief RAM System Top Address Register. 200 * @{ 201 */ 202 #define MXC_F_SFE_REVA_RAM_STA_RAM_STA_POS 10 /**< RAM_STA_RAM_STA Position */ 203 #define MXC_F_SFE_REVA_RAM_STA_RAM_STA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_REVA_RAM_STA_RAM_STA_POS)) /**< RAM_STA_RAM_STA Mask */ 204 205 /**@} end of group SFE_REVA_RAM_STA_Register */ 206 207 #ifdef __cplusplus 208 } 209 #endif 210 211 #endif /* _SFE_REVA_REGS_H_ */ 212
