1 /** 2 * @file sdhc_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SDHC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SDHC_REVA_REGS_H_ 27 #define _SDHC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup sdhc_reva 65 * @defgroup sdhc_reva_registers SDHC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SDHC_REVA Peripheral Module. 67 * @details SDHC/SDIO Controller 68 */ 69 70 /** 71 * @ingroup sdhc_reva_registers 72 * Structure type to access the SDHC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t sdma; /**< <tt>\b 0x00:</tt> SDHC_REVA SDMA Register */ 76 __IO uint16_t blk_size; /**< <tt>\b 0x04:</tt> SDHC_REVA BLK_SIZE Register */ 77 __IO uint16_t blk_cnt; /**< <tt>\b 0x06:</tt> SDHC_REVA BLK_CNT Register */ 78 __IO uint32_t arg_1; /**< <tt>\b 0x08:</tt> SDHC_REVA ARG_1 Register */ 79 __IO uint16_t trans; /**< <tt>\b 0x0C:</tt> SDHC_REVA TRANS Register */ 80 __IO uint16_t cmd; /**< <tt>\b 0x0E:</tt> SDHC_REVA CMD Register */ 81 __IO uint32_t resp[4]; /**< <tt>\b 0x010:</tt> SDHC_REVA RESP Register */ 82 __IO uint32_t buffer; /**< <tt>\b 0x20:</tt> SDHC_REVA BUFFER Register */ 83 __I uint32_t present; /**< <tt>\b 0x024:</tt> SDHC_REVA PRESENT Register */ 84 __IO uint8_t host_cn_1; /**< <tt>\b 0x028:</tt> SDHC_REVA HOST_CN_1 Register */ 85 __IO uint8_t pwr; /**< <tt>\b 0x029:</tt> SDHC_REVA PWR Register */ 86 __IO uint8_t blk_gap; /**< <tt>\b 0x02A:</tt> SDHC_REVA BLK_GAP Register */ 87 __IO uint8_t wakeup; /**< <tt>\b 0x02B:</tt> SDHC_REVA WAKEUP Register */ 88 __IO uint16_t clk_cn; /**< <tt>\b 0x02C:</tt> SDHC_REVA CLK_CN Register */ 89 __IO uint8_t to; /**< <tt>\b 0x02E:</tt> SDHC_REVA TO Register */ 90 __IO uint8_t sw_reset; /**< <tt>\b 0x02F:</tt> SDHC_REVA SW_RESET Register */ 91 __IO uint16_t int_stat; /**< <tt>\b 0x030:</tt> SDHC_REVA INT_STAT Register */ 92 __IO uint16_t er_int_stat; /**< <tt>\b 0x032:</tt> SDHC_REVA ER_INT_STAT Register */ 93 __IO uint16_t int_en; /**< <tt>\b 0x034:</tt> SDHC_REVA INT_EN Register */ 94 __IO uint16_t er_int_en; /**< <tt>\b 0x36:</tt> SDHC_REVA ER_INT_EN Register */ 95 __IO uint16_t int_signal; /**< <tt>\b 0x038:</tt> SDHC_REVA INT_SIGNAL Register */ 96 __IO uint16_t er_int_signal; /**< <tt>\b 0x03A:</tt> SDHC_REVA ER_INT_SIGNAL Register */ 97 __IO uint16_t auto_cmd_er; /**< <tt>\b 0x03C:</tt> SDHC_REVA AUTO_CMD_ER Register */ 98 __IO uint16_t host_cn_2; /**< <tt>\b 0x03E:</tt> SDHC_REVA HOST_CN_2 Register */ 99 __I uint32_t cfg_0; /**< <tt>\b 0x040:</tt> SDHC_REVA CFG_0 Register */ 100 __I uint32_t cfg_1; /**< <tt>\b 0x044:</tt> SDHC_REVA CFG_1 Register */ 101 __I uint32_t max_curr_cfg; /**< <tt>\b 0x048:</tt> SDHC_REVA MAX_CURR_CFG Register */ 102 __R uint32_t rsv_0x4c; 103 __O uint16_t force_cmd; /**< <tt>\b 0x050:</tt> SDHC_REVA FORCE_CMD Register */ 104 __IO uint16_t force_event_int_stat; /**< <tt>\b 0x052:</tt> SDHC_REVA FORCE_EVENT_INT_STAT Register */ 105 __IO uint8_t adma_er; /**< <tt>\b 0x054:</tt> SDHC_REVA ADMA_ER Register */ 106 __R uint8_t rsv_0x55_0x57[3]; 107 __IO uint32_t adma_addr_0; /**< <tt>\b 0x058:</tt> SDHC_REVA ADMA_ADDR_0 Register */ 108 __IO uint32_t adma_addr_1; /**< <tt>\b 0x05C:</tt> SDHC_REVA ADMA_ADDR_1 Register */ 109 __I uint16_t preset_0; /**< <tt>\b 0x060:</tt> SDHC_REVA PRESET_0 Register */ 110 __I uint16_t preset_1; /**< <tt>\b 0x062:</tt> SDHC_REVA PRESET_1 Register */ 111 __I uint16_t preset_2; /**< <tt>\b 0x064:</tt> SDHC_REVA PRESET_2 Register */ 112 __I uint16_t preset_3; /**< <tt>\b 0x066:</tt> SDHC_REVA PRESET_3 Register */ 113 __I uint16_t preset_4; /**< <tt>\b 0x068:</tt> SDHC_REVA PRESET_4 Register */ 114 __I uint16_t preset_5; /**< <tt>\b 0x06A:</tt> SDHC_REVA PRESET_5 Register */ 115 __I uint16_t preset_6; /**< <tt>\b 0x06C:</tt> SDHC_REVA PRESET_6 Register */ 116 __I uint16_t preset_7; /**< <tt>\b 0x06E:</tt> SDHC_REVA PRESET_7 Register */ 117 __R uint32_t rsv_0x70_0xfb[35]; 118 __I uint16_t slot_int; /**< <tt>\b 0x0FC:</tt> SDHC_REVA SLOT_INT Register */ 119 __IO uint16_t host_cn_ver; /**< <tt>\b 0x0FE:</tt> SDHC_REVA HOST_CN_VER Register */ 120 } mxc_sdhc_reva_regs_t; 121 122 /* Register offsets for module SDHC_REVA */ 123 /** 124 * @ingroup sdhc_reva_registers 125 * @defgroup SDHC_REVA_Register_Offsets Register Offsets 126 * @brief SDHC_REVA Peripheral Register Offsets from the SDHC_REVA Base Peripheral Address. 127 * @{ 128 */ 129 #define MXC_R_SDHC_REVA_SDMA ((uint32_t)0x00000000UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0000</tt> */ 130 #define MXC_R_SDHC_REVA_BLK_SIZE ((uint32_t)0x00000004UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0004</tt> */ 131 #define MXC_R_SDHC_REVA_BLK_CNT ((uint32_t)0x00000006UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0006</tt> */ 132 #define MXC_R_SDHC_REVA_ARG_1 ((uint32_t)0x00000008UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0008</tt> */ 133 #define MXC_R_SDHC_REVA_TRANS ((uint32_t)0x0000000CUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x000C</tt> */ 134 #define MXC_R_SDHC_REVA_CMD ((uint32_t)0x0000000EUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x000E</tt> */ 135 #define MXC_R_SDHC_REVA_RESP ((uint32_t)0x00000010UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0010</tt> */ 136 #define MXC_R_SDHC_REVA_BUFFER ((uint32_t)0x00000020UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0020</tt> */ 137 #define MXC_R_SDHC_REVA_PRESENT ((uint32_t)0x00000024UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0024</tt> */ 138 #define MXC_R_SDHC_REVA_HOST_CN_1 ((uint32_t)0x00000028UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0028</tt> */ 139 #define MXC_R_SDHC_REVA_PWR ((uint32_t)0x00000029UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0029</tt> */ 140 #define MXC_R_SDHC_REVA_BLK_GAP ((uint32_t)0x0000002AUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x002A</tt> */ 141 #define MXC_R_SDHC_REVA_WAKEUP ((uint32_t)0x0000002BUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x002B</tt> */ 142 #define MXC_R_SDHC_REVA_CLK_CN ((uint32_t)0x0000002CUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x002C</tt> */ 143 #define MXC_R_SDHC_REVA_TO ((uint32_t)0x0000002EUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x002E</tt> */ 144 #define MXC_R_SDHC_REVA_SW_RESET ((uint32_t)0x0000002FUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x002F</tt> */ 145 #define MXC_R_SDHC_REVA_INT_STAT ((uint32_t)0x00000030UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0030</tt> */ 146 #define MXC_R_SDHC_REVA_ER_INT_STAT ((uint32_t)0x00000032UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0032</tt> */ 147 #define MXC_R_SDHC_REVA_INT_EN ((uint32_t)0x00000034UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0034</tt> */ 148 #define MXC_R_SDHC_REVA_ER_INT_EN ((uint32_t)0x00000036UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0036</tt> */ 149 #define MXC_R_SDHC_REVA_INT_SIGNAL ((uint32_t)0x00000038UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0038</tt> */ 150 #define MXC_R_SDHC_REVA_ER_INT_SIGNAL ((uint32_t)0x0000003AUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x003A</tt> */ 151 #define MXC_R_SDHC_REVA_AUTO_CMD_ER ((uint32_t)0x0000003CUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x003C</tt> */ 152 #define MXC_R_SDHC_REVA_HOST_CN_2 ((uint32_t)0x0000003EUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x003E</tt> */ 153 #define MXC_R_SDHC_REVA_CFG_0 ((uint32_t)0x00000040UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0040</tt> */ 154 #define MXC_R_SDHC_REVA_CFG_1 ((uint32_t)0x00000044UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0044</tt> */ 155 #define MXC_R_SDHC_REVA_MAX_CURR_CFG ((uint32_t)0x00000048UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0048</tt> */ 156 #define MXC_R_SDHC_REVA_FORCE_CMD ((uint32_t)0x00000050UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0050</tt> */ 157 #define MXC_R_SDHC_REVA_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0052</tt> */ 158 #define MXC_R_SDHC_REVA_ADMA_ER ((uint32_t)0x00000054UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0054</tt> */ 159 #define MXC_R_SDHC_REVA_ADMA_ADDR_0 ((uint32_t)0x00000058UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0058</tt> */ 160 #define MXC_R_SDHC_REVA_ADMA_ADDR_1 ((uint32_t)0x0000005CUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x005C</tt> */ 161 #define MXC_R_SDHC_REVA_PRESET_0 ((uint32_t)0x00000060UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0060</tt> */ 162 #define MXC_R_SDHC_REVA_PRESET_1 ((uint32_t)0x00000062UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0062</tt> */ 163 #define MXC_R_SDHC_REVA_PRESET_2 ((uint32_t)0x00000064UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0064</tt> */ 164 #define MXC_R_SDHC_REVA_PRESET_3 ((uint32_t)0x00000066UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0066</tt> */ 165 #define MXC_R_SDHC_REVA_PRESET_4 ((uint32_t)0x00000068UL) /**< Offset from SDHC_REVA Base Address: <tt> 0x0068</tt> */ 166 #define MXC_R_SDHC_REVA_PRESET_5 ((uint32_t)0x0000006AUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x006A</tt> */ 167 #define MXC_R_SDHC_REVA_PRESET_6 ((uint32_t)0x0000006CUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x006C</tt> */ 168 #define MXC_R_SDHC_REVA_PRESET_7 ((uint32_t)0x0000006EUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x006E</tt> */ 169 #define MXC_R_SDHC_REVA_SLOT_INT ((uint32_t)0x000000FCUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x00FC</tt> */ 170 #define MXC_R_SDHC_REVA_HOST_CN_VER ((uint32_t)0x000000FEUL) /**< Offset from SDHC_REVA Base Address: <tt> 0x00FE</tt> */ 171 /**@} end of group sdhc_reva_registers */ 172 173 /** 174 * @ingroup sdhc_reva_registers 175 * @defgroup SDHC_REVA_SDMA SDHC_REVA_SDMA 176 * @brief SDMA System Address / Argument 2. 177 * @{ 178 */ 179 #define MXC_F_SDHC_REVA_SDMA_ADDR_POS 0 /**< SDMA_ADDR Position */ 180 #define MXC_F_SDHC_REVA_SDMA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_SDMA_ADDR_POS)) /**< SDMA_ADDR Mask */ 181 182 /**@} end of group SDHC_REVA_SDMA_Register */ 183 184 /** 185 * @ingroup sdhc_reva_registers 186 * @defgroup SDHC_REVA_BLK_SIZE SDHC_REVA_BLK_SIZE 187 * @brief Block Size. 188 * @{ 189 */ 190 #define MXC_F_SDHC_REVA_BLK_SIZE_TRANS_POS 0 /**< BLK_SIZE_TRANS Position */ 191 #define MXC_F_SDHC_REVA_BLK_SIZE_TRANS ((uint16_t)(0xFFFUL << MXC_F_SDHC_REVA_BLK_SIZE_TRANS_POS)) /**< BLK_SIZE_TRANS Mask */ 192 193 #define MXC_F_SDHC_REVA_BLK_SIZE_HOST_BUFF_POS 12 /**< BLK_SIZE_HOST_BUFF Position */ 194 #define MXC_F_SDHC_REVA_BLK_SIZE_HOST_BUFF ((uint16_t)(0x7UL << MXC_F_SDHC_REVA_BLK_SIZE_HOST_BUFF_POS)) /**< BLK_SIZE_HOST_BUFF Mask */ 195 196 /**@} end of group SDHC_REVA_BLK_SIZE_Register */ 197 198 /** 199 * @ingroup sdhc_reva_registers 200 * @defgroup SDHC_REVA_BLK_CNT SDHC_REVA_BLK_CNT 201 * @brief Block Count. 202 * @{ 203 */ 204 #define MXC_F_SDHC_REVA_BLK_CNT_COUNT_POS 0 /**< BLK_CNT_COUNT Position */ 205 #define MXC_F_SDHC_REVA_BLK_CNT_COUNT ((uint16_t)(0xFFFFUL << MXC_F_SDHC_REVA_BLK_CNT_COUNT_POS)) /**< BLK_CNT_COUNT Mask */ 206 207 /**@} end of group SDHC_REVA_BLK_CNT_Register */ 208 209 /** 210 * @ingroup sdhc_reva_registers 211 * @defgroup SDHC_REVA_ARG_1 SDHC_REVA_ARG_1 212 * @brief Argument 1. 213 * @{ 214 */ 215 #define MXC_F_SDHC_REVA_ARG_1_CMD_POS 0 /**< ARG_1_CMD Position */ 216 #define MXC_F_SDHC_REVA_ARG_1_CMD ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_ARG_1_CMD_POS)) /**< ARG_1_CMD Mask */ 217 218 /**@} end of group SDHC_REVA_ARG_1_Register */ 219 220 /** 221 * @ingroup sdhc_reva_registers 222 * @defgroup SDHC_REVA_TRANS SDHC_REVA_TRANS 223 * @brief Transfer Mode. 224 * @{ 225 */ 226 #define MXC_F_SDHC_REVA_TRANS_DMA_EN_POS 0 /**< TRANS_DMA_EN Position */ 227 #define MXC_F_SDHC_REVA_TRANS_DMA_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_TRANS_DMA_EN_POS)) /**< TRANS_DMA_EN Mask */ 228 229 #define MXC_F_SDHC_REVA_TRANS_BLK_CNT_EN_POS 1 /**< TRANS_BLK_CNT_EN Position */ 230 #define MXC_F_SDHC_REVA_TRANS_BLK_CNT_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_TRANS_BLK_CNT_EN_POS)) /**< TRANS_BLK_CNT_EN Mask */ 231 232 #define MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN_POS 2 /**< TRANS_AUTO_CMD_EN Position */ 233 #define MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN_POS)) /**< TRANS_AUTO_CMD_EN Mask */ 234 #define MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_DISABLE ((uint16_t)0x0UL) /**< TRANS_AUTO_CMD_EN_DISABLE Value */ 235 #define MXC_S_SDHC_REVA_TRANS_AUTO_CMD_EN_DISABLE (MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_DISABLE << MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_DISABLE Setting */ 236 #define MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD12 ((uint16_t)0x1UL) /**< TRANS_AUTO_CMD_EN_CMD12 Value */ 237 #define MXC_S_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD12 (MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD12 << MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD12 Setting */ 238 #define MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD23 ((uint16_t)0x2UL) /**< TRANS_AUTO_CMD_EN_CMD23 Value */ 239 #define MXC_S_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD23 (MXC_V_SDHC_REVA_TRANS_AUTO_CMD_EN_CMD23 << MXC_F_SDHC_REVA_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD23 Setting */ 240 241 #define MXC_F_SDHC_REVA_TRANS_READ_WRITE_POS 4 /**< TRANS_READ_WRITE Position */ 242 #define MXC_F_SDHC_REVA_TRANS_READ_WRITE ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_TRANS_READ_WRITE_POS)) /**< TRANS_READ_WRITE Mask */ 243 244 #define MXC_F_SDHC_REVA_TRANS_MULTI_POS 5 /**< TRANS_MULTI Position */ 245 #define MXC_F_SDHC_REVA_TRANS_MULTI ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_TRANS_MULTI_POS)) /**< TRANS_MULTI Mask */ 246 247 /**@} end of group SDHC_REVA_TRANS_Register */ 248 249 /** 250 * @ingroup sdhc_reva_registers 251 * @defgroup SDHC_REVA_CMD SDHC_REVA_CMD 252 * @brief Command. 253 * @{ 254 */ 255 #define MXC_F_SDHC_REVA_CMD_RESP_TYPE_POS 0 /**< CMD_RESP_TYPE Position */ 256 #define MXC_F_SDHC_REVA_CMD_RESP_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_CMD_RESP_TYPE_POS)) /**< CMD_RESP_TYPE Mask */ 257 258 #define MXC_F_SDHC_REVA_CMD_CRC_CHK_EN_POS 3 /**< CMD_CRC_CHK_EN Position */ 259 #define MXC_F_SDHC_REVA_CMD_CRC_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CMD_CRC_CHK_EN_POS)) /**< CMD_CRC_CHK_EN Mask */ 260 261 #define MXC_F_SDHC_REVA_CMD_IDX_CHK_EN_POS 4 /**< CMD_IDX_CHK_EN Position */ 262 #define MXC_F_SDHC_REVA_CMD_IDX_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CMD_IDX_CHK_EN_POS)) /**< CMD_IDX_CHK_EN Mask */ 263 264 #define MXC_F_SDHC_REVA_CMD_DATA_PRES_SEL_POS 5 /**< CMD_DATA_PRES_SEL Position */ 265 #define MXC_F_SDHC_REVA_CMD_DATA_PRES_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CMD_DATA_PRES_SEL_POS)) /**< CMD_DATA_PRES_SEL Mask */ 266 267 #define MXC_F_SDHC_REVA_CMD_TYPE_POS 6 /**< CMD_TYPE Position */ 268 #define MXC_F_SDHC_REVA_CMD_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_CMD_TYPE_POS)) /**< CMD_TYPE Mask */ 269 270 #define MXC_F_SDHC_REVA_CMD_IDX_POS 8 /**< CMD_IDX Position */ 271 #define MXC_F_SDHC_REVA_CMD_IDX ((uint16_t)(0x3FUL << MXC_F_SDHC_REVA_CMD_IDX_POS)) /**< CMD_IDX Mask */ 272 273 /**@} end of group SDHC_REVA_CMD_Register */ 274 275 /** 276 * @ingroup sdhc_reva_registers 277 * @defgroup SDHC_REVA_RESP SDHC_REVA_RESP 278 * @brief Response 0 Register 0-15. 279 * @{ 280 */ 281 #define MXC_F_SDHC_REVA_RESP_CMD_RESP_POS 0 /**< RESP_CMD_RESP Position */ 282 #define MXC_F_SDHC_REVA_RESP_CMD_RESP ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_RESP_CMD_RESP_POS)) /**< RESP_CMD_RESP Mask */ 283 284 /**@} end of group SDHC_REVA_RESP_Register */ 285 286 /** 287 * @ingroup sdhc_reva_registers 288 * @defgroup SDHC_REVA_BUFFER SDHC_REVA_BUFFER 289 * @brief Buffer Data Port. 290 * @{ 291 */ 292 #define MXC_F_SDHC_REVA_BUFFER_DATA_POS 0 /**< BUFFER_DATA Position */ 293 #define MXC_F_SDHC_REVA_BUFFER_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_BUFFER_DATA_POS)) /**< BUFFER_DATA Mask */ 294 295 /**@} end of group SDHC_REVA_BUFFER_Register */ 296 297 /** 298 * @ingroup sdhc_reva_registers 299 * @defgroup SDHC_REVA_PRESENT SDHC_REVA_PRESENT 300 * @brief Present State. 301 * @{ 302 */ 303 #define MXC_F_SDHC_REVA_PRESENT_CMD_POS 0 /**< PRESENT_CMD Position */ 304 #define MXC_F_SDHC_REVA_PRESENT_CMD ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_CMD_POS)) /**< PRESENT_CMD Mask */ 305 306 #define MXC_F_SDHC_REVA_PRESENT_DAT_POS 1 /**< PRESENT_DAT Position */ 307 #define MXC_F_SDHC_REVA_PRESENT_DAT ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_DAT_POS)) /**< PRESENT_DAT Mask */ 308 309 #define MXC_F_SDHC_REVA_PRESENT_DAT_LINE_ACTIVE_POS 2 /**< PRESENT_DAT_LINE_ACTIVE Position */ 310 #define MXC_F_SDHC_REVA_PRESENT_DAT_LINE_ACTIVE ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_DAT_LINE_ACTIVE_POS)) /**< PRESENT_DAT_LINE_ACTIVE Mask */ 311 312 #define MXC_F_SDHC_REVA_PRESENT_RETUNING_POS 3 /**< PRESENT_RETUNING Position */ 313 #define MXC_F_SDHC_REVA_PRESENT_RETUNING ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_RETUNING_POS)) /**< PRESENT_RETUNING Mask */ 314 315 #define MXC_F_SDHC_REVA_PRESENT_WRITE_TRANSFER_POS 8 /**< PRESENT_WRITE_TRANSFER Position */ 316 #define MXC_F_SDHC_REVA_PRESENT_WRITE_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_WRITE_TRANSFER_POS)) /**< PRESENT_WRITE_TRANSFER Mask */ 317 318 #define MXC_F_SDHC_REVA_PRESENT_READ_TRANSFER_POS 9 /**< PRESENT_READ_TRANSFER Position */ 319 #define MXC_F_SDHC_REVA_PRESENT_READ_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_READ_TRANSFER_POS)) /**< PRESENT_READ_TRANSFER Mask */ 320 321 #define MXC_F_SDHC_REVA_PRESENT_BUFFER_WRITE_POS 10 /**< PRESENT_BUFFER_WRITE Position */ 322 #define MXC_F_SDHC_REVA_PRESENT_BUFFER_WRITE ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_BUFFER_WRITE_POS)) /**< PRESENT_BUFFER_WRITE Mask */ 323 324 #define MXC_F_SDHC_REVA_PRESENT_BUFFER_READ_POS 11 /**< PRESENT_BUFFER_READ Position */ 325 #define MXC_F_SDHC_REVA_PRESENT_BUFFER_READ ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_BUFFER_READ_POS)) /**< PRESENT_BUFFER_READ Mask */ 326 327 #define MXC_F_SDHC_REVA_PRESENT_CARD_INSERTED_POS 16 /**< PRESENT_CARD_INSERTED Position */ 328 #define MXC_F_SDHC_REVA_PRESENT_CARD_INSERTED ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_CARD_INSERTED_POS)) /**< PRESENT_CARD_INSERTED Mask */ 329 330 #define MXC_F_SDHC_REVA_PRESENT_CARD_STATE_POS 17 /**< PRESENT_CARD_STATE Position */ 331 #define MXC_F_SDHC_REVA_PRESENT_CARD_STATE ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_CARD_STATE_POS)) /**< PRESENT_CARD_STATE Mask */ 332 333 #define MXC_F_SDHC_REVA_PRESENT_CARD_DETECT_POS 18 /**< PRESENT_CARD_DETECT Position */ 334 #define MXC_F_SDHC_REVA_PRESENT_CARD_DETECT ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_CARD_DETECT_POS)) /**< PRESENT_CARD_DETECT Mask */ 335 336 #define MXC_F_SDHC_REVA_PRESENT_WP_POS 19 /**< PRESENT_WP Position */ 337 #define MXC_F_SDHC_REVA_PRESENT_WP ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_WP_POS)) /**< PRESENT_WP Mask */ 338 339 #define MXC_F_SDHC_REVA_PRESENT_DAT_SIGNAL_LEVEL_POS 20 /**< PRESENT_DAT_SIGNAL_LEVEL Position */ 340 #define MXC_F_SDHC_REVA_PRESENT_DAT_SIGNAL_LEVEL ((uint32_t)(0xFUL << MXC_F_SDHC_REVA_PRESENT_DAT_SIGNAL_LEVEL_POS)) /**< PRESENT_DAT_SIGNAL_LEVEL Mask */ 341 342 #define MXC_F_SDHC_REVA_PRESENT_CMD_SIGNAL_LEVEL_POS 24 /**< PRESENT_CMD_SIGNAL_LEVEL Position */ 343 #define MXC_F_SDHC_REVA_PRESENT_CMD_SIGNAL_LEVEL ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_PRESENT_CMD_SIGNAL_LEVEL_POS)) /**< PRESENT_CMD_SIGNAL_LEVEL Mask */ 344 345 /**@} end of group SDHC_REVA_PRESENT_Register */ 346 347 /** 348 * @ingroup sdhc_reva_registers 349 * @defgroup SDHC_REVA_HOST_CN_1 SDHC_REVA_HOST_CN_1 350 * @brief Host Control 1. 351 * @{ 352 */ 353 #define MXC_F_SDHC_REVA_HOST_CN_1_LED_CN_POS 0 /**< HOST_CN_1_LED_CN Position */ 354 #define MXC_F_SDHC_REVA_HOST_CN_1_LED_CN ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_LED_CN_POS)) /**< HOST_CN_1_LED_CN Mask */ 355 356 #define MXC_F_SDHC_REVA_HOST_CN_1_DATA_TRANSFER_WIDTH_POS 1 /**< HOST_CN_1_DATA_TRANSFER_WIDTH Position */ 357 #define MXC_F_SDHC_REVA_HOST_CN_1_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_DATA_TRANSFER_WIDTH Mask */ 358 359 #define MXC_F_SDHC_REVA_HOST_CN_1_HS_EN_POS 2 /**< HOST_CN_1_HS_EN Position */ 360 #define MXC_F_SDHC_REVA_HOST_CN_1_HS_EN ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_HS_EN_POS)) /**< HOST_CN_1_HS_EN Mask */ 361 362 #define MXC_F_SDHC_REVA_HOST_CN_1_DMA_SELECT_POS 3 /**< HOST_CN_1_DMA_SELECT Position */ 363 #define MXC_F_SDHC_REVA_HOST_CN_1_DMA_SELECT ((uint8_t)(0x3UL << MXC_F_SDHC_REVA_HOST_CN_1_DMA_SELECT_POS)) /**< HOST_CN_1_DMA_SELECT Mask */ 364 365 #define MXC_F_SDHC_REVA_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS 5 /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Position */ 366 #define MXC_F_SDHC_REVA_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Mask */ 367 368 #define MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_TEST_POS 6 /**< HOST_CN_1_CARD_DETECT_TEST Position */ 369 #define MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_TEST ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_TEST_POS)) /**< HOST_CN_1_CARD_DETECT_TEST Mask */ 370 371 #define MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_SIGNAL_POS 7 /**< HOST_CN_1_CARD_DETECT_SIGNAL Position */ 372 #define MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_SIGNAL ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_1_CARD_DETECT_SIGNAL_POS)) /**< HOST_CN_1_CARD_DETECT_SIGNAL Mask */ 373 374 /**@} end of group SDHC_REVA_HOST_CN_1_Register */ 375 376 /** 377 * @ingroup sdhc_reva_registers 378 * @defgroup SDHC_REVA_PWR SDHC_REVA_PWR 379 * @brief Power Control. 380 * @{ 381 */ 382 #define MXC_F_SDHC_REVA_PWR_BUS_POWER_POS 0 /**< PWR_BUS_POWER Position */ 383 #define MXC_F_SDHC_REVA_PWR_BUS_POWER ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_PWR_BUS_POWER_POS)) /**< PWR_BUS_POWER Mask */ 384 385 #define MXC_F_SDHC_REVA_PWR_BUS_VOLT_SEL_POS 1 /**< PWR_BUS_VOLT_SEL Position */ 386 #define MXC_F_SDHC_REVA_PWR_BUS_VOLT_SEL ((uint8_t)(0x7UL << MXC_F_SDHC_REVA_PWR_BUS_VOLT_SEL_POS)) /**< PWR_BUS_VOLT_SEL Mask */ 387 388 /**@} end of group SDHC_REVA_PWR_Register */ 389 390 /** 391 * @ingroup sdhc_reva_registers 392 * @defgroup SDHC_REVA_BLK_GAP SDHC_REVA_BLK_GAP 393 * @brief Block Gap Control. 394 * @{ 395 */ 396 #define MXC_F_SDHC_REVA_BLK_GAP_STOP_POS 0 /**< BLK_GAP_STOP Position */ 397 #define MXC_F_SDHC_REVA_BLK_GAP_STOP ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_BLK_GAP_STOP_POS)) /**< BLK_GAP_STOP Mask */ 398 399 #define MXC_F_SDHC_REVA_BLK_GAP_CONT_POS 1 /**< BLK_GAP_CONT Position */ 400 #define MXC_F_SDHC_REVA_BLK_GAP_CONT ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_BLK_GAP_CONT_POS)) /**< BLK_GAP_CONT Mask */ 401 402 #define MXC_F_SDHC_REVA_BLK_GAP_READ_WAIT_POS 2 /**< BLK_GAP_READ_WAIT Position */ 403 #define MXC_F_SDHC_REVA_BLK_GAP_READ_WAIT ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_BLK_GAP_READ_WAIT_POS)) /**< BLK_GAP_READ_WAIT Mask */ 404 405 #define MXC_F_SDHC_REVA_BLK_GAP_INTR_POS 3 /**< BLK_GAP_INTR Position */ 406 #define MXC_F_SDHC_REVA_BLK_GAP_INTR ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_BLK_GAP_INTR_POS)) /**< BLK_GAP_INTR Mask */ 407 408 /**@} end of group SDHC_REVA_BLK_GAP_Register */ 409 410 /** 411 * @ingroup sdhc_reva_registers 412 * @defgroup SDHC_REVA_WAKEUP SDHC_REVA_WAKEUP 413 * @brief Wakeup Control. 414 * @{ 415 */ 416 #define MXC_F_SDHC_REVA_WAKEUP_CARD_INT_POS 0 /**< WAKEUP_CARD_INT Position */ 417 #define MXC_F_SDHC_REVA_WAKEUP_CARD_INT ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_WAKEUP_CARD_INT_POS)) /**< WAKEUP_CARD_INT Mask */ 418 419 #define MXC_F_SDHC_REVA_WAKEUP_CARD_INS_POS 1 /**< WAKEUP_CARD_INS Position */ 420 #define MXC_F_SDHC_REVA_WAKEUP_CARD_INS ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_WAKEUP_CARD_INS_POS)) /**< WAKEUP_CARD_INS Mask */ 421 422 #define MXC_F_SDHC_REVA_WAKEUP_CARD_REM_POS 2 /**< WAKEUP_CARD_REM Position */ 423 #define MXC_F_SDHC_REVA_WAKEUP_CARD_REM ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_WAKEUP_CARD_REM_POS)) /**< WAKEUP_CARD_REM Mask */ 424 425 /**@} end of group SDHC_REVA_WAKEUP_Register */ 426 427 /** 428 * @ingroup sdhc_reva_registers 429 * @defgroup SDHC_REVA_CLK_CN SDHC_REVA_CLK_CN 430 * @brief Clock Control. 431 * @{ 432 */ 433 #define MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_EN_POS 0 /**< CLK_CN_INTERNAL_CLK_EN Position */ 434 #define MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_EN_POS)) /**< CLK_CN_INTERNAL_CLK_EN Mask */ 435 436 #define MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_STABLE_POS 1 /**< CLK_CN_INTERNAL_CLK_STABLE Position */ 437 #define MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_STABLE ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CLK_CN_INTERNAL_CLK_STABLE_POS)) /**< CLK_CN_INTERNAL_CLK_STABLE Mask */ 438 439 #define MXC_F_SDHC_REVA_CLK_CN_SD_CLK_EN_POS 2 /**< CLK_CN_SD_CLK_EN Position */ 440 #define MXC_F_SDHC_REVA_CLK_CN_SD_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CLK_CN_SD_CLK_EN_POS)) /**< CLK_CN_SD_CLK_EN Mask */ 441 442 #define MXC_F_SDHC_REVA_CLK_CN_CLK_GEN_SEL_POS 5 /**< CLK_CN_CLK_GEN_SEL Position */ 443 #define MXC_F_SDHC_REVA_CLK_CN_CLK_GEN_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_CLK_CN_CLK_GEN_SEL_POS)) /**< CLK_CN_CLK_GEN_SEL Mask */ 444 445 #define MXC_F_SDHC_REVA_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS 6 /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Position */ 446 #define MXC_F_SDHC_REVA_CLK_CN_UPPER_SDCLK_FREQ_SEL ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Mask */ 447 448 #define MXC_F_SDHC_REVA_CLK_CN_SDCLK_FREQ_SEL_POS 8 /**< CLK_CN_SDCLK_FREQ_SEL Position */ 449 #define MXC_F_SDHC_REVA_CLK_CN_SDCLK_FREQ_SEL ((uint16_t)(0xFFUL << MXC_F_SDHC_REVA_CLK_CN_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_SDCLK_FREQ_SEL Mask */ 450 451 /**@} end of group SDHC_REVA_CLK_CN_Register */ 452 453 /** 454 * @ingroup sdhc_reva_registers 455 * @defgroup SDHC_REVA_TO SDHC_REVA_TO 456 * @brief Timeout Control. 457 * @{ 458 */ 459 #define MXC_F_SDHC_REVA_TO_DATA_COUNT_VALUE_POS 0 /**< TO_DATA_COUNT_VALUE Position */ 460 #define MXC_F_SDHC_REVA_TO_DATA_COUNT_VALUE ((uint8_t)(0x7UL << MXC_F_SDHC_REVA_TO_DATA_COUNT_VALUE_POS)) /**< TO_DATA_COUNT_VALUE Mask */ 461 462 /**@} end of group SDHC_REVA_TO_Register */ 463 464 /** 465 * @ingroup sdhc_reva_registers 466 * @defgroup SDHC_REVA_SW_RESET SDHC_REVA_SW_RESET 467 * @brief Software Reset. 468 * @{ 469 */ 470 #define MXC_F_SDHC_REVA_SW_RESET_RESET_ALL_POS 0 /**< SW_RESET_RESET_ALL Position */ 471 #define MXC_F_SDHC_REVA_SW_RESET_RESET_ALL ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_SW_RESET_RESET_ALL_POS)) /**< SW_RESET_RESET_ALL Mask */ 472 473 #define MXC_F_SDHC_REVA_SW_RESET_RESET_CMD_POS 1 /**< SW_RESET_RESET_CMD Position */ 474 #define MXC_F_SDHC_REVA_SW_RESET_RESET_CMD ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_SW_RESET_RESET_CMD_POS)) /**< SW_RESET_RESET_CMD Mask */ 475 476 #define MXC_F_SDHC_REVA_SW_RESET_RESET_DAT_POS 2 /**< SW_RESET_RESET_DAT Position */ 477 #define MXC_F_SDHC_REVA_SW_RESET_RESET_DAT ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_SW_RESET_RESET_DAT_POS)) /**< SW_RESET_RESET_DAT Mask */ 478 479 /**@} end of group SDHC_REVA_SW_RESET_Register */ 480 481 /** 482 * @ingroup sdhc_reva_registers 483 * @defgroup SDHC_REVA_INT_STAT SDHC_REVA_INT_STAT 484 * @brief Normal Interrupt Status. 485 * @{ 486 */ 487 #define MXC_F_SDHC_REVA_INT_STAT_CMD_COMP_POS 0 /**< INT_STAT_CMD_COMP Position */ 488 #define MXC_F_SDHC_REVA_INT_STAT_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_CMD_COMP_POS)) /**< INT_STAT_CMD_COMP Mask */ 489 490 #define MXC_F_SDHC_REVA_INT_STAT_TRANS_COMP_POS 1 /**< INT_STAT_TRANS_COMP Position */ 491 #define MXC_F_SDHC_REVA_INT_STAT_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_TRANS_COMP_POS)) /**< INT_STAT_TRANS_COMP Mask */ 492 493 #define MXC_F_SDHC_REVA_INT_STAT_BLK_GAP_EVENT_POS 2 /**< INT_STAT_BLK_GAP_EVENT Position */ 494 #define MXC_F_SDHC_REVA_INT_STAT_BLK_GAP_EVENT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_BLK_GAP_EVENT_POS)) /**< INT_STAT_BLK_GAP_EVENT Mask */ 495 496 #define MXC_F_SDHC_REVA_INT_STAT_DMA_POS 3 /**< INT_STAT_DMA Position */ 497 #define MXC_F_SDHC_REVA_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_DMA_POS)) /**< INT_STAT_DMA Mask */ 498 499 #define MXC_F_SDHC_REVA_INT_STAT_BUFF_WR_READY_POS 4 /**< INT_STAT_BUFF_WR_READY Position */ 500 #define MXC_F_SDHC_REVA_INT_STAT_BUFF_WR_READY ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_BUFF_WR_READY_POS)) /**< INT_STAT_BUFF_WR_READY Mask */ 501 502 #define MXC_F_SDHC_REVA_INT_STAT_BUFF_RD_READY_POS 5 /**< INT_STAT_BUFF_RD_READY Position */ 503 #define MXC_F_SDHC_REVA_INT_STAT_BUFF_RD_READY ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_BUFF_RD_READY_POS)) /**< INT_STAT_BUFF_RD_READY Mask */ 504 505 #define MXC_F_SDHC_REVA_INT_STAT_CARD_INSERTION_POS 6 /**< INT_STAT_CARD_INSERTION Position */ 506 #define MXC_F_SDHC_REVA_INT_STAT_CARD_INSERTION ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_CARD_INSERTION_POS)) /**< INT_STAT_CARD_INSERTION Mask */ 507 508 #define MXC_F_SDHC_REVA_INT_STAT_CARD_REMOVAL_POS 7 /**< INT_STAT_CARD_REMOVAL Position */ 509 #define MXC_F_SDHC_REVA_INT_STAT_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_CARD_REMOVAL_POS)) /**< INT_STAT_CARD_REMOVAL Mask */ 510 511 #define MXC_F_SDHC_REVA_INT_STAT_CARD_INTR_POS 8 /**< INT_STAT_CARD_INTR Position */ 512 #define MXC_F_SDHC_REVA_INT_STAT_CARD_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_CARD_INTR_POS)) /**< INT_STAT_CARD_INTR Mask */ 513 514 #define MXC_F_SDHC_REVA_INT_STAT_RETUNING_POS 12 /**< INT_STAT_RETUNING Position */ 515 #define MXC_F_SDHC_REVA_INT_STAT_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_RETUNING_POS)) /**< INT_STAT_RETUNING Mask */ 516 517 #define MXC_F_SDHC_REVA_INT_STAT_ERR_INTR_POS 15 /**< INT_STAT_ERR_INTR Position */ 518 #define MXC_F_SDHC_REVA_INT_STAT_ERR_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_STAT_ERR_INTR_POS)) /**< INT_STAT_ERR_INTR Mask */ 519 520 /**@} end of group SDHC_REVA_INT_STAT_Register */ 521 522 /** 523 * @ingroup sdhc_reva_registers 524 * @defgroup SDHC_REVA_ER_INT_STAT SDHC_REVA_ER_INT_STAT 525 * @brief Error Interrupt Status. 526 * @{ 527 */ 528 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_TO_POS 0 /**< ER_INT_STAT_CMD_TO Position */ 529 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_CMD_TO_POS)) /**< ER_INT_STAT_CMD_TO Mask */ 530 531 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_CRC_POS 1 /**< ER_INT_STAT_CMD_CRC Position */ 532 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_CMD_CRC_POS)) /**< ER_INT_STAT_CMD_CRC Mask */ 533 534 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_END_BIT_POS 2 /**< ER_INT_STAT_CMD_END_BIT Position */ 535 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_CMD_END_BIT_POS)) /**< ER_INT_STAT_CMD_END_BIT Mask */ 536 537 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_IDX_POS 3 /**< ER_INT_STAT_CMD_IDX Position */ 538 #define MXC_F_SDHC_REVA_ER_INT_STAT_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_CMD_IDX_POS)) /**< ER_INT_STAT_CMD_IDX Mask */ 539 540 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_TO_POS 4 /**< ER_INT_STAT_DATA_TO Position */ 541 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_DATA_TO_POS)) /**< ER_INT_STAT_DATA_TO Mask */ 542 543 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_CRC_POS 5 /**< ER_INT_STAT_DATA_CRC Position */ 544 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_DATA_CRC_POS)) /**< ER_INT_STAT_DATA_CRC Mask */ 545 546 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_END_BIT_POS 6 /**< ER_INT_STAT_DATA_END_BIT Position */ 547 #define MXC_F_SDHC_REVA_ER_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_DATA_END_BIT_POS)) /**< ER_INT_STAT_DATA_END_BIT Mask */ 548 549 #define MXC_F_SDHC_REVA_ER_INT_STAT_CURRENT_LIMIT_POS 7 /**< ER_INT_STAT_CURRENT_LIMIT Position */ 550 #define MXC_F_SDHC_REVA_ER_INT_STAT_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_CURRENT_LIMIT_POS)) /**< ER_INT_STAT_CURRENT_LIMIT Mask */ 551 552 #define MXC_F_SDHC_REVA_ER_INT_STAT_AUTO_CMD_12_POS 8 /**< ER_INT_STAT_AUTO_CMD_12 Position */ 553 #define MXC_F_SDHC_REVA_ER_INT_STAT_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_AUTO_CMD_12_POS)) /**< ER_INT_STAT_AUTO_CMD_12 Mask */ 554 555 #define MXC_F_SDHC_REVA_ER_INT_STAT_ADMA_POS 9 /**< ER_INT_STAT_ADMA Position */ 556 #define MXC_F_SDHC_REVA_ER_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_ADMA_POS)) /**< ER_INT_STAT_ADMA Mask */ 557 558 #define MXC_F_SDHC_REVA_ER_INT_STAT_DMA_POS 12 /**< ER_INT_STAT_DMA Position */ 559 #define MXC_F_SDHC_REVA_ER_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_STAT_DMA_POS)) /**< ER_INT_STAT_DMA Mask */ 560 561 /**@} end of group SDHC_REVA_ER_INT_STAT_Register */ 562 563 /** 564 * @ingroup sdhc_reva_registers 565 * @defgroup SDHC_REVA_INT_EN SDHC_REVA_INT_EN 566 * @brief Normal Interrupt Status Enable. 567 * @{ 568 */ 569 #define MXC_F_SDHC_REVA_INT_EN_CMD_COMP_POS 0 /**< INT_EN_CMD_COMP Position */ 570 #define MXC_F_SDHC_REVA_INT_EN_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_CMD_COMP_POS)) /**< INT_EN_CMD_COMP Mask */ 571 572 #define MXC_F_SDHC_REVA_INT_EN_TRANS_COMP_POS 1 /**< INT_EN_TRANS_COMP Position */ 573 #define MXC_F_SDHC_REVA_INT_EN_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_TRANS_COMP_POS)) /**< INT_EN_TRANS_COMP Mask */ 574 575 #define MXC_F_SDHC_REVA_INT_EN_BLK_GAP_POS 2 /**< INT_EN_BLK_GAP Position */ 576 #define MXC_F_SDHC_REVA_INT_EN_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_BLK_GAP_POS)) /**< INT_EN_BLK_GAP Mask */ 577 578 #define MXC_F_SDHC_REVA_INT_EN_DMA_POS 3 /**< INT_EN_DMA Position */ 579 #define MXC_F_SDHC_REVA_INT_EN_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_DMA_POS)) /**< INT_EN_DMA Mask */ 580 581 #define MXC_F_SDHC_REVA_INT_EN_BUFFER_WR_POS 4 /**< INT_EN_BUFFER_WR Position */ 582 #define MXC_F_SDHC_REVA_INT_EN_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_BUFFER_WR_POS)) /**< INT_EN_BUFFER_WR Mask */ 583 584 #define MXC_F_SDHC_REVA_INT_EN_BUFFER_RD_POS 5 /**< INT_EN_BUFFER_RD Position */ 585 #define MXC_F_SDHC_REVA_INT_EN_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_BUFFER_RD_POS)) /**< INT_EN_BUFFER_RD Mask */ 586 587 #define MXC_F_SDHC_REVA_INT_EN_CARD_INSERT_POS 6 /**< INT_EN_CARD_INSERT Position */ 588 #define MXC_F_SDHC_REVA_INT_EN_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_CARD_INSERT_POS)) /**< INT_EN_CARD_INSERT Mask */ 589 590 #define MXC_F_SDHC_REVA_INT_EN_CARD_REMOVAL_POS 7 /**< INT_EN_CARD_REMOVAL Position */ 591 #define MXC_F_SDHC_REVA_INT_EN_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_CARD_REMOVAL_POS)) /**< INT_EN_CARD_REMOVAL Mask */ 592 593 #define MXC_F_SDHC_REVA_INT_EN_CARD_INT_POS 8 /**< INT_EN_CARD_INT Position */ 594 #define MXC_F_SDHC_REVA_INT_EN_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_CARD_INT_POS)) /**< INT_EN_CARD_INT Mask */ 595 596 #define MXC_F_SDHC_REVA_INT_EN_RETUNING_POS 12 /**< INT_EN_RETUNING Position */ 597 #define MXC_F_SDHC_REVA_INT_EN_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_EN_RETUNING_POS)) /**< INT_EN_RETUNING Mask */ 598 599 /**@} end of group SDHC_REVA_INT_EN_Register */ 600 601 /** 602 * @ingroup sdhc_reva_registers 603 * @defgroup SDHC_REVA_ER_INT_EN SDHC_REVA_ER_INT_EN 604 * @brief Error Interrupt Status Enable. 605 * @{ 606 */ 607 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_TO_POS 0 /**< ER_INT_EN_CMD_TO Position */ 608 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_CMD_TO_POS)) /**< ER_INT_EN_CMD_TO Mask */ 609 610 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_CRC_POS 1 /**< ER_INT_EN_CMD_CRC Position */ 611 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_CMD_CRC_POS)) /**< ER_INT_EN_CMD_CRC Mask */ 612 613 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_END_BIT_POS 2 /**< ER_INT_EN_CMD_END_BIT Position */ 614 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_CMD_END_BIT_POS)) /**< ER_INT_EN_CMD_END_BIT Mask */ 615 616 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_IDX_POS 3 /**< ER_INT_EN_CMD_IDX Position */ 617 #define MXC_F_SDHC_REVA_ER_INT_EN_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_CMD_IDX_POS)) /**< ER_INT_EN_CMD_IDX Mask */ 618 619 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_TO_POS 4 /**< ER_INT_EN_DATA_TO Position */ 620 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_DATA_TO_POS)) /**< ER_INT_EN_DATA_TO Mask */ 621 622 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_CRC_POS 5 /**< ER_INT_EN_DATA_CRC Position */ 623 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_DATA_CRC_POS)) /**< ER_INT_EN_DATA_CRC Mask */ 624 625 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_END_BIT_POS 6 /**< ER_INT_EN_DATA_END_BIT Position */ 626 #define MXC_F_SDHC_REVA_ER_INT_EN_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_DATA_END_BIT_POS)) /**< ER_INT_EN_DATA_END_BIT Mask */ 627 628 #define MXC_F_SDHC_REVA_ER_INT_EN_AUTO_CMD_POS 8 /**< ER_INT_EN_AUTO_CMD Position */ 629 #define MXC_F_SDHC_REVA_ER_INT_EN_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_AUTO_CMD_POS)) /**< ER_INT_EN_AUTO_CMD Mask */ 630 631 #define MXC_F_SDHC_REVA_ER_INT_EN_ADMA_POS 9 /**< ER_INT_EN_ADMA Position */ 632 #define MXC_F_SDHC_REVA_ER_INT_EN_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_ADMA_POS)) /**< ER_INT_EN_ADMA Mask */ 633 634 #define MXC_F_SDHC_REVA_ER_INT_EN_TUNING_POS 10 /**< ER_INT_EN_TUNING Position */ 635 #define MXC_F_SDHC_REVA_ER_INT_EN_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_TUNING_POS)) /**< ER_INT_EN_TUNING Mask */ 636 637 #define MXC_F_SDHC_REVA_ER_INT_EN_VENDOR_POS 12 /**< ER_INT_EN_VENDOR Position */ 638 #define MXC_F_SDHC_REVA_ER_INT_EN_VENDOR ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_EN_VENDOR_POS)) /**< ER_INT_EN_VENDOR Mask */ 639 640 /**@} end of group SDHC_REVA_ER_INT_EN_Register */ 641 642 /** 643 * @ingroup sdhc_reva_registers 644 * @defgroup SDHC_REVA_INT_SIGNAL SDHC_REVA_INT_SIGNAL 645 * @brief Normal Interrupt Signal Enable. 646 * @{ 647 */ 648 #define MXC_F_SDHC_REVA_INT_SIGNAL_CMD_COMP_POS 0 /**< INT_SIGNAL_CMD_COMP Position */ 649 #define MXC_F_SDHC_REVA_INT_SIGNAL_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_CMD_COMP_POS)) /**< INT_SIGNAL_CMD_COMP Mask */ 650 651 #define MXC_F_SDHC_REVA_INT_SIGNAL_TRANS_COMP_POS 1 /**< INT_SIGNAL_TRANS_COMP Position */ 652 #define MXC_F_SDHC_REVA_INT_SIGNAL_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_TRANS_COMP_POS)) /**< INT_SIGNAL_TRANS_COMP Mask */ 653 654 #define MXC_F_SDHC_REVA_INT_SIGNAL_BLK_GAP_POS 2 /**< INT_SIGNAL_BLK_GAP Position */ 655 #define MXC_F_SDHC_REVA_INT_SIGNAL_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_BLK_GAP_POS)) /**< INT_SIGNAL_BLK_GAP Mask */ 656 657 #define MXC_F_SDHC_REVA_INT_SIGNAL_DMA_POS 3 /**< INT_SIGNAL_DMA Position */ 658 #define MXC_F_SDHC_REVA_INT_SIGNAL_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_DMA_POS)) /**< INT_SIGNAL_DMA Mask */ 659 660 #define MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_WR_POS 4 /**< INT_SIGNAL_BUFFER_WR Position */ 661 #define MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_WR_POS)) /**< INT_SIGNAL_BUFFER_WR Mask */ 662 663 #define MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_RD_POS 5 /**< INT_SIGNAL_BUFFER_RD Position */ 664 #define MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_BUFFER_RD_POS)) /**< INT_SIGNAL_BUFFER_RD Mask */ 665 666 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INSERT_POS 6 /**< INT_SIGNAL_CARD_INSERT Position */ 667 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INSERT_POS)) /**< INT_SIGNAL_CARD_INSERT Mask */ 668 669 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_REMOVAL_POS 7 /**< INT_SIGNAL_CARD_REMOVAL Position */ 670 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_CARD_REMOVAL_POS)) /**< INT_SIGNAL_CARD_REMOVAL Mask */ 671 672 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INT_POS 8 /**< INT_SIGNAL_CARD_INT Position */ 673 #define MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_CARD_INT_POS)) /**< INT_SIGNAL_CARD_INT Mask */ 674 675 #define MXC_F_SDHC_REVA_INT_SIGNAL_RETUNING_POS 12 /**< INT_SIGNAL_RETUNING Position */ 676 #define MXC_F_SDHC_REVA_INT_SIGNAL_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_INT_SIGNAL_RETUNING_POS)) /**< INT_SIGNAL_RETUNING Mask */ 677 678 /**@} end of group SDHC_REVA_INT_SIGNAL_Register */ 679 680 /** 681 * @ingroup sdhc_reva_registers 682 * @defgroup SDHC_REVA_ER_INT_SIGNAL SDHC_REVA_ER_INT_SIGNAL 683 * @brief Error Interrupt Signal Enable. 684 * @{ 685 */ 686 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_TO_POS 0 /**< ER_INT_SIGNAL_CMD_TO Position */ 687 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_TO_POS)) /**< ER_INT_SIGNAL_CMD_TO Mask */ 688 689 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_CRC_POS 1 /**< ER_INT_SIGNAL_CMD_CRC Position */ 690 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_CRC_POS)) /**< ER_INT_SIGNAL_CMD_CRC Mask */ 691 692 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_END_BIT_POS 2 /**< ER_INT_SIGNAL_CMD_END_BIT Position */ 693 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_END_BIT_POS)) /**< ER_INT_SIGNAL_CMD_END_BIT Mask */ 694 695 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_IDX_POS 3 /**< ER_INT_SIGNAL_CMD_IDX Position */ 696 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_CMD_IDX_POS)) /**< ER_INT_SIGNAL_CMD_IDX Mask */ 697 698 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_TO_POS 4 /**< ER_INT_SIGNAL_DATA_TO Position */ 699 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_TO_POS)) /**< ER_INT_SIGNAL_DATA_TO Mask */ 700 701 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_CRC_POS 5 /**< ER_INT_SIGNAL_DATA_CRC Position */ 702 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_CRC_POS)) /**< ER_INT_SIGNAL_DATA_CRC Mask */ 703 704 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_END_BIT_POS 6 /**< ER_INT_SIGNAL_DATA_END_BIT Position */ 705 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_DATA_END_BIT_POS)) /**< ER_INT_SIGNAL_DATA_END_BIT Mask */ 706 707 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CURR_LIM_POS 7 /**< ER_INT_SIGNAL_CURR_LIM Position */ 708 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_CURR_LIM ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_CURR_LIM_POS)) /**< ER_INT_SIGNAL_CURR_LIM Mask */ 709 710 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_AUTO_CMD_POS 8 /**< ER_INT_SIGNAL_AUTO_CMD Position */ 711 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_AUTO_CMD_POS)) /**< ER_INT_SIGNAL_AUTO_CMD Mask */ 712 713 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_ADMA_POS 9 /**< ER_INT_SIGNAL_ADMA Position */ 714 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_ADMA_POS)) /**< ER_INT_SIGNAL_ADMA Mask */ 715 716 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_TUNING_POS 10 /**< ER_INT_SIGNAL_TUNING Position */ 717 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_TUNING_POS)) /**< ER_INT_SIGNAL_TUNING Mask */ 718 719 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_TAR_RESP_POS 12 /**< ER_INT_SIGNAL_TAR_RESP Position */ 720 #define MXC_F_SDHC_REVA_ER_INT_SIGNAL_TAR_RESP ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_ER_INT_SIGNAL_TAR_RESP_POS)) /**< ER_INT_SIGNAL_TAR_RESP Mask */ 721 722 /**@} end of group SDHC_REVA_ER_INT_SIGNAL_Register */ 723 724 /** 725 * @ingroup sdhc_reva_registers 726 * @defgroup SDHC_REVA_AUTO_CMD_ER SDHC_REVA_AUTO_CMD_ER 727 * @brief Auto CMD Error Status. 728 * @{ 729 */ 730 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_EXCUTED_POS 0 /**< AUTO_CMD_ER_NOT_EXCUTED Position */ 731 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_EXCUTED ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_EXCUTED_POS)) /**< AUTO_CMD_ER_NOT_EXCUTED Mask */ 732 733 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_TO_POS 1 /**< AUTO_CMD_ER_TO Position */ 734 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_TO_POS)) /**< AUTO_CMD_ER_TO Mask */ 735 736 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_CRC_POS 2 /**< AUTO_CMD_ER_CRC Position */ 737 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_CRC_POS)) /**< AUTO_CMD_ER_CRC Mask */ 738 739 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_END_BIT_POS 3 /**< AUTO_CMD_ER_END_BIT Position */ 740 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_END_BIT_POS)) /**< AUTO_CMD_ER_END_BIT Mask */ 741 742 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_INDEX_POS 4 /**< AUTO_CMD_ER_INDEX Position */ 743 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_INDEX_POS)) /**< AUTO_CMD_ER_INDEX Mask */ 744 745 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_ISSUED_POS 7 /**< AUTO_CMD_ER_NOT_ISSUED Position */ 746 #define MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_AUTO_CMD_ER_NOT_ISSUED_POS)) /**< AUTO_CMD_ER_NOT_ISSUED Mask */ 747 748 /**@} end of group SDHC_REVA_AUTO_CMD_ER_Register */ 749 750 /** 751 * @ingroup sdhc_reva_registers 752 * @defgroup SDHC_REVA_HOST_CN_2 SDHC_REVA_HOST_CN_2 753 * @brief Host Control 2. 754 * @{ 755 */ 756 #define MXC_F_SDHC_REVA_HOST_CN_2_UHS_POS 0 /**< HOST_CN_2_UHS Position */ 757 #define MXC_F_SDHC_REVA_HOST_CN_2_UHS ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_HOST_CN_2_UHS_POS)) /**< HOST_CN_2_UHS Mask */ 758 759 #define MXC_F_SDHC_REVA_HOST_CN_2_SIGNAL_V1_8_POS 3 /**< HOST_CN_2_SIGNAL_V1_8 Position */ 760 #define MXC_F_SDHC_REVA_HOST_CN_2_SIGNAL_V1_8 ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_2_SIGNAL_V1_8_POS)) /**< HOST_CN_2_SIGNAL_V1_8 Mask */ 761 762 #define MXC_F_SDHC_REVA_HOST_CN_2_DRIVER_STRENGTH_POS 4 /**< HOST_CN_2_DRIVER_STRENGTH Position */ 763 #define MXC_F_SDHC_REVA_HOST_CN_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_HOST_CN_2_DRIVER_STRENGTH_POS)) /**< HOST_CN_2_DRIVER_STRENGTH Mask */ 764 765 #define MXC_F_SDHC_REVA_HOST_CN_2_EXCUTE_POS 6 /**< HOST_CN_2_EXCUTE Position */ 766 #define MXC_F_SDHC_REVA_HOST_CN_2_EXCUTE ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_2_EXCUTE_POS)) /**< HOST_CN_2_EXCUTE Mask */ 767 768 #define MXC_F_SDHC_REVA_HOST_CN_2_SAMPLING_CLK_POS 7 /**< HOST_CN_2_SAMPLING_CLK Position */ 769 #define MXC_F_SDHC_REVA_HOST_CN_2_SAMPLING_CLK ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_2_SAMPLING_CLK_POS)) /**< HOST_CN_2_SAMPLING_CLK Mask */ 770 771 #define MXC_F_SDHC_REVA_HOST_CN_2_ASYNCH_INT_POS 14 /**< HOST_CN_2_ASYNCH_INT Position */ 772 #define MXC_F_SDHC_REVA_HOST_CN_2_ASYNCH_INT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_2_ASYNCH_INT_POS)) /**< HOST_CN_2_ASYNCH_INT Mask */ 773 774 #define MXC_F_SDHC_REVA_HOST_CN_2_PRESET_VAL_EN_POS 15 /**< HOST_CN_2_PRESET_VAL_EN Position */ 775 #define MXC_F_SDHC_REVA_HOST_CN_2_PRESET_VAL_EN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_HOST_CN_2_PRESET_VAL_EN_POS)) /**< HOST_CN_2_PRESET_VAL_EN Mask */ 776 777 /**@} end of group SDHC_REVA_HOST_CN_2_Register */ 778 779 /** 780 * @ingroup sdhc_reva_registers 781 * @defgroup SDHC_REVA_CFG_0 SDHC_REVA_CFG_0 782 * @brief Capabilities 0-31. 783 * @{ 784 */ 785 #define MXC_F_SDHC_REVA_CFG_0_TO_CLK_FREQ_POS 0 /**< CFG_0_TO_CLK_FREQ Position */ 786 #define MXC_F_SDHC_REVA_CFG_0_TO_CLK_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_REVA_CFG_0_TO_CLK_FREQ_POS)) /**< CFG_0_TO_CLK_FREQ Mask */ 787 788 #define MXC_F_SDHC_REVA_CFG_0_TO_CLK_UNIT_POS 7 /**< CFG_0_TO_CLK_UNIT Position */ 789 #define MXC_F_SDHC_REVA_CFG_0_TO_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_TO_CLK_UNIT_POS)) /**< CFG_0_TO_CLK_UNIT Mask */ 790 791 #define MXC_F_SDHC_REVA_CFG_0_CLK_FREQ_POS 8 /**< CFG_0_CLK_FREQ Position */ 792 #define MXC_F_SDHC_REVA_CFG_0_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_REVA_CFG_0_CLK_FREQ_POS)) /**< CFG_0_CLK_FREQ Mask */ 793 794 #define MXC_F_SDHC_REVA_CFG_0_MAX_BLK_LEN_POS 16 /**< CFG_0_MAX_BLK_LEN Position */ 795 #define MXC_F_SDHC_REVA_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_REVA_CFG_0_MAX_BLK_LEN_POS)) /**< CFG_0_MAX_BLK_LEN Mask */ 796 797 #define MXC_F_SDHC_REVA_CFG_0_BIT_8_POS 18 /**< CFG_0_BIT_8 Position */ 798 #define MXC_F_SDHC_REVA_CFG_0_BIT_8 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_BIT_8_POS)) /**< CFG_0_BIT_8 Mask */ 799 800 #define MXC_F_SDHC_REVA_CFG_0_ADMA2_POS 19 /**< CFG_0_ADMA2 Position */ 801 #define MXC_F_SDHC_REVA_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_ADMA2_POS)) /**< CFG_0_ADMA2 Mask */ 802 803 #define MXC_F_SDHC_REVA_CFG_0_HS_POS 21 /**< CFG_0_HS Position */ 804 #define MXC_F_SDHC_REVA_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_HS_POS)) /**< CFG_0_HS Mask */ 805 806 #define MXC_F_SDHC_REVA_CFG_0_SDMA_POS 22 /**< CFG_0_SDMA Position */ 807 #define MXC_F_SDHC_REVA_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_SDMA_POS)) /**< CFG_0_SDMA Mask */ 808 809 #define MXC_F_SDHC_REVA_CFG_0_SUSPEND_POS 23 /**< CFG_0_SUSPEND Position */ 810 #define MXC_F_SDHC_REVA_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_SUSPEND_POS)) /**< CFG_0_SUSPEND Mask */ 811 812 #define MXC_F_SDHC_REVA_CFG_0_V3_3_POS 24 /**< CFG_0_V3_3 Position */ 813 #define MXC_F_SDHC_REVA_CFG_0_V3_3 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_V3_3_POS)) /**< CFG_0_V3_3 Mask */ 814 815 #define MXC_F_SDHC_REVA_CFG_0_V3_0_POS 25 /**< CFG_0_V3_0 Position */ 816 #define MXC_F_SDHC_REVA_CFG_0_V3_0 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_V3_0_POS)) /**< CFG_0_V3_0 Mask */ 817 818 #define MXC_F_SDHC_REVA_CFG_0_V1_8_POS 26 /**< CFG_0_V1_8 Position */ 819 #define MXC_F_SDHC_REVA_CFG_0_V1_8 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_V1_8_POS)) /**< CFG_0_V1_8 Mask */ 820 821 #define MXC_F_SDHC_REVA_CFG_0_BIT_64_SYS_BUS_POS 28 /**< CFG_0_BIT_64_SYS_BUS Position */ 822 #define MXC_F_SDHC_REVA_CFG_0_BIT_64_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_BIT_64_SYS_BUS_POS)) /**< CFG_0_BIT_64_SYS_BUS Mask */ 823 824 #define MXC_F_SDHC_REVA_CFG_0_ASYNC_INT_POS 29 /**< CFG_0_ASYNC_INT Position */ 825 #define MXC_F_SDHC_REVA_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_0_ASYNC_INT_POS)) /**< CFG_0_ASYNC_INT Mask */ 826 827 #define MXC_F_SDHC_REVA_CFG_0_SLOT_TYPE_POS 30 /**< CFG_0_SLOT_TYPE Position */ 828 #define MXC_F_SDHC_REVA_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_REVA_CFG_0_SLOT_TYPE_POS)) /**< CFG_0_SLOT_TYPE Mask */ 829 830 /**@} end of group SDHC_REVA_CFG_0_Register */ 831 832 /** 833 * @ingroup sdhc_reva_registers 834 * @defgroup SDHC_REVA_CFG_1 SDHC_REVA_CFG_1 835 * @brief Capabilities 32-63. 836 * @{ 837 */ 838 #define MXC_F_SDHC_REVA_CFG_1_SDR50_POS 0 /**< CFG_1_SDR50 Position */ 839 #define MXC_F_SDHC_REVA_CFG_1_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_SDR50_POS)) /**< CFG_1_SDR50 Mask */ 840 841 #define MXC_F_SDHC_REVA_CFG_1_SDR104_POS 1 /**< CFG_1_SDR104 Position */ 842 #define MXC_F_SDHC_REVA_CFG_1_SDR104 ((uint32_t)(0x0UL << MXC_F_SDHC_REVA_CFG_1_SDR104_POS)) /**< CFG_1_SDR104 Mask */ 843 844 #define MXC_F_SDHC_REVA_CFG_1_DDR50_POS 2 /**< CFG_1_DDR50 Position */ 845 #define MXC_F_SDHC_REVA_CFG_1_DDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_DDR50_POS)) /**< CFG_1_DDR50 Mask */ 846 847 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_A_POS 4 /**< CFG_1_DRIVER_A Position */ 848 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_A ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_DRIVER_A_POS)) /**< CFG_1_DRIVER_A Mask */ 849 850 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_C_POS 5 /**< CFG_1_DRIVER_C Position */ 851 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_C ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_DRIVER_C_POS)) /**< CFG_1_DRIVER_C Mask */ 852 853 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_D_POS 6 /**< CFG_1_DRIVER_D Position */ 854 #define MXC_F_SDHC_REVA_CFG_1_DRIVER_D ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_DRIVER_D_POS)) /**< CFG_1_DRIVER_D Mask */ 855 856 #define MXC_F_SDHC_REVA_CFG_1_TIMER_CNT_TUNING_POS 8 /**< CFG_1_TIMER_CNT_TUNING Position */ 857 #define MXC_F_SDHC_REVA_CFG_1_TIMER_CNT_TUNING ((uint32_t)(0xFUL << MXC_F_SDHC_REVA_CFG_1_TIMER_CNT_TUNING_POS)) /**< CFG_1_TIMER_CNT_TUNING Mask */ 858 859 #define MXC_F_SDHC_REVA_CFG_1_TUNING_SDR50_POS 13 /**< CFG_1_TUNING_SDR50 Position */ 860 #define MXC_F_SDHC_REVA_CFG_1_TUNING_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_REVA_CFG_1_TUNING_SDR50_POS)) /**< CFG_1_TUNING_SDR50 Mask */ 861 862 #define MXC_F_SDHC_REVA_CFG_1_RETUNING_POS 14 /**< CFG_1_RETUNING Position */ 863 #define MXC_F_SDHC_REVA_CFG_1_RETUNING ((uint32_t)(0x3UL << MXC_F_SDHC_REVA_CFG_1_RETUNING_POS)) /**< CFG_1_RETUNING Mask */ 864 865 #define MXC_F_SDHC_REVA_CFG_1_CLK_MULTI_POS 16 /**< CFG_1_CLK_MULTI Position */ 866 #define MXC_F_SDHC_REVA_CFG_1_CLK_MULTI ((uint32_t)(0xFFUL << MXC_F_SDHC_REVA_CFG_1_CLK_MULTI_POS)) /**< CFG_1_CLK_MULTI Mask */ 867 868 /**@} end of group SDHC_REVA_CFG_1_Register */ 869 870 /** 871 * @ingroup sdhc_reva_registers 872 * @defgroup SDHC_REVA_MAX_CURR_CFG SDHC_REVA_MAX_CURR_CFG 873 * @brief Maximum Current Capabilities. 874 * @{ 875 */ 876 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_3_POS 0 /**< MAX_CURR_CFG_V3_3 Position */ 877 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_3 ((uint32_t)(0xFFUL << MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_3_POS)) /**< MAX_CURR_CFG_V3_3 Mask */ 878 879 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_0_POS 8 /**< MAX_CURR_CFG_V3_0 Position */ 880 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_0 ((uint32_t)(0xFFUL << MXC_F_SDHC_REVA_MAX_CURR_CFG_V3_0_POS)) /**< MAX_CURR_CFG_V3_0 Mask */ 881 882 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V1_8_POS 16 /**< MAX_CURR_CFG_V1_8 Position */ 883 #define MXC_F_SDHC_REVA_MAX_CURR_CFG_V1_8 ((uint32_t)(0xFFUL << MXC_F_SDHC_REVA_MAX_CURR_CFG_V1_8_POS)) /**< MAX_CURR_CFG_V1_8 Mask */ 884 885 /**@} end of group SDHC_REVA_MAX_CURR_CFG_Register */ 886 887 /** 888 * @ingroup sdhc_reva_registers 889 * @defgroup SDHC_REVA_FORCE_CMD SDHC_REVA_FORCE_CMD 890 * @brief Force Event for Auto CMD Error Status. 891 * @{ 892 */ 893 #define MXC_F_SDHC_REVA_FORCE_CMD_NOT_EXCU_POS 0 /**< FORCE_CMD_NOT_EXCU Position */ 894 #define MXC_F_SDHC_REVA_FORCE_CMD_NOT_EXCU ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_NOT_EXCU_POS)) /**< FORCE_CMD_NOT_EXCU Mask */ 895 896 #define MXC_F_SDHC_REVA_FORCE_CMD_TO_POS 1 /**< FORCE_CMD_TO Position */ 897 #define MXC_F_SDHC_REVA_FORCE_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_TO_POS)) /**< FORCE_CMD_TO Mask */ 898 899 #define MXC_F_SDHC_REVA_FORCE_CMD_CRC_POS 2 /**< FORCE_CMD_CRC Position */ 900 #define MXC_F_SDHC_REVA_FORCE_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_CRC_POS)) /**< FORCE_CMD_CRC Mask */ 901 902 #define MXC_F_SDHC_REVA_FORCE_CMD_END_BIT_POS 3 /**< FORCE_CMD_END_BIT Position */ 903 #define MXC_F_SDHC_REVA_FORCE_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_END_BIT_POS)) /**< FORCE_CMD_END_BIT Mask */ 904 905 #define MXC_F_SDHC_REVA_FORCE_CMD_INDEX_POS 4 /**< FORCE_CMD_INDEX Position */ 906 #define MXC_F_SDHC_REVA_FORCE_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_INDEX_POS)) /**< FORCE_CMD_INDEX Mask */ 907 908 #define MXC_F_SDHC_REVA_FORCE_CMD_NOT_ISSUED_POS 7 /**< FORCE_CMD_NOT_ISSUED Position */ 909 #define MXC_F_SDHC_REVA_FORCE_CMD_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_CMD_NOT_ISSUED_POS)) /**< FORCE_CMD_NOT_ISSUED Mask */ 910 911 /**@} end of group SDHC_REVA_FORCE_CMD_Register */ 912 913 /** 914 * @ingroup sdhc_reva_registers 915 * @defgroup SDHC_REVA_FORCE_EVENT_INT_STAT SDHC_REVA_FORCE_EVENT_INT_STAT 916 * @brief Force Event for Error Interrupt Status. 917 * @{ 918 */ 919 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_TO_POS 0 /**< FORCE_EVENT_INT_STAT_CMD_TO Position */ 920 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_TO_POS)) /**< FORCE_EVENT_INT_STAT_CMD_TO Mask */ 921 922 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_CRC_POS 1 /**< FORCE_EVENT_INT_STAT_CMD_CRC Position */ 923 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_CRC_POS)) /**< FORCE_EVENT_INT_STAT_CMD_CRC Mask */ 924 925 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS 2 /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Position */ 926 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Mask */ 927 928 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_INDEX_POS 3 /**< FORCE_EVENT_INT_STAT_CMD_INDEX Position */ 929 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CMD_INDEX_POS)) /**< FORCE_EVENT_INT_STAT_CMD_INDEX Mask */ 930 931 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_TO_POS 4 /**< FORCE_EVENT_INT_STAT_DATA_TO Position */ 932 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_TO_POS)) /**< FORCE_EVENT_INT_STAT_DATA_TO Mask */ 933 934 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_CRC_POS 5 /**< FORCE_EVENT_INT_STAT_DATA_CRC Position */ 935 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_CRC_POS)) /**< FORCE_EVENT_INT_STAT_DATA_CRC Mask */ 936 937 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS 6 /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Position */ 938 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Mask */ 939 940 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS 7 /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Position */ 941 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CURR_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS)) /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Mask */ 942 943 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_AUTO_CMD_POS 8 /**< FORCE_EVENT_INT_STAT_AUTO_CMD Position */ 944 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_AUTO_CMD_POS)) /**< FORCE_EVENT_INT_STAT_AUTO_CMD Mask */ 945 946 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_ADMA_POS 9 /**< FORCE_EVENT_INT_STAT_ADMA Position */ 947 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_ADMA_POS)) /**< FORCE_EVENT_INT_STAT_ADMA Mask */ 948 949 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_VENDOR_POS 12 /**< FORCE_EVENT_INT_STAT_VENDOR Position */ 950 #define MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_VENDOR ((uint16_t)(0x7UL << MXC_F_SDHC_REVA_FORCE_EVENT_INT_STAT_VENDOR_POS)) /**< FORCE_EVENT_INT_STAT_VENDOR Mask */ 951 952 /**@} end of group SDHC_REVA_FORCE_EVENT_INT_STAT_Register */ 953 954 /** 955 * @ingroup sdhc_reva_registers 956 * @defgroup SDHC_REVA_ADMA_ER SDHC_REVA_ADMA_ER 957 * @brief ADMA Error Status. 958 * @{ 959 */ 960 #define MXC_F_SDHC_REVA_ADMA_ER_STATE_POS 0 /**< ADMA_ER_STATE Position */ 961 #define MXC_F_SDHC_REVA_ADMA_ER_STATE ((uint8_t)(0x3UL << MXC_F_SDHC_REVA_ADMA_ER_STATE_POS)) /**< ADMA_ER_STATE Mask */ 962 963 #define MXC_F_SDHC_REVA_ADMA_ER_LEN_MISMATCH_POS 2 /**< ADMA_ER_LEN_MISMATCH Position */ 964 #define MXC_F_SDHC_REVA_ADMA_ER_LEN_MISMATCH ((uint8_t)(0x1UL << MXC_F_SDHC_REVA_ADMA_ER_LEN_MISMATCH_POS)) /**< ADMA_ER_LEN_MISMATCH Mask */ 965 966 /**@} end of group SDHC_REVA_ADMA_ER_Register */ 967 968 /** 969 * @ingroup sdhc_reva_registers 970 * @defgroup SDHC_REVA_ADMA_ADDR_0 SDHC_REVA_ADMA_ADDR_0 971 * @brief ADMA System Address 0-31. 972 * @{ 973 */ 974 #define MXC_F_SDHC_REVA_ADMA_ADDR_0_ADDR_POS 0 /**< ADMA_ADDR_0_ADDR Position */ 975 #define MXC_F_SDHC_REVA_ADMA_ADDR_0_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_ADMA_ADDR_0_ADDR_POS)) /**< ADMA_ADDR_0_ADDR Mask */ 976 977 /**@} end of group SDHC_REVA_ADMA_ADDR_0_Register */ 978 979 /** 980 * @ingroup sdhc_reva_registers 981 * @defgroup SDHC_REVA_ADMA_ADDR_1 SDHC_REVA_ADMA_ADDR_1 982 * @brief ADMA System Address 32-63. 983 * @{ 984 */ 985 #define MXC_F_SDHC_REVA_ADMA_ADDR_1_ADDR_POS 0 /**< ADMA_ADDR_1_ADDR Position */ 986 #define MXC_F_SDHC_REVA_ADMA_ADDR_1_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_REVA_ADMA_ADDR_1_ADDR_POS)) /**< ADMA_ADDR_1_ADDR Mask */ 987 988 /**@} end of group SDHC_REVA_ADMA_ADDR_1_Register */ 989 990 /** 991 * @ingroup sdhc_reva_registers 992 * @defgroup SDHC_REVA_PRESET_0 SDHC_REVA_PRESET_0 993 * @brief Preset Value for Initialization. 994 * @{ 995 */ 996 #define MXC_F_SDHC_REVA_PRESET_0_SDCLK_FREQ_POS 0 /**< PRESET_0_SDCLK_FREQ Position */ 997 #define MXC_F_SDHC_REVA_PRESET_0_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_0_SDCLK_FREQ_POS)) /**< PRESET_0_SDCLK_FREQ Mask */ 998 999 #define MXC_F_SDHC_REVA_PRESET_0_CLK_GEN_POS 10 /**< PRESET_0_CLK_GEN Position */ 1000 #define MXC_F_SDHC_REVA_PRESET_0_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_0_CLK_GEN_POS)) /**< PRESET_0_CLK_GEN Mask */ 1001 1002 #define MXC_F_SDHC_REVA_PRESET_0_DRIVER_STRENGTH_POS 14 /**< PRESET_0_DRIVER_STRENGTH Position */ 1003 #define MXC_F_SDHC_REVA_PRESET_0_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_0_DRIVER_STRENGTH_POS)) /**< PRESET_0_DRIVER_STRENGTH Mask */ 1004 1005 /**@} end of group SDHC_REVA_PRESET_0_Register */ 1006 1007 /** 1008 * @ingroup sdhc_reva_registers 1009 * @defgroup SDHC_REVA_PRESET_1 SDHC_REVA_PRESET_1 1010 * @brief Preset Value for Default Speed. 1011 * @{ 1012 */ 1013 #define MXC_F_SDHC_REVA_PRESET_1_SDCLK_FREQ_POS 0 /**< PRESET_1_SDCLK_FREQ Position */ 1014 #define MXC_F_SDHC_REVA_PRESET_1_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_1_SDCLK_FREQ_POS)) /**< PRESET_1_SDCLK_FREQ Mask */ 1015 1016 #define MXC_F_SDHC_REVA_PRESET_1_CLK_GEN_POS 10 /**< PRESET_1_CLK_GEN Position */ 1017 #define MXC_F_SDHC_REVA_PRESET_1_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_1_CLK_GEN_POS)) /**< PRESET_1_CLK_GEN Mask */ 1018 1019 #define MXC_F_SDHC_REVA_PRESET_1_DRIVER_STRENGTH_POS 14 /**< PRESET_1_DRIVER_STRENGTH Position */ 1020 #define MXC_F_SDHC_REVA_PRESET_1_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_1_DRIVER_STRENGTH_POS)) /**< PRESET_1_DRIVER_STRENGTH Mask */ 1021 1022 /**@} end of group SDHC_REVA_PRESET_1_Register */ 1023 1024 /** 1025 * @ingroup sdhc_reva_registers 1026 * @defgroup SDHC_REVA_PRESET_2 SDHC_REVA_PRESET_2 1027 * @brief Preset Value for High Speed. 1028 * @{ 1029 */ 1030 #define MXC_F_SDHC_REVA_PRESET_2_SDCLK_FREQ_POS 0 /**< PRESET_2_SDCLK_FREQ Position */ 1031 #define MXC_F_SDHC_REVA_PRESET_2_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_2_SDCLK_FREQ_POS)) /**< PRESET_2_SDCLK_FREQ Mask */ 1032 1033 #define MXC_F_SDHC_REVA_PRESET_2_CLK_GEN_POS 10 /**< PRESET_2_CLK_GEN Position */ 1034 #define MXC_F_SDHC_REVA_PRESET_2_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_2_CLK_GEN_POS)) /**< PRESET_2_CLK_GEN Mask */ 1035 1036 #define MXC_F_SDHC_REVA_PRESET_2_DRIVER_STRENGTH_POS 14 /**< PRESET_2_DRIVER_STRENGTH Position */ 1037 #define MXC_F_SDHC_REVA_PRESET_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_2_DRIVER_STRENGTH_POS)) /**< PRESET_2_DRIVER_STRENGTH Mask */ 1038 1039 /**@} end of group SDHC_REVA_PRESET_2_Register */ 1040 1041 /** 1042 * @ingroup sdhc_reva_registers 1043 * @defgroup SDHC_REVA_PRESET_3 SDHC_REVA_PRESET_3 1044 * @brief Preset Value for SDR12. 1045 * @{ 1046 */ 1047 #define MXC_F_SDHC_REVA_PRESET_3_SDCLK_FREQ_POS 0 /**< PRESET_3_SDCLK_FREQ Position */ 1048 #define MXC_F_SDHC_REVA_PRESET_3_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_3_SDCLK_FREQ_POS)) /**< PRESET_3_SDCLK_FREQ Mask */ 1049 1050 #define MXC_F_SDHC_REVA_PRESET_3_CLK_GEN_POS 10 /**< PRESET_3_CLK_GEN Position */ 1051 #define MXC_F_SDHC_REVA_PRESET_3_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_3_CLK_GEN_POS)) /**< PRESET_3_CLK_GEN Mask */ 1052 1053 #define MXC_F_SDHC_REVA_PRESET_3_DRIVER_STRENGTH_POS 14 /**< PRESET_3_DRIVER_STRENGTH Position */ 1054 #define MXC_F_SDHC_REVA_PRESET_3_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_3_DRIVER_STRENGTH_POS)) /**< PRESET_3_DRIVER_STRENGTH Mask */ 1055 1056 /**@} end of group SDHC_REVA_PRESET_3_Register */ 1057 1058 /** 1059 * @ingroup sdhc_reva_registers 1060 * @defgroup SDHC_REVA_PRESET_4 SDHC_REVA_PRESET_4 1061 * @brief Preset Value for SDR25. 1062 * @{ 1063 */ 1064 #define MXC_F_SDHC_REVA_PRESET_4_SDCLK_FREQ_POS 0 /**< PRESET_4_SDCLK_FREQ Position */ 1065 #define MXC_F_SDHC_REVA_PRESET_4_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_4_SDCLK_FREQ_POS)) /**< PRESET_4_SDCLK_FREQ Mask */ 1066 1067 #define MXC_F_SDHC_REVA_PRESET_4_CLK_GEN_POS 10 /**< PRESET_4_CLK_GEN Position */ 1068 #define MXC_F_SDHC_REVA_PRESET_4_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_4_CLK_GEN_POS)) /**< PRESET_4_CLK_GEN Mask */ 1069 1070 #define MXC_F_SDHC_REVA_PRESET_4_DRIVER_STRENGTH_POS 14 /**< PRESET_4_DRIVER_STRENGTH Position */ 1071 #define MXC_F_SDHC_REVA_PRESET_4_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_4_DRIVER_STRENGTH_POS)) /**< PRESET_4_DRIVER_STRENGTH Mask */ 1072 1073 /**@} end of group SDHC_REVA_PRESET_4_Register */ 1074 1075 /** 1076 * @ingroup sdhc_reva_registers 1077 * @defgroup SDHC_REVA_PRESET_5 SDHC_REVA_PRESET_5 1078 * @brief Preset Value for SDR50. 1079 * @{ 1080 */ 1081 #define MXC_F_SDHC_REVA_PRESET_5_SDCLK_FREQ_POS 0 /**< PRESET_5_SDCLK_FREQ Position */ 1082 #define MXC_F_SDHC_REVA_PRESET_5_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_5_SDCLK_FREQ_POS)) /**< PRESET_5_SDCLK_FREQ Mask */ 1083 1084 #define MXC_F_SDHC_REVA_PRESET_5_CLK_GEN_POS 10 /**< PRESET_5_CLK_GEN Position */ 1085 #define MXC_F_SDHC_REVA_PRESET_5_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_5_CLK_GEN_POS)) /**< PRESET_5_CLK_GEN Mask */ 1086 1087 #define MXC_F_SDHC_REVA_PRESET_5_DRIVER_STRENGTH_POS 14 /**< PRESET_5_DRIVER_STRENGTH Position */ 1088 #define MXC_F_SDHC_REVA_PRESET_5_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_5_DRIVER_STRENGTH_POS)) /**< PRESET_5_DRIVER_STRENGTH Mask */ 1089 1090 /**@} end of group SDHC_REVA_PRESET_5_Register */ 1091 1092 /** 1093 * @ingroup sdhc_reva_registers 1094 * @defgroup SDHC_REVA_PRESET_6 SDHC_REVA_PRESET_6 1095 * @brief Preset Value for SDR104. 1096 * @{ 1097 */ 1098 #define MXC_F_SDHC_REVA_PRESET_6_SDCLK_FREQ_POS 0 /**< PRESET_6_SDCLK_FREQ Position */ 1099 #define MXC_F_SDHC_REVA_PRESET_6_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_6_SDCLK_FREQ_POS)) /**< PRESET_6_SDCLK_FREQ Mask */ 1100 1101 #define MXC_F_SDHC_REVA_PRESET_6_CLK_GEN_POS 10 /**< PRESET_6_CLK_GEN Position */ 1102 #define MXC_F_SDHC_REVA_PRESET_6_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_6_CLK_GEN_POS)) /**< PRESET_6_CLK_GEN Mask */ 1103 1104 #define MXC_F_SDHC_REVA_PRESET_6_DRIVER_STRENGTH_POS 14 /**< PRESET_6_DRIVER_STRENGTH Position */ 1105 #define MXC_F_SDHC_REVA_PRESET_6_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_6_DRIVER_STRENGTH_POS)) /**< PRESET_6_DRIVER_STRENGTH Mask */ 1106 1107 /**@} end of group SDHC_REVA_PRESET_6_Register */ 1108 1109 /** 1110 * @ingroup sdhc_reva_registers 1111 * @defgroup SDHC_REVA_PRESET_7 SDHC_REVA_PRESET_7 1112 * @brief Preset Value for DDR50. 1113 * @{ 1114 */ 1115 #define MXC_F_SDHC_REVA_PRESET_7_SDCLK_FREQ_POS 0 /**< PRESET_7_SDCLK_FREQ Position */ 1116 #define MXC_F_SDHC_REVA_PRESET_7_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_REVA_PRESET_7_SDCLK_FREQ_POS)) /**< PRESET_7_SDCLK_FREQ Mask */ 1117 1118 #define MXC_F_SDHC_REVA_PRESET_7_CLK_GEN_POS 10 /**< PRESET_7_CLK_GEN Position */ 1119 #define MXC_F_SDHC_REVA_PRESET_7_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_PRESET_7_CLK_GEN_POS)) /**< PRESET_7_CLK_GEN Mask */ 1120 1121 #define MXC_F_SDHC_REVA_PRESET_7_DRIVER_STRENGTH_POS 14 /**< PRESET_7_DRIVER_STRENGTH Position */ 1122 #define MXC_F_SDHC_REVA_PRESET_7_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_REVA_PRESET_7_DRIVER_STRENGTH_POS)) /**< PRESET_7_DRIVER_STRENGTH Mask */ 1123 1124 /**@} end of group SDHC_REVA_PRESET_7_Register */ 1125 1126 /** 1127 * @ingroup sdhc_reva_registers 1128 * @defgroup SDHC_REVA_SLOT_INT SDHC_REVA_SLOT_INT 1129 * @brief Slot Interrupt Status. 1130 * @{ 1131 */ 1132 #define MXC_F_SDHC_REVA_SLOT_INT_INT_SIGNALS_POS 0 /**< SLOT_INT_INT_SIGNALS Position */ 1133 #define MXC_F_SDHC_REVA_SLOT_INT_INT_SIGNALS ((uint16_t)(0x1UL << MXC_F_SDHC_REVA_SLOT_INT_INT_SIGNALS_POS)) /**< SLOT_INT_INT_SIGNALS Mask */ 1134 1135 /**@} end of group SDHC_REVA_SLOT_INT_Register */ 1136 1137 /** 1138 * @ingroup sdhc_reva_registers 1139 * @defgroup SDHC_REVA_HOST_CN_VER SDHC_REVA_HOST_CN_VER 1140 * @brief Host Controller Version. 1141 * @{ 1142 */ 1143 #define MXC_F_SDHC_REVA_HOST_CN_VER_SPEC_VER_POS 0 /**< HOST_CN_VER_SPEC_VER Position */ 1144 #define MXC_F_SDHC_REVA_HOST_CN_VER_SPEC_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_REVA_HOST_CN_VER_SPEC_VER_POS)) /**< HOST_CN_VER_SPEC_VER Mask */ 1145 1146 #define MXC_F_SDHC_REVA_HOST_CN_VER_VEND_VER_POS 8 /**< HOST_CN_VER_VEND_VER Position */ 1147 #define MXC_F_SDHC_REVA_HOST_CN_VER_VEND_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_REVA_HOST_CN_VER_VEND_VER_POS)) /**< HOST_CN_VER_VEND_VER Mask */ 1148 1149 /**@} end of group SDHC_REVA_HOST_CN_VER_Register */ 1150 1151 #ifdef __cplusplus 1152 } 1153 #endif 1154 1155 #endif /* _SDHC_REVA_REGS_H_ */ 1156
