1 /** 2 * @file rtc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup rtc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_RTC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_RTC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup rtc 67 * @defgroup rtc_registers RTC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 69 * @details Real Time Clock and Alarm. 70 */ 71 72 /** 73 * @ingroup rtc_registers 74 * Structure type to access the RTC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */ 78 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */ 79 __IO uint32_t toda; /**< <tt>\b 0x08:</tt> RTC TODA Register */ 80 __IO uint32_t sseca; /**< <tt>\b 0x0C:</tt> RTC SSECA Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */ 82 __R uint32_t rsv_0x14; 83 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */ 84 } mxc_rtc_regs_t; 85 86 /* Register offsets for module RTC */ 87 /** 88 * @ingroup rtc_registers 89 * @defgroup RTC_Register_Offsets Register Offsets 90 * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 99 /**@} end of group rtc_registers */ 100 101 /** 102 * @ingroup rtc_registers 103 * @defgroup RTC_SEC RTC_SEC 104 * @brief RTC Second Counter. This register contains the 32-bit second counter. 105 * @{ 106 */ 107 #define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ 108 #define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ 109 110 /**@} end of group RTC_SEC_Register */ 111 112 /** 113 * @ingroup rtc_registers 114 * @defgroup RTC_SSEC RTC_SSEC 115 * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented 116 * when this register rolls over from 0xFF to 0x00. 117 * @{ 118 */ 119 #define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ 120 #define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ 121 122 /**@} end of group RTC_SSEC_Register */ 123 124 /** 125 * @ingroup rtc_registers 126 * @defgroup RTC_TODA RTC_TODA 127 * @brief Time-of-day Alarm. 128 * @{ 129 */ 130 #define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ 131 #define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ 132 133 /**@} end of group RTC_TODA_Register */ 134 135 /** 136 * @ingroup rtc_registers 137 * @defgroup RTC_SSECA RTC_SSECA 138 * @brief RTC sub-second alarm. This register contains the reload value for the sub- 139 * second alarm. 140 * @{ 141 */ 142 #define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ 143 #define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ 144 145 /**@} end of group RTC_SSECA_Register */ 146 147 /** 148 * @ingroup rtc_registers 149 * @defgroup RTC_CTRL RTC_CTRL 150 * @brief RTC Control Register. 151 * @{ 152 */ 153 #define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ 154 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ 155 #define MXC_V_RTC_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ 156 #define MXC_S_RTC_CTRL_ENABLE_DIS (MXC_V_RTC_CTRL_ENABLE_DIS << MXC_F_RTC_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ 157 #define MXC_V_RTC_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */ 158 #define MXC_S_RTC_CTRL_ENABLE_EN (MXC_V_RTC_CTRL_ENABLE_EN << MXC_F_RTC_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ 159 160 #define MXC_F_RTC_CTRL_TOD_ALARM_EN_POS 1 /**< CTRL_TOD_ALARM_EN Position */ 161 #define MXC_F_RTC_CTRL_TOD_ALARM_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_EN_POS)) /**< CTRL_TOD_ALARM_EN Mask */ 162 #define MXC_V_RTC_CTRL_TOD_ALARM_EN_DIS ((uint32_t)0x0UL) /**< CTRL_TOD_ALARM_EN_DIS Value */ 163 #define MXC_S_RTC_CTRL_TOD_ALARM_EN_DIS (MXC_V_RTC_CTRL_TOD_ALARM_EN_DIS << MXC_F_RTC_CTRL_TOD_ALARM_EN_POS) /**< CTRL_TOD_ALARM_EN_DIS Setting */ 164 #define MXC_V_RTC_CTRL_TOD_ALARM_EN_EN ((uint32_t)0x1UL) /**< CTRL_TOD_ALARM_EN_EN Value */ 165 #define MXC_S_RTC_CTRL_TOD_ALARM_EN_EN (MXC_V_RTC_CTRL_TOD_ALARM_EN_EN << MXC_F_RTC_CTRL_TOD_ALARM_EN_POS) /**< CTRL_TOD_ALARM_EN_EN Setting */ 166 167 #define MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS 2 /**< CTRL_SSEC_ALARM_EN Position */ 168 #define MXC_F_RTC_CTRL_SSEC_ALARM_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS)) /**< CTRL_SSEC_ALARM_EN Mask */ 169 #define MXC_V_RTC_CTRL_SSEC_ALARM_EN_DIS ((uint32_t)0x0UL) /**< CTRL_SSEC_ALARM_EN_DIS Value */ 170 #define MXC_S_RTC_CTRL_SSEC_ALARM_EN_DIS (MXC_V_RTC_CTRL_SSEC_ALARM_EN_DIS << MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS) /**< CTRL_SSEC_ALARM_EN_DIS Setting */ 171 #define MXC_V_RTC_CTRL_SSEC_ALARM_EN_EN ((uint32_t)0x1UL) /**< CTRL_SSEC_ALARM_EN_EN Value */ 172 #define MXC_S_RTC_CTRL_SSEC_ALARM_EN_EN (MXC_V_RTC_CTRL_SSEC_ALARM_EN_EN << MXC_F_RTC_CTRL_SSEC_ALARM_EN_POS) /**< CTRL_SSEC_ALARM_EN_EN Setting */ 173 174 #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 175 #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 176 #define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */ 177 #define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */ 178 #define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */ 179 #define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */ 180 181 #define MXC_F_RTC_CTRL_READY_POS 4 /**< CTRL_READY Position */ 182 #define MXC_F_RTC_CTRL_READY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_READY_POS)) /**< CTRL_READY Mask */ 183 #define MXC_V_RTC_CTRL_READY_NOT_READY ((uint32_t)0x0UL) /**< CTRL_READY_NOT_READY Value */ 184 #define MXC_S_RTC_CTRL_READY_NOT_READY (MXC_V_RTC_CTRL_READY_NOT_READY << MXC_F_RTC_CTRL_READY_POS) /**< CTRL_READY_NOT_READY Setting */ 185 #define MXC_V_RTC_CTRL_READY_READY ((uint32_t)0x1UL) /**< CTRL_READY_READY Value */ 186 #define MXC_S_RTC_CTRL_READY_READY (MXC_V_RTC_CTRL_READY_READY << MXC_F_RTC_CTRL_READY_POS) /**< CTRL_READY_READY Setting */ 187 188 #define MXC_F_RTC_CTRL_READY_INT_EN_POS 5 /**< CTRL_READY_INT_EN Position */ 189 #define MXC_F_RTC_CTRL_READY_INT_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_READY_INT_EN_POS)) /**< CTRL_READY_INT_EN Mask */ 190 #define MXC_V_RTC_CTRL_READY_INT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_READY_INT_EN_DIS Value */ 191 #define MXC_S_RTC_CTRL_READY_INT_EN_DIS (MXC_V_RTC_CTRL_READY_INT_EN_DIS << MXC_F_RTC_CTRL_READY_INT_EN_POS) /**< CTRL_READY_INT_EN_DIS Setting */ 192 #define MXC_V_RTC_CTRL_READY_INT_EN_EN ((uint32_t)0x1UL) /**< CTRL_READY_INT_EN_EN Value */ 193 #define MXC_S_RTC_CTRL_READY_INT_EN_EN (MXC_V_RTC_CTRL_READY_INT_EN_EN << MXC_F_RTC_CTRL_READY_INT_EN_POS) /**< CTRL_READY_INT_EN_EN Setting */ 194 195 #define MXC_F_RTC_CTRL_TOD_ALARM_FL_POS 6 /**< CTRL_TOD_ALARM_FL Position */ 196 #define MXC_F_RTC_CTRL_TOD_ALARM_FL ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_FL_POS)) /**< CTRL_TOD_ALARM_FL Mask */ 197 #define MXC_V_RTC_CTRL_TOD_ALARM_FL_INACTIVE ((uint32_t)0x0UL) /**< CTRL_TOD_ALARM_FL_INACTIVE Value */ 198 #define MXC_S_RTC_CTRL_TOD_ALARM_FL_INACTIVE (MXC_V_RTC_CTRL_TOD_ALARM_FL_INACTIVE << MXC_F_RTC_CTRL_TOD_ALARM_FL_POS) /**< CTRL_TOD_ALARM_FL_INACTIVE Setting */ 199 #define MXC_V_RTC_CTRL_TOD_ALARM_FL_PENDING ((uint32_t)0x1UL) /**< CTRL_TOD_ALARM_FL_PENDING Value */ 200 #define MXC_S_RTC_CTRL_TOD_ALARM_FL_PENDING (MXC_V_RTC_CTRL_TOD_ALARM_FL_PENDING << MXC_F_RTC_CTRL_TOD_ALARM_FL_POS) /**< CTRL_TOD_ALARM_FL_PENDING Setting */ 201 202 #define MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS 7 /**< CTRL_SSEC_ALARM_FL Position */ 203 #define MXC_F_RTC_CTRL_SSEC_ALARM_FL ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS)) /**< CTRL_SSEC_ALARM_FL Mask */ 204 #define MXC_V_RTC_CTRL_SSEC_ALARM_FL_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SSEC_ALARM_FL_INACTIVE Value */ 205 #define MXC_S_RTC_CTRL_SSEC_ALARM_FL_INACTIVE (MXC_V_RTC_CTRL_SSEC_ALARM_FL_INACTIVE << MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS) /**< CTRL_SSEC_ALARM_FL_INACTIVE Setting */ 206 #define MXC_V_RTC_CTRL_SSEC_ALARM_FL_PENDING ((uint32_t)0x1UL) /**< CTRL_SSEC_ALARM_FL_PENDING Value */ 207 #define MXC_S_RTC_CTRL_SSEC_ALARM_FL_PENDING (MXC_V_RTC_CTRL_SSEC_ALARM_FL_PENDING << MXC_F_RTC_CTRL_SSEC_ALARM_FL_POS) /**< CTRL_SSEC_ALARM_FL_PENDING Setting */ 208 209 #define MXC_F_RTC_CTRL_SQWOUT_EN_POS 8 /**< CTRL_SQWOUT_EN Position */ 210 #define MXC_F_RTC_CTRL_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQWOUT_EN_POS)) /**< CTRL_SQWOUT_EN Mask */ 211 #define MXC_V_RTC_CTRL_SQWOUT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_SQWOUT_EN_DIS Value */ 212 #define MXC_S_RTC_CTRL_SQWOUT_EN_DIS (MXC_V_RTC_CTRL_SQWOUT_EN_DIS << MXC_F_RTC_CTRL_SQWOUT_EN_POS) /**< CTRL_SQWOUT_EN_DIS Setting */ 213 #define MXC_V_RTC_CTRL_SQWOUT_EN_EN ((uint32_t)0x1UL) /**< CTRL_SQWOUT_EN_EN Value */ 214 #define MXC_S_RTC_CTRL_SQWOUT_EN_EN (MXC_V_RTC_CTRL_SQWOUT_EN_EN << MXC_F_RTC_CTRL_SQWOUT_EN_POS) /**< CTRL_SQWOUT_EN_EN Setting */ 215 216 #define MXC_F_RTC_CTRL_FREQ_SEL_POS 9 /**< CTRL_FREQ_SEL Position */ 217 #define MXC_F_RTC_CTRL_FREQ_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FREQ_SEL_POS)) /**< CTRL_FREQ_SEL Mask */ 218 #define MXC_V_RTC_CTRL_FREQ_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FREQ_SEL_FREQ1HZ Value */ 219 #define MXC_S_RTC_CTRL_FREQ_SEL_FREQ1HZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ1HZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) /**< CTRL_FREQ_SEL_FREQ1HZ Setting */ 220 #define MXC_V_RTC_CTRL_FREQ_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FREQ_SEL_FREQ512HZ Value */ 221 #define MXC_S_RTC_CTRL_FREQ_SEL_FREQ512HZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ512HZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) /**< CTRL_FREQ_SEL_FREQ512HZ Setting */ 222 #define MXC_V_RTC_CTRL_FREQ_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FREQ_SEL_FREQ4KHZ Value */ 223 #define MXC_S_RTC_CTRL_FREQ_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_FREQ_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_FREQ_SEL_POS) /**< CTRL_FREQ_SEL_FREQ4KHZ Setting */ 224 225 #define MXC_F_RTC_CTRL_ACRE_POS 14 /**< CTRL_ACRE Position */ 226 #define MXC_F_RTC_CTRL_ACRE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ACRE_POS)) /**< CTRL_ACRE Mask */ 227 #define MXC_V_RTC_CTRL_ACRE_SYNC ((uint32_t)0x0UL) /**< CTRL_ACRE_SYNC Value */ 228 #define MXC_S_RTC_CTRL_ACRE_SYNC (MXC_V_RTC_CTRL_ACRE_SYNC << MXC_F_RTC_CTRL_ACRE_POS) /**< CTRL_ACRE_SYNC Setting */ 229 #define MXC_V_RTC_CTRL_ACRE_ASYNC ((uint32_t)0x1UL) /**< CTRL_ACRE_ASYNC Value */ 230 #define MXC_S_RTC_CTRL_ACRE_ASYNC (MXC_V_RTC_CTRL_ACRE_ASYNC << MXC_F_RTC_CTRL_ACRE_POS) /**< CTRL_ACRE_ASYNC Setting */ 231 232 #define MXC_F_RTC_CTRL_WRITE_EN_POS 15 /**< CTRL_WRITE_EN Position */ 233 #define MXC_F_RTC_CTRL_WRITE_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WRITE_EN_POS)) /**< CTRL_WRITE_EN Mask */ 234 #define MXC_V_RTC_CTRL_WRITE_EN_DIS ((uint32_t)0x0UL) /**< CTRL_WRITE_EN_DIS Value */ 235 #define MXC_S_RTC_CTRL_WRITE_EN_DIS (MXC_V_RTC_CTRL_WRITE_EN_DIS << MXC_F_RTC_CTRL_WRITE_EN_POS) /**< CTRL_WRITE_EN_DIS Setting */ 236 #define MXC_V_RTC_CTRL_WRITE_EN_EN ((uint32_t)0x1UL) /**< CTRL_WRITE_EN_EN Value */ 237 #define MXC_S_RTC_CTRL_WRITE_EN_EN (MXC_V_RTC_CTRL_WRITE_EN_EN << MXC_F_RTC_CTRL_WRITE_EN_POS) /**< CTRL_WRITE_EN_EN Setting */ 238 239 /**@} end of group RTC_CTRL_Register */ 240 241 /** 242 * @ingroup rtc_registers 243 * @defgroup RTC_OSCCTRL RTC_OSCCTRL 244 * @brief RTC Oscillator Control Register. 245 * @{ 246 */ 247 #define MXC_F_RTC_OSCCTRL_FILTER_EN_POS 0 /**< OSCCTRL_FILTER_EN Position */ 248 #define MXC_F_RTC_OSCCTRL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FILTER_EN_POS)) /**< OSCCTRL_FILTER_EN Mask */ 249 250 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ 251 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ 252 253 #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ 254 #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ 255 256 #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ 257 #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ 258 259 #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 260 #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 261 262 #define MXC_F_RTC_OSCCTRL_32KOUT_POS 5 /**< OSCCTRL_32KOUT Position */ 263 #define MXC_F_RTC_OSCCTRL_32KOUT ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_32KOUT_POS)) /**< OSCCTRL_32KOUT Mask */ 264 265 /**@} end of group RTC_OSCCTRL_Register */ 266 267 #ifdef __cplusplus 268 } 269 #endif 270 271 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_RTC_REGS_H_ 272
