1 /** 2 * @file qdec_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the QDEC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _QDEC_REVA_REGS_H_ 27 #define _QDEC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup qdec_reva 65 * @defgroup qdec_reva_registers QDEC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the QDEC_REVA Peripheral Module. 67 * @details Quadrature Encoder Interface 68 */ 69 70 /** 71 * @ingroup qdec_reva_registers 72 * Structure type to access the QDEC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> QDEC_REVA CTRL Register */ 76 __IO uint32_t intfl; /**< <tt>\b 0x0004:</tt> QDEC_REVA INTFL Register */ 77 __IO uint32_t inten; /**< <tt>\b 0x0008:</tt> QDEC_REVA INTEN Register */ 78 __IO uint32_t maxcnt; /**< <tt>\b 0x000C:</tt> QDEC_REVA MAXCNT Register */ 79 __IO uint32_t initial; /**< <tt>\b 0x0010:</tt> QDEC_REVA INITIAL Register */ 80 __IO uint32_t compare; /**< <tt>\b 0x0014:</tt> QDEC_REVA COMPARE Register */ 81 __I uint32_t index; /**< <tt>\b 0x0018:</tt> QDEC_REVA INDEX Register */ 82 __I uint32_t capture; /**< <tt>\b 0x001C:</tt> QDEC_REVA CAPTURE Register */ 83 __I uint32_t status; /**< <tt>\b 0x0020:</tt> QDEC_REVA STATUS Register */ 84 __IO uint32_t position; /**< <tt>\b 0x0024:</tt> QDEC_REVA POSITION Register */ 85 __IO uint32_t capdly; /**< <tt>\b 0x0028:</tt> QDEC_REVA CAPDLY Register */ 86 } mxc_qdec_reva_regs_t; 87 88 /* Register offsets for module QDEC_REVA */ 89 /** 90 * @ingroup qdec_reva_registers 91 * @defgroup QDEC_REVA_Register_Offsets Register Offsets 92 * @brief QDEC_REVA Peripheral Register Offsets from the QDEC_REVA Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_QDEC_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_QDEC_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_QDEC_REVA_INTEN ((uint32_t)0x00000008UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_QDEC_REVA_MAXCNT ((uint32_t)0x0000000CUL) /**< Offset from QDEC_REVA Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_QDEC_REVA_INITIAL ((uint32_t)0x00000010UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_QDEC_REVA_COMPARE ((uint32_t)0x00000014UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0014</tt> */ 101 #define MXC_R_QDEC_REVA_INDEX ((uint32_t)0x00000018UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0018</tt> */ 102 #define MXC_R_QDEC_REVA_CAPTURE ((uint32_t)0x0000001CUL) /**< Offset from QDEC_REVA Base Address: <tt> 0x001C</tt> */ 103 #define MXC_R_QDEC_REVA_STATUS ((uint32_t)0x00000020UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0020</tt> */ 104 #define MXC_R_QDEC_REVA_POSITION ((uint32_t)0x00000024UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0024</tt> */ 105 #define MXC_R_QDEC_REVA_CAPDLY ((uint32_t)0x00000028UL) /**< Offset from QDEC_REVA Base Address: <tt> 0x0028</tt> */ 106 /**@} end of group qdec_reva_registers */ 107 108 /** 109 * @ingroup qdec_reva_registers 110 * @defgroup QDEC_REVA_CTRL QDEC_REVA_CTRL 111 * @brief Control Register. 112 * @{ 113 */ 114 #define MXC_F_QDEC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 115 #define MXC_F_QDEC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 116 117 #define MXC_F_QDEC_REVA_CTRL_MODE_POS 1 /**< CTRL_MODE Position */ 118 #define MXC_F_QDEC_REVA_CTRL_MODE ((uint32_t)(0x3UL << MXC_F_QDEC_REVA_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ 119 #define MXC_V_QDEC_REVA_CTRL_MODE_X1MODE ((uint32_t)0x0UL) /**< CTRL_MODE_X1MODE Value */ 120 #define MXC_S_QDEC_REVA_CTRL_MODE_X1MODE (MXC_V_QDEC_REVA_CTRL_MODE_X1MODE << MXC_F_QDEC_REVA_CTRL_MODE_POS) /**< CTRL_MODE_X1MODE Setting */ 121 #define MXC_V_QDEC_REVA_CTRL_MODE_X2MODE ((uint32_t)0x1UL) /**< CTRL_MODE_X2MODE Value */ 122 #define MXC_S_QDEC_REVA_CTRL_MODE_X2MODE (MXC_V_QDEC_REVA_CTRL_MODE_X2MODE << MXC_F_QDEC_REVA_CTRL_MODE_POS) /**< CTRL_MODE_X2MODE Setting */ 123 #define MXC_V_QDEC_REVA_CTRL_MODE_X4MODE ((uint32_t)0x2UL) /**< CTRL_MODE_X4MODE Value */ 124 #define MXC_S_QDEC_REVA_CTRL_MODE_X4MODE (MXC_V_QDEC_REVA_CTRL_MODE_X4MODE << MXC_F_QDEC_REVA_CTRL_MODE_POS) /**< CTRL_MODE_X4MODE Setting */ 125 126 #define MXC_F_QDEC_REVA_CTRL_SWAP_POS 3 /**< CTRL_SWAP Position */ 127 #define MXC_F_QDEC_REVA_CTRL_SWAP ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_CTRL_SWAP_POS)) /**< CTRL_SWAP Mask */ 128 129 #define MXC_F_QDEC_REVA_CTRL_FILTER_POS 4 /**< CTRL_FILTER Position */ 130 #define MXC_F_QDEC_REVA_CTRL_FILTER ((uint32_t)(0x3UL << MXC_F_QDEC_REVA_CTRL_FILTER_POS)) /**< CTRL_FILTER Mask */ 131 #define MXC_V_QDEC_REVA_CTRL_FILTER_1_SAMPLE ((uint32_t)0x0UL) /**< CTRL_FILTER_1_SAMPLE Value */ 132 #define MXC_S_QDEC_REVA_CTRL_FILTER_1_SAMPLE (MXC_V_QDEC_REVA_CTRL_FILTER_1_SAMPLE << MXC_F_QDEC_REVA_CTRL_FILTER_POS) /**< CTRL_FILTER_1_SAMPLE Setting */ 133 #define MXC_V_QDEC_REVA_CTRL_FILTER_2_SAMPLES ((uint32_t)0x1UL) /**< CTRL_FILTER_2_SAMPLES Value */ 134 #define MXC_S_QDEC_REVA_CTRL_FILTER_2_SAMPLES (MXC_V_QDEC_REVA_CTRL_FILTER_2_SAMPLES << MXC_F_QDEC_REVA_CTRL_FILTER_POS) /**< CTRL_FILTER_2_SAMPLES Setting */ 135 #define MXC_V_QDEC_REVA_CTRL_FILTER_3_SAMPLES ((uint32_t)0x2UL) /**< CTRL_FILTER_3_SAMPLES Value */ 136 #define MXC_S_QDEC_REVA_CTRL_FILTER_3_SAMPLES (MXC_V_QDEC_REVA_CTRL_FILTER_3_SAMPLES << MXC_F_QDEC_REVA_CTRL_FILTER_POS) /**< CTRL_FILTER_3_SAMPLES Setting */ 137 #define MXC_V_QDEC_REVA_CTRL_FILTER_4_SAMPLES ((uint32_t)0x3UL) /**< CTRL_FILTER_4_SAMPLES Value */ 138 #define MXC_S_QDEC_REVA_CTRL_FILTER_4_SAMPLES (MXC_V_QDEC_REVA_CTRL_FILTER_4_SAMPLES << MXC_F_QDEC_REVA_CTRL_FILTER_POS) /**< CTRL_FILTER_4_SAMPLES Setting */ 139 140 #define MXC_F_QDEC_REVA_CTRL_RST_INDEX_POS 6 /**< CTRL_RST_INDEX Position */ 141 #define MXC_F_QDEC_REVA_CTRL_RST_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_CTRL_RST_INDEX_POS)) /**< CTRL_RST_INDEX Mask */ 142 143 #define MXC_F_QDEC_REVA_CTRL_RST_MAXCNT_POS 7 /**< CTRL_RST_MAXCNT Position */ 144 #define MXC_F_QDEC_REVA_CTRL_RST_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_CTRL_RST_MAXCNT_POS)) /**< CTRL_RST_MAXCNT Mask */ 145 146 #define MXC_F_QDEC_REVA_CTRL_STICKY_POS 8 /**< CTRL_STICKY Position */ 147 #define MXC_F_QDEC_REVA_CTRL_STICKY ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_CTRL_STICKY_POS)) /**< CTRL_STICKY Mask */ 148 149 #define MXC_F_QDEC_REVA_CTRL_PSC_POS 16 /**< CTRL_PSC Position */ 150 #define MXC_F_QDEC_REVA_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_QDEC_REVA_CTRL_PSC_POS)) /**< CTRL_PSC Mask */ 151 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CTRL_PSC_DIV1 Value */ 152 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV1 (MXC_V_QDEC_REVA_CTRL_PSC_DIV1 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV1 Setting */ 153 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CTRL_PSC_DIV2 Value */ 154 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV2 (MXC_V_QDEC_REVA_CTRL_PSC_DIV2 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV2 Setting */ 155 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CTRL_PSC_DIV4 Value */ 156 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV4 (MXC_V_QDEC_REVA_CTRL_PSC_DIV4 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV4 Setting */ 157 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CTRL_PSC_DIV8 Value */ 158 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV8 (MXC_V_QDEC_REVA_CTRL_PSC_DIV8 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV8 Setting */ 159 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CTRL_PSC_DIV16 Value */ 160 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV16 (MXC_V_QDEC_REVA_CTRL_PSC_DIV16 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV16 Setting */ 161 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CTRL_PSC_DIV32 Value */ 162 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV32 (MXC_V_QDEC_REVA_CTRL_PSC_DIV32 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV32 Setting */ 163 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CTRL_PSC_DIV64 Value */ 164 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV64 (MXC_V_QDEC_REVA_CTRL_PSC_DIV64 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV64 Setting */ 165 #define MXC_V_QDEC_REVA_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CTRL_PSC_DIV128 Value */ 166 #define MXC_S_QDEC_REVA_CTRL_PSC_DIV128 (MXC_V_QDEC_REVA_CTRL_PSC_DIV128 << MXC_F_QDEC_REVA_CTRL_PSC_POS) /**< CTRL_PSC_DIV128 Setting */ 167 168 /**@} end of group QDEC_REVA_CTRL_Register */ 169 170 /** 171 * @ingroup qdec_reva_registers 172 * @defgroup QDEC_REVA_INTFL QDEC_REVA_INTFL 173 * @brief Interrupt Flag Register. 174 * @{ 175 */ 176 #define MXC_F_QDEC_REVA_INTFL_INDEX_POS 0 /**< INTFL_INDEX Position */ 177 #define MXC_F_QDEC_REVA_INTFL_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_INDEX_POS)) /**< INTFL_INDEX Mask */ 178 179 #define MXC_F_QDEC_REVA_INTFL_QERR_POS 1 /**< INTFL_QERR Position */ 180 #define MXC_F_QDEC_REVA_INTFL_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_QERR_POS)) /**< INTFL_QERR Mask */ 181 182 #define MXC_F_QDEC_REVA_INTFL_COMPARE_POS 2 /**< INTFL_COMPARE Position */ 183 #define MXC_F_QDEC_REVA_INTFL_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_COMPARE_POS)) /**< INTFL_COMPARE Mask */ 184 185 #define MXC_F_QDEC_REVA_INTFL_MAXCNT_POS 3 /**< INTFL_MAXCNT Position */ 186 #define MXC_F_QDEC_REVA_INTFL_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_MAXCNT_POS)) /**< INTFL_MAXCNT Mask */ 187 188 #define MXC_F_QDEC_REVA_INTFL_CAPTURE_POS 4 /**< INTFL_CAPTURE Position */ 189 #define MXC_F_QDEC_REVA_INTFL_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_CAPTURE_POS)) /**< INTFL_CAPTURE Mask */ 190 191 #define MXC_F_QDEC_REVA_INTFL_DIR_POS 5 /**< INTFL_DIR Position */ 192 #define MXC_F_QDEC_REVA_INTFL_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_DIR_POS)) /**< INTFL_DIR Mask */ 193 194 #define MXC_F_QDEC_REVA_INTFL_MOVE_POS 6 /**< INTFL_MOVE Position */ 195 #define MXC_F_QDEC_REVA_INTFL_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTFL_MOVE_POS)) /**< INTFL_MOVE Mask */ 196 197 /**@} end of group QDEC_REVA_INTFL_Register */ 198 199 /** 200 * @ingroup qdec_reva_registers 201 * @defgroup QDEC_REVA_INTEN QDEC_REVA_INTEN 202 * @brief Interrupt Enable Register. 203 * @{ 204 */ 205 #define MXC_F_QDEC_REVA_INTEN_INDEX_POS 0 /**< INTEN_INDEX Position */ 206 #define MXC_F_QDEC_REVA_INTEN_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_INDEX_POS)) /**< INTEN_INDEX Mask */ 207 208 #define MXC_F_QDEC_REVA_INTEN_QERR_POS 1 /**< INTEN_QERR Position */ 209 #define MXC_F_QDEC_REVA_INTEN_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_QERR_POS)) /**< INTEN_QERR Mask */ 210 211 #define MXC_F_QDEC_REVA_INTEN_COMPARE_POS 2 /**< INTEN_COMPARE Position */ 212 #define MXC_F_QDEC_REVA_INTEN_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_COMPARE_POS)) /**< INTEN_COMPARE Mask */ 213 214 #define MXC_F_QDEC_REVA_INTEN_MAXCNT_POS 3 /**< INTEN_MAXCNT Position */ 215 #define MXC_F_QDEC_REVA_INTEN_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_MAXCNT_POS)) /**< INTEN_MAXCNT Mask */ 216 217 #define MXC_F_QDEC_REVA_INTEN_CAPTURE_POS 4 /**< INTEN_CAPTURE Position */ 218 #define MXC_F_QDEC_REVA_INTEN_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_CAPTURE_POS)) /**< INTEN_CAPTURE Mask */ 219 220 #define MXC_F_QDEC_REVA_INTEN_DIR_POS 5 /**< INTEN_DIR Position */ 221 #define MXC_F_QDEC_REVA_INTEN_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_DIR_POS)) /**< INTEN_DIR Mask */ 222 223 #define MXC_F_QDEC_REVA_INTEN_MOVE_POS 6 /**< INTEN_MOVE Position */ 224 #define MXC_F_QDEC_REVA_INTEN_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_INTEN_MOVE_POS)) /**< INTEN_MOVE Mask */ 225 226 /**@} end of group QDEC_REVA_INTEN_Register */ 227 228 /** 229 * @ingroup qdec_reva_registers 230 * @defgroup QDEC_REVA_MAXCNT QDEC_REVA_MAXCNT 231 * @brief Maximum Count Register. 232 * @{ 233 */ 234 #define MXC_F_QDEC_REVA_MAXCNT_MAXCNT_POS 0 /**< MAXCNT_MAXCNT Position */ 235 #define MXC_F_QDEC_REVA_MAXCNT_MAXCNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_MAXCNT_MAXCNT_POS)) /**< MAXCNT_MAXCNT Mask */ 236 237 /**@} end of group QDEC_REVA_MAXCNT_Register */ 238 239 /** 240 * @ingroup qdec_reva_registers 241 * @defgroup QDEC_REVA_INITIAL QDEC_REVA_INITIAL 242 * @brief Initial Count Register. 243 * @{ 244 */ 245 #define MXC_F_QDEC_REVA_INITIAL_INITIAL_POS 0 /**< INITIAL_INITIAL Position */ 246 #define MXC_F_QDEC_REVA_INITIAL_INITIAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_INITIAL_INITIAL_POS)) /**< INITIAL_INITIAL Mask */ 247 248 /**@} end of group QDEC_REVA_INITIAL_Register */ 249 250 /** 251 * @ingroup qdec_reva_registers 252 * @defgroup QDEC_REVA_COMPARE QDEC_REVA_COMPARE 253 * @brief Compare Register. 254 * @{ 255 */ 256 #define MXC_F_QDEC_REVA_COMPARE_COMPARE_POS 0 /**< COMPARE_COMPARE Position */ 257 #define MXC_F_QDEC_REVA_COMPARE_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_COMPARE_COMPARE_POS)) /**< COMPARE_COMPARE Mask */ 258 259 /**@} end of group QDEC_REVA_COMPARE_Register */ 260 261 /** 262 * @ingroup qdec_reva_registers 263 * @defgroup QDEC_REVA_INDEX QDEC_REVA_INDEX 264 * @brief Index Register. count captured when QEI fired 265 * @{ 266 */ 267 #define MXC_F_QDEC_REVA_INDEX_INDEX_POS 0 /**< INDEX_INDEX Position */ 268 #define MXC_F_QDEC_REVA_INDEX_INDEX ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_INDEX_INDEX_POS)) /**< INDEX_INDEX Mask */ 269 270 /**@} end of group QDEC_REVA_INDEX_Register */ 271 272 /** 273 * @ingroup qdec_reva_registers 274 * @defgroup QDEC_REVA_CAPTURE QDEC_REVA_CAPTURE 275 * @brief Capture Register. counter captured when QES fired 276 * @{ 277 */ 278 #define MXC_F_QDEC_REVA_CAPTURE_CAPTURE_POS 0 /**< CAPTURE_CAPTURE Position */ 279 #define MXC_F_QDEC_REVA_CAPTURE_CAPTURE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_CAPTURE_CAPTURE_POS)) /**< CAPTURE_CAPTURE Mask */ 280 281 /**@} end of group QDEC_REVA_CAPTURE_Register */ 282 283 /** 284 * @ingroup qdec_reva_registers 285 * @defgroup QDEC_REVA_STATUS QDEC_REVA_STATUS 286 * @brief Status Register. 287 * @{ 288 */ 289 #define MXC_F_QDEC_REVA_STATUS_DIR_POS 0 /**< STATUS_DIR Position */ 290 #define MXC_F_QDEC_REVA_STATUS_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_REVA_STATUS_DIR_POS)) /**< STATUS_DIR Mask */ 291 292 /**@} end of group QDEC_REVA_STATUS_Register */ 293 294 /** 295 * @ingroup qdec_reva_registers 296 * @defgroup QDEC_REVA_POSITION QDEC_REVA_POSITION 297 * @brief Count Register. raw counter value 298 * @{ 299 */ 300 #define MXC_F_QDEC_REVA_POSITION_POSITION_POS 0 /**< POSITION_POSITION Position */ 301 #define MXC_F_QDEC_REVA_POSITION_POSITION ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_POSITION_POSITION_POS)) /**< POSITION_POSITION Mask */ 302 303 /**@} end of group QDEC_REVA_POSITION_Register */ 304 305 /** 306 * @ingroup qdec_reva_registers 307 * @defgroup QDEC_REVA_CAPDLY QDEC_REVA_CAPDLY 308 * @brief delay CAPTURE 309 * @{ 310 */ 311 #define MXC_F_QDEC_REVA_CAPDLY_CAPDLY_POS 0 /**< CAPDLY_CAPDLY Position */ 312 #define MXC_F_QDEC_REVA_CAPDLY_CAPDLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_REVA_CAPDLY_CAPDLY_POS)) /**< CAPDLY_CAPDLY Mask */ 313 314 /**@} end of group QDEC_REVA_CAPDLY_Register */ 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif /* _QDEC_REVA_REGS_H_ */ 321
