1 /**
2  * @file    icc_reva_regs.h
3  * @brief   Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
4  */
5 
6 /******************************************************************************
7  *
8  * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9  * Analog Devices, Inc.),
10  * Copyright (C) 2023-2024 Analog Devices, Inc.
11  *
12  * Licensed under the Apache License, Version 2.0 (the "License");
13  * you may not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  *     http://www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an "AS IS" BASIS,
20  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  *
24  ******************************************************************************/
25 
26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
28 
29 /* **** Includes **** */
30 #include <stdint.h>
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #if defined (__ICCARM__)
37   #pragma system_include
38 #endif
39 
40 #if defined (__CC_ARM)
41   #pragma anon_unions
42 #endif
43 /// @cond
44 /*
45     If types are not defined elsewhere (CMSIS) define them here
46 */
47 #ifndef __IO
48 #define __IO volatile
49 #endif
50 #ifndef __I
51 #define __I  volatile const
52 #endif
53 #ifndef __O
54 #define __O  volatile
55 #endif
56 #ifndef __R
57 #define __R  volatile const
58 #endif
59 /// @endcond
60 
61 /* **** Definitions **** */
62 
63 /**
64  * @ingroup     icc_reva
65  * @defgroup    icc_reva_registers ICC_REVA_Registers
66  * @brief       Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
67  * @details Instruction Cache Controller Registers
68  */
69 
70 /**
71  * @ingroup icc_reva_registers
72  * Structure type to access the ICC_REVA Registers.
73  */
74 typedef struct {
75     __I  uint32_t info;                 /**< <tt>\b 0x0000:</tt> ICC_REVA INFO Register */
76     __I  uint32_t sz;                   /**< <tt>\b 0x0004:</tt> ICC_REVA SZ Register */
77     __R  uint32_t rsv_0x8_0xff[62];
78     __IO uint32_t ctrl;                 /**< <tt>\b 0x0100:</tt> ICC_REVA CTRL Register */
79     __R  uint32_t rsv_0x104_0x6ff[383];
80     __IO uint32_t invalidate;           /**< <tt>\b 0x0700:</tt> ICC_REVA INVALIDATE Register */
81 } mxc_icc_reva_regs_t;
82 
83 /* Register offsets for module ICC_REVA */
84 /**
85  * @ingroup    icc_reva_registers
86  * @defgroup   ICC_REVA_Register_Offsets Register Offsets
87  * @brief      ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address.
88  * @{
89  */
90 #define MXC_R_ICC_REVA_INFO                ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0000</tt> */
91 #define MXC_R_ICC_REVA_SZ                  ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0004</tt> */
92 #define MXC_R_ICC_REVA_CTRL                ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0100</tt> */
93 #define MXC_R_ICC_REVA_INVALIDATE          ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0700</tt> */
94 /**@} end of group icc_reva_registers */
95 
96 /**
97  * @ingroup  icc_reva_registers
98  * @defgroup ICC_REVA_INFO ICC_REVA_INFO
99  * @brief    Cache ID Register.
100  * @{
101  */
102 #define MXC_F_ICC_REVA_INFO_RELNUM_POS                 0 /**< INFO_RELNUM Position */
103 #define MXC_F_ICC_REVA_INFO_RELNUM                     ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
104 
105 #define MXC_F_ICC_REVA_INFO_PARTNUM_POS                6 /**< INFO_PARTNUM Position */
106 #define MXC_F_ICC_REVA_INFO_PARTNUM                    ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
107 
108 #define MXC_F_ICC_REVA_INFO_ID_POS                     10 /**< INFO_ID Position */
109 #define MXC_F_ICC_REVA_INFO_ID                         ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */
110 
111 /**@} end of group ICC_REVA_INFO_Register */
112 
113 /**
114  * @ingroup  icc_reva_registers
115  * @defgroup ICC_REVA_SZ ICC_REVA_SZ
116  * @brief    Memory Configuration Register.
117  * @{
118  */
119 #define MXC_F_ICC_REVA_SZ_CCH_POS                      0 /**< SZ_CCH Position */
120 #define MXC_F_ICC_REVA_SZ_CCH                          ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */
121 
122 #define MXC_F_ICC_REVA_SZ_MEM_POS                      16 /**< SZ_MEM Position */
123 #define MXC_F_ICC_REVA_SZ_MEM                          ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */
124 
125 /**@} end of group ICC_REVA_SZ_Register */
126 
127 /**
128  * @ingroup  icc_reva_registers
129  * @defgroup ICC_REVA_CTRL ICC_REVA_CTRL
130  * @brief    Cache Control and Status Register.
131  * @{
132  */
133 #define MXC_F_ICC_REVA_CTRL_EN_POS                     0 /**< CTRL_EN Position */
134 #define MXC_F_ICC_REVA_CTRL_EN                         ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
135 
136 #define MXC_F_ICC_REVA_CTRL_RDY_POS                    16 /**< CTRL_RDY Position */
137 #define MXC_F_ICC_REVA_CTRL_RDY                        ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
138 
139 /**@} end of group ICC_REVA_CTRL_Register */
140 
141 #ifdef __cplusplus
142 }
143 #endif
144 
145 #endif  // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
146 
147