1 /** 2 * @file i2s_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2s_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_I2S_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_I2S_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2s 67 * @defgroup i2s_registers I2S_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. 69 * @details Inter-IC Sound Interface. 70 */ 71 72 /** 73 * @ingroup i2s_registers 74 * Structure type to access the I2S Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0ch0; /**< <tt>\b 0x00:</tt> I2S CTRL0CH0 Register */ 78 __R uint32_t rsv_0x4_0xf[3]; 79 __IO uint32_t ctrl1ch0; /**< <tt>\b 0x10:</tt> I2S CTRL1CH0 Register */ 80 __R uint32_t rsv_0x14_0x1f[3]; 81 __IO uint32_t filtch0; /**< <tt>\b 0x20:</tt> I2S FILTCH0 Register */ 82 __R uint32_t rsv_0x24_0x2f[3]; 83 __IO uint32_t dmach0; /**< <tt>\b 0x30:</tt> I2S DMACH0 Register */ 84 __R uint32_t rsv_0x34_0x3f[3]; 85 __IO uint32_t fifoch0; /**< <tt>\b 0x40:</tt> I2S FIFOCH0 Register */ 86 __R uint32_t rsv_0x44_0x4f[3]; 87 __IO uint32_t intfl; /**< <tt>\b 0x50:</tt> I2S INTFL Register */ 88 __IO uint32_t inten; /**< <tt>\b 0x54:</tt> I2S INTEN Register */ 89 __IO uint32_t extsetup; /**< <tt>\b 0x58:</tt> I2S EXTSETUP Register */ 90 __IO uint32_t wken; /**< <tt>\b 0x5C:</tt> I2S WKEN Register */ 91 __IO uint32_t wkfl; /**< <tt>\b 0x60:</tt> I2S WKFL Register */ 92 } mxc_i2s_regs_t; 93 94 /* Register offsets for module I2S */ 95 /** 96 * @ingroup i2s_registers 97 * @defgroup I2S_Register_Offsets Register Offsets 98 * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: <tt> 0x0010</tt> */ 103 #define MXC_R_I2S_FILTCH0 ((uint32_t)0x00000020UL) /**< Offset from I2S Base Address: <tt> 0x0020</tt> */ 104 #define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: <tt> 0x0030</tt> */ 105 #define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: <tt> 0x0040</tt> */ 106 #define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: <tt> 0x0050</tt> */ 107 #define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: <tt> 0x0054</tt> */ 108 #define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: <tt> 0x0058</tt> */ 109 #define MXC_R_I2S_WKEN ((uint32_t)0x0000005CUL) /**< Offset from I2S Base Address: <tt> 0x005C</tt> */ 110 #define MXC_R_I2S_WKFL ((uint32_t)0x00000060UL) /**< Offset from I2S Base Address: <tt> 0x0060</tt> */ 111 /**@} end of group i2s_registers */ 112 113 /** 114 * @ingroup i2s_registers 115 * @defgroup I2S_CTRL0CH0 I2S_CTRL0CH0 116 * @brief Global mode channel. 117 * @{ 118 */ 119 #define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ 120 #define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ 121 122 #define MXC_F_I2S_CTRL0CH0_PDM_FILT_POS 2 /**< CTRL0CH0_PDM_FILT Position */ 123 #define MXC_F_I2S_CTRL0CH0_PDM_FILT ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_FILT_POS)) /**< CTRL0CH0_PDM_FILT Mask */ 124 125 #define MXC_F_I2S_CTRL0CH0_PDM_EN_POS 3 /**< CTRL0CH0_PDM_EN Position */ 126 #define MXC_F_I2S_CTRL0CH0_PDM_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_EN_POS)) /**< CTRL0CH0_PDM_EN Mask */ 127 128 #define MXC_F_I2S_CTRL0CH0_USEDDR_POS 4 /**< CTRL0CH0_USEDDR Position */ 129 #define MXC_F_I2S_CTRL0CH0_USEDDR ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_USEDDR_POS)) /**< CTRL0CH0_USEDDR Mask */ 130 131 #define MXC_F_I2S_CTRL0CH0_PDM_INV_POS 5 /**< CTRL0CH0_PDM_INV Position */ 132 #define MXC_F_I2S_CTRL0CH0_PDM_INV ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_INV_POS)) /**< CTRL0CH0_PDM_INV Mask */ 133 134 #define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ 135 #define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ 136 137 #define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ 138 #define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ 139 140 #define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ 141 #define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ 142 143 #define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ 144 #define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ 145 146 #define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ 147 #define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ 148 149 #define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ 150 #define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ 151 152 #define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ 153 #define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ 154 155 #define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ 156 #define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ 157 158 #define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ 159 #define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ 160 161 #define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ 162 #define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ 163 164 #define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ 165 #define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ 166 167 #define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */ 168 #define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ 169 170 #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ 171 #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ 172 173 /**@} end of group I2S_CTRL0CH0_Register */ 174 175 /** 176 * @ingroup i2s_registers 177 * @defgroup I2S_CTRL1CH0 I2S_CTRL1CH0 178 * @brief Local channel Setup. 179 * @{ 180 */ 181 #define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ 182 #define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ 183 184 #define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ 185 #define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ 186 187 #define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ 188 #define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ 189 190 #define MXC_F_I2S_CTRL1CH0_EXTCLK_EN_POS 14 /**< CTRL1CH0_EXTCLK_EN Position */ 191 #define MXC_F_I2S_CTRL1CH0_EXTCLK_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EXTCLK_EN_POS)) /**< CTRL1CH0_EXTCLK_EN Mask */ 192 193 #define MXC_F_I2S_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ 194 #define MXC_F_I2S_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ 195 196 #define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ 197 #define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ 198 199 /**@} end of group I2S_CTRL1CH0_Register */ 200 201 /** 202 * @ingroup i2s_registers 203 * @defgroup I2S_DMACH0 I2S_DMACH0 204 * @brief DMA Control. 205 * @{ 206 */ 207 #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ 208 #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ 209 210 #define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ 211 #define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ 212 213 #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ 214 #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ 215 216 #define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ 217 #define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ 218 219 #define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ 220 #define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ 221 222 #define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ 223 #define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ 224 225 /**@} end of group I2S_DMACH0_Register */ 226 227 /** 228 * @ingroup i2s_registers 229 * @defgroup I2S_FIFOCH0 I2S_FIFOCH0 230 * @brief I2S Fifo. 231 * @{ 232 */ 233 #define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ 234 #define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ 235 236 /**@} end of group I2S_FIFOCH0_Register */ 237 238 /** 239 * @ingroup i2s_registers 240 * @defgroup I2S_INTFL I2S_INTFL 241 * @brief ISR Status. 242 * @{ 243 */ 244 #define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ 245 #define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ 246 247 #define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ 248 #define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ 249 250 #define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ 251 #define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ 252 253 #define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ 254 #define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ 255 256 /**@} end of group I2S_INTFL_Register */ 257 258 /** 259 * @ingroup i2s_registers 260 * @defgroup I2S_INTEN I2S_INTEN 261 * @brief Interrupt Enable. 262 * @{ 263 */ 264 #define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ 265 #define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ 266 267 #define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ 268 #define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ 269 270 #define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ 271 #define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ 272 273 #define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ 274 #define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ 275 276 /**@} end of group I2S_INTEN_Register */ 277 278 /** 279 * @ingroup i2s_registers 280 * @defgroup I2S_EXTSETUP I2S_EXTSETUP 281 * @brief Ext Control. 282 * @{ 283 */ 284 #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ 285 #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ 286 287 /**@} end of group I2S_EXTSETUP_Register */ 288 289 #ifdef __cplusplus 290 } 291 #endif 292 293 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_I2S_REGS_H_ 294
