1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_I2C_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_I2C_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c 67 * @defgroup i2c_registers I2C_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_registers 74 * Structure type to access the I2C Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> I2C CTRL0 Register */ 78 __IO uint32_t stat; /**< <tt>\b 0x04:</tt> I2C STAT Register */ 79 __IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */ 80 __IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */ 81 __IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */ 82 __IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */ 83 __IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */ 84 __IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */ 85 __IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */ 86 __IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */ 87 __IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */ 88 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 89 __IO uint32_t mstr_mode; /**< <tt>\b 0x30:</tt> I2C MSTR_MODE Register */ 90 __IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */ 91 __IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */ 92 __R uint32_t rsv_0x3c; 93 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 94 __IO uint32_t slv_addr; /**< <tt>\b 0x44:</tt> I2C SLV_ADDR Register */ 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 96 } mxc_i2c_regs_t; 97 98 /* Register offsets for module I2C */ 99 /** 100 * @ingroup i2c_registers 101 * @defgroup I2C_Register_Offsets Register Offsets 102 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_I2C_STAT ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 112 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 119 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 120 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_I2C_SLV_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ 122 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 123 /**@} end of group i2c_registers */ 124 125 /** 126 * @ingroup i2c_registers 127 * @defgroup I2C_CTRL0 I2C_CTRL0 128 * @brief Control Register 0. 129 * @{ 130 */ 131 #define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */ 132 #define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */ 133 #define MXC_V_I2C_CTRL0_I2CEN_DIS ((uint32_t)0x0UL) /**< CTRL0_I2CEN_DIS Value */ 134 #define MXC_S_I2C_CTRL0_I2CEN_DIS (MXC_V_I2C_CTRL0_I2CEN_DIS << MXC_F_I2C_CTRL0_I2CEN_POS) /**< CTRL0_I2CEN_DIS Setting */ 135 #define MXC_V_I2C_CTRL0_I2CEN_EN ((uint32_t)0x1UL) /**< CTRL0_I2CEN_EN Value */ 136 #define MXC_S_I2C_CTRL0_I2CEN_EN (MXC_V_I2C_CTRL0_I2CEN_EN << MXC_F_I2C_CTRL0_I2CEN_POS) /**< CTRL0_I2CEN_EN Setting */ 137 138 #define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */ 139 #define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */ 140 #define MXC_V_I2C_CTRL0_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL0_MST_SLAVE_MODE Value */ 141 #define MXC_S_I2C_CTRL0_MST_SLAVE_MODE (MXC_V_I2C_CTRL0_MST_SLAVE_MODE << MXC_F_I2C_CTRL0_MST_POS) /**< CTRL0_MST_SLAVE_MODE Setting */ 142 #define MXC_V_I2C_CTRL0_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL0_MST_MASTER_MODE Value */ 143 #define MXC_S_I2C_CTRL0_MST_MASTER_MODE (MXC_V_I2C_CTRL0_MST_MASTER_MODE << MXC_F_I2C_CTRL0_MST_POS) /**< CTRL0_MST_MASTER_MODE Setting */ 144 145 #define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */ 146 #define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */ 147 #define MXC_V_I2C_CTRL0_GCEN_DIS ((uint32_t)0x0UL) /**< CTRL0_GCEN_DIS Value */ 148 #define MXC_S_I2C_CTRL0_GCEN_DIS (MXC_V_I2C_CTRL0_GCEN_DIS << MXC_F_I2C_CTRL0_GCEN_POS) /**< CTRL0_GCEN_DIS Setting */ 149 #define MXC_V_I2C_CTRL0_GCEN_EN ((uint32_t)0x1UL) /**< CTRL0_GCEN_EN Value */ 150 #define MXC_S_I2C_CTRL0_GCEN_EN (MXC_V_I2C_CTRL0_GCEN_EN << MXC_F_I2C_CTRL0_GCEN_POS) /**< CTRL0_GCEN_EN Setting */ 151 152 #define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */ 153 #define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */ 154 #define MXC_V_I2C_CTRL0_IRXM_DIS ((uint32_t)0x0UL) /**< CTRL0_IRXM_DIS Value */ 155 #define MXC_S_I2C_CTRL0_IRXM_DIS (MXC_V_I2C_CTRL0_IRXM_DIS << MXC_F_I2C_CTRL0_IRXM_POS) /**< CTRL0_IRXM_DIS Setting */ 156 #define MXC_V_I2C_CTRL0_IRXM_EN ((uint32_t)0x1UL) /**< CTRL0_IRXM_EN Value */ 157 #define MXC_S_I2C_CTRL0_IRXM_EN (MXC_V_I2C_CTRL0_IRXM_EN << MXC_F_I2C_CTRL0_IRXM_POS) /**< CTRL0_IRXM_EN Setting */ 158 159 #define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */ 160 #define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */ 161 #define MXC_V_I2C_CTRL0_ACK_ACK ((uint32_t)0x0UL) /**< CTRL0_ACK_ACK Value */ 162 #define MXC_S_I2C_CTRL0_ACK_ACK (MXC_V_I2C_CTRL0_ACK_ACK << MXC_F_I2C_CTRL0_ACK_POS) /**< CTRL0_ACK_ACK Setting */ 163 #define MXC_V_I2C_CTRL0_ACK_NACK ((uint32_t)0x1UL) /**< CTRL0_ACK_NACK Value */ 164 #define MXC_S_I2C_CTRL0_ACK_NACK (MXC_V_I2C_CTRL0_ACK_NACK << MXC_F_I2C_CTRL0_ACK_POS) /**< CTRL0_ACK_NACK Setting */ 165 166 #define MXC_F_I2C_CTRL0_SCL_OUT_POS 6 /**< CTRL0_SCL_OUT Position */ 167 #define MXC_F_I2C_CTRL0_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_OUT_POS)) /**< CTRL0_SCL_OUT Mask */ 168 #define MXC_V_I2C_CTRL0_SCL_OUT_LOW ((uint32_t)0x0UL) /**< CTRL0_SCL_OUT_LOW Value */ 169 #define MXC_S_I2C_CTRL0_SCL_OUT_LOW (MXC_V_I2C_CTRL0_SCL_OUT_LOW << MXC_F_I2C_CTRL0_SCL_OUT_POS) /**< CTRL0_SCL_OUT_LOW Setting */ 170 #define MXC_V_I2C_CTRL0_SCL_OUT_HIGH ((uint32_t)0x1UL) /**< CTRL0_SCL_OUT_HIGH Value */ 171 #define MXC_S_I2C_CTRL0_SCL_OUT_HIGH (MXC_V_I2C_CTRL0_SCL_OUT_HIGH << MXC_F_I2C_CTRL0_SCL_OUT_POS) /**< CTRL0_SCL_OUT_HIGH Setting */ 172 173 #define MXC_F_I2C_CTRL0_SDA_OUT_POS 7 /**< CTRL0_SDA_OUT Position */ 174 #define MXC_F_I2C_CTRL0_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_OUT_POS)) /**< CTRL0_SDA_OUT Mask */ 175 #define MXC_V_I2C_CTRL0_SDA_OUT_LOW ((uint32_t)0x0UL) /**< CTRL0_SDA_OUT_LOW Value */ 176 #define MXC_S_I2C_CTRL0_SDA_OUT_LOW (MXC_V_I2C_CTRL0_SDA_OUT_LOW << MXC_F_I2C_CTRL0_SDA_OUT_POS) /**< CTRL0_SDA_OUT_LOW Setting */ 177 #define MXC_V_I2C_CTRL0_SDA_OUT_HIGH ((uint32_t)0x1UL) /**< CTRL0_SDA_OUT_HIGH Value */ 178 #define MXC_S_I2C_CTRL0_SDA_OUT_HIGH (MXC_V_I2C_CTRL0_SDA_OUT_HIGH << MXC_F_I2C_CTRL0_SDA_OUT_POS) /**< CTRL0_SDA_OUT_HIGH Setting */ 179 180 #define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */ 181 #define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */ 182 #define MXC_V_I2C_CTRL0_SCL_LOW ((uint32_t)0x0UL) /**< CTRL0_SCL_LOW Value */ 183 #define MXC_S_I2C_CTRL0_SCL_LOW (MXC_V_I2C_CTRL0_SCL_LOW << MXC_F_I2C_CTRL0_SCL_POS) /**< CTRL0_SCL_LOW Setting */ 184 #define MXC_V_I2C_CTRL0_SCL_HIGH ((uint32_t)0x1UL) /**< CTRL0_SCL_HIGH Value */ 185 #define MXC_S_I2C_CTRL0_SCL_HIGH (MXC_V_I2C_CTRL0_SCL_HIGH << MXC_F_I2C_CTRL0_SCL_POS) /**< CTRL0_SCL_HIGH Setting */ 186 187 #define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */ 188 #define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */ 189 #define MXC_V_I2C_CTRL0_SDA_LOW ((uint32_t)0x0UL) /**< CTRL0_SDA_LOW Value */ 190 #define MXC_S_I2C_CTRL0_SDA_LOW (MXC_V_I2C_CTRL0_SDA_LOW << MXC_F_I2C_CTRL0_SDA_POS) /**< CTRL0_SDA_LOW Setting */ 191 #define MXC_V_I2C_CTRL0_SDA_HIGH ((uint32_t)0x1UL) /**< CTRL0_SDA_HIGH Value */ 192 #define MXC_S_I2C_CTRL0_SDA_HIGH (MXC_V_I2C_CTRL0_SDA_HIGH << MXC_F_I2C_CTRL0_SDA_POS) /**< CTRL0_SDA_HIGH Setting */ 193 194 #define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */ 195 #define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */ 196 #define MXC_V_I2C_CTRL0_SWOE_DIS ((uint32_t)0x0UL) /**< CTRL0_SWOE_DIS Value */ 197 #define MXC_S_I2C_CTRL0_SWOE_DIS (MXC_V_I2C_CTRL0_SWOE_DIS << MXC_F_I2C_CTRL0_SWOE_POS) /**< CTRL0_SWOE_DIS Setting */ 198 #define MXC_V_I2C_CTRL0_SWOE_EN ((uint32_t)0x1UL) /**< CTRL0_SWOE_EN Value */ 199 #define MXC_S_I2C_CTRL0_SWOE_EN (MXC_V_I2C_CTRL0_SWOE_EN << MXC_F_I2C_CTRL0_SWOE_POS) /**< CTRL0_SWOE_EN Setting */ 200 201 #define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */ 202 #define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */ 203 #define MXC_V_I2C_CTRL0_READ_WRITE ((uint32_t)0x0UL) /**< CTRL0_READ_WRITE Value */ 204 #define MXC_S_I2C_CTRL0_READ_WRITE (MXC_V_I2C_CTRL0_READ_WRITE << MXC_F_I2C_CTRL0_READ_POS) /**< CTRL0_READ_WRITE Setting */ 205 #define MXC_V_I2C_CTRL0_READ_READ ((uint32_t)0x1UL) /**< CTRL0_READ_READ Value */ 206 #define MXC_S_I2C_CTRL0_READ_READ (MXC_V_I2C_CTRL0_READ_READ << MXC_F_I2C_CTRL0_READ_POS) /**< CTRL0_READ_READ Setting */ 207 208 #define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */ 209 #define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */ 210 #define MXC_V_I2C_CTRL0_SCL_STRD_EN ((uint32_t)0x0UL) /**< CTRL0_SCL_STRD_EN Value */ 211 #define MXC_S_I2C_CTRL0_SCL_STRD_EN (MXC_V_I2C_CTRL0_SCL_STRD_EN << MXC_F_I2C_CTRL0_SCL_STRD_POS) /**< CTRL0_SCL_STRD_EN Setting */ 212 #define MXC_V_I2C_CTRL0_SCL_STRD_DIS ((uint32_t)0x1UL) /**< CTRL0_SCL_STRD_DIS Value */ 213 #define MXC_S_I2C_CTRL0_SCL_STRD_DIS (MXC_V_I2C_CTRL0_SCL_STRD_DIS << MXC_F_I2C_CTRL0_SCL_STRD_POS) /**< CTRL0_SCL_STRD_DIS Setting */ 214 215 #define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */ 216 #define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */ 217 #define MXC_V_I2C_CTRL0_SCL_PPM_DIS ((uint32_t)0x0UL) /**< CTRL0_SCL_PPM_DIS Value */ 218 #define MXC_S_I2C_CTRL0_SCL_PPM_DIS (MXC_V_I2C_CTRL0_SCL_PPM_DIS << MXC_F_I2C_CTRL0_SCL_PPM_POS) /**< CTRL0_SCL_PPM_DIS Setting */ 219 #define MXC_V_I2C_CTRL0_SCL_PPM_EN ((uint32_t)0x1UL) /**< CTRL0_SCL_PPM_EN Value */ 220 #define MXC_S_I2C_CTRL0_SCL_PPM_EN (MXC_V_I2C_CTRL0_SCL_PPM_EN << MXC_F_I2C_CTRL0_SCL_PPM_POS) /**< CTRL0_SCL_PPM_EN Setting */ 221 222 /**@} end of group I2C_CTRL0_Register */ 223 224 /** 225 * @ingroup i2c_registers 226 * @defgroup I2C_STAT I2C_STAT 227 * @brief Status Register. 228 * @{ 229 */ 230 #define MXC_F_I2C_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 231 #define MXC_F_I2C_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 232 #define MXC_V_I2C_STAT_BUSY_IDLE ((uint32_t)0x0UL) /**< STAT_BUSY_IDLE Value */ 233 #define MXC_S_I2C_STAT_BUSY_IDLE (MXC_V_I2C_STAT_BUSY_IDLE << MXC_F_I2C_STAT_BUSY_POS) /**< STAT_BUSY_IDLE Setting */ 234 #define MXC_V_I2C_STAT_BUSY_BUSY ((uint32_t)0x1UL) /**< STAT_BUSY_BUSY Value */ 235 #define MXC_S_I2C_STAT_BUSY_BUSY (MXC_V_I2C_STAT_BUSY_BUSY << MXC_F_I2C_STAT_BUSY_POS) /**< STAT_BUSY_BUSY Setting */ 236 237 #define MXC_F_I2C_STAT_RXE_POS 1 /**< STAT_RXE Position */ 238 #define MXC_F_I2C_STAT_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STAT_RXE_POS)) /**< STAT_RXE Mask */ 239 #define MXC_V_I2C_STAT_RXE_NOT_EMPTY ((uint32_t)0x0UL) /**< STAT_RXE_NOT_EMPTY Value */ 240 #define MXC_S_I2C_STAT_RXE_NOT_EMPTY (MXC_V_I2C_STAT_RXE_NOT_EMPTY << MXC_F_I2C_STAT_RXE_POS) /**< STAT_RXE_NOT_EMPTY Setting */ 241 #define MXC_V_I2C_STAT_RXE_EMPTY ((uint32_t)0x1UL) /**< STAT_RXE_EMPTY Value */ 242 #define MXC_S_I2C_STAT_RXE_EMPTY (MXC_V_I2C_STAT_RXE_EMPTY << MXC_F_I2C_STAT_RXE_POS) /**< STAT_RXE_EMPTY Setting */ 243 244 #define MXC_F_I2C_STAT_RXF_POS 2 /**< STAT_RXF Position */ 245 #define MXC_F_I2C_STAT_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STAT_RXF_POS)) /**< STAT_RXF Mask */ 246 #define MXC_V_I2C_STAT_RXF_NOT_FULL ((uint32_t)0x0UL) /**< STAT_RXF_NOT_FULL Value */ 247 #define MXC_S_I2C_STAT_RXF_NOT_FULL (MXC_V_I2C_STAT_RXF_NOT_FULL << MXC_F_I2C_STAT_RXF_POS) /**< STAT_RXF_NOT_FULL Setting */ 248 #define MXC_V_I2C_STAT_RXF_FULL ((uint32_t)0x1UL) /**< STAT_RXF_FULL Value */ 249 #define MXC_S_I2C_STAT_RXF_FULL (MXC_V_I2C_STAT_RXF_FULL << MXC_F_I2C_STAT_RXF_POS) /**< STAT_RXF_FULL Setting */ 250 251 #define MXC_F_I2C_STAT_TXE_POS 3 /**< STAT_TXE Position */ 252 #define MXC_F_I2C_STAT_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STAT_TXE_POS)) /**< STAT_TXE Mask */ 253 #define MXC_V_I2C_STAT_TXE_NOT_EMPTY ((uint32_t)0x0UL) /**< STAT_TXE_NOT_EMPTY Value */ 254 #define MXC_S_I2C_STAT_TXE_NOT_EMPTY (MXC_V_I2C_STAT_TXE_NOT_EMPTY << MXC_F_I2C_STAT_TXE_POS) /**< STAT_TXE_NOT_EMPTY Setting */ 255 #define MXC_V_I2C_STAT_TXE_EMPTY ((uint32_t)0x1UL) /**< STAT_TXE_EMPTY Value */ 256 #define MXC_S_I2C_STAT_TXE_EMPTY (MXC_V_I2C_STAT_TXE_EMPTY << MXC_F_I2C_STAT_TXE_POS) /**< STAT_TXE_EMPTY Setting */ 257 258 #define MXC_F_I2C_STAT_TXF_POS 4 /**< STAT_TXF Position */ 259 #define MXC_F_I2C_STAT_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STAT_TXF_POS)) /**< STAT_TXF Mask */ 260 #define MXC_V_I2C_STAT_TXF_NOT_FULL ((uint32_t)0x0UL) /**< STAT_TXF_NOT_FULL Value */ 261 #define MXC_S_I2C_STAT_TXF_NOT_FULL (MXC_V_I2C_STAT_TXF_NOT_FULL << MXC_F_I2C_STAT_TXF_POS) /**< STAT_TXF_NOT_FULL Setting */ 262 #define MXC_V_I2C_STAT_TXF_FULL ((uint32_t)0x1UL) /**< STAT_TXF_FULL Value */ 263 #define MXC_S_I2C_STAT_TXF_FULL (MXC_V_I2C_STAT_TXF_FULL << MXC_F_I2C_STAT_TXF_POS) /**< STAT_TXF_FULL Setting */ 264 265 #define MXC_F_I2C_STAT_CKMD_POS 5 /**< STAT_CKMD Position */ 266 #define MXC_F_I2C_STAT_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STAT_CKMD_POS)) /**< STAT_CKMD Mask */ 267 #define MXC_V_I2C_STAT_CKMD_SCL_NOT_ACTIVE ((uint32_t)0x0UL) /**< STAT_CKMD_SCL_NOT_ACTIVE Value */ 268 #define MXC_S_I2C_STAT_CKMD_SCL_NOT_ACTIVE (MXC_V_I2C_STAT_CKMD_SCL_NOT_ACTIVE << MXC_F_I2C_STAT_CKMD_POS) /**< STAT_CKMD_SCL_NOT_ACTIVE Setting */ 269 #define MXC_V_I2C_STAT_CKMD_SCL_ACTIVE ((uint32_t)0x1UL) /**< STAT_CKMD_SCL_ACTIVE Value */ 270 #define MXC_S_I2C_STAT_CKMD_SCL_ACTIVE (MXC_V_I2C_STAT_CKMD_SCL_ACTIVE << MXC_F_I2C_STAT_CKMD_POS) /**< STAT_CKMD_SCL_ACTIVE Setting */ 271 272 /**@} end of group I2C_STAT_Register */ 273 274 /** 275 * @ingroup i2c_registers 276 * @defgroup I2C_INT_FL0 I2C_INT_FL0 277 * @brief Interrupt Status Register. 278 * @{ 279 */ 280 #define MXC_F_I2C_INT_FL0_DONEI_POS 0 /**< INT_FL0_DONEI Position */ 281 #define MXC_F_I2C_INT_FL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONEI_POS)) /**< INT_FL0_DONEI Mask */ 282 #define MXC_V_I2C_INT_FL0_DONEI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONEI_INACTIVE Value */ 283 #define MXC_S_I2C_INT_FL0_DONEI_INACTIVE (MXC_V_I2C_INT_FL0_DONEI_INACTIVE << MXC_F_I2C_INT_FL0_DONEI_POS) /**< INT_FL0_DONEI_INACTIVE Setting */ 284 #define MXC_V_I2C_INT_FL0_DONEI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONEI_PENDING Value */ 285 #define MXC_S_I2C_INT_FL0_DONEI_PENDING (MXC_V_I2C_INT_FL0_DONEI_PENDING << MXC_F_I2C_INT_FL0_DONEI_POS) /**< INT_FL0_DONEI_PENDING Setting */ 286 287 #define MXC_F_I2C_INT_FL0_IRXMI_POS 1 /**< INT_FL0_IRXMI Position */ 288 #define MXC_F_I2C_INT_FL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_IRXMI_POS)) /**< INT_FL0_IRXMI Mask */ 289 #define MXC_V_I2C_INT_FL0_IRXMI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_IRXMI_INACTIVE Value */ 290 #define MXC_S_I2C_INT_FL0_IRXMI_INACTIVE (MXC_V_I2C_INT_FL0_IRXMI_INACTIVE << MXC_F_I2C_INT_FL0_IRXMI_POS) /**< INT_FL0_IRXMI_INACTIVE Setting */ 291 #define MXC_V_I2C_INT_FL0_IRXMI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_IRXMI_PENDING Value */ 292 #define MXC_S_I2C_INT_FL0_IRXMI_PENDING (MXC_V_I2C_INT_FL0_IRXMI_PENDING << MXC_F_I2C_INT_FL0_IRXMI_POS) /**< INT_FL0_IRXMI_PENDING Setting */ 293 294 #define MXC_F_I2C_INT_FL0_GCI_POS 2 /**< INT_FL0_GCI Position */ 295 #define MXC_F_I2C_INT_FL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GCI_POS)) /**< INT_FL0_GCI Mask */ 296 #define MXC_V_I2C_INT_FL0_GCI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GCI_INACTIVE Value */ 297 #define MXC_S_I2C_INT_FL0_GCI_INACTIVE (MXC_V_I2C_INT_FL0_GCI_INACTIVE << MXC_F_I2C_INT_FL0_GCI_POS) /**< INT_FL0_GCI_INACTIVE Setting */ 298 #define MXC_V_I2C_INT_FL0_GCI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GCI_PENDING Value */ 299 #define MXC_S_I2C_INT_FL0_GCI_PENDING (MXC_V_I2C_INT_FL0_GCI_PENDING << MXC_F_I2C_INT_FL0_GCI_POS) /**< INT_FL0_GCI_PENDING Setting */ 300 301 #define MXC_F_I2C_INT_FL0_AMI_POS 3 /**< INT_FL0_AMI Position */ 302 #define MXC_F_I2C_INT_FL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_AMI_POS)) /**< INT_FL0_AMI Mask */ 303 #define MXC_V_I2C_INT_FL0_AMI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_AMI_INACTIVE Value */ 304 #define MXC_S_I2C_INT_FL0_AMI_INACTIVE (MXC_V_I2C_INT_FL0_AMI_INACTIVE << MXC_F_I2C_INT_FL0_AMI_POS) /**< INT_FL0_AMI_INACTIVE Setting */ 305 #define MXC_V_I2C_INT_FL0_AMI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_AMI_PENDING Value */ 306 #define MXC_S_I2C_INT_FL0_AMI_PENDING (MXC_V_I2C_INT_FL0_AMI_PENDING << MXC_F_I2C_INT_FL0_AMI_POS) /**< INT_FL0_AMI_PENDING Setting */ 307 308 #define MXC_F_I2C_INT_FL0_RXTHI_POS 4 /**< INT_FL0_RXTHI Position */ 309 #define MXC_F_I2C_INT_FL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RXTHI_POS)) /**< INT_FL0_RXTHI Mask */ 310 #define MXC_V_I2C_INT_FL0_RXTHI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RXTHI_INACTIVE Value */ 311 #define MXC_S_I2C_INT_FL0_RXTHI_INACTIVE (MXC_V_I2C_INT_FL0_RXTHI_INACTIVE << MXC_F_I2C_INT_FL0_RXTHI_POS) /**< INT_FL0_RXTHI_INACTIVE Setting */ 312 #define MXC_V_I2C_INT_FL0_RXTHI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RXTHI_PENDING Value */ 313 #define MXC_S_I2C_INT_FL0_RXTHI_PENDING (MXC_V_I2C_INT_FL0_RXTHI_PENDING << MXC_F_I2C_INT_FL0_RXTHI_POS) /**< INT_FL0_RXTHI_PENDING Setting */ 314 315 #define MXC_F_I2C_INT_FL0_TXTHI_POS 5 /**< INT_FL0_TXTHI Position */ 316 #define MXC_F_I2C_INT_FL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TXTHI_POS)) /**< INT_FL0_TXTHI Mask */ 317 #define MXC_V_I2C_INT_FL0_TXTHI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TXTHI_INACTIVE Value */ 318 #define MXC_S_I2C_INT_FL0_TXTHI_INACTIVE (MXC_V_I2C_INT_FL0_TXTHI_INACTIVE << MXC_F_I2C_INT_FL0_TXTHI_POS) /**< INT_FL0_TXTHI_INACTIVE Setting */ 319 #define MXC_V_I2C_INT_FL0_TXTHI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TXTHI_PENDING Value */ 320 #define MXC_S_I2C_INT_FL0_TXTHI_PENDING (MXC_V_I2C_INT_FL0_TXTHI_PENDING << MXC_F_I2C_INT_FL0_TXTHI_POS) /**< INT_FL0_TXTHI_PENDING Setting */ 321 322 #define MXC_F_I2C_INT_FL0_STOPI_POS 6 /**< INT_FL0_STOPI Position */ 323 #define MXC_F_I2C_INT_FL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOPI_POS)) /**< INT_FL0_STOPI Mask */ 324 #define MXC_V_I2C_INT_FL0_STOPI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOPI_INACTIVE Value */ 325 #define MXC_S_I2C_INT_FL0_STOPI_INACTIVE (MXC_V_I2C_INT_FL0_STOPI_INACTIVE << MXC_F_I2C_INT_FL0_STOPI_POS) /**< INT_FL0_STOPI_INACTIVE Setting */ 326 #define MXC_V_I2C_INT_FL0_STOPI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOPI_PENDING Value */ 327 #define MXC_S_I2C_INT_FL0_STOPI_PENDING (MXC_V_I2C_INT_FL0_STOPI_PENDING << MXC_F_I2C_INT_FL0_STOPI_POS) /**< INT_FL0_STOPI_PENDING Setting */ 328 329 #define MXC_F_I2C_INT_FL0_ADRACKI_POS 7 /**< INT_FL0_ADRACKI Position */ 330 #define MXC_F_I2C_INT_FL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADRACKI_POS)) /**< INT_FL0_ADRACKI Mask */ 331 #define MXC_V_I2C_INT_FL0_ADRACKI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADRACKI_INACTIVE Value */ 332 #define MXC_S_I2C_INT_FL0_ADRACKI_INACTIVE (MXC_V_I2C_INT_FL0_ADRACKI_INACTIVE << MXC_F_I2C_INT_FL0_ADRACKI_POS) /**< INT_FL0_ADRACKI_INACTIVE Setting */ 333 #define MXC_V_I2C_INT_FL0_ADRACKI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADRACKI_PENDING Value */ 334 #define MXC_S_I2C_INT_FL0_ADRACKI_PENDING (MXC_V_I2C_INT_FL0_ADRACKI_PENDING << MXC_F_I2C_INT_FL0_ADRACKI_POS) /**< INT_FL0_ADRACKI_PENDING Setting */ 335 336 #define MXC_F_I2C_INT_FL0_ARBERI_POS 8 /**< INT_FL0_ARBERI Position */ 337 #define MXC_F_I2C_INT_FL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARBERI_POS)) /**< INT_FL0_ARBERI Mask */ 338 #define MXC_V_I2C_INT_FL0_ARBERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARBERI_INACTIVE Value */ 339 #define MXC_S_I2C_INT_FL0_ARBERI_INACTIVE (MXC_V_I2C_INT_FL0_ARBERI_INACTIVE << MXC_F_I2C_INT_FL0_ARBERI_POS) /**< INT_FL0_ARBERI_INACTIVE Setting */ 340 #define MXC_V_I2C_INT_FL0_ARBERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARBERI_PENDING Value */ 341 #define MXC_S_I2C_INT_FL0_ARBERI_PENDING (MXC_V_I2C_INT_FL0_ARBERI_PENDING << MXC_F_I2C_INT_FL0_ARBERI_POS) /**< INT_FL0_ARBERI_PENDING Setting */ 342 343 #define MXC_F_I2C_INT_FL0_TOERI_POS 9 /**< INT_FL0_TOERI Position */ 344 #define MXC_F_I2C_INT_FL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TOERI_POS)) /**< INT_FL0_TOERI Mask */ 345 #define MXC_V_I2C_INT_FL0_TOERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TOERI_INACTIVE Value */ 346 #define MXC_S_I2C_INT_FL0_TOERI_INACTIVE (MXC_V_I2C_INT_FL0_TOERI_INACTIVE << MXC_F_I2C_INT_FL0_TOERI_POS) /**< INT_FL0_TOERI_INACTIVE Setting */ 347 #define MXC_V_I2C_INT_FL0_TOERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TOERI_PENDING Value */ 348 #define MXC_S_I2C_INT_FL0_TOERI_PENDING (MXC_V_I2C_INT_FL0_TOERI_PENDING << MXC_F_I2C_INT_FL0_TOERI_POS) /**< INT_FL0_TOERI_PENDING Setting */ 349 350 #define MXC_F_I2C_INT_FL0_ADRERI_POS 10 /**< INT_FL0_ADRERI Position */ 351 #define MXC_F_I2C_INT_FL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADRERI_POS)) /**< INT_FL0_ADRERI Mask */ 352 #define MXC_V_I2C_INT_FL0_ADRERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADRERI_INACTIVE Value */ 353 #define MXC_S_I2C_INT_FL0_ADRERI_INACTIVE (MXC_V_I2C_INT_FL0_ADRERI_INACTIVE << MXC_F_I2C_INT_FL0_ADRERI_POS) /**< INT_FL0_ADRERI_INACTIVE Setting */ 354 #define MXC_V_I2C_INT_FL0_ADRERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADRERI_PENDING Value */ 355 #define MXC_S_I2C_INT_FL0_ADRERI_PENDING (MXC_V_I2C_INT_FL0_ADRERI_PENDING << MXC_F_I2C_INT_FL0_ADRERI_POS) /**< INT_FL0_ADRERI_PENDING Setting */ 356 357 #define MXC_F_I2C_INT_FL0_DATAERI_POS 11 /**< INT_FL0_DATAERI Position */ 358 #define MXC_F_I2C_INT_FL0_DATAERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATAERI_POS)) /**< INT_FL0_DATAERI Mask */ 359 #define MXC_V_I2C_INT_FL0_DATAERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATAERI_INACTIVE Value */ 360 #define MXC_S_I2C_INT_FL0_DATAERI_INACTIVE (MXC_V_I2C_INT_FL0_DATAERI_INACTIVE << MXC_F_I2C_INT_FL0_DATAERI_POS) /**< INT_FL0_DATAERI_INACTIVE Setting */ 361 #define MXC_V_I2C_INT_FL0_DATAERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATAERI_PENDING Value */ 362 #define MXC_S_I2C_INT_FL0_DATAERI_PENDING (MXC_V_I2C_INT_FL0_DATAERI_PENDING << MXC_F_I2C_INT_FL0_DATAERI_POS) /**< INT_FL0_DATAERI_PENDING Setting */ 363 364 #define MXC_F_I2C_INT_FL0_DNRERI_POS 12 /**< INT_FL0_DNRERI Position */ 365 #define MXC_F_I2C_INT_FL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DNRERI_POS)) /**< INT_FL0_DNRERI Mask */ 366 #define MXC_V_I2C_INT_FL0_DNRERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DNRERI_INACTIVE Value */ 367 #define MXC_S_I2C_INT_FL0_DNRERI_INACTIVE (MXC_V_I2C_INT_FL0_DNRERI_INACTIVE << MXC_F_I2C_INT_FL0_DNRERI_POS) /**< INT_FL0_DNRERI_INACTIVE Setting */ 368 #define MXC_V_I2C_INT_FL0_DNRERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DNRERI_PENDING Value */ 369 #define MXC_S_I2C_INT_FL0_DNRERI_PENDING (MXC_V_I2C_INT_FL0_DNRERI_PENDING << MXC_F_I2C_INT_FL0_DNRERI_POS) /**< INT_FL0_DNRERI_PENDING Setting */ 370 371 #define MXC_F_I2C_INT_FL0_STRTERI_POS 13 /**< INT_FL0_STRTERI Position */ 372 #define MXC_F_I2C_INT_FL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STRTERI_POS)) /**< INT_FL0_STRTERI Mask */ 373 #define MXC_V_I2C_INT_FL0_STRTERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STRTERI_INACTIVE Value */ 374 #define MXC_S_I2C_INT_FL0_STRTERI_INACTIVE (MXC_V_I2C_INT_FL0_STRTERI_INACTIVE << MXC_F_I2C_INT_FL0_STRTERI_POS) /**< INT_FL0_STRTERI_INACTIVE Setting */ 375 #define MXC_V_I2C_INT_FL0_STRTERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STRTERI_PENDING Value */ 376 #define MXC_S_I2C_INT_FL0_STRTERI_PENDING (MXC_V_I2C_INT_FL0_STRTERI_PENDING << MXC_F_I2C_INT_FL0_STRTERI_POS) /**< INT_FL0_STRTERI_PENDING Setting */ 377 378 #define MXC_F_I2C_INT_FL0_STOPERI_POS 14 /**< INT_FL0_STOPERI Position */ 379 #define MXC_F_I2C_INT_FL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOPERI_POS)) /**< INT_FL0_STOPERI Mask */ 380 #define MXC_V_I2C_INT_FL0_STOPERI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOPERI_INACTIVE Value */ 381 #define MXC_S_I2C_INT_FL0_STOPERI_INACTIVE (MXC_V_I2C_INT_FL0_STOPERI_INACTIVE << MXC_F_I2C_INT_FL0_STOPERI_POS) /**< INT_FL0_STOPERI_INACTIVE Setting */ 382 #define MXC_V_I2C_INT_FL0_STOPERI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOPERI_PENDING Value */ 383 #define MXC_S_I2C_INT_FL0_STOPERI_PENDING (MXC_V_I2C_INT_FL0_STOPERI_PENDING << MXC_F_I2C_INT_FL0_STOPERI_POS) /**< INT_FL0_STOPERI_PENDING Setting */ 384 385 #define MXC_F_I2C_INT_FL0_TXLOI_POS 15 /**< INT_FL0_TXLOI Position */ 386 #define MXC_F_I2C_INT_FL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TXLOI_POS)) /**< INT_FL0_TXLOI Mask */ 387 #define MXC_V_I2C_INT_FL0_TXLOI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TXLOI_INACTIVE Value */ 388 #define MXC_S_I2C_INT_FL0_TXLOI_INACTIVE (MXC_V_I2C_INT_FL0_TXLOI_INACTIVE << MXC_F_I2C_INT_FL0_TXLOI_POS) /**< INT_FL0_TXLOI_INACTIVE Setting */ 389 #define MXC_V_I2C_INT_FL0_TXLOI_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TXLOI_PENDING Value */ 390 #define MXC_S_I2C_INT_FL0_TXLOI_PENDING (MXC_V_I2C_INT_FL0_TXLOI_PENDING << MXC_F_I2C_INT_FL0_TXLOI_POS) /**< INT_FL0_TXLOI_PENDING Setting */ 391 392 /**@} end of group I2C_INT_FL0_Register */ 393 394 /** 395 * @ingroup i2c_registers 396 * @defgroup I2C_INT_EN0 I2C_INT_EN0 397 * @brief Interrupt Enable Register. 398 * @{ 399 */ 400 #define MXC_F_I2C_INT_EN0_DONEIE_POS 0 /**< INT_EN0_DONEIE Position */ 401 #define MXC_F_I2C_INT_EN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONEIE_POS)) /**< INT_EN0_DONEIE Mask */ 402 #define MXC_V_I2C_INT_EN0_DONEIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONEIE_DIS Value */ 403 #define MXC_S_I2C_INT_EN0_DONEIE_DIS (MXC_V_I2C_INT_EN0_DONEIE_DIS << MXC_F_I2C_INT_EN0_DONEIE_POS) /**< INT_EN0_DONEIE_DIS Setting */ 404 #define MXC_V_I2C_INT_EN0_DONEIE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONEIE_EN Value */ 405 #define MXC_S_I2C_INT_EN0_DONEIE_EN (MXC_V_I2C_INT_EN0_DONEIE_EN << MXC_F_I2C_INT_EN0_DONEIE_POS) /**< INT_EN0_DONEIE_EN Setting */ 406 407 #define MXC_F_I2C_INT_EN0_IRXMIE_POS 1 /**< INT_EN0_IRXMIE Position */ 408 #define MXC_F_I2C_INT_EN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_IRXMIE_POS)) /**< INT_EN0_IRXMIE Mask */ 409 #define MXC_V_I2C_INT_EN0_IRXMIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_IRXMIE_DIS Value */ 410 #define MXC_S_I2C_INT_EN0_IRXMIE_DIS (MXC_V_I2C_INT_EN0_IRXMIE_DIS << MXC_F_I2C_INT_EN0_IRXMIE_POS) /**< INT_EN0_IRXMIE_DIS Setting */ 411 #define MXC_V_I2C_INT_EN0_IRXMIE_EN ((uint32_t)0x1UL) /**< INT_EN0_IRXMIE_EN Value */ 412 #define MXC_S_I2C_INT_EN0_IRXMIE_EN (MXC_V_I2C_INT_EN0_IRXMIE_EN << MXC_F_I2C_INT_EN0_IRXMIE_POS) /**< INT_EN0_IRXMIE_EN Setting */ 413 414 #define MXC_F_I2C_INT_EN0_GCIE_POS 2 /**< INT_EN0_GCIE Position */ 415 #define MXC_F_I2C_INT_EN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GCIE_POS)) /**< INT_EN0_GCIE Mask */ 416 #define MXC_V_I2C_INT_EN0_GCIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_GCIE_DIS Value */ 417 #define MXC_S_I2C_INT_EN0_GCIE_DIS (MXC_V_I2C_INT_EN0_GCIE_DIS << MXC_F_I2C_INT_EN0_GCIE_POS) /**< INT_EN0_GCIE_DIS Setting */ 418 #define MXC_V_I2C_INT_EN0_GCIE_EN ((uint32_t)0x1UL) /**< INT_EN0_GCIE_EN Value */ 419 #define MXC_S_I2C_INT_EN0_GCIE_EN (MXC_V_I2C_INT_EN0_GCIE_EN << MXC_F_I2C_INT_EN0_GCIE_POS) /**< INT_EN0_GCIE_EN Setting */ 420 421 #define MXC_F_I2C_INT_EN0_AMIE_POS 3 /**< INT_EN0_AMIE Position */ 422 #define MXC_F_I2C_INT_EN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_AMIE_POS)) /**< INT_EN0_AMIE Mask */ 423 #define MXC_V_I2C_INT_EN0_AMIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_AMIE_DIS Value */ 424 #define MXC_S_I2C_INT_EN0_AMIE_DIS (MXC_V_I2C_INT_EN0_AMIE_DIS << MXC_F_I2C_INT_EN0_AMIE_POS) /**< INT_EN0_AMIE_DIS Setting */ 425 #define MXC_V_I2C_INT_EN0_AMIE_EN ((uint32_t)0x1UL) /**< INT_EN0_AMIE_EN Value */ 426 #define MXC_S_I2C_INT_EN0_AMIE_EN (MXC_V_I2C_INT_EN0_AMIE_EN << MXC_F_I2C_INT_EN0_AMIE_POS) /**< INT_EN0_AMIE_EN Setting */ 427 428 #define MXC_F_I2C_INT_EN0_RXTHIE_POS 4 /**< INT_EN0_RXTHIE Position */ 429 #define MXC_F_I2C_INT_EN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RXTHIE_POS)) /**< INT_EN0_RXTHIE Mask */ 430 #define MXC_V_I2C_INT_EN0_RXTHIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RXTHIE_DIS Value */ 431 #define MXC_S_I2C_INT_EN0_RXTHIE_DIS (MXC_V_I2C_INT_EN0_RXTHIE_DIS << MXC_F_I2C_INT_EN0_RXTHIE_POS) /**< INT_EN0_RXTHIE_DIS Setting */ 432 #define MXC_V_I2C_INT_EN0_RXTHIE_EN ((uint32_t)0x1UL) /**< INT_EN0_RXTHIE_EN Value */ 433 #define MXC_S_I2C_INT_EN0_RXTHIE_EN (MXC_V_I2C_INT_EN0_RXTHIE_EN << MXC_F_I2C_INT_EN0_RXTHIE_POS) /**< INT_EN0_RXTHIE_EN Setting */ 434 435 #define MXC_F_I2C_INT_EN0_TXTHIE_POS 5 /**< INT_EN0_TXTHIE Position */ 436 #define MXC_F_I2C_INT_EN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TXTHIE_POS)) /**< INT_EN0_TXTHIE Mask */ 437 #define MXC_V_I2C_INT_EN0_TXTHIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_TXTHIE_DIS Value */ 438 #define MXC_S_I2C_INT_EN0_TXTHIE_DIS (MXC_V_I2C_INT_EN0_TXTHIE_DIS << MXC_F_I2C_INT_EN0_TXTHIE_POS) /**< INT_EN0_TXTHIE_DIS Setting */ 439 #define MXC_V_I2C_INT_EN0_TXTHIE_EN ((uint32_t)0x1UL) /**< INT_EN0_TXTHIE_EN Value */ 440 #define MXC_S_I2C_INT_EN0_TXTHIE_EN (MXC_V_I2C_INT_EN0_TXTHIE_EN << MXC_F_I2C_INT_EN0_TXTHIE_POS) /**< INT_EN0_TXTHIE_EN Setting */ 441 442 #define MXC_F_I2C_INT_EN0_STOPIE_POS 6 /**< INT_EN0_STOPIE Position */ 443 #define MXC_F_I2C_INT_EN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOPIE_POS)) /**< INT_EN0_STOPIE Mask */ 444 #define MXC_V_I2C_INT_EN0_STOPIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOPIE_DIS Value */ 445 #define MXC_S_I2C_INT_EN0_STOPIE_DIS (MXC_V_I2C_INT_EN0_STOPIE_DIS << MXC_F_I2C_INT_EN0_STOPIE_POS) /**< INT_EN0_STOPIE_DIS Setting */ 446 #define MXC_V_I2C_INT_EN0_STOPIE_EN ((uint32_t)0x1UL) /**< INT_EN0_STOPIE_EN Value */ 447 #define MXC_S_I2C_INT_EN0_STOPIE_EN (MXC_V_I2C_INT_EN0_STOPIE_EN << MXC_F_I2C_INT_EN0_STOPIE_POS) /**< INT_EN0_STOPIE_EN Setting */ 448 449 #define MXC_F_I2C_INT_EN0_ADRACKIE_POS 7 /**< INT_EN0_ADRACKIE Position */ 450 #define MXC_F_I2C_INT_EN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADRACKIE_POS)) /**< INT_EN0_ADRACKIE Mask */ 451 #define MXC_V_I2C_INT_EN0_ADRACKIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADRACKIE_DIS Value */ 452 #define MXC_S_I2C_INT_EN0_ADRACKIE_DIS (MXC_V_I2C_INT_EN0_ADRACKIE_DIS << MXC_F_I2C_INT_EN0_ADRACKIE_POS) /**< INT_EN0_ADRACKIE_DIS Setting */ 453 #define MXC_V_I2C_INT_EN0_ADRACKIE_EN ((uint32_t)0x1UL) /**< INT_EN0_ADRACKIE_EN Value */ 454 #define MXC_S_I2C_INT_EN0_ADRACKIE_EN (MXC_V_I2C_INT_EN0_ADRACKIE_EN << MXC_F_I2C_INT_EN0_ADRACKIE_POS) /**< INT_EN0_ADRACKIE_EN Setting */ 455 456 #define MXC_F_I2C_INT_EN0_ARBERIE_POS 8 /**< INT_EN0_ARBERIE Position */ 457 #define MXC_F_I2C_INT_EN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARBERIE_POS)) /**< INT_EN0_ARBERIE Mask */ 458 #define MXC_V_I2C_INT_EN0_ARBERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARBERIE_DIS Value */ 459 #define MXC_S_I2C_INT_EN0_ARBERIE_DIS (MXC_V_I2C_INT_EN0_ARBERIE_DIS << MXC_F_I2C_INT_EN0_ARBERIE_POS) /**< INT_EN0_ARBERIE_DIS Setting */ 460 #define MXC_V_I2C_INT_EN0_ARBERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_ARBERIE_EN Value */ 461 #define MXC_S_I2C_INT_EN0_ARBERIE_EN (MXC_V_I2C_INT_EN0_ARBERIE_EN << MXC_F_I2C_INT_EN0_ARBERIE_POS) /**< INT_EN0_ARBERIE_EN Setting */ 462 463 #define MXC_F_I2C_INT_EN0_TOERIE_POS 9 /**< INT_EN0_TOERIE Position */ 464 #define MXC_F_I2C_INT_EN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TOERIE_POS)) /**< INT_EN0_TOERIE Mask */ 465 #define MXC_V_I2C_INT_EN0_TOERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_TOERIE_DIS Value */ 466 #define MXC_S_I2C_INT_EN0_TOERIE_DIS (MXC_V_I2C_INT_EN0_TOERIE_DIS << MXC_F_I2C_INT_EN0_TOERIE_POS) /**< INT_EN0_TOERIE_DIS Setting */ 467 #define MXC_V_I2C_INT_EN0_TOERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_TOERIE_EN Value */ 468 #define MXC_S_I2C_INT_EN0_TOERIE_EN (MXC_V_I2C_INT_EN0_TOERIE_EN << MXC_F_I2C_INT_EN0_TOERIE_POS) /**< INT_EN0_TOERIE_EN Setting */ 469 470 #define MXC_F_I2C_INT_EN0_ADRERIE_POS 10 /**< INT_EN0_ADRERIE Position */ 471 #define MXC_F_I2C_INT_EN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADRERIE_POS)) /**< INT_EN0_ADRERIE Mask */ 472 #define MXC_V_I2C_INT_EN0_ADRERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADRERIE_DIS Value */ 473 #define MXC_S_I2C_INT_EN0_ADRERIE_DIS (MXC_V_I2C_INT_EN0_ADRERIE_DIS << MXC_F_I2C_INT_EN0_ADRERIE_POS) /**< INT_EN0_ADRERIE_DIS Setting */ 474 #define MXC_V_I2C_INT_EN0_ADRERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_ADRERIE_EN Value */ 475 #define MXC_S_I2C_INT_EN0_ADRERIE_EN (MXC_V_I2C_INT_EN0_ADRERIE_EN << MXC_F_I2C_INT_EN0_ADRERIE_POS) /**< INT_EN0_ADRERIE_EN Setting */ 476 477 #define MXC_F_I2C_INT_EN0_DATAERIE_POS 11 /**< INT_EN0_DATAERIE Position */ 478 #define MXC_F_I2C_INT_EN0_DATAERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATAERIE_POS)) /**< INT_EN0_DATAERIE Mask */ 479 #define MXC_V_I2C_INT_EN0_DATAERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATAERIE_DIS Value */ 480 #define MXC_S_I2C_INT_EN0_DATAERIE_DIS (MXC_V_I2C_INT_EN0_DATAERIE_DIS << MXC_F_I2C_INT_EN0_DATAERIE_POS) /**< INT_EN0_DATAERIE_DIS Setting */ 481 #define MXC_V_I2C_INT_EN0_DATAERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_DATAERIE_EN Value */ 482 #define MXC_S_I2C_INT_EN0_DATAERIE_EN (MXC_V_I2C_INT_EN0_DATAERIE_EN << MXC_F_I2C_INT_EN0_DATAERIE_POS) /**< INT_EN0_DATAERIE_EN Setting */ 483 484 #define MXC_F_I2C_INT_EN0_DNRERIE_POS 12 /**< INT_EN0_DNRERIE Position */ 485 #define MXC_F_I2C_INT_EN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DNRERIE_POS)) /**< INT_EN0_DNRERIE Mask */ 486 #define MXC_V_I2C_INT_EN0_DNRERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DNRERIE_DIS Value */ 487 #define MXC_S_I2C_INT_EN0_DNRERIE_DIS (MXC_V_I2C_INT_EN0_DNRERIE_DIS << MXC_F_I2C_INT_EN0_DNRERIE_POS) /**< INT_EN0_DNRERIE_DIS Setting */ 488 #define MXC_V_I2C_INT_EN0_DNRERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_DNRERIE_EN Value */ 489 #define MXC_S_I2C_INT_EN0_DNRERIE_EN (MXC_V_I2C_INT_EN0_DNRERIE_EN << MXC_F_I2C_INT_EN0_DNRERIE_POS) /**< INT_EN0_DNRERIE_EN Setting */ 490 491 #define MXC_F_I2C_INT_EN0_STRTERIE_POS 13 /**< INT_EN0_STRTERIE Position */ 492 #define MXC_F_I2C_INT_EN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STRTERIE_POS)) /**< INT_EN0_STRTERIE Mask */ 493 #define MXC_V_I2C_INT_EN0_STRTERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_STRTERIE_DIS Value */ 494 #define MXC_S_I2C_INT_EN0_STRTERIE_DIS (MXC_V_I2C_INT_EN0_STRTERIE_DIS << MXC_F_I2C_INT_EN0_STRTERIE_POS) /**< INT_EN0_STRTERIE_DIS Setting */ 495 #define MXC_V_I2C_INT_EN0_STRTERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_STRTERIE_EN Value */ 496 #define MXC_S_I2C_INT_EN0_STRTERIE_EN (MXC_V_I2C_INT_EN0_STRTERIE_EN << MXC_F_I2C_INT_EN0_STRTERIE_POS) /**< INT_EN0_STRTERIE_EN Setting */ 497 498 #define MXC_F_I2C_INT_EN0_STOPERIE_POS 14 /**< INT_EN0_STOPERIE Position */ 499 #define MXC_F_I2C_INT_EN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOPERIE_POS)) /**< INT_EN0_STOPERIE Mask */ 500 #define MXC_V_I2C_INT_EN0_STOPERIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOPERIE_DIS Value */ 501 #define MXC_S_I2C_INT_EN0_STOPERIE_DIS (MXC_V_I2C_INT_EN0_STOPERIE_DIS << MXC_F_I2C_INT_EN0_STOPERIE_POS) /**< INT_EN0_STOPERIE_DIS Setting */ 502 #define MXC_V_I2C_INT_EN0_STOPERIE_EN ((uint32_t)0x1UL) /**< INT_EN0_STOPERIE_EN Value */ 503 #define MXC_S_I2C_INT_EN0_STOPERIE_EN (MXC_V_I2C_INT_EN0_STOPERIE_EN << MXC_F_I2C_INT_EN0_STOPERIE_POS) /**< INT_EN0_STOPERIE_EN Setting */ 504 505 #define MXC_F_I2C_INT_EN0_TXLOIE_POS 15 /**< INT_EN0_TXLOIE Position */ 506 #define MXC_F_I2C_INT_EN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TXLOIE_POS)) /**< INT_EN0_TXLOIE Mask */ 507 #define MXC_V_I2C_INT_EN0_TXLOIE_DIS ((uint32_t)0x0UL) /**< INT_EN0_TXLOIE_DIS Value */ 508 #define MXC_S_I2C_INT_EN0_TXLOIE_DIS (MXC_V_I2C_INT_EN0_TXLOIE_DIS << MXC_F_I2C_INT_EN0_TXLOIE_POS) /**< INT_EN0_TXLOIE_DIS Setting */ 509 #define MXC_V_I2C_INT_EN0_TXLOIE_EN ((uint32_t)0x1UL) /**< INT_EN0_TXLOIE_EN Value */ 510 #define MXC_S_I2C_INT_EN0_TXLOIE_EN (MXC_V_I2C_INT_EN0_TXLOIE_EN << MXC_F_I2C_INT_EN0_TXLOIE_POS) /**< INT_EN0_TXLOIE_EN Setting */ 511 512 /**@} end of group I2C_INT_EN0_Register */ 513 514 /** 515 * @ingroup i2c_registers 516 * @defgroup I2C_INT_FL1 I2C_INT_FL1 517 * @brief Interrupt Status Register 1. 518 * @{ 519 */ 520 #define MXC_F_I2C_INT_FL1_RXOFI_POS 0 /**< INT_FL1_RXOFI Position */ 521 #define MXC_F_I2C_INT_FL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RXOFI_POS)) /**< INT_FL1_RXOFI Mask */ 522 #define MXC_V_I2C_INT_FL1_RXOFI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RXOFI_INACTIVE Value */ 523 #define MXC_S_I2C_INT_FL1_RXOFI_INACTIVE (MXC_V_I2C_INT_FL1_RXOFI_INACTIVE << MXC_F_I2C_INT_FL1_RXOFI_POS) /**< INT_FL1_RXOFI_INACTIVE Setting */ 524 #define MXC_V_I2C_INT_FL1_RXOFI_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RXOFI_PENDING Value */ 525 #define MXC_S_I2C_INT_FL1_RXOFI_PENDING (MXC_V_I2C_INT_FL1_RXOFI_PENDING << MXC_F_I2C_INT_FL1_RXOFI_POS) /**< INT_FL1_RXOFI_PENDING Setting */ 526 527 #define MXC_F_I2C_INT_FL1_TXUFI_POS 1 /**< INT_FL1_TXUFI Position */ 528 #define MXC_F_I2C_INT_FL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TXUFI_POS)) /**< INT_FL1_TXUFI Mask */ 529 #define MXC_V_I2C_INT_FL1_TXUFI_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TXUFI_INACTIVE Value */ 530 #define MXC_S_I2C_INT_FL1_TXUFI_INACTIVE (MXC_V_I2C_INT_FL1_TXUFI_INACTIVE << MXC_F_I2C_INT_FL1_TXUFI_POS) /**< INT_FL1_TXUFI_INACTIVE Setting */ 531 #define MXC_V_I2C_INT_FL1_TXUFI_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TXUFI_PENDING Value */ 532 #define MXC_S_I2C_INT_FL1_TXUFI_PENDING (MXC_V_I2C_INT_FL1_TXUFI_PENDING << MXC_F_I2C_INT_FL1_TXUFI_POS) /**< INT_FL1_TXUFI_PENDING Setting */ 533 534 /**@} end of group I2C_INT_FL1_Register */ 535 536 /** 537 * @ingroup i2c_registers 538 * @defgroup I2C_INT_EN1 I2C_INT_EN1 539 * @brief Interrupt Staus Register 1. 540 * @{ 541 */ 542 #define MXC_F_I2C_INT_EN1_RXOFIE_POS 0 /**< INT_EN1_RXOFIE Position */ 543 #define MXC_F_I2C_INT_EN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RXOFIE_POS)) /**< INT_EN1_RXOFIE Mask */ 544 #define MXC_V_I2C_INT_EN1_RXOFIE_DIS ((uint32_t)0x0UL) /**< INT_EN1_RXOFIE_DIS Value */ 545 #define MXC_S_I2C_INT_EN1_RXOFIE_DIS (MXC_V_I2C_INT_EN1_RXOFIE_DIS << MXC_F_I2C_INT_EN1_RXOFIE_POS) /**< INT_EN1_RXOFIE_DIS Setting */ 546 #define MXC_V_I2C_INT_EN1_RXOFIE_EN ((uint32_t)0x1UL) /**< INT_EN1_RXOFIE_EN Value */ 547 #define MXC_S_I2C_INT_EN1_RXOFIE_EN (MXC_V_I2C_INT_EN1_RXOFIE_EN << MXC_F_I2C_INT_EN1_RXOFIE_POS) /**< INT_EN1_RXOFIE_EN Setting */ 548 549 #define MXC_F_I2C_INT_EN1_TXUFIE_POS 1 /**< INT_EN1_TXUFIE Position */ 550 #define MXC_F_I2C_INT_EN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TXUFIE_POS)) /**< INT_EN1_TXUFIE Mask */ 551 #define MXC_V_I2C_INT_EN1_TXUFIE_DIS ((uint32_t)0x0UL) /**< INT_EN1_TXUFIE_DIS Value */ 552 #define MXC_S_I2C_INT_EN1_TXUFIE_DIS (MXC_V_I2C_INT_EN1_TXUFIE_DIS << MXC_F_I2C_INT_EN1_TXUFIE_POS) /**< INT_EN1_TXUFIE_DIS Setting */ 553 #define MXC_V_I2C_INT_EN1_TXUFIE_EN ((uint32_t)0x1UL) /**< INT_EN1_TXUFIE_EN Value */ 554 #define MXC_S_I2C_INT_EN1_TXUFIE_EN (MXC_V_I2C_INT_EN1_TXUFIE_EN << MXC_F_I2C_INT_EN1_TXUFIE_POS) /**< INT_EN1_TXUFIE_EN Setting */ 555 556 /**@} end of group I2C_INT_EN1_Register */ 557 558 /** 559 * @ingroup i2c_registers 560 * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN 561 * @brief FIFO Configuration Register. 562 * @{ 563 */ 564 #define MXC_F_I2C_FIFO_LEN_RXLEN_POS 0 /**< FIFO_LEN_RXLEN Position */ 565 #define MXC_F_I2C_FIFO_LEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RXLEN_POS)) /**< FIFO_LEN_RXLEN Mask */ 566 567 #define MXC_F_I2C_FIFO_LEN_TXLEN_POS 8 /**< FIFO_LEN_TXLEN Position */ 568 #define MXC_F_I2C_FIFO_LEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TXLEN_POS)) /**< FIFO_LEN_TXLEN Mask */ 569 570 /**@} end of group I2C_FIFO_LEN_Register */ 571 572 /** 573 * @ingroup i2c_registers 574 * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 575 * @brief Receive Control Register 0. 576 * @{ 577 */ 578 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ 579 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ 580 #define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */ 581 #define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */ 582 #define MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_DONT_RESPOND Value */ 583 #define MXC_S_I2C_RX_CTRL0_DNR_DONT_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_DONT_RESPOND Setting */ 584 585 #define MXC_F_I2C_RX_CTRL0_RXFSH_POS 7 /**< RX_CTRL0_RXFSH Position */ 586 #define MXC_F_I2C_RX_CTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS)) /**< RX_CTRL0_RXFSH Mask */ 587 #define MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RXFSH_NOT_FLUSHED Value */ 588 #define MXC_S_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RXFSH_POS) /**< RX_CTRL0_RXFSH_NOT_FLUSHED Setting */ 589 #define MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RXFSH_FLUSH Value */ 590 #define MXC_S_I2C_RX_CTRL0_RXFSH_FLUSH (MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH << MXC_F_I2C_RX_CTRL0_RXFSH_POS) /**< RX_CTRL0_RXFSH_FLUSH Setting */ 591 592 #define MXC_F_I2C_RX_CTRL0_RXTH_POS 8 /**< RX_CTRL0_RXTH Position */ 593 #define MXC_F_I2C_RX_CTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS)) /**< RX_CTRL0_RXTH Mask */ 594 595 /**@} end of group I2C_RX_CTRL0_Register */ 596 597 /** 598 * @ingroup i2c_registers 599 * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 600 * @brief Receive Control Register 1. 601 * @{ 602 */ 603 #define MXC_F_I2C_RX_CTRL1_RXCNT_POS 0 /**< RX_CTRL1_RXCNT Position */ 604 #define MXC_F_I2C_RX_CTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RXCNT_POS)) /**< RX_CTRL1_RXCNT Mask */ 605 606 #define MXC_F_I2C_RX_CTRL1_RXFIFO_POS 8 /**< RX_CTRL1_RXFIFO Position */ 607 #define MXC_F_I2C_RX_CTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RXFIFO_POS)) /**< RX_CTRL1_RXFIFO Mask */ 608 609 /**@} end of group I2C_RX_CTRL1_Register */ 610 611 /** 612 * @ingroup i2c_registers 613 * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 614 * @brief Transmit Control Register 0. 615 * @{ 616 */ 617 #define MXC_F_I2C_TX_CTRL0_TXPRELD_POS 0 /**< TX_CTRL0_TXPRELD Position */ 618 #define MXC_F_I2C_TX_CTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TXPRELD_POS)) /**< TX_CTRL0_TXPRELD Mask */ 619 #define MXC_V_I2C_TX_CTRL0_TXPRELD_NORMAL ((uint32_t)0x0UL) /**< TX_CTRL0_TXPRELD_NORMAL Value */ 620 #define MXC_S_I2C_TX_CTRL0_TXPRELD_NORMAL (MXC_V_I2C_TX_CTRL0_TXPRELD_NORMAL << MXC_F_I2C_TX_CTRL0_TXPRELD_POS) /**< TX_CTRL0_TXPRELD_NORMAL Setting */ 621 #define MXC_V_I2C_TX_CTRL0_TXPRELD_PRELOAD ((uint32_t)0x1UL) /**< TX_CTRL0_TXPRELD_PRELOAD Value */ 622 #define MXC_S_I2C_TX_CTRL0_TXPRELD_PRELOAD (MXC_V_I2C_TX_CTRL0_TXPRELD_PRELOAD << MXC_F_I2C_TX_CTRL0_TXPRELD_POS) /**< TX_CTRL0_TXPRELD_PRELOAD Setting */ 623 624 #define MXC_F_I2C_TX_CTRL0_TXFSH_POS 7 /**< TX_CTRL0_TXFSH Position */ 625 #define MXC_F_I2C_TX_CTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TXFSH_POS)) /**< TX_CTRL0_TXFSH Mask */ 626 #define MXC_V_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TXFSH_NOT_FLUSHED Value */ 627 #define MXC_S_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TXFSH_POS) /**< TX_CTRL0_TXFSH_NOT_FLUSHED Setting */ 628 #define MXC_V_I2C_TX_CTRL0_TXFSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TXFSH_FLUSH Value */ 629 #define MXC_S_I2C_TX_CTRL0_TXFSH_FLUSH (MXC_V_I2C_TX_CTRL0_TXFSH_FLUSH << MXC_F_I2C_TX_CTRL0_TXFSH_POS) /**< TX_CTRL0_TXFSH_FLUSH Setting */ 630 631 #define MXC_F_I2C_TX_CTRL0_TXTH_POS 8 /**< TX_CTRL0_TXTH Position */ 632 #define MXC_F_I2C_TX_CTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TXTH_POS)) /**< TX_CTRL0_TXTH Mask */ 633 634 /**@} end of group I2C_TX_CTRL0_Register */ 635 636 /** 637 * @ingroup i2c_registers 638 * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 639 * @brief Transmit Control Register 1. 640 * @{ 641 */ 642 #define MXC_F_I2C_TX_CTRL1_TXRDY_POS 0 /**< TX_CTRL1_TXRDY Position */ 643 #define MXC_F_I2C_TX_CTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TXRDY_POS)) /**< TX_CTRL1_TXRDY Mask */ 644 #define MXC_V_I2C_TX_CTRL1_TXRDY_NOT_READY ((uint32_t)0x0UL) /**< TX_CTRL1_TXRDY_NOT_READY Value */ 645 #define MXC_S_I2C_TX_CTRL1_TXRDY_NOT_READY (MXC_V_I2C_TX_CTRL1_TXRDY_NOT_READY << MXC_F_I2C_TX_CTRL1_TXRDY_POS) /**< TX_CTRL1_TXRDY_NOT_READY Setting */ 646 #define MXC_V_I2C_TX_CTRL1_TXRDY_READY ((uint32_t)0x1UL) /**< TX_CTRL1_TXRDY_READY Value */ 647 #define MXC_S_I2C_TX_CTRL1_TXRDY_READY (MXC_V_I2C_TX_CTRL1_TXRDY_READY << MXC_F_I2C_TX_CTRL1_TXRDY_POS) /**< TX_CTRL1_TXRDY_READY Setting */ 648 649 #define MXC_F_I2C_TX_CTRL1_TXLAST_POS 1 /**< TX_CTRL1_TXLAST Position */ 650 #define MXC_F_I2C_TX_CTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TXLAST_POS)) /**< TX_CTRL1_TXLAST Mask */ 651 #define MXC_V_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST ((uint32_t)0x0UL) /**< TX_CTRL1_TXLAST_PAUSE_ON_LAST Value */ 652 #define MXC_S_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST (MXC_V_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST << MXC_F_I2C_TX_CTRL1_TXLAST_POS) /**< TX_CTRL1_TXLAST_PAUSE_ON_LAST Setting */ 653 #define MXC_V_I2C_TX_CTRL1_TXLAST_END_ON_LAST ((uint32_t)0x1UL) /**< TX_CTRL1_TXLAST_END_ON_LAST Value */ 654 #define MXC_S_I2C_TX_CTRL1_TXLAST_END_ON_LAST (MXC_V_I2C_TX_CTRL1_TXLAST_END_ON_LAST << MXC_F_I2C_TX_CTRL1_TXLAST_POS) /**< TX_CTRL1_TXLAST_END_ON_LAST Setting */ 655 656 #define MXC_F_I2C_TX_CTRL1_TXFIFO_POS 8 /**< TX_CTRL1_TXFIFO Position */ 657 #define MXC_F_I2C_TX_CTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TXFIFO_POS)) /**< TX_CTRL1_TXFIFO Mask */ 658 659 /**@} end of group I2C_TX_CTRL1_Register */ 660 661 /** 662 * @ingroup i2c_registers 663 * @defgroup I2C_FIFO I2C_FIFO 664 * @brief Data Register. 665 * @{ 666 */ 667 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 668 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 669 670 /**@} end of group I2C_FIFO_Register */ 671 672 /** 673 * @ingroup i2c_registers 674 * @defgroup I2C_MSTR_MODE I2C_MSTR_MODE 675 * @brief Master Control Register. 676 * @{ 677 */ 678 #define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */ 679 #define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */ 680 #define MXC_V_I2C_MSTR_MODE_START_START ((uint32_t)0x1UL) /**< MSTR_MODE_START_START Value */ 681 #define MXC_S_I2C_MSTR_MODE_START_START (MXC_V_I2C_MSTR_MODE_START_START << MXC_F_I2C_MSTR_MODE_START_POS) /**< MSTR_MODE_START_START Setting */ 682 683 #define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */ 684 #define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */ 685 #define MXC_V_I2C_MSTR_MODE_RESTART_RESTART ((uint32_t)0x1UL) /**< MSTR_MODE_RESTART_RESTART Value */ 686 #define MXC_S_I2C_MSTR_MODE_RESTART_RESTART (MXC_V_I2C_MSTR_MODE_RESTART_RESTART << MXC_F_I2C_MSTR_MODE_RESTART_POS) /**< MSTR_MODE_RESTART_RESTART Setting */ 687 688 #define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */ 689 #define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */ 690 #define MXC_V_I2C_MSTR_MODE_STOP_STOP ((uint32_t)0x1UL) /**< MSTR_MODE_STOP_STOP Value */ 691 #define MXC_S_I2C_MSTR_MODE_STOP_STOP (MXC_V_I2C_MSTR_MODE_STOP_STOP << MXC_F_I2C_MSTR_MODE_STOP_POS) /**< MSTR_MODE_STOP_STOP Setting */ 692 693 #define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */ 694 #define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */ 695 #define MXC_V_I2C_MSTR_MODE_SEA_7BIT_ADDR ((uint32_t)0x0UL) /**< MSTR_MODE_SEA_7BIT_ADDR Value */ 696 #define MXC_S_I2C_MSTR_MODE_SEA_7BIT_ADDR (MXC_V_I2C_MSTR_MODE_SEA_7BIT_ADDR << MXC_F_I2C_MSTR_MODE_SEA_POS) /**< MSTR_MODE_SEA_7BIT_ADDR Setting */ 697 #define MXC_V_I2C_MSTR_MODE_SEA_10BIT_ADDR ((uint32_t)0x1UL) /**< MSTR_MODE_SEA_10BIT_ADDR Value */ 698 #define MXC_S_I2C_MSTR_MODE_SEA_10BIT_ADDR (MXC_V_I2C_MSTR_MODE_SEA_10BIT_ADDR << MXC_F_I2C_MSTR_MODE_SEA_POS) /**< MSTR_MODE_SEA_10BIT_ADDR Setting */ 699 700 /**@} end of group I2C_MSTR_MODE_Register */ 701 702 /** 703 * @ingroup i2c_registers 704 * @defgroup I2C_CLK_LO I2C_CLK_LO 705 * @brief Clock Low Register. 706 * @{ 707 */ 708 #define MXC_F_I2C_CLK_LO_SCL_LO_POS 0 /**< CLK_LO_SCL_LO Position */ 709 #define MXC_F_I2C_CLK_LO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_SCL_LO_POS)) /**< CLK_LO_SCL_LO Mask */ 710 711 /**@} end of group I2C_CLK_LO_Register */ 712 713 /** 714 * @ingroup i2c_registers 715 * @defgroup I2C_CLK_HI I2C_CLK_HI 716 * @brief Clock high Register. 717 * @{ 718 */ 719 #define MXC_F_I2C_CLK_HI_SCL_HI_POS 0 /**< CLK_HI_SCL_HI Position */ 720 #define MXC_F_I2C_CLK_HI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_SCL_HI_POS)) /**< CLK_HI_SCL_HI Mask */ 721 722 /**@} end of group I2C_CLK_HI_Register */ 723 724 /** 725 * @ingroup i2c_registers 726 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 727 * @brief Timeout Register 728 * @{ 729 */ 730 #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ 731 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ 732 733 /**@} end of group I2C_TIMEOUT_Register */ 734 735 /** 736 * @ingroup i2c_registers 737 * @defgroup I2C_SLV_ADDR I2C_SLV_ADDR 738 * @brief Slave Address Register. 739 * @{ 740 */ 741 #define MXC_F_I2C_SLV_ADDR_SLA_POS 0 /**< SLV_ADDR_SLA Position */ 742 #define MXC_F_I2C_SLV_ADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLV_ADDR_SLA_POS)) /**< SLV_ADDR_SLA Mask */ 743 744 #define MXC_F_I2C_SLV_ADDR_EA_POS 15 /**< SLV_ADDR_EA Position */ 745 #define MXC_F_I2C_SLV_ADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLV_ADDR_EA_POS)) /**< SLV_ADDR_EA Mask */ 746 #define MXC_V_I2C_SLV_ADDR_EA_7BIT_ADDR ((uint32_t)0x0UL) /**< SLV_ADDR_EA_7BIT_ADDR Value */ 747 #define MXC_S_I2C_SLV_ADDR_EA_7BIT_ADDR (MXC_V_I2C_SLV_ADDR_EA_7BIT_ADDR << MXC_F_I2C_SLV_ADDR_EA_POS) /**< SLV_ADDR_EA_7BIT_ADDR Setting */ 748 #define MXC_V_I2C_SLV_ADDR_EA_10BIT_ADDR ((uint32_t)0x1UL) /**< SLV_ADDR_EA_10BIT_ADDR Value */ 749 #define MXC_S_I2C_SLV_ADDR_EA_10BIT_ADDR (MXC_V_I2C_SLV_ADDR_EA_10BIT_ADDR << MXC_F_I2C_SLV_ADDR_EA_POS) /**< SLV_ADDR_EA_10BIT_ADDR Setting */ 750 751 /**@} end of group I2C_SLV_ADDR_Register */ 752 753 /** 754 * @ingroup i2c_registers 755 * @defgroup I2C_DMA I2C_DMA 756 * @brief DMA Register. 757 * @{ 758 */ 759 #define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ 760 #define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ 761 #define MXC_V_I2C_DMA_TXEN_DIS ((uint32_t)0x0UL) /**< DMA_TXEN_DIS Value */ 762 #define MXC_S_I2C_DMA_TXEN_DIS (MXC_V_I2C_DMA_TXEN_DIS << MXC_F_I2C_DMA_TXEN_POS) /**< DMA_TXEN_DIS Setting */ 763 #define MXC_V_I2C_DMA_TXEN_EN ((uint32_t)0x1UL) /**< DMA_TXEN_EN Value */ 764 #define MXC_S_I2C_DMA_TXEN_EN (MXC_V_I2C_DMA_TXEN_EN << MXC_F_I2C_DMA_TXEN_POS) /**< DMA_TXEN_EN Setting */ 765 766 #define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ 767 #define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ 768 #define MXC_V_I2C_DMA_RXEN_DIS ((uint32_t)0x0UL) /**< DMA_RXEN_DIS Value */ 769 #define MXC_S_I2C_DMA_RXEN_DIS (MXC_V_I2C_DMA_RXEN_DIS << MXC_F_I2C_DMA_RXEN_POS) /**< DMA_RXEN_DIS Setting */ 770 #define MXC_V_I2C_DMA_RXEN_EN ((uint32_t)0x1UL) /**< DMA_RXEN_EN Value */ 771 #define MXC_S_I2C_DMA_RXEN_EN (MXC_V_I2C_DMA_RXEN_EN << MXC_F_I2C_DMA_RXEN_POS) /**< DMA_RXEN_EN Setting */ 772 773 /**@} end of group I2C_DMA_Register */ 774 775 #ifdef __cplusplus 776 } 777 #endif 778 779 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_I2C_REGS_H_ 780
