1 /** 2 * @file i2c_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C_REVA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_reva_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ 29 #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c_reva 67 * @defgroup i2c_reva_registers I2C_REVA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C_REVA Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_reva_registers 74 * Structure type to access the I2C_REVA Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C_REVA CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C_REVA STATUS Register */ 79 __IO uint32_t intfl0; /**< <tt>\b 0x08:</tt> I2C_REVA INTFL0 Register */ 80 __IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C_REVA INTEN0 Register */ 81 __IO uint32_t intfl1; /**< <tt>\b 0x10:</tt> I2C_REVA INTFL1 Register */ 82 __IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C_REVA INTEN1 Register */ 83 __IO uint32_t fifolen; /**< <tt>\b 0x18:</tt> I2C_REVA FIFOLEN Register */ 84 __IO uint32_t rxctrl0; /**< <tt>\b 0x1C:</tt> I2C_REVA RXCTRL0 Register */ 85 __IO uint32_t rxctrl1; /**< <tt>\b 0x20:</tt> I2C_REVA RXCTRL1 Register */ 86 __IO uint32_t txctrl0; /**< <tt>\b 0x24:</tt> I2C_REVA TXCTRL0 Register */ 87 __IO uint32_t txctrl1; /**< <tt>\b 0x28:</tt> I2C_REVA TXCTRL1 Register */ 88 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C_REVA FIFO Register */ 89 __IO uint32_t mstctrl; /**< <tt>\b 0x30:</tt> I2C_REVA MSTCTRL Register */ 90 __IO uint32_t clklo; /**< <tt>\b 0x34:</tt> I2C_REVA CLKLO Register */ 91 __IO uint32_t clkhi; /**< <tt>\b 0x38:</tt> I2C_REVA CLKHI Register */ 92 __IO uint32_t hsclk; /**< <tt>\b 0x3C:</tt> I2C_REVA HSCLK Register */ 93 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C_REVA TIMEOUT Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C_REVA DMA Register */ 96 union { 97 __IO uint32_t slave_multi[4]; /**< <tt>\b 0x4C:</tt> I2C_REVA SLAVE_MULTI Register */ 98 struct { 99 __IO uint32_t slave0; /**< <tt>\b 0x4C:</tt> I2C_REVA SLAVE0 Register */ 100 __IO uint32_t slave1; /**< <tt>\b 0x50:</tt> I2C_REVA SLAVE1 Register */ 101 __IO uint32_t slave2; /**< <tt>\b 0x54:</tt> I2C_REVA SLAVE2 Register */ 102 __IO uint32_t slave3; /**< <tt>\b 0x58:</tt> I2C_REVA SLAVE3 Register */ 103 }; 104 }; 105 } mxc_i2c_reva_regs_t; 106 107 /** 108 * @ingroup i2c_reva_registers 109 * @defgroup I2C_REVA_CTRL I2C_REVA_CTRL 110 * @brief Control Register0. 111 * @{ 112 */ 113 #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 114 #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 115 116 #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ 117 #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ 118 119 #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ 120 #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ 121 122 #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ 123 #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ 124 125 #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ 126 #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ 127 128 #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 129 #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 130 131 #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 132 #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 133 134 #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 135 #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 136 137 #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 138 #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 139 140 #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ 141 #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ 142 143 #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ 144 #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ 145 146 #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ 147 #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ 148 149 #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ 150 #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ 151 152 #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ 153 #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ 154 155 /**@} end of group I2C_REVA_CTRL_Register */ 156 157 /** 158 * @ingroup i2c_reva_registers 159 * @defgroup I2C_REVA_STATUS I2C_REVA_STATUS 160 * @brief Status Register. 161 * @{ 162 */ 163 #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 164 #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 165 166 #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ 167 #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ 168 169 #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 170 #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 171 172 #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ 173 #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ 174 175 #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 176 #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 177 178 #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ 179 #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ 180 181 /**@} end of group I2C_REVA_STATUS_Register */ 182 183 /** 184 * @ingroup i2c_reva_registers 185 * @defgroup I2C_REVA_INTFL0 I2C_REVA_INTFL0 186 * @brief Interrupt Status Register. 187 * @{ 188 */ 189 #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ 190 #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ 191 192 #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ 193 #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ 194 195 #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ 196 #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ 197 198 #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ 199 #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ 200 201 #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ 202 #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ 203 204 #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ 205 #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ 206 207 #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ 208 #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ 209 210 #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ 211 #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ 212 213 #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ 214 #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ 215 216 #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ 217 #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ 218 219 #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ 220 #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ 221 222 #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ 223 #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ 224 225 #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ 226 #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ 227 228 #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ 229 #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ 230 231 #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ 232 #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ 233 234 #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ 235 #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ 236 237 #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ 238 #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ 239 240 #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ 241 #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ 242 243 #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ 244 #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ 245 246 /**@} end of group I2C_REVA_INTFL0_Register */ 247 248 /** 249 * @ingroup i2c_reva_registers 250 * @defgroup I2C_REVA_INTEN0 I2C_REVA_INTEN0 251 * @brief Interrupt Enable Register. 252 * @{ 253 */ 254 #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ 255 #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ 256 257 #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ 258 #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ 259 260 #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ 261 #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ 262 263 #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ 264 #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ 265 266 #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ 267 #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ 268 269 #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ 270 #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ 271 272 #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ 273 #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ 274 275 #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ 276 #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ 277 278 #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ 279 #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ 280 281 #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ 282 #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ 283 284 #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ 285 #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ 286 287 #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ 288 #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ 289 290 #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ 291 #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ 292 293 #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ 294 #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ 295 296 #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ 297 #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ 298 299 #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ 300 #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ 301 302 #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ 303 #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ 304 305 #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ 306 #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ 307 308 #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ 309 #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ 310 311 /**@} end of group I2C_REVA_INTEN0_Register */ 312 313 /** 314 * @ingroup i2c_reva_registers 315 * @defgroup I2C_REVA_INTFL1 I2C_REVA_INTFL1 316 * @brief Interrupt Status Register 1. 317 * @{ 318 */ 319 #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ 320 #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ 321 322 #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ 323 #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ 324 325 #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ 326 #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ 327 328 /**@} end of group I2C_REVA_INTFL1_Register */ 329 330 /** 331 * @ingroup i2c_reva_registers 332 * @defgroup I2C_REVA_INTEN1 I2C_REVA_INTEN1 333 * @brief Interrupt Staus Register 1. 334 * @{ 335 */ 336 #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ 337 #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ 338 339 #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ 340 #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ 341 342 #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ 343 #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ 344 345 /**@} end of group I2C_REVA_INTEN1_Register */ 346 347 /** 348 * @ingroup i2c_reva_registers 349 * @defgroup I2C_REVA_FIFOLEN I2C_REVA_FIFOLEN 350 * @brief FIFO Configuration Register. 351 * @{ 352 */ 353 #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ 354 #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ 355 356 #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ 357 #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ 358 359 /**@} end of group I2C_REVA_FIFOLEN_Register */ 360 361 /** 362 * @ingroup i2c_reva_registers 363 * @defgroup I2C_REVA_RXCTRL0 I2C_REVA_RXCTRL0 364 * @brief Receive Control Register 0. 365 * @{ 366 */ 367 #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ 368 #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ 369 370 #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ 371 #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ 372 373 #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ 374 #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ 375 376 /**@} end of group I2C_REVA_RXCTRL0_Register */ 377 378 /** 379 * @ingroup i2c_reva_registers 380 * @defgroup I2C_REVA_RXCTRL1 I2C_REVA_RXCTRL1 381 * @brief Receive Control Register 1. 382 * @{ 383 */ 384 #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ 385 #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ 386 387 #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ 388 #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ 389 390 /**@} end of group I2C_REVA_RXCTRL1_Register */ 391 392 /** 393 * @ingroup i2c_reva_registers 394 * @defgroup I2C_REVA_TXCTRL0 I2C_REVA_TXCTRL0 395 * @brief Transmit Control Register 0. 396 * @{ 397 */ 398 #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ 399 #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ 400 401 #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ 402 #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ 403 404 #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ 405 #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ 406 407 #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ 408 #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ 409 410 #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ 411 #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ 412 413 #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ 414 #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ 415 416 #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ 417 #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ 418 419 #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ 420 #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ 421 422 /**@} end of group I2C_REVA_TXCTRL0_Register */ 423 424 /** 425 * @ingroup i2c_reva_registers 426 * @defgroup I2C_REVA_TXCTRL1 I2C_REVA_TXCTRL1 427 * @brief Transmit Control Register 1. 428 * @{ 429 */ 430 #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ 431 #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ 432 433 #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ 434 #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ 435 436 /**@} end of group I2C_REVA_TXCTRL1_Register */ 437 438 /** 439 * @ingroup i2c_reva_registers 440 * @defgroup I2C_REVA_FIFO I2C_REVA_FIFO 441 * @brief Data Register. 442 * @{ 443 */ 444 #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 445 #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 446 447 /**@} end of group I2C_REVA_FIFO_Register */ 448 449 /** 450 * @ingroup i2c_reva_registers 451 * @defgroup I2C_REVA_MSTCTRL I2C_REVA_MSTCTRL 452 * @brief Master Control Register. 453 * @{ 454 */ 455 #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ 456 #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ 457 458 #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ 459 #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ 460 461 #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ 462 #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ 463 464 #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ 465 #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ 466 467 /**@} end of group I2C_REVA_MSTCTRL_Register */ 468 469 /** 470 * @ingroup i2c_reva_registers 471 * @defgroup I2C_REVA_CLKLO I2C_REVA_CLKLO 472 * @brief Clock Low Register. 473 * @{ 474 */ 475 #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ 476 #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ 477 478 /**@} end of group I2C_REVA_CLKLO_Register */ 479 480 /** 481 * @ingroup i2c_reva_registers 482 * @defgroup I2C_REVA_CLKHI I2C_REVA_CLKHI 483 * @brief Clock high Register. 484 * @{ 485 */ 486 #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ 487 #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ 488 489 /**@} end of group I2C_REVA_CLKHI_Register */ 490 491 /** 492 * @ingroup i2c_reva_registers 493 * @defgroup I2C_REVA_HSCLK I2C_REVA_HSCLK 494 * @brief Clock high Register. 495 * @{ 496 */ 497 #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ 498 #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ 499 500 #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ 501 #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ 502 503 /**@} end of group I2C_REVA_HSCLK_Register */ 504 505 /** 506 * @ingroup i2c_reva_registers 507 * @defgroup I2C_REVA_TIMEOUT I2C_REVA_TIMEOUT 508 * @brief Timeout Register 509 * @{ 510 */ 511 #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ 512 #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ 513 514 /**@} end of group I2C_REVA_TIMEOUT_Register */ 515 516 /** 517 * @ingroup i2c_reva_registers 518 * @defgroup I2C_REVA_DMA I2C_REVA_DMA 519 * @brief DMA Register. 520 * @{ 521 */ 522 #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ 523 #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 524 525 #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ 526 #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 527 528 /**@} end of group I2C_REVA_DMA_Register */ 529 530 /** 531 * @ingroup i2c_reva_registers 532 * @defgroup I2C_REVA_SLAVE_MULTI I2C_REVA_SLAVE_MULTI 533 * @brief Slave Address Register. 534 * @{ 535 */ 536 #define MXC_F_I2C_REVA_SLAVE_MULTI_ADDR_POS 0 /**< SLAVE_MULTI_ADDR Position */ 537 #define MXC_F_I2C_REVA_SLAVE_MULTI_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_MULTI_ADDR_POS)) /**< SLAVE_MULTI_ADDR Mask */ 538 539 #define MXC_F_I2C_REVA_SLAVE_MULTI_DIS_POS 10 /**< SLAVE_MULTI_DIS Position */ 540 #define MXC_F_I2C_REVA_SLAVE_MULTI_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_MULTI_DIS_POS)) /**< SLAVE_MULTI_DIS Mask */ 541 542 #define MXC_F_I2C_REVA_SLAVE_MULTI_EXT_ADDR_EN_POS 15 /**< SLAVE_MULTI_EXT_ADDR_EN Position */ 543 #define MXC_F_I2C_REVA_SLAVE_MULTI_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_MULTI_EXT_ADDR_EN_POS)) /**< SLAVE_MULTI_EXT_ADDR_EN Mask */ 544 545 /**@} end of group I2C_REVA_SLAVE_MULTI_Register */ 546 547 #ifdef __cplusplus 548 } 549 #endif 550 551 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ 552
