1 /** 2 * @file htmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_HTMR_HTMR_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_HTMR_HTMR_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup htmr 65 * @defgroup htmr_registers HTMR_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 67 * @details High Speed Timer Module. 68 */ 69 70 /** 71 * @ingroup htmr_registers 72 * Structure type to access the HTMR Registers. 73 */ 74 typedef struct { 75 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> HTMR SEC Register */ 76 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> HTMR SSEC Register */ 77 __IO uint32_t ras; /**< <tt>\b 0x08:</tt> HTMR RAS Register */ 78 __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> HTMR RSSA Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> HTMR CTRL Register */ 80 } mxc_htmr_reva_regs_t; 81 82 /* Register offsets for module HTMR */ 83 /** 84 * @ingroup htmr_registers 85 * @defgroup HTMR_Register_Offsets Register Offsets 86 * @brief HTMR Peripheral Register Offsets from the HTMR Base Peripheral Address. 87 * @{ 88 */ 89 #define MXC_R_HTMR_REVA_SEC ((uint32_t)0x00000000UL) /**< Offset from HTMR Base Address: <tt> 0x0000</tt> */ 90 #define MXC_R_HTMR_REVA_SSEC ((uint32_t)0x00000004UL) /**< Offset from HTMR Base Address: <tt> 0x0004</tt> */ 91 #define MXC_R_HTMR_REVA_RAS ((uint32_t)0x00000008UL) /**< Offset from HTMR Base Address: <tt> 0x0008</tt> */ 92 #define MXC_R_HTMR_REVA_RSSA ((uint32_t)0x0000000CUL) /**< Offset from HTMR Base Address: <tt> 0x000C</tt> */ 93 #define MXC_R_HTMR_REVA_CTRL ((uint32_t)0x00000010UL) /**< Offset from HTMR Base Address: <tt> 0x0010</tt> */ 94 /**@} end of group htmr_registers */ 95 96 /** 97 * @ingroup htmr_registers 98 * @defgroup HTMR_SSEC HTMR_SSEC 99 * @brief HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). 100 * HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 101 * @{ 102 */ 103 #define MXC_F_HTMR_REVA_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ 104 #define MXC_F_HTMR_REVA_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_HTMR_REVA_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ 105 106 /**@} end of group HTMR_SSEC_Register */ 107 108 /** 109 * @ingroup htmr_registers 110 * @defgroup HTMR_RAS HTMR_RAS 111 * @brief Long Interval Alarm. 112 * @{ 113 */ 114 #define MXC_F_HTMR_REVA_RAS_RAS_POS 0 /**< RAS_RAS Position */ 115 #define MXC_F_HTMR_REVA_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_HTMR_REVA_RAS_RAS_POS)) /**< RAS_RAS Mask */ 116 117 /**@} end of group HTMR_RAS_Register */ 118 119 /** 120 * @ingroup htmr_registers 121 * @defgroup HTMR_RSSA HTMR_RSSA 122 * @brief HTimer Short Interval Alarm. This register contains the reload value for the 123 * short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. 124 * @{ 125 */ 126 #define MXC_F_HTMR_REVA_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ 127 #define MXC_F_HTMR_REVA_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_REVA_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ 128 129 /**@} end of group HTMR_RSSA_Register */ 130 131 /** 132 * @ingroup htmr_registers 133 * @defgroup HTMR_CTRL HTMR_CTRL 134 * @brief HTimer Control Register. 135 * @{ 136 */ 137 #define MXC_F_HTMR_REVA_CTRL_HTEN_POS 0 /**< CTRL_HTEN Position */ 138 #define MXC_F_HTMR_REVA_CTRL_HTEN ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_HTEN_POS)) /**< CTRL_HTEN Mask */ 139 140 #define MXC_F_HTMR_REVA_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 141 #define MXC_F_HTMR_REVA_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 142 143 #define MXC_F_HTMR_REVA_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 144 #define MXC_F_HTMR_REVA_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 145 146 #define MXC_F_HTMR_REVA_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 147 #define MXC_F_HTMR_REVA_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 148 149 #define MXC_F_HTMR_REVA_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 150 #define MXC_F_HTMR_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 151 152 #define MXC_F_HTMR_REVA_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 153 #define MXC_F_HTMR_REVA_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 154 155 #define MXC_F_HTMR_REVA_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 156 #define MXC_F_HTMR_REVA_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 157 158 #define MXC_F_HTMR_REVA_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 159 #define MXC_F_HTMR_REVA_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 160 161 #define MXC_F_HTMR_REVA_CTRL_ACRE_POS 14 /**< CTRL_ACRE Position */ 162 #define MXC_F_HTMR_REVA_CTRL_ACRE ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_ACRE_POS)) /**< CTRL_ACRE Mask */ 163 164 #define MXC_F_HTMR_REVA_CTRL_WE_POS 15 /**< CTRL_WE Position */ 165 #define MXC_F_HTMR_REVA_CTRL_WE ((uint32_t)(0x1UL << MXC_F_HTMR_REVA_CTRL_WE_POS)) /**< CTRL_WE Mask */ 166 167 /**@} end of group HTMR_CTRL_Register */ 168 169 #ifdef __cplusplus 170 } 171 #endif 172 173 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_HTMR_HTMR_REVA_REGS_H_ 174 175
