1 /** 2 * @file htmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup htmr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_HTMR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_HTMR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup htmr 67 * @defgroup htmr_registers HTMR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 69 * @details High Speed Timer Module. 70 */ 71 72 /** 73 * @ingroup htmr_registers 74 * Structure type to access the HTMR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lnicnt; /**< <tt>\b 0x00:</tt> HTMR LNICNT Register */ 78 __IO uint32_t shicnt; /**< <tt>\b 0x04:</tt> HTMR SHICNT Register */ 79 __IO uint32_t lnialm; /**< <tt>\b 0x08:</tt> HTMR LNIALM Register */ 80 __IO uint32_t shialm; /**< <tt>\b 0x0C:</tt> HTMR SHIALM Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> HTMR CTRL Register */ 82 __IO uint32_t trim; /**< <tt>\b 0x14:</tt> HTMR TRIM Register */ 83 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> HTMR OSCCTRL Register */ 84 } mxc_htmr_regs_t; 85 86 /* Register offsets for module HTMR */ 87 /** 88 * @ingroup htmr_registers 89 * @defgroup HTMR_Register_Offsets Register Offsets 90 * @brief HTMR Peripheral Register Offsets from the HTMR Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_HTMR_LNICNT ((uint32_t)0x00000000UL) /**< Offset from HTMR Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_HTMR_SHICNT ((uint32_t)0x00000004UL) /**< Offset from HTMR Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_HTMR_LNIALM ((uint32_t)0x00000008UL) /**< Offset from HTMR Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_HTMR_SHIALM ((uint32_t)0x0000000CUL) /**< Offset from HTMR Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_HTMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from HTMR Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_HTMR_TRIM ((uint32_t)0x00000014UL) /**< Offset from HTMR Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_HTMR_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from HTMR Base Address: <tt> 0x0018</tt> */ 100 /**@} end of group htmr_registers */ 101 102 /** 103 * @ingroup htmr_registers 104 * @defgroup HTMR_LNICNT HTMR_LNICNT 105 * @brief HTimer Long-Interval Counter. This register contains the 32 most significant 106 * bits of the counter. 107 * @{ 108 */ 109 #define MXC_F_HTMR_LNICNT_CNT_POS 0 /**< LNICNT_CNT Position */ 110 #define MXC_F_HTMR_LNICNT_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_LNICNT_CNT_POS)) /**< LNICNT_CNT Mask */ 111 112 /**@} end of group HTMR_LNICNT_Register */ 113 114 /** 115 * @ingroup htmr_registers 116 * @defgroup HTMR_SHICNT HTMR_SHICNT 117 * @brief HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). 118 * HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 119 * @{ 120 */ 121 #define MXC_F_HTMR_SHICNT_CNT_POS 0 /**< SHICNT_CNT Position */ 122 #define MXC_F_HTMR_SHICNT_CNT ((uint32_t)(0xFFUL << MXC_F_HTMR_SHICNT_CNT_POS)) /**< SHICNT_CNT Mask */ 123 124 /**@} end of group HTMR_SHICNT_Register */ 125 126 /** 127 * @ingroup htmr_registers 128 * @defgroup HTMR_LNIALM HTMR_LNIALM 129 * @brief HTimer Long Interval Alarm Value Register. 130 * @{ 131 */ 132 #define MXC_F_HTMR_LNIALM_ALM_POS 0 /**< LNIALM_ALM Position */ 133 #define MXC_F_HTMR_LNIALM_ALM ((uint32_t)(0xFFFFFUL << MXC_F_HTMR_LNIALM_ALM_POS)) /**< LNIALM_ALM Mask */ 134 135 /**@} end of group HTMR_LNIALM_Register */ 136 137 /** 138 * @ingroup htmr_registers 139 * @defgroup HTMR_SHIALM HTMR_SHIALM 140 * @brief HTimer Short Interval Alarm Value Register. 141 * @{ 142 */ 143 #define MXC_F_HTMR_SHIALM_ALM_POS 0 /**< SHIALM_ALM Position */ 144 #define MXC_F_HTMR_SHIALM_ALM ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_SHIALM_ALM_POS)) /**< SHIALM_ALM Mask */ 145 146 /**@} end of group HTMR_SHIALM_Register */ 147 148 /** 149 * @ingroup htmr_registers 150 * @defgroup HTMR_CTRL HTMR_CTRL 151 * @brief HTimer Control Register. 152 * @{ 153 */ 154 #define MXC_F_HTMR_CTRL_EN_POS 0 /**< CTRL_EN Position */ 155 #define MXC_F_HTMR_CTRL_EN ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_EN_POS)) /**< CTRL_EN Mask */ 156 157 #define MXC_F_HTMR_CTRL_LONG_ALM_IE_POS 1 /**< CTRL_LONG_ALM_IE Position */ 158 #define MXC_F_HTMR_CTRL_LONG_ALM_IE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_LONG_ALM_IE_POS)) /**< CTRL_LONG_ALM_IE Mask */ 159 160 #define MXC_F_HTMR_CTRL_SHORT_ALM_IE_POS 2 /**< CTRL_SHORT_ALM_IE Position */ 161 #define MXC_F_HTMR_CTRL_SHORT_ALM_IE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_SHORT_ALM_IE_POS)) /**< CTRL_SHORT_ALM_IE Mask */ 162 163 #define MXC_F_HTMR_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 164 #define MXC_F_HTMR_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 165 166 #define MXC_F_HTMR_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 167 #define MXC_F_HTMR_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 168 169 #define MXC_F_HTMR_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ 170 #define MXC_F_HTMR_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ 171 172 #define MXC_F_HTMR_CTRL_LONG_ALM_IF_POS 6 /**< CTRL_LONG_ALM_IF Position */ 173 #define MXC_F_HTMR_CTRL_LONG_ALM_IF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_LONG_ALM_IF_POS)) /**< CTRL_LONG_ALM_IF Mask */ 174 175 #define MXC_F_HTMR_CTRL_SHORT_ALM_IF_POS 7 /**< CTRL_SHORT_ALM_IF Position */ 176 #define MXC_F_HTMR_CTRL_SHORT_ALM_IF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_SHORT_ALM_IF_POS)) /**< CTRL_SHORT_ALM_IF Mask */ 177 178 #define MXC_F_HTMR_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ 179 #define MXC_F_HTMR_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ 180 181 /**@} end of group HTMR_CTRL_Register */ 182 183 /** 184 * @ingroup htmr_registers 185 * @defgroup HTMR_TRIM HTMR_TRIM 186 * @brief HTimer Trim Register. 187 * @{ 188 */ 189 #define MXC_F_HTMR_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ 190 #define MXC_F_HTMR_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_HTMR_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ 191 192 #define MXC_F_HTMR_TRIM_VBAT_TMR_POS 8 /**< TRIM_VBAT_TMR Position */ 193 #define MXC_F_HTMR_TRIM_VBAT_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_HTMR_TRIM_VBAT_TMR_POS)) /**< TRIM_VBAT_TMR Mask */ 194 195 /**@} end of group HTMR_TRIM_Register */ 196 197 /** 198 * @ingroup htmr_registers 199 * @defgroup HTMR_OSCCTRL HTMR_OSCCTRL 200 * @brief HTimer Oscillator Control Register. 201 * @{ 202 */ 203 #define MXC_F_HTMR_OSCCTRL_FILTER_EN_POS 0 /**< OSCCTRL_FILTER_EN Position */ 204 #define MXC_F_HTMR_OSCCTRL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_FILTER_EN_POS)) /**< OSCCTRL_FILTER_EN Mask */ 205 206 #define MXC_F_HTMR_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ 207 #define MXC_F_HTMR_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ 208 209 #define MXC_F_HTMR_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ 210 #define MXC_F_HTMR_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ 211 212 #define MXC_F_HTMR_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ 213 #define MXC_F_HTMR_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ 214 215 #define MXC_F_HTMR_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 216 #define MXC_F_HTMR_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 217 218 #define MXC_F_HTMR_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ 219 #define MXC_F_HTMR_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_HTMR_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ 220 221 /**@} end of group HTMR_OSCCTRL_Register */ 222 223 #ifdef __cplusplus 224 } 225 #endif 226 227 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_HTMR_REGS_H_ 228
