1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */ 78 __IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */ 79 __IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */ 85 __IO uint32_t memckcn; /**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */ 86 __IO uint32_t memzcn; /**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 89 __IO uint32_t rstr1; /**< <tt>\b 0x44:</tt> GCR RSTR1 Register */ 90 __IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */ 91 __IO uint32_t event_en; /**< <tt>\b 0x4C:</tt> GCR EVENT_EN Register */ 92 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 93 __IO uint32_t syssie; /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */ 94 __R uint32_t rsv_0x58_0x63[3]; 95 __IO uint32_t ecc_er; /**< <tt>\b 0x64:</tt> GCR ECC_ER Register */ 96 __IO uint32_t ecc_ced; /**< <tt>\b 0x68:</tt> GCR ECC_CED Register */ 97 __IO uint32_t ecc_irqen; /**< <tt>\b 0x6C:</tt> GCR ECC_IRQEN Register */ 98 __IO uint32_t ecc_errad; /**< <tt>\b 0x70:</tt> GCR ECC_ERRAD Register */ 99 __IO uint32_t btle_ldocr; /**< <tt>\b 0x74:</tt> GCR BTLE_LDOCR Register */ 100 __IO uint32_t btle_ldodcr; /**< <tt>\b 0x78:</tt> GCR BTLE_LDODCR Register */ 101 __R uint32_t rsv_0x7c; 102 __IO uint32_t gp0; /**< <tt>\b 0x80:</tt> GCR GP0 Register */ 103 __IO uint32_t apb_async; /**< <tt>\b 0x84:</tt> GCR APB_ASYNC Register */ 104 } mxc_gcr_regs_t; 105 106 /* Register offsets for module GCR */ 107 /** 108 * @ingroup gcr_registers 109 * @defgroup GCR_Register_Offsets Register Offsets 110 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 111 * @{ 112 */ 113 #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 114 #define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 115 #define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 116 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 117 #define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 118 #define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 119 #define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 120 #define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 121 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 122 #define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 123 #define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 124 #define MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 125 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 126 #define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 127 #define MXC_R_GCR_ECC_ER ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 128 #define MXC_R_GCR_ECC_CED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 129 #define MXC_R_GCR_ECC_IRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 130 #define MXC_R_GCR_ECC_ERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 131 #define MXC_R_GCR_BTLE_LDOCR ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: <tt> 0x0074</tt> */ 132 #define MXC_R_GCR_BTLE_LDODCR ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: <tt> 0x0078</tt> */ 133 #define MXC_R_GCR_GP0 ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: <tt> 0x0080</tt> */ 134 #define MXC_R_GCR_APB_ASYNC ((uint32_t)0x00000084UL) /**< Offset from GCR Base Address: <tt> 0x0084</tt> */ 135 /**@} end of group gcr_registers */ 136 137 /** 138 * @ingroup gcr_registers 139 * @defgroup GCR_SCON GCR_SCON 140 * @brief System Control. 141 * @{ 142 */ 143 #define MXC_F_GCR_SCON_BSTAPEN_POS 0 /**< SCON_BSTAPEN Position */ 144 #define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */ 145 146 #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ 147 #define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ 148 #define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ 149 #define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ 150 #define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ 151 #define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ 152 153 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ 154 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ 155 156 #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ 157 #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */ 158 159 #define MXC_F_GCR_SCON_DCACHE_FLUSH_POS 7 /**< SCON_DCACHE_FLUSH Position */ 160 #define MXC_F_GCR_SCON_DCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS)) /**< SCON_DCACHE_FLUSH Mask */ 161 162 #define MXC_F_GCR_SCON_SRCC_DIS_POS 9 /**< SCON_SRCC_DIS Position */ 163 #define MXC_F_GCR_SCON_SRCC_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SRCC_DIS_POS)) /**< SCON_SRCC_DIS Mask */ 164 165 #define MXC_F_GCR_SCON_CCHK_POS 13 /**< SCON_CCHK Position */ 166 #define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */ 167 168 #define MXC_F_GCR_SCON_CHKRES_POS 15 /**< SCON_CHKRES Position */ 169 #define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */ 170 171 #define MXC_F_GCR_SCON_OVR_POS 16 /**< SCON_OVR Position */ 172 #define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) /**< SCON_OVR Mask */ 173 #define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL) /**< SCON_OVR_0_9V Value */ 174 #define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0_9V Setting */ 175 #define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL) /**< SCON_OVR_1_0V Value */ 176 #define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_0V Setting */ 177 #define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL) /**< SCON_OVR_1_1V Value */ 178 #define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_1V Setting */ 179 180 /**@} end of group GCR_SCON_Register */ 181 182 /** 183 * @ingroup gcr_registers 184 * @defgroup GCR_RSTR0 GCR_RSTR0 185 * @brief Reset. 186 * @{ 187 */ 188 #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ 189 #define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ 190 191 #define MXC_F_GCR_RSTR0_WDT0_POS 1 /**< RSTR0_WDT0 Position */ 192 #define MXC_F_GCR_RSTR0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT0_POS)) /**< RSTR0_WDT0 Mask */ 193 194 #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ 195 #define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ 196 197 #define MXC_F_GCR_RSTR0_GPIO1_POS 3 /**< RSTR0_GPIO1 Position */ 198 #define MXC_F_GCR_RSTR0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) /**< RSTR0_GPIO1 Mask */ 199 200 #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ 201 #define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ 202 203 #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ 204 #define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ 205 206 #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ 207 #define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ 208 209 #define MXC_F_GCR_RSTR0_TIMER3_POS 8 /**< RSTR0_TIMER3 Position */ 210 #define MXC_F_GCR_RSTR0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) /**< RSTR0_TIMER3 Mask */ 211 212 #define MXC_F_GCR_RSTR0_TIMER4_POS 9 /**< RSTR0_TIMER4 Position */ 213 #define MXC_F_GCR_RSTR0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER4_POS)) /**< RSTR0_TIMER4 Mask */ 214 215 #define MXC_F_GCR_RSTR0_TIMER5_POS 10 /**< RSTR0_TIMER5 Position */ 216 #define MXC_F_GCR_RSTR0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER5_POS)) /**< RSTR0_TIMER5 Mask */ 217 218 #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ 219 #define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ 220 221 #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ 222 #define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */ 223 224 #define MXC_F_GCR_RSTR0_SPI1_POS 13 /**< RSTR0_SPI1 Position */ 225 #define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */ 226 227 #define MXC_F_GCR_RSTR0_SPI2_POS 14 /**< RSTR0_SPI2 Position */ 228 #define MXC_F_GCR_RSTR0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI2_POS)) /**< RSTR0_SPI2 Mask */ 229 230 #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ 231 #define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */ 232 233 #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ 234 #define MXC_F_GCR_RSTR0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */ 235 236 #define MXC_F_GCR_RSTR0_CRYPTO_POS 18 /**< RSTR0_CRYPTO Position */ 237 #define MXC_F_GCR_RSTR0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) /**< RSTR0_CRYPTO Mask */ 238 239 #define MXC_F_GCR_RSTR0_SMPHR_POS 22 /**< RSTR0_SMPHR Position */ 240 #define MXC_F_GCR_RSTR0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) /**< RSTR0_SMPHR Mask */ 241 242 #define MXC_F_GCR_RSTR0_USB_POS 23 /**< RSTR0_USB Position */ 243 #define MXC_F_GCR_RSTR0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_USB_POS)) /**< RSTR0_USB Mask */ 244 245 #define MXC_F_GCR_RSTR0_ADC_POS 26 /**< RSTR0_ADC Position */ 246 #define MXC_F_GCR_RSTR0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_ADC_POS)) /**< RSTR0_ADC Mask */ 247 248 #define MXC_F_GCR_RSTR0_DMA1_POS 27 /**< RSTR0_DMA1 Position */ 249 #define MXC_F_GCR_RSTR0_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA1_POS)) /**< RSTR0_DMA1 Mask */ 250 251 #define MXC_F_GCR_RSTR0_UART2_POS 28 /**< RSTR0_UART2 Position */ 252 #define MXC_F_GCR_RSTR0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART2_POS)) /**< RSTR0_UART2 Mask */ 253 254 #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ 255 #define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */ 256 257 #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ 258 #define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */ 259 260 #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ 261 #define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ 262 263 /**@} end of group GCR_RSTR0_Register */ 264 265 /** 266 * @ingroup gcr_registers 267 * @defgroup GCR_CLKCN GCR_CLKCN 268 * @brief Clock Control. 269 * @{ 270 */ 271 #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ 272 #define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ 273 #define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */ 274 #define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ 275 #define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */ 276 #define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ 277 #define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */ 278 #define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ 279 #define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */ 280 #define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ 281 #define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ 282 #define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */ 283 #define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ 284 #define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */ 285 #define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ 286 #define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */ 287 #define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ 288 #define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ 289 290 #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ 291 #define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ 292 #define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ 293 #define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ 294 #define MXC_V_GCR_CLKCN_CLKSEL_XTAL32M ((uint32_t)0x2UL) /**< CLKCN_CLKSEL_XTAL32M Value */ 295 #define MXC_S_GCR_CLKCN_CLKSEL_XTAL32M (MXC_V_GCR_CLKCN_CLKSEL_XTAL32M << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_XTAL32M Setting */ 296 #define MXC_V_GCR_CLKCN_CLKSEL_LIRC8 ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_LIRC8 Value */ 297 #define MXC_S_GCR_CLKCN_CLKSEL_LIRC8 (MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_LIRC8 Setting */ 298 #define MXC_V_GCR_CLKCN_CLKSEL_HIRC96 ((uint32_t)0x4UL) /**< CLKCN_CLKSEL_HIRC96 Value */ 299 #define MXC_S_GCR_CLKCN_CLKSEL_HIRC96 (MXC_V_GCR_CLKCN_CLKSEL_HIRC96 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC96 Setting */ 300 #define MXC_V_GCR_CLKCN_CLKSEL_HIRC8 ((uint32_t)0x5UL) /**< CLKCN_CLKSEL_HIRC8 Value */ 301 #define MXC_S_GCR_CLKCN_CLKSEL_HIRC8 (MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC8 Setting */ 302 #define MXC_V_GCR_CLKCN_CLKSEL_XTAL32K ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_XTAL32K Value */ 303 #define MXC_S_GCR_CLKCN_CLKSEL_XTAL32K (MXC_V_GCR_CLKCN_CLKSEL_XTAL32K << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_XTAL32K Setting */ 304 305 #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ 306 #define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ 307 308 #define MXC_F_GCR_CLKCN_CCD_POS 15 /**< CLKCN_CCD Position */ 309 #define MXC_F_GCR_CLKCN_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CCD_POS)) /**< CLKCN_CCD Mask */ 310 311 #define MXC_F_GCR_CLKCN_X32M_EN_POS 16 /**< CLKCN_X32M_EN Position */ 312 #define MXC_F_GCR_CLKCN_X32M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32M_EN_POS)) /**< CLKCN_X32M_EN Mask */ 313 314 #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ 315 #define MXC_F_GCR_CLKCN_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */ 316 317 #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ 318 #define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ 319 320 #define MXC_F_GCR_CLKCN_HIRC96M_EN_POS 19 /**< CLKCN_HIRC96M_EN Position */ 321 #define MXC_F_GCR_CLKCN_HIRC96M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC96M_EN_POS)) /**< CLKCN_HIRC96M_EN Mask */ 322 323 #define MXC_F_GCR_CLKCN_HIRC8M_EN_POS 20 /**< CLKCN_HIRC8M_EN Position */ 324 #define MXC_F_GCR_CLKCN_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) /**< CLKCN_HIRC8M_EN Mask */ 325 326 #define MXC_F_GCR_CLKCN_HIRC8M_VS_POS 21 /**< CLKCN_HIRC8M_VS Position */ 327 #define MXC_F_GCR_CLKCN_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) /**< CLKCN_HIRC8M_VS Mask */ 328 329 #define MXC_F_GCR_CLKCN_X32M_RDY_POS 24 /**< CLKCN_X32M_RDY Position */ 330 #define MXC_F_GCR_CLKCN_X32M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32M_RDY_POS)) /**< CLKCN_X32M_RDY Mask */ 331 332 #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ 333 #define MXC_F_GCR_CLKCN_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */ 334 335 #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ 336 #define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ 337 338 #define MXC_F_GCR_CLKCN_HIRC96M_RDY_POS 27 /**< CLKCN_HIRC96M_RDY Position */ 339 #define MXC_F_GCR_CLKCN_HIRC96M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC96M_RDY_POS)) /**< CLKCN_HIRC96M_RDY Mask */ 340 341 #define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS 28 /**< CLKCN_HIRC8M_RDY Position */ 342 #define MXC_F_GCR_CLKCN_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) /**< CLKCN_HIRC8M_RDY Mask */ 343 344 /**@} end of group GCR_CLKCN_Register */ 345 346 /** 347 * @ingroup gcr_registers 348 * @defgroup GCR_PM GCR_PM 349 * @brief Power Management. 350 * @{ 351 */ 352 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 353 #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 354 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 355 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 356 #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ 357 #define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ 358 #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ 359 #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ 360 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 361 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 362 363 #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ 364 #define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ 365 366 #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ 367 #define MXC_F_GCR_PM_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */ 368 369 #define MXC_F_GCR_PM_USBWKEN_POS 6 /**< PM_USBWKEN Position */ 370 #define MXC_F_GCR_PM_USBWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_USBWKEN_POS)) /**< PM_USBWKEN Mask */ 371 372 #define MXC_F_GCR_PM_WUTWKEN_POS 7 /**< PM_WUTWKEN Position */ 373 #define MXC_F_GCR_PM_WUTWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUTWKEN_POS)) /**< PM_WUTWKEN Mask */ 374 375 #define MXC_F_GCR_PM_COMPWKEN_POS 8 /**< PM_COMPWKEN Position */ 376 #define MXC_F_GCR_PM_COMPWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_COMPWKEN_POS)) /**< PM_COMPWKEN Mask */ 377 378 #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ 379 #define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ 380 381 #define MXC_F_GCR_PM_HIRC96MPD_POS 16 /**< PM_HIRC96MPD Position */ 382 #define MXC_F_GCR_PM_HIRC96MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC96MPD_POS)) /**< PM_HIRC96MPD Mask */ 383 384 #define MXC_F_GCR_PM_HIRC8MPD_POS 17 /**< PM_HIRC8MPD Position */ 385 #define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */ 386 387 #define MXC_F_GCR_PM_XTALPB_POS 20 /**< PM_XTALPB Position */ 388 #define MXC_F_GCR_PM_XTALPB ((uint32_t)(0x1UL << MXC_F_GCR_PM_XTALPB_POS)) /**< PM_XTALPB Mask */ 389 390 /**@} end of group GCR_PM_Register */ 391 392 /** 393 * @ingroup gcr_registers 394 * @defgroup GCR_PCKDIV GCR_PCKDIV 395 * @brief Peripheral Clock Divider. 396 * @{ 397 */ 398 #define MXC_F_GCR_PCKDIV_SDHCFRQ_POS 7 /**< PCKDIV_SDHCFRQ Position */ 399 #define MXC_F_GCR_PCKDIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_SDHCFRQ_POS)) /**< PCKDIV_SDHCFRQ Mask */ 400 401 #define MXC_F_GCR_PCKDIV_ADCFRQ_POS 10 /**< PCKDIV_ADCFRQ Position */ 402 #define MXC_F_GCR_PCKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCKDIV_ADCFRQ_POS)) /**< PCKDIV_ADCFRQ Mask */ 403 404 #define MXC_F_GCR_PCKDIV_AONCD_POS 14 /**< PCKDIV_AONCD Position */ 405 #define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ 406 #define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ 407 #define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ 408 #define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ 409 #define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ 410 #define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ 411 #define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ 412 #define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ 413 #define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ 414 415 /**@} end of group GCR_PCKDIV_Register */ 416 417 /** 418 * @ingroup gcr_registers 419 * @defgroup GCR_PERCKCN0 GCR_PERCKCN0 420 * @brief Peripheral Clock Disable. 421 * @{ 422 */ 423 #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ 424 #define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */ 425 426 #define MXC_F_GCR_PERCKCN0_GPIO1D_POS 1 /**< PERCKCN0_GPIO1D Position */ 427 #define MXC_F_GCR_PERCKCN0_GPIO1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) /**< PERCKCN0_GPIO1D Mask */ 428 429 #define MXC_F_GCR_PERCKCN0_USBD_POS 3 /**< PERCKCN0_USBD Position */ 430 #define MXC_F_GCR_PERCKCN0_USBD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_USBD_POS)) /**< PERCKCN0_USBD Mask */ 431 432 #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ 433 #define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ 434 435 #define MXC_F_GCR_PERCKCN0_SPI1D_POS 6 /**< PERCKCN0_SPI1D Position */ 436 #define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ 437 438 #define MXC_F_GCR_PERCKCN0_SPI2D_POS 7 /**< PERCKCN0_SPI2D Position */ 439 #define MXC_F_GCR_PERCKCN0_SPI2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI2D_POS)) /**< PERCKCN0_SPI2D Mask */ 440 441 #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ 442 #define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */ 443 444 #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ 445 #define MXC_F_GCR_PERCKCN0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */ 446 447 #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ 448 #define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ 449 450 #define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */ 451 #define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */ 452 453 #define MXC_F_GCR_PERCKCN0_TIMER0D_POS 15 /**< PERCKCN0_TIMER0D Position */ 454 #define MXC_F_GCR_PERCKCN0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER0D_POS)) /**< PERCKCN0_TIMER0D Mask */ 455 456 #define MXC_F_GCR_PERCKCN0_TIMER1D_POS 16 /**< PERCKCN0_TIMER1D Position */ 457 #define MXC_F_GCR_PERCKCN0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER1D_POS)) /**< PERCKCN0_TIMER1D Mask */ 458 459 #define MXC_F_GCR_PERCKCN0_TIMER2D_POS 17 /**< PERCKCN0_TIMER2D Position */ 460 #define MXC_F_GCR_PERCKCN0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER2D_POS)) /**< PERCKCN0_TIMER2D Mask */ 461 462 #define MXC_F_GCR_PERCKCN0_TIMER3D_POS 18 /**< PERCKCN0_TIMER3D Position */ 463 #define MXC_F_GCR_PERCKCN0_TIMER3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER3D_POS)) /**< PERCKCN0_TIMER3D Mask */ 464 465 #define MXC_F_GCR_PERCKCN0_TIMER4D_POS 19 /**< PERCKCN0_TIMER4D Position */ 466 #define MXC_F_GCR_PERCKCN0_TIMER4D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER4D_POS)) /**< PERCKCN0_TIMER4D Mask */ 467 468 #define MXC_F_GCR_PERCKCN0_TIMER5D_POS 20 /**< PERCKCN0_TIMER5D Position */ 469 #define MXC_F_GCR_PERCKCN0_TIMER5D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER5D_POS)) /**< PERCKCN0_TIMER5D Mask */ 470 471 #define MXC_F_GCR_PERCKCN0_ADCD_POS 23 /**< PERCKCN0_ADCD Position */ 472 #define MXC_F_GCR_PERCKCN0_ADCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_ADCD_POS)) /**< PERCKCN0_ADCD Mask */ 473 474 #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ 475 #define MXC_F_GCR_PERCKCN0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */ 476 477 #define MXC_F_GCR_PERCKCN0_PTD_POS 29 /**< PERCKCN0_PTD Position */ 478 #define MXC_F_GCR_PERCKCN0_PTD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_PTD_POS)) /**< PERCKCN0_PTD Mask */ 479 480 #define MXC_F_GCR_PERCKCN0_SPIXIPD_POS 30 /**< PERCKCN0_SPIXIPD Position */ 481 #define MXC_F_GCR_PERCKCN0_SPIXIPD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPIXIPD_POS)) /**< PERCKCN0_SPIXIPD Mask */ 482 483 #define MXC_F_GCR_PERCKCN0_SPIMD_POS 31 /**< PERCKCN0_SPIMD Position */ 484 #define MXC_F_GCR_PERCKCN0_SPIMD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPIMD_POS)) /**< PERCKCN0_SPIMD Mask */ 485 486 /**@} end of group GCR_PERCKCN0_Register */ 487 488 /** 489 * @ingroup gcr_registers 490 * @defgroup GCR_MEMCKCN GCR_MEMCKCN 491 * @brief Memory Clock Control Register. 492 * @{ 493 */ 494 #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ 495 #define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ 496 497 #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 16 /**< MEMCKCN_SYSRAM0LS Position */ 498 #define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */ 499 500 #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 17 /**< MEMCKCN_SYSRAM1LS Position */ 501 #define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */ 502 503 #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 18 /**< MEMCKCN_SYSRAM2LS Position */ 504 #define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */ 505 506 #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 19 /**< MEMCKCN_SYSRAM3LS Position */ 507 #define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */ 508 509 #define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS 20 /**< MEMCKCN_SYSRAM4LS Position */ 510 #define MXC_F_GCR_MEMCKCN_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) /**< MEMCKCN_SYSRAM4LS Mask */ 511 512 #define MXC_F_GCR_MEMCKCN_SYSRAM5LS_POS 21 /**< MEMCKCN_SYSRAM5LS Position */ 513 #define MXC_F_GCR_MEMCKCN_SYSRAM5LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM5LS_POS)) /**< MEMCKCN_SYSRAM5LS Mask */ 514 515 #define MXC_F_GCR_MEMCKCN_SYSRAM6LS_POS 22 /**< MEMCKCN_SYSRAM6LS Position */ 516 #define MXC_F_GCR_MEMCKCN_SYSRAM6LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM6LS_POS)) /**< MEMCKCN_SYSRAM6LS Mask */ 517 518 #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 24 /**< MEMCKCN_ICACHELS Position */ 519 #define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */ 520 521 #define MXC_F_GCR_MEMCKCN_ICACHEXIPLS_POS 25 /**< MEMCKCN_ICACHEXIPLS Position */ 522 #define MXC_F_GCR_MEMCKCN_ICACHEXIPLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHEXIPLS_POS)) /**< MEMCKCN_ICACHEXIPLS Mask */ 523 524 #define MXC_F_GCR_MEMCKCN_SCACHELS_POS 26 /**< MEMCKCN_SCACHELS Position */ 525 #define MXC_F_GCR_MEMCKCN_SCACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SCACHELS_POS)) /**< MEMCKCN_SCACHELS Mask */ 526 527 #define MXC_F_GCR_MEMCKCN_CRYPTOLS_POS 27 /**< MEMCKCN_CRYPTOLS Position */ 528 #define MXC_F_GCR_MEMCKCN_CRYPTOLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_CRYPTOLS_POS)) /**< MEMCKCN_CRYPTOLS Mask */ 529 530 #define MXC_F_GCR_MEMCKCN_USBLS_POS 28 /**< MEMCKCN_USBLS Position */ 531 #define MXC_F_GCR_MEMCKCN_USBLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_USBLS_POS)) /**< MEMCKCN_USBLS Mask */ 532 533 #define MXC_F_GCR_MEMCKCN_ROM0LS_POS 29 /**< MEMCKCN_ROM0LS Position */ 534 #define MXC_F_GCR_MEMCKCN_ROM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROM0LS_POS)) /**< MEMCKCN_ROM0LS Mask */ 535 536 #define MXC_F_GCR_MEMCKCN_ROM1LS_POS 30 /**< MEMCKCN_ROM1LS Position */ 537 #define MXC_F_GCR_MEMCKCN_ROM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROM1LS_POS)) /**< MEMCKCN_ROM1LS Mask */ 538 539 #define MXC_F_GCR_MEMCKCN_ICACHE1LS_POS 31 /**< MEMCKCN_ICACHE1LS Position */ 540 #define MXC_F_GCR_MEMCKCN_ICACHE1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHE1LS_POS)) /**< MEMCKCN_ICACHE1LS Mask */ 541 542 /**@} end of group GCR_MEMCKCN_Register */ 543 544 /** 545 * @ingroup gcr_registers 546 * @defgroup GCR_MEMZCN GCR_MEMZCN 547 * @brief Memory Zeroize Control. 548 * @{ 549 */ 550 #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ 551 #define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ 552 553 #define MXC_F_GCR_MEMZCN_SRAM1Z_POS 1 /**< MEMZCN_SRAM1Z Position */ 554 #define MXC_F_GCR_MEMZCN_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) /**< MEMZCN_SRAM1Z Mask */ 555 556 #define MXC_F_GCR_MEMZCN_SRAM2_POS 2 /**< MEMZCN_SRAM2 Position */ 557 #define MXC_F_GCR_MEMZCN_SRAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2_POS)) /**< MEMZCN_SRAM2 Mask */ 558 559 #define MXC_F_GCR_MEMZCN_SRAM3Z_POS 3 /**< MEMZCN_SRAM3Z Position */ 560 #define MXC_F_GCR_MEMZCN_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) /**< MEMZCN_SRAM3Z Mask */ 561 562 #define MXC_F_GCR_MEMZCN_SRAM4Z_POS 4 /**< MEMZCN_SRAM4Z Position */ 563 #define MXC_F_GCR_MEMZCN_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) /**< MEMZCN_SRAM4Z Mask */ 564 565 #define MXC_F_GCR_MEMZCN_SRAM5Z_POS 5 /**< MEMZCN_SRAM5Z Position */ 566 #define MXC_F_GCR_MEMZCN_SRAM5Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM5Z_POS)) /**< MEMZCN_SRAM5Z Mask */ 567 568 #define MXC_F_GCR_MEMZCN_SRAM6Z_POS 6 /**< MEMZCN_SRAM6Z Position */ 569 #define MXC_F_GCR_MEMZCN_SRAM6Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM6Z_POS)) /**< MEMZCN_SRAM6Z Mask */ 570 571 #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 8 /**< MEMZCN_ICACHEZ Position */ 572 #define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ 573 574 #define MXC_F_GCR_MEMZCN_ICACHEXIPZ_POS 9 /**< MEMZCN_ICACHEXIPZ Position */ 575 #define MXC_F_GCR_MEMZCN_ICACHEXIPZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEXIPZ_POS)) /**< MEMZCN_ICACHEXIPZ Mask */ 576 577 #define MXC_F_GCR_MEMZCN_SCACHEDATAZ_POS 10 /**< MEMZCN_SCACHEDATAZ Position */ 578 #define MXC_F_GCR_MEMZCN_SCACHEDATAZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SCACHEDATAZ_POS)) /**< MEMZCN_SCACHEDATAZ Mask */ 579 580 #define MXC_F_GCR_MEMZCN_SCACHETAGZ_POS 11 /**< MEMZCN_SCACHETAGZ Position */ 581 #define MXC_F_GCR_MEMZCN_SCACHETAGZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SCACHETAGZ_POS)) /**< MEMZCN_SCACHETAGZ Mask */ 582 583 #define MXC_F_GCR_MEMZCN_CRYPTOZ_POS 12 /**< MEMZCN_CRYPTOZ Position */ 584 #define MXC_F_GCR_MEMZCN_CRYPTOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_CRYPTOZ_POS)) /**< MEMZCN_CRYPTOZ Mask */ 585 586 #define MXC_F_GCR_MEMZCN_USBFIFOZ_POS 13 /**< MEMZCN_USBFIFOZ Position */ 587 #define MXC_F_GCR_MEMZCN_USBFIFOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_USBFIFOZ_POS)) /**< MEMZCN_USBFIFOZ Mask */ 588 589 #define MXC_F_GCR_MEMZCN_ICACHE1Z_POS 14 /**< MEMZCN_ICACHE1Z Position */ 590 #define MXC_F_GCR_MEMZCN_ICACHE1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHE1Z_POS)) /**< MEMZCN_ICACHE1Z Mask */ 591 592 /**@} end of group GCR_MEMZCN_Register */ 593 594 /** 595 * @ingroup gcr_registers 596 * @defgroup GCR_SYSST GCR_SYSST 597 * @brief System Status Register. 598 * @{ 599 */ 600 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 601 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 602 603 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ 604 #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ 605 606 #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ 607 #define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ 608 609 /**@} end of group GCR_SYSST_Register */ 610 611 /** 612 * @ingroup gcr_registers 613 * @defgroup GCR_RSTR1 GCR_RSTR1 614 * @brief Reset 1. 615 * @{ 616 */ 617 #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */ 618 #define MXC_F_GCR_RSTR1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */ 619 620 #define MXC_F_GCR_RSTR1_PT_POS 1 /**< RSTR1_PT Position */ 621 #define MXC_F_GCR_RSTR1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PT_POS)) /**< RSTR1_PT Mask */ 622 623 #define MXC_F_GCR_RSTR1_SPIXIP_POS 3 /**< RSTR1_SPIXIP Position */ 624 #define MXC_F_GCR_RSTR1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXIP_POS)) /**< RSTR1_SPIXIP Mask */ 625 626 #define MXC_F_GCR_RSTR1_XSPIM_POS 4 /**< RSTR1_XSPIM Position */ 627 #define MXC_F_GCR_RSTR1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_XSPIM_POS)) /**< RSTR1_XSPIM Mask */ 628 629 #define MXC_F_GCR_RSTR1_SDHC_POS 6 /**< RSTR1_SDHC Position */ 630 #define MXC_F_GCR_RSTR1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SDHC_POS)) /**< RSTR1_SDHC Mask */ 631 632 #define MXC_F_GCR_RSTR1_OWIRE_POS 7 /**< RSTR1_OWIRE Position */ 633 #define MXC_F_GCR_RSTR1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_OWIRE_POS)) /**< RSTR1_OWIRE Mask */ 634 635 #define MXC_F_GCR_RSTR1_WDT1_POS 8 /**< RSTR1_WDT1 Position */ 636 #define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */ 637 638 #define MXC_F_GCR_RSTR1_SPI0_POS 9 /**< RSTR1_SPI0 Position */ 639 #define MXC_F_GCR_RSTR1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPI0_POS)) /**< RSTR1_SPI0 Mask */ 640 641 #define MXC_F_GCR_RSTR1_SPIXMEM_POS 15 /**< RSTR1_SPIXMEM Position */ 642 #define MXC_F_GCR_RSTR1_SPIXMEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXMEM_POS)) /**< RSTR1_SPIXMEM Mask */ 643 644 #define MXC_F_GCR_RSTR1_SMPHR_POS 16 /**< RSTR1_SMPHR Position */ 645 #define MXC_F_GCR_RSTR1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SMPHR_POS)) /**< RSTR1_SMPHR Mask */ 646 647 #define MXC_F_GCR_RSTR1_WDT2_POS 17 /**< RSTR1_WDT2 Position */ 648 #define MXC_F_GCR_RSTR1_WDT2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT2_POS)) /**< RSTR1_WDT2 Mask */ 649 650 #define MXC_F_GCR_RSTR1_BTLE_POS 18 /**< RSTR1_BTLE Position */ 651 #define MXC_F_GCR_RSTR1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_BTLE_POS)) /**< RSTR1_BTLE Mask */ 652 653 #define MXC_F_GCR_RSTR1_AUDIO_POS 19 /**< RSTR1_AUDIO Position */ 654 #define MXC_F_GCR_RSTR1_AUDIO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_AUDIO_POS)) /**< RSTR1_AUDIO Mask */ 655 656 #define MXC_F_GCR_RSTR1_I2C2_POS 20 /**< RSTR1_I2C2 Position */ 657 #define MXC_F_GCR_RSTR1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C2_POS)) /**< RSTR1_I2C2 Mask */ 658 659 #define MXC_F_GCR_RSTR1_RPU_POS 21 /**< RSTR1_RPU Position */ 660 #define MXC_F_GCR_RSTR1_RPU ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_RPU_POS)) /**< RSTR1_RPU Mask */ 661 662 #define MXC_F_GCR_RSTR1_HTMR0_POS 22 /**< RSTR1_HTMR0 Position */ 663 #define MXC_F_GCR_RSTR1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR0_POS)) /**< RSTR1_HTMR0 Mask */ 664 665 #define MXC_F_GCR_RSTR1_HTMR1_POS 23 /**< RSTR1_HTMR1 Position */ 666 #define MXC_F_GCR_RSTR1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR1_POS)) /**< RSTR1_HTMR1 Mask */ 667 668 #define MXC_F_GCR_RSTR1_DVS_POS 24 /**< RSTR1_DVS Position */ 669 #define MXC_F_GCR_RSTR1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_DVS_POS)) /**< RSTR1_DVS Mask */ 670 671 #define MXC_F_GCR_RSTR1_SIMO_POS 25 /**< RSTR1_SIMO Position */ 672 #define MXC_F_GCR_RSTR1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SIMO_POS)) /**< RSTR1_SIMO Mask */ 673 674 /**@} end of group GCR_RSTR1_Register */ 675 676 /** 677 * @ingroup gcr_registers 678 * @defgroup GCR_PERCKCN1 GCR_PERCKCN1 679 * @brief Peripheral Clock Disable. 680 * @{ 681 */ 682 #define MXC_F_GCR_PERCKCN1_BTLED_POS 0 /**< PERCKCN1_BTLED Position */ 683 #define MXC_F_GCR_PERCKCN1_BTLED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_BTLED_POS)) /**< PERCKCN1_BTLED Mask */ 684 685 #define MXC_F_GCR_PERCKCN1_UART2D_POS 1 /**< PERCKCN1_UART2D Position */ 686 #define MXC_F_GCR_PERCKCN1_UART2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_UART2D_POS)) /**< PERCKCN1_UART2D Mask */ 687 688 #define MXC_F_GCR_PERCKCN1_TRNGD_POS 2 /**< PERCKCN1_TRNGD Position */ 689 #define MXC_F_GCR_PERCKCN1_TRNGD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) /**< PERCKCN1_TRNGD Mask */ 690 691 #define MXC_F_GCR_PERCKCN1_SCACHED_POS 7 /**< PERCKCN1_SCACHED Position */ 692 #define MXC_F_GCR_PERCKCN1_SCACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SCACHED_POS)) /**< PERCKCN1_SCACHED Mask */ 693 694 #define MXC_F_GCR_PERCKCN1_SDMAD_POS 8 /**< PERCKCN1_SDMAD Position */ 695 #define MXC_F_GCR_PERCKCN1_SDMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SDMAD_POS)) /**< PERCKCN1_SDMAD Mask */ 696 697 #define MXC_F_GCR_PERCKCN1_SMPHRD_POS 9 /**< PERCKCN1_SMPHRD Position */ 698 #define MXC_F_GCR_PERCKCN1_SMPHRD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SMPHRD_POS)) /**< PERCKCN1_SMPHRD Mask */ 699 700 #define MXC_F_GCR_PERCKCN1_SDHCD_POS 10 /**< PERCKCN1_SDHCD Position */ 701 #define MXC_F_GCR_PERCKCN1_SDHCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SDHCD_POS)) /**< PERCKCN1_SDHCD Mask */ 702 703 #define MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS 12 /**< PERCKCN1_ICACHEXIPD Position */ 704 #define MXC_F_GCR_PERCKCN1_ICACHEXIPD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS)) /**< PERCKCN1_ICACHEXIPD Mask */ 705 706 #define MXC_F_GCR_PERCKCN1_OWIRED_POS 13 /**< PERCKCN1_OWIRED Position */ 707 #define MXC_F_GCR_PERCKCN1_OWIRED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_OWIRED_POS)) /**< PERCKCN1_OWIRED Mask */ 708 709 #define MXC_F_GCR_PERCKCN1_SPI0D_POS 14 /**< PERCKCN1_SPI0D Position */ 710 #define MXC_F_GCR_PERCKCN1_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPI0D_POS)) /**< PERCKCN1_SPI0D Mask */ 711 712 #define MXC_F_GCR_PERCKCN1_SPIXIPDD_POS 20 /**< PERCKCN1_SPIXIPDD Position */ 713 #define MXC_F_GCR_PERCKCN1_SPIXIPDD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPIXIPDD_POS)) /**< PERCKCN1_SPIXIPDD Mask */ 714 715 #define MXC_F_GCR_PERCKCN1_DMA1D_POS 21 /**< PERCKCN1_DMA1D Position */ 716 #define MXC_F_GCR_PERCKCN1_DMA1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_DMA1D_POS)) /**< PERCKCN1_DMA1D Mask */ 717 718 #define MXC_F_GCR_PERCKCN1_AUDIOD_POS 23 /**< PERCKCN1_AUDIOD Position */ 719 #define MXC_F_GCR_PERCKCN1_AUDIOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_AUDIOD_POS)) /**< PERCKCN1_AUDIOD Mask */ 720 721 #define MXC_F_GCR_PERCKCN1_I2C2D_POS 24 /**< PERCKCN1_I2C2D Position */ 722 #define MXC_F_GCR_PERCKCN1_I2C2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_I2C2D_POS)) /**< PERCKCN1_I2C2D Mask */ 723 724 #define MXC_F_GCR_PERCKCN1_HTMR0D_POS 25 /**< PERCKCN1_HTMR0D Position */ 725 #define MXC_F_GCR_PERCKCN1_HTMR0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_HTMR0D_POS)) /**< PERCKCN1_HTMR0D Mask */ 726 727 #define MXC_F_GCR_PERCKCN1_HTMR1D_POS 26 /**< PERCKCN1_HTMR1D Position */ 728 #define MXC_F_GCR_PERCKCN1_HTMR1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_HTMR1D_POS)) /**< PERCKCN1_HTMR1D Mask */ 729 730 #define MXC_F_GCR_PERCKCN1_WDT0D_POS 27 /**< PERCKCN1_WDT0D Position */ 731 #define MXC_F_GCR_PERCKCN1_WDT0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT0D_POS)) /**< PERCKCN1_WDT0D Mask */ 732 733 #define MXC_F_GCR_PERCKCN1_WDT1D_POS 28 /**< PERCKCN1_WDT1D Position */ 734 #define MXC_F_GCR_PERCKCN1_WDT1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT1D_POS)) /**< PERCKCN1_WDT1D Mask */ 735 736 #define MXC_F_GCR_PERCKCN1_WDT2D_POS 29 /**< PERCKCN1_WDT2D Position */ 737 #define MXC_F_GCR_PERCKCN1_WDT2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT2D_POS)) /**< PERCKCN1_WDT2D Mask */ 738 739 #define MXC_F_GCR_PERCKCN1_CPU1D_POS 31 /**< PERCKCN1_CPU1D Position */ 740 #define MXC_F_GCR_PERCKCN1_CPU1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CPU1D_POS)) /**< PERCKCN1_CPU1D Mask */ 741 742 /**@} end of group GCR_PERCKCN1_Register */ 743 744 /** 745 * @ingroup gcr_registers 746 * @defgroup GCR_EVENT_EN GCR_EVENT_EN 747 * @brief Event Enable Register. 748 * @{ 749 */ 750 #define MXC_F_GCR_EVENT_EN_CPU0DMAEVENT_POS 0 /**< EVENT_EN_CPU0DMAEVENT Position */ 751 #define MXC_F_GCR_EVENT_EN_CPU0DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMAEVENT_POS)) /**< EVENT_EN_CPU0DMAEVENT Mask */ 752 753 #define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS 1 /**< EVENT_EN_CPU0DMA1EVENT Position */ 754 #define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS)) /**< EVENT_EN_CPU0DMA1EVENT Mask */ 755 756 #define MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS 2 /**< EVENT_EN_CPU0TXEVENT Position */ 757 #define MXC_F_GCR_EVENT_EN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS)) /**< EVENT_EN_CPU0TXEVENT Mask */ 758 759 #define MXC_F_GCR_EVENT_EN_CPU1DMAEVENT_POS 3 /**< EVENT_EN_CPU1DMAEVENT Position */ 760 #define MXC_F_GCR_EVENT_EN_CPU1DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMAEVENT_POS)) /**< EVENT_EN_CPU1DMAEVENT Mask */ 761 762 #define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS 4 /**< EVENT_EN_CPU1DMA1EVENT Position */ 763 #define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS)) /**< EVENT_EN_CPU1DMA1EVENT Mask */ 764 765 #define MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS 5 /**< EVENT_EN_CPU1TXEVENT Position */ 766 #define MXC_F_GCR_EVENT_EN_CPU1TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS)) /**< EVENT_EN_CPU1TXEVENT Mask */ 767 768 /**@} end of group GCR_EVENT_EN_Register */ 769 770 /** 771 * @ingroup gcr_registers 772 * @defgroup GCR_REVISION GCR_REVISION 773 * @brief Revision Register. 774 * @{ 775 */ 776 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 777 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 778 779 /**@} end of group GCR_REVISION_Register */ 780 781 /** 782 * @ingroup gcr_registers 783 * @defgroup GCR_SYSSIE GCR_SYSSIE 784 * @brief System Status Interrupt Enable Register. 785 * @{ 786 */ 787 #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ 788 #define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ 789 790 #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ 791 #define MXC_F_GCR_SYSSIE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */ 792 793 #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ 794 #define MXC_F_GCR_SYSSIE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */ 795 796 /**@} end of group GCR_SYSSIE_Register */ 797 798 /** 799 * @ingroup gcr_registers 800 * @defgroup GCR_ECC_ER GCR_ECC_ER 801 * @brief ECC Error Register 802 * @{ 803 */ 804 #define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS 0 /**< ECC_ER_SYSRAM0ECCERR Position */ 805 #define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS)) /**< ECC_ER_SYSRAM0ECCERR Mask */ 806 807 #define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS 1 /**< ECC_ER_SYSRAM1ECCERR Position */ 808 #define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS)) /**< ECC_ER_SYSRAM1ECCERR Mask */ 809 810 #define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS 2 /**< ECC_ER_SYSRAM2ECCERR Position */ 811 #define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS)) /**< ECC_ER_SYSRAM2ECCERR Mask */ 812 813 #define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS 3 /**< ECC_ER_SYSRAM3ECCERR Position */ 814 #define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS)) /**< ECC_ER_SYSRAM3ECCERR Mask */ 815 816 #define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS 4 /**< ECC_ER_SYSRAM4ECCERR Position */ 817 #define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS)) /**< ECC_ER_SYSRAM4ECCERR Mask */ 818 819 #define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS 5 /**< ECC_ER_SYSRAM5ECCERR Position */ 820 #define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS)) /**< ECC_ER_SYSRAM5ECCERR Mask */ 821 822 #define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS 6 /**< ECC_ER_SYSRAM6ECCERR Position */ 823 #define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS)) /**< ECC_ER_SYSRAM6ECCERR Mask */ 824 825 #define MXC_F_GCR_ECC_ER_IC0ECCERR_POS 8 /**< ECC_ER_IC0ECCERR Position */ 826 #define MXC_F_GCR_ECC_ER_IC0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC0ECCERR_POS)) /**< ECC_ER_IC0ECCERR Mask */ 827 828 #define MXC_F_GCR_ECC_ER_IC1ECCERR_POS 9 /**< ECC_ER_IC1ECCERR Position */ 829 #define MXC_F_GCR_ECC_ER_IC1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC1ECCERR_POS)) /**< ECC_ER_IC1ECCERR Mask */ 830 831 #define MXC_F_GCR_ECC_ER_ICXIPECCERR_POS 10 /**< ECC_ER_ICXIPECCERR Position */ 832 #define MXC_F_GCR_ECC_ER_ICXIPECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_ICXIPECCERR_POS)) /**< ECC_ER_ICXIPECCERR Mask */ 833 834 #define MXC_F_GCR_ECC_ER_FL0ECCERR_POS 11 /**< ECC_ER_FL0ECCERR Position */ 835 #define MXC_F_GCR_ECC_ER_FL0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL0ECCERR_POS)) /**< ECC_ER_FL0ECCERR Mask */ 836 837 #define MXC_F_GCR_ECC_ER_FL1ECCERR_POS 12 /**< ECC_ER_FL1ECCERR Position */ 838 #define MXC_F_GCR_ECC_ER_FL1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL1ECCERR_POS)) /**< ECC_ER_FL1ECCERR Mask */ 839 840 /**@} end of group GCR_ECC_ER_Register */ 841 842 /** 843 * @ingroup gcr_registers 844 * @defgroup GCR_ECC_CED GCR_ECC_CED 845 * @brief ECC Correctable Error Detected Register 846 * @{ 847 */ 848 #define MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED_POS 0 /**< ECC_CED_SYSRAM0ECCNDED Position */ 849 #define MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED_POS)) /**< ECC_CED_SYSRAM0ECCNDED Mask */ 850 851 #define MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED_POS 1 /**< ECC_CED_SYSRAM1ECCNDED Position */ 852 #define MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED_POS)) /**< ECC_CED_SYSRAM1ECCNDED Mask */ 853 854 #define MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED_POS 2 /**< ECC_CED_SYSRAM2ECCNDED Position */ 855 #define MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED_POS)) /**< ECC_CED_SYSRAM2ECCNDED Mask */ 856 857 #define MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED_POS 3 /**< ECC_CED_SYSRAM3ECCNDED Position */ 858 #define MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED_POS)) /**< ECC_CED_SYSRAM3ECCNDED Mask */ 859 860 #define MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED_POS 4 /**< ECC_CED_SYSRAM4ECCNDED Position */ 861 #define MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED_POS)) /**< ECC_CED_SYSRAM4ECCNDED Mask */ 862 863 #define MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED_POS 5 /**< ECC_CED_SYSRAM5ECCNDED Position */ 864 #define MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED_POS)) /**< ECC_CED_SYSRAM5ECCNDED Mask */ 865 866 #define MXC_F_GCR_ECC_CED_IC0ECCNDED_POS 8 /**< ECC_CED_IC0ECCNDED Position */ 867 #define MXC_F_GCR_ECC_CED_IC0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC0ECCNDED_POS)) /**< ECC_CED_IC0ECCNDED Mask */ 868 869 #define MXC_F_GCR_ECC_CED_IC1ECCNDED_POS 9 /**< ECC_CED_IC1ECCNDED Position */ 870 #define MXC_F_GCR_ECC_CED_IC1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC1ECCNDED_POS)) /**< ECC_CED_IC1ECCNDED Mask */ 871 872 #define MXC_F_GCR_ECC_CED_ICXIPECCNDED_POS 10 /**< ECC_CED_ICXIPECCNDED Position */ 873 #define MXC_F_GCR_ECC_CED_ICXIPECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_ICXIPECCNDED_POS)) /**< ECC_CED_ICXIPECCNDED Mask */ 874 875 #define MXC_F_GCR_ECC_CED_FL0ECCNDED_POS 11 /**< ECC_CED_FL0ECCNDED Position */ 876 #define MXC_F_GCR_ECC_CED_FL0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL0ECCNDED_POS)) /**< ECC_CED_FL0ECCNDED Mask */ 877 878 #define MXC_F_GCR_ECC_CED_FL1ECCNDED_POS 12 /**< ECC_CED_FL1ECCNDED Position */ 879 #define MXC_F_GCR_ECC_CED_FL1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL1ECCNDED_POS)) /**< ECC_CED_FL1ECCNDED Mask */ 880 881 /**@} end of group GCR_ECC_CED_Register */ 882 883 /** 884 * @ingroup gcr_registers 885 * @defgroup GCR_ECC_IRQEN GCR_ECC_IRQEN 886 * @brief ECC IRQ Enable Register 887 * @{ 888 */ 889 #define MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN_POS 0 /**< ECC_IRQEN_SYSRAM0ECCEN Position */ 890 #define MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN_POS)) /**< ECC_IRQEN_SYSRAM0ECCEN Mask */ 891 892 #define MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN_POS 1 /**< ECC_IRQEN_SYSRAM1ECCEN Position */ 893 #define MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN_POS)) /**< ECC_IRQEN_SYSRAM1ECCEN Mask */ 894 895 #define MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN_POS 2 /**< ECC_IRQEN_SYSRAM2ECCEN Position */ 896 #define MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN_POS)) /**< ECC_IRQEN_SYSRAM2ECCEN Mask */ 897 898 #define MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN_POS 3 /**< ECC_IRQEN_SYSRAM3ECCEN Position */ 899 #define MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN_POS)) /**< ECC_IRQEN_SYSRAM3ECCEN Mask */ 900 901 #define MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN_POS 4 /**< ECC_IRQEN_SYSRAM4ECCEN Position */ 902 #define MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN_POS)) /**< ECC_IRQEN_SYSRAM4ECCEN Mask */ 903 904 #define MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN_POS 5 /**< ECC_IRQEN_SYSRAM5ECCEN Position */ 905 #define MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN_POS)) /**< ECC_IRQEN_SYSRAM5ECCEN Mask */ 906 907 #define MXC_F_GCR_ECC_IRQEN_IC0ECCEN_POS 8 /**< ECC_IRQEN_IC0ECCEN Position */ 908 #define MXC_F_GCR_ECC_IRQEN_IC0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_IC0ECCEN_POS)) /**< ECC_IRQEN_IC0ECCEN Mask */ 909 910 #define MXC_F_GCR_ECC_IRQEN_IC1ECCEN_POS 9 /**< ECC_IRQEN_IC1ECCEN Position */ 911 #define MXC_F_GCR_ECC_IRQEN_IC1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_IC1ECCEN_POS)) /**< ECC_IRQEN_IC1ECCEN Mask */ 912 913 #define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS 10 /**< ECC_IRQEN_ICXIPECCEN Position */ 914 #define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS)) /**< ECC_IRQEN_ICXIPECCEN Mask */ 915 916 #define MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS 11 /**< ECC_IRQEN_FL0ECCEN Position */ 917 #define MXC_F_GCR_ECC_IRQEN_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS)) /**< ECC_IRQEN_FL0ECCEN Mask */ 918 919 #define MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS 12 /**< ECC_IRQEN_FL1ECCEN Position */ 920 #define MXC_F_GCR_ECC_IRQEN_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS)) /**< ECC_IRQEN_FL1ECCEN Mask */ 921 922 /**@} end of group GCR_ECC_IRQEN_Register */ 923 924 /** 925 * @ingroup gcr_registers 926 * @defgroup GCR_ECC_ERRAD GCR_ECC_ERRAD 927 * @brief ECC Error Address Register 928 * @{ 929 */ 930 #define MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS 0 /**< ECC_ERRAD_DATARAMADDR Position */ 931 #define MXC_F_GCR_ECC_ERRAD_DATARAMADDR ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS)) /**< ECC_ERRAD_DATARAMADDR Mask */ 932 933 #define MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS 14 /**< ECC_ERRAD_DATARAMBANK Position */ 934 #define MXC_F_GCR_ECC_ERRAD_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS)) /**< ECC_ERRAD_DATARAMBANK Mask */ 935 936 #define MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS 15 /**< ECC_ERRAD_DATARAMERR Position */ 937 #define MXC_F_GCR_ECC_ERRAD_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS)) /**< ECC_ERRAD_DATARAMERR Mask */ 938 939 #define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS 16 /**< ECC_ERRAD_TAGRAMADDR Position */ 940 #define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS)) /**< ECC_ERRAD_TAGRAMADDR Mask */ 941 942 #define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS 30 /**< ECC_ERRAD_TAGRAMBANK Position */ 943 #define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS)) /**< ECC_ERRAD_TAGRAMBANK Mask */ 944 945 #define MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS 31 /**< ECC_ERRAD_TAGRAMERR Position */ 946 #define MXC_F_GCR_ECC_ERRAD_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS)) /**< ECC_ERRAD_TAGRAMERR Mask */ 947 948 /**@} end of group GCR_ECC_ERRAD_Register */ 949 950 /** 951 * @ingroup gcr_registers 952 * @defgroup GCR_BTLE_LDOCR GCR_BTLE_LDOCR 953 * @brief BTLE LDO Control Register 954 * @{ 955 */ 956 #define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 0 /**< BTLE_LDOCR_LDOTXEN Position */ 957 #define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) /**< BTLE_LDOCR_LDOTXEN Mask */ 958 959 #define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS 1 /**< BTLE_LDOCR_LDOTXOPULLD Position */ 960 #define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS)) /**< BTLE_LDOCR_LDOTXOPULLD Mask */ 961 962 #define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 2 /**< BTLE_LDOCR_LDOTXVSEL Position */ 963 #define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) /**< BTLE_LDOCR_LDOTXVSEL Mask */ 964 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Value */ 965 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Setting */ 966 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Value */ 967 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Setting */ 968 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Value */ 969 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Setting */ 970 #define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Value */ 971 #define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Setting */ 972 973 #define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 4 /**< BTLE_LDOCR_LDORXEN Position */ 974 #define MXC_F_GCR_BTLE_LDOCR_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS)) /**< BTLE_LDOCR_LDORXEN Mask */ 975 976 #define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS 5 /**< BTLE_LDOCR_LDORXPULLD Position */ 977 #define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS)) /**< BTLE_LDOCR_LDORXPULLD Mask */ 978 979 #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 6 /**< BTLE_LDOCR_LDORXVSEL Position */ 980 #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)) /**< BTLE_LDOCR_LDORXVSEL Mask */ 981 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDORXVSEL_0_7 Value */ 982 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_7 Setting */ 983 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDORXVSEL_0_85 Value */ 984 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_85 Setting */ 985 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDORXVSEL_0_9 Value */ 986 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_9 Setting */ 987 #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDORXVSEL_1_1 Value */ 988 #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_1_1 Setting */ 989 990 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 8 /**< BTLE_LDOCR_LDORXBYP Position */ 991 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) /**< BTLE_LDOCR_LDORXBYP Mask */ 992 993 #define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 9 /**< BTLE_LDOCR_LDORXDISCH Position */ 994 #define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) /**< BTLE_LDOCR_LDORXDISCH Mask */ 995 996 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 10 /**< BTLE_LDOCR_LDOTXBYP Position */ 997 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS)) /**< BTLE_LDOCR_LDOTXBYP Mask */ 998 999 #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 11 /**< BTLE_LDOCR_LDOTXDISCH Position */ 1000 #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS)) /**< BTLE_LDOCR_LDOTXDISCH Mask */ 1001 1002 #define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 12 /**< BTLE_LDOCR_LDOTXENDLY Position */ 1003 #define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) /**< BTLE_LDOCR_LDOTXENDLY Mask */ 1004 1005 #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 13 /**< BTLE_LDOCR_LDORXENDLY Position */ 1006 #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS)) /**< BTLE_LDOCR_LDORXENDLY Mask */ 1007 1008 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS 14 /**< BTLE_LDOCR_LDORXBYPENENDLY Position */ 1009 #define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDORXBYPENENDLY Mask */ 1010 1011 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS 15 /**< BTLE_LDOCR_LDOTXBYPENENDLY Position */ 1012 #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDOTXBYPENENDLY Mask */ 1013 1014 /**@} end of group GCR_BTLE_LDOCR_Register */ 1015 1016 /** 1017 * @ingroup gcr_registers 1018 * @defgroup GCR_BTLE_LDODCR GCR_BTLE_LDODCR 1019 * @brief BTLE LDO Delay Register 1020 * @{ 1021 */ 1022 #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS 0 /**< BTLE_LDODCR_BYPDLYCNT Position */ 1023 #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS)) /**< BTLE_LDODCR_BYPDLYCNT Mask */ 1024 1025 #define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 8 /**< BTLE_LDODCR_LDORXDLYCNT Position */ 1026 #define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) /**< BTLE_LDODCR_LDORXDLYCNT Mask */ 1027 1028 #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 20 /**< BTLE_LDODCR_LDOTXDLYCNT Position */ 1029 #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS)) /**< BTLE_LDODCR_LDOTXDLYCNT Mask */ 1030 1031 /**@} end of group GCR_BTLE_LDODCR_Register */ 1032 1033 /** 1034 * @ingroup gcr_registers 1035 * @defgroup GCR_GP0 GCR_GP0 1036 * @brief General Purpose Register 0 1037 * @{ 1038 */ 1039 #define MXC_F_GCR_GP0_GPR0_POS 0 /**< GP0_GPR0 Position */ 1040 #define MXC_F_GCR_GP0_GPR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_GP0_GPR0_POS)) /**< GP0_GPR0 Mask */ 1041 1042 /**@} end of group GCR_GP0_Register */ 1043 1044 /** 1045 * @ingroup gcr_registers 1046 * @defgroup GCR_APB_ASYNC GCR_APB_ASYNC 1047 * @brief APB Asynchronous Bridge Select Register 1048 * @{ 1049 */ 1050 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS 0 /**< APB_ASYNC_APBASYNCI2C0 Position */ 1051 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS)) /**< APB_ASYNC_APBASYNCI2C0 Mask */ 1052 1053 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS 1 /**< APB_ASYNC_APBASYNCI2C1 Position */ 1054 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS)) /**< APB_ASYNC_APBASYNCI2C1 Mask */ 1055 1056 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS 2 /**< APB_ASYNC_APBASYNCI2C2 Position */ 1057 #define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS)) /**< APB_ASYNC_APBASYNCI2C2 Mask */ 1058 1059 #define MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS 3 /**< APB_ASYNC_APBASYNCPT Position */ 1060 #define MXC_F_GCR_APB_ASYNC_APBASYNCPT ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS)) /**< APB_ASYNC_APBASYNCPT Mask */ 1061 1062 /**@} end of group GCR_APB_ASYNC_Register */ 1063 1064 #ifdef __cplusplus 1065 } 1066 #endif 1067 1068 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_ 1069
