1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 85 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 86 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 89 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 90 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 91 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 92 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 93 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 94 __R uint32_t rsv_0x58_0x63[3]; 95 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 96 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 97 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 98 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 99 __IO uint32_t btleldoctrl; /**< <tt>\b 0x74:</tt> GCR BTLELDOCTRL Register */ 100 __IO uint32_t btleldodly; /**< <tt>\b 0x78:</tt> GCR BTLELDODLY Register */ 101 __R uint32_t rsv_0x7c; 102 __IO uint32_t gpr0; /**< <tt>\b 0x80:</tt> GCR GPR0 Register */ 103 } mxc_gcr_regs_t; 104 105 /* Register offsets for module GCR */ 106 /** 107 * @ingroup gcr_registers 108 * @defgroup GCR_Register_Offsets Register Offsets 109 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 110 * @{ 111 */ 112 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 113 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 114 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 115 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 116 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 117 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 118 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 119 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 120 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 122 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 123 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 124 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 125 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 126 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 127 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 128 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 129 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 130 #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: <tt> 0x0074</tt> */ 131 #define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: <tt> 0x0078</tt> */ 132 #define MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: <tt> 0x0080</tt> */ 133 /**@} end of group gcr_registers */ 134 135 /** 136 * @ingroup gcr_registers 137 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 138 * @brief System Control. 139 * @{ 140 */ 141 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ 142 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 143 144 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ 145 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ 146 147 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 148 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 149 150 #define MXC_F_GCR_SYSCTRL_SYSCACHE_DIS_POS 9 /**< SYSCTRL_SYSCACHE_DIS Position */ 151 #define MXC_F_GCR_SYSCTRL_SYSCACHE_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SYSCACHE_DIS_POS)) /**< SYSCTRL_SYSCACHE_DIS Mask */ 152 153 #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ 154 #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ 155 156 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 157 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 158 159 #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ 160 #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ 161 162 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 163 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 164 165 #define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ 166 #define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ 167 #define MXC_V_GCR_SYSCTRL_OVR_V0_9 ((uint32_t)0x0UL) /**< SYSCTRL_OVR_V0_9 Value */ 168 #define MXC_S_GCR_SYSCTRL_OVR_V0_9 (MXC_V_GCR_SYSCTRL_OVR_V0_9 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V0_9 Setting */ 169 #define MXC_V_GCR_SYSCTRL_OVR_V1_0 ((uint32_t)0x1UL) /**< SYSCTRL_OVR_V1_0 Value */ 170 #define MXC_S_GCR_SYSCTRL_OVR_V1_0 (MXC_V_GCR_SYSCTRL_OVR_V1_0 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V1_0 Setting */ 171 #define MXC_V_GCR_SYSCTRL_OVR_V1_1 ((uint32_t)0x2UL) /**< SYSCTRL_OVR_V1_1 Value */ 172 #define MXC_S_GCR_SYSCTRL_OVR_V1_1 (MXC_V_GCR_SYSCTRL_OVR_V1_1 << MXC_F_GCR_SYSCTRL_OVR_POS) /**< SYSCTRL_OVR_V1_1 Setting */ 173 174 /**@} end of group GCR_SYSCTRL_Register */ 175 176 /** 177 * @ingroup gcr_registers 178 * @defgroup GCR_RST0 GCR_RST0 179 * @brief Reset. 180 * @{ 181 */ 182 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 183 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 184 185 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 186 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 187 188 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 189 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 190 191 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 192 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 193 194 #define MXC_F_GCR_RST0_GPIO2_POS 4 /**< RST0_GPIO2 Position */ 195 #define MXC_F_GCR_RST0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO2_POS)) /**< RST0_GPIO2 Mask */ 196 197 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 198 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 199 200 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 201 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 202 203 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 204 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 205 206 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 207 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 208 209 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 210 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 211 212 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 213 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 214 215 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 216 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 217 218 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 219 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 220 221 #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ 222 #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ 223 224 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 225 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 226 227 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 228 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 229 230 #define MXC_F_GCR_RST0_CRYPTO_POS 18 /**< RST0_CRYPTO Position */ 231 #define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) /**< RST0_CRYPTO Mask */ 232 233 #define MXC_F_GCR_RST0_CAN0_POS 19 /**< RST0_CAN0 Position */ 234 #define MXC_F_GCR_RST0_CAN0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CAN0_POS)) /**< RST0_CAN0 Mask */ 235 236 #define MXC_F_GCR_RST0_CAN1_POS 20 /**< RST0_CAN1 Position */ 237 #define MXC_F_GCR_RST0_CAN1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CAN1_POS)) /**< RST0_CAN1 Mask */ 238 239 #define MXC_F_GCR_RST0_HPB_POS 21 /**< RST0_HPB Position */ 240 #define MXC_F_GCR_RST0_HPB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_HPB_POS)) /**< RST0_HPB Mask */ 241 242 #define MXC_F_GCR_RST0_SMPHR_POS 22 /**< RST0_SMPHR Position */ 243 #define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS)) /**< RST0_SMPHR Mask */ 244 245 #define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ 246 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ 247 248 #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ 249 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ 250 251 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 252 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 253 254 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 255 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 256 257 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 258 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 259 260 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 261 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 262 263 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 264 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 265 266 /**@} end of group GCR_RST0_Register */ 267 268 /** 269 * @ingroup gcr_registers 270 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 271 * @brief Clock Control. 272 * @{ 273 */ 274 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 275 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 276 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 277 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 278 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 279 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 280 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 281 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 282 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 283 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 284 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 285 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 286 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 287 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 288 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 289 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 290 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 291 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 292 293 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 294 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 295 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ 296 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ 297 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ITO ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_SEL_ITO Value */ 298 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ITO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ITO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ITO Setting */ 299 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ 300 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ 301 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 302 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 303 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 304 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 305 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 306 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 307 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 308 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 309 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ 310 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ 311 312 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 313 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 314 315 #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ 316 #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ 317 318 #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 319 #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 320 321 #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ 322 #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ 323 324 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 325 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 326 327 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 328 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 329 330 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 331 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 332 333 #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ 334 #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ 335 336 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 337 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 338 339 #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ 340 #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ 341 342 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 343 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 344 345 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 346 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 347 348 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 349 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 350 351 /**@} end of group GCR_CLKCTRL_Register */ 352 353 /** 354 * @ingroup gcr_registers 355 * @defgroup GCR_PM GCR_PM 356 * @brief Power Management. 357 * @{ 358 */ 359 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 360 #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 361 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 362 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 363 #define MXC_V_GCR_PM_MODE_SLEEP ((uint32_t)0x1UL) /**< PM_MODE_SLEEP Value */ 364 #define MXC_S_GCR_PM_MODE_SLEEP (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SLEEP Setting */ 365 #define MXC_V_GCR_PM_MODE_STANDBY ((uint32_t)0x2UL) /**< PM_MODE_STANDBY Value */ 366 #define MXC_S_GCR_PM_MODE_STANDBY (MXC_V_GCR_PM_MODE_STANDBY << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_STANDBY Setting */ 367 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 368 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 369 #define MXC_V_GCR_PM_MODE_LPM ((uint32_t)0x8UL) /**< PM_MODE_LPM Value */ 370 #define MXC_S_GCR_PM_MODE_LPM (MXC_V_GCR_PM_MODE_LPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_LPM Setting */ 371 #define MXC_V_GCR_PM_MODE_UPM ((uint32_t)0x9UL) /**< PM_MODE_UPM Value */ 372 #define MXC_S_GCR_PM_MODE_UPM (MXC_V_GCR_PM_MODE_UPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_UPM Setting */ 373 #define MXC_V_GCR_PM_MODE_POWERDOWN ((uint32_t)0xAUL) /**< PM_MODE_POWERDOWN Value */ 374 #define MXC_S_GCR_PM_MODE_POWERDOWN (MXC_V_GCR_PM_MODE_POWERDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_POWERDOWN Setting */ 375 376 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 377 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 378 379 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 380 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 381 382 #define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ 383 #define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ 384 385 #define MXC_F_GCR_PM_WUT_WE_POS 7 /**< PM_WUT_WE Position */ 386 #define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) /**< PM_WUT_WE Mask */ 387 388 #define MXC_F_GCR_PM_AINCOMP_WE_POS 9 /**< PM_AINCOMP_WE Position */ 389 #define MXC_F_GCR_PM_AINCOMP_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS)) /**< PM_AINCOMP_WE Mask */ 390 391 #define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ 392 #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ 393 394 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 395 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 396 397 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 398 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 399 400 #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ 401 #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ 402 403 /**@} end of group GCR_PM_Register */ 404 405 /** 406 * @ingroup gcr_registers 407 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 408 * @brief Peripheral Clock Divider. 409 * @{ 410 */ 411 #define MXC_F_GCR_PCLKDIV_SDIOCLKDIV_POS 7 /**< PCLKDIV_SDIOCLKDIV Position */ 412 #define MXC_F_GCR_PCLKDIV_SDIOCLKDIV ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_SDIOCLKDIV_POS)) /**< PCLKDIV_SDIOCLKDIV Mask */ 413 414 #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ 415 #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ 416 417 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS 14 /**< PCLKDIV_CNNCLKDIV Position */ 418 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)) /**< PCLKDIV_CNNCLKDIV Mask */ 419 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 ((uint32_t)0x0UL) /**< PCLKDIV_CNNCLKDIV_DIV2 Value */ 420 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV2 Setting */ 421 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 ((uint32_t)0x1UL) /**< PCLKDIV_CNNCLKDIV_DIV4 Value */ 422 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV4 Setting */ 423 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 ((uint32_t)0x2UL) /**< PCLKDIV_CNNCLKDIV_DIV8 Value */ 424 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV8 Setting */ 425 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 ((uint32_t)0x3UL) /**< PCLKDIV_CNNCLKDIV_DIV16 Value */ 426 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV16 Setting */ 427 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 ((uint32_t)0x4UL) /**< PCLKDIV_CNNCLKDIV_DIV1 Value */ 428 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV1 Setting */ 429 430 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS 17 /**< PCLKDIV_CNNCLKSEL Position */ 431 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS)) /**< PCLKDIV_CNNCLKSEL Mask */ 432 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_PCLK ((uint32_t)0x0UL) /**< PCLKDIV_CNNCLKSEL_PCLK Value */ 433 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_PCLK (MXC_V_GCR_PCLKDIV_CNNCLKSEL_PCLK << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_PCLK Setting */ 434 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_ISO ((uint32_t)0x1UL) /**< PCLKDIV_CNNCLKSEL_ISO Value */ 435 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_ISO (MXC_V_GCR_PCLKDIV_CNNCLKSEL_ISO << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_ISO Setting */ 436 #define MXC_V_GCR_PCLKDIV_CNNCLKSEL_ITO ((uint32_t)0x3UL) /**< PCLKDIV_CNNCLKSEL_ITO Value */ 437 #define MXC_S_GCR_PCLKDIV_CNNCLKSEL_ITO (MXC_V_GCR_PCLKDIV_CNNCLKSEL_ITO << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS) /**< PCLKDIV_CNNCLKSEL_ITO Setting */ 438 439 /**@} end of group GCR_PCLKDIV_Register */ 440 441 /** 442 * @ingroup gcr_registers 443 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 444 * @brief Peripheral Clock Disable. 445 * @{ 446 */ 447 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 448 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 449 450 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 451 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 452 453 #define MXC_F_GCR_PCLKDIS0_GPIO2_POS 2 /**< PCLKDIS0_GPIO2 Position */ 454 #define MXC_F_GCR_PCLKDIS0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO2_POS)) /**< PCLKDIS0_GPIO2 Mask */ 455 456 #define MXC_F_GCR_PCLKDIS0_USB_POS 3 /**< PCLKDIS0_USB Position */ 457 #define MXC_F_GCR_PCLKDIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_USB_POS)) /**< PCLKDIS0_USB Mask */ 458 459 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 460 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 461 462 #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ 463 #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ 464 465 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ 466 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 467 468 #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ 469 #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ 470 471 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 472 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 473 474 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 475 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 476 477 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 478 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 479 480 #define MXC_F_GCR_PCLKDIS0_CRYPTO_POS 14 /**< PCLKDIS0_CRYPTO Position */ 481 #define MXC_F_GCR_PCLKDIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CRYPTO_POS)) /**< PCLKDIS0_CRYPTO Mask */ 482 483 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 484 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 485 486 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 487 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 488 489 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 490 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 491 492 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 493 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 494 495 #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ 496 #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ 497 498 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 499 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 500 501 #define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ 502 #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ 503 504 #define MXC_F_GCR_PCLKDIS0_SPIXIP_POS 30 /**< PCLKDIS0_SPIXIP Position */ 505 #define MXC_F_GCR_PCLKDIS0_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIP_POS)) /**< PCLKDIS0_SPIXIP Mask */ 506 507 #define MXC_F_GCR_PCLKDIS0_SPIXIPC_POS 31 /**< PCLKDIS0_SPIXIPC Position */ 508 #define MXC_F_GCR_PCLKDIS0_SPIXIPC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIPC_POS)) /**< PCLKDIS0_SPIXIPC Mask */ 509 510 /**@} end of group GCR_PCLKDIS0_Register */ 511 512 /** 513 * @ingroup gcr_registers 514 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 515 * @brief Memory Clock Control Register. 516 * @{ 517 */ 518 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 519 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 520 521 #define MXC_F_GCR_MEMCTRL_HYPCLKDS_POS 8 /**< MEMCTRL_HYPCLKDS Position */ 522 #define MXC_F_GCR_MEMCTRL_HYPCLKDS ((uint32_t)(0x3UL << MXC_F_GCR_MEMCTRL_HYPCLKDS_POS)) /**< MEMCTRL_HYPCLKDS Mask */ 523 524 /**@} end of group GCR_MEMCTRL_Register */ 525 526 /** 527 * @ingroup gcr_registers 528 * @defgroup GCR_MEMZ GCR_MEMZ 529 * @brief Memory Zeroize Control. 530 * @{ 531 */ 532 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 533 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 534 535 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 536 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 537 538 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 539 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 540 541 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 542 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 543 544 #define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ 545 #define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ 546 547 #define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ 548 #define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ 549 550 #define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ 551 #define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ 552 553 #define MXC_F_GCR_MEMZ_RAM7_POS 7 /**< MEMZ_RAM7 Position */ 554 #define MXC_F_GCR_MEMZ_RAM7 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM7_POS)) /**< MEMZ_RAM7 Mask */ 555 556 #define MXC_F_GCR_MEMZ_RAM8_POS 8 /**< MEMZ_RAM8 Position */ 557 #define MXC_F_GCR_MEMZ_RAM8 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM8_POS)) /**< MEMZ_RAM8 Mask */ 558 559 #define MXC_F_GCR_MEMZ_ICC0_POS 9 /**< MEMZ_ICC0 Position */ 560 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 561 562 #define MXC_F_GCR_MEMZ_ICC1_POS 10 /**< MEMZ_ICC1 Position */ 563 #define MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) /**< MEMZ_ICC1 Mask */ 564 565 #define MXC_F_GCR_MEMZ_ICCXIP_POS 11 /**< MEMZ_ICCXIP Position */ 566 #define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ 567 568 #define MXC_F_GCR_MEMZ_USBFIFO_POS 12 /**< MEMZ_USBFIFO Position */ 569 #define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ 570 571 #define MXC_F_GCR_MEMZ_MAARAM_POS 13 /**< MEMZ_MAARAM Position */ 572 #define MXC_F_GCR_MEMZ_MAARAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_MAARAM_POS)) /**< MEMZ_MAARAM Mask */ 573 574 #define MXC_F_GCR_MEMZ_DCACHE_DATA_POS 14 /**< MEMZ_DCACHE_DATA Position */ 575 #define MXC_F_GCR_MEMZ_DCACHE_DATA ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_DCACHE_DATA_POS)) /**< MEMZ_DCACHE_DATA Mask */ 576 577 #define MXC_F_GCR_MEMZ_DCACHE_TAG_POS 15 /**< MEMZ_DCACHE_TAG Position */ 578 #define MXC_F_GCR_MEMZ_DCACHE_TAG ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_DCACHE_TAG_POS)) /**< MEMZ_DCACHE_TAG Mask */ 579 580 /**@} end of group GCR_MEMZ_Register */ 581 582 /** 583 * @ingroup gcr_registers 584 * @defgroup GCR_SYSST GCR_SYSST 585 * @brief System Status Register. 586 * @{ 587 */ 588 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 589 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 590 591 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ 592 #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ 593 594 #define MXC_F_GCR_SYSST_DATAINTERR_POS 2 /**< SYSST_DATAINTERR Position */ 595 #define MXC_F_GCR_SYSST_DATAINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_DATAINTERR_POS)) /**< SYSST_DATAINTERR Mask */ 596 597 /**@} end of group GCR_SYSST_Register */ 598 599 /** 600 * @ingroup gcr_registers 601 * @defgroup GCR_RST1 GCR_RST1 602 * @brief Reset 1. 603 * @{ 604 */ 605 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 606 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 607 608 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 609 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 610 611 #define MXC_F_GCR_RST1_SPIXIP_POS 3 /**< RST1_SPIXIP Position */ 612 #define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) /**< RST1_SPIXIP Mask */ 613 614 #define MXC_F_GCR_RST1_SPIXIPM_POS 4 /**< RST1_SPIXIPM Position */ 615 #define MXC_F_GCR_RST1_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIPM_POS)) /**< RST1_SPIXIPM Mask */ 616 617 #define MXC_F_GCR_RST1_OWM_POS 7 /**< RST1_OWM Position */ 618 #define MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS)) /**< RST1_OWM Mask */ 619 620 #define MXC_F_GCR_RST1_SPI3_POS 11 /**< RST1_SPI3 Position */ 621 #define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) /**< RST1_SPI3 Mask */ 622 623 #define MXC_F_GCR_RST1_SPI4_POS 13 /**< RST1_SPI4 Position */ 624 #define MXC_F_GCR_RST1_SPI4 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI4_POS)) /**< RST1_SPI4 Mask */ 625 626 #define MXC_F_GCR_RST1_SMPHR_POS 16 /**< RST1_SMPHR Position */ 627 #define MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS)) /**< RST1_SMPHR Mask */ 628 629 #define MXC_F_GCR_RST1_BTLE_POS 18 /**< RST1_BTLE Position */ 630 #define MXC_F_GCR_RST1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS)) /**< RST1_BTLE Mask */ 631 632 #define MXC_F_GCR_RST1_I2S_POS 19 /**< RST1_I2S Position */ 633 #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ 634 635 #define MXC_F_GCR_RST1_I2C2_POS 20 /**< RST1_I2C2 Position */ 636 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ 637 638 #define MXC_F_GCR_RST1_PUF_POS 28 /**< RST1_PUF Position */ 639 #define MXC_F_GCR_RST1_PUF ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PUF_POS)) /**< RST1_PUF Mask */ 640 641 #define MXC_F_GCR_RST1_CPU1_POS 31 /**< RST1_CPU1 Position */ 642 #define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) /**< RST1_CPU1 Mask */ 643 644 /**@} end of group GCR_RST1_Register */ 645 646 /** 647 * @ingroup gcr_registers 648 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 649 * @brief Peripheral Clock Disable. 650 * @{ 651 */ 652 #define MXC_F_GCR_PCLKDIS1_BTLE_POS 0 /**< PCLKDIS1_BTLE Position */ 653 #define MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS)) /**< PCLKDIS1_BTLE Mask */ 654 655 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 656 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 657 658 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 659 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 660 661 #define MXC_F_GCR_PCLKDIS1_PUF_POS 3 /**< PCLKDIS1_PUF Position */ 662 #define MXC_F_GCR_PCLKDIS1_PUF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PUF_POS)) /**< PCLKDIS1_PUF Mask */ 663 664 #define MXC_F_GCR_PCLKDIS1_HPB_POS 4 /**< PCLKDIS1_HPB Position */ 665 #define MXC_F_GCR_PCLKDIS1_HPB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_HPB_POS)) /**< PCLKDIS1_HPB Mask */ 666 667 #define MXC_F_GCR_PCLKDIS1_SYSCACHE_POS 7 /**< PCLKDIS1_SYSCACHE Position */ 668 #define MXC_F_GCR_PCLKDIS1_SYSCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SYSCACHE_POS)) /**< PCLKDIS1_SYSCACHE Mask */ 669 670 #define MXC_F_GCR_PCLKDIS1_SMPHR_POS 9 /**< PCLKDIS1_SMPHR Position */ 671 #define MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) /**< PCLKDIS1_SMPHR Mask */ 672 673 #define MXC_F_GCR_PCLKDIS1_CAN0_POS 11 /**< PCLKDIS1_CAN0 Position */ 674 #define MXC_F_GCR_PCLKDIS1_CAN0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CAN0_POS)) /**< PCLKDIS1_CAN0 Mask */ 675 676 #define MXC_F_GCR_PCLKDIS1_OWM_POS 13 /**< PCLKDIS1_OWM Position */ 677 #define MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) /**< PCLKDIS1_OWM Mask */ 678 679 #define MXC_F_GCR_PCLKDIS1_SPI3_POS 16 /**< PCLKDIS1_SPI3 Position */ 680 #define MXC_F_GCR_PCLKDIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI3_POS)) /**< PCLKDIS1_SPI3 Mask */ 681 682 #define MXC_F_GCR_PCLKDIS1_SPI4_POS 17 /**< PCLKDIS1_SPI4 Position */ 683 #define MXC_F_GCR_PCLKDIS1_SPI4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI4_POS)) /**< PCLKDIS1_SPI4 Mask */ 684 685 #define MXC_F_GCR_PCLKDIS1_CAN1_POS 19 /**< PCLKDIS1_CAN1 Position */ 686 #define MXC_F_GCR_PCLKDIS1_CAN1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CAN1_POS)) /**< PCLKDIS1_CAN1 Mask */ 687 688 #define MXC_F_GCR_PCLKDIS1_SPIXR_POS 20 /**< PCLKDIS1_SPIXR Position */ 689 #define MXC_F_GCR_PCLKDIS1_SPIXR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPIXR_POS)) /**< PCLKDIS1_SPIXR Mask */ 690 691 #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ 692 #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ 693 694 #define MXC_F_GCR_PCLKDIS1_I2C2_POS 24 /**< PCLKDIS1_I2C2 Position */ 695 #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ 696 697 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 27 /**< PCLKDIS1_WDT0 Position */ 698 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 699 700 #define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 /**< PCLKDIS1_CPU1 Position */ 701 #define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) /**< PCLKDIS1_CPU1 Mask */ 702 703 /**@} end of group GCR_PCLKDIS1_Register */ 704 705 /** 706 * @ingroup gcr_registers 707 * @defgroup GCR_EVENTEN GCR_EVENTEN 708 * @brief Event Enable Register. 709 * @{ 710 */ 711 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 712 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 713 714 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 715 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 716 717 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 718 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 719 720 /**@} end of group GCR_EVENTEN_Register */ 721 722 /** 723 * @ingroup gcr_registers 724 * @defgroup GCR_REVISION GCR_REVISION 725 * @brief Revision Register. 726 * @{ 727 */ 728 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 729 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 730 731 /**@} end of group GCR_REVISION_Register */ 732 733 /** 734 * @ingroup gcr_registers 735 * @defgroup GCR_SYSIE GCR_SYSIE 736 * @brief System Status Interrupt Enable Register. 737 * @{ 738 */ 739 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 740 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 741 742 /**@} end of group GCR_SYSIE_Register */ 743 744 /** 745 * @ingroup gcr_registers 746 * @defgroup GCR_ECCERR GCR_ECCERR 747 * @brief ECC Error Register 748 * @{ 749 */ 750 #define MXC_F_GCR_ECCERR_RAM0_POS 0 /**< ECCERR_RAM0 Position */ 751 #define MXC_F_GCR_ECCERR_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_POS)) /**< ECCERR_RAM0 Mask */ 752 753 #define MXC_F_GCR_ECCERR_RAM1_POS 1 /**< ECCERR_RAM1 Position */ 754 #define MXC_F_GCR_ECCERR_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM1_POS)) /**< ECCERR_RAM1 Mask */ 755 756 #define MXC_F_GCR_ECCERR_RAM2_POS 2 /**< ECCERR_RAM2 Position */ 757 #define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ 758 759 #define MXC_F_GCR_ECCERR_RAM3_POS 3 /**< ECCERR_RAM3 Position */ 760 #define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ 761 762 #define MXC_F_GCR_ECCERR_RAM4_POS 4 /**< ECCERR_RAM4 Position */ 763 #define MXC_F_GCR_ECCERR_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM4_POS)) /**< ECCERR_RAM4 Mask */ 764 765 #define MXC_F_GCR_ECCERR_RAM5_POS 5 /**< ECCERR_RAM5 Position */ 766 #define MXC_F_GCR_ECCERR_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM5_POS)) /**< ECCERR_RAM5 Mask */ 767 768 #define MXC_F_GCR_ECCERR_RAM6_POS 6 /**< ECCERR_RAM6 Position */ 769 #define MXC_F_GCR_ECCERR_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM6_POS)) /**< ECCERR_RAM6 Mask */ 770 771 #define MXC_F_GCR_ECCERR_ICACHE0_POS 8 /**< ECCERR_ICACHE0 Position */ 772 #define MXC_F_GCR_ECCERR_ICACHE0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICACHE0_POS)) /**< ECCERR_ICACHE0 Mask */ 773 774 #define MXC_F_GCR_ECCERR_ICACHEXIP_POS 10 /**< ECCERR_ICACHEXIP Position */ 775 #define MXC_F_GCR_ECCERR_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICACHEXIP_POS)) /**< ECCERR_ICACHEXIP Mask */ 776 777 /**@} end of group GCR_ECCERR_Register */ 778 779 /** 780 * @ingroup gcr_registers 781 * @defgroup GCR_ECCCED GCR_ECCCED 782 * @brief ECC Not Double Error Detect Register 783 * @{ 784 */ 785 #define MXC_F_GCR_ECCCED_RAM0_POS 0 /**< ECCCED_RAM0 Position */ 786 #define MXC_F_GCR_ECCCED_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_POS)) /**< ECCCED_RAM0 Mask */ 787 788 #define MXC_F_GCR_ECCCED_RAM1_POS 1 /**< ECCCED_RAM1 Position */ 789 #define MXC_F_GCR_ECCCED_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM1_POS)) /**< ECCCED_RAM1 Mask */ 790 791 #define MXC_F_GCR_ECCCED_RAM2_POS 2 /**< ECCCED_RAM2 Position */ 792 #define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ 793 794 #define MXC_F_GCR_ECCCED_RAM3_POS 3 /**< ECCCED_RAM3 Position */ 795 #define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ 796 797 #define MXC_F_GCR_ECCCED_RAM4_POS 4 /**< ECCCED_RAM4 Position */ 798 #define MXC_F_GCR_ECCCED_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM4_POS)) /**< ECCCED_RAM4 Mask */ 799 800 #define MXC_F_GCR_ECCCED_RAM5_POS 5 /**< ECCCED_RAM5 Position */ 801 #define MXC_F_GCR_ECCCED_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM5_POS)) /**< ECCCED_RAM5 Mask */ 802 803 #define MXC_F_GCR_ECCCED_RAM6_POS 6 /**< ECCCED_RAM6 Position */ 804 #define MXC_F_GCR_ECCCED_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM6_POS)) /**< ECCCED_RAM6 Mask */ 805 806 #define MXC_F_GCR_ECCCED_ICACHE0_POS 8 /**< ECCCED_ICACHE0 Position */ 807 #define MXC_F_GCR_ECCCED_ICACHE0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICACHE0_POS)) /**< ECCCED_ICACHE0 Mask */ 808 809 #define MXC_F_GCR_ECCCED_ICACHEXIP_POS 10 /**< ECCCED_ICACHEXIP Position */ 810 #define MXC_F_GCR_ECCCED_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICACHEXIP_POS)) /**< ECCCED_ICACHEXIP Mask */ 811 812 /**@} end of group GCR_ECCCED_Register */ 813 814 /** 815 * @ingroup gcr_registers 816 * @defgroup GCR_ECCIE GCR_ECCIE 817 * @brief ECC IRQ Enable Register 818 * @{ 819 */ 820 #define MXC_F_GCR_ECCIE_RAM0_POS 0 /**< ECCIE_RAM0 Position */ 821 #define MXC_F_GCR_ECCIE_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM0_POS)) /**< ECCIE_RAM0 Mask */ 822 823 #define MXC_F_GCR_ECCIE_RAM1_POS 1 /**< ECCIE_RAM1 Position */ 824 #define MXC_F_GCR_ECCIE_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM1_POS)) /**< ECCIE_RAM1 Mask */ 825 826 #define MXC_F_GCR_ECCIE_RAM2_POS 2 /**< ECCIE_RAM2 Position */ 827 #define MXC_F_GCR_ECCIE_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM2_POS)) /**< ECCIE_RAM2 Mask */ 828 829 #define MXC_F_GCR_ECCIE_RAM3_POS 3 /**< ECCIE_RAM3 Position */ 830 #define MXC_F_GCR_ECCIE_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM3_POS)) /**< ECCIE_RAM3 Mask */ 831 832 #define MXC_F_GCR_ECCIE_RAM4_POS 4 /**< ECCIE_RAM4 Position */ 833 #define MXC_F_GCR_ECCIE_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM4_POS)) /**< ECCIE_RAM4 Mask */ 834 835 #define MXC_F_GCR_ECCIE_RAM5_POS 5 /**< ECCIE_RAM5 Position */ 836 #define MXC_F_GCR_ECCIE_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM5_POS)) /**< ECCIE_RAM5 Mask */ 837 838 #define MXC_F_GCR_ECCIE_RAM6_POS 6 /**< ECCIE_RAM6 Position */ 839 #define MXC_F_GCR_ECCIE_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM6_POS)) /**< ECCIE_RAM6 Mask */ 840 841 #define MXC_F_GCR_ECCIE_ICACHE0_POS 8 /**< ECCIE_ICACHE0 Position */ 842 #define MXC_F_GCR_ECCIE_ICACHE0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICACHE0_POS)) /**< ECCIE_ICACHE0 Mask */ 843 844 #define MXC_F_GCR_ECCIE_ICACHEXIP_POS 10 /**< ECCIE_ICACHEXIP Position */ 845 #define MXC_F_GCR_ECCIE_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICACHEXIP_POS)) /**< ECCIE_ICACHEXIP Mask */ 846 847 /**@} end of group GCR_ECCIE_Register */ 848 849 /** 850 * @ingroup gcr_registers 851 * @defgroup GCR_ECCADDR GCR_ECCADDR 852 * @brief ECC Error Address Register 853 * @{ 854 */ 855 #define MXC_F_GCR_ECCADDR_DADDR_POS 0 /**< ECCADDR_DADDR Position */ 856 #define MXC_F_GCR_ECCADDR_DADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DADDR_POS)) /**< ECCADDR_DADDR Mask */ 857 858 #define MXC_F_GCR_ECCADDR_DB_POS 14 /**< ECCADDR_DB Position */ 859 #define MXC_F_GCR_ECCADDR_DB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DB_POS)) /**< ECCADDR_DB Mask */ 860 861 #define MXC_F_GCR_ECCADDR_DE_POS 15 /**< ECCADDR_DE Position */ 862 #define MXC_F_GCR_ECCADDR_DE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DE_POS)) /**< ECCADDR_DE Mask */ 863 864 #define MXC_F_GCR_ECCADDR_TADDR_POS 16 /**< ECCADDR_TADDR Position */ 865 #define MXC_F_GCR_ECCADDR_TADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TADDR_POS)) /**< ECCADDR_TADDR Mask */ 866 867 #define MXC_F_GCR_ECCADDR_TB_POS 30 /**< ECCADDR_TB Position */ 868 #define MXC_F_GCR_ECCADDR_TB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TB_POS)) /**< ECCADDR_TB Mask */ 869 870 #define MXC_F_GCR_ECCADDR_TE_POS 31 /**< ECCADDR_TE Position */ 871 #define MXC_F_GCR_ECCADDR_TE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TE_POS)) /**< ECCADDR_TE Mask */ 872 873 /**@} end of group GCR_ECCADDR_Register */ 874 875 /** 876 * @ingroup gcr_registers 877 * @defgroup GCR_BTLELDOCTRL GCR_BTLELDOCTRL 878 * @brief BTLE LDO Control Register 879 * @{ 880 */ 881 #define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ 882 #define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ 883 884 #define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ 885 #define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ 886 887 #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ 888 #define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ 889 890 #define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ 891 #define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ 892 893 #define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ 894 #define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ 895 896 #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ 897 #define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ 898 899 #define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ 900 #define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ 901 902 #define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ 903 #define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ 904 905 #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ 906 #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ 907 908 #define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ 909 #define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ 910 911 #define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ 912 #define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ 913 914 #define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ 915 #define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ 916 917 #define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ 918 #define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ 919 920 #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ 921 #define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ 922 923 /**@} end of group GCR_BTLELDOCTRL_Register */ 924 925 /** 926 * @ingroup gcr_registers 927 * @defgroup GCR_BTLELDODLY GCR_BTLELDODLY 928 * @brief BTLE LDO Delay Register 929 * @{ 930 */ 931 #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ 932 #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ 933 934 #define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 8 /**< BTLELDODLY_LDOTXDLYCNT Position */ 935 #define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ 936 937 #define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 20 /**< BTLELDODLY_LDORXDLYCNT Position */ 938 #define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ 939 940 /**@} end of group GCR_BTLELDODLY_Register */ 941 942 #ifdef __cplusplus 943 } 944 #endif 945 946 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_GCR_REGS_H_ 947
