1 /** 2 * @file flc_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup flc_reva 65 * @defgroup flc_reva_registers FLC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. 67 * @details Flash Memory Control. 68 */ 69 70 /** 71 * @ingroup flc_reva_registers 72 * Structure type to access the FLC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC_REVA ADDR Register */ 76 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC_REVA CLKDIV Register */ 77 __IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC_REVA CTRL Register */ 78 __R uint32_t rsv_0xc_0x23[6]; 79 __IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC_REVA INTR Register */ 80 __IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC_REVA ECCDATA Register */ 81 __R uint32_t rsv_0x2c; 82 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC_REVA DATA Register */ 83 __O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC_REVA ACTRL Register */ 84 } mxc_flc_reva_regs_t; 85 86 /* Register offsets for module FLC_REVA */ 87 /** 88 * @ingroup flc_reva_registers 89 * @defgroup FLC_REVA_Register_Offsets Register Offsets 90 * @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */ 97 #define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */ 98 #define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */ 99 #define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */ 100 /**@} end of group flc_reva_registers */ 101 102 /** 103 * @ingroup flc_reva_registers 104 * @defgroup FLC_REVA_ADDR FLC_REVA_ADDR 105 * @brief Flash Write Address. 106 * @{ 107 */ 108 #define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 109 #define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 110 111 /**@} end of group FLC_REVA_ADDR_Register */ 112 113 /** 114 * @ingroup flc_reva_registers 115 * @defgroup FLC_REVA_CLKDIV FLC_REVA_CLKDIV 116 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 117 * MHz clock for Flash controller. 118 * @{ 119 */ 120 #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 121 #define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 122 123 /**@} end of group FLC_REVA_CLKDIV_Register */ 124 125 /** 126 * @ingroup flc_reva_registers 127 * @defgroup FLC_REVA_CTRL FLC_REVA_CTRL 128 * @brief Flash Control Register. 129 * @{ 130 */ 131 #define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ 132 #define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ 133 134 #define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ 135 #define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ 136 137 #define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ 138 #define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ 139 140 #define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ 141 #define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ 142 143 #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ 144 #define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ 145 #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ 146 #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ 147 #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ 148 #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ 149 #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ 150 #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ 151 152 #define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ 153 #define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ 154 155 #define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ 156 #define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ 157 158 #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ 159 #define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ 160 #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ 161 #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ 162 #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ 163 #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ 164 165 /**@} end of group FLC_REVA_CTRL_Register */ 166 167 /** 168 * @ingroup flc_reva_registers 169 * @defgroup FLC_REVA_INTR FLC_REVA_INTR 170 * @brief Flash Interrupt Register. 171 * @{ 172 */ 173 #define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ 174 #define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ 175 176 #define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ 177 #define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ 178 179 #define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ 180 #define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ 181 182 #define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ 183 #define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ 184 185 /**@} end of group FLC_REVA_INTR_Register */ 186 187 /** 188 * @ingroup flc_reva_registers 189 * @defgroup FLC_REVA_ECCDATA FLC_REVA_ECCDATA 190 * @brief ECC Data Register. 191 * @{ 192 */ 193 #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ 194 #define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ 195 196 #define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ 197 #define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ 198 199 /**@} end of group FLC_REVA_ECCDATA_Register */ 200 201 /** 202 * @ingroup flc_reva_registers 203 * @defgroup FLC_REVA_DATA FLC_REVA_DATA 204 * @brief Flash Write Data. 205 * @{ 206 */ 207 #define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ 208 #define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ 209 210 /**@} end of group FLC_REVA_DATA_Register */ 211 212 /** 213 * @ingroup flc_reva_registers 214 * @defgroup FLC_REVA_ACTRL FLC_REVA_ACTRL 215 * @brief Access Control Register. Writing the ACTRL register with the following values in 216 * the order shown, allows read and write access to the system and user Information 217 * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 218 * 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of 219 * any word will disable access to system and user information block. Readback of 220 * this register is always zero. 221 * @{ 222 */ 223 #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ 224 #define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ 225 226 /**@} end of group FLC_REVA_ACTRL_Register */ 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_ 233
