1 /** 2 * @file emac_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the EMAC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_EMAC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_EMAC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup emac 66 * @defgroup emac_registers EMAC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the EMAC Peripheral Module. 68 * @details 10/100 Ethernet MAC. 69 */ 70 71 /** 72 * @ingroup emac_registers 73 * Structure type to access the EMAC Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cn; /**< <tt>\b 0x00:</tt> EMAC CN Register */ 77 __IO uint32_t cfg; /**< <tt>\b 0x04:</tt> EMAC CFG Register */ 78 __I uint32_t status; /**< <tt>\b 0x08:</tt> EMAC STATUS Register */ 79 __R uint32_t rsv_0xc_0x13[2]; 80 __IO uint32_t tx_st; /**< <tt>\b 0x14:</tt> EMAC TX_ST Register */ 81 __IO uint32_t rxbuf_ptr; /**< <tt>\b 0x18:</tt> EMAC RXBUF_PTR Register */ 82 __IO uint32_t txbuf_ptr; /**< <tt>\b 0x1C:</tt> EMAC TXBUF_PTR Register */ 83 __IO uint32_t rx_st; /**< <tt>\b 0x20:</tt> EMAC RX_ST Register */ 84 __IO uint32_t int_st; /**< <tt>\b 0x24:</tt> EMAC INT_ST Register */ 85 __O uint32_t int_en; /**< <tt>\b 0x28:</tt> EMAC INT_EN Register */ 86 __O uint32_t int_dis; /**< <tt>\b 0x2C:</tt> EMAC INT_DIS Register */ 87 __I uint32_t int_mask; /**< <tt>\b 0x30:</tt> EMAC INT_MASK Register */ 88 __IO uint32_t phy_mt; /**< <tt>\b 0x34:</tt> EMAC PHY_MT Register */ 89 __I uint32_t pt; /**< <tt>\b 0x38:</tt> EMAC PT Register */ 90 __IO uint32_t pfr; /**< <tt>\b 0x3C:</tt> EMAC PFR Register */ 91 __IO uint32_t ftok; /**< <tt>\b 0x40:</tt> EMAC FTOK Register */ 92 __IO uint32_t scf; /**< <tt>\b 0x44:</tt> EMAC SCF Register */ 93 __IO uint32_t mcf; /**< <tt>\b 0x48:</tt> EMAC MCF Register */ 94 __IO uint32_t frok; /**< <tt>\b 0x4C:</tt> EMAC FROK Register */ 95 __IO uint32_t fcs_err; /**< <tt>\b 0x50:</tt> EMAC FCS_ERR Register */ 96 __IO uint32_t algn_err; /**< <tt>\b 0x54:</tt> EMAC ALGN_ERR Register */ 97 __IO uint32_t dftxf; /**< <tt>\b 0x58:</tt> EMAC DFTXF Register */ 98 __IO uint32_t lc; /**< <tt>\b 0x5C:</tt> EMAC LC Register */ 99 __IO uint32_t ec; /**< <tt>\b 0x60:</tt> EMAC EC Register */ 100 __IO uint32_t tur_err; /**< <tt>\b 0x64:</tt> EMAC TUR_ERR Register */ 101 __IO uint32_t cs_err; /**< <tt>\b 0x68:</tt> EMAC CS_ERR Register */ 102 __IO uint32_t rr_err; /**< <tt>\b 0x6C:</tt> EMAC RR_ERR Register */ 103 __IO uint32_t ror_err; /**< <tt>\b 0x70:</tt> EMAC ROR_ERR Register */ 104 __IO uint32_t rs_err; /**< <tt>\b 0x74:</tt> EMAC RS_ERR Register */ 105 __IO uint32_t el_err; /**< <tt>\b 0x78:</tt> EMAC EL_ERR Register */ 106 __IO uint32_t rj; /**< <tt>\b 0x7C:</tt> EMAC RJ Register */ 107 __IO uint32_t usf; /**< <tt>\b 0x80:</tt> EMAC USF Register */ 108 __IO uint32_t sqe_err; /**< <tt>\b 0x84:</tt> EMAC SQE_ERR Register */ 109 __IO uint32_t rlfm; /**< <tt>\b 0x88:</tt> EMAC RLFM Register */ 110 __IO uint32_t tpf; /**< <tt>\b 0x8C:</tt> EMAC TPF Register */ 111 __IO uint32_t hashl; /**< <tt>\b 0x90:</tt> EMAC HASHL Register */ 112 __IO uint32_t hashh; /**< <tt>\b 0x94:</tt> EMAC HASHH Register */ 113 __IO uint32_t sa1l; /**< <tt>\b 0x98:</tt> EMAC SA1L Register */ 114 __IO uint32_t sa1h; /**< <tt>\b 0x9C:</tt> EMAC SA1H Register */ 115 __IO uint32_t sa2l; /**< <tt>\b 0xA0:</tt> EMAC SA2L Register */ 116 __IO uint32_t sa2h; /**< <tt>\b 0xA4:</tt> EMAC SA2H Register */ 117 __IO uint32_t sa3l; /**< <tt>\b 0xA8:</tt> EMAC SA3L Register */ 118 __IO uint32_t sa3h; /**< <tt>\b 0xAC:</tt> EMAC SA3H Register */ 119 __IO uint32_t sa4l; /**< <tt>\b 0xB0:</tt> EMAC SA4L Register */ 120 __IO uint32_t sa4h; /**< <tt>\b 0xB4:</tt> EMAC SA4H Register */ 121 __IO uint32_t tid_ck; /**< <tt>\b 0xB8:</tt> EMAC TID_CK Register */ 122 __IO uint32_t tpq; /**< <tt>\b 0xBC:</tt> EMAC TPQ Register */ 123 __R uint32_t rsv_0xc0_0xfb[15]; 124 __I uint32_t rev; /**< <tt>\b 0xFC:</tt> EMAC REV Register */ 125 } mxc_emac_regs_t; 126 127 /* Register offsets for module EMAC */ 128 /** 129 * @ingroup emac_registers 130 * @defgroup EMAC_Register_Offsets Register Offsets 131 * @brief EMAC Peripheral Register Offsets from the EMAC Base Peripheral Address. 132 * @{ 133 */ 134 #define MXC_R_EMAC_CN ((uint32_t)0x00000000UL) /**< Offset from EMAC Base Address: <tt> 0x0000</tt> */ 135 #define MXC_R_EMAC_CFG ((uint32_t)0x00000004UL) /**< Offset from EMAC Base Address: <tt> 0x0004</tt> */ 136 #define MXC_R_EMAC_STATUS ((uint32_t)0x00000008UL) /**< Offset from EMAC Base Address: <tt> 0x0008</tt> */ 137 #define MXC_R_EMAC_TX_ST ((uint32_t)0x00000014UL) /**< Offset from EMAC Base Address: <tt> 0x0014</tt> */ 138 #define MXC_R_EMAC_RXBUF_PTR ((uint32_t)0x00000018UL) /**< Offset from EMAC Base Address: <tt> 0x0018</tt> */ 139 #define MXC_R_EMAC_TXBUF_PTR ((uint32_t)0x0000001CUL) /**< Offset from EMAC Base Address: <tt> 0x001C</tt> */ 140 #define MXC_R_EMAC_RX_ST ((uint32_t)0x00000020UL) /**< Offset from EMAC Base Address: <tt> 0x0020</tt> */ 141 #define MXC_R_EMAC_INT_ST ((uint32_t)0x00000024UL) /**< Offset from EMAC Base Address: <tt> 0x0024</tt> */ 142 #define MXC_R_EMAC_INT_EN ((uint32_t)0x00000028UL) /**< Offset from EMAC Base Address: <tt> 0x0028</tt> */ 143 #define MXC_R_EMAC_INT_DIS ((uint32_t)0x0000002CUL) /**< Offset from EMAC Base Address: <tt> 0x002C</tt> */ 144 #define MXC_R_EMAC_INT_MASK ((uint32_t)0x00000030UL) /**< Offset from EMAC Base Address: <tt> 0x0030</tt> */ 145 #define MXC_R_EMAC_PHY_MT ((uint32_t)0x00000034UL) /**< Offset from EMAC Base Address: <tt> 0x0034</tt> */ 146 #define MXC_R_EMAC_PT ((uint32_t)0x00000038UL) /**< Offset from EMAC Base Address: <tt> 0x0038</tt> */ 147 #define MXC_R_EMAC_PFR ((uint32_t)0x0000003CUL) /**< Offset from EMAC Base Address: <tt> 0x003C</tt> */ 148 #define MXC_R_EMAC_FTOK ((uint32_t)0x00000040UL) /**< Offset from EMAC Base Address: <tt> 0x0040</tt> */ 149 #define MXC_R_EMAC_SCF ((uint32_t)0x00000044UL) /**< Offset from EMAC Base Address: <tt> 0x0044</tt> */ 150 #define MXC_R_EMAC_MCF ((uint32_t)0x00000048UL) /**< Offset from EMAC Base Address: <tt> 0x0048</tt> */ 151 #define MXC_R_EMAC_FROK ((uint32_t)0x0000004CUL) /**< Offset from EMAC Base Address: <tt> 0x004C</tt> */ 152 #define MXC_R_EMAC_FCS_ERR ((uint32_t)0x00000050UL) /**< Offset from EMAC Base Address: <tt> 0x0050</tt> */ 153 #define MXC_R_EMAC_ALGN_ERR ((uint32_t)0x00000054UL) /**< Offset from EMAC Base Address: <tt> 0x0054</tt> */ 154 #define MXC_R_EMAC_DFTXF ((uint32_t)0x00000058UL) /**< Offset from EMAC Base Address: <tt> 0x0058</tt> */ 155 #define MXC_R_EMAC_LC ((uint32_t)0x0000005CUL) /**< Offset from EMAC Base Address: <tt> 0x005C</tt> */ 156 #define MXC_R_EMAC_EC ((uint32_t)0x00000060UL) /**< Offset from EMAC Base Address: <tt> 0x0060</tt> */ 157 #define MXC_R_EMAC_TUR_ERR ((uint32_t)0x00000064UL) /**< Offset from EMAC Base Address: <tt> 0x0064</tt> */ 158 #define MXC_R_EMAC_CS_ERR ((uint32_t)0x00000068UL) /**< Offset from EMAC Base Address: <tt> 0x0068</tt> */ 159 #define MXC_R_EMAC_RR_ERR ((uint32_t)0x0000006CUL) /**< Offset from EMAC Base Address: <tt> 0x006C</tt> */ 160 #define MXC_R_EMAC_ROR_ERR ((uint32_t)0x00000070UL) /**< Offset from EMAC Base Address: <tt> 0x0070</tt> */ 161 #define MXC_R_EMAC_RS_ERR ((uint32_t)0x00000074UL) /**< Offset from EMAC Base Address: <tt> 0x0074</tt> */ 162 #define MXC_R_EMAC_EL_ERR ((uint32_t)0x00000078UL) /**< Offset from EMAC Base Address: <tt> 0x0078</tt> */ 163 #define MXC_R_EMAC_RJ ((uint32_t)0x0000007CUL) /**< Offset from EMAC Base Address: <tt> 0x007C</tt> */ 164 #define MXC_R_EMAC_USF ((uint32_t)0x00000080UL) /**< Offset from EMAC Base Address: <tt> 0x0080</tt> */ 165 #define MXC_R_EMAC_SQE_ERR ((uint32_t)0x00000084UL) /**< Offset from EMAC Base Address: <tt> 0x0084</tt> */ 166 #define MXC_R_EMAC_RLFM ((uint32_t)0x00000088UL) /**< Offset from EMAC Base Address: <tt> 0x0088</tt> */ 167 #define MXC_R_EMAC_TPF ((uint32_t)0x0000008CUL) /**< Offset from EMAC Base Address: <tt> 0x008C</tt> */ 168 #define MXC_R_EMAC_HASHL ((uint32_t)0x00000090UL) /**< Offset from EMAC Base Address: <tt> 0x0090</tt> */ 169 #define MXC_R_EMAC_HASHH ((uint32_t)0x00000094UL) /**< Offset from EMAC Base Address: <tt> 0x0094</tt> */ 170 #define MXC_R_EMAC_SA1L ((uint32_t)0x00000098UL) /**< Offset from EMAC Base Address: <tt> 0x0098</tt> */ 171 #define MXC_R_EMAC_SA1H ((uint32_t)0x0000009CUL) /**< Offset from EMAC Base Address: <tt> 0x009C</tt> */ 172 #define MXC_R_EMAC_SA2L ((uint32_t)0x000000A0UL) /**< Offset from EMAC Base Address: <tt> 0x00A0</tt> */ 173 #define MXC_R_EMAC_SA2H ((uint32_t)0x000000A4UL) /**< Offset from EMAC Base Address: <tt> 0x00A4</tt> */ 174 #define MXC_R_EMAC_SA3L ((uint32_t)0x000000A8UL) /**< Offset from EMAC Base Address: <tt> 0x00A8</tt> */ 175 #define MXC_R_EMAC_SA3H ((uint32_t)0x000000ACUL) /**< Offset from EMAC Base Address: <tt> 0x00AC</tt> */ 176 #define MXC_R_EMAC_SA4L ((uint32_t)0x000000B0UL) /**< Offset from EMAC Base Address: <tt> 0x00B0</tt> */ 177 #define MXC_R_EMAC_SA4H ((uint32_t)0x000000B4UL) /**< Offset from EMAC Base Address: <tt> 0x00B4</tt> */ 178 #define MXC_R_EMAC_TID_CK ((uint32_t)0x000000B8UL) /**< Offset from EMAC Base Address: <tt> 0x00B8</tt> */ 179 #define MXC_R_EMAC_TPQ ((uint32_t)0x000000BCUL) /**< Offset from EMAC Base Address: <tt> 0x00BC</tt> */ 180 #define MXC_R_EMAC_REV ((uint32_t)0x000000FCUL) /**< Offset from EMAC Base Address: <tt> 0x00FC</tt> */ 181 /**@} end of group emac_registers */ 182 183 /** 184 * @ingroup emac_registers 185 * @defgroup EMAC_CN EMAC_CN 186 * @brief Network Control Register. 187 * @{ 188 */ 189 #define MXC_F_EMAC_CN_LB_POS 0 /**< CN_LB Position */ 190 #define MXC_F_EMAC_CN_LB ((uint32_t)(0x1UL << MXC_F_EMAC_CN_LB_POS)) /**< CN_LB Mask */ 191 192 #define MXC_F_EMAC_CN_LBL_POS 1 /**< CN_LBL Position */ 193 #define MXC_F_EMAC_CN_LBL ((uint32_t)(0x1UL << MXC_F_EMAC_CN_LBL_POS)) /**< CN_LBL Mask */ 194 195 #define MXC_F_EMAC_CN_RXEN_POS 2 /**< CN_RXEN Position */ 196 #define MXC_F_EMAC_CN_RXEN ((uint32_t)(0x1UL << MXC_F_EMAC_CN_RXEN_POS)) /**< CN_RXEN Mask */ 197 198 #define MXC_F_EMAC_CN_TXEN_POS 3 /**< CN_TXEN Position */ 199 #define MXC_F_EMAC_CN_TXEN ((uint32_t)(0x1UL << MXC_F_EMAC_CN_TXEN_POS)) /**< CN_TXEN Mask */ 200 201 #define MXC_F_EMAC_CN_MPEN_POS 4 /**< CN_MPEN Position */ 202 #define MXC_F_EMAC_CN_MPEN ((uint32_t)(0x1UL << MXC_F_EMAC_CN_MPEN_POS)) /**< CN_MPEN Mask */ 203 204 #define MXC_F_EMAC_CN_CLST_POS 5 /**< CN_CLST Position */ 205 #define MXC_F_EMAC_CN_CLST ((uint32_t)(0x1UL << MXC_F_EMAC_CN_CLST_POS)) /**< CN_CLST Mask */ 206 207 #define MXC_F_EMAC_CN_INCST_POS 6 /**< CN_INCST Position */ 208 #define MXC_F_EMAC_CN_INCST ((uint32_t)(0x1UL << MXC_F_EMAC_CN_INCST_POS)) /**< CN_INCST Mask */ 209 210 #define MXC_F_EMAC_CN_WREN_POS 7 /**< CN_WREN Position */ 211 #define MXC_F_EMAC_CN_WREN ((uint32_t)(0x1UL << MXC_F_EMAC_CN_WREN_POS)) /**< CN_WREN Mask */ 212 213 #define MXC_F_EMAC_CN_BP_POS 8 /**< CN_BP Position */ 214 #define MXC_F_EMAC_CN_BP ((uint32_t)(0x1UL << MXC_F_EMAC_CN_BP_POS)) /**< CN_BP Mask */ 215 216 #define MXC_F_EMAC_CN_TXSTART_POS 9 /**< CN_TXSTART Position */ 217 #define MXC_F_EMAC_CN_TXSTART ((uint32_t)(0x1UL << MXC_F_EMAC_CN_TXSTART_POS)) /**< CN_TXSTART Mask */ 218 219 #define MXC_F_EMAC_CN_TXHALT_POS 10 /**< CN_TXHALT Position */ 220 #define MXC_F_EMAC_CN_TXHALT ((uint32_t)(0x1UL << MXC_F_EMAC_CN_TXHALT_POS)) /**< CN_TXHALT Mask */ 221 222 #define MXC_F_EMAC_CN_TXPF_POS 11 /**< CN_TXPF Position */ 223 #define MXC_F_EMAC_CN_TXPF ((uint32_t)(0x1UL << MXC_F_EMAC_CN_TXPF_POS)) /**< CN_TXPF Mask */ 224 225 #define MXC_F_EMAC_CN_TXZQPF_POS 12 /**< CN_TXZQPF Position */ 226 #define MXC_F_EMAC_CN_TXZQPF ((uint32_t)(0x1UL << MXC_F_EMAC_CN_TXZQPF_POS)) /**< CN_TXZQPF Mask */ 227 228 /**@} end of group EMAC_CN_Register */ 229 230 /** 231 * @ingroup emac_registers 232 * @defgroup EMAC_CFG EMAC_CFG 233 * @brief Network Configuration Register. 234 * @{ 235 */ 236 #define MXC_F_EMAC_CFG_SPEED_POS 0 /**< CFG_SPEED Position */ 237 #define MXC_F_EMAC_CFG_SPEED ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_SPEED_POS)) /**< CFG_SPEED Mask */ 238 239 #define MXC_F_EMAC_CFG_FULLDPLX_POS 1 /**< CFG_FULLDPLX Position */ 240 #define MXC_F_EMAC_CFG_FULLDPLX ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_FULLDPLX_POS)) /**< CFG_FULLDPLX Mask */ 241 242 #define MXC_F_EMAC_CFG_BITRATE_POS 2 /**< CFG_BITRATE Position */ 243 #define MXC_F_EMAC_CFG_BITRATE ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_BITRATE_POS)) /**< CFG_BITRATE Mask */ 244 245 #define MXC_F_EMAC_CFG_JUMBOFR_POS 3 /**< CFG_JUMBOFR Position */ 246 #define MXC_F_EMAC_CFG_JUMBOFR ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_JUMBOFR_POS)) /**< CFG_JUMBOFR Mask */ 247 248 #define MXC_F_EMAC_CFG_COPYAF_POS 4 /**< CFG_COPYAF Position */ 249 #define MXC_F_EMAC_CFG_COPYAF ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_COPYAF_POS)) /**< CFG_COPYAF Mask */ 250 251 #define MXC_F_EMAC_CFG_NOBC_POS 5 /**< CFG_NOBC Position */ 252 #define MXC_F_EMAC_CFG_NOBC ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_NOBC_POS)) /**< CFG_NOBC Mask */ 253 254 #define MXC_F_EMAC_CFG_MHEN_POS 6 /**< CFG_MHEN Position */ 255 #define MXC_F_EMAC_CFG_MHEN ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_MHEN_POS)) /**< CFG_MHEN Mask */ 256 257 #define MXC_F_EMAC_CFG_UHEN_POS 7 /**< CFG_UHEN Position */ 258 #define MXC_F_EMAC_CFG_UHEN ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_UHEN_POS)) /**< CFG_UHEN Mask */ 259 260 #define MXC_F_EMAC_CFG_RXFR_POS 8 /**< CFG_RXFR Position */ 261 #define MXC_F_EMAC_CFG_RXFR ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_RXFR_POS)) /**< CFG_RXFR Mask */ 262 263 #define MXC_F_EMAC_CFG_MDCCLK_POS 10 /**< CFG_MDCCLK Position */ 264 #define MXC_F_EMAC_CFG_MDCCLK ((uint32_t)(0x3UL << MXC_F_EMAC_CFG_MDCCLK_POS)) /**< CFG_MDCCLK Mask */ 265 #define MXC_V_EMAC_CFG_MDCCLK_DIV8 ((uint32_t)0x0UL) /**< CFG_MDCCLK_DIV8 Value */ 266 #define MXC_S_EMAC_CFG_MDCCLK_DIV8 (MXC_V_EMAC_CFG_MDCCLK_DIV8 << MXC_F_EMAC_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV8 Setting */ 267 #define MXC_V_EMAC_CFG_MDCCLK_DIV16 ((uint32_t)0x1UL) /**< CFG_MDCCLK_DIV16 Value */ 268 #define MXC_S_EMAC_CFG_MDCCLK_DIV16 (MXC_V_EMAC_CFG_MDCCLK_DIV16 << MXC_F_EMAC_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV16 Setting */ 269 #define MXC_V_EMAC_CFG_MDCCLK_DIV32 ((uint32_t)0x2UL) /**< CFG_MDCCLK_DIV32 Value */ 270 #define MXC_S_EMAC_CFG_MDCCLK_DIV32 (MXC_V_EMAC_CFG_MDCCLK_DIV32 << MXC_F_EMAC_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV32 Setting */ 271 #define MXC_V_EMAC_CFG_MDCCLK_DIV64 ((uint32_t)0x3UL) /**< CFG_MDCCLK_DIV64 Value */ 272 #define MXC_S_EMAC_CFG_MDCCLK_DIV64 (MXC_V_EMAC_CFG_MDCCLK_DIV64 << MXC_F_EMAC_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV64 Setting */ 273 274 #define MXC_F_EMAC_CFG_RTTST_POS 12 /**< CFG_RTTST Position */ 275 #define MXC_F_EMAC_CFG_RTTST ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_RTTST_POS)) /**< CFG_RTTST Mask */ 276 277 #define MXC_F_EMAC_CFG_PAUSEEN_POS 13 /**< CFG_PAUSEEN Position */ 278 #define MXC_F_EMAC_CFG_PAUSEEN ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_PAUSEEN_POS)) /**< CFG_PAUSEEN Mask */ 279 280 #define MXC_F_EMAC_CFG_RXBUFFOFS_POS 14 /**< CFG_RXBUFFOFS Position */ 281 #define MXC_F_EMAC_CFG_RXBUFFOFS ((uint32_t)(0x3UL << MXC_F_EMAC_CFG_RXBUFFOFS_POS)) /**< CFG_RXBUFFOFS Mask */ 282 283 #define MXC_F_EMAC_CFG_RXLFCEN_POS 16 /**< CFG_RXLFCEN Position */ 284 #define MXC_F_EMAC_CFG_RXLFCEN ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_RXLFCEN_POS)) /**< CFG_RXLFCEN Mask */ 285 286 #define MXC_F_EMAC_CFG_DCRXFCS_POS 17 /**< CFG_DCRXFCS Position */ 287 #define MXC_F_EMAC_CFG_DCRXFCS ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_DCRXFCS_POS)) /**< CFG_DCRXFCS Mask */ 288 289 #define MXC_F_EMAC_CFG_HDPLXRXEN_POS 18 /**< CFG_HDPLXRXEN Position */ 290 #define MXC_F_EMAC_CFG_HDPLXRXEN ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_HDPLXRXEN_POS)) /**< CFG_HDPLXRXEN Mask */ 291 292 #define MXC_F_EMAC_CFG_IGNRXFCS_POS 19 /**< CFG_IGNRXFCS Position */ 293 #define MXC_F_EMAC_CFG_IGNRXFCS ((uint32_t)(0x1UL << MXC_F_EMAC_CFG_IGNRXFCS_POS)) /**< CFG_IGNRXFCS Mask */ 294 295 /**@} end of group EMAC_CFG_Register */ 296 297 /** 298 * @ingroup emac_registers 299 * @defgroup EMAC_STATUS EMAC_STATUS 300 * @brief Network Status Register. 301 * @{ 302 */ 303 #define MXC_F_EMAC_STATUS_LINK_POS 0 /**< STATUS_LINK Position */ 304 #define MXC_F_EMAC_STATUS_LINK ((uint32_t)(0x1UL << MXC_F_EMAC_STATUS_LINK_POS)) /**< STATUS_LINK Mask */ 305 306 #define MXC_F_EMAC_STATUS_MDIO_POS 1 /**< STATUS_MDIO Position */ 307 #define MXC_F_EMAC_STATUS_MDIO ((uint32_t)(0x1UL << MXC_F_EMAC_STATUS_MDIO_POS)) /**< STATUS_MDIO Mask */ 308 309 #define MXC_F_EMAC_STATUS_IDLE_POS 2 /**< STATUS_IDLE Position */ 310 #define MXC_F_EMAC_STATUS_IDLE ((uint32_t)(0x1UL << MXC_F_EMAC_STATUS_IDLE_POS)) /**< STATUS_IDLE Mask */ 311 312 /**@} end of group EMAC_STATUS_Register */ 313 314 /** 315 * @ingroup emac_registers 316 * @defgroup EMAC_TX_ST EMAC_TX_ST 317 * @brief Transmit Status Register. 318 * @{ 319 */ 320 #define MXC_F_EMAC_TX_ST_UBR_POS 0 /**< TX_ST_UBR Position */ 321 #define MXC_F_EMAC_TX_ST_UBR ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_UBR_POS)) /**< TX_ST_UBR Mask */ 322 323 #define MXC_F_EMAC_TX_ST_COLS_POS 1 /**< TX_ST_COLS Position */ 324 #define MXC_F_EMAC_TX_ST_COLS ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_COLS_POS)) /**< TX_ST_COLS Mask */ 325 326 #define MXC_F_EMAC_TX_ST_RTYLIM_POS 2 /**< TX_ST_RTYLIM Position */ 327 #define MXC_F_EMAC_TX_ST_RTYLIM ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_RTYLIM_POS)) /**< TX_ST_RTYLIM Mask */ 328 329 #define MXC_F_EMAC_TX_ST_TXGO_POS 3 /**< TX_ST_TXGO Position */ 330 #define MXC_F_EMAC_TX_ST_TXGO ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_TXGO_POS)) /**< TX_ST_TXGO Mask */ 331 332 #define MXC_F_EMAC_TX_ST_BEMF_POS 4 /**< TX_ST_BEMF Position */ 333 #define MXC_F_EMAC_TX_ST_BEMF ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_BEMF_POS)) /**< TX_ST_BEMF Mask */ 334 335 #define MXC_F_EMAC_TX_ST_TXCMPL_POS 5 /**< TX_ST_TXCMPL Position */ 336 #define MXC_F_EMAC_TX_ST_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_TXCMPL_POS)) /**< TX_ST_TXCMPL Mask */ 337 338 #define MXC_F_EMAC_TX_ST_TXUR_POS 6 /**< TX_ST_TXUR Position */ 339 #define MXC_F_EMAC_TX_ST_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_TX_ST_TXUR_POS)) /**< TX_ST_TXUR Mask */ 340 341 /**@} end of group EMAC_TX_ST_Register */ 342 343 /** 344 * @ingroup emac_registers 345 * @defgroup EMAC_RXBUF_PTR EMAC_RXBUF_PTR 346 * @brief Receive Buffer Queue Pointer Register. 347 * @{ 348 */ 349 #define MXC_F_EMAC_RXBUF_PTR_RXBUF_POS 2 /**< RXBUF_PTR_RXBUF Position */ 350 #define MXC_F_EMAC_RXBUF_PTR_RXBUF ((uint32_t)(0x3FFFFFFFUL << MXC_F_EMAC_RXBUF_PTR_RXBUF_POS)) /**< RXBUF_PTR_RXBUF Mask */ 351 352 /**@} end of group EMAC_RXBUF_PTR_Register */ 353 354 /** 355 * @ingroup emac_registers 356 * @defgroup EMAC_TXBUF_PTR EMAC_TXBUF_PTR 357 * @brief Transmit Buffer Queue Pointer Register. 358 * @{ 359 */ 360 #define MXC_F_EMAC_TXBUF_PTR_TXBUF_POS 2 /**< TXBUF_PTR_TXBUF Position */ 361 #define MXC_F_EMAC_TXBUF_PTR_TXBUF ((uint32_t)(0x3FFFFFFFUL << MXC_F_EMAC_TXBUF_PTR_TXBUF_POS)) /**< TXBUF_PTR_TXBUF Mask */ 362 363 /**@} end of group EMAC_TXBUF_PTR_Register */ 364 365 /** 366 * @ingroup emac_registers 367 * @defgroup EMAC_RX_ST EMAC_RX_ST 368 * @brief Receive Status Register. 369 * @{ 370 */ 371 #define MXC_F_EMAC_RX_ST_BNA_POS 0 /**< RX_ST_BNA Position */ 372 #define MXC_F_EMAC_RX_ST_BNA ((uint32_t)(0x1UL << MXC_F_EMAC_RX_ST_BNA_POS)) /**< RX_ST_BNA Mask */ 373 374 #define MXC_F_EMAC_RX_ST_FR_POS 1 /**< RX_ST_FR Position */ 375 #define MXC_F_EMAC_RX_ST_FR ((uint32_t)(0x1UL << MXC_F_EMAC_RX_ST_FR_POS)) /**< RX_ST_FR Mask */ 376 377 #define MXC_F_EMAC_RX_ST_RXOR_POS 2 /**< RX_ST_RXOR Position */ 378 #define MXC_F_EMAC_RX_ST_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_RX_ST_RXOR_POS)) /**< RX_ST_RXOR Mask */ 379 380 /**@} end of group EMAC_RX_ST_Register */ 381 382 /** 383 * @ingroup emac_registers 384 * @defgroup EMAC_INT_ST EMAC_INT_ST 385 * @brief Interrupt Status Register. 386 * @{ 387 */ 388 #define MXC_F_EMAC_INT_ST_MPS_POS 0 /**< INT_ST_MPS Position */ 389 #define MXC_F_EMAC_INT_ST_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_MPS_POS)) /**< INT_ST_MPS Mask */ 390 391 #define MXC_F_EMAC_INT_ST_RXCMPL_POS 1 /**< INT_ST_RXCMPL Position */ 392 #define MXC_F_EMAC_INT_ST_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_RXCMPL_POS)) /**< INT_ST_RXCMPL Mask */ 393 394 #define MXC_F_EMAC_INT_ST_RXUBR_POS 2 /**< INT_ST_RXUBR Position */ 395 #define MXC_F_EMAC_INT_ST_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_RXUBR_POS)) /**< INT_ST_RXUBR Mask */ 396 397 #define MXC_F_EMAC_INT_ST_TXUBR_POS 3 /**< INT_ST_TXUBR Position */ 398 #define MXC_F_EMAC_INT_ST_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_TXUBR_POS)) /**< INT_ST_TXUBR Mask */ 399 400 #define MXC_F_EMAC_INT_ST_TXUR_POS 4 /**< INT_ST_TXUR Position */ 401 #define MXC_F_EMAC_INT_ST_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_TXUR_POS)) /**< INT_ST_TXUR Mask */ 402 403 #define MXC_F_EMAC_INT_ST_RLE_POS 5 /**< INT_ST_RLE Position */ 404 #define MXC_F_EMAC_INT_ST_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_RLE_POS)) /**< INT_ST_RLE Mask */ 405 406 #define MXC_F_EMAC_INT_ST_TXERR_POS 6 /**< INT_ST_TXERR Position */ 407 #define MXC_F_EMAC_INT_ST_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_TXERR_POS)) /**< INT_ST_TXERR Mask */ 408 409 #define MXC_F_EMAC_INT_ST_TXCMPL_POS 7 /**< INT_ST_TXCMPL Position */ 410 #define MXC_F_EMAC_INT_ST_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_TXCMPL_POS)) /**< INT_ST_TXCMPL Mask */ 411 412 #define MXC_F_EMAC_INT_ST_LC_POS 9 /**< INT_ST_LC Position */ 413 #define MXC_F_EMAC_INT_ST_LC ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_LC_POS)) /**< INT_ST_LC Mask */ 414 415 #define MXC_F_EMAC_INT_ST_RXOR_POS 10 /**< INT_ST_RXOR Position */ 416 #define MXC_F_EMAC_INT_ST_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_RXOR_POS)) /**< INT_ST_RXOR Mask */ 417 418 #define MXC_F_EMAC_INT_ST_HRESPNO_POS 11 /**< INT_ST_HRESPNO Position */ 419 #define MXC_F_EMAC_INT_ST_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_HRESPNO_POS)) /**< INT_ST_HRESPNO Mask */ 420 421 #define MXC_F_EMAC_INT_ST_PPR_POS 12 /**< INT_ST_PPR Position */ 422 #define MXC_F_EMAC_INT_ST_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_PPR_POS)) /**< INT_ST_PPR Mask */ 423 424 #define MXC_F_EMAC_INT_ST_PTZ_POS 13 /**< INT_ST_PTZ Position */ 425 #define MXC_F_EMAC_INT_ST_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_INT_ST_PTZ_POS)) /**< INT_ST_PTZ Mask */ 426 427 /**@} end of group EMAC_INT_ST_Register */ 428 429 /** 430 * @ingroup emac_registers 431 * @defgroup EMAC_INT_EN EMAC_INT_EN 432 * @brief Interrupt Enable Register. 433 * @{ 434 */ 435 #define MXC_F_EMAC_INT_EN_MPS_POS 0 /**< INT_EN_MPS Position */ 436 #define MXC_F_EMAC_INT_EN_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_MPS_POS)) /**< INT_EN_MPS Mask */ 437 438 #define MXC_F_EMAC_INT_EN_RXCMPL_POS 1 /**< INT_EN_RXCMPL Position */ 439 #define MXC_F_EMAC_INT_EN_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_RXCMPL_POS)) /**< INT_EN_RXCMPL Mask */ 440 441 #define MXC_F_EMAC_INT_EN_RXUBR_POS 2 /**< INT_EN_RXUBR Position */ 442 #define MXC_F_EMAC_INT_EN_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_RXUBR_POS)) /**< INT_EN_RXUBR Mask */ 443 444 #define MXC_F_EMAC_INT_EN_TXUBR_POS 3 /**< INT_EN_TXUBR Position */ 445 #define MXC_F_EMAC_INT_EN_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_TXUBR_POS)) /**< INT_EN_TXUBR Mask */ 446 447 #define MXC_F_EMAC_INT_EN_TXUR_POS 4 /**< INT_EN_TXUR Position */ 448 #define MXC_F_EMAC_INT_EN_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_TXUR_POS)) /**< INT_EN_TXUR Mask */ 449 450 #define MXC_F_EMAC_INT_EN_RLE_POS 5 /**< INT_EN_RLE Position */ 451 #define MXC_F_EMAC_INT_EN_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_RLE_POS)) /**< INT_EN_RLE Mask */ 452 453 #define MXC_F_EMAC_INT_EN_TXERR_POS 6 /**< INT_EN_TXERR Position */ 454 #define MXC_F_EMAC_INT_EN_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_TXERR_POS)) /**< INT_EN_TXERR Mask */ 455 456 #define MXC_F_EMAC_INT_EN_TXCMPL_POS 7 /**< INT_EN_TXCMPL Position */ 457 #define MXC_F_EMAC_INT_EN_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_TXCMPL_POS)) /**< INT_EN_TXCMPL Mask */ 458 459 #define MXC_F_EMAC_INT_EN_LC_POS 9 /**< INT_EN_LC Position */ 460 #define MXC_F_EMAC_INT_EN_LC ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_LC_POS)) /**< INT_EN_LC Mask */ 461 462 #define MXC_F_EMAC_INT_EN_RXOR_POS 10 /**< INT_EN_RXOR Position */ 463 #define MXC_F_EMAC_INT_EN_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_RXOR_POS)) /**< INT_EN_RXOR Mask */ 464 465 #define MXC_F_EMAC_INT_EN_HRESPNO_POS 11 /**< INT_EN_HRESPNO Position */ 466 #define MXC_F_EMAC_INT_EN_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_HRESPNO_POS)) /**< INT_EN_HRESPNO Mask */ 467 468 #define MXC_F_EMAC_INT_EN_PPR_POS 12 /**< INT_EN_PPR Position */ 469 #define MXC_F_EMAC_INT_EN_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_PPR_POS)) /**< INT_EN_PPR Mask */ 470 471 #define MXC_F_EMAC_INT_EN_PTZ_POS 13 /**< INT_EN_PTZ Position */ 472 #define MXC_F_EMAC_INT_EN_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_INT_EN_PTZ_POS)) /**< INT_EN_PTZ Mask */ 473 474 /**@} end of group EMAC_INT_EN_Register */ 475 476 /** 477 * @ingroup emac_registers 478 * @defgroup EMAC_INT_DIS EMAC_INT_DIS 479 * @brief Interrupt Disable Register. 480 * @{ 481 */ 482 #define MXC_F_EMAC_INT_DIS_MPS_POS 0 /**< INT_DIS_MPS Position */ 483 #define MXC_F_EMAC_INT_DIS_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_MPS_POS)) /**< INT_DIS_MPS Mask */ 484 485 #define MXC_F_EMAC_INT_DIS_RXCMPL_POS 1 /**< INT_DIS_RXCMPL Position */ 486 #define MXC_F_EMAC_INT_DIS_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_RXCMPL_POS)) /**< INT_DIS_RXCMPL Mask */ 487 488 #define MXC_F_EMAC_INT_DIS_RXUBR_POS 2 /**< INT_DIS_RXUBR Position */ 489 #define MXC_F_EMAC_INT_DIS_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_RXUBR_POS)) /**< INT_DIS_RXUBR Mask */ 490 491 #define MXC_F_EMAC_INT_DIS_TXUBR_POS 3 /**< INT_DIS_TXUBR Position */ 492 #define MXC_F_EMAC_INT_DIS_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_TXUBR_POS)) /**< INT_DIS_TXUBR Mask */ 493 494 #define MXC_F_EMAC_INT_DIS_TXUR_POS 4 /**< INT_DIS_TXUR Position */ 495 #define MXC_F_EMAC_INT_DIS_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_TXUR_POS)) /**< INT_DIS_TXUR Mask */ 496 497 #define MXC_F_EMAC_INT_DIS_RLE_POS 5 /**< INT_DIS_RLE Position */ 498 #define MXC_F_EMAC_INT_DIS_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_RLE_POS)) /**< INT_DIS_RLE Mask */ 499 500 #define MXC_F_EMAC_INT_DIS_TXERR_POS 6 /**< INT_DIS_TXERR Position */ 501 #define MXC_F_EMAC_INT_DIS_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_TXERR_POS)) /**< INT_DIS_TXERR Mask */ 502 503 #define MXC_F_EMAC_INT_DIS_TXCMPL_POS 7 /**< INT_DIS_TXCMPL Position */ 504 #define MXC_F_EMAC_INT_DIS_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_TXCMPL_POS)) /**< INT_DIS_TXCMPL Mask */ 505 506 #define MXC_F_EMAC_INT_DIS_LC_POS 9 /**< INT_DIS_LC Position */ 507 #define MXC_F_EMAC_INT_DIS_LC ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_LC_POS)) /**< INT_DIS_LC Mask */ 508 509 #define MXC_F_EMAC_INT_DIS_RXOR_POS 10 /**< INT_DIS_RXOR Position */ 510 #define MXC_F_EMAC_INT_DIS_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_RXOR_POS)) /**< INT_DIS_RXOR Mask */ 511 512 #define MXC_F_EMAC_INT_DIS_HRESPNO_POS 11 /**< INT_DIS_HRESPNO Position */ 513 #define MXC_F_EMAC_INT_DIS_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_HRESPNO_POS)) /**< INT_DIS_HRESPNO Mask */ 514 515 #define MXC_F_EMAC_INT_DIS_PPR_POS 12 /**< INT_DIS_PPR Position */ 516 #define MXC_F_EMAC_INT_DIS_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_PPR_POS)) /**< INT_DIS_PPR Mask */ 517 518 #define MXC_F_EMAC_INT_DIS_PTZ_POS 13 /**< INT_DIS_PTZ Position */ 519 #define MXC_F_EMAC_INT_DIS_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_INT_DIS_PTZ_POS)) /**< INT_DIS_PTZ Mask */ 520 521 /**@} end of group EMAC_INT_DIS_Register */ 522 523 /** 524 * @ingroup emac_registers 525 * @defgroup EMAC_INT_MASK EMAC_INT_MASK 526 * @brief Interrupt Mask Register. 527 * @{ 528 */ 529 #define MXC_F_EMAC_INT_MASK_MPS_POS 0 /**< INT_MASK_MPS Position */ 530 #define MXC_F_EMAC_INT_MASK_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_MPS_POS)) /**< INT_MASK_MPS Mask */ 531 532 #define MXC_F_EMAC_INT_MASK_RXCMPL_POS 1 /**< INT_MASK_RXCMPL Position */ 533 #define MXC_F_EMAC_INT_MASK_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_RXCMPL_POS)) /**< INT_MASK_RXCMPL Mask */ 534 535 #define MXC_F_EMAC_INT_MASK_RXUBR_POS 2 /**< INT_MASK_RXUBR Position */ 536 #define MXC_F_EMAC_INT_MASK_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_RXUBR_POS)) /**< INT_MASK_RXUBR Mask */ 537 538 #define MXC_F_EMAC_INT_MASK_TXUBR_POS 3 /**< INT_MASK_TXUBR Position */ 539 #define MXC_F_EMAC_INT_MASK_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_TXUBR_POS)) /**< INT_MASK_TXUBR Mask */ 540 541 #define MXC_F_EMAC_INT_MASK_TXUR_POS 4 /**< INT_MASK_TXUR Position */ 542 #define MXC_F_EMAC_INT_MASK_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_TXUR_POS)) /**< INT_MASK_TXUR Mask */ 543 544 #define MXC_F_EMAC_INT_MASK_RLE_POS 5 /**< INT_MASK_RLE Position */ 545 #define MXC_F_EMAC_INT_MASK_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_RLE_POS)) /**< INT_MASK_RLE Mask */ 546 547 #define MXC_F_EMAC_INT_MASK_TXERR_POS 6 /**< INT_MASK_TXERR Position */ 548 #define MXC_F_EMAC_INT_MASK_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_TXERR_POS)) /**< INT_MASK_TXERR Mask */ 549 550 #define MXC_F_EMAC_INT_MASK_TXCMPL_POS 7 /**< INT_MASK_TXCMPL Position */ 551 #define MXC_F_EMAC_INT_MASK_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_TXCMPL_POS)) /**< INT_MASK_TXCMPL Mask */ 552 553 #define MXC_F_EMAC_INT_MASK_LC_POS 9 /**< INT_MASK_LC Position */ 554 #define MXC_F_EMAC_INT_MASK_LC ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_LC_POS)) /**< INT_MASK_LC Mask */ 555 556 #define MXC_F_EMAC_INT_MASK_RXOR_POS 10 /**< INT_MASK_RXOR Position */ 557 #define MXC_F_EMAC_INT_MASK_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_RXOR_POS)) /**< INT_MASK_RXOR Mask */ 558 559 #define MXC_F_EMAC_INT_MASK_HRESPNO_POS 11 /**< INT_MASK_HRESPNO Position */ 560 #define MXC_F_EMAC_INT_MASK_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_HRESPNO_POS)) /**< INT_MASK_HRESPNO Mask */ 561 562 #define MXC_F_EMAC_INT_MASK_PPR_POS 12 /**< INT_MASK_PPR Position */ 563 #define MXC_F_EMAC_INT_MASK_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_PPR_POS)) /**< INT_MASK_PPR Mask */ 564 565 #define MXC_F_EMAC_INT_MASK_PTZ_POS 13 /**< INT_MASK_PTZ Position */ 566 #define MXC_F_EMAC_INT_MASK_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_INT_MASK_PTZ_POS)) /**< INT_MASK_PTZ Mask */ 567 568 /**@} end of group EMAC_INT_MASK_Register */ 569 570 /** 571 * @ingroup emac_registers 572 * @defgroup EMAC_PHY_MT EMAC_PHY_MT 573 * @brief PHY Maintenance Register. 574 * @{ 575 */ 576 #define MXC_F_EMAC_PHY_MT_DATA_POS 0 /**< PHY_MT_DATA Position */ 577 #define MXC_F_EMAC_PHY_MT_DATA ((uint32_t)(0xFFFFUL << MXC_F_EMAC_PHY_MT_DATA_POS)) /**< PHY_MT_DATA Mask */ 578 579 #define MXC_F_EMAC_PHY_MT_REGADDR_POS 18 /**< PHY_MT_REGADDR Position */ 580 #define MXC_F_EMAC_PHY_MT_REGADDR ((uint32_t)(0x1FUL << MXC_F_EMAC_PHY_MT_REGADDR_POS)) /**< PHY_MT_REGADDR Mask */ 581 582 #define MXC_F_EMAC_PHY_MT_PHYADDR_POS 23 /**< PHY_MT_PHYADDR Position */ 583 #define MXC_F_EMAC_PHY_MT_PHYADDR ((uint32_t)(0x1FUL << MXC_F_EMAC_PHY_MT_PHYADDR_POS)) /**< PHY_MT_PHYADDR Mask */ 584 585 #define MXC_F_EMAC_PHY_MT_OP_POS 28 /**< PHY_MT_OP Position */ 586 #define MXC_F_EMAC_PHY_MT_OP ((uint32_t)(0x3UL << MXC_F_EMAC_PHY_MT_OP_POS)) /**< PHY_MT_OP Mask */ 587 #define MXC_V_EMAC_PHY_MT_OP_WRITE ((uint32_t)0x1UL) /**< PHY_MT_OP_WRITE Value */ 588 #define MXC_S_EMAC_PHY_MT_OP_WRITE (MXC_V_EMAC_PHY_MT_OP_WRITE << MXC_F_EMAC_PHY_MT_OP_POS) /**< PHY_MT_OP_WRITE Setting */ 589 #define MXC_V_EMAC_PHY_MT_OP_READ ((uint32_t)0x2UL) /**< PHY_MT_OP_READ Value */ 590 #define MXC_S_EMAC_PHY_MT_OP_READ (MXC_V_EMAC_PHY_MT_OP_READ << MXC_F_EMAC_PHY_MT_OP_POS) /**< PHY_MT_OP_READ Setting */ 591 592 #define MXC_F_EMAC_PHY_MT_SOP_POS 30 /**< PHY_MT_SOP Position */ 593 #define MXC_F_EMAC_PHY_MT_SOP ((uint32_t)(0x3UL << MXC_F_EMAC_PHY_MT_SOP_POS)) /**< PHY_MT_SOP Mask */ 594 595 /**@} end of group EMAC_PHY_MT_Register */ 596 597 /** 598 * @ingroup emac_registers 599 * @defgroup EMAC_PT EMAC_PT 600 * @brief Pause Time Register. 601 * @{ 602 */ 603 #define MXC_F_EMAC_PT_TIME_POS 0 /**< PT_TIME Position */ 604 #define MXC_F_EMAC_PT_TIME ((uint32_t)(0xFFFFUL << MXC_F_EMAC_PT_TIME_POS)) /**< PT_TIME Mask */ 605 606 /**@} end of group EMAC_PT_Register */ 607 608 /** 609 * @ingroup emac_registers 610 * @defgroup EMAC_PFR EMAC_PFR 611 * @brief Pause Frame Received OK. 612 * @{ 613 */ 614 #define MXC_F_EMAC_PFR_PFR_POS 0 /**< PFR_PFR Position */ 615 #define MXC_F_EMAC_PFR_PFR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_PFR_PFR_POS)) /**< PFR_PFR Mask */ 616 617 /**@} end of group EMAC_PFR_Register */ 618 619 /** 620 * @ingroup emac_registers 621 * @defgroup EMAC_FTOK EMAC_FTOK 622 * @brief Frames Transmitted OK. 623 * @{ 624 */ 625 #define MXC_F_EMAC_FTOK_FTOK_POS 0 /**< FTOK_FTOK Position */ 626 #define MXC_F_EMAC_FTOK_FTOK ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_FTOK_FTOK_POS)) /**< FTOK_FTOK Mask */ 627 628 /**@} end of group EMAC_FTOK_Register */ 629 630 /** 631 * @ingroup emac_registers 632 * @defgroup EMAC_SCF EMAC_SCF 633 * @brief Single Collision Frames. 634 * @{ 635 */ 636 #define MXC_F_EMAC_SCF_SCF_POS 0 /**< SCF_SCF Position */ 637 #define MXC_F_EMAC_SCF_SCF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_SCF_SCF_POS)) /**< SCF_SCF Mask */ 638 639 /**@} end of group EMAC_SCF_Register */ 640 641 /** 642 * @ingroup emac_registers 643 * @defgroup EMAC_MCF EMAC_MCF 644 * @brief Multiple Collision Frames. 645 * @{ 646 */ 647 #define MXC_F_EMAC_MCF_MCF_POS 0 /**< MCF_MCF Position */ 648 #define MXC_F_EMAC_MCF_MCF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_MCF_MCF_POS)) /**< MCF_MCF Mask */ 649 650 /**@} end of group EMAC_MCF_Register */ 651 652 /** 653 * @ingroup emac_registers 654 * @defgroup EMAC_FROK EMAC_FROK 655 * @brief Fames Received OK. 656 * @{ 657 */ 658 #define MXC_F_EMAC_FROK_FROK_POS 0 /**< FROK_FROK Position */ 659 #define MXC_F_EMAC_FROK_FROK ((uint32_t)(0xFFFFFFUL << MXC_F_EMAC_FROK_FROK_POS)) /**< FROK_FROK Mask */ 660 661 /**@} end of group EMAC_FROK_Register */ 662 663 /** 664 * @ingroup emac_registers 665 * @defgroup EMAC_FCS_ERR EMAC_FCS_ERR 666 * @brief Frame Check Sequence Errors. 667 * @{ 668 */ 669 #define MXC_F_EMAC_FCS_ERR_FCSERR_POS 0 /**< FCS_ERR_FCSERR Position */ 670 #define MXC_F_EMAC_FCS_ERR_FCSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_FCS_ERR_FCSERR_POS)) /**< FCS_ERR_FCSERR Mask */ 671 672 /**@} end of group EMAC_FCS_ERR_Register */ 673 674 /** 675 * @ingroup emac_registers 676 * @defgroup EMAC_ALGN_ERR EMAC_ALGN_ERR 677 * @brief Alignment Errors. 678 * @{ 679 */ 680 #define MXC_F_EMAC_ALGN_ERR_ALGNERR_POS 0 /**< ALGN_ERR_ALGNERR Position */ 681 #define MXC_F_EMAC_ALGN_ERR_ALGNERR ((uint32_t)(0xFFUL << MXC_F_EMAC_ALGN_ERR_ALGNERR_POS)) /**< ALGN_ERR_ALGNERR Mask */ 682 683 /**@} end of group EMAC_ALGN_ERR_Register */ 684 685 /** 686 * @ingroup emac_registers 687 * @defgroup EMAC_DFTXF EMAC_DFTXF 688 * @brief Deferred Transmission Frames. 689 * @{ 690 */ 691 #define MXC_F_EMAC_DFTXF_DFTXF_POS 0 /**< DFTXF_DFTXF Position */ 692 #define MXC_F_EMAC_DFTXF_DFTXF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_DFTXF_DFTXF_POS)) /**< DFTXF_DFTXF Mask */ 693 694 /**@} end of group EMAC_DFTXF_Register */ 695 696 /** 697 * @ingroup emac_registers 698 * @defgroup EMAC_LC EMAC_LC 699 * @brief Late Collisions. 700 * @{ 701 */ 702 #define MXC_F_EMAC_LC_LC_POS 0 /**< LC_LC Position */ 703 #define MXC_F_EMAC_LC_LC ((uint32_t)(0xFFUL << MXC_F_EMAC_LC_LC_POS)) /**< LC_LC Mask */ 704 705 /**@} end of group EMAC_LC_Register */ 706 707 /** 708 * @ingroup emac_registers 709 * @defgroup EMAC_EC EMAC_EC 710 * @brief Excessive Collisions. 711 * @{ 712 */ 713 #define MXC_F_EMAC_EC_EC_POS 0 /**< EC_EC Position */ 714 #define MXC_F_EMAC_EC_EC ((uint32_t)(0xFFUL << MXC_F_EMAC_EC_EC_POS)) /**< EC_EC Mask */ 715 716 /**@} end of group EMAC_EC_Register */ 717 718 /** 719 * @ingroup emac_registers 720 * @defgroup EMAC_TUR_ERR EMAC_TUR_ERR 721 * @brief Transmit Underrun Errors. 722 * @{ 723 */ 724 #define MXC_F_EMAC_TUR_ERR_TURERR_POS 0 /**< TUR_ERR_TURERR Position */ 725 #define MXC_F_EMAC_TUR_ERR_TURERR ((uint32_t)(0xFFUL << MXC_F_EMAC_TUR_ERR_TURERR_POS)) /**< TUR_ERR_TURERR Mask */ 726 727 /**@} end of group EMAC_TUR_ERR_Register */ 728 729 /** 730 * @ingroup emac_registers 731 * @defgroup EMAC_CS_ERR EMAC_CS_ERR 732 * @brief Carrier Sense Errors. 733 * @{ 734 */ 735 #define MXC_F_EMAC_CS_ERR_CSERR_POS 0 /**< CS_ERR_CSERR Position */ 736 #define MXC_F_EMAC_CS_ERR_CSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_CS_ERR_CSERR_POS)) /**< CS_ERR_CSERR Mask */ 737 738 /**@} end of group EMAC_CS_ERR_Register */ 739 740 /** 741 * @ingroup emac_registers 742 * @defgroup EMAC_RR_ERR EMAC_RR_ERR 743 * @brief Receive Resource Errors. 744 * @{ 745 */ 746 #define MXC_F_EMAC_RR_ERR_RRERR_POS 0 /**< RR_ERR_RRERR Position */ 747 #define MXC_F_EMAC_RR_ERR_RRERR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_RR_ERR_RRERR_POS)) /**< RR_ERR_RRERR Mask */ 748 749 /**@} end of group EMAC_RR_ERR_Register */ 750 751 /** 752 * @ingroup emac_registers 753 * @defgroup EMAC_ROR_ERR EMAC_ROR_ERR 754 * @brief Receive Overrun Errors. 755 * @{ 756 */ 757 #define MXC_F_EMAC_ROR_ERR_RORERR_POS 0 /**< ROR_ERR_RORERR Position */ 758 #define MXC_F_EMAC_ROR_ERR_RORERR ((uint32_t)(0xFFUL << MXC_F_EMAC_ROR_ERR_RORERR_POS)) /**< ROR_ERR_RORERR Mask */ 759 760 /**@} end of group EMAC_ROR_ERR_Register */ 761 762 /** 763 * @ingroup emac_registers 764 * @defgroup EMAC_RS_ERR EMAC_RS_ERR 765 * @brief Receive Symbol Errors. 766 * @{ 767 */ 768 #define MXC_F_EMAC_RS_ERR_RSERR_POS 0 /**< RS_ERR_RSERR Position */ 769 #define MXC_F_EMAC_RS_ERR_RSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_RS_ERR_RSERR_POS)) /**< RS_ERR_RSERR Mask */ 770 771 /**@} end of group EMAC_RS_ERR_Register */ 772 773 /** 774 * @ingroup emac_registers 775 * @defgroup EMAC_EL_ERR EMAC_EL_ERR 776 * @brief Excessive Length Errors. 777 * @{ 778 */ 779 #define MXC_F_EMAC_EL_ERR_ELERR_POS 0 /**< EL_ERR_ELERR Position */ 780 #define MXC_F_EMAC_EL_ERR_ELERR ((uint32_t)(0xFFUL << MXC_F_EMAC_EL_ERR_ELERR_POS)) /**< EL_ERR_ELERR Mask */ 781 782 /**@} end of group EMAC_EL_ERR_Register */ 783 784 /** 785 * @ingroup emac_registers 786 * @defgroup EMAC_RJ EMAC_RJ 787 * @brief Receive Jabber. 788 * @{ 789 */ 790 #define MXC_F_EMAC_RJ_RJERR_POS 0 /**< RJ_RJERR Position */ 791 #define MXC_F_EMAC_RJ_RJERR ((uint32_t)(0xFFUL << MXC_F_EMAC_RJ_RJERR_POS)) /**< RJ_RJERR Mask */ 792 793 /**@} end of group EMAC_RJ_Register */ 794 795 /** 796 * @ingroup emac_registers 797 * @defgroup EMAC_USF EMAC_USF 798 * @brief Undersize Frames. 799 * @{ 800 */ 801 #define MXC_F_EMAC_USF_USF_POS 0 /**< USF_USF Position */ 802 #define MXC_F_EMAC_USF_USF ((uint32_t)(0xFFUL << MXC_F_EMAC_USF_USF_POS)) /**< USF_USF Mask */ 803 804 /**@} end of group EMAC_USF_Register */ 805 806 /** 807 * @ingroup emac_registers 808 * @defgroup EMAC_SQE_ERR EMAC_SQE_ERR 809 * @brief SQE Test Errors. 810 * @{ 811 */ 812 #define MXC_F_EMAC_SQE_ERR_SQEERR_POS 0 /**< SQE_ERR_SQEERR Position */ 813 #define MXC_F_EMAC_SQE_ERR_SQEERR ((uint32_t)(0xFFUL << MXC_F_EMAC_SQE_ERR_SQEERR_POS)) /**< SQE_ERR_SQEERR Mask */ 814 815 /**@} end of group EMAC_SQE_ERR_Register */ 816 817 /** 818 * @ingroup emac_registers 819 * @defgroup EMAC_RLFM EMAC_RLFM 820 * @brief Received Length Field Mismatch. 821 * @{ 822 */ 823 #define MXC_F_EMAC_RLFM_RLFM_POS 0 /**< RLFM_RLFM Position */ 824 #define MXC_F_EMAC_RLFM_RLFM ((uint32_t)(0xFFUL << MXC_F_EMAC_RLFM_RLFM_POS)) /**< RLFM_RLFM Mask */ 825 826 /**@} end of group EMAC_RLFM_Register */ 827 828 /** 829 * @ingroup emac_registers 830 * @defgroup EMAC_TPF EMAC_TPF 831 * @brief Transmitted Pause Frames. 832 * @{ 833 */ 834 #define MXC_F_EMAC_TPF_TPF_POS 0 /**< TPF_TPF Position */ 835 #define MXC_F_EMAC_TPF_TPF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_TPF_TPF_POS)) /**< TPF_TPF Mask */ 836 837 /**@} end of group EMAC_TPF_Register */ 838 839 /** 840 * @ingroup emac_registers 841 * @defgroup EMAC_HASHL EMAC_HASHL 842 * @brief Hash Register Bottom [31:0]. 843 * @{ 844 */ 845 #define MXC_F_EMAC_HASHL_HASH_POS 0 /**< HASHL_HASH Position */ 846 #define MXC_F_EMAC_HASHL_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_HASHL_HASH_POS)) /**< HASHL_HASH Mask */ 847 848 /**@} end of group EMAC_HASHL_Register */ 849 850 /** 851 * @ingroup emac_registers 852 * @defgroup EMAC_HASHH EMAC_HASHH 853 * @brief Hash Register top [63:32]. 854 * @{ 855 */ 856 #define MXC_F_EMAC_HASHH_HASH_POS 0 /**< HASHH_HASH Position */ 857 #define MXC_F_EMAC_HASHH_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_HASHH_HASH_POS)) /**< HASHH_HASH Mask */ 858 859 /**@} end of group EMAC_HASHH_Register */ 860 861 /** 862 * @ingroup emac_registers 863 * @defgroup EMAC_SA1L EMAC_SA1L 864 * @brief Specific Address 1 Bottom. 865 * @{ 866 */ 867 #define MXC_F_EMAC_SA1L_ADDR_POS 0 /**< SA1L_ADDR Position */ 868 #define MXC_F_EMAC_SA1L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_SA1L_ADDR_POS)) /**< SA1L_ADDR Mask */ 869 870 /**@} end of group EMAC_SA1L_Register */ 871 872 /** 873 * @ingroup emac_registers 874 * @defgroup EMAC_SA1H EMAC_SA1H 875 * @brief Specific Address 1 Top. 876 * @{ 877 */ 878 #define MXC_F_EMAC_SA1H_ADDR_POS 0 /**< SA1H_ADDR Position */ 879 #define MXC_F_EMAC_SA1H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_SA1H_ADDR_POS)) /**< SA1H_ADDR Mask */ 880 881 /**@} end of group EMAC_SA1H_Register */ 882 883 /** 884 * @ingroup emac_registers 885 * @defgroup EMAC_SA2L EMAC_SA2L 886 * @brief Specific Address 2 Bottom. 887 * @{ 888 */ 889 #define MXC_F_EMAC_SA2L_ADDR_POS 0 /**< SA2L_ADDR Position */ 890 #define MXC_F_EMAC_SA2L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_SA2L_ADDR_POS)) /**< SA2L_ADDR Mask */ 891 892 /**@} end of group EMAC_SA2L_Register */ 893 894 /** 895 * @ingroup emac_registers 896 * @defgroup EMAC_SA2H EMAC_SA2H 897 * @brief Specific Address 2 Top. 898 * @{ 899 */ 900 #define MXC_F_EMAC_SA2H_ADDR_POS 0 /**< SA2H_ADDR Position */ 901 #define MXC_F_EMAC_SA2H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_SA2H_ADDR_POS)) /**< SA2H_ADDR Mask */ 902 903 /**@} end of group EMAC_SA2H_Register */ 904 905 /** 906 * @ingroup emac_registers 907 * @defgroup EMAC_SA3L EMAC_SA3L 908 * @brief Specific Address 3 Bottom. 909 * @{ 910 */ 911 #define MXC_F_EMAC_SA3L_ADDR_POS 0 /**< SA3L_ADDR Position */ 912 #define MXC_F_EMAC_SA3L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_SA3L_ADDR_POS)) /**< SA3L_ADDR Mask */ 913 914 /**@} end of group EMAC_SA3L_Register */ 915 916 /** 917 * @ingroup emac_registers 918 * @defgroup EMAC_SA3H EMAC_SA3H 919 * @brief Specific Address 3 Top. 920 * @{ 921 */ 922 #define MXC_F_EMAC_SA3H_ADDR_POS 0 /**< SA3H_ADDR Position */ 923 #define MXC_F_EMAC_SA3H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_SA3H_ADDR_POS)) /**< SA3H_ADDR Mask */ 924 925 /**@} end of group EMAC_SA3H_Register */ 926 927 /** 928 * @ingroup emac_registers 929 * @defgroup EMAC_SA4L EMAC_SA4L 930 * @brief Specific Address 4 Bottom. 931 * @{ 932 */ 933 #define MXC_F_EMAC_SA4L_ADDR_POS 0 /**< SA4L_ADDR Position */ 934 #define MXC_F_EMAC_SA4L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_SA4L_ADDR_POS)) /**< SA4L_ADDR Mask */ 935 936 /**@} end of group EMAC_SA4L_Register */ 937 938 /** 939 * @ingroup emac_registers 940 * @defgroup EMAC_SA4H EMAC_SA4H 941 * @brief Specific Address 4 Top. 942 * @{ 943 */ 944 #define MXC_F_EMAC_SA4H_ADDR_POS 0 /**< SA4H_ADDR Position */ 945 #define MXC_F_EMAC_SA4H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_SA4H_ADDR_POS)) /**< SA4H_ADDR Mask */ 946 947 /**@} end of group EMAC_SA4H_Register */ 948 949 /** 950 * @ingroup emac_registers 951 * @defgroup EMAC_TID_CK EMAC_TID_CK 952 * @brief Type ID Checking. 953 * @{ 954 */ 955 #define MXC_F_EMAC_TID_CK_TID_POS 0 /**< TID_CK_TID Position */ 956 #define MXC_F_EMAC_TID_CK_TID ((uint32_t)(0xFFFFUL << MXC_F_EMAC_TID_CK_TID_POS)) /**< TID_CK_TID Mask */ 957 958 /**@} end of group EMAC_TID_CK_Register */ 959 960 /** 961 * @ingroup emac_registers 962 * @defgroup EMAC_TPQ EMAC_TPQ 963 * @brief Transmit Pause Quantum. 964 * @{ 965 */ 966 #define MXC_F_EMAC_TPQ_TPQ_POS 0 /**< TPQ_TPQ Position */ 967 #define MXC_F_EMAC_TPQ_TPQ ((uint32_t)(0xFFFFUL << MXC_F_EMAC_TPQ_TPQ_POS)) /**< TPQ_TPQ Mask */ 968 969 /**@} end of group EMAC_TPQ_Register */ 970 971 /** 972 * @ingroup emac_registers 973 * @defgroup EMAC_REV EMAC_REV 974 * @brief Revision register. 975 * @{ 976 */ 977 #define MXC_F_EMAC_REV_REV_POS 0 /**< REV_REV Position */ 978 #define MXC_F_EMAC_REV_REV ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REV_REV_POS)) /**< REV_REV Mask */ 979 980 #define MXC_F_EMAC_REV_PART_POS 16 /**< REV_PART Position */ 981 #define MXC_F_EMAC_REV_PART ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REV_PART_POS)) /**< REV_PART Mask */ 982 983 /**@} end of group EMAC_REV_Register */ 984 985 #ifdef __cplusplus 986 } 987 #endif 988 989 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_EMAC_REGS_H_ 990
