1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _DMA_REVA_REGS_H_ 27 #define _DMA_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup dma 65 * @defgroup dma_registers DMA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 67 * @details DMA Controller Fully programmable, chaining capable DMA channels. 68 */ 69 70 /** 71 * @ingroup dma_registers 72 * Structure type to access the DMA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */ 76 __IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */ 77 __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */ 78 __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */ 79 __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */ 80 __IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */ 81 __IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */ 82 __IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */ 83 } mxc_dma_reva_ch_regs_t; 84 85 typedef struct { 86 __IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */ 87 __I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */ 88 __R uint32_t rsv_0x8_0xff[62]; 89 __IO mxc_dma_reva_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 90 } mxc_dma_reva_regs_t; 91 92 /* Register offsets for module DMA */ 93 /** 94 * @ingroup dma_registers 95 * @defgroup DMA_Register_Offsets Register Offsets 96 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 100 #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ 101 #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ 102 #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ 103 #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ 104 #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ 105 #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ 106 #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ 107 #define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 108 #define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 109 #define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 110 /**@} end of group dma_registers */ 111 112 /** 113 * @ingroup dma_registers 114 * @defgroup DMA_INTEN DMA_INTEN 115 * @brief DMA Control Register. 116 * @{ 117 */ 118 #define MXC_F_DMA_REVA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ 119 #define MXC_F_DMA_REVA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ 120 121 #define MXC_F_DMA_REVA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ 122 #define MXC_F_DMA_REVA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ 123 124 #define MXC_F_DMA_REVA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ 125 #define MXC_F_DMA_REVA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ 126 127 #define MXC_F_DMA_REVA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ 128 #define MXC_F_DMA_REVA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ 129 130 #define MXC_F_DMA_REVA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ 131 #define MXC_F_DMA_REVA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ 132 133 #define MXC_F_DMA_REVA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ 134 #define MXC_F_DMA_REVA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ 135 136 #define MXC_F_DMA_REVA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ 137 #define MXC_F_DMA_REVA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ 138 139 #define MXC_F_DMA_REVA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ 140 #define MXC_F_DMA_REVA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ 141 142 #define MXC_F_DMA_REVA_INTEN_CH8_POS 8 /**< INTEN_CH8 Position */ 143 #define MXC_F_DMA_REVA_INTEN_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */ 144 145 #define MXC_F_DMA_REVA_INTEN_CH9_POS 9 /**< INTEN_CH9 Position */ 146 #define MXC_F_DMA_REVA_INTEN_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */ 147 148 #define MXC_F_DMA_REVA_INTEN_CH10_POS 10 /**< INTEN_CH10 Position */ 149 #define MXC_F_DMA_REVA_INTEN_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */ 150 151 #define MXC_F_DMA_REVA_INTEN_CH11_POS 11 /**< INTEN_CH11 Position */ 152 #define MXC_F_DMA_REVA_INTEN_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */ 153 154 #define MXC_F_DMA_REVA_INTEN_CH12_POS 12 /**< INTEN_CH12 Position */ 155 #define MXC_F_DMA_REVA_INTEN_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */ 156 157 #define MXC_F_DMA_REVA_INTEN_CH13_POS 13 /**< INTEN_CH13 Position */ 158 #define MXC_F_DMA_REVA_INTEN_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */ 159 160 #define MXC_F_DMA_REVA_INTEN_CH14_POS 14 /**< INTEN_CH14 Position */ 161 #define MXC_F_DMA_REVA_INTEN_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */ 162 163 #define MXC_F_DMA_REVA_INTEN_CH15_POS 15 /**< INTEN_CH15 Position */ 164 #define MXC_F_DMA_REVA_INTEN_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */ 165 166 /**@} end of group DMA_INTEN_Register */ 167 168 /** 169 * @ingroup dma_registers 170 * @defgroup DMA_INTFL DMA_INTFL 171 * @brief DMA Interrupt Register. 172 * @{ 173 */ 174 #define MXC_F_DMA_REVA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ 175 #define MXC_F_DMA_REVA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ 176 177 #define MXC_F_DMA_REVA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ 178 #define MXC_F_DMA_REVA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ 179 180 #define MXC_F_DMA_REVA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ 181 #define MXC_F_DMA_REVA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ 182 183 #define MXC_F_DMA_REVA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ 184 #define MXC_F_DMA_REVA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ 185 186 #define MXC_F_DMA_REVA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ 187 #define MXC_F_DMA_REVA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ 188 189 #define MXC_F_DMA_REVA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ 190 #define MXC_F_DMA_REVA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ 191 192 #define MXC_F_DMA_REVA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ 193 #define MXC_F_DMA_REVA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ 194 195 #define MXC_F_DMA_REVA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ 196 #define MXC_F_DMA_REVA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ 197 198 #define MXC_F_DMA_REVA_INTFL_CH8_POS 8 /**< INTFL_CH8 Position */ 199 #define MXC_F_DMA_REVA_INTFL_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */ 200 201 #define MXC_F_DMA_REVA_INTFL_CH9_POS 9 /**< INTFL_CH9 Position */ 202 #define MXC_F_DMA_REVA_INTFL_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */ 203 204 #define MXC_F_DMA_REVA_INTFL_CH10_POS 10 /**< INTFL_CH10 Position */ 205 #define MXC_F_DMA_REVA_INTFL_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */ 206 207 #define MXC_F_DMA_REVA_INTFL_CH11_POS 11 /**< INTFL_CH11 Position */ 208 #define MXC_F_DMA_REVA_INTFL_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */ 209 210 #define MXC_F_DMA_REVA_INTFL_CH12_POS 12 /**< INTFL_CH12 Position */ 211 #define MXC_F_DMA_REVA_INTFL_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */ 212 213 #define MXC_F_DMA_REVA_INTFL_CH13_POS 13 /**< INTFL_CH13 Position */ 214 #define MXC_F_DMA_REVA_INTFL_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */ 215 216 #define MXC_F_DMA_REVA_INTFL_CH14_POS 14 /**< INTFL_CH14 Position */ 217 #define MXC_F_DMA_REVA_INTFL_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */ 218 219 #define MXC_F_DMA_REVA_INTFL_CH15_POS 15 /**< INTFL_CH15 Position */ 220 #define MXC_F_DMA_REVA_INTFL_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */ 221 222 /**@} end of group DMA_INTFL_Register */ 223 224 /** 225 * @ingroup dma_registers 226 * @defgroup DMA_CTRL DMA_CTRL 227 * @brief DMA Channel Control Register. 228 * @{ 229 */ 230 #define MXC_F_DMA_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 231 #define MXC_F_DMA_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 232 233 #define MXC_F_DMA_REVA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ 234 #define MXC_F_DMA_REVA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ 235 236 #define MXC_F_DMA_REVA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ 237 #define MXC_F_DMA_REVA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ 238 #define MXC_V_DMA_REVA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ 239 #define MXC_S_DMA_REVA_CTRL_PRI_HIGH (MXC_V_DMA_REVA_CTRL_PRI_HIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ 240 #define MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ 241 #define MXC_S_DMA_REVA_CTRL_PRI_MEDHIGH (MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ 242 #define MXC_V_DMA_REVA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ 243 #define MXC_S_DMA_REVA_CTRL_PRI_MEDLOW (MXC_V_DMA_REVA_CTRL_PRI_MEDLOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ 244 #define MXC_V_DMA_REVA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ 245 #define MXC_S_DMA_REVA_CTRL_PRI_LOW (MXC_V_DMA_REVA_CTRL_PRI_LOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ 246 247 #define MXC_F_DMA_REVA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ 248 #define MXC_F_DMA_REVA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_REVA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ 249 #define MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ 250 #define MXC_S_DMA_REVA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ 251 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ 252 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ 253 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ 254 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ 255 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ 256 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ 257 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ 258 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ 259 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ 260 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ 261 #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ 262 #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ 263 #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ 264 #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ 265 #define MXC_V_DMA_REVA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ 266 #define MXC_S_DMA_REVA_CTRL_REQUEST_ADC (MXC_V_DMA_REVA_CTRL_REQUEST_ADC << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ 267 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ 268 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ 269 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ 270 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ 271 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX ((uint32_t)0x10UL) /**< CTRL_REQUEST_SPI_MSS0RX Value */ 272 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0RX Setting */ 273 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */ 274 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */ 275 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */ 276 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */ 277 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */ 278 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */ 279 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */ 280 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */ 281 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */ 282 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */ 283 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */ 284 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */ 285 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */ 286 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */ 287 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */ 288 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */ 289 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */ 290 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */ 291 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */ 292 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */ 293 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */ 294 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */ 295 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ 296 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ 297 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ 298 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ 299 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ 300 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ 301 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ 302 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ 303 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ 304 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ 305 #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ 306 #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ 307 #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ 308 #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ 309 #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ 310 #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ 311 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ 312 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ 313 #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX ((uint32_t)0x30UL) /**< CTRL_REQUEST_SPI_MSS0TX Value */ 314 #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0TX Setting */ 315 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */ 316 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */ 317 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */ 318 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */ 319 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */ 320 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */ 321 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */ 322 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */ 323 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */ 324 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */ 325 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */ 326 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */ 327 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */ 328 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */ 329 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */ 330 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */ 331 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */ 332 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */ 333 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */ 334 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */ 335 #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */ 336 #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */ 337 338 #define MXC_F_DMA_REVA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ 339 #define MXC_F_DMA_REVA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ 340 341 #define MXC_F_DMA_REVA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ 342 #define MXC_F_DMA_REVA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_REVA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ 343 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ 344 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO4 (MXC_V_DMA_REVA_CTRL_TO_PER_TO4 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ 345 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ 346 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO8 (MXC_V_DMA_REVA_CTRL_TO_PER_TO8 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ 347 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ 348 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO16 (MXC_V_DMA_REVA_CTRL_TO_PER_TO16 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ 349 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ 350 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO32 (MXC_V_DMA_REVA_CTRL_TO_PER_TO32 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ 351 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ 352 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO64 (MXC_V_DMA_REVA_CTRL_TO_PER_TO64 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ 353 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ 354 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO128 (MXC_V_DMA_REVA_CTRL_TO_PER_TO128 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ 355 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ 356 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO256 (MXC_V_DMA_REVA_CTRL_TO_PER_TO256 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ 357 #define MXC_V_DMA_REVA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ 358 #define MXC_S_DMA_REVA_CTRL_TO_PER_TO512 (MXC_V_DMA_REVA_CTRL_TO_PER_TO512 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ 359 360 #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ 361 #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ 362 #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ 363 #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ 364 #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ 365 #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ 366 #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ 367 #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ 368 #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ 369 #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ 370 371 #define MXC_F_DMA_REVA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ 372 #define MXC_F_DMA_REVA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ 373 #define MXC_V_DMA_REVA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ 374 #define MXC_S_DMA_REVA_CTRL_SRCWD_BYTE (MXC_V_DMA_REVA_CTRL_SRCWD_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ 375 #define MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ 376 #define MXC_S_DMA_REVA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ 377 #define MXC_V_DMA_REVA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ 378 #define MXC_S_DMA_REVA_CTRL_SRCWD_WORD (MXC_V_DMA_REVA_CTRL_SRCWD_WORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ 379 380 #define MXC_F_DMA_REVA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ 381 #define MXC_F_DMA_REVA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ 382 383 #define MXC_F_DMA_REVA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ 384 #define MXC_F_DMA_REVA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ 385 #define MXC_V_DMA_REVA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ 386 #define MXC_S_DMA_REVA_CTRL_DSTWD_BYTE (MXC_V_DMA_REVA_CTRL_DSTWD_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ 387 #define MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ 388 #define MXC_S_DMA_REVA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ 389 #define MXC_V_DMA_REVA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ 390 #define MXC_S_DMA_REVA_CTRL_DSTWD_WORD (MXC_V_DMA_REVA_CTRL_DSTWD_WORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ 391 392 #define MXC_F_DMA_REVA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ 393 #define MXC_F_DMA_REVA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ 394 395 #define MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ 396 #define MXC_F_DMA_REVA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ 397 398 #define MXC_F_DMA_REVA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ 399 #define MXC_F_DMA_REVA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ 400 401 #define MXC_F_DMA_REVA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ 402 #define MXC_F_DMA_REVA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ 403 404 /**@} end of group DMA_CTRL_Register */ 405 406 /** 407 * @ingroup dma_registers 408 * @defgroup DMA_STATUS DMA_STATUS 409 * @brief DMA Channel Status Register. 410 * @{ 411 */ 412 #define MXC_F_DMA_REVA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ 413 #define MXC_F_DMA_REVA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ 414 415 #define MXC_F_DMA_REVA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ 416 #define MXC_F_DMA_REVA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ 417 418 #define MXC_F_DMA_REVA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ 419 #define MXC_F_DMA_REVA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ 420 421 #define MXC_F_DMA_REVA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ 422 #define MXC_F_DMA_REVA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ 423 424 #define MXC_F_DMA_REVA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ 425 #define MXC_F_DMA_REVA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ 426 427 #define MXC_F_DMA_REVA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ 428 #define MXC_F_DMA_REVA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ 429 430 /**@} end of group DMA_STATUS_Register */ 431 432 /** 433 * @ingroup dma_registers 434 * @defgroup DMA_SRC DMA_SRC 435 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 436 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 437 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 438 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 439 * register is reloaded with the contents of DMA_SRC_RLD. 440 * @{ 441 */ 442 #define MXC_F_DMA_REVA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 443 #define MXC_F_DMA_REVA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 444 445 /**@} end of group DMA_SRC_Register */ 446 447 /** 448 * @ingroup dma_registers 449 * @defgroup DMA_DST DMA_DST 450 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 451 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 452 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 453 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 454 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 455 * @{ 456 */ 457 #define MXC_F_DMA_REVA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 458 #define MXC_F_DMA_REVA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 459 460 /**@} end of group DMA_DST_Register */ 461 462 /** 463 * @ingroup dma_registers 464 * @defgroup DMA_CNT DMA_CNT 465 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 466 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 467 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 468 * reaches 0, a count-to-zero condition is triggered. 469 * @{ 470 */ 471 #define MXC_F_DMA_REVA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 472 #define MXC_F_DMA_REVA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 473 474 /**@} end of group DMA_CNT_Register */ 475 476 /** 477 * @ingroup dma_registers 478 * @defgroup DMA_SRCRLD DMA_SRCRLD 479 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 480 * upon a count-to-zero condition. 481 * @{ 482 */ 483 #define MXC_F_DMA_REVA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ 484 #define MXC_F_DMA_REVA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ 485 486 /**@} end of group DMA_SRCRLD_Register */ 487 488 /** 489 * @ingroup dma_registers 490 * @defgroup DMA_DSTRLD DMA_DSTRLD 491 * @brief Destination Address Reload Value. The value of this register is loaded into 492 * DMA0_DST upon a count-to-zero condition. 493 * @{ 494 */ 495 #define MXC_F_DMA_REVA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ 496 #define MXC_F_DMA_REVA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ 497 498 /**@} end of group DMA_DSTRLD_Register */ 499 500 /** 501 * @ingroup dma_registers 502 * @defgroup DMA_CNTRLD DMA_CNTRLD 503 * @brief DMA Channel Count Reload Register. 504 * @{ 505 */ 506 #define MXC_F_DMA_REVA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ 507 #define MXC_F_DMA_REVA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ 508 509 #define MXC_F_DMA_REVA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ 510 #define MXC_F_DMA_REVA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ 511 512 /**@} end of group DMA_CNTRLD_Register */ 513 514 #ifdef __cplusplus 515 } 516 #endif 517 518 #endif /* _DMA_REVA_REGS_H_ */ 519
