1 /** 2 * @file can_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CAN_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _CAN_REVA_REGS_H_ 27 #define _CAN_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup can_reva 65 * @defgroup can_reva_registers CAN_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the CAN REVA Peripheral Module. 67 * @details Controller Area Network Registers 68 */ 69 70 /** 71 * @ingroup can_reva_registers 72 * Structure type to access the CAN_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint8_t mode; /**< <tt>\b 0x0000:</tt> CAN REVA MODE Register */ 76 __IO uint8_t cmd; /**< <tt>\b 0x0001:</tt> CAN REVA CMD Register */ 77 __I uint8_t stat; /**< <tt>\b 0x0002:</tt> CAN REVA STAT Register */ 78 __IO uint8_t intfl; /**< <tt>\b 0x0003:</tt> CAN REVA INTFL Register */ 79 __IO uint8_t inten; /**< <tt>\b 0x0004:</tt> CAN REVA INTEN Register */ 80 __IO uint8_t rmc; /**< <tt>\b 0x0005:</tt> CAN REVA RMC Register */ 81 __IO uint8_t bustim0; /**< <tt>\b 0x0006:</tt> CAN REVA BUSTIM0 Register */ 82 __IO uint8_t bustim1; /**< <tt>\b 0x0007:</tt> CAN REVA BUSTIM1 Register */ 83 union{ 84 __IO uint32_t txfifo32; /**< <tt>\b 0x0008:</tt> CAN REVA TXFIFO32 Register */ 85 __IO uint16_t txfifo16[2]; /**< <tt>\b 0x0008:</tt> CAN REVA TXFIFO16 Register */ 86 __IO uint8_t txfifo8[4]; /**< <tt>\b 0x0008:</tt> CAN REVA TXFIFO8 Register */ 87 }; 88 union{ 89 __I uint32_t rxfifo32; /**< <tt>\b 0x000C:</tt> CAN REVA RXFIFO32 Register */ 90 __I uint16_t rxfifo16[2]; /**< <tt>\b 0x000C:</tt> CAN REVA RXFIFO16 Register */ 91 __I uint8_t rxfifo8[4]; /**< <tt>\b 0x000C:</tt> CAN REVA RXFIFO8 Register */ 92 }; 93 union{ 94 __IO uint32_t acr32; /**< <tt>\b 0x0010:</tt> CAN REVA ACR32 Register */ 95 __IO uint16_t acr16[2]; /**< <tt>\b 0x0010:</tt> CAN REVA ACR16 Register */ 96 __IO uint8_t acr8[4]; /**< <tt>\b 0x0010:</tt> CAN REVA ACR8 Register */ 97 }; 98 union{ 99 __IO uint32_t amr32; /**< <tt>\b 0x0014:</tt> CAN REVA AMR32 Register */ 100 __IO uint16_t amr16[2]; /**< <tt>\b 0x0014:</tt> CAN REVA AMR16 Register */ 101 __IO uint8_t amr8[4]; /**< <tt>\b 0x0014:</tt> CAN REVA AMR8 Register */ 102 }; 103 __I uint8_t ecc; /**< <tt>\b 0x0018:</tt> CAN REVA ECC Register */ 104 __IO uint8_t rxerr; /**< <tt>\b 0x0019:</tt> CAN REVA RXERR Register */ 105 __IO uint8_t txerr; /**< <tt>\b 0x001A:</tt> CAN REVA TXERR Register */ 106 __I uint8_t alc; /**< <tt>\b 0x001B:</tt> CAN REVA ALC Register */ 107 __IO uint32_t nbt; /**< <tt>\b 0x001C:</tt> CAN REVA NBT Register */ 108 __IO uint32_t dbt_sspp; /**< <tt>\b 0x0020:</tt> CAN REVA DBT_SSPP Register */ 109 __IO uint8_t fdctrl; /**< <tt>\b 0x0024:</tt> CAN REVA FDCTRL Register */ 110 __I uint8_t fdstat; /**< <tt>\b 0x0025:</tt> CAN REVA FDSTAT Register */ 111 __I uint8_t dperr; /**< <tt>\b 0x0026:</tt> CAN REVA DPERR Register */ 112 __I uint8_t aperr; /**< <tt>\b 0x0027:</tt> CAN REVA APERR Register */ 113 __IO uint8_t test; /**< <tt>\b 0x0028:</tt> CAN REVA TEST Register */ 114 __IO uint8_t wupclkdiv; /**< <tt>\b 0x0029:</tt> CAN REVA WUPCLKDIV Register */ 115 __IO uint16_t wupft; /**< <tt>\b 0x002A:</tt> CAN REVA WUPFT Register */ 116 __IO uint32_t wupet; /**< <tt>\b 0x002C:</tt> CAN REVA WUPET Register */ 117 __IO uint16_t rxdcnt; /**< <tt>\b 0x0030:</tt> CAN REVA RXDCNT Register */ 118 __IO uint8_t txscnt; /**< <tt>\b 0x0032:</tt> CAN REVA TXSCNT Register */ 119 __IO uint8_t txdecmp; /**< <tt>\b 0x0033:</tt> CAN REVA TXDECMP Register */ 120 __IO uint8_t eintfl; /**< <tt>\b 0x0034:</tt> CAN REVA EINTFL Register */ 121 __IO uint8_t einten; /**< <tt>\b 0x0035:</tt> CAN REVA EINTEN Register */ 122 __IO uint16_t rxto; /**< <tt>\b 0x0036:</tt> CAN REVA RXTO Register */ 123 } mxc_can_reva_regs_t; 124 125 /* Register offsets for module CAN REVA */ 126 /** 127 * @ingroup can_reva_registers 128 * @defgroup CAN_REVA_Register_Offsets Register Offsets 129 * @brief CAN REVA Peripheral Register Offsets from the CAN REVA Base Peripheral Address. 130 * @{ 131 */ 132 #define MXC_R_CAN_REVA_MODE ((uint32_t)0x00000000UL) /**< Offset from CAN REVA Base Address: <tt> 0x0000</tt> */ 133 #define MXC_R_CAN_REVA_CMD ((uint32_t)0x00000001UL) /**< Offset from CAN REVA Base Address: <tt> 0x0001</tt> */ 134 #define MXC_R_CAN_REVA_STAT ((uint32_t)0x00000002UL) /**< Offset from CAN REVA Base Address: <tt> 0x0002</tt> */ 135 #define MXC_R_CAN_REVA_INTFL ((uint32_t)0x00000003UL) /**< Offset from CAN REVA Base Address: <tt> 0x0003</tt> */ 136 #define MXC_R_CAN_REVA_INTEN ((uint32_t)0x00000004UL) /**< Offset from CAN REVA Base Address: <tt> 0x0004</tt> */ 137 #define MXC_R_CAN_REVA_RMC ((uint32_t)0x00000005UL) /**< Offset from CAN REVA Base Address: <tt> 0x0005</tt> */ 138 #define MXC_R_CAN_REVA_BUSTIM0 ((uint32_t)0x00000006UL) /**< Offset from CAN REVA Base Address: <tt> 0x0006</tt> */ 139 #define MXC_R_CAN_REVA_BUSTIM1 ((uint32_t)0x00000007UL) /**< Offset from CAN REVA Base Address: <tt> 0x0007</tt> */ 140 #define MXC_R_CAN_REVA_TXFIFO32 ((uint32_t)0x00000008UL) /**< Offset from CAN REVA Base Address: <tt> 0x0008</tt> */ 141 #define MXC_R_CAN_REVA_TXFIFO16 ((uint32_t)0x00000008UL) /**< Offset from CAN REVA Base Address: <tt> 0x0008</tt> */ 142 #define MXC_R_CAN_REVA_TXFIFO8 ((uint32_t)0x00000008UL) /**< Offset from CAN REVA Base Address: <tt> 0x0008</tt> */ 143 #define MXC_R_CAN_REVA_RXFIFO32 ((uint32_t)0x0000000CUL) /**< Offset from CAN REVA Base Address: <tt> 0x000C</tt> */ 144 #define MXC_R_CAN_REVA_RXFIFO16 ((uint32_t)0x0000000CUL) /**< Offset from CAN REVA Base Address: <tt> 0x000C</tt> */ 145 #define MXC_R_CAN_REVA_RXFIFO8 ((uint32_t)0x0000000CUL) /**< Offset from CAN REVA Base Address: <tt> 0x000C</tt> */ 146 #define MXC_R_CAN_REVA_ACR32 ((uint32_t)0x00000010UL) /**< Offset from CAN REVA Base Address: <tt> 0x0010</tt> */ 147 #define MXC_R_CAN_REVA_ACR16 ((uint32_t)0x00000010UL) /**< Offset from CAN REVA Base Address: <tt> 0x0010</tt> */ 148 #define MXC_R_CAN_REVA_ACR8 ((uint32_t)0x00000010UL) /**< Offset from CAN REVA Base Address: <tt> 0x0010</tt> */ 149 #define MXC_R_CAN_REVA_AMR32 ((uint32_t)0x00000014UL) /**< Offset from CAN REVA Base Address: <tt> 0x0014</tt> */ 150 #define MXC_R_CAN_REVA_AMR16 ((uint32_t)0x00000014UL) /**< Offset from CAN REVA Base Address: <tt> 0x0014</tt> */ 151 #define MXC_R_CAN_REVA_AMR8 ((uint32_t)0x00000014UL) /**< Offset from CAN REVA Base Address: <tt> 0x0014</tt> */ 152 #define MXC_R_CAN_REVA_ECC ((uint32_t)0x00000018UL) /**< Offset from CAN REVA Base Address: <tt> 0x0018</tt> */ 153 #define MXC_R_CAN_REVA_RXERR ((uint32_t)0x00000019UL) /**< Offset from CAN REVA Base Address: <tt> 0x0019</tt> */ 154 #define MXC_R_CAN_REVA_TXERR ((uint32_t)0x0000001AUL) /**< Offset from CAN REVA Base Address: <tt> 0x001A</tt> */ 155 #define MXC_R_CAN_REVA_ALC ((uint32_t)0x0000001BUL) /**< Offset from CAN REVA Base Address: <tt> 0x001B</tt> */ 156 #define MXC_R_CAN_REVA_NBT ((uint32_t)0x0000001CUL) /**< Offset from CAN REVA Base Address: <tt> 0x001C</tt> */ 157 #define MXC_R_CAN_REVA_DBT_SSPP ((uint32_t)0x00000020UL) /**< Offset from CAN REVA Base Address: <tt> 0x0020</tt> */ 158 #define MXC_R_CAN_REVA_FDCTRL ((uint32_t)0x00000024UL) /**< Offset from CAN REVA Base Address: <tt> 0x0024</tt> */ 159 #define MXC_R_CAN_REVA_FDSTAT ((uint32_t)0x00000025UL) /**< Offset from CAN REVA Base Address: <tt> 0x0025</tt> */ 160 #define MXC_R_CAN_REVA_DPERR ((uint32_t)0x00000026UL) /**< Offset from CAN REVA Base Address: <tt> 0x0026</tt> */ 161 #define MXC_R_CAN_REVA_APERR ((uint32_t)0x00000027UL) /**< Offset from CAN REVA Base Address: <tt> 0x0027</tt> */ 162 #define MXC_R_CAN_REVA_TEST ((uint32_t)0x00000028UL) /**< Offset from CAN REVA Base Address: <tt> 0x0028</tt> */ 163 #define MXC_R_CAN_REVA_WUPCLKDIV ((uint32_t)0x00000029UL) /**< Offset from CAN REVA Base Address: <tt> 0x0029</tt> */ 164 #define MXC_R_CAN_REVA_WUPFT ((uint32_t)0x0000002AUL) /**< Offset from CAN REVA Base Address: <tt> 0x002A</tt> */ 165 #define MXC_R_CAN_REVA_WUPET ((uint32_t)0x0000002CUL) /**< Offset from CAN REVA Base Address: <tt> 0x002C</tt> */ 166 #define MXC_R_CAN_REVA_RXDCNT ((uint32_t)0x00000030UL) /**< Offset from CAN REVA Base Address: <tt> 0x0030</tt> */ 167 #define MXC_R_CAN_REVA_TXSCNT ((uint32_t)0x00000032UL) /**< Offset from CAN REVA Base Address: <tt> 0x0032</tt> */ 168 #define MXC_R_CAN_REVA_TXDECMP ((uint32_t)0x00000033UL) /**< Offset from CAN REVA Base Address: <tt> 0x0033</tt> */ 169 #define MXC_R_CAN_REVA_EINTFL ((uint32_t)0x00000034UL) /**< Offset from CAN REVA Base Address: <tt> 0x0034</tt> */ 170 #define MXC_R_CAN_REVA_EINTEN ((uint32_t)0x00000035UL) /**< Offset from CAN REVA Base Address: <tt> 0x0035</tt> */ 171 #define MXC_R_CAN_REVA_RXTO ((uint32_t)0x00000036UL) /**< Offset from CAN REVA Base Address: <tt> 0x0036</tt> */ 172 /**@} end of group can_reva_registers */ 173 174 /** 175 * @ingroup can_reva_registers 176 * @defgroup CAN_REVA_MODE CAN_REVA_MODE 177 * @brief Mode Register. 178 * @{ 179 */ 180 #define MXC_F_CAN_REVA_MODE_AFM_POS 0 /**< MODE_AFM Position */ 181 #define MXC_F_CAN_REVA_MODE_AFM ((uint8_t)(0x1UL << MXC_F_CAN_REVA_MODE_AFM_POS)) /**< MODE_AFM Mask */ 182 183 #define MXC_F_CAN_REVA_MODE_LOM_POS 1 /**< MODE_LOM Position */ 184 #define MXC_F_CAN_REVA_MODE_LOM ((uint8_t)(0x1UL << MXC_F_CAN_REVA_MODE_LOM_POS)) /**< MODE_LOM Mask */ 185 186 #define MXC_F_CAN_REVA_MODE_RST_POS 2 /**< MODE_RST Position */ 187 #define MXC_F_CAN_REVA_MODE_RST ((uint8_t)(0x1UL << MXC_F_CAN_REVA_MODE_RST_POS)) /**< MODE_RST Mask */ 188 189 #define MXC_F_CAN_REVA_MODE_RXTRIG_POS 3 /**< MODE_RXTRIG Position */ 190 #define MXC_F_CAN_REVA_MODE_RXTRIG ((uint8_t)(0x7UL << MXC_F_CAN_REVA_MODE_RXTRIG_POS)) /**< MODE_RXTRIG Mask */ 191 #define MXC_V_CAN_REVA_MODE_RXTRIG_1W ((uint8_t)0x0UL) /**< MODE_RXTRIG_1W Value */ 192 #define MXC_S_CAN_REVA_MODE_RXTRIG_1W (MXC_V_CAN_REVA_MODE_RXTRIG_1W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_1W Setting */ 193 #define MXC_V_CAN_REVA_MODE_RXTRIG_4W ((uint8_t)0x1UL) /**< MODE_RXTRIG_4W Value */ 194 #define MXC_S_CAN_REVA_MODE_RXTRIG_4W (MXC_V_CAN_REVA_MODE_RXTRIG_4W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_4W Setting */ 195 #define MXC_V_CAN_REVA_MODE_RXTRIG_8W ((uint8_t)0x2UL) /**< MODE_RXTRIG_8W Value */ 196 #define MXC_S_CAN_REVA_MODE_RXTRIG_8W (MXC_V_CAN_REVA_MODE_RXTRIG_8W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_8W Setting */ 197 #define MXC_V_CAN_REVA_MODE_RXTRIG_16W ((uint8_t)0x3UL) /**< MODE_RXTRIG_16W Value */ 198 #define MXC_S_CAN_REVA_MODE_RXTRIG_16W (MXC_V_CAN_REVA_MODE_RXTRIG_16W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_16W Setting */ 199 #define MXC_V_CAN_REVA_MODE_RXTRIG_32W ((uint8_t)0x4UL) /**< MODE_RXTRIG_32W Value */ 200 #define MXC_S_CAN_REVA_MODE_RXTRIG_32W (MXC_V_CAN_REVA_MODE_RXTRIG_32W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_32W Setting */ 201 #define MXC_V_CAN_REVA_MODE_RXTRIG_64W ((uint8_t)0x5UL) /**< MODE_RXTRIG_64W Value */ 202 #define MXC_S_CAN_REVA_MODE_RXTRIG_64W (MXC_V_CAN_REVA_MODE_RXTRIG_64W << MXC_F_CAN_REVA_MODE_RXTRIG_POS) /**< MODE_RXTRIG_64W Setting */ 203 204 #define MXC_F_CAN_REVA_MODE_DMA_POS 6 /**< MODE_DMA Position */ 205 #define MXC_F_CAN_REVA_MODE_DMA ((uint8_t)(0x1UL << MXC_F_CAN_REVA_MODE_DMA_POS)) /**< MODE_DMA Mask */ 206 207 #define MXC_F_CAN_REVA_MODE_SLP_POS 7 /**< MODE_SLP Position */ 208 #define MXC_F_CAN_REVA_MODE_SLP ((uint8_t)(0x1UL << MXC_F_CAN_REVA_MODE_SLP_POS)) /**< MODE_SLP Mask */ 209 210 /**@} end of group CAN_REVA_MODE_Register */ 211 212 /** 213 * @ingroup can_reva_registers 214 * @defgroup CAN_REVA_CMD CAN_REVA_CMD 215 * @brief Command Register. 216 * @{ 217 */ 218 #define MXC_F_CAN_REVA_CMD_ABORT_POS 1 /**< CMD_ABORT Position */ 219 #define MXC_F_CAN_REVA_CMD_ABORT ((uint8_t)(0x1UL << MXC_F_CAN_REVA_CMD_ABORT_POS)) /**< CMD_ABORT Mask */ 220 221 #define MXC_F_CAN_REVA_CMD_TXREQ_POS 2 /**< CMD_TXREQ Position */ 222 #define MXC_F_CAN_REVA_CMD_TXREQ ((uint8_t)(0x1UL << MXC_F_CAN_REVA_CMD_TXREQ_POS)) /**< CMD_TXREQ Mask */ 223 224 /**@} end of group CAN_REVA_CMD_Register */ 225 226 /** 227 * @ingroup can_reva_registers 228 * @defgroup CAN_REVA_STAT CAN_REVA_STAT 229 * @brief Status Register. 230 * @{ 231 */ 232 #define MXC_F_CAN_REVA_STAT_BUS_OFF_POS 0 /**< STAT_BUS_OFF Position */ 233 #define MXC_F_CAN_REVA_STAT_BUS_OFF ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_BUS_OFF_POS)) /**< STAT_BUS_OFF Mask */ 234 235 #define MXC_F_CAN_REVA_STAT_ERR_POS 1 /**< STAT_ERR Position */ 236 #define MXC_F_CAN_REVA_STAT_ERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_ERR_POS)) /**< STAT_ERR Mask */ 237 238 #define MXC_F_CAN_REVA_STAT_TX_POS 2 /**< STAT_TX Position */ 239 #define MXC_F_CAN_REVA_STAT_TX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_TX_POS)) /**< STAT_TX Mask */ 240 241 #define MXC_F_CAN_REVA_STAT_RX_POS 3 /**< STAT_RX Position */ 242 #define MXC_F_CAN_REVA_STAT_RX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_RX_POS)) /**< STAT_RX Mask */ 243 244 #define MXC_F_CAN_REVA_STAT_TXBUF_POS 5 /**< STAT_TXBUF Position */ 245 #define MXC_F_CAN_REVA_STAT_TXBUF ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_TXBUF_POS)) /**< STAT_TXBUF Mask */ 246 247 #define MXC_F_CAN_REVA_STAT_DOR_POS 6 /**< STAT_DOR Position */ 248 #define MXC_F_CAN_REVA_STAT_DOR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_DOR_POS)) /**< STAT_DOR Mask */ 249 250 #define MXC_F_CAN_REVA_STAT_RXBUF_POS 7 /**< STAT_RXBUF Position */ 251 #define MXC_F_CAN_REVA_STAT_RXBUF ((uint8_t)(0x1UL << MXC_F_CAN_REVA_STAT_RXBUF_POS)) /**< STAT_RXBUF Mask */ 252 253 /**@} end of group CAN_REVA_STAT_Register */ 254 255 /** 256 * @ingroup can_reva_registers 257 * @defgroup CAN_REVA_INTFL CAN_REVA_INTFL 258 * @brief Interrupt Status Register. 259 * @{ 260 */ 261 #define MXC_F_CAN_REVA_INTFL_DOR_POS 0 /**< INTFL_DOR Position */ 262 #define MXC_F_CAN_REVA_INTFL_DOR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_DOR_POS)) /**< INTFL_DOR Mask */ 263 264 #define MXC_F_CAN_REVA_INTFL_BERR_POS 1 /**< INTFL_BERR Position */ 265 #define MXC_F_CAN_REVA_INTFL_BERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_BERR_POS)) /**< INTFL_BERR Mask */ 266 267 #define MXC_F_CAN_REVA_INTFL_TX_POS 2 /**< INTFL_TX Position */ 268 #define MXC_F_CAN_REVA_INTFL_TX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_TX_POS)) /**< INTFL_TX Mask */ 269 270 #define MXC_F_CAN_REVA_INTFL_RX_POS 3 /**< INTFL_RX Position */ 271 #define MXC_F_CAN_REVA_INTFL_RX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_RX_POS)) /**< INTFL_RX Mask */ 272 273 #define MXC_F_CAN_REVA_INTFL_ERPSV_POS 4 /**< INTFL_ERPSV Position */ 274 #define MXC_F_CAN_REVA_INTFL_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_ERPSV_POS)) /**< INTFL_ERPSV Mask */ 275 276 #define MXC_F_CAN_REVA_INTFL_ERWARN_POS 5 /**< INTFL_ERWARN Position */ 277 #define MXC_F_CAN_REVA_INTFL_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_ERWARN_POS)) /**< INTFL_ERWARN Mask */ 278 279 #define MXC_F_CAN_REVA_INTFL_AL_POS 6 /**< INTFL_AL Position */ 280 #define MXC_F_CAN_REVA_INTFL_AL ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_AL_POS)) /**< INTFL_AL Mask */ 281 282 #define MXC_F_CAN_REVA_INTFL_WU_POS 7 /**< INTFL_WU Position */ 283 #define MXC_F_CAN_REVA_INTFL_WU ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTFL_WU_POS)) /**< INTFL_WU Mask */ 284 285 /**@} end of group CAN_REVA_INTFL_Register */ 286 287 /** 288 * @ingroup can_reva_registers 289 * @defgroup CAN_REVA_INTEN CAN_REVA_INTEN 290 * @brief Interrupt Enable Register. 291 * @{ 292 */ 293 #define MXC_F_CAN_REVA_INTEN_DOR_POS 0 /**< INTEN_DOR Position */ 294 #define MXC_F_CAN_REVA_INTEN_DOR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_DOR_POS)) /**< INTEN_DOR Mask */ 295 296 #define MXC_F_CAN_REVA_INTEN_BERR_POS 1 /**< INTEN_BERR Position */ 297 #define MXC_F_CAN_REVA_INTEN_BERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_BERR_POS)) /**< INTEN_BERR Mask */ 298 299 #define MXC_F_CAN_REVA_INTEN_TX_POS 2 /**< INTEN_TX Position */ 300 #define MXC_F_CAN_REVA_INTEN_TX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_TX_POS)) /**< INTEN_TX Mask */ 301 302 #define MXC_F_CAN_REVA_INTEN_RX_POS 3 /**< INTEN_RX Position */ 303 #define MXC_F_CAN_REVA_INTEN_RX ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_RX_POS)) /**< INTEN_RX Mask */ 304 305 #define MXC_F_CAN_REVA_INTEN_ERPSV_POS 4 /**< INTEN_ERPSV Position */ 306 #define MXC_F_CAN_REVA_INTEN_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_ERPSV_POS)) /**< INTEN_ERPSV Mask */ 307 308 #define MXC_F_CAN_REVA_INTEN_ERWARN_POS 5 /**< INTEN_ERWARN Position */ 309 #define MXC_F_CAN_REVA_INTEN_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_ERWARN_POS)) /**< INTEN_ERWARN Mask */ 310 311 #define MXC_F_CAN_REVA_INTEN_AL_POS 6 /**< INTEN_AL Position */ 312 #define MXC_F_CAN_REVA_INTEN_AL ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_AL_POS)) /**< INTEN_AL Mask */ 313 314 #define MXC_F_CAN_REVA_INTEN_WU_POS 7 /**< INTEN_WU Position */ 315 #define MXC_F_CAN_REVA_INTEN_WU ((uint8_t)(0x1UL << MXC_F_CAN_REVA_INTEN_WU_POS)) /**< INTEN_WU Mask */ 316 317 /**@} end of group CAN_REVA_INTEN_Register */ 318 319 /** 320 * @ingroup can_reva_registers 321 * @defgroup CAN_REVA_RMC CAN_REVA_RMC 322 * @brief Receive Message Counter Register. 323 * @{ 324 */ 325 #define MXC_F_CAN_REVA_RMC_NUM_MSGS_POS 0 /**< RMC_NUM_MSGS Position */ 326 #define MXC_F_CAN_REVA_RMC_NUM_MSGS ((uint8_t)(0x1FUL << MXC_F_CAN_REVA_RMC_NUM_MSGS_POS)) /**< RMC_NUM_MSGS Mask */ 327 328 /**@} end of group CAN_REVA_RMC_Register */ 329 330 /** 331 * @ingroup can_reva_registers 332 * @defgroup CAN_REVA_BUSTIM0 CAN_REVA_BUSTIM0 333 * @brief Bus Timing Register 0. 334 * @{ 335 */ 336 #define MXC_F_CAN_REVA_BUSTIM0_BR_CLKDIV_POS 0 /**< BUSTIM0_BR_CLKDIV Position */ 337 #define MXC_F_CAN_REVA_BUSTIM0_BR_CLKDIV ((uint8_t)(0x3FUL << MXC_F_CAN_REVA_BUSTIM0_BR_CLKDIV_POS)) /**< BUSTIM0_BR_CLKDIV Mask */ 338 339 #define MXC_F_CAN_REVA_BUSTIM0_SJW_POS 6 /**< BUSTIM0_SJW Position */ 340 #define MXC_F_CAN_REVA_BUSTIM0_SJW ((uint8_t)(0x3UL << MXC_F_CAN_REVA_BUSTIM0_SJW_POS)) /**< BUSTIM0_SJW Mask */ 341 342 /**@} end of group CAN_REVA_BUSTIM0_Register */ 343 344 /** 345 * @ingroup can_reva_registers 346 * @defgroup CAN_REVA_BUSTIM1 CAN_REVA_BUSTIM1 347 * @brief Bus Timing Register 1. 348 * @{ 349 */ 350 #define MXC_F_CAN_REVA_BUSTIM1_TSEG1_POS 0 /**< BUSTIM1_TSEG1 Position */ 351 #define MXC_F_CAN_REVA_BUSTIM1_TSEG1 ((uint8_t)(0xFUL << MXC_F_CAN_REVA_BUSTIM1_TSEG1_POS)) /**< BUSTIM1_TSEG1 Mask */ 352 353 #define MXC_F_CAN_REVA_BUSTIM1_TSEG2_POS 4 /**< BUSTIM1_TSEG2 Position */ 354 #define MXC_F_CAN_REVA_BUSTIM1_TSEG2 ((uint8_t)(0x7UL << MXC_F_CAN_REVA_BUSTIM1_TSEG2_POS)) /**< BUSTIM1_TSEG2 Mask */ 355 356 #define MXC_F_CAN_REVA_BUSTIM1_SAM_POS 7 /**< BUSTIM1_SAM Position */ 357 #define MXC_F_CAN_REVA_BUSTIM1_SAM ((uint8_t)(0x1UL << MXC_F_CAN_REVA_BUSTIM1_SAM_POS)) /**< BUSTIM1_SAM Mask */ 358 359 /**@} end of group CAN_REVA_BUSTIM1_Register */ 360 361 /** 362 * @ingroup can_reva_registers 363 * @defgroup CAN_REVA_TXFIFO32 CAN_REVA_TXFIFO32 364 * @brief Transmit FIFO Register. 365 * @{ 366 */ 367 #define MXC_F_CAN_REVA_TXFIFO32_DATA_POS 0 /**< TXFIFO32_DATA Position */ 368 #define MXC_F_CAN_REVA_TXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_REVA_TXFIFO32_DATA_POS)) /**< TXFIFO32_DATA Mask */ 369 370 /**@} end of group CAN_REVA_TXFIFO32_Register */ 371 372 /** 373 * @ingroup can_reva_registers 374 * @defgroup CAN_REVA_TXFIFO16 CAN_REVA_TXFIFO16 375 * @brief Transmit FIFO Register. 376 * @{ 377 */ 378 #define MXC_F_CAN_REVA_TXFIFO16_DATA_POS 0 /**< TXFIFO16_DATA Position */ 379 #define MXC_F_CAN_REVA_TXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_TXFIFO16_DATA_POS)) /**< TXFIFO16_DATA Mask */ 380 381 /**@} end of group CAN_REVA_TXFIFO16_Register */ 382 383 /** 384 * @ingroup can_reva_registers 385 * @defgroup CAN_REVA_TXFIFO8 CAN_REVA_TXFIFO8 386 * @brief Transmit FIFO Register. 387 * @{ 388 */ 389 #define MXC_F_CAN_REVA_TXFIFO8_DATA_POS 0 /**< TXFIFO8_DATA Position */ 390 #define MXC_F_CAN_REVA_TXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_TXFIFO8_DATA_POS)) /**< TXFIFO8_DATA Mask */ 391 392 /**@} end of group CAN_REVA_TXFIFO8_Register */ 393 394 /** 395 * @ingroup can_reva_registers 396 * @defgroup CAN_REVA_RXFIFO32 CAN_REVA_RXFIFO32 397 * @brief Receive FIFO Register. 398 * @{ 399 */ 400 #define MXC_F_CAN_REVA_RXFIFO32_DATA_POS 0 /**< RXFIFO32_DATA Position */ 401 #define MXC_F_CAN_REVA_RXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_REVA_RXFIFO32_DATA_POS)) /**< RXFIFO32_DATA Mask */ 402 403 /**@} end of group CAN_REVA_RXFIFO32_Register */ 404 405 /** 406 * @ingroup can_reva_registers 407 * @defgroup CAN_REVA_RXFIFO16 CAN_REVA_RXFIFO16 408 * @brief Receive FIFO Register. 409 * @{ 410 */ 411 #define MXC_F_CAN_REVA_RXFIFO16_DATA_POS 0 /**< RXFIFO16_DATA Position */ 412 #define MXC_F_CAN_REVA_RXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_RXFIFO16_DATA_POS)) /**< RXFIFO16_DATA Mask */ 413 414 /**@} end of group CAN_REVA_RXFIFO16_Register */ 415 416 /** 417 * @ingroup can_reva_registers 418 * @defgroup CAN_REVA_RXFIFO8 CAN_REVA_RXFIFO8 419 * @brief Receive FIFO Register. 420 * @{ 421 */ 422 #define MXC_F_CAN_REVA_RXFIFO8_DATA_POS 0 /**< RXFIFO8_DATA Position */ 423 #define MXC_F_CAN_REVA_RXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_RXFIFO8_DATA_POS)) /**< RXFIFO8_DATA Mask */ 424 425 /**@} end of group CAN_REVA_RXFIFO8_Register */ 426 427 /** 428 * @ingroup can_reva_registers 429 * @defgroup CAN_REVA_ACR32 CAN_REVA_ACR32 430 * @brief Acceptance Code Register. 431 * @{ 432 */ 433 #define MXC_F_CAN_REVA_ACR32_ACR_POS 0 /**< ACR32_ACR Position */ 434 #define MXC_F_CAN_REVA_ACR32_ACR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_REVA_ACR32_ACR_POS)) /**< ACR32_ACR Mask */ 435 436 /**@} end of group CAN_REVA_ACR32_Register */ 437 438 /** 439 * @ingroup can_reva_registers 440 * @defgroup CAN_REVA_ACR16 CAN_REVA_ACR16 441 * @brief Acceptance Code Register. 442 * @{ 443 */ 444 #define MXC_F_CAN_REVA_ACR16_ACR_POS 0 /**< ACR16_ACR Position */ 445 #define MXC_F_CAN_REVA_ACR16_ACR ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_ACR16_ACR_POS)) /**< ACR16_ACR Mask */ 446 447 /**@} end of group CAN_REVA_ACR16_Register */ 448 449 /** 450 * @ingroup can_reva_registers 451 * @defgroup CAN_REVA_ACR8 CAN_REVA_ACR8 452 * @brief Acceptance Code Register. 453 * @{ 454 */ 455 #define MXC_F_CAN_REVA_ACR8_ACR_POS 0 /**< ACR8_ACR Position */ 456 #define MXC_F_CAN_REVA_ACR8_ACR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_ACR8_ACR_POS)) /**< ACR8_ACR Mask */ 457 458 /**@} end of group CAN_REVA_ACR8_Register */ 459 460 /** 461 * @ingroup can_reva_registers 462 * @defgroup CAN_REVA_AMR32 CAN_REVA_AMR32 463 * @brief Acceptance Mask Register. 464 * @{ 465 */ 466 #define MXC_F_CAN_REVA_AMR32_AMR_POS 0 /**< AMR32_AMR Position */ 467 #define MXC_F_CAN_REVA_AMR32_AMR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_REVA_AMR32_AMR_POS)) /**< AMR32_AMR Mask */ 468 469 /**@} end of group CAN_REVA_AMR32_Register */ 470 471 /** 472 * @ingroup can_reva_registers 473 * @defgroup CAN_REVA_AMR16 CAN_REVA_AMR16 474 * @brief Acceptance Mask Register. 475 * @{ 476 */ 477 #define MXC_F_CAN_REVA_AMR16_AMR_POS 0 /**< AMR16_AMR Position */ 478 #define MXC_F_CAN_REVA_AMR16_AMR ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_AMR16_AMR_POS)) /**< AMR16_AMR Mask */ 479 480 /**@} end of group CAN_REVA_AMR16_Register */ 481 482 /** 483 * @ingroup can_reva_registers 484 * @defgroup CAN_REVA_AMR8 CAN_REVA_AMR8 485 * @brief Acceptance Mask Register. 486 * @{ 487 */ 488 #define MXC_F_CAN_REVA_AMR8_AMR_POS 0 /**< AMR8_AMR Position */ 489 #define MXC_F_CAN_REVA_AMR8_AMR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_AMR8_AMR_POS)) /**< AMR8_AMR Mask */ 490 491 /**@} end of group CAN_REVA_AMR8_Register */ 492 493 /** 494 * @ingroup can_reva_registers 495 * @defgroup CAN_REVA_ECC CAN_REVA_ECC 496 * @brief Error Code Capture Register. 497 * @{ 498 */ 499 #define MXC_F_CAN_REVA_ECC_BER_POS 0 /**< ECC_BER Position */ 500 #define MXC_F_CAN_REVA_ECC_BER ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_BER_POS)) /**< ECC_BER Mask */ 501 502 #define MXC_F_CAN_REVA_ECC_STFER_POS 1 /**< ECC_STFER Position */ 503 #define MXC_F_CAN_REVA_ECC_STFER ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_STFER_POS)) /**< ECC_STFER Mask */ 504 505 #define MXC_F_CAN_REVA_ECC_CRCER_POS 2 /**< ECC_CRCER Position */ 506 #define MXC_F_CAN_REVA_ECC_CRCER ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_CRCER_POS)) /**< ECC_CRCER Mask */ 507 508 #define MXC_F_CAN_REVA_ECC_FRMER_POS 3 /**< ECC_FRMER Position */ 509 #define MXC_F_CAN_REVA_ECC_FRMER ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_FRMER_POS)) /**< ECC_FRMER Mask */ 510 511 #define MXC_F_CAN_REVA_ECC_ACKER_POS 4 /**< ECC_ACKER Position */ 512 #define MXC_F_CAN_REVA_ECC_ACKER ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_ACKER_POS)) /**< ECC_ACKER Mask */ 513 514 #define MXC_F_CAN_REVA_ECC_EDIR_POS 5 /**< ECC_EDIR Position */ 515 #define MXC_F_CAN_REVA_ECC_EDIR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_EDIR_POS)) /**< ECC_EDIR Mask */ 516 517 #define MXC_F_CAN_REVA_ECC_TXWRN_POS 6 /**< ECC_TXWRN Position */ 518 #define MXC_F_CAN_REVA_ECC_TXWRN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_TXWRN_POS)) /**< ECC_TXWRN Mask */ 519 520 #define MXC_F_CAN_REVA_ECC_RXWRN_POS 7 /**< ECC_RXWRN Position */ 521 #define MXC_F_CAN_REVA_ECC_RXWRN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_ECC_RXWRN_POS)) /**< ECC_RXWRN Mask */ 522 523 /**@} end of group CAN_REVA_ECC_Register */ 524 525 /** 526 * @ingroup can_reva_registers 527 * @defgroup CAN_REVA_RXERR CAN_REVA_RXERR 528 * @brief Receive Error Counter. 529 * @{ 530 */ 531 #define MXC_F_CAN_REVA_RXERR_RXERR_POS 0 /**< RXERR_RXERR Position */ 532 #define MXC_F_CAN_REVA_RXERR_RXERR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_RXERR_RXERR_POS)) /**< RXERR_RXERR Mask */ 533 534 /**@} end of group CAN_REVA_RXERR_Register */ 535 536 /** 537 * @ingroup can_reva_registers 538 * @defgroup CAN_REVA_TXERR CAN_REVA_TXERR 539 * @brief Invalidate All Registers. 540 * @{ 541 */ 542 #define MXC_F_CAN_REVA_TXERR_TXERR_POS 0 /**< TXERR_TXERR Position */ 543 #define MXC_F_CAN_REVA_TXERR_TXERR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_TXERR_TXERR_POS)) /**< TXERR_TXERR Mask */ 544 545 /**@} end of group CAN_REVA_TXERR_Register */ 546 547 /** 548 * @ingroup can_reva_registers 549 * @defgroup CAN_REVA_ALC CAN_REVA_ALC 550 * @brief Arbitration Lost Code Capture Register. 551 * @{ 552 */ 553 #define MXC_F_CAN_REVA_ALC_ALC_POS 0 /**< ALC_ALC Position */ 554 #define MXC_F_CAN_REVA_ALC_ALC ((uint8_t)(0x1FUL << MXC_F_CAN_REVA_ALC_ALC_POS)) /**< ALC_ALC Mask */ 555 556 /**@} end of group CAN_REVA_ALC_Register */ 557 558 /** 559 * @ingroup can_reva_registers 560 * @defgroup CAN_REVA_NBT CAN_REVA_NBT 561 * @brief Nominal Bit Timing Register. 562 * @{ 563 */ 564 #define MXC_F_CAN_REVA_NBT_NBRP_POS 0 /**< NBT_NBRP Position */ 565 #define MXC_F_CAN_REVA_NBT_NBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_REVA_NBT_NBRP_POS)) /**< NBT_NBRP Mask */ 566 567 #define MXC_F_CAN_REVA_NBT_NSEG1_POS 10 /**< NBT_NSEG1 Position */ 568 #define MXC_F_CAN_REVA_NBT_NSEG1 ((uint32_t)(0xFFUL << MXC_F_CAN_REVA_NBT_NSEG1_POS)) /**< NBT_NSEG1 Mask */ 569 570 #define MXC_F_CAN_REVA_NBT_NSEG2_POS 18 /**< NBT_NSEG2 Position */ 571 #define MXC_F_CAN_REVA_NBT_NSEG2 ((uint32_t)(0x7FUL << MXC_F_CAN_REVA_NBT_NSEG2_POS)) /**< NBT_NSEG2 Mask */ 572 573 #define MXC_F_CAN_REVA_NBT_NSJW_POS 25 /**< NBT_NSJW Position */ 574 #define MXC_F_CAN_REVA_NBT_NSJW ((uint32_t)(0x7FUL << MXC_F_CAN_REVA_NBT_NSJW_POS)) /**< NBT_NSJW Mask */ 575 576 /**@} end of group CAN_REVA_NBT_Register */ 577 578 /** 579 * @ingroup can_reva_registers 580 * @defgroup CAN_REVA_DBT_SSPP CAN_REVA_DBT_SSPP 581 * @brief Data Bit Timing Register. 582 * @{ 583 */ 584 #define MXC_F_CAN_REVA_DBT_SSPP_DBRP_POS 0 /**< DBT_SSPP_DBRP Position */ 585 #define MXC_F_CAN_REVA_DBT_SSPP_DBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_REVA_DBT_SSPP_DBRP_POS)) /**< DBT_SSPP_DBRP Mask */ 586 587 #define MXC_F_CAN_REVA_DBT_SSPP_DSEG1_POS 10 /**< DBT_SSPP_DSEG1 Position */ 588 #define MXC_F_CAN_REVA_DBT_SSPP_DSEG1 ((uint32_t)(0x3FUL << MXC_F_CAN_REVA_DBT_SSPP_DSEG1_POS)) /**< DBT_SSPP_DSEG1 Mask */ 589 590 #define MXC_F_CAN_REVA_DBT_SSPP_DSEG2_POS 16 /**< DBT_SSPP_DSEG2 Position */ 591 #define MXC_F_CAN_REVA_DBT_SSPP_DSEG2 ((uint32_t)(0xFUL << MXC_F_CAN_REVA_DBT_SSPP_DSEG2_POS)) /**< DBT_SSPP_DSEG2 Mask */ 592 593 #define MXC_F_CAN_REVA_DBT_SSPP_DSJW_POS 20 /**< DBT_SSPP_DSJW Position */ 594 #define MXC_F_CAN_REVA_DBT_SSPP_DSJW ((uint32_t)(0xFUL << MXC_F_CAN_REVA_DBT_SSPP_DSJW_POS)) /**< DBT_SSPP_DSJW Mask */ 595 596 #define MXC_F_CAN_REVA_DBT_SSPP_SSPP_POS 24 /**< DBT_SSPP_SSPP Position */ 597 #define MXC_F_CAN_REVA_DBT_SSPP_SSPP ((uint32_t)(0x7FUL << MXC_F_CAN_REVA_DBT_SSPP_SSPP_POS)) /**< DBT_SSPP_SSPP Mask */ 598 599 /**@} end of group CAN_REVA_DBT_SSPP_Register */ 600 601 /** 602 * @ingroup can_reva_registers 603 * @defgroup CAN_REVA_FDCTRL CAN_REVA_FDCTRL 604 * @brief FD Control Register. 605 * @{ 606 */ 607 #define MXC_F_CAN_REVA_FDCTRL_FDEN_POS 0 /**< FDCTRL_FDEN Position */ 608 #define MXC_F_CAN_REVA_FDCTRL_FDEN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_FDEN_POS)) /**< FDCTRL_FDEN Mask */ 609 610 #define MXC_F_CAN_REVA_FDCTRL_BRSEN_POS 1 /**< FDCTRL_BRSEN Position */ 611 #define MXC_F_CAN_REVA_FDCTRL_BRSEN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_BRSEN_POS)) /**< FDCTRL_BRSEN Mask */ 612 613 #define MXC_F_CAN_REVA_FDCTRL_EXTBT_POS 2 /**< FDCTRL_EXTBT Position */ 614 #define MXC_F_CAN_REVA_FDCTRL_EXTBT ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_EXTBT_POS)) /**< FDCTRL_EXTBT Mask */ 615 616 #define MXC_F_CAN_REVA_FDCTRL_ISO_POS 3 /**< FDCTRL_ISO Position */ 617 #define MXC_F_CAN_REVA_FDCTRL_ISO ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_ISO_POS)) /**< FDCTRL_ISO Mask */ 618 619 #define MXC_F_CAN_REVA_FDCTRL_DAR_POS 4 /**< FDCTRL_DAR Position */ 620 #define MXC_F_CAN_REVA_FDCTRL_DAR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_DAR_POS)) /**< FDCTRL_DAR Mask */ 621 622 #define MXC_F_CAN_REVA_FDCTRL_REOM_POS 5 /**< FDCTRL_REOM Position */ 623 #define MXC_F_CAN_REVA_FDCTRL_REOM ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_REOM_POS)) /**< FDCTRL_REOM Mask */ 624 625 #define MXC_F_CAN_REVA_FDCTRL_PED_POS 6 /**< FDCTRL_PED Position */ 626 #define MXC_F_CAN_REVA_FDCTRL_PED ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDCTRL_PED_POS)) /**< FDCTRL_PED Mask */ 627 628 /**@} end of group CAN_REVA_FDCTRL_Register */ 629 630 /** 631 * @ingroup can_reva_registers 632 * @defgroup CAN_REVA_FDSTAT CAN_REVA_FDSTAT 633 * @brief Invalidate All Registers. 634 * @{ 635 */ 636 #define MXC_F_CAN_REVA_FDSTAT_BITERR_POS 0 /**< FDSTAT_BITERR Position */ 637 #define MXC_F_CAN_REVA_FDSTAT_BITERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDSTAT_BITERR_POS)) /**< FDSTAT_BITERR Mask */ 638 639 #define MXC_F_CAN_REVA_FDSTAT_CRCERR_POS 1 /**< FDSTAT_CRCERR Position */ 640 #define MXC_F_CAN_REVA_FDSTAT_CRCERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDSTAT_CRCERR_POS)) /**< FDSTAT_CRCERR Mask */ 641 642 #define MXC_F_CAN_REVA_FDSTAT_FRMERR_POS 2 /**< FDSTAT_FRMERR Position */ 643 #define MXC_F_CAN_REVA_FDSTAT_FRMERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDSTAT_FRMERR_POS)) /**< FDSTAT_FRMERR Mask */ 644 645 #define MXC_F_CAN_REVA_FDSTAT_STFERR_POS 3 /**< FDSTAT_STFERR Position */ 646 #define MXC_F_CAN_REVA_FDSTAT_STFERR ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDSTAT_STFERR_POS)) /**< FDSTAT_STFERR Mask */ 647 648 #define MXC_F_CAN_REVA_FDSTAT_PEE_POS 4 /**< FDSTAT_PEE Position */ 649 #define MXC_F_CAN_REVA_FDSTAT_PEE ((uint8_t)(0x1UL << MXC_F_CAN_REVA_FDSTAT_PEE_POS)) /**< FDSTAT_PEE Mask */ 650 651 #define MXC_F_CAN_REVA_FDSTAT_STATE_POS 6 /**< FDSTAT_STATE Position */ 652 #define MXC_F_CAN_REVA_FDSTAT_STATE ((uint8_t)(0x3UL << MXC_F_CAN_REVA_FDSTAT_STATE_POS)) /**< FDSTAT_STATE Mask */ 653 #define MXC_V_CAN_REVA_FDSTAT_STATE_INT ((uint8_t)0x0UL) /**< FDSTAT_STATE_INT Value */ 654 #define MXC_S_CAN_REVA_FDSTAT_STATE_INT (MXC_V_CAN_REVA_FDSTAT_STATE_INT << MXC_F_CAN_REVA_FDSTAT_STATE_POS) /**< FDSTAT_STATE_INT Setting */ 655 #define MXC_V_CAN_REVA_FDSTAT_STATE_IDLE ((uint8_t)0x1UL) /**< FDSTAT_STATE_IDLE Value */ 656 #define MXC_S_CAN_REVA_FDSTAT_STATE_IDLE (MXC_V_CAN_REVA_FDSTAT_STATE_IDLE << MXC_F_CAN_REVA_FDSTAT_STATE_POS) /**< FDSTAT_STATE_IDLE Setting */ 657 #define MXC_V_CAN_REVA_FDSTAT_STATE_RX ((uint8_t)0x2UL) /**< FDSTAT_STATE_RX Value */ 658 #define MXC_S_CAN_REVA_FDSTAT_STATE_RX (MXC_V_CAN_REVA_FDSTAT_STATE_RX << MXC_F_CAN_REVA_FDSTAT_STATE_POS) /**< FDSTAT_STATE_RX Setting */ 659 #define MXC_V_CAN_REVA_FDSTAT_STATE_TX ((uint8_t)0x3UL) /**< FDSTAT_STATE_TX Value */ 660 #define MXC_S_CAN_REVA_FDSTAT_STATE_TX (MXC_V_CAN_REVA_FDSTAT_STATE_TX << MXC_F_CAN_REVA_FDSTAT_STATE_POS) /**< FDSTAT_STATE_TX Setting */ 661 662 /**@} end of group CAN_REVA_FDSTAT_Register */ 663 664 /** 665 * @ingroup can_reva_registers 666 * @defgroup CAN_REVA_DPERR CAN_REVA_DPERR 667 * @brief Data Phase Error Counter Register. 668 * @{ 669 */ 670 #define MXC_F_CAN_REVA_DPERR_DPERR_POS 0 /**< DPERR_DPERR Position */ 671 #define MXC_F_CAN_REVA_DPERR_DPERR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_DPERR_DPERR_POS)) /**< DPERR_DPERR Mask */ 672 673 /**@} end of group CAN_REVA_DPERR_Register */ 674 675 /** 676 * @ingroup can_reva_registers 677 * @defgroup CAN_REVA_APERR CAN_REVA_APERR 678 * @brief Arbitration Phase Error Counter Register. 679 * @{ 680 */ 681 #define MXC_F_CAN_REVA_APERR_APERR_POS 0 /**< APERR_APERR Position */ 682 #define MXC_F_CAN_REVA_APERR_APERR ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_APERR_APERR_POS)) /**< APERR_APERR Mask */ 683 684 /**@} end of group CAN_REVA_APERR_Register */ 685 686 /** 687 * @ingroup can_reva_registers 688 * @defgroup CAN_REVA_TEST CAN_REVA_TEST 689 * @brief Invalidate All Registers. 690 * @{ 691 */ 692 #define MXC_F_CAN_REVA_TEST_LBEN_POS 0 /**< TEST_LBEN Position */ 693 #define MXC_F_CAN_REVA_TEST_LBEN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_TEST_LBEN_POS)) /**< TEST_LBEN Mask */ 694 695 #define MXC_F_CAN_REVA_TEST_TXC_POS 1 /**< TEST_TXC Position */ 696 #define MXC_F_CAN_REVA_TEST_TXC ((uint8_t)(0x1UL << MXC_F_CAN_REVA_TEST_TXC_POS)) /**< TEST_TXC Mask */ 697 698 /**@} end of group CAN_REVA_TEST_Register */ 699 700 /** 701 * @ingroup can_reva_registers 702 * @defgroup CAN_REVA_WUPCLKDIV CAN_REVA_WUPCLKDIV 703 * @brief Wake-up timer prescaler. 704 * @{ 705 */ 706 #define MXC_F_CAN_REVA_WUPCLKDIV_WUPDIV_POS 0 /**< WUPCLKDIV_WUPDIV Position */ 707 #define MXC_F_CAN_REVA_WUPCLKDIV_WUPDIV ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_WUPCLKDIV_WUPDIV_POS)) /**< WUPCLKDIV_WUPDIV Mask */ 708 709 /**@} end of group CAN_REVA_WUPCLKDIV_Register */ 710 711 /** 712 * @ingroup can_reva_registers 713 * @defgroup CAN_REVA_WUPFT CAN_REVA_WUPFT 714 * @brief Wake up Filter Time Register. 715 * @{ 716 */ 717 #define MXC_F_CAN_REVA_WUPFT_WUPFT_POS 0 /**< WUPFT_WUPFT Position */ 718 #define MXC_F_CAN_REVA_WUPFT_WUPFT ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_WUPFT_WUPFT_POS)) /**< WUPFT_WUPFT Mask */ 719 720 /**@} end of group CAN_REVA_WUPFT_Register */ 721 722 /** 723 * @ingroup can_reva_registers 724 * @defgroup CAN_REVA_WUPET CAN_REVA_WUPET 725 * @brief Wake-up Expire Time Register. 726 * @{ 727 */ 728 #define MXC_F_CAN_REVA_WUPET_WUPET_POS 0 /**< WUPET_WUPET Position */ 729 #define MXC_F_CAN_REVA_WUPET_WUPET ((uint32_t)(0xFFFFFUL << MXC_F_CAN_REVA_WUPET_WUPET_POS)) /**< WUPET_WUPET Mask */ 730 731 /**@} end of group CAN_REVA_WUPET_Register */ 732 733 /** 734 * @ingroup can_reva_registers 735 * @defgroup CAN_REVA_RXDCNT CAN_REVA_RXDCNT 736 * @brief RX FIFO Data Counter Register. 737 * @{ 738 */ 739 #define MXC_F_CAN_REVA_RXDCNT_RXDCNT_POS 0 /**< RXDCNT_RXDCNT Position */ 740 #define MXC_F_CAN_REVA_RXDCNT_RXDCNT ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_RXDCNT_RXDCNT_POS)) /**< RXDCNT_RXDCNT Mask */ 741 742 /**@} end of group CAN_REVA_RXDCNT_Register */ 743 744 /** 745 * @ingroup can_reva_registers 746 * @defgroup CAN_REVA_TXSCNT CAN_REVA_TXSCNT 747 * @brief TX FIFO Space Counter. 748 * @{ 749 */ 750 #define MXC_F_CAN_REVA_TXSCNT_TXSCNT_POS 0 /**< TXSCNT_TXSCNT Position */ 751 #define MXC_F_CAN_REVA_TXSCNT_TXSCNT ((uint8_t)(0xFFUL << MXC_F_CAN_REVA_TXSCNT_TXSCNT_POS)) /**< TXSCNT_TXSCNT Mask */ 752 753 /**@} end of group CAN_REVA_TXSCNT_Register */ 754 755 /** 756 * @ingroup can_reva_registers 757 * @defgroup CAN_REVA_TXDECMP CAN_REVA_TXDECMP 758 * @brief Invalidate All Registers. 759 * @{ 760 */ 761 #define MXC_F_CAN_REVA_TXDECMP_TDCO_POS 0 /**< TXDECMP_TDCO Position */ 762 #define MXC_F_CAN_REVA_TXDECMP_TDCO ((uint8_t)(0x7FUL << MXC_F_CAN_REVA_TXDECMP_TDCO_POS)) /**< TXDECMP_TDCO Mask */ 763 764 #define MXC_F_CAN_REVA_TXDECMP_TDCEN_POS 7 /**< TXDECMP_TDCEN Position */ 765 #define MXC_F_CAN_REVA_TXDECMP_TDCEN ((uint8_t)(0x1UL << MXC_F_CAN_REVA_TXDECMP_TDCEN_POS)) /**< TXDECMP_TDCEN Mask */ 766 767 /**@} end of group CAN_REVA_TXDECMP_Register */ 768 769 /** 770 * @ingroup can_reva_registers 771 * @defgroup CAN_REVA_EINTFL CAN_REVA_EINTFL 772 * @brief Extended Interrupt Flag Register. 773 * @{ 774 */ 775 #define MXC_F_CAN_REVA_EINTFL_RX_THD_POS 0 /**< EINTFL_RX_THD Position */ 776 #define MXC_F_CAN_REVA_EINTFL_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_REVA_EINTFL_RX_THD_POS)) /**< EINTFL_RX_THD Mask */ 777 778 #define MXC_F_CAN_REVA_EINTFL_RX_TO_POS 1 /**< EINTFL_RX_TO Position */ 779 #define MXC_F_CAN_REVA_EINTFL_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_REVA_EINTFL_RX_TO_POS)) /**< EINTFL_RX_TO Mask */ 780 781 /**@} end of group CAN_REVA_EINTFL_Register */ 782 783 /** 784 * @ingroup can_reva_registers 785 * @defgroup CAN_REVA_EINTEN CAN_REVA_EINTEN 786 * @brief Extended Interrupt Enable Register. 787 * @{ 788 */ 789 #define MXC_F_CAN_REVA_EINTEN_RX_THD_POS 0 /**< EINTEN_RX_THD Position */ 790 #define MXC_F_CAN_REVA_EINTEN_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_REVA_EINTEN_RX_THD_POS)) /**< EINTEN_RX_THD Mask */ 791 792 #define MXC_F_CAN_REVA_EINTEN_RX_TO_POS 1 /**< EINTEN_RX_TO Position */ 793 #define MXC_F_CAN_REVA_EINTEN_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_REVA_EINTEN_RX_TO_POS)) /**< EINTEN_RX_TO Mask */ 794 795 /**@} end of group CAN_REVA_EINTEN_Register */ 796 797 /** 798 * @ingroup can_reva_registers 799 * @defgroup CAN_REVA_RXTO CAN_REVA_RXTO 800 * @brief RX FIFO Timeout Register. 801 * @{ 802 */ 803 #define MXC_F_CAN_REVA_RXTO_RX_TO_POS 0 /**< RXTO_RX_TO Position */ 804 #define MXC_F_CAN_REVA_RXTO_RX_TO ((uint16_t)(0xFFFFUL << MXC_F_CAN_REVA_RXTO_RX_TO_POS)) /**< RXTO_RX_TO Mask */ 805 806 /**@} end of group CAN_REVA_RXTO_Register */ 807 808 #ifdef __cplusplus 809 } 810 #endif 811 812 #endif /* _CAN_REVA_REGS_H_ */ 813
