1 /** 2 * @file aes_revb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _AES_REVB_REGS_H_ 27 #define _AES_REVB_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup aes_revb 65 * @defgroup aes_revb_registers AES_REVB_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module. 67 * @details AES Keys. 68 */ 69 70 /** 71 * @ingroup aes_revb_registers 72 * Structure type to access the AES_REVB Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_REVB CTRL Register */ 76 __IO uint32_t status; /**< <tt>\b 0x0004:</tt> AES_REVB STATUS Register */ 77 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> AES_REVB INTFL Register */ 78 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> AES_REVB INTEN Register */ 79 __IO uint32_t fifo; /**< <tt>\b 0x0010:</tt> AES_REVB FIFO Register */ 80 } mxc_aes_revb_regs_t; 81 82 /* Register offsets for module AES_REVB */ 83 /** 84 * @ingroup aes_revb_registers 85 * @defgroup AES_REVB_Register_Offsets Register Offsets 86 * @brief AES_REVB Peripheral Register Offsets from the AES_REVB Base Peripheral Address. 87 * @{ 88 */ 89 #define MXC_R_AES_REVB_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES_REVB Base Address: <tt> 0x0000</tt> */ 90 #define MXC_R_AES_REVB_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES_REVB Base Address: <tt> 0x0004</tt> */ 91 #define MXC_R_AES_REVB_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES_REVB Base Address: <tt> 0x0008</tt> */ 92 #define MXC_R_AES_REVB_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES_REVB Base Address: <tt> 0x000C</tt> */ 93 #define MXC_R_AES_REVB_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES_REVB Base Address: <tt> 0x0010</tt> */ 94 /**@} end of group aes_revb_registers */ 95 96 /** 97 * @ingroup aes_revb_registers 98 * @defgroup AES_REVB_CTRL AES_REVB_CTRL 99 * @brief AES Control Register 100 * @{ 101 */ 102 #define MXC_F_AES_REVB_CTRL_EN_POS 0 /**< CTRL_EN Position */ 103 #define MXC_F_AES_REVB_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_EN_POS)) /**< CTRL_EN Mask */ 104 105 #define MXC_F_AES_REVB_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ 106 #define MXC_F_AES_REVB_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ 107 108 #define MXC_F_AES_REVB_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ 109 #define MXC_F_AES_REVB_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ 110 111 #define MXC_F_AES_REVB_CTRL_START_POS 3 /**< CTRL_START Position */ 112 #define MXC_F_AES_REVB_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_START_POS)) /**< CTRL_START Mask */ 113 114 #define MXC_F_AES_REVB_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ 115 #define MXC_F_AES_REVB_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ 116 117 #define MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ 118 #define MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ 119 120 #define MXC_F_AES_REVB_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ 121 #define MXC_F_AES_REVB_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ 122 #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ 123 #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128 (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES128 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ 124 #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ 125 #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192 (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES192 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ 126 #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ 127 #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256 (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES256 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ 128 129 #define MXC_F_AES_REVB_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ 130 #define MXC_F_AES_REVB_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_REVB_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ 131 132 /**@} end of group AES_REVB_CTRL_Register */ 133 134 /** 135 * @ingroup aes_revb_registers 136 * @defgroup AES_REVB_STATUS AES_REVB_STATUS 137 * @brief AES Status Register 138 * @{ 139 */ 140 #define MXC_F_AES_REVB_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 141 #define MXC_F_AES_REVB_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 142 143 #define MXC_F_AES_REVB_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ 144 #define MXC_F_AES_REVB_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ 145 146 #define MXC_F_AES_REVB_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ 147 #define MXC_F_AES_REVB_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ 148 149 #define MXC_F_AES_REVB_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ 150 #define MXC_F_AES_REVB_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ 151 152 #define MXC_F_AES_REVB_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ 153 #define MXC_F_AES_REVB_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ 154 155 /**@} end of group AES_REVB_STATUS_Register */ 156 157 /** 158 * @ingroup aes_revb_registers 159 * @defgroup AES_REVB_INTFL AES_REVB_INTFL 160 * @brief AES Interrupt Flag Register 161 * @{ 162 */ 163 #define MXC_F_AES_REVB_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ 164 #define MXC_F_AES_REVB_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ 165 166 #define MXC_F_AES_REVB_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ 167 #define MXC_F_AES_REVB_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ 168 169 #define MXC_F_AES_REVB_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ 170 #define MXC_F_AES_REVB_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ 171 172 #define MXC_F_AES_REVB_INTFL_OV_POS 3 /**< INTFL_OV Position */ 173 #define MXC_F_AES_REVB_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_OV_POS)) /**< INTFL_OV Mask */ 174 175 /**@} end of group AES_REVB_INTFL_Register */ 176 177 /** 178 * @ingroup aes_revb_registers 179 * @defgroup AES_REVB_INTEN AES_REVB_INTEN 180 * @brief AES Interrupt Enable Register 181 * @{ 182 */ 183 #define MXC_F_AES_REVB_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ 184 #define MXC_F_AES_REVB_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ 185 186 #define MXC_F_AES_REVB_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ 187 #define MXC_F_AES_REVB_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ 188 189 #define MXC_F_AES_REVB_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ 190 #define MXC_F_AES_REVB_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ 191 192 #define MXC_F_AES_REVB_INTEN_OV_POS 3 /**< INTEN_OV Position */ 193 #define MXC_F_AES_REVB_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_OV_POS)) /**< INTEN_OV Mask */ 194 195 /**@} end of group AES_REVB_INTEN_Register */ 196 197 /** 198 * @ingroup aes_revb_registers 199 * @defgroup AES_REVB_FIFO AES_REVB_FIFO 200 * @brief AES Data Register 201 * @{ 202 */ 203 #define MXC_F_AES_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 204 #define MXC_F_AES_REVB_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 205 206 /**@} end of group AES_REVB_FIFO_Register */ 207 208 #ifdef __cplusplus 209 } 210 #endif 211 212 #endif /* _AES_REVB_REGS_H_ */ 213
