1 /** 2 * @file adc_revb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _ADC_REVB_REGS_H_ 27 #define _ADC_REVB_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup adc_revb 65 * @defgroup adc_revb_registers ADC_REVB_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 67 * @details Inter-Integrated Circuit. 68 */ 69 70 /** 71 * @ingroup adc_revb_registers 72 * Structure type to access the ADC Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> ADC CTRL0 Register */ 76 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> ADC CTRL1 Register */ 77 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> ADC CLKCTRL Register */ 78 __IO uint32_t sampclkctrl; /**< <tt>\b 0x0C:</tt> ADC SAMPCLKCTRL Register */ 79 __IO uint32_t chsel0; /**< <tt>\b 0x10:</tt> ADC CHSEL0 Register */ 80 __IO uint32_t chsel1; /**< <tt>\b 0x14:</tt> ADC CHSEL1 Register */ 81 __IO uint32_t chsel2; /**< <tt>\b 0x18:</tt> ADC CHSEL2 Register */ 82 __IO uint32_t chsel3; /**< <tt>\b 0x1C:</tt> ADC CHSEL3 Register */ 83 __IO uint32_t chsel4; /**< <tt>\b 0x20:</tt> ADC CHSEL4 Register */ 84 __IO uint32_t chsel5; /**< <tt>\b 0x24:</tt> ADC CHSEL5 Register */ 85 __IO uint32_t chsel6; /**< <tt>\b 0x28:</tt> ADC CHSEL6 Register */ 86 __IO uint32_t chsel7; /**< <tt>\b 0x2C:</tt> ADC CHSEL7 Register */ 87 __IO uint32_t restart; /**< <tt>\b 0x30:</tt> ADC RESTART Register */ 88 __R uint32_t rsv_0x34_0x3b[2]; 89 __IO uint32_t datafmt; /**< <tt>\b 0x3C:</tt> ADC DATAFMT Register */ 90 __IO uint32_t fifodmactrl; /**< <tt>\b 0x40:</tt> ADC FIFODMACTRL Register */ 91 __IO uint32_t data; /**< <tt>\b 0x44:</tt> ADC DATA Register */ 92 __IO uint32_t status; /**< <tt>\b 0x48:</tt> ADC STATUS Register */ 93 __IO uint32_t chstatus; /**< <tt>\b 0x4C:</tt> ADC CHSTATUS Register */ 94 __IO uint32_t inten; /**< <tt>\b 0x50:</tt> ADC INTEN Register */ 95 __IO uint32_t intfl; /**< <tt>\b 0x54:</tt> ADC INTFL Register */ 96 __R uint32_t rsv_0x58_0x5f[2]; 97 __IO uint32_t sfraddroffset; /**< <tt>\b 0x60:</tt> ADC SFRADDROFFSET Register */ 98 __IO uint32_t sfraddr; /**< <tt>\b 0x64:</tt> ADC SFRADDR Register */ 99 __IO uint32_t sfrwrdata; /**< <tt>\b 0x68:</tt> ADC SFRWRDATA Register */ 100 __IO uint32_t sfrrddata; /**< <tt>\b 0x6C:</tt> ADC SFRRDDATA Register */ 101 __IO uint32_t sfrstatus; /**< <tt>\b 0x70:</tt> ADC SFRSTATUS Register */ 102 } mxc_adc_revb_regs_t; 103 104 /* Register offsets for module ADC */ 105 /** 106 * @ingroup adc_revb_registers 107 * @defgroup ADC_REVB_Register_Offsets Register Offsets 108 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. 109 * @{ 110 */ 111 #define MXC_R_ADC_REVB_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt> 0x0000</tt> */ 112 #define MXC_R_ADC_REVB_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt> 0x0004</tt> */ 113 #define MXC_R_ADC_REVB_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt> 0x0008</tt> */ 114 #define MXC_R_ADC_REVB_SAMPCLKCTRL ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt> 0x000C</tt> */ 115 #define MXC_R_ADC_REVB_CHSEL0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt> 0x0010</tt> */ 116 #define MXC_R_ADC_REVB_CHSEL1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt> 0x0014</tt> */ 117 #define MXC_R_ADC_REVB_CHSEL2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt> 0x0018</tt> */ 118 #define MXC_R_ADC_REVB_CHSEL3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt> 0x001C</tt> */ 119 #define MXC_R_ADC_REVB_CHSEL4 ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt> 0x0020</tt> */ 120 #define MXC_R_ADC_REVB_CHSEL5 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt> 0x0024</tt> */ 121 #define MXC_R_ADC_REVB_CHSEL6 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt> 0x0028</tt> */ 122 #define MXC_R_ADC_REVB_CHSEL7 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt> 0x002C</tt> */ 123 #define MXC_R_ADC_REVB_RESTART ((uint32_t)0x00000030UL) /**< Offset from ADC Base Address: <tt> 0x0030</tt> */ 124 #define MXC_R_ADC_REVB_DATAFMT ((uint32_t)0x0000003CUL) /**< Offset from ADC Base Address: <tt> 0x003C</tt> */ 125 #define MXC_R_ADC_REVB_FIFODMACTRL ((uint32_t)0x00000040UL) /**< Offset from ADC Base Address: <tt> 0x0040</tt> */ 126 #define MXC_R_ADC_REVB_DATA ((uint32_t)0x00000044UL) /**< Offset from ADC Base Address: <tt> 0x0044</tt> */ 127 #define MXC_R_ADC_REVB_STATUS ((uint32_t)0x00000048UL) /**< Offset from ADC Base Address: <tt> 0x0048</tt> */ 128 #define MXC_R_ADC_REVB_CHSTATUS ((uint32_t)0x0000004CUL) /**< Offset from ADC Base Address: <tt> 0x004C</tt> */ 129 #define MXC_R_ADC_REVB_INTEN ((uint32_t)0x00000050UL) /**< Offset from ADC Base Address: <tt> 0x0050</tt> */ 130 #define MXC_R_ADC_REVB_INTFL ((uint32_t)0x00000054UL) /**< Offset from ADC Base Address: <tt> 0x0054</tt> */ 131 #define MXC_R_ADC_REVB_SFRADDROFFSET ((uint32_t)0x00000060UL) /**< Offset from ADC Base Address: <tt> 0x0060</tt> */ 132 #define MXC_R_ADC_REVB_SFRADDR ((uint32_t)0x00000064UL) /**< Offset from ADC Base Address: <tt> 0x0064</tt> */ 133 #define MXC_R_ADC_REVB_SFRWRDATA ((uint32_t)0x00000068UL) /**< Offset from ADC Base Address: <tt> 0x0068</tt> */ 134 #define MXC_R_ADC_REVB_SFRRDDATA ((uint32_t)0x0000006CUL) /**< Offset from ADC Base Address: <tt> 0x006C</tt> */ 135 #define MXC_R_ADC_REVB_SFRSTATUS ((uint32_t)0x00000070UL) /**< Offset from ADC Base Address: <tt> 0x0070</tt> */ 136 /**@} end of group adc_revb_registers */ 137 138 /** 139 * @ingroup adc_revb_registers 140 * @defgroup ADC_REVB_CTRL0 ADC_REVB_CTRL0 141 * @brief Control Register 0. 142 * @{ 143 */ 144 #define MXC_F_ADC_REVB_CTRL0_ADC_EN_POS 0 /**< CTRL0_ADC_REVB_EN Position */ 145 #define MXC_F_ADC_REVB_CTRL0_ADC_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL0_ADC_EN_POS)) /**< CTRL0_ADC_REVB_EN Mask */ 146 147 #define MXC_F_ADC_REVB_CTRL0_BIAS_EN_POS 1 /**< CTRL0_BIAS_EN Position */ 148 #define MXC_F_ADC_REVB_CTRL0_BIAS_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL0_BIAS_EN_POS)) /**< CTRL0_BIAS_EN Mask */ 149 150 #define MXC_F_ADC_REVB_CTRL0_SKIP_CAL_POS 2 /**< CTRL0_SKIP_CAL Position */ 151 #define MXC_F_ADC_REVB_CTRL0_SKIP_CAL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL0_SKIP_CAL_POS)) /**< CTRL0_SKIP_CAL Mask */ 152 153 #define MXC_F_ADC_REVB_CTRL0_CHOP_FORCE_POS 3 /**< CTRL0_CHOP_FORCE Position */ 154 #define MXC_F_ADC_REVB_CTRL0_CHOP_FORCE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL0_CHOP_FORCE_POS)) /**< CTRL0_CHOP_FORCE Mask */ 155 156 #define MXC_F_ADC_REVB_CTRL0_RESETB_POS 4 /**< CTRL0_RESETB Position */ 157 #define MXC_F_ADC_REVB_CTRL0_RESETB ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL0_RESETB_POS)) /**< CTRL0_RESETB Mask */ 158 159 /**@} end of group ADC_REVB_CTRL0_Register */ 160 161 /** 162 * @ingroup adc_revb_registers 163 * @defgroup ADC_REVB_CTRL1 ADC_REVB_CTRL1 164 * @brief Control Register 1. 165 * @{ 166 */ 167 #define MXC_F_ADC_REVB_CTRL1_START_POS 0 /**< CTRL1_START Position */ 168 #define MXC_F_ADC_REVB_CTRL1_START ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL1_START_POS)) /**< CTRL1_START Mask */ 169 170 #define MXC_F_ADC_REVB_CTRL1_TRIG_MODE_POS 1 /**< CTRL1_TRIG_MODE Position */ 171 #define MXC_F_ADC_REVB_CTRL1_TRIG_MODE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL1_TRIG_MODE_POS)) /**< CTRL1_TRIG_MODE Mask */ 172 173 #define MXC_F_ADC_REVB_CTRL1_CNV_MODE_POS 2 /**< CTRL1_CNV_MODE Position */ 174 #define MXC_F_ADC_REVB_CTRL1_CNV_MODE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL1_CNV_MODE_POS)) /**< CTRL1_CNV_MODE Mask */ 175 176 #define MXC_F_ADC_REVB_CTRL1_SAMP_CK_OFF_POS 3 /**< CTRL1_SAMP_CK_OFF Position */ 177 #define MXC_F_ADC_REVB_CTRL1_SAMP_CK_OFF ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL1_SAMP_CK_OFF_POS)) /**< CTRL1_SAMP_CK_OFF Mask */ 178 179 #define MXC_F_ADC_REVB_CTRL1_TRIG_SEL_POS 4 /**< CTRL1_TRIG_SEL Position */ 180 #define MXC_F_ADC_REVB_CTRL1_TRIG_SEL ((uint32_t)(0x7UL << MXC_F_ADC_REVB_CTRL1_TRIG_SEL_POS)) /**< CTRL1_TRIG_SEL Mask */ 181 182 #define MXC_F_ADC_REVB_CTRL1_TS_SEL_POS 7 /**< CTRL1_TS_SEL Position */ 183 #define MXC_F_ADC_REVB_CTRL1_TS_SEL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_CTRL1_TS_SEL_POS)) /**< CTRL1_TS_SEL Mask */ 184 185 #define MXC_F_ADC_REVB_CTRL1_AVG_POS 8 /**< CTRL1_AVG Position */ 186 #define MXC_F_ADC_REVB_CTRL1_AVG ((uint32_t)(0x7UL << MXC_F_ADC_REVB_CTRL1_AVG_POS)) /**< CTRL1_AVG Mask */ 187 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG1 ((uint32_t)0x0UL) /**< CTRL1_AVG_AVG1 Value */ 188 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG1 (MXC_V_ADC_REVB_CTRL1_AVG_AVG1 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG1 Setting */ 189 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG2 ((uint32_t)0x1UL) /**< CTRL1_AVG_AVG2 Value */ 190 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG2 (MXC_V_ADC_REVB_CTRL1_AVG_AVG2 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG2 Setting */ 191 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG4 ((uint32_t)0x2UL) /**< CTRL1_AVG_AVG4 Value */ 192 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG4 (MXC_V_ADC_REVB_CTRL1_AVG_AVG4 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG4 Setting */ 193 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG8 ((uint32_t)0x3UL) /**< CTRL1_AVG_AVG8 Value */ 194 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG8 (MXC_V_ADC_REVB_CTRL1_AVG_AVG8 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG8 Setting */ 195 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG16 ((uint32_t)0x4UL) /**< CTRL1_AVG_AVG16 Value */ 196 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG16 (MXC_V_ADC_REVB_CTRL1_AVG_AVG16 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG16 Setting */ 197 #define MXC_V_ADC_REVB_CTRL1_AVG_AVG32 ((uint32_t)0x5UL) /**< CTRL1_AVG_AVG32 Value */ 198 #define MXC_S_ADC_REVB_CTRL1_AVG_AVG32 (MXC_V_ADC_REVB_CTRL1_AVG_AVG32 << MXC_F_ADC_REVB_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG32 Setting */ 199 200 #define MXC_F_ADC_REVB_CTRL1_NUM_SLOTS_POS 16 /**< CTRL1_NUM_SLOTS Position */ 201 #define MXC_F_ADC_REVB_CTRL1_NUM_SLOTS ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CTRL1_NUM_SLOTS_POS)) /**< CTRL1_NUM_SLOTS Mask */ 202 203 /**@} end of group ADC_REVB_CTRL1_Register */ 204 205 /** 206 * @ingroup adc_revb_registers 207 * @defgroup ADC_REVB_CLKCTRL ADC_REVB_CLKCTRL 208 * @brief Clock Control Register. 209 * @{ 210 */ 211 #define MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS 0 /**< CLKCTRL_CLKSEL Position */ 212 #define MXC_F_ADC_REVB_CLKCTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS)) /**< CLKCTRL_CLKSEL Mask */ 213 #define MXC_V_ADC_REVB_CLKCTRL_CLKSEL_HCLK ((uint32_t)0x0UL) /**< CLKCTRL_CLKSEL_HCLK Value */ 214 #define MXC_S_ADC_REVB_CLKCTRL_CLKSEL_HCLK (MXC_V_ADC_REVB_CLKCTRL_CLKSEL_HCLK << MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_HCLK Setting */ 215 #define MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC0 ((uint32_t)0x1UL) /**< CLKCTRL_CLKSEL_CLK_ADC0 Value */ 216 #define MXC_S_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC0 (MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC0 << MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC0 Setting */ 217 #define MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC1 ((uint32_t)0x2UL) /**< CLKCTRL_CLKSEL_CLK_ADC1 Value */ 218 #define MXC_S_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC1 (MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC1 << MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC1 Setting */ 219 #define MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC2 ((uint32_t)0x3UL) /**< CLKCTRL_CLKSEL_CLK_ADC2 Value */ 220 #define MXC_S_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC2 (MXC_V_ADC_REVB_CLKCTRL_CLKSEL_CLK_ADC2 << MXC_F_ADC_REVB_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC2 Setting */ 221 222 #define MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS 4 /**< CLKCTRL_CLKDIV Position */ 223 #define MXC_F_ADC_REVB_CLKCTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ 224 #define MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV2 ((uint32_t)0x0UL) /**< CLKCTRL_CLKDIV_DIV2 Value */ 225 #define MXC_S_ADC_REVB_CLKCTRL_CLKDIV_DIV2 (MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV2 << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV2 Setting */ 226 #define MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV4 ((uint32_t)0x1UL) /**< CLKCTRL_CLKDIV_DIV4 Value */ 227 #define MXC_S_ADC_REVB_CLKCTRL_CLKDIV_DIV4 (MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV4 << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV4 Setting */ 228 #define MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV8 ((uint32_t)0x2UL) /**< CLKCTRL_CLKDIV_DIV8 Value */ 229 #define MXC_S_ADC_REVB_CLKCTRL_CLKDIV_DIV8 (MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV8 << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV8 Setting */ 230 #define MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV16 ((uint32_t)0x3UL) /**< CLKCTRL_CLKDIV_DIV16 Value */ 231 #define MXC_S_ADC_REVB_CLKCTRL_CLKDIV_DIV16 (MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV16 << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV16 Setting */ 232 #define MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV1 ((uint32_t)0x4UL) /**< CLKCTRL_CLKDIV_DIV1 Value */ 233 #define MXC_S_ADC_REVB_CLKCTRL_CLKDIV_DIV1 (MXC_V_ADC_REVB_CLKCTRL_CLKDIV_DIV1 << MXC_F_ADC_REVB_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV1 Setting */ 234 235 /**@} end of group ADC_REVB_CLKCTRL_Register */ 236 237 /** 238 * @ingroup adc_revb_registers 239 * @defgroup ADC_REVB_SAMPCLKCTRL ADC_REVB_SAMPCLKCTRL 240 * @brief Sample Clock Control Register. 241 * @{ 242 */ 243 #define MXC_F_ADC_REVB_SAMPCLKCTRL_TRACK_CNT_POS 0 /**< SAMPCLKCTRL_TRACK_CNT Position */ 244 #define MXC_F_ADC_REVB_SAMPCLKCTRL_TRACK_CNT ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_SAMPCLKCTRL_TRACK_CNT_POS)) /**< SAMPCLKCTRL_TRACK_CNT Mask */ 245 246 #define MXC_F_ADC_REVB_SAMPCLKCTRL_IDLE_CNT_POS 16 /**< SAMPCLKCTRL_IDLE_CNT Position */ 247 #define MXC_F_ADC_REVB_SAMPCLKCTRL_IDLE_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_REVB_SAMPCLKCTRL_IDLE_CNT_POS)) /**< SAMPCLKCTRL_IDLE_CNT Mask */ 248 249 /**@} end of group ADC_REVB_SAMPCLKCTRL_Register */ 250 251 /** 252 * @ingroup adc_revb_registers 253 * @defgroup ADC_REVB_CHSEL0 ADC_REVB_CHSEL0 254 * @brief Channel Select Register 0. 255 * @{ 256 */ 257 #define MXC_F_ADC_REVB_CHSEL0_SLOT0_ID_POS 0 /**< CHSEL0_SLOT0_ID Position */ 258 #define MXC_F_ADC_REVB_CHSEL0_SLOT0_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL0_SLOT0_ID_POS)) /**< CHSEL0_SLOT0_ID Mask */ 259 260 #define MXC_F_ADC_REVB_CHSEL0_SLOT1_ID_POS 8 /**< CHSEL0_SLOT1_ID Position */ 261 #define MXC_F_ADC_REVB_CHSEL0_SLOT1_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL0_SLOT1_ID_POS)) /**< CHSEL0_SLOT1_ID Mask */ 262 263 #define MXC_F_ADC_REVB_CHSEL0_SLOT2_ID_POS 16 /**< CHSEL0_SLOT2_ID Position */ 264 #define MXC_F_ADC_REVB_CHSEL0_SLOT2_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL0_SLOT2_ID_POS)) /**< CHSEL0_SLOT2_ID Mask */ 265 266 #define MXC_F_ADC_REVB_CHSEL0_SLOT3_ID_POS 24 /**< CHSEL0_SLOT3_ID Position */ 267 #define MXC_F_ADC_REVB_CHSEL0_SLOT3_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL0_SLOT3_ID_POS)) /**< CHSEL0_SLOT3_ID Mask */ 268 269 /**@} end of group ADC_REVB_CHSEL0_Register */ 270 271 /** 272 * @ingroup adc_revb_registers 273 * @defgroup ADC_REVB_CHSEL1 ADC_REVB_CHSEL1 274 * @brief Channel Select Register 1. 275 * @{ 276 */ 277 #define MXC_F_ADC_REVB_CHSEL1_SLOT4_ID_POS 0 /**< CHSEL1_SLOT4_ID Position */ 278 #define MXC_F_ADC_REVB_CHSEL1_SLOT4_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL1_SLOT4_ID_POS)) /**< CHSEL1_SLOT4_ID Mask */ 279 280 #define MXC_F_ADC_REVB_CHSEL1_SLOT5_ID_POS 8 /**< CHSEL1_SLOT5_ID Position */ 281 #define MXC_F_ADC_REVB_CHSEL1_SLOT5_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL1_SLOT5_ID_POS)) /**< CHSEL1_SLOT5_ID Mask */ 282 283 #define MXC_F_ADC_REVB_CHSEL1_SLOT6_ID_POS 16 /**< CHSEL1_SLOT6_ID Position */ 284 #define MXC_F_ADC_REVB_CHSEL1_SLOT6_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL1_SLOT6_ID_POS)) /**< CHSEL1_SLOT6_ID Mask */ 285 286 #define MXC_F_ADC_REVB_CHSEL1_SLOT7_ID_POS 24 /**< CHSEL1_SLOT7_ID Position */ 287 #define MXC_F_ADC_REVB_CHSEL1_SLOT7_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL1_SLOT7_ID_POS)) /**< CHSEL1_SLOT7_ID Mask */ 288 289 /**@} end of group ADC_REVB_CHSEL1_Register */ 290 291 /** 292 * @ingroup adc_revb_registers 293 * @defgroup ADC_REVB_CHSEL2 ADC_REVB_CHSEL2 294 * @brief Channel Select Register 2. 295 * @{ 296 */ 297 #define MXC_F_ADC_REVB_CHSEL2_SLOT8_ID_POS 0 /**< CHSEL2_SLOT8_ID Position */ 298 #define MXC_F_ADC_REVB_CHSEL2_SLOT8_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL2_SLOT8_ID_POS)) /**< CHSEL2_SLOT8_ID Mask */ 299 300 #define MXC_F_ADC_REVB_CHSEL2_SLOT9_ID_POS 8 /**< CHSEL2_SLOT9_ID Position */ 301 #define MXC_F_ADC_REVB_CHSEL2_SLOT9_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL2_SLOT9_ID_POS)) /**< CHSEL2_SLOT9_ID Mask */ 302 303 #define MXC_F_ADC_REVB_CHSEL2_SLOT10_ID_POS 16 /**< CHSEL2_SLOT10_ID Position */ 304 #define MXC_F_ADC_REVB_CHSEL2_SLOT10_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL2_SLOT10_ID_POS)) /**< CHSEL2_SLOT10_ID Mask */ 305 306 #define MXC_F_ADC_REVB_CHSEL2_SLOT11_ID_POS 24 /**< CHSEL2_SLOT11_ID Position */ 307 #define MXC_F_ADC_REVB_CHSEL2_SLOT11_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL2_SLOT11_ID_POS)) /**< CHSEL2_SLOT11_ID Mask */ 308 309 /**@} end of group ADC_REVB_CHSEL2_Register */ 310 311 /** 312 * @ingroup adc_revb_registers 313 * @defgroup ADC_REVB_CHSEL3 ADC_REVB_CHSEL3 314 * @brief Channel Select Register 3. 315 * @{ 316 */ 317 #define MXC_F_ADC_REVB_CHSEL3_SLOT12_ID_POS 0 /**< CHSEL3_SLOT12_ID Position */ 318 #define MXC_F_ADC_REVB_CHSEL3_SLOT12_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL3_SLOT12_ID_POS)) /**< CHSEL3_SLOT12_ID Mask */ 319 320 #define MXC_F_ADC_REVB_CHSEL3_SLOT13_ID_POS 8 /**< CHSEL3_SLOT13_ID Position */ 321 #define MXC_F_ADC_REVB_CHSEL3_SLOT13_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL3_SLOT13_ID_POS)) /**< CHSEL3_SLOT13_ID Mask */ 322 323 #define MXC_F_ADC_REVB_CHSEL3_SLOT14_ID_POS 16 /**< CHSEL3_SLOT14_ID Position */ 324 #define MXC_F_ADC_REVB_CHSEL3_SLOT14_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL3_SLOT14_ID_POS)) /**< CHSEL3_SLOT14_ID Mask */ 325 326 #define MXC_F_ADC_REVB_CHSEL3_SLOT15_ID_POS 24 /**< CHSEL3_SLOT15_ID Position */ 327 #define MXC_F_ADC_REVB_CHSEL3_SLOT15_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL3_SLOT15_ID_POS)) /**< CHSEL3_SLOT15_ID Mask */ 328 329 /**@} end of group ADC_REVB_CHSEL3_Register */ 330 331 /** 332 * @ingroup adc_revb_registers 333 * @defgroup ADC_REVB_CHSEL4 ADC_REVB_CHSEL4 334 * @brief Channel Select Register 4. 335 * @{ 336 */ 337 #define MXC_F_ADC_REVB_CHSEL4_SLOT16_ID_POS 0 /**< CHSEL4_SLOT16_ID Position */ 338 #define MXC_F_ADC_REVB_CHSEL4_SLOT16_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL4_SLOT16_ID_POS)) /**< CHSEL4_SLOT16_ID Mask */ 339 340 #define MXC_F_ADC_REVB_CHSEL4_SLOT17_ID_POS 8 /**< CHSEL4_SLOT17_ID Position */ 341 #define MXC_F_ADC_REVB_CHSEL4_SLOT17_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL4_SLOT17_ID_POS)) /**< CHSEL4_SLOT17_ID Mask */ 342 343 #define MXC_F_ADC_REVB_CHSEL4_SLOT18_ID_POS 16 /**< CHSEL4_SLOT18_ID Position */ 344 #define MXC_F_ADC_REVB_CHSEL4_SLOT18_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL4_SLOT18_ID_POS)) /**< CHSEL4_SLOT18_ID Mask */ 345 346 #define MXC_F_ADC_REVB_CHSEL4_SLOT19_ID_POS 24 /**< CHSEL4_SLOT19_ID Position */ 347 #define MXC_F_ADC_REVB_CHSEL4_SLOT19_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL4_SLOT19_ID_POS)) /**< CHSEL4_SLOT19_ID Mask */ 348 349 /**@} end of group ADC_REVB_CHSEL4_Register */ 350 351 /** 352 * @ingroup adc_revb_registers 353 * @defgroup ADC_REVB_CHSEL5 ADC_REVB_CHSEL5 354 * @brief Channel Select Register 5. 355 * @{ 356 */ 357 #define MXC_F_ADC_REVB_CHSEL5_SLOT20_ID_POS 0 /**< CHSEL5_SLOT20_ID Position */ 358 #define MXC_F_ADC_REVB_CHSEL5_SLOT20_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL5_SLOT20_ID_POS)) /**< CHSEL5_SLOT20_ID Mask */ 359 360 #define MXC_F_ADC_REVB_CHSEL5_SLOT21_ID_POS 8 /**< CHSEL5_SLOT21_ID Position */ 361 #define MXC_F_ADC_REVB_CHSEL5_SLOT21_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL5_SLOT21_ID_POS)) /**< CHSEL5_SLOT21_ID Mask */ 362 363 #define MXC_F_ADC_REVB_CHSEL5_SLOT22_ID_POS 16 /**< CHSEL5_SLOT22_ID Position */ 364 #define MXC_F_ADC_REVB_CHSEL5_SLOT22_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL5_SLOT22_ID_POS)) /**< CHSEL5_SLOT22_ID Mask */ 365 366 #define MXC_F_ADC_REVB_CHSEL5_SLOT23_ID_POS 24 /**< CHSEL5_SLOT23_ID Position */ 367 #define MXC_F_ADC_REVB_CHSEL5_SLOT23_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL5_SLOT23_ID_POS)) /**< CHSEL5_SLOT23_ID Mask */ 368 369 /**@} end of group ADC_REVB_CHSEL5_Register */ 370 371 /** 372 * @ingroup adc_revb_registers 373 * @defgroup ADC_REVB_CHSEL6 ADC_REVB_CHSEL6 374 * @brief Channel Select Register 6. 375 * @{ 376 */ 377 #define MXC_F_ADC_REVB_CHSEL6_SLOT24_ID_POS 0 /**< CHSEL6_SLOT24_ID Position */ 378 #define MXC_F_ADC_REVB_CHSEL6_SLOT24_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL6_SLOT24_ID_POS)) /**< CHSEL6_SLOT24_ID Mask */ 379 380 #define MXC_F_ADC_REVB_CHSEL6_SLOT25_ID_POS 8 /**< CHSEL6_SLOT25_ID Position */ 381 #define MXC_F_ADC_REVB_CHSEL6_SLOT25_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL6_SLOT25_ID_POS)) /**< CHSEL6_SLOT25_ID Mask */ 382 383 #define MXC_F_ADC_REVB_CHSEL6_SLOT26_ID_POS 16 /**< CHSEL6_SLOT26_ID Position */ 384 #define MXC_F_ADC_REVB_CHSEL6_SLOT26_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL6_SLOT26_ID_POS)) /**< CHSEL6_SLOT26_ID Mask */ 385 386 #define MXC_F_ADC_REVB_CHSEL6_SLOT27_ID_POS 24 /**< CHSEL6_SLOT27_ID Position */ 387 #define MXC_F_ADC_REVB_CHSEL6_SLOT27_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL6_SLOT27_ID_POS)) /**< CHSEL6_SLOT27_ID Mask */ 388 389 /**@} end of group ADC_REVB_CHSEL6_Register */ 390 391 /** 392 * @ingroup adc_revb_registers 393 * @defgroup ADC_REVB_CHSEL7 ADC_REVB_CHSEL7 394 * @brief Channel Select Register 7. 395 * @{ 396 */ 397 #define MXC_F_ADC_REVB_CHSEL7_SLOT28_ID_POS 0 /**< CHSEL7_SLOT28_ID Position */ 398 #define MXC_F_ADC_REVB_CHSEL7_SLOT28_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL7_SLOT28_ID_POS)) /**< CHSEL7_SLOT28_ID Mask */ 399 400 #define MXC_F_ADC_REVB_CHSEL7_SLOT29_ID_POS 8 /**< CHSEL7_SLOT29_ID Position */ 401 #define MXC_F_ADC_REVB_CHSEL7_SLOT29_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL7_SLOT29_ID_POS)) /**< CHSEL7_SLOT29_ID Mask */ 402 403 #define MXC_F_ADC_REVB_CHSEL7_SLOT30_ID_POS 16 /**< CHSEL7_SLOT30_ID Position */ 404 #define MXC_F_ADC_REVB_CHSEL7_SLOT30_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL7_SLOT30_ID_POS)) /**< CHSEL7_SLOT30_ID Mask */ 405 406 #define MXC_F_ADC_REVB_CHSEL7_SLOT31_ID_POS 24 /**< CHSEL7_SLOT31_ID Position */ 407 #define MXC_F_ADC_REVB_CHSEL7_SLOT31_ID ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_CHSEL7_SLOT31_ID_POS)) /**< CHSEL7_SLOT31_ID Mask */ 408 409 /**@} end of group ADC_REVB_CHSEL7_Register */ 410 411 /** 412 * @ingroup adc_revb_registers 413 * @defgroup ADC_REVB_RESTART ADC_REVB_RESTART 414 * @brief Restart Count Control Register 415 * @{ 416 */ 417 #define MXC_F_ADC_REVB_RESTART_CNT_POS 0 /**< RESTART_CNT Position */ 418 #define MXC_F_ADC_REVB_RESTART_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_REVB_RESTART_CNT_POS)) /**< RESTART_CNT Mask */ 419 420 /**@} end of group ADC_REVB_RESTART_Register */ 421 422 /** 423 * @ingroup adc_revb_registers 424 * @defgroup ADC_REVB_DATAFMT ADC_REVB_DATAFMT 425 * @brief Channel Data Format Register 426 * @{ 427 */ 428 #define MXC_F_ADC_REVB_DATAFMT_MODE_POS 0 /**< DATAFMT_MODE Position */ 429 #define MXC_F_ADC_REVB_DATAFMT_MODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_REVB_DATAFMT_MODE_POS)) /**< DATAFMT_MODE Mask */ 430 431 /**@} end of group ADC_REVB_DATAFMT_Register */ 432 433 /** 434 * @ingroup adc_revb_registers 435 * @defgroup ADC_REVB_FIFODMACTRL ADC_REVB_FIFODMACTRL 436 * @brief FIFO and DMA control 437 * @{ 438 */ 439 #define MXC_F_ADC_REVB_FIFODMACTRL_DMA_EN_POS 0 /**< FIFODMACTRL_DMA_EN Position */ 440 #define MXC_F_ADC_REVB_FIFODMACTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVB_FIFODMACTRL_DMA_EN_POS)) /**< FIFODMACTRL_DMA_EN Mask */ 441 442 #define MXC_F_ADC_REVB_FIFODMACTRL_FLUSH_POS 1 /**< FIFODMACTRL_FLUSH Position */ 443 #define MXC_F_ADC_REVB_FIFODMACTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_ADC_REVB_FIFODMACTRL_FLUSH_POS)) /**< FIFODMACTRL_FLUSH Mask */ 444 445 #define MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT_POS 2 /**< FIFODMACTRL_DATA_FORMAT Position */ 446 #define MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT ((uint32_t)(0x3UL << MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT_POS)) /**< FIFODMACTRL_DATA_FORMAT Mask */ 447 #define MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_STATUS ((uint32_t)0x0UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Value */ 448 #define MXC_S_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_STATUS (MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_STATUS << MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Setting */ 449 #define MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_ONLY ((uint32_t)0x1UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Value */ 450 #define MXC_S_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_ONLY (MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_DATA_ONLY << MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Setting */ 451 #define MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY ((uint32_t)0x2UL) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Value */ 452 #define MXC_S_ADC_REVB_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY (MXC_V_ADC_REVB_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY << MXC_F_ADC_REVB_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Setting */ 453 454 #define MXC_F_ADC_REVB_FIFODMACTRL_THRESH_POS 8 /**< FIFODMACTRL_THRESH Position */ 455 #define MXC_F_ADC_REVB_FIFODMACTRL_THRESH ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_FIFODMACTRL_THRESH_POS)) /**< FIFODMACTRL_THRESH Mask */ 456 457 /**@} end of group ADC_REVB_FIFODMACTRL_Register */ 458 459 /** 460 * @ingroup adc_revb_registers 461 * @defgroup ADC_REVB_DATA ADC_REVB_DATA 462 * @brief Data Register (FIFO). 463 * @{ 464 */ 465 #define MXC_F_ADC_REVB_DATA_DATA_POS 0 /**< DATA_DATA Position */ 466 #define MXC_F_ADC_REVB_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */ 467 468 #define MXC_F_ADC_REVB_DATA_CHAN_POS 16 /**< DATA_CHAN Position */ 469 #define MXC_F_ADC_REVB_DATA_CHAN ((uint32_t)(0x1FUL << MXC_F_ADC_REVB_DATA_CHAN_POS)) /**< DATA_CHAN Mask */ 470 471 #define MXC_F_ADC_REVB_DATA_INVALID_POS 24 /**< DATA_INVALID Position */ 472 #define MXC_F_ADC_REVB_DATA_INVALID ((uint32_t)(0x1UL << MXC_F_ADC_REVB_DATA_INVALID_POS)) /**< DATA_INVALID Mask */ 473 474 #define MXC_F_ADC_REVB_DATA_CLIPPED_POS 31 /**< DATA_CLIPPED Position */ 475 #define MXC_F_ADC_REVB_DATA_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_REVB_DATA_CLIPPED_POS)) /**< DATA_CLIPPED Mask */ 476 477 /**@} end of group ADC_REVB_DATA_Register */ 478 479 /** 480 * @ingroup adc_revb_registers 481 * @defgroup ADC_REVB_STATUS ADC_REVB_STATUS 482 * @brief Status Register 483 * @{ 484 */ 485 #define MXC_F_ADC_REVB_STATUS_READY_POS 0 /**< STATUS_READY Position */ 486 #define MXC_F_ADC_REVB_STATUS_READY ((uint32_t)(0x1UL << MXC_F_ADC_REVB_STATUS_READY_POS)) /**< STATUS_READY Mask */ 487 488 #define MXC_F_ADC_REVB_STATUS_EMPTY_POS 1 /**< STATUS_EMPTY Position */ 489 #define MXC_F_ADC_REVB_STATUS_EMPTY ((uint32_t)(0x1UL << MXC_F_ADC_REVB_STATUS_EMPTY_POS)) /**< STATUS_EMPTY Mask */ 490 491 #define MXC_F_ADC_REVB_STATUS_FULL_POS 2 /**< STATUS_FULL Position */ 492 #define MXC_F_ADC_REVB_STATUS_FULL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_STATUS_FULL_POS)) /**< STATUS_FULL Mask */ 493 494 #define MXC_F_ADC_REVB_STATUS_FIFO_LEVEL_POS 8 /**< STATUS_FIFO_LEVEL Position */ 495 #define MXC_F_ADC_REVB_STATUS_FIFO_LEVEL ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_STATUS_FIFO_LEVEL_POS)) /**< STATUS_FIFO_LEVEL Mask */ 496 497 /**@} end of group ADC_REVB_STATUS_Register */ 498 499 /** 500 * @ingroup adc_revb_registers 501 * @defgroup ADC_REVB_CHSTATUS ADC_REVB_CHSTATUS 502 * @brief Channel Status 503 * @{ 504 */ 505 #define MXC_F_ADC_REVB_CHSTATUS_CLIPPED_POS 0 /**< CHSTATUS_CLIPPED Position */ 506 #define MXC_F_ADC_REVB_CHSTATUS_CLIPPED ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_REVB_CHSTATUS_CLIPPED_POS)) /**< CHSTATUS_CLIPPED Mask */ 507 508 /**@} end of group ADC_REVB_CHSTATUS_Register */ 509 510 /** 511 * @ingroup adc_revb_registers 512 * @defgroup ADC_REVB_INTEN ADC_REVB_INTEN 513 * @brief Interrupt Enable Register. 514 * @{ 515 */ 516 #define MXC_F_ADC_REVB_INTEN_READY_POS 0 /**< INTEN_READY Position */ 517 #define MXC_F_ADC_REVB_INTEN_READY ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_READY_POS)) /**< INTEN_READY Mask */ 518 519 #define MXC_F_ADC_REVB_INTEN_ABORT_POS 2 /**< INTEN_ABORT Position */ 520 #define MXC_F_ADC_REVB_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 521 522 #define MXC_F_ADC_REVB_INTEN_START_DET_POS 3 /**< INTEN_START_DET Position */ 523 #define MXC_F_ADC_REVB_INTEN_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_START_DET_POS)) /**< INTEN_START_DET Mask */ 524 525 #define MXC_F_ADC_REVB_INTEN_SEQ_STARTED_POS 4 /**< INTEN_SEQ_STARTED Position */ 526 #define MXC_F_ADC_REVB_INTEN_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_SEQ_STARTED_POS)) /**< INTEN_SEQ_STARTED Mask */ 527 528 #define MXC_F_ADC_REVB_INTEN_SEQ_DONE_POS 5 /**< INTEN_SEQ_DONE Position */ 529 #define MXC_F_ADC_REVB_INTEN_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_SEQ_DONE_POS)) /**< INTEN_SEQ_DONE Mask */ 530 531 #define MXC_F_ADC_REVB_INTEN_CONV_DONE_POS 6 /**< INTEN_CONV_DONE Position */ 532 #define MXC_F_ADC_REVB_INTEN_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_CONV_DONE_POS)) /**< INTEN_CONV_DONE Mask */ 533 534 #define MXC_F_ADC_REVB_INTEN_CLIPPED_POS 7 /**< INTEN_CLIPPED Position */ 535 #define MXC_F_ADC_REVB_INTEN_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_CLIPPED_POS)) /**< INTEN_CLIPPED Mask */ 536 537 #define MXC_F_ADC_REVB_INTEN_FIFO_LVL_POS 8 /**< INTEN_FIFO_LVL Position */ 538 #define MXC_F_ADC_REVB_INTEN_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_FIFO_LVL_POS)) /**< INTEN_FIFO_LVL Mask */ 539 540 #define MXC_F_ADC_REVB_INTEN_FIFO_UFL_POS 9 /**< INTEN_FIFO_UFL Position */ 541 #define MXC_F_ADC_REVB_INTEN_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_FIFO_UFL_POS)) /**< INTEN_FIFO_UFL Mask */ 542 543 #define MXC_F_ADC_REVB_INTEN_FIFO_OFL_POS 10 /**< INTEN_FIFO_OFL Position */ 544 #define MXC_F_ADC_REVB_INTEN_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTEN_FIFO_OFL_POS)) /**< INTEN_FIFO_OFL Mask */ 545 546 /**@} end of group ADC_REVB_INTEN_Register */ 547 548 /** 549 * @ingroup adc_revb_registers 550 * @defgroup ADC_REVB_INTFL ADC_REVB_INTFL 551 * @brief Interrupt Flags Register. 552 * @{ 553 */ 554 #define MXC_F_ADC_REVB_INTFL_READY_POS 0 /**< INTFL_READY Position */ 555 #define MXC_F_ADC_REVB_INTFL_READY ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_READY_POS)) /**< INTFL_READY Mask */ 556 557 #define MXC_F_ADC_REVB_INTFL_ABORT_POS 2 /**< INTFL_ABORT Position */ 558 #define MXC_F_ADC_REVB_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 559 560 #define MXC_F_ADC_REVB_INTFL_START_DET_POS 3 /**< INTFL_START_DET Position */ 561 #define MXC_F_ADC_REVB_INTFL_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_START_DET_POS)) /**< INTFL_START_DET Mask */ 562 563 #define MXC_F_ADC_REVB_INTFL_SEQ_STARTED_POS 4 /**< INTFL_SEQ_STARTED Position */ 564 #define MXC_F_ADC_REVB_INTFL_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_SEQ_STARTED_POS)) /**< INTFL_SEQ_STARTED Mask */ 565 566 #define MXC_F_ADC_REVB_INTFL_SEQ_DONE_POS 5 /**< INTFL_SEQ_DONE Position */ 567 #define MXC_F_ADC_REVB_INTFL_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_SEQ_DONE_POS)) /**< INTFL_SEQ_DONE Mask */ 568 569 #define MXC_F_ADC_REVB_INTFL_CONV_DONE_POS 6 /**< INTFL_CONV_DONE Position */ 570 #define MXC_F_ADC_REVB_INTFL_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_CONV_DONE_POS)) /**< INTFL_CONV_DONE Mask */ 571 572 #define MXC_F_ADC_REVB_INTFL_CLIPPED_POS 7 /**< INTFL_CLIPPED Position */ 573 #define MXC_F_ADC_REVB_INTFL_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_CLIPPED_POS)) /**< INTFL_CLIPPED Mask */ 574 575 #define MXC_F_ADC_REVB_INTFL_FIFO_LVL_POS 8 /**< INTFL_FIFO_LVL Position */ 576 #define MXC_F_ADC_REVB_INTFL_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_FIFO_LVL_POS)) /**< INTFL_FIFO_LVL Mask */ 577 578 #define MXC_F_ADC_REVB_INTFL_FIFO_UFL_POS 9 /**< INTFL_FIFO_UFL Position */ 579 #define MXC_F_ADC_REVB_INTFL_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_FIFO_UFL_POS)) /**< INTFL_FIFO_UFL Mask */ 580 581 #define MXC_F_ADC_REVB_INTFL_FIFO_OFL_POS 10 /**< INTFL_FIFO_OFL Position */ 582 #define MXC_F_ADC_REVB_INTFL_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_REVB_INTFL_FIFO_OFL_POS)) /**< INTFL_FIFO_OFL Mask */ 583 584 /**@} end of group ADC_REVB_INTFL_Register */ 585 586 /** 587 * @ingroup adc_revb_registers 588 * @defgroup ADC_REVB_SFRADDROFFSET ADC_REVB_SFRADDROFFSET 589 * @brief SFR Address Offset Register 590 * @{ 591 */ 592 #define MXC_F_ADC_REVB_SFRADDROFFSET_OFFSET_POS 0 /**< SFRADDROFFSET_OFFSET Position */ 593 #define MXC_F_ADC_REVB_SFRADDROFFSET_OFFSET ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_SFRADDROFFSET_OFFSET_POS)) /**< SFRADDROFFSET_OFFSET Mask */ 594 595 /**@} end of group ADC_REVB_SFRADDROFFSET_Register */ 596 597 /** 598 * @ingroup adc_revb_registers 599 * @defgroup ADC_REVB_SFRADDR ADC_REVB_SFRADDR 600 * @brief SFR Address Register 601 * @{ 602 */ 603 #define MXC_F_ADC_REVB_SFRADDR_ADDR_POS 0 /**< SFRADDR_ADDR Position */ 604 #define MXC_F_ADC_REVB_SFRADDR_ADDR ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_SFRADDR_ADDR_POS)) /**< SFRADDR_ADDR Mask */ 605 606 /**@} end of group ADC_REVB_SFRADDR_Register */ 607 608 /** 609 * @ingroup adc_revb_registers 610 * @defgroup ADC_REVB_SFRWRDATA ADC_REVB_SFRWRDATA 611 * @brief SFR Write Data Register 612 * @{ 613 */ 614 #define MXC_F_ADC_REVB_SFRWRDATA_DATA_POS 0 /**< SFRWRDATA_DATA Position */ 615 #define MXC_F_ADC_REVB_SFRWRDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_SFRWRDATA_DATA_POS)) /**< SFRWRDATA_DATA Mask */ 616 617 /**@} end of group ADC_REVB_SFRWRDATA_Register */ 618 619 /** 620 * @ingroup adc_revb_registers 621 * @defgroup ADC_REVB_SFRRDDATA ADC_REVB_SFRRDDATA 622 * @brief SFR Read Data Register 623 * @{ 624 */ 625 #define MXC_F_ADC_REVB_SFRRDDATA_DATA_POS 0 /**< SFRRDDATA_DATA Position */ 626 #define MXC_F_ADC_REVB_SFRRDDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_REVB_SFRRDDATA_DATA_POS)) /**< SFRRDDATA_DATA Mask */ 627 628 /**@} end of group ADC_REVB_SFRRDDATA_Register */ 629 630 /** 631 * @ingroup adc_revb_registers 632 * @defgroup ADC_REVB_SFRSTATUS ADC_REVB_SFRSTATUS 633 * @brief SFR Status Register 634 * @{ 635 */ 636 #define MXC_F_ADC_REVB_SFRSTATUS_NACK_POS 0 /**< SFRSTATUS_NACK Position */ 637 #define MXC_F_ADC_REVB_SFRSTATUS_NACK ((uint32_t)(0x1UL << MXC_F_ADC_REVB_SFRSTATUS_NACK_POS)) /**< SFRSTATUS_NACK Mask */ 638 639 /**@} end of group ADC_REVB_SFRSTATUS_Register */ 640 641 #ifdef __cplusplus 642 } 643 #endif 644 645 #endif /* _ADC_REVB_REGS_H_ */ 646
