1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "emcc_reva.h"
22
23 #if TARGET_NUM != 32650
24 #include "emcc.h"
MXC_EMCC_RevA_ID(mxc_emcc_reva_regs_t * emcc,mxc_emcc_info_t id)25 uint32_t MXC_EMCC_RevA_ID(mxc_emcc_reva_regs_t *emcc, mxc_emcc_info_t id)
26 {
27 switch (id) {
28 case EMCC_INFO_RELNUM:
29 return (((emcc->info) & MXC_F_EMCC_REVA_INFO_RELNUM)) >> MXC_F_EMCC_REVA_INFO_RELNUM_POS;
30
31 case EMCC_INFO_PARTNUM:
32 return (((emcc->info) & MXC_F_EMCC_REVA_INFO_PARTNUM)) >> MXC_F_EMCC_REVA_INFO_PARTNUM_POS;
33
34 case EMCC_INFO_ID:
35 default:
36 return (((emcc->info) & MXC_F_EMCC_REVA_INFO_ID)) >> MXC_F_EMCC_REVA_INFO_ID_POS;
37 }
38 }
39 #endif
40
MXC_EMCC_RevA_CacheSize(mxc_emcc_reva_regs_t * emcc)41 uint32_t MXC_EMCC_RevA_CacheSize(mxc_emcc_reva_regs_t *emcc)
42 {
43 return (((emcc->sz) & MXC_F_EMCC_REVA_SZ_CCH)) >> MXC_F_EMCC_REVA_SZ_CCH_POS;
44 }
45
MXC_EMCC_RevA_MemSize(mxc_emcc_reva_regs_t * emcc)46 uint32_t MXC_EMCC_RevA_MemSize(mxc_emcc_reva_regs_t *emcc)
47 {
48 return (emcc->sz & MXC_F_EMCC_REVA_SZ_MEM) >> MXC_F_EMCC_REVA_SZ_MEM_POS;
49 }
50
MXC_EMCC_RevA_Enable(mxc_emcc_reva_regs_t * emcc)51 void MXC_EMCC_RevA_Enable(mxc_emcc_reva_regs_t *emcc)
52 {
53 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_EN;
54 }
55
MXC_EMCC_RevA_Disable(mxc_emcc_reva_regs_t * emcc)56 void MXC_EMCC_RevA_Disable(mxc_emcc_reva_regs_t *emcc)
57 {
58 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_EN;
59 }
60
MXC_EMCC_RevA_WriteAllocateEnable(mxc_emcc_reva_regs_t * emcc)61 void MXC_EMCC_RevA_WriteAllocateEnable(mxc_emcc_reva_regs_t *emcc)
62 {
63 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_WRITE_ALLOC;
64 }
65
MXC_EMCC_RevA_WriteAllocateDisable(mxc_emcc_reva_regs_t * emcc)66 void MXC_EMCC_RevA_WriteAllocateDisable(mxc_emcc_reva_regs_t *emcc)
67 {
68 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_WRITE_ALLOC;
69 }
70
MXC_EMCC_RevA_CriticalWordFirstEnable(mxc_emcc_reva_regs_t * emcc)71 void MXC_EMCC_RevA_CriticalWordFirstEnable(mxc_emcc_reva_regs_t *emcc) //cwfst_dis
72 {
73 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_CWFST_DIS;
74 }
75
MXC_EMCC_RevA_CriticalWordFirstDisable(mxc_emcc_reva_regs_t * emcc)76 void MXC_EMCC_RevA_CriticalWordFirstDisable(mxc_emcc_reva_regs_t *emcc) //cwfst_dis
77 {
78 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_CWFST_DIS;
79 }
80
MXC_EMCC_RevA_Ready(mxc_emcc_reva_regs_t * emcc)81 uint32_t MXC_EMCC_RevA_Ready(mxc_emcc_reva_regs_t *emcc)
82 {
83 return (emcc->ctrl & MXC_F_EMCC_REVA_CTRL_RDY) >> MXC_F_EMCC_REVA_CTRL_RDY_POS;
84 }
85
