1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include <string.h>
23 #include "mxc_device.h"
24 #include "mxc_assert.h"
25 #include "mxc_pins.h"
26 #include "mxc_sys.h"
27 #include "csi2.h"
28 #include "csi2_reva.h"
29 #include "dma.h"
30 #include "dma_reva.h"
31 #include "mcr_regs.h"
32 #include "nvic_table.h"
33
34 /* **** Definitions **** */
35
36 /* **** Globals **** */
37
38 /* **** Functions **** */
39
40 /******************************************/
41 /* Global Control/Configuration Functions */
42 /******************************************/
43
MXC_CSI2_Init(mxc_csi2_req_t * req,mxc_csi2_ctrl_cfg_t * ctrl_cfg,mxc_csi2_vfifo_cfg_t * vfifo_cfg)44 int MXC_CSI2_Init(mxc_csi2_req_t *req, mxc_csi2_ctrl_cfg_t *ctrl_cfg,
45 mxc_csi2_vfifo_cfg_t *vfifo_cfg)
46 {
47 int error = E_NO_ERROR;
48 #ifdef __riscv
49 #warning "RISC-V Core does not have access to CSI2 IRQ. Drivers are not supported on RISC-V"
50 return E_NOT_SUPPORTED;
51 #else
52 error = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPLL);
53 if (error)
54 return error;
55
56 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CSI2);
57 if (error)
58 return error;
59
60 // Turn on LDO2P5
61 MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_2P5EN;
62
63 error = MXC_CSI2_RevA_Init((mxc_csi2_reva_regs_t *)MXC_CSI2, req, ctrl_cfg, vfifo_cfg);
64 if (error)
65 return error;
66
67 MXC_NVIC_SetVector(CSI2_IRQn, MXC_CSI2_RevA_Handler);
68 NVIC_EnableIRQ(CSI2_IRQn);
69 #endif
70 return error;
71 }
72
MXC_CSI2_Shutdown(void)73 int MXC_CSI2_Shutdown(void)
74 {
75 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CSI2);
76
77 return MXC_CSI2_RevA_Shutdown((mxc_csi2_reva_regs_t *)MXC_CSI2);
78 }
79
MXC_CSI2_Start(int num_data_lanes)80 int MXC_CSI2_Start(int num_data_lanes)
81 {
82 return MXC_CSI2_RevA_Start((mxc_csi2_reva_regs_t *)MXC_CSI2, num_data_lanes);
83 }
84
MXC_CSI2_Stop(void)85 int MXC_CSI2_Stop(void)
86 {
87 return MXC_CSI2_RevA_Stop((mxc_csi2_reva_regs_t *)MXC_CSI2);
88 }
89
MXC_CSI2_CaptureFrame(int num_data_lanes)90 int MXC_CSI2_CaptureFrame(int num_data_lanes)
91 {
92 return MXC_CSI2_RevA_CaptureFrameDMA(num_data_lanes);
93 }
94
MXC_CSI2_CaptureFrameDMA()95 int MXC_CSI2_CaptureFrameDMA()
96 {
97 return MXC_CSI2_RevA_CaptureFrameDMA();
98 }
99
MXC_CSI2_SetLaneCtrlSource(mxc_csi2_lane_src_t * src)100 int MXC_CSI2_SetLaneCtrlSource(mxc_csi2_lane_src_t *src)
101 {
102 return MXC_CSI2_RevA_SetLaneCtrlSource((mxc_csi2_reva_regs_t *)MXC_CSI2, src);
103 }
104
MXC_CSI2_GetLaneCtrlSource(mxc_csi2_lane_src_t * src)105 int MXC_CSI2_GetLaneCtrlSource(mxc_csi2_lane_src_t *src)
106 {
107 return MXC_CSI2_RevA_GetLaneCtrlSource((mxc_csi2_reva_regs_t *)MXC_CSI2, src);
108 }
109
MXC_CSI2_GetImageDetails(uint32_t * imgLen,uint32_t * w,uint32_t * h)110 void MXC_CSI2_GetImageDetails(uint32_t *imgLen, uint32_t *w, uint32_t *h)
111 {
112 MXC_CSI2_RevA_GetImageDetails(imgLen, w, h);
113 }
114
MXC_CSI2_Callback(mxc_csi2_req_t * req,int retVal)115 int MXC_CSI2_Callback(mxc_csi2_req_t *req, int retVal)
116 {
117 return MXC_CSI2_RevA_Callback(req, retVal);
118 }
119
120 // int MXC_CSI2_Handler(void)
121 // {
122 // return MXC_CSI2_RevA_Handler((mxc_csi2_reva_regs_t *)MXC_CSI2);
123 // }
124
125 /********************************/
126 /* CSI2 RX Controller Functions */
127 /********************************/
128
MXC_CSI2_CTRL_Config(mxc_csi2_ctrl_cfg_t * cfg)129 int MXC_CSI2_CTRL_Config(mxc_csi2_ctrl_cfg_t *cfg)
130 {
131 return MXC_CSI2_RevA_CTRL_Config((mxc_csi2_reva_regs_t *)MXC_CSI2, cfg);
132 }
133
MXC_CSI2_CTRL_EnableInt(uint32_t mask)134 void MXC_CSI2_CTRL_EnableInt(uint32_t mask)
135 {
136 MXC_CSI2_RevA_CTRL_EnableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask);
137 }
138
MXC_CSI2_CTRL_DisableInt(uint32_t mask)139 void MXC_CSI2_CTRL_DisableInt(uint32_t mask)
140 {
141 MXC_CSI2_RevA_CTRL_DisableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask);
142 }
143
MXC_CSI2_CTRL_GetFlags(void)144 int MXC_CSI2_CTRL_GetFlags(void)
145 {
146 return MXC_CSI2_RevA_CTRL_GetFlags((mxc_csi2_reva_regs_t *)MXC_CSI2);
147 }
148
MXC_CSI2_CTRL_ClearFlags(uint32_t flags)149 void MXC_CSI2_CTRL_ClearFlags(uint32_t flags)
150 {
151 MXC_CSI2_RevA_CTRL_ClearFlags((mxc_csi2_reva_regs_t *)MXC_CSI2, flags);
152 }
153
154 /*****************************************/
155 /* CSI2 VFIFO - Control/Config functions */
156 /*****************************************/
157
MXC_CSI2_VFIFO_Config(mxc_csi2_vfifo_cfg_t * cfg)158 int MXC_CSI2_VFIFO_Config(mxc_csi2_vfifo_cfg_t *cfg)
159 {
160 return MXC_CSI2_RevA_VFIFO_Config((mxc_csi2_reva_regs_t *)MXC_CSI2, cfg);
161 }
162
MXC_CSI2_VFIFO_ProcessRAWtoRGB(mxc_csi2_req_t * req)163 int MXC_CSI2_VFIFO_ProcessRAWtoRGB(mxc_csi2_req_t *req)
164 {
165 return MXC_CSI2_RevA_VFIFO_ProcessRAWtoRGB((mxc_csi2_reva_regs_t *)MXC_CSI2, req);
166 }
167
MXC_CSI2_VFIFO_NextFIFOTrigMode(uint8_t ff_not_empty,uint8_t ff_abv_thd,uint8_t ff_full)168 int MXC_CSI2_VFIFO_NextFIFOTrigMode(uint8_t ff_not_empty, uint8_t ff_abv_thd, uint8_t ff_full)
169 {
170 return MXC_CSI2_RevA_VFIFO_NextFIFOTrigMode((mxc_csi2_reva_regs_t *)MXC_CSI2, ff_not_empty,
171 ff_abv_thd, ff_full);
172 }
173
MXC_CSI2_VFIFO_EnableInt(uint32_t mask,uint32_t edge)174 void MXC_CSI2_VFIFO_EnableInt(uint32_t mask, uint32_t edge)
175 {
176 MXC_CSI2_RevA_VFIFO_EnableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask, edge);
177 }
178
MXC_CSI2_VFIFO_ChangeIntMode(uint32_t mask,uint32_t edge)179 void MXC_CSI2_VFIFO_ChangeIntMode(uint32_t mask, uint32_t edge)
180 {
181 MXC_CSI2_RevA_VFIFO_ChangeIntMode((mxc_csi2_reva_regs_t *)MXC_CSI2, mask, edge);
182 }
183
MXC_CSI2_VFIFO_DisableInt(uint32_t mask)184 void MXC_CSI2_VFIFO_DisableInt(uint32_t mask)
185 {
186 MXC_CSI2_RevA_VFIFO_DisableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask);
187 }
188
MXC_CSI2_VFIFO_GetFlags(void)189 int MXC_CSI2_VFIFO_GetFlags(void)
190 {
191 return MXC_CSI2_RevA_VFIFO_GetFlags((mxc_csi2_reva_regs_t *)MXC_CSI2);
192 }
193
MXC_CSI2_VFIFO_ClearFlags(uint32_t flags)194 void MXC_CSI2_VFIFO_ClearFlags(uint32_t flags)
195 {
196 MXC_CSI2_RevA_VFIFO_ClearFlags((mxc_csi2_reva_regs_t *)MXC_CSI2, flags);
197 }
198
MXC_CSI2_VFIFO_Enable(void)199 int MXC_CSI2_VFIFO_Enable(void)
200 {
201 return MXC_CSI2_RevA_VFIFO_Enable((mxc_csi2_reva_regs_t *)MXC_CSI2);
202 }
203
MXC_CSI2_VFIFO_Disable(void)204 int MXC_CSI2_VFIFO_Disable(void)
205 {
206 return MXC_CSI2_RevA_VFIFO_Disable((mxc_csi2_reva_regs_t *)MXC_CSI2);
207 }
208
MXC_CSI2_VFIFO_SetPayloadType(mxc_csi2_payload0_t payload0,mxc_csi2_payload1_t payload1)209 int MXC_CSI2_VFIFO_SetPayloadType(mxc_csi2_payload0_t payload0, mxc_csi2_payload1_t payload1)
210 {
211 return MXC_CSI2_RevA_VFIFO_SetPayloadType((mxc_csi2_reva_regs_t *)MXC_CSI2, payload0, payload1);
212 }
213
MXC_CSI2_VFIFO_GetPayloadType(uint32_t * payload0,uint32_t * payload1)214 int MXC_CSI2_VFIFO_GetPayloadType(uint32_t *payload0, uint32_t *payload1)
215 {
216 return MXC_CSI2_RevA_VFIFO_GetPayloadType((mxc_csi2_reva_regs_t *)MXC_CSI2, payload0, payload1);
217 }
218
MXC_CSI2_VFIFO_SetDMAMode(mxc_csi2_dma_mode_t dma_mode)219 int MXC_CSI2_VFIFO_SetDMAMode(mxc_csi2_dma_mode_t dma_mode)
220 {
221 return MXC_CSI2_RevA_VFIFO_SetDMAMode((mxc_csi2_reva_regs_t *)MXC_CSI2, dma_mode);
222 }
223
MXC_CSI2_VFIFO_GetDMAMode(void)224 mxc_csi2_dma_mode_t MXC_CSI2_VFIFO_GetDMAMode(void)
225 {
226 return MXC_CSI2_RevA_VFIFO_GetDMAMode((mxc_csi2_reva_regs_t *)MXC_CSI2);
227 }
228
MXC_CSI2_VFIFO_SetRGBType(mxc_csi2_rgb_type_t rgb_type)229 int MXC_CSI2_VFIFO_SetRGBType(mxc_csi2_rgb_type_t rgb_type)
230 {
231 return MXC_CSI2_RevA_VFIFO_SetRGBType((mxc_csi2_reva_regs_t *)MXC_CSI2, rgb_type);
232 }
233
MXC_CSI2_VFIFO_GetRGBType(void)234 mxc_csi2_rgb_type_t MXC_CSI2_VFIFO_GetRGBType(void)
235 {
236 return MXC_CSI2_RevA_VFIFO_GetRGBType((mxc_csi2_reva_regs_t *)MXC_CSI2);
237 }
238
MXC_CSI2_VFIFO_SetRAWFormat(mxc_csi2_raw_format_t raw_format)239 int MXC_CSI2_VFIFO_SetRAWFormat(mxc_csi2_raw_format_t raw_format)
240 {
241 return MXC_CSI2_RevA_VFIFO_SetRAWFormat((mxc_csi2_reva_regs_t *)MXC_CSI2, raw_format);
242 }
243
MXC_CSI2_VFIFO_GetRAWFormat(void)244 mxc_csi2_raw_format_t MXC_CSI2_VFIFO_GetRAWFormat(void)
245 {
246 return MXC_CSI2_RevA_VFIFO_GetRAWFormat((mxc_csi2_reva_regs_t *)MXC_CSI2);
247 }
248
MXC_CSI2_VFIFO_GetFIFOEntityCount(void)249 int MXC_CSI2_VFIFO_GetFIFOEntityCount(void)
250 {
251 return MXC_CSI2_RevA_VFIFO_GetFIFOEntityCount((mxc_csi2_reva_regs_t *)MXC_CSI2);
252 }
253
MXC_CSI2_VFIFO_SetAHBWait(mxc_csi2_ahbwait_t wait_en)254 void MXC_CSI2_VFIFO_SetAHBWait(mxc_csi2_ahbwait_t wait_en)
255 {
256 MXC_CSI2_RevA_VFIFO_SetAHBWait((mxc_csi2_reva_regs_t *)MXC_CSI2, wait_en);
257 }
258
MXC_CSI2_VFIFO_GetAHBWait(void)259 mxc_csi2_ahbwait_t MXC_CSI2_VFIFO_GetAHBWait(void)
260 {
261 return MXC_CSI2_RevA_VFIFO_GetAHBWait((mxc_csi2_reva_regs_t *)MXC_CSI2);
262 }
263
264 /***********************************************/
265 /* CSI2 PHY Protocol Interface (PPI) Functions */
266 /***********************************************/
267
MXC_CSI2_PPI_EnableInt(uint32_t mask)268 void MXC_CSI2_PPI_EnableInt(uint32_t mask)
269 {
270 MXC_CSI2_RevA_PPI_EnableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask);
271 }
272
MXC_CSI2_PPI_DisableInt(uint32_t mask)273 void MXC_CSI2_PPI_DisableInt(uint32_t mask)
274 {
275 MXC_CSI2_RevA_PPI_DisableInt((mxc_csi2_reva_regs_t *)MXC_CSI2, mask);
276 }
277
MXC_CSI2_PPI_GetFlags(void)278 int MXC_CSI2_PPI_GetFlags(void)
279 {
280 return MXC_CSI2_RevA_PPI_GetFlags((mxc_csi2_reva_regs_t *)MXC_CSI2);
281 }
282
MXC_CSI2_PPI_ClearFlags(uint32_t flags)283 void MXC_CSI2_PPI_ClearFlags(uint32_t flags)
284 {
285 MXC_CSI2_RevA_PPI_ClearFlags((mxc_csi2_reva_regs_t *)MXC_CSI2, flags);
286 }
287
MXC_CSI2_PPI_Stop(void)288 int MXC_CSI2_PPI_Stop(void)
289 {
290 return MXC_CSI2_RevA_PPI_Stop();
291 }
292
293 /************************************/
294 /* CSI2 DMA - Used for all features */
295 /************************************/
296
MXC_CSI2_DMA_Frame_Complete(void)297 bool MXC_CSI2_DMA_Frame_Complete(void)
298 {
299 return MXC_CSI2_RevA_DMA_Frame_Complete();
300 }
301
MXC_CSI2_GetCaptureStats()302 mxc_csi2_capture_stats_t MXC_CSI2_GetCaptureStats()
303 {
304 mxc_csi2_reva_capture_stats_t stats = MXC_CSI2_RevA_DMA_GetCaptureStats();
305 mxc_csi2_capture_stats_t ret = { .success = stats.success,
306 .ctrl_err = stats.ctrl_err,
307 .ppi_err = stats.ppi_err,
308 .vfifo_err = stats.vfifo_err,
309 .frame_size = stats.frame_size,
310 .bytes_captured = stats.bytes_captured };
311 return ret;
312 }
313
MXC_CSI2_DMA_Config(uint8_t * dst_addr,uint32_t byte_cnt,uint32_t burst_size)314 int MXC_CSI2_DMA_Config(uint8_t *dst_addr, uint32_t byte_cnt, uint32_t burst_size)
315 {
316 return MXC_CSI2_RevA_DMA_Config(dst_addr, byte_cnt, burst_size);
317 }
318
MXC_CSI2_DMA_GetChannel(void)319 int MXC_CSI2_DMA_GetChannel(void)
320 {
321 return MXC_CSI2_RevA_DMA_GetChannel();
322 }
323
MXC_CSI2_DMA_GetCurrentLineCnt(void)324 int MXC_CSI2_DMA_GetCurrentLineCnt(void)
325 {
326 return MXC_CSI2_RevA_DMA_GetCurrentLineCnt();
327 }
328
MXC_CSI2_DMA_GetCurrentFrameEndCnt(void)329 int MXC_CSI2_DMA_GetCurrentFrameEndCnt(void)
330 {
331 return MXC_CSI2_RevA_DMA_GetCurrentFrameEndCnt();
332 }
333
MXC_CSI2_DMA_Callback(int a,int b)334 void MXC_CSI2_DMA_Callback(int a, int b)
335 {
336 MXC_CSI2_RevA_DMA_Callback((mxc_dma_reva_regs_t *)MXC_DMA, a, b);
337 }
338
339 /**@} end of group csi2 */
340