1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ 23 24 #ifndef TARGET_NUM 25 #define TARGET_NUM 32665 26 #endif 27 28 #define MXC_NUMCORES 2 29 30 #include <stdint.h> 31 32 #ifndef FALSE 33 #define FALSE (0) 34 #endif 35 36 #ifndef TRUE 37 #define TRUE (1) 38 #endif 39 40 #if !defined(__GNUC__) 41 #define CMSIS_VECTAB_VIRTUAL 42 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" 43 #endif 44 45 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 46 #if defined(__GNUC__) 47 48 #ifndef __weak 49 #define __weak __attribute__((weak)) 50 #endif 51 52 #elif defined(__CC_ARM) 53 54 #define inline __inline 55 #pragma anon_unions 56 57 #endif 58 59 typedef enum { 60 NonMaskableInt_IRQn = -14, 61 HardFault_IRQn = -13, 62 MemoryManagement_IRQn = -12, 63 BusFault_IRQn = -11, 64 UsageFault_IRQn = -10, 65 SVCall_IRQn = -5, 66 DebugMonitor_IRQn = -4, 67 PendSV_IRQn = -2, 68 SysTick_IRQn = -1, 69 70 /* Device-specific interrupt sources (external to ARM core) */ 71 /* table entry number */ 72 /* |||| */ 73 /* |||| table offset address */ 74 /* vvvv vvvvvv */ 75 76 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 77 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 78 USB_IRQn, /* 0x12 0x0048 18: USB */ 79 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 80 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 81 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 82 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 83 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 84 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/ 85 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4*/ 86 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ 87 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 88 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 89 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 90 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 91 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 92 SPI1_IRQn, /* 0x20 0x0080 32: SPI1 */ 93 SPI2_IRQn, /* 0x21 0x0084 33: SPI2 */ 94 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 95 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 96 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 97 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 98 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ 99 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ 100 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 101 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 102 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ 103 TPU_IRQn, /* 0x2B 0x00AC 43: Crypto */ 104 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 105 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 106 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 107 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 108 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 109 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 110 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 111 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 112 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 113 RSV36_IRQn, /* 0x35 0x00D4 53: Reserved */ 114 SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */ 115 BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */ 116 BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */ 117 BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */ 118 BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */ 119 BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ 120 BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/ 121 BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */ 122 BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */ 123 BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */ 124 BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ 125 BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */ 126 BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */ 127 BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/ 128 BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */ 129 WUT_IRQn, /* 0x45 0x0114 69: WUT Wakeup */ 130 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 131 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 132 SPI0_IRQn, /* 0x48 0x0120 72: SPI0 AHB*/ 133 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ 134 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 135 PT_IRQn, /* 0x4B 0x012C 75: Pulse train */ 136 SDMA_IRQn, /* 0x4C 0x0130 76: Smart DMA 0 */ 137 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 138 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ 139 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ 140 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 141 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 142 SDHC_IRQn, /* 0x52 0x0148 82: SDIO/SDHC */ 143 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */ 144 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ 145 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ 146 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ 147 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ 148 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ 149 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ 150 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ 151 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ 152 DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ 153 DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ 154 DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ 155 DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ 156 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */ 157 WDT2_IRQn, /* 0x61 0x0184 97: Watchdog Timer 2 */ 158 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ 159 DVS_IRQn, /* 0x63 0x018C 99: DVS Controller */ 160 SIMO_IRQn, /* 0x64 0x0190 100: SIMO Controller */ 161 SCA_IRQn, /* 0x65 0x0194 101: SCA */ 162 AUDIO_IRQn, /* 0x66 0x0198 102: Audio subsystem */ 163 FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */ 164 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ 165 UART4_IRQn, /* 0x69 0x01A4 105: UART 4 */ 166 UART5_IRQn, /* 0x6A 0x01A8 106: UART 5 */ 167 CameraIF_IRQn, /* 0x6B 0x01AC 107: Camera IF */ 168 I3C_IRQn, /* 0x6C 0x01B0 108: I3C */ 169 HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */ 170 HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */ 171 MXC_IRQ_EXT_COUNT 172 } IRQn_Type; 173 174 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 175 176 /* ================================================================================ */ 177 /* ================ Processor and Core Peripheral Section ================ */ 178 /* ================================================================================ */ 179 180 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 181 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 182 #define __MPU_PRESENT 1 /*!< MPU present or not */ 183 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 184 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 185 #define __FPU_PRESENT 1 /*!< FPU present or not */ 186 187 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 188 189 #include "system_max32665.h" /*!< System Header */ 190 191 /* ================================================================================ */ 192 /* ================== Device Specific Memory Section ================== */ 193 /* ================================================================================ */ 194 195 #define MXC_ROM_MEM_BASE 0x00000000UL 196 #define MXC_ROM_MEM_SIZE 0x00020000UL 197 #define MXC_XIP_MEM_BASE 0x08000000UL 198 #define MXC_XIP_MEM_SIZE 0x08000000UL 199 #define MXC_FLASH0_MEM_BASE 0x10000000UL 200 #define MXC_FLASH1_MEM_BASE 0x10080000UL 201 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 202 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 203 #define MXC_FLASH_MEM_SIZE 0x00080000UL 204 #define MXC_INFO0_MEM_BASE 0x10800000UL 205 #define MXC_INFO1_MEM_BASE 0x10804000UL 206 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 207 #define MXC_INFO_MEM_SIZE 0x00004000UL 208 #define MXC_SRAM_MEM_BASE 0x20000000UL 209 #define MXC_SRAM_MEM_SIZE 0x0008C000UL 210 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL 211 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL 212 213 /* ================================================================================ */ 214 /* ================ Device Specific Peripheral Section ================ */ 215 /* ================================================================================ */ 216 217 /* 218 Base addresses and configuration settings for all MAX32665 peripheral modules. 219 */ 220 221 /******************************************************************************/ 222 /* Global control */ 223 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 224 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 225 226 /******************************************************************************/ 227 /* Non-battery backed SI Registers */ 228 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 229 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 230 231 /******************************************************************************/ 232 /* Non-battery backed Function Control */ 233 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 234 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 235 236 /******************************************************************************/ 237 /* Trust Protection Unit */ 238 #define MXC_BASE_TPU ((uint32_t)0x40001000UL) 239 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) 240 241 /******************************************************************************/ 242 /* RPU */ 243 #define MXC_BASE_RPU ((uint32_t)0x40002000UL) 244 #define MXC_RPU ((mxc_rpu_regs_t *)MXC_BASE_RPU) 245 #define MXC_RPU_NUM_BUS_MASTERS 9 246 247 /******************************************************************************/ 248 /* Watchdog */ 249 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 250 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 251 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) 252 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 253 #define MXC_BASE_WDT2 ((uint32_t)0x40003800UL) 254 #define MXC_WDT2 ((mxc_wdt_regs_t *)MXC_BASE_WDT2) 255 256 /******************************************************************************/ 257 /* Security Monitor */ 258 #define MXC_BASE_SMON ((uint32_t)0x40004000UL) 259 #define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON) 260 261 /******************************************************************************/ 262 /* SIMO */ 263 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL) 264 #define MXC_SIMO ((mxc_simo_regs_t *)MXC_BASE_SIMO) 265 266 /******************************************************************************/ 267 /* DVS */ 268 #define MXC_BASE_DVS ((uint32_t)0x40004800UL) 269 #define MXC_DVS ((mxc_dvs_regs_t *)MXC_BASE_DVS) 270 271 /******************************************************************************/ 272 /* AES Keys */ 273 #define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL) 274 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 275 276 // DEPRECATED(1-10-2023): Scheduled for removal. 277 #define MXC_BASE_AESKEY MXC_BASE_AESKEYS 278 #define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY) 279 280 /******************************************************************************/ 281 /* Trim System Initalization Register */ 282 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) 283 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 284 285 /******************************************************************************/ 286 /* Real Time Clock */ 287 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 288 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 289 290 /******************************************************************************/ 291 /* Wakeup Timer */ 292 #define MXC_BASE_WUT ((uint32_t)0x40006400UL) 293 #define MXC_WUT ((mxc_wut_regs_t *)MXC_BASE_WUT) 294 295 /******************************************************************************/ 296 /* Power Sequencer */ 297 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 298 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 299 /******************************************************************************/ 300 /* Power Sequencer */ 301 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 302 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 303 304 /******************************************************************************/ 305 /* GPIO */ 306 #define MXC_CFG_GPIO_INSTANCES (2) 307 #define MXC_CFG_GPIO_PINS_PORT (32) 308 309 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 310 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 311 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 312 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 313 314 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1) 315 316 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) 317 318 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : (IRQn_Type)0) 319 320 /******************************************************************************/ 321 /* Timer */ 322 #define MXC_CFG_TMR_INSTANCES (6) 323 324 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 325 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 326 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 327 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 328 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 329 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 330 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 331 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 332 #define MXC_BASE_TMR4 ((uint32_t)0x40014000UL) 333 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 334 #define MXC_BASE_TMR5 ((uint32_t)0x40015000UL) 335 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 336 337 #define MXC_TMR_GET_IRQ(i) \ 338 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 339 (i) == 1 ? TMR1_IRQn : \ 340 (i) == 2 ? TMR2_IRQn : \ 341 (i) == 3 ? TMR3_IRQn : \ 342 (i) == 4 ? TMR4_IRQn : \ 343 (i) == 5 ? TMR5_IRQn : \ 344 0) 345 346 #define MXC_TMR_GET_BASE(i) \ 347 ((i) == 0 ? MXC_BASE_TMR0 : \ 348 (i) == 1 ? MXC_BASE_TMR1 : \ 349 (i) == 2 ? MXC_BASE_TMR2 : \ 350 (i) == 3 ? MXC_BASE_TMR3 : \ 351 (i) == 4 ? MXC_BASE_TMR4 : \ 352 (i) == 5 ? MXC_BASE_TMR5 : \ 353 0) 354 355 #define MXC_TMR_GET_TMR(i) \ 356 ((i) == 0 ? MXC_TMR0 : \ 357 (i) == 1 ? MXC_TMR1 : \ 358 (i) == 2 ? MXC_TMR2 : \ 359 (i) == 3 ? MXC_TMR3 : \ 360 (i) == 4 ? MXC_TMR4 : \ 361 (i) == 5 ? MXC_TMR5 : \ 362 0) 363 364 #define MXC_TMR_GET_IDX(p) \ 365 ((p) == MXC_TMR0 ? 0 : \ 366 (p) == MXC_TMR1 ? 1 : \ 367 (p) == MXC_TMR2 ? 2 : \ 368 (p) == MXC_TMR3 ? 3 : \ 369 (p) == MXC_TMR4 ? 4 : \ 370 (p) == MXC_TMR5 ? 5 : \ 371 -1) 372 373 /******************************************************************************/ 374 /* High Speed Timer */ 375 #define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL) 376 #define MXC_HTMR0 ((mxc_htmr_regs_t *)MXC_BASE_HTMR0) 377 #define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL) 378 #define MXC_HTMR1 ((mxc_htmr_regs_t *)MXC_BASE_HTMR1) 379 380 /******************************************************************************/ 381 /* I2C */ 382 #define MXC_I2C_INSTANCES (3) 383 384 #define MXC_BASE_I2C0_BUS0 ((uint32_t)0x4001D000UL) 385 #define MXC_I2C0_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0_BUS0) 386 #define MXC_BASE_I2C1_BUS0 ((uint32_t)0x4001E000UL) 387 #define MXC_I2C1_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C1_BUS0) 388 #define MXC_BASE_I2C2_BUS0 ((uint32_t)0x4001F000UL) 389 #define MXC_I2C2_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C2_BUS0) 390 391 #define MXC_BASE_I2C0_BUS1 ((uint32_t)0x4011D000UL) 392 #define MXC_I2C0_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C0_BUS1) 393 #define MXC_BASE_I2C1_BUS1 ((uint32_t)0x4011E000UL) 394 #define MXC_I2C1_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1_BUS1) 395 #define MXC_BASE_I2C2_BUS1 ((uint32_t)0x4011F000UL) 396 #define MXC_I2C2_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C2_BUS1) 397 398 #define MXC_I2C_GET_IRQ(i) \ 399 (IRQn_Type)((i) == 0x0 ? I2C0_IRQn : \ 400 (i) == 0x1 ? I2C1_IRQn : \ 401 (i) == 0x2 ? I2C2_IRQn : \ 402 (i) == 0x8000 ? I2C0_IRQn : \ 403 (i) == 0x8001 ? I2C1_IRQn : \ 404 (i) == 0x8002 ? I2C2_IRQn : \ 405 0) 406 407 #define MXC_I2C_GET_BASE(i) \ 408 ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 : \ 409 (i) == 0x1 ? MXC_BASE_I2C1_BUS0 : \ 410 (i) == 0x2 ? MXC_BASE_I2C2_BUS0 : \ 411 (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 : \ 412 (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 : \ 413 (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : \ 414 0) 415 416 #define MXC_I2C_GET_IDX(p) \ 417 ((p) == MXC_I2C0_BUS0 ? 0x0 : \ 418 (p) == MXC_I2C1_BUS0 ? 0x1 : \ 419 (p) == MXC_I2C2_BUS0 ? 0x2 : \ 420 (p) == MXC_I2C0_BUS1 ? 0x8000 : \ 421 (p) == MXC_I2C1_BUS1 ? 0x8001 : \ 422 (p) == MXC_I2C2_BUS1 ? 0x8002 : \ 423 -1) 424 425 #define MXC_I2C_GET_I2C(p) \ 426 ((p) == 0x0 ? MXC_I2C0_BUS0 : \ 427 (p) == 0x1 ? MXC_I2C1_BUS0 : \ 428 (p) == 0x2 ? MXC_I2C2_BUS0 : \ 429 (p) == 0x8000 ? MXC_I2C0_BUS1 : \ 430 (p) == 0x8001 ? MXC_I2C1_BUS1 : \ 431 (p) == 0x8002 ? MXC_I2C2_BUS1 : \ 432 0) 433 #define MXC_I2C_FIFO_DEPTH (8) 434 435 /******************************************************************************/ 436 /* SPI Execute in Place */ 437 #define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL) 438 #define MXC_SPIXFM ((mxc_spixfm_regs_t *)MXC_BASE_SPIXFM) 439 440 #define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL) 441 #define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO) 442 /******************************************************************************/ 443 /* SPI Execute in Place Master */ 444 445 #define MXC_CFG_SPIXFC_FIFO_DEPTH (16) 446 447 #define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL) 448 #define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC) 449 450 /******************************************************************************/ 451 /* DMA */ 452 #define MXC_DMA_CHANNELS (16) 453 #define MXC_DMA_INSTANCES (2) 454 #define MXC_DMA_CH_OFFSET (8) 455 456 #define MXC_BASE_DMA0 ((uint32_t)0x40028000UL) 457 #define MXC_DMA0 ((mxc_dma_regs_t *)MXC_BASE_DMA0) 458 #define MXC_BASE_DMA1 ((uint32_t)0x40035000UL) 459 #define MXC_DMA1 ((mxc_dma_regs_t *)MXC_BASE_DMA1) 460 461 #define MXC_DMA_GET_BASE(i) ((i) == 0 ? MXC_BASE_DMA0 : (i) == 1 ? MXC_BASE_DMA1 : 0) 462 463 #define MXC_DMA_GET_DMA(i) ((i) == 0 ? MXC_DMA0 : (i) == 1 ? MXC_DMA1 : 0) 464 465 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) 466 467 #define MXC_DMA0_CH_GET_IRQ(i) \ 468 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 469 ((i) == 1) ? DMA1_IRQn : \ 470 ((i) == 2) ? DMA2_IRQn : \ 471 ((i) == 3) ? DMA3_IRQn : \ 472 ((i) == 4) ? DMA4_IRQn : \ 473 ((i) == 5) ? DMA5_IRQn : \ 474 ((i) == 6) ? DMA6_IRQn : \ 475 ((i) == 7) ? DMA7_IRQn : \ 476 0)) 477 478 #define MXC_DMA1_CH_GET_IRQ(i) \ 479 ((IRQn_Type)(((i) == 0) ? DMA8_IRQn : \ 480 ((i) == 1) ? DMA9_IRQn : \ 481 ((i) == 2) ? DMA10_IRQn : \ 482 ((i) == 3) ? DMA11_IRQn : \ 483 ((i) == 4) ? DMA12_IRQn : \ 484 ((i) == 5) ? DMA13_IRQn : \ 485 ((i) == 6) ? DMA14_IRQn : \ 486 ((i) == 7) ? DMA15_IRQn : \ 487 0)) 488 489 #define MXC_DMA_CH_GET_IRQ(i) \ 490 (((i) > (MXC_DMA_CH_OFFSET - 1)) ? MXC_DMA1_CH_GET_IRQ(i % MXC_DMA_CH_OFFSET) : \ 491 MXC_DMA0_CH_GET_IRQ(i)) 492 493 /* Create alias for MXC_DMA0 for backwards compatibility with code that was 494 written for parts that only had one DMA instance. */ 495 #define MXC_DMA MXC_DMA0 496 497 /******************************************************************************/ 498 /* FLC */ 499 #define MXC_FLC_INSTANCES (2) 500 501 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) 502 #define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) 503 #define MXC_BASE_FLC1 ((uint32_t)0x40029400UL) 504 #define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1) 505 506 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : (i) == 1 ? FLC1_IRQn : 0) 507 508 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0) 509 510 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0) 511 512 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1) 513 514 /******************************************************************************/ 515 /* Instruction Cache */ 516 #define MXC_ICC_INSTANCES (2) 517 518 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL) 519 #define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0) 520 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL) 521 #define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1) 522 523 #define MXC_ICC MXC_ICC0 524 525 #define MXC_ICC_GET_BASE(i) ((i) == 0 ? MXC_BASE_ICC0 : (i) == 1 ? MXC_BASE_ICC1 : 0) 526 527 #define MXC_ICC_GET_ICC(i) ((i) == 0 ? MXC_ICC0 : (i) == 1 ? MXC_ICC1 : 0) 528 529 #define MXC_ICC_GET_IDX(p) ((p) == MXC_ICC0 ? 0 : (p) == MXC_ICC1 ? 1 : -1) 530 531 /******************************************************************************/ 532 /* Instruction Cache XIP */ 533 #define MXC_BASE_SFCC ((uint32_t)0x4002F000UL) 534 #define MXC_SFCC ((mxc_icc_regs_t *)MXC_BASE_SFCC) 535 536 /******************************************************************************/ 537 /* Data Cache */ 538 #define MXC_BASE_SRCC ((uint32_t)0x40033000UL) 539 #define MXC_SRCC ((mxc_srcc_regs_t *)MXC_BASE_SRCC) 540 541 /******************************************************************************/ 542 /* ADC */ 543 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 544 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 545 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz 546 547 /******************************************************************************/ 548 /* Smart DMA */ 549 #define MXC_BASE_SDMA ((uint32_t)0x40036000UL) 550 #define MXC_SDMA ((mxc_sdma_regs_t *)MXC_BASE_SDMA) 551 552 /******************************************************************************/ 553 /* SPI XIP Data */ 554 #define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL) 555 #define MXC_SPIXR ((mxc_spixr_regs_t *)MXC_BASE_SPIXR) 556 557 /*******************************************************************************/ 558 /* Pulse Train Generation */ 559 #define MXC_CFG_PT_INSTANCES (16) 560 561 #define MXC_BASE_PTG_BUS0 ((uint32_t)0x4003C000UL) 562 #define MXC_PTG_BUS0 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0) 563 #define MXC_BASE_PT0_BUS0 ((uint32_t)0x4003C020UL) 564 #define MXC_PT0_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0) 565 #define MXC_BASE_PT1_BUS0 ((uint32_t)0x4003C040UL) 566 #define MXC_PT1_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0) 567 #define MXC_BASE_PT2_BUS0 ((uint32_t)0x4003C060UL) 568 #define MXC_PT2_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0) 569 #define MXC_BASE_PT3_BUS0 ((uint32_t)0x4003C080UL) 570 #define MXC_PT3_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0) 571 #define MXC_BASE_PT4_BUS0 ((uint32_t)0x4003C0A0UL) 572 #define MXC_PT4_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0) 573 #define MXC_BASE_PT5_BUS0 ((uint32_t)0x4003C0C0UL) 574 #define MXC_PT5_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0) 575 #define MXC_BASE_PT6_BUS0 ((uint32_t)0x4003C0E0UL) 576 #define MXC_PT6_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0) 577 #define MXC_BASE_PT7_BUS0 ((uint32_t)0x4003C100UL) 578 #define MXC_PT7_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0) 579 #define MXC_BASE_PT8_BUS0 ((uint32_t)0x4003C120UL) 580 #define MXC_PT8_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0) 581 #define MXC_BASE_PT9_BUS0 ((uint32_t)0x4003C140UL) 582 #define MXC_PT9_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0) 583 #define MXC_BASE_PT10_BUS0 ((uint32_t)0x4003C160UL) 584 #define MXC_PT10_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0) 585 #define MXC_BASE_PT11_BUS0 ((uint32_t)0x4003C180UL) 586 #define MXC_PT11_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0) 587 #define MXC_BASE_PT12_BUS0 ((uint32_t)0x4003C1A0UL) 588 #define MXC_PT12_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0) 589 #define MXC_BASE_PT13_BUS0 ((uint32_t)0x4003C1C0UL) 590 #define MXC_PT13_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0) 591 #define MXC_BASE_PT14_BUS0 ((uint32_t)0x4003C1E0UL) 592 #define MXC_PT14_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0) 593 #define MXC_BASE_PT15_BUS0 ((uint32_t)0x4003C200UL) 594 #define MXC_PT15_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0) 595 596 #define MXC_BASE_PTG_BUS1 ((uint32_t)0x4013C000UL) 597 #define MXC_PTG_BUS1 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1) 598 #define MXC_BASE_PT0_BUS1 ((uint32_t)0x4013C020UL) 599 #define MXC_PT0_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1) 600 #define MXC_BASE_PT1_BUS1 ((uint32_t)0x4013C040UL) 601 #define MXC_PT1_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1) 602 #define MXC_BASE_PT2_BUS1 ((uint32_t)0x4013C060UL) 603 #define MXC_PT2_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1) 604 #define MXC_BASE_PT3_BUS1 ((uint32_t)0x4013C080UL) 605 #define MXC_PT3_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1) 606 #define MXC_BASE_PT4_BUS1 ((uint32_t)0x4013C0A0UL) 607 #define MXC_PT4_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1) 608 #define MXC_BASE_PT5_BUS1 ((uint32_t)0x4013C0C0UL) 609 #define MXC_PT5_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1) 610 #define MXC_BASE_PT6_BUS1 ((uint32_t)0x4013C0E0UL) 611 #define MXC_PT6_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1) 612 #define MXC_BASE_PT7_BUS1 ((uint32_t)0x4013C100UL) 613 #define MXC_PT7_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1) 614 #define MXC_BASE_PT8_BUS1 ((uint32_t)0x4013C120UL) 615 #define MXC_PT8_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1) 616 #define MXC_BASE_PT9_BUS1 ((uint32_t)0x4013C140UL) 617 #define MXC_PT9_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1) 618 #define MXC_BASE_PT10_BUS1 ((uint32_t)0x4013C160UL) 619 #define MXC_PT10_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1) 620 #define MXC_BASE_PT11_BUS1 ((uint32_t)0x4013C180UL) 621 #define MXC_PT11_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1) 622 #define MXC_BASE_PT12_BUS1 ((uint32_t)0x4013C1A0UL) 623 #define MXC_PT12_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1) 624 #define MXC_BASE_PT13_BUS1 ((uint32_t)0x4013C1C0UL) 625 #define MXC_PT13_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1) 626 #define MXC_BASE_PT14_BUS1 ((uint32_t)0x4013C1E0UL) 627 #define MXC_PT14_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1) 628 #define MXC_BASE_PT15_BUS1 ((uint32_t)0x4013C200UL) 629 #define MXC_PT15_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1) 630 631 #define MXC_PT_GET_BASE(i) \ 632 ((i) == 0x0 ? MXC_BASE_PT0_BUS0 : \ 633 (i) == 0x1 ? MXC_BASE_PT1_BUS0 : \ 634 (i) == 0x2 ? MXC_BASE_PT2_BUS0 : \ 635 (i) == 0x3 ? MXC_BASE_PT3_BUS0 : \ 636 (i) == 0x4 ? MXC_BASE_PT4_BUS0 : \ 637 (i) == 0x5 ? MXC_BASE_PT5_BUS0 : \ 638 (i) == 0x6 ? MXC_BASE_PT6_BUS0 : \ 639 (i) == 0x7 ? MXC_BASE_PT7_BUS0 : \ 640 (i) == 0x8 ? MXC_BASE_PT8_BUS0 : \ 641 (i) == 0x9 ? MXC_BASE_PT9_BUS0 : \ 642 (i) == 0xA ? MXC_BASE_PT10_BUS0 : \ 643 (i) == 0xB ? MXC_BASE_PT11_BUS0 : \ 644 (i) == 0xC ? MXC_BASE_PT12_BUS0 : \ 645 (i) == 0xD ? MXC_BASE_PT13_BUS0 : \ 646 (i) == 0xE ? MXC_BASE_PT14_BUS0 : \ 647 (i) == 0xF ? MXC_BASE_PT15_BUS0 : \ 648 (i) == 0x8000 ? MXC_BASE_PT0_BUS1 : \ 649 (i) == 0x8001 ? MXC_BASE_PT1_BUS1 : \ 650 (i) == 0x8002 ? MXC_BASE_PT2_BUS1 : \ 651 (i) == 0x8003 ? MXC_BASE_PT3_BUS1 : \ 652 (i) == 0x8004 ? MXC_BASE_PT4_BUS1 : \ 653 (i) == 0x8005 ? MXC_BASE_PT5_BUS1 : \ 654 (i) == 0x8006 ? MXC_BASE_PT6_BUS1 : \ 655 (i) == 0x8007 ? MXC_BASE_PT7_BUS1 : \ 656 (i) == 0x8008 ? MXC_BASE_PT8_BUS1 : \ 657 (i) == 0x8009 ? MXC_BASE_PT9_BUS1 : \ 658 (i) == 0x800A ? MXC_BASE_PT10_BUS1 : \ 659 (i) == 0x800B ? MXC_BASE_PT11_BUS1 : \ 660 (i) == 0x800C ? MXC_BASE_PT12_BUS1 : \ 661 (i) == 0x800D ? MXC_BASE_PT13_BUS1 : \ 662 (i) == 0x800E ? MXC_BASE_PT14_BUS1 : \ 663 (i) == 0x800F ? MXC_BASE_PT15_BUS1 : \ 664 0) 665 666 #define MXC_PT_GET_PT(i) \ 667 ((i) == 0x0 ? MXC_PT0_BUS0 : \ 668 (i) == 0x1 ? MXC_PT1_BUS0 : \ 669 (i) == 0x2 ? MXC_PT2_BUS0 : \ 670 (i) == 0x3 ? MXC_PT3_BUS0 : \ 671 (i) == 0x4 ? MXC_PT4_BUS0 : \ 672 (i) == 0x5 ? MXC_PT5_BUS0 : \ 673 (i) == 0x6 ? MXC_PT6_BUS0 : \ 674 (i) == 0x7 ? MXC_PT7_BUS0 : \ 675 (i) == 0x8 ? MXC_PT8_BUS0 : \ 676 (i) == 0x9 ? MXC_PT9_BUS0 : \ 677 (i) == 0xA ? MXC_PT10_BUS0 : \ 678 (i) == 0xB ? MXC_PT11_BUS0 : \ 679 (i) == 0xC ? MXC_PT12_BUS0 : \ 680 (i) == 0xD ? MXC_PT13_BUS0 : \ 681 (i) == 0xE ? MXC_PT14_BUS0 : \ 682 (i) == 0xF ? MXC_PT15_BUS0 : \ 683 (i) == 0x8000 ? MXC_PT0_BUS1 : \ 684 (i) == 0x8001 ? MXC_PT1_BUS1 : \ 685 (i) == 0x8002 ? MXC_PT2_BUS1 : \ 686 (i) == 0x8003 ? MXC_PT3_BUS1 : \ 687 (i) == 0x8004 ? MXC_PT4_BUS1 : \ 688 (i) == 0x8005 ? MXC_PT5_BUS1 : \ 689 (i) == 0x8006 ? MXC_PT6_BUS1 : \ 690 (i) == 0x8007 ? MXC_PT7_BUS1 : \ 691 (i) == 0x8008 ? MXC_PT8_BUS1 : \ 692 (i) == 0x8009 ? MXC_PT9_BUS1 : \ 693 (i) == 0x800A ? MXC_PT10_BUS1 : \ 694 (i) == 0x800B ? MXC_PT11_BUS1 : \ 695 (i) == 0x800C ? MXC_PT12_BUS1 : \ 696 (i) == 0x800D ? MXC_PT13_BUS1 : \ 697 (i) == 0x800E ? MXC_PT14_BUS1 : \ 698 (i) == 0x800F ? MXC_PT15_BUS1 : \ 699 0) 700 701 #define MXC_PT_GET_IDX(p) \ 702 ((p) == MXC_PT0_BUS0 ? 0x0 : \ 703 (p) == MXC_PT1_BUS0 ? 0x1 : \ 704 (p) == MXC_PT2_BUS0 ? 0x2 : \ 705 (p) == MXC_PT3_BUS0 ? 0x3 : \ 706 (p) == MXC_PT4_BUS0 ? 0x4 : \ 707 (p) == MXC_PT5_BUS0 ? 0x5 : \ 708 (p) == MXC_PT6_BUS0 ? 0x6 : \ 709 (p) == MXC_PT7_BUS0 ? 0x7 : \ 710 (p) == MXC_PT8_BUS0 ? 0x8 : \ 711 (p) == MXC_PT9_BUS0 ? 0x9 : \ 712 (p) == MXC_PT10_BUS0 ? 0xA : \ 713 (p) == MXC_PT11_BUS0 ? 0xB : \ 714 (p) == MXC_PT12_BUS0 ? 0xC : \ 715 (p) == MXC_PT13_BUS0 ? 0xD : \ 716 (p) == MXC_PT14_BUS0 ? 0xE : \ 717 (p) == MXC_PT15_BUS0 ? 0xF : \ 718 (p) == MXC_PT0_BUS1 ? 0x8000 : \ 719 (p) == MXC_PT1_BUS1 ? 0x8001 : \ 720 (p) == MXC_PT2_BUS1 ? 0x8002 : \ 721 (p) == MXC_PT3_BUS1 ? 0x8003 : \ 722 (p) == MXC_PT4_BUS1 ? 0x8004 : \ 723 (p) == MXC_PT5_BUS1 ? 0x8005 : \ 724 (p) == MXC_PT6_BUS1 ? 0x8006 : \ 725 (p) == MXC_PT7_BUS1 ? 0x8007 : \ 726 (p) == MXC_PT8_BUS1 ? 0x8008 : \ 727 (p) == MXC_PT9_BUS1 ? 0x8009 : \ 728 (p) == MXC_PT10_BUS1 ? 0x800A : \ 729 (p) == MXC_PT11_BUS1 ? 0x800B : \ 730 (p) == MXC_PT12_BUS1 ? 0x800C : \ 731 (p) == MXC_PT13_BUS1 ? 0x800D : \ 732 (p) == MXC_PT14_BUS1 ? 0x800E : \ 733 (p) == MXC_PT15_BUS1 ? 0x800F : \ 734 -1) 735 736 #define MXC_PT_GET_BUS(i) (((i)&0x00100000UL) >> 20) 737 738 #define MXC_PTG_GET_PTG(i) \ 739 (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 : MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0) 740 741 /******************************************************************************/ 742 /* One Wire Master */ 743 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL) 744 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) 745 746 /******************************************************************************/ 747 /* Semaphore */ 748 #define MXC_CFG_SEMA_INSTANCES (8) 749 750 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL) 751 #define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA) 752 753 /******************************************************************************/ 754 /* UART / Serial Port Interface */ 755 #define MXC_UART_INSTANCES (3) 756 #define MXC_UART_FIFO_DEPTH (32) 757 758 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 759 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 760 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 761 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 762 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 763 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 764 765 #define MXC_UART_GET_IRQ(i) \ 766 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 767 (IRQn_Type)(i) == 1 ? UART1_IRQn : \ 768 (IRQn_Type)(i) == 2 ? UART2_IRQn : \ 769 0) 770 771 #define MXC_UART_GET_BASE(i) \ 772 ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : (i) == 2 ? MXC_BASE_UART2 : 0) 773 774 #define MXC_UART_GET_UART(i) \ 775 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : 0) 776 777 #define MXC_UART_GET_IDX(p) \ 778 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : -1) 779 780 /******************************************************************************/ 781 /* SPI */ 782 #define MXC_SPI_INSTANCES (3) 783 #define MXC_SPI_SS_INSTANCES (4) 784 #define MXC_SPI_FIFO_DEPTH (32) 785 786 #define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL) 787 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 788 #define MXC_BASE_SPI1 ((uint32_t)0x40046000UL) 789 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 790 #define MXC_BASE_SPI2 ((uint32_t)0x40047000UL) 791 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) 792 793 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1) 794 795 #define MXC_SPI_GET_BASE(i) \ 796 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0) 797 798 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0) 799 800 #define MXC_SPI_GET_IRQ(i) \ 801 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0) 802 803 /******************************************************************************/ 804 /* TRNG */ 805 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 806 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 807 808 /******************************************************************************/ 809 /* Audio Subsystem */ 810 #define MXC_BASE_AUDIO ((uint32_t)0x4004C000UL) 811 #define MXC_AUDIO ((mxc_audio_regs_t *)MXC_BASE_AUDIO) 812 813 /******************************************************************************/ 814 /* Bluetooth Low Energy */ 815 #define MXC_BASE_BTLE (0x40050000UL) 816 #define MXC_BTLE ((mxc_btle_regs_t *)MXC_BASE_BTLE) 817 #define MXC_BASE_BTLE_DBB_CTRL (MXC_BASE_BTLE + 0x1000) 818 #define MXC_BASE_BTLE_DBB_TX (MXC_BASE_BTLE + 0x2000) 819 #define MXC_BASE_BTLE_DBB_RX (MXC_BASE_BTLE + 0x3000) 820 #define MXC_BASE_BTLE_DBB_EXT_RFFE (MXC_BASE_BTLE + 0x8000) 821 822 // Base address definitions needed for DBB register definitions in BTLE stack 823 #define DBB_CTRL_BASE MXC_BASE_BTLE_DBB_CTRL 824 #define DBB_TX_BASE MXC_BASE_BTLE_DBB_TX 825 #define DBB_RX_BASE MXC_BASE_BTLE_DBB_RX 826 #define DBB_EXT_RFFE_BASE MXC_BASE_BTLE_DBB_EXT_RFFE 827 828 /******************************************************************************/ 829 /* USB */ 830 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL) 831 #define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS) 832 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */ 833 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */ 834 #define MXC_USBHS_MAX_PACKET 512 835 836 /******************************************************************************/ 837 /* SDHC */ 838 #define MXC_BASE_SDHC ((uint32_t)0x400B6000UL) 839 #define MXC_SDHC ((mxc_sdhc_regs_t *)MXC_BASE_SDHC) 840 841 /******************************************************************************/ 842 /* Bit Shifting */ 843 #define MXC_F_BIT_0 (1 << 0) 844 #define MXC_F_BIT_1 (1 << 1) 845 #define MXC_F_BIT_2 (1 << 2) 846 #define MXC_F_BIT_3 (1 << 3) 847 #define MXC_F_BIT_4 (1 << 4) 848 #define MXC_F_BIT_5 (1 << 5) 849 #define MXC_F_BIT_6 (1 << 6) 850 #define MXC_F_BIT_7 (1 << 7) 851 #define MXC_F_BIT_8 (1 << 8) 852 #define MXC_F_BIT_9 (1 << 9) 853 #define MXC_F_BIT_10 (1 << 10) 854 #define MXC_F_BIT_11 (1 << 11) 855 #define MXC_F_BIT_12 (1 << 12) 856 #define MXC_F_BIT_13 (1 << 13) 857 #define MXC_F_BIT_14 (1 << 14) 858 #define MXC_F_BIT_15 (1 << 15) 859 #define MXC_F_BIT_16 (1 << 16) 860 #define MXC_F_BIT_17 (1 << 17) 861 #define MXC_F_BIT_18 (1 << 18) 862 #define MXC_F_BIT_19 (1 << 19) 863 #define MXC_F_BIT_20 (1 << 20) 864 #define MXC_F_BIT_21 (1 << 21) 865 #define MXC_F_BIT_22 (1 << 22) 866 #define MXC_F_BIT_23 (1 << 23) 867 #define MXC_F_BIT_24 (1 << 24) 868 #define MXC_F_BIT_25 (1 << 25) 869 #define MXC_F_BIT_26 (1 << 26) 870 #define MXC_F_BIT_27 (1 << 27) 871 #define MXC_F_BIT_28 (1 << 28) 872 #define MXC_F_BIT_29 (1 << 29) 873 #define MXC_F_BIT_30 (1 << 30) 874 #define MXC_F_BIT_31 (1 << 31) 875 876 /******************************************************************************/ 877 /* Bit Banding */ 878 #define BITBAND(reg, bit) \ 879 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 880 ((bit) << 2)) 881 882 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 883 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 884 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 885 886 #define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask))) 887 888 /******************************************************************************/ 889 /* SCB CPACR */ 890 891 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 892 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 893 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 894 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 895 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 896 897 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ 898
