1 /**
2 ******************************************************************************
3 * @file mx25lm51245g.c
4 * @modify MCD Application Team
5 * @brief This file provides the MX25LM51245G OSPI drivers.
6 ******************************************************************************
7 * MX25LM51245G action :
8 * STR Octal IO protocol (SOPI) and DTR Octal IO protocol (DOPI) bits of
9 * Configuration Register 2 :
10 * DOPI = 1 and SOPI = 0: Operates in DTR Octal IO protocol (accepts 8-8-8 commands)
11 * DOPI = 0 and SOPI = 1: Operates in STR Octal IO protocol (accepts 8-8-8 commands)
12 * DOPI = 0 and SOPI = 0: Operates in Single IO protocol (accepts 1-1-1 commands)
13 * Enter SOPI mode by configuring DOPI = 0 and SOPI = 1 in CR2-Addr0
14 * Exit SOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
15 * Enter DOPI mode by configuring DOPI = 1 and SOPI = 0 in CR2-Addr0
16 * Exit DOPI mode by configuring DOPI = 0 and SOPI = 0 in CR2-Addr0
17 *
18 * Memory commands support STR(Single Transfer Rate) &
19 * DTR(Double Transfer Rate) modes in OPI
20 *
21 * Memory commands support STR(Single Transfer Rate) &
22 * DTR(Double Transfer Rate) modes in SPI
23 *
24 ******************************************************************************
25 * @attention
26 *
27 * <h2><center>© Copyright (c) 2018 STMicroelectronics.
28 * All rights reserved.</center></h2>
29 *
30 * This software component is licensed by ST under BSD 3-Clause license,
31 * the "License"; You may not use this file except in compliance with the
32 * License. You may obtain a copy of the License at:
33 * opensource.org/licenses/BSD-3-Clause
34 *
35 ******************************************************************************
36 */
37
38 /* Includes ------------------------------------------------------------------*/
39 #include "mx25lm51245g.h"
40
41 /** @addtogroup BSP
42 * @{
43 */
44
45 /** @addtogroup Components
46 * @{
47 */
48
49 /** @defgroup MX25LM51245G MX25LM51245G
50 * @{
51 */
52
53 /** @defgroup MX25LM51245G_Exported_Functions MX25LM51245G Exported Functions
54 * @{
55 */
56
57 /**
58 * @brief Get Flash information
59 * @param pInfo pointer to information structure
60 * @retval error status
61 */
MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t * pInfo)62 int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo)
63 {
64 /* Configure the structure with the memory configuration */
65 pInfo->FlashSize = MX25LM51245G_FLASH_SIZE;
66 pInfo->EraseSectorSize = MX25LM51245G_SECTOR_64K;
67 pInfo->EraseSectorsNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SECTOR_64K);
68 pInfo->EraseSubSectorSize = MX25LM51245G_SUBSECTOR_4K;
69 pInfo->EraseSubSectorNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K);
70 pInfo->EraseSubSector1Size = MX25LM51245G_SUBSECTOR_4K;
71 pInfo->EraseSubSector1Number = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_SUBSECTOR_4K);
72 pInfo->ProgPageSize = MX25LM51245G_PAGE_SIZE;
73 pInfo->ProgPagesNumber = (MX25LM51245G_FLASH_SIZE/MX25LM51245G_PAGE_SIZE);
74
75 return MX25LM51245G_OK;
76 };
77
78 /**
79 * @brief Polling WIP(Write In Progress) bit become to 0
80 * SPI/OPI;
81 * @param Ctx Component object pointer
82 * @param Mode Interface mode
83 * @param Rate Transfer rate
84 * @retval error status
85 */
MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)86 int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
87 {
88 OSPI_RegularCmdTypeDef s_command = {0};
89 OSPI_AutoPollingTypeDef s_config = {0};
90
91 /* SPI mode and DTR transfer not supported by memory */
92 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
93 {
94 return MX25LM51245G_ERROR;
95 }
96
97 /* Configure automatic polling mode to wait for memory ready */
98 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
99 #if defined (OCTOSPI_CR_MSEL)
100 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
101 #else
102 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
103 #endif
104 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
105 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
106 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
107 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
108 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
109 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
110 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
111 s_command.Address = 0U;
112 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
113 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
114 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
115 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
116 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
117 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
118 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
119
120 s_config.Match = 0U;
121 s_config.Mask = MX25LM51245G_SR_WIP;
122 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
123 s_config.Interval = MX25LM51245G_AUTOPOLLING_INTERVAL_TIME;
124 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
125
126 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
127 {
128 return MX25LM51245G_ERROR;
129 }
130
131 if (HAL_OSPI_AutoPolling(Ctx, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
132 {
133 return MX25LM51245G_ERROR;
134 }
135
136 return MX25LM51245G_OK;
137 }
138
139 /* Read/Write Array Commands (3/4 Byte Address Command Set) *********************/
140 /**
141 * @brief Reads an amount of data from the OSPI memory on STR mode.
142 * SPI/OPI; 1-1-1/8-8-8
143 * @param Ctx Component object pointer
144 * @param Mode Interface mode
145 * @param AddressSize Address size
146 * @param pData Pointer to data to be read
147 * @param ReadAddr Read start address
148 * @param Size Size of data to read
149 * @retval OSPI memory status
150 */
MX25LM51245G_ReadSTR(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_AddressSize_t AddressSize,uint8_t * pData,uint32_t ReadAddr,uint32_t Size)151 int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
152 {
153 OSPI_RegularCmdTypeDef s_command = {0};
154
155 /* OPI mode and 3-bytes address size not supported by memory */
156 if ((Mode == MX25LM51245G_OPI_MODE) && (AddressSize == MX25LM51245G_3BYTES_SIZE))
157 {
158 return MX25LM51245G_ERROR;
159 }
160
161 /* Initialize the read command */
162 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
163 #if defined (OCTOSPI_CR_MSEL)
164 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
165 #else
166 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
167 #endif
168 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
169 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
170 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
171 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD;
172 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
173 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
174 s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
175 s_command.Address = ReadAddr;
176 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
177 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
178 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
179 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? DUMMY_CYCLES_READ : DUMMY_CYCLES_READ_OCTAL;
180 s_command.NbData = Size;
181 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
182 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
183
184 /* Send the command */
185 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
186 {
187 return MX25LM51245G_ERROR;
188 }
189
190 /* Reception of the data */
191 if (HAL_OSPI_Receive(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
192 {
193 return MX25LM51245G_ERROR;
194 }
195
196 return MX25LM51245G_OK;
197 }
198
199 /**
200 * @brief Reads an amount of data from the OSPI memory on DTR mode.
201 * OPI
202 * @param Ctx Component object pointer
203 * @param AddressSize Address size
204 * @param pData Pointer to data to be read
205 * @param ReadAddr Read start addressS
206 * @param Size Size of data to read
207 * @note Only OPI mode support DTR transfer rate
208 * @retval OSPI memory status
209 */
MX25LM51245G_ReadDTR(OSPI_HandleTypeDef * Ctx,uint8_t * pData,uint32_t ReadAddr,uint32_t Size)210 int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
211 {
212 OSPI_RegularCmdTypeDef s_command = {0};
213
214 /* Initialize the read command */
215 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
216 #if defined (OCTOSPI_CR_MSEL)
217 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
218 #else
219 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
220 #endif
221 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
222 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
223 s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
224 s_command.Instruction = MX25LM51245G_OCTA_READ_DTR_CMD;
225 s_command.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
226 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_ENABLE;
227 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
228 s_command.Address = ReadAddr;
229 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
230 s_command.DataMode = HAL_OSPI_DATA_8_LINES;
231 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_ENABLE;
232 s_command.DummyCycles = DUMMY_CYCLES_READ_OCTAL_DTR;
233 s_command.NbData = Size;
234 s_command.DQSMode = HAL_OSPI_DQS_ENABLE;
235 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
236
237 /* Send the command */
238 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
239 {
240 return MX25LM51245G_ERROR;
241 }
242
243 /* Reception of the data */
244 if (HAL_OSPI_Receive(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
245 {
246 return MX25LM51245G_ERROR;
247 }
248
249 return MX25LM51245G_OK;
250 }
251
252 /**
253 * @brief Writes an amount of data to the OSPI memory.
254 * SPI/OPI
255 * @param Ctx Component object pointer
256 * @param Mode Interface mode
257 * @param AddressSize Address size
258 * @param pData Pointer to data to be written
259 * @param WriteAddr Write start address
260 * @param Size Size of data to write. Range 1 ~ MX25LM51245G_PAGE_SIZE
261 * @note Address size is forced to 3 Bytes when the 4 Bytes address size
262 * command is not available for the specified interface mode
263 * @retval OSPI memory status
264 */
MX25LM51245G_PageProgram(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_AddressSize_t AddressSize,uint8_t * pData,uint32_t WriteAddr,uint32_t Size)265 int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
266 {
267 OSPI_RegularCmdTypeDef s_command = {0};
268
269 /* OPI mode and 3-bytes address size not supported by memory */
270 if ((Mode == MX25LM51245G_OPI_MODE) && (AddressSize == MX25LM51245G_3BYTES_SIZE))
271 {
272 return MX25LM51245G_ERROR;
273 }
274
275 /* Initialize the program command */
276 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
277 #if defined (OCTOSPI_CR_MSEL)
278 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
279 #else
280 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
281 #endif
282 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
283 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
284 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
285 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD;
286 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
287 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
288 s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
289 s_command.Address = WriteAddr;
290 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
291 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
292 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
293 s_command.DummyCycles = 0U;
294 s_command.NbData = Size;
295 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
296 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
297
298 /* Configure the command */
299 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
300 {
301 return MX25LM51245G_ERROR;
302 }
303
304 /* Transmission of the data */
305 if (HAL_OSPI_Transmit(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
306 {
307 return MX25LM51245G_ERROR;
308 }
309
310 return MX25LM51245G_OK;
311 }
312
313 /**
314 * @brief Writes an amount of data to the OSPI memory on DTR mode.
315 * SPI/OPI
316 * @param Ctx Component object pointer
317 * @param pData Pointer to data to be written
318 * @param WriteAddr Write start address
319 * @param Size Size of data to write. Range 1 ~ MX25LM51245G_PAGE_SIZE
320 * @note Only OPI mode support DTR transfer rate
321 * @retval OSPI memory status
322 */
MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef * Ctx,uint8_t * pData,uint32_t WriteAddr,uint32_t Size)323 int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
324 {
325 OSPI_RegularCmdTypeDef s_command = {0};
326
327 /* Initialize the program command */
328 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
329 #if defined (OCTOSPI_CR_MSEL)
330 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
331 #else
332 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
333 #endif
334 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
335 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
336 s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
337 s_command.Instruction = MX25LM51245G_OCTA_PAGE_PROG_CMD;
338 s_command.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
339 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_ENABLE;
340 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
341 s_command.Address = WriteAddr;
342 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
343 s_command.DataMode = HAL_OSPI_DATA_8_LINES;
344 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_ENABLE;
345 s_command.DummyCycles = 0U;
346 s_command.NbData = Size;
347 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
348 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
349
350 /* Configure the command */
351 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
352 {
353 return MX25LM51245G_ERROR;
354 }
355
356 /* Transmission of the data */
357 if (HAL_OSPI_Transmit(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
358 {
359 return MX25LM51245G_ERROR;
360 }
361
362 return MX25LM51245G_OK;
363 }
364
365 /**
366 * @brief Erases the specified block of the OSPI memory.
367 * MX25LM51245G support 4K, 64K size block erase commands.
368 * SPI/OPI; 1-1-1/8-8-8
369 * @param Ctx Component object pointer
370 * @param Mode Interface mode
371 * @param AddressSize Address size
372 * @param BlockAddress Block address to erase
373 * @param BlockSize Block size to erase
374 * @retval OSPI memory status
375 */
MX25LM51245G_BlockErase(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,MX25LM51245G_AddressSize_t AddressSize,uint32_t BlockAddress,MX25LM51245G_Erase_t BlockSize)376 int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize)
377 {
378 OSPI_RegularCmdTypeDef s_command = {0};
379
380 /* SPI mode and DTR transfer not supported by memory */
381 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
382 {
383 return MX25LM51245G_ERROR;
384 }
385
386 /* OPI mode and 3-bytes address size not supported by memory */
387 if ((Mode == MX25LM51245G_OPI_MODE) && (AddressSize == MX25LM51245G_3BYTES_SIZE))
388 {
389 return MX25LM51245G_ERROR;
390 }
391
392 /* Initialize the erase command */
393 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
394 #if defined (OCTOSPI_CR_MSEL)
395 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
396 #else
397 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
398 #endif
399 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
400 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
401 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
402 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
403 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
404 s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
405 s_command.Address = BlockAddress;
406 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
407 s_command.DataMode = HAL_OSPI_DATA_NONE;
408 s_command.DummyCycles = 0U;
409 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
410 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
411
412 switch(Mode)
413 {
414 case MX25LM51245G_OPI_MODE :
415 if(BlockSize == MX25LM51245G_ERASE_64K)
416 {
417 s_command.Instruction = MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD;
418 }
419 else
420 {
421 s_command.Instruction = MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD;
422 }
423 break;
424
425 case MX25LM51245G_SPI_MODE :
426 default:
427 if(BlockSize == MX25LM51245G_ERASE_64K)
428 {
429 s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SECTOR_ERASE_64K_CMD : MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD;
430 }
431 else
432 {
433 s_command.Instruction = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_SUBSECTOR_ERASE_4K_CMD : MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD;
434 }
435 break;
436 }
437
438 /* Send the command */
439 if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
440 {
441 return MX25LM51245G_ERROR;
442 }
443
444 return MX25LM51245G_OK;
445 }
446
447 /**
448 * @brief Whole chip erase.
449 * SPI/OPI; 1-0-0/8-0-0
450 * @param Ctx Component object pointer
451 * @param Mode Interface mode
452 * @retval error status
453 */
MX25LM51245G_ChipErase(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)454 int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
455 {
456 OSPI_RegularCmdTypeDef s_command = {0};
457
458 /* SPI mode and DTR transfer not supported by memory */
459 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
460 {
461 return MX25LM51245G_ERROR;
462 }
463
464 /* Initialize the erase command */
465 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
466 #if defined (OCTOSPI_CR_MSEL)
467 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
468 #else
469 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
470 #endif
471 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
472 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
473 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
474 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_BULK_ERASE_CMD : MX25LM51245G_OCTA_BULK_ERASE_CMD;
475 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
476 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
477 s_command.DataMode = HAL_OSPI_DATA_NONE;
478 s_command.DummyCycles = 0U;
479 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
480 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
481
482 /* Send the command */
483 if(HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
484 {
485 return MX25LM51245G_ERROR;
486 }
487
488 return MX25LM51245G_OK;
489 }
490
491 /**
492 * @brief Enable memory mapped mode for the OSPI memory on STR mode.
493 * SPI/OPI; 1-1-1/8-8-8
494 * @param Ctx Component object pointer
495 * @param Mode Interface mode
496 * @param AddressSize Address size
497 * @retval OSPI memory status
498 */
MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_AddressSize_t AddressSize)499 int32_t MX25LM51245G_EnableSTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize)
500 {
501 OSPI_RegularCmdTypeDef s_command = {0};
502 OSPI_MemoryMappedTypeDef s_mem_mapped_cfg = {0};
503
504 /* OPI mode and 3-bytes address size not supported by memory */
505 if ((Mode == MX25LM51245G_OPI_MODE) && (AddressSize == MX25LM51245G_3BYTES_SIZE))
506 {
507 return MX25LM51245G_ERROR;
508 }
509
510 /* Initialize the read command */
511 s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
512 #if defined (OCTOSPI_CR_MSEL)
513 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
514 #else
515 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
516 #endif
517 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
518 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
519 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
520 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_FAST_READ_CMD : MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD) : MX25LM51245G_OCTA_READ_CMD;
521 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
522 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
523 s_command.AddressSize = (AddressSize == MX25LM51245G_3BYTES_SIZE) ? HAL_OSPI_ADDRESS_24_BITS : HAL_OSPI_ADDRESS_32_BITS;
524 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
525 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
526 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
527 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? DUMMY_CYCLES_READ : DUMMY_CYCLES_READ_OCTAL;
528 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
529 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
530
531 /* Send the read command */
532 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
533 {
534 return MX25LM51245G_ERROR;
535 }
536
537 /* Initialize the program command */
538 s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
539 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? ((AddressSize == MX25LM51245G_3BYTES_SIZE) ? MX25LM51245G_PAGE_PROG_CMD : MX25LM51245G_4_BYTE_PAGE_PROG_CMD) : MX25LM51245G_OCTA_PAGE_PROG_CMD;
540 s_command.DummyCycles = 0U;
541
542 /* Send the write command */
543 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
544 {
545 return MX25LM51245G_ERROR;
546 }
547
548 /* Configure the memory mapped mode */
549 s_mem_mapped_cfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
550
551 if (HAL_OSPI_MemoryMapped(Ctx, &s_mem_mapped_cfg) != HAL_OK)
552 {
553 return MX25LM51245G_ERROR;
554 }
555
556 return MX25LM51245G_OK;
557 }
558
559 /**
560 * @brief Enable memory mapped mode for the OSPI memory on DTR mode.
561 * @param Ctx Component object pointer
562 * @param Mode Interface mode
563 * @param AddressSize Address size
564 * @note Only OPI mode support DTR transfer rate
565 * @retval OSPI memory status
566 */
MX25LM51245G_EnableDTRMemoryMappedMode(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode)567 int32_t MX25LM51245G_EnableDTRMemoryMappedMode(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode)
568 {
569 /* Prevent unused argument(s) compilation warning */
570 UNUSED(Mode);
571
572 OSPI_RegularCmdTypeDef s_command = {0};
573 OSPI_MemoryMappedTypeDef s_mem_mapped_cfg = {0};
574
575 /* Initialize the read command */
576 s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
577 #if defined (OCTOSPI_CR_MSEL)
578 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
579 #else
580 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
581 #endif
582 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
583 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
584 s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
585 s_command.Instruction = MX25LM51245G_OCTA_READ_DTR_CMD;
586 s_command.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
587 s_command.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_ENABLE;
588 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
589 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
590 s_command.DataMode = HAL_OSPI_DATA_8_LINES;
591 s_command.DataDtrMode = HAL_OSPI_DATA_DTR_ENABLE;
592 s_command.DummyCycles = DUMMY_CYCLES_READ_OCTAL_DTR;
593 s_command.DQSMode = HAL_OSPI_DQS_ENABLE;
594 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
595
596 /* Send the command */
597 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
598 {
599 return MX25LM51245G_ERROR;
600 }
601
602 /* Initialize the program command */
603 s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
604 s_command.Instruction = MX25LM51245G_OCTA_PAGE_PROG_CMD;
605 s_command.DummyCycles = 0U;
606 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
607
608 /* Send the command */
609 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
610 {
611 return MX25LM51245G_ERROR;
612 }
613 /* Configure the memory mapped mode */
614 s_mem_mapped_cfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
615
616 if (HAL_OSPI_MemoryMapped(Ctx, &s_mem_mapped_cfg) != HAL_OK)
617 {
618 return MX25LM51245G_ERROR;
619 }
620
621 return MX25LM51245G_OK;
622 }
623
624 /**
625 * @brief Flash suspend program or erase command
626 * SPI/OPI
627 * @param Ctx Component object pointer
628 * @param Mode Interface select
629 * @param Rate Transfer rate STR or DTR
630 * @retval error status
631 */
MX25LM51245G_Suspend(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)632 int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
633 {
634 OSPI_RegularCmdTypeDef s_command = {0};
635
636 /* SPI mode and DTR transfer not supported by memory */
637 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
638 {
639 return MX25LM51245G_ERROR;
640 }
641
642 /* Initialize the suspend command */
643 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
644 #if defined (OCTOSPI_CR_MSEL)
645 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
646 #else
647 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
648 #endif
649 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
650 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
651 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
652 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_SUSPEND_CMD : MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD;
653 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
654 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
655 s_command.DataMode = HAL_OSPI_DATA_NONE;
656 s_command.DummyCycles = 0U;
657 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
658 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
659
660 /* Send the command */
661 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
662 {
663 return MX25LM51245G_ERROR;
664 }
665
666 return MX25LM51245G_OK;
667 }
668
669 /**
670 * @brief Flash resume program or erase command
671 * SPI/OPI
672 * @param Ctx Component object pointer
673 * @param Mode Interface select
674 * @param Rate Transfer rate STR or DTR
675 * @retval error status
676 */
MX25LM51245G_Resume(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)677 int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
678 {
679 OSPI_RegularCmdTypeDef s_command = {0};
680
681 /* SPI mode and DTR transfer not supported by memory */
682 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
683 {
684 return MX25LM51245G_ERROR;
685 }
686
687 /* Initialize the resume command */
688 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
689 #if defined (OCTOSPI_CR_MSEL)
690 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
691 #else
692 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
693 #endif
694 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
695 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
696 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
697 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_PROG_ERASE_RESUME_CMD : MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD;
698 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
699 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
700 s_command.DataMode = HAL_OSPI_DATA_NONE;
701 s_command.DummyCycles = 0U;
702 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
703 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
704
705 /* Send the command */
706 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
707 {
708 return MX25LM51245G_ERROR;
709 }
710
711 return MX25LM51245G_OK;
712 }
713
714 /* Register/Setting Commands **************************************************/
715 /**
716 * @brief This function send a Write Enable and wait it is effective.
717 * SPI/OPI
718 * @param Ctx Component object pointer
719 * @param Mode Interface mode
720 * @param Rate Transfer rate STR or DTR
721 * @retval error status
722 */
MX25LM51245G_WriteEnable(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)723 int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
724 {
725 OSPI_RegularCmdTypeDef s_command = {0};
726 OSPI_AutoPollingTypeDef s_config = {0};
727
728 /* SPI mode and DTR transfer not supported by memory */
729 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
730 {
731 return MX25LM51245G_ERROR;
732 }
733
734 /* Initialize the write enable command */
735 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
736 #if defined (OCTOSPI_CR_MSEL)
737 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
738 #else
739 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
740 #endif
741 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
742 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
743 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
744 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_ENABLE_CMD : MX25LM51245G_OCTA_WRITE_ENABLE_CMD;
745 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
746 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
747 s_command.DataMode = HAL_OSPI_DATA_NONE;
748 s_command.DummyCycles = 0U;
749 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
750 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
751
752 /* Send the command */
753 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
754 {
755 return MX25LM51245G_ERROR;
756 }
757
758 /* Configure automatic polling mode to wait for write enabling */
759 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
760 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
761 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
762 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
763 s_command.Address = 0U;
764 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
765 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
766 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
767 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
768 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
769
770 /* Send the command */
771 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
772 {
773 return MX25LM51245G_ERROR;
774 }
775
776 s_config.Match = 2U;
777 s_config.Mask = 2U;
778 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
779 s_config.Interval = MX25LM51245G_AUTOPOLLING_INTERVAL_TIME;
780 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
781
782 if (HAL_OSPI_AutoPolling(Ctx, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
783 {
784 return MX25LM51245G_ERROR;
785 }
786
787 return MX25LM51245G_OK;
788 }
789
790 /**
791 * @brief This function reset the (WEN) Write Enable Latch bit.
792 * SPI/OPI
793 * @param Ctx Component object pointer
794 * @param Mode Interface mode
795 * @param Rate Transfer rate STR or DTR
796 * @retval error status
797 */
MX25LM51245G_WriteDisable(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)798 int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
799 {
800 OSPI_RegularCmdTypeDef s_command = {0};
801
802 /* SPI mode and DTR transfer not supported by memory */
803 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
804 {
805 return MX25LM51245G_ERROR;
806 }
807
808 /* Initialize the write disable command */
809 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
810 #if defined (OCTOSPI_CR_MSEL)
811 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
812 #else
813 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
814 #endif
815 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
816 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
817 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
818 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_DISABLE_CMD : MX25LM51245G_OCTA_WRITE_DISABLE_CMD;
819 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
820 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
821 s_command.DataMode = HAL_OSPI_DATA_NONE;
822 s_command.DummyCycles = 0U;
823 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
824 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
825
826 /* Send the command */
827 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
828 {
829 return MX25LM51245G_ERROR;
830 }
831
832 return MX25LM51245G_OK;
833 }
834
835 /**
836 * @brief Read Flash Status register value
837 * SPI/OPI
838 * @param Ctx Component object pointer
839 * @param Mode Interface mode
840 * @param Rate Transfer rate STR or DTR
841 * @param Value Status register value pointer
842 * @retval error status
843 */
MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t * Value)844 int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
845 {
846 OSPI_RegularCmdTypeDef s_command = {0};
847
848 /* SPI mode and DTR transfer not supported by memory */
849 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
850 {
851 return MX25LM51245G_ERROR;
852 }
853
854 /* Initialize the reading of status register */
855 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
856 #if defined (OCTOSPI_CR_MSEL)
857 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
858 #else
859 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
860 #endif
861 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
862 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
863 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
864 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_STATUS_REG_CMD : MX25LM51245G_OCTA_READ_STATUS_REG_CMD;
865 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
866 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
867 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
868 s_command.Address = 0U;
869 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
870 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
871 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
872 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
873 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
874 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
875 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
876
877 /* Send the command */
878 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
879 {
880 return MX25LM51245G_ERROR;
881 }
882
883 /* Reception of the data */
884 if (HAL_OSPI_Receive(Ctx, Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
885 {
886 return MX25LM51245G_ERROR;
887 }
888
889 return MX25LM51245G_OK;
890 }
891
892 /**
893 * @brief Write Flash Status register
894 * SPI/OPI
895 * @param Ctx Component object pointer
896 * @param Mode Interface mode
897 * @param Rate Transfer rate STR or DTR
898 * @param Value Value to write to Status register
899 * @retval error status
900 */
MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t Value)901 int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
902 {
903 OSPI_RegularCmdTypeDef s_command = {0};
904 uint8_t reg[2];
905
906 /* SPI mode and DTR transfer not supported by memory */
907 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
908 {
909 return MX25LM51245G_ERROR;
910 }
911
912 /* In SPI mode, the status register is configured with configuration register */
913 if (Mode == MX25LM51245G_SPI_MODE)
914 {
915 if (MX25LM51245G_ReadCfgRegister(Ctx, Mode, Rate, ®[1]) != MX25LM51245G_OK)
916 {
917 return MX25LM51245G_ERROR;
918 }
919 }
920 reg[0] = Value;
921
922 /* Initialize the writing of status register */
923 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
924 #if defined (OCTOSPI_CR_MSEL)
925 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
926 #else
927 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
928 #endif
929 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
930 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
931 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
932 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
933 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
934 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
935 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
936 s_command.Address = 0U;
937 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
938 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
939 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
940 s_command.DummyCycles = 0U;
941 s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
942 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
943 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
944
945 /* Send the command */
946 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
947 {
948 return MX25LM51245G_ERROR;
949 }
950
951 if (HAL_OSPI_Transmit(Ctx, reg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
952 {
953 return MX25LM51245G_ERROR;
954 }
955
956 return MX25LM51245G_OK;
957 }
958
959 /**
960 * @brief Write Flash configuration register
961 * SPI/OPI
962 * @param Ctx Component object pointer
963 * @param Mode Interface mode
964 * @param Rate Transfer rate STR or DTR
965 * @param Value Value to write to configuration register
966 * @retval error status
967 */
MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t Value)968 int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
969 {
970 OSPI_RegularCmdTypeDef s_command = {0};
971 uint8_t reg[2];
972
973 /* SPI mode and DTR transfer not supported by memory */
974 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
975 {
976 return MX25LM51245G_ERROR;
977 }
978
979 /* In SPI mode, the configuration register is configured with status register */
980 if (Mode == MX25LM51245G_SPI_MODE)
981 {
982 if (MX25LM51245G_ReadStatusRegister(Ctx, Mode, Rate, ®[0]) != MX25LM51245G_OK)
983 {
984 return MX25LM51245G_ERROR;
985 }
986 reg[1] = Value;
987 }
988 else
989 {
990 reg[0] = Value;
991 }
992
993 /* Initialize the writing of configuration register */
994 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
995 #if defined (OCTOSPI_CR_MSEL)
996 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
997 #else
998 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
999 #endif
1000 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1001 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1002 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1003 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_STATUS_REG_CMD : MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD;
1004 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
1005 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1006 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1007 s_command.Address = 1U;
1008 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1009 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1010 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1011 s_command.DummyCycles = 0U;
1012 s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 2U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
1013 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1014 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1015
1016 /* Send the command */
1017 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1018 {
1019 return MX25LM51245G_ERROR;
1020 }
1021
1022 if (HAL_OSPI_Transmit(Ctx, reg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1023 {
1024 return MX25LM51245G_ERROR;
1025 }
1026
1027 return MX25LM51245G_OK;
1028 }
1029
1030 /**
1031 * @brief Read Flash configuration register value
1032 * SPI/OPI
1033 * @param Ctx Component object pointer
1034 * @param Mode Interface mode
1035 * @param Rate Transfer rate STR or DTR
1036 * @param Value configuration register value pointer
1037 * @retval error status
1038 */
MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t * Value)1039 int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
1040 {
1041 OSPI_RegularCmdTypeDef s_command = {0};
1042
1043 /* SPI mode and DTR transfer not supported by memory */
1044 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1045 {
1046 return MX25LM51245G_ERROR;
1047 }
1048
1049 /* Initialize the reading of configuration register */
1050 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1051 #if defined (OCTOSPI_CR_MSEL)
1052 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1053 #else
1054 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1055 #endif
1056 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1057 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1058 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1059 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG_CMD : MX25LM51245G_OCTA_READ_CFG_REG_CMD;
1060 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
1061 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1062 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1063 s_command.Address = 1U;
1064 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1065 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1066 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1067 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
1068 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
1069 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
1070 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1071
1072 /* Send the command */
1073 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1074 {
1075 return MX25LM51245G_ERROR;
1076 }
1077
1078 /* Reception of the data */
1079 if (HAL_OSPI_Receive(Ctx, Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1080 {
1081 return MX25LM51245G_ERROR;
1082 }
1083
1084 return MX25LM51245G_OK;
1085 }
1086
1087 /**
1088 * @brief Write Flash configuration register 2
1089 * SPI/OPI
1090 * @param Ctx Component object pointer
1091 * @param Mode Interface mode
1092 * @param Rate Transfer rate STR or DTR
1093 * @param Value Value to write to configuration register
1094 * @retval error status
1095 */
MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint32_t WriteAddr,uint8_t Value)1096 int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value)
1097 {
1098 OSPI_RegularCmdTypeDef s_command = {0};
1099
1100 /* SPI mode and DTR transfer not supported by memory */
1101 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1102 {
1103 return MX25LM51245G_ERROR;
1104 }
1105
1106 /* Initialize the writing of configuration register 2 */
1107 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1108 #if defined (OCTOSPI_CR_MSEL)
1109 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1110 #else
1111 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1112 #endif
1113 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1114 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1115 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1116 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_CFG_REG2_CMD : MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD;
1117 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
1118 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1119 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1120 s_command.Address = WriteAddr;
1121 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1122 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1123 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1124 s_command.DummyCycles = 0U;
1125 s_command.NbData = (Mode == MX25LM51245G_SPI_MODE) ? 1U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U);
1126 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1127 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1128
1129 /* Send the command */
1130 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1131 {
1132 return MX25LM51245G_ERROR;
1133 }
1134
1135 if (HAL_OSPI_Transmit(Ctx, &Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1136 {
1137 return MX25LM51245G_ERROR;
1138 }
1139
1140 return MX25LM51245G_OK;
1141 }
1142
1143 /**
1144 * @brief Read Flash configuration register 2 value
1145 * SPI/OPI
1146 * @param Ctx Component object pointer
1147 * @param Mode Interface mode
1148 * @param Rate Transfer rate STR or DTR
1149 * @param Value configuration register 2 value pointer
1150 * @retval error status
1151 */
MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint32_t ReadAddr,uint8_t * Value)1152 int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value)
1153 {
1154 OSPI_RegularCmdTypeDef s_command = {0};
1155
1156 /* SPI mode and DTR transfer not supported by memory */
1157 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1158 {
1159 return MX25LM51245G_ERROR;
1160 }
1161
1162 /* Initialize the reading of status register */
1163 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1164 #if defined (OCTOSPI_CR_MSEL)
1165 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1166 #else
1167 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1168 #endif
1169 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1170 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1171 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1172 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_CFG_REG2_CMD : MX25LM51245G_OCTA_READ_CFG_REG2_CMD;
1173 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_8_LINES;
1174 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1175 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1176 s_command.Address = ReadAddr;
1177 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1178 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1179 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1180 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
1181 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
1182 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
1183 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1184
1185 /* Send the command */
1186 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1187 {
1188 return MX25LM51245G_ERROR;
1189 }
1190
1191 /* Reception of the data */
1192 if (HAL_OSPI_Receive(Ctx, Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1193 {
1194 return MX25LM51245G_ERROR;
1195 }
1196
1197 return MX25LM51245G_OK;
1198 }
1199
1200 /**
1201 * @brief Write Flash Security register
1202 * SPI/OPI
1203 * @param Ctx Component object pointer
1204 * @param Mode Interface mode
1205 * @param Rate Transfer rate STR or DTR
1206 * @param Value Value to write to Security register
1207 * @retval error status
1208 */
MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t Value)1209 int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value)
1210 {
1211 /* Prevent unused argument(s) compilation warning */
1212 UNUSED(Value);
1213
1214 OSPI_RegularCmdTypeDef s_command = {0};
1215
1216 /* SPI mode and DTR transfer not supported by memory */
1217 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1218 {
1219 return MX25LM51245G_ERROR;
1220 }
1221
1222 /* Initialize the write of security register */
1223 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1224 #if defined (OCTOSPI_CR_MSEL)
1225 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1226 #else
1227 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1228 #endif
1229 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1230 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1231 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1232 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_WRITE_SECURITY_REG_CMD : MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD;
1233 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
1234 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1235 s_command.DataMode = HAL_OSPI_DATA_NONE;
1236 s_command.DummyCycles = 0U;
1237 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1238 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1239
1240 /* Send the command */
1241 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1242 {
1243 return MX25LM51245G_ERROR;
1244 }
1245
1246 return MX25LM51245G_OK;
1247 }
1248
1249 /**
1250 * @brief Read Flash Security register value
1251 * SPI/OPI
1252 * @param Ctx Component object pointer
1253 * @param Mode Interface mode
1254 * @param Rate Transfer rate STR or DTR
1255 * @param Value Security register value pointer
1256 * @retval error status
1257 */
MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t * Value)1258 int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value)
1259 {
1260 OSPI_RegularCmdTypeDef s_command = {0};
1261
1262 /* SPI mode and DTR transfer not supported by memory */
1263 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1264 {
1265 return MX25LM51245G_ERROR;
1266 }
1267
1268 /* Initialize the reading of security register */
1269 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1270 #if defined (OCTOSPI_CR_MSEL)
1271 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1272 #else
1273 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1274 #endif
1275 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1276 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1277 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1278 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_SECURITY_REG_CMD : MX25LM51245G_OCTA_READ_SECURITY_REG_CMD;
1279 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
1280 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1281 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1282 s_command.Address = 0U;
1283 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1284 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1285 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1286 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
1287 s_command.NbData = (Rate == MX25LM51245G_DTR_TRANSFER) ? 2U : 1U;
1288 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
1289 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1290
1291 /* Send the command */
1292 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1293 {
1294 return MX25LM51245G_ERROR;
1295 }
1296
1297 /* Reception of the data */
1298 if (HAL_OSPI_Receive(Ctx, Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1299 {
1300 return MX25LM51245G_ERROR;
1301 }
1302
1303 return MX25LM51245G_OK;
1304 }
1305
1306
1307 /* ID Commands ****************************************************************/
1308 /**
1309 * @brief Read Flash 3 Byte IDs.
1310 * Manufacturer ID, Memory type, Memory density
1311 * SPI/OPI; 1-0-1/1-0-8
1312 * @param Ctx Component object pointer
1313 * @param Mode Interface mode
1314 * @param ID 3 bytes IDs pointer
1315 * @param DualFlash Dual flash mode state
1316 * @retval error status
1317 */
MX25LM51245G_ReadID(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate,uint8_t * ID)1318 int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID)
1319 {
1320 OSPI_RegularCmdTypeDef s_command = {0};
1321
1322 /* SPI mode and DTR transfer not supported by memory */
1323 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1324 {
1325 return MX25LM51245G_ERROR;
1326 }
1327
1328 /* Initialize the read ID command */
1329 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1330 #if defined (OCTOSPI_CR_MSEL)
1331 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1332 #else
1333 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1334 #endif
1335 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1336 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1337 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1338 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_READ_ID_CMD : MX25LM51245G_OCTA_READ_ID_CMD;
1339 s_command.AddressMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_ADDRESS_NONE : HAL_OSPI_ADDRESS_8_LINES;
1340 s_command.AddressDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
1341 s_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
1342 s_command.Address = 0U;
1343 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1344 s_command.DataMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_8_LINES;
1345 s_command.DataDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
1346 s_command.DummyCycles = (Mode == MX25LM51245G_SPI_MODE) ? 0U : ((Rate == MX25LM51245G_DTR_TRANSFER) ? DUMMY_CYCLES_REG_OCTAL_DTR : DUMMY_CYCLES_REG_OCTAL);
1347 s_command.NbData = 3U;
1348 s_command.DQSMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
1349 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1350
1351 /* Configure the command */
1352 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1353 {
1354 return MX25LM51245G_ERROR;
1355 }
1356
1357 /* Reception of the data */
1358 if (HAL_OSPI_Receive(Ctx, ID, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1359 {
1360 return MX25LM51245G_ERROR;
1361 }
1362
1363 return MX25LM51245G_OK;
1364 }
1365
1366 /* Reset Commands *************************************************************/
1367 /**
1368 * @brief Flash reset enable command
1369 * SPI/OPI
1370 * @param Ctx Component object pointer
1371 * @param Mode Interface select
1372 * @param Rate Transfer rate STR or DTR
1373 * @retval error status
1374 */
MX25LM51245G_ResetEnable(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)1375 int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
1376 {
1377 OSPI_RegularCmdTypeDef s_command = {0};
1378
1379 /* SPI mode and DTR transfer not supported by memory */
1380 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1381 {
1382 return MX25LM51245G_ERROR;
1383 }
1384
1385 /* Initialize the reset enable command */
1386 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1387 #if defined (OCTOSPI_CR_MSEL)
1388 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1389 #else
1390 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1391 #endif
1392 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1393 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1394 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1395 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_ENABLE_CMD : MX25LM51245G_OCTA_RESET_ENABLE_CMD;
1396 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
1397 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1398 s_command.DataMode = HAL_OSPI_DATA_NONE;
1399 s_command.DummyCycles = 0U;
1400 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1401 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1402
1403 /* Send the command */
1404 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1405 {
1406 return MX25LM51245G_ERROR;
1407 }
1408
1409 return MX25LM51245G_OK;
1410 }
1411
1412 /**
1413 * @brief Flash reset memory command
1414 * SPI/OPI
1415 * @param Ctx Component object pointer
1416 * @param Mode Interface select
1417 * @param Rate Transfer rate STR or DTR
1418 * @retval error status
1419 */
MX25LM51245G_ResetMemory(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)1420 int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
1421 {
1422 OSPI_RegularCmdTypeDef s_command = {0};
1423
1424 /* SPI mode and DTR transfer not supported by memory */
1425 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1426 {
1427 return MX25LM51245G_ERROR;
1428 }
1429
1430 /* Initialize the reset enable command */
1431 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1432 #if defined (OCTOSPI_CR_MSEL)
1433 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1434 #else
1435 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1436 #endif
1437 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1438 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1439 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1440 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_RESET_MEMORY_CMD : MX25LM51245G_OCTA_RESET_MEMORY_CMD;
1441 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
1442 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1443 s_command.DataMode = HAL_OSPI_DATA_NONE;
1444 s_command.DummyCycles = 0U;
1445 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1446 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1447
1448 /* Send the command */
1449 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1450 {
1451 return MX25LM51245G_ERROR;
1452 }
1453
1454 return MX25LM51245G_OK;
1455 }
1456
1457 /**
1458 * @brief Flash no operation command
1459 * SPI/OPI
1460 * @param Ctx Component object pointer
1461 * @param Mode Interface select
1462 * @param Rate Transfer rate STR or DTR
1463 * @retval error status
1464 */
MX25LM51245G_NoOperation(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)1465 int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
1466 {
1467 OSPI_RegularCmdTypeDef s_command = {0};
1468
1469 /* SPI mode and DTR transfer not supported by memory */
1470 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1471 {
1472 return MX25LM51245G_ERROR;
1473 }
1474
1475 /* Initialize the no operation command */
1476 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1477 #if defined (OCTOSPI_CR_MSEL)
1478 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1479 #else
1480 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1481 #endif
1482 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1483 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1484 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1485 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_NOP_CMD : MX25LM51245G_OCTA_NOP_CMD;
1486 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
1487 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1488 s_command.DataMode = HAL_OSPI_DATA_NONE;
1489 s_command.DummyCycles = 0U;
1490 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1491 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1492
1493 /* Send the command */
1494 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1495 {
1496 return MX25LM51245G_ERROR;
1497 }
1498
1499 return MX25LM51245G_OK;
1500 }
1501
1502 /**
1503 * @brief Flash enter deep power-down command
1504 * SPI/OPI
1505 * @param Ctx Component object pointer
1506 * @param Mode Interface select
1507 * @param Rate Transfer rate STR or DTR
1508 * @retval error status
1509 */
MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef * Ctx,MX25LM51245G_Interface_t Mode,MX25LM51245G_Transfer_t Rate)1510 int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate)
1511 {
1512 OSPI_RegularCmdTypeDef s_command = {0};
1513
1514 /* SPI mode and DTR transfer not supported by memory */
1515 if ((Mode == MX25LM51245G_SPI_MODE) && (Rate == MX25LM51245G_DTR_TRANSFER))
1516 {
1517 return MX25LM51245G_ERROR;
1518 }
1519
1520 /* Initialize the enter power down command */
1521 s_command.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
1522 #if defined (OCTOSPI_CR_MSEL)
1523 s_command.FlashSelect = HAL_OSPI_FLASH_SELECT_IO_7_0;
1524 #else
1525 s_command.FlashId = HAL_OSPI_FLASH_ID_1;
1526 #endif
1527 s_command.InstructionMode = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_1_LINE : HAL_OSPI_INSTRUCTION_8_LINES;
1528 s_command.InstructionDtrMode = (Rate == MX25LM51245G_DTR_TRANSFER) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1529 s_command.InstructionSize = (Mode == MX25LM51245G_SPI_MODE) ? HAL_OSPI_INSTRUCTION_8_BITS : HAL_OSPI_INSTRUCTION_16_BITS;
1530 s_command.Instruction = (Mode == MX25LM51245G_SPI_MODE) ? MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD : MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD;
1531 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
1532 s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
1533 s_command.DataMode = HAL_OSPI_DATA_NONE;
1534 s_command.DummyCycles = 0U;
1535 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1536 s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
1537
1538 /* Send the command */
1539 if (HAL_OSPI_Command(Ctx, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1540 {
1541 return MX25LM51245G_ERROR;
1542 }
1543
1544 return MX25LM51245G_OK;
1545 }
1546
1547 /**
1548 * @}
1549 */
1550
1551 /**
1552 * @}
1553 */
1554
1555 /**
1556 * @}
1557 */
1558
1559 /**
1560 * @}
1561 */
1562
1563 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1564
