1 /** 2 ****************************************************************************** 3 * @file mx25lm51245g.h 4 * @modify MCD Application Team 5 * @brief This file contains all the description of the 6 * MX25LM51245G OSPI memory. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2018 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef MX25LM51245G_H 23 #define MX25LM51245G_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "mx25lm51245g_conf.h" 31 32 /** @addtogroup BSP 33 * @{ 34 */ 35 36 /** @addtogroup Components 37 * @{ 38 */ 39 40 /** @addtogroup MX25LM51245G 41 * @{ 42 */ 43 /** @defgroup MX25LM51245G_Exported_Constants MX25LM51245G Exported Constants 44 * @{ 45 */ 46 47 /** 48 * @brief MX25LM51245G Size configuration 49 */ 50 #define MX25LM51245G_SECTOR_64K (uint32_t)(64 * 1024) /* 1024 sectors of 64KBytes */ 51 #define MX25LM51245G_SUBSECTOR_4K (uint32_t)(4 * 1024) /* 16384 subsectors of 4KBytes */ 52 53 #define MX25LM51245G_FLASH_SIZE (uint32_t)(512*1024*1024/8) /* 512 Mbits => 64MBytes */ 54 #define MX25LM51245G_PAGE_SIZE (uint32_t)256 /* 262144 pages of 256 Bytes */ 55 56 /** 57 * @brief MX25LM51245G Timing configuration 58 */ 59 60 #define MX25LM51245G_BULK_ERASE_MAX_TIME 460000U 61 #define MX25LM51245G_SECTOR_ERASE_MAX_TIME 1000U 62 #define MX25LM51245G_SUBSECTOR_4K_ERASE_MAX_TIME 400U 63 #define MX25LM51245G_WRITE_REG_MAX_TIME 40U 64 65 #define MX25LM51245G_RESET_MAX_TIME 100U /* when SWreset during erase operation */ 66 67 #define MX25LM51245G_AUTOPOLLING_INTERVAL_TIME 0x10U 68 69 /** 70 * @brief MX25LM51245G Error codes 71 */ 72 #define MX25LM51245G_OK (0) 73 #define MX25LM51245G_ERROR (-1) 74 75 /** 76 * @brief re-definition of legacy memory mapped functions 77 */ 78 #define MX25LM51245G_EnableMemoryMappedModeDTR MX25LM51245G_EnableDTRMemoryMappedMode 79 #define MX25LM51245G_EnableMemoryMappedModeSTR MX25LM51245G_EnableSTRMemoryMappedMode 80 81 82 /****************************************************************************** 83 * @brief MX25LM51245G Commands 84 ****************************************************************************/ 85 86 /*******************************************************************/ 87 /********************************* SPI ****************************/ 88 /*******************************************************************/ 89 90 /***** READ/WRITE MEMORY Operations with 3-Byte Address ****************************/ 91 #define MX25LM51245G_READ_CMD 0x03U /*!< Normal Read 3 Byte Address */ 92 #define MX25LM51245G_FAST_READ_CMD 0x0BU /*!< Fast Read 3 Byte Address */ 93 #define MX25LM51245G_PAGE_PROG_CMD 0x02U /*!< Page Program 3 Byte Address */ 94 #define MX25LM51245G_SUBSECTOR_ERASE_4K_CMD 0x20U /*!< SubSector Erase 4KB 3 Byte Address */ 95 #define MX25LM51245G_SECTOR_ERASE_64K_CMD 0xD8U /*!< Sector Erase 64KB 3 Byte Address */ 96 #define MX25LM51245G_BULK_ERASE_CMD 0x60U /*!< Bulk Erase */ 97 98 /***** READ/WRITE MEMORY Operations with 4-Byte Address ****************************/ 99 #define MX25LM51245G_4_BYTE_ADDR_READ_CMD 0x13U /*!< Normal Read 4 Byte address */ 100 #define MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD 0x0CU /*!< Fast Read 4 Byte address */ 101 #define MX25LM51245G_4_BYTE_PAGE_PROG_CMD 0x12U /*!< Page Program 4 Byte Address */ 102 #define MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD 0x21U /*!< SubSector Erase 4KB 4 Byte Address */ 103 #define MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD 0xDCU /*!< Sector Erase 64KB 4 Byte Address */ 104 105 /***** Setting commands ************************************************************/ 106 #define MX25LM51245G_WRITE_ENABLE_CMD 0x06U /*!< Write Enable */ 107 #define MX25LM51245G_WRITE_DISABLE_CMD 0x04U /*!< Write Disable */ 108 #define MX25LM51245G_PROG_ERASE_SUSPEND_CMD 0xB0U /*!< Program/Erase suspend */ 109 #define MX25LM51245G_PROG_ERASE_RESUME_CMD 0x30U /*!< Program/Erase resume */ 110 #define MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD 0xB9U /*!< Enter deep power down */ 111 #define MX25LM51245G_SET_BURST_LENGTH_CMD 0xC0U /*!< Set burst length */ 112 #define MX25LM51245G_ENTER_SECURED_OTP_CMD 0xB1U /*!< Enter secured OTP) */ 113 #define MX25LM51245G_EXIT_SECURED_OTP_CMD 0xC1U /*!< Exit secured OTP) */ 114 115 /***** RESET commands ************************************************************/ 116 #define MX25LM51245G_NOP_CMD 0x00U /*!< No operation */ 117 #define MX25LM51245G_RESET_ENABLE_CMD 0x66U /*!< Reset Enable */ 118 #define MX25LM51245G_RESET_MEMORY_CMD 0x99U /*!< Reset Memory */ 119 120 /***** Register Commands (SPI) ****************************************************/ 121 #define MX25LM51245G_READ_ID_CMD 0x9FU /*!< Read IDentification */ 122 #define MX25LM51245G_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AU /*!< Read Serial Flash Discoverable Parameter */ 123 #define MX25LM51245G_READ_STATUS_REG_CMD 0x05U /*!< Read Status Register */ 124 #define MX25LM51245G_READ_CFG_REG_CMD 0x15U /*!< Read configuration Register */ 125 #define MX25LM51245G_WRITE_STATUS_REG_CMD 0x01U /*!< Write Status Register */ 126 #define MX25LM51245G_READ_CFG_REG2_CMD 0x71U /*!< Read configuration Register2 */ 127 #define MX25LM51245G_WRITE_CFG_REG2_CMD 0x72U /*!< Write configuration Register2 */ 128 #define MX25LM51245G_READ_FAST_BOOT_REG_CMD 0x16U /*!< Read fast boot Register */ 129 #define MX25LM51245G_WRITE_FAST_BOOT_REG_CMD 0x17U /*!< Write fast boot Register */ 130 #define MX25LM51245G_ERASE_FAST_BOOT_REG_CMD 0x18U /*!< Erase fast boot Register */ 131 #define MX25LM51245G_READ_SECURITY_REG_CMD 0x2BU /*!< Read security Register */ 132 #define MX25LM51245G_WRITE_SECURITY_REG_CMD 0x2FU /*!< Write security Register */ 133 #define MX25LM51245G_READ_LOCK_REG_CMD 0x2DU /*!< Read lock Register */ 134 #define MX25LM51245G_WRITE_LOCK_REG_CMD 0x2CU /*!< Write lock Register */ 135 136 #define MX25LM51245G_READ_DPB_REG_CMD 0xE0U /*!< Read DPB register */ 137 #define MX25LM51245G_WRITE_DPB_REG_CMD 0xE1U /*!< Write DPB register */ 138 #define MX25LM51245G_READ_SPB_STATUS_CMD 0xE2U /*!< Read SPB status */ 139 #define MX25LM51245G_WRITE_SPB_BIT_CMD 0xE3U /*!< SPB bit program */ 140 #define MX25LM51245G_ERASE_ALL_SPB_CMD 0xE4U /*!< Erase all SPB bit */ 141 #define MX25LM51245G_WRITE_PROTECT_SEL_CMD 0x68U /*!< Write Protect selection */ 142 #define MX25LM51245G_GANG_BLOCK_LOCK_CMD 0x7EU /*!< Gang block lock: whole chip write protect */ 143 #define MX25LM51245G_GANG_BLOCK_UNLOCK_CMD 0x98U /*!< Gang block unlock: whole chip write unprotect */ 144 #define MX25LM51245G_READ_PASSWORD_REGISTER_CMD 0x27U /*!< Read Password */ 145 #define MX25LM51245G_WRITE_PASSWORD_REGISTER_CMD 0x28U /*!< Write Password */ 146 #define MX25LM51245G_PASSWORD_UNLOCK_CMD 0x29U /*!< Unlock Password */ 147 148 149 /*******************************************************************/ 150 /********************************* OPI ****************************/ 151 /*******************************************************************/ 152 153 /***** READ/WRITE MEMORY Operations ****************************/ 154 #define MX25LM51245G_OCTA_READ_CMD 0xEC13U /*!< Octa IO Read */ 155 #define MX25LM51245G_OCTA_READ_DTR_CMD 0xEE11U /*!< Octa IO Read DTR */ 156 #define MX25LM51245G_OCTA_PAGE_PROG_CMD 0x12EDU /*!< Octa Page Program */ 157 #define MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD 0x21DEU /*!< Octa SubSector Erase 4KB */ 158 #define MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD 0xDC23U /*!< Octa Sector Erase 64KB 3 */ 159 #define MX25LM51245G_OCTA_BULK_ERASE_CMD 0x609FU /*!< Octa Bulk Erase */ 160 161 /***** Setting commands ************************************************************/ 162 #define MX25LM51245G_OCTA_WRITE_ENABLE_CMD 0x06F9U /*!< Octa Write Enable */ 163 #define MX25LM51245G_OCTA_WRITE_DISABLE_CMD 0x04FBU /*!< Octa Write Disable */ 164 #define MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD 0xB04FU /*!< Octa Program/Erase suspend */ 165 #define MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD 0x30CFU /*!< Octa Program/Erase resume */ 166 #define MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD 0xB946U /*!< Octa Enter deep power down */ 167 #define MX25LM51245G_OCTA_SET_BURST_LENGTH_CMD 0xC03FU /*!< Octa Set burst length */ 168 #define MX25LM51245G_OCTA_ENTER_SECURED_OTP_CMD 0xB14EU /*!< Octa Enter secured OTP) */ 169 #define MX25LM51245G_OCTA_EXIT_SECURED_OTP_CMD 0xC13EU /*!< Octa Exit secured OTP) */ 170 171 /***** RESET commands ************************************************************/ 172 #define MX25LM51245G_OCTA_NOP_CMD 0x00FFU /*!< Octa No operation */ 173 #define MX25LM51245G_OCTA_RESET_ENABLE_CMD 0x6699U /*!< Octa Reset Enable */ 174 #define MX25LM51245G_OCTA_RESET_MEMORY_CMD 0x9966U /*!< Octa Reset Memory */ 175 176 /***** Register Commands (OPI) ****************************************************/ 177 #define MX25LM51245G_OCTA_READ_ID_CMD 0x9F60U /*!< Octa Read IDentification */ 178 #define MX25LM51245G_OCTA_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AA5U /*!< Octa Read Serial Flash Discoverable Parameter */ 179 #define MX25LM51245G_OCTA_READ_STATUS_REG_CMD 0x05FAU /*!< Octa Read Status Register */ 180 #define MX25LM51245G_OCTA_READ_CFG_REG_CMD 0x15EAU /*!< Octa Read configuration Register */ 181 #define MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD 0x01FEU /*!< Octa Write Status Register */ 182 #define MX25LM51245G_OCTA_READ_CFG_REG2_CMD 0x718EU /*!< Octa Read configuration Register2 */ 183 #define MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD 0x728DU /*!< Octa Write configuration Register2 */ 184 #define MX25LM51245G_OCTA_READ_FAST_BOOT_REG_CMD 0x16E9U /*!< Octa Read fast boot Register */ 185 #define MX25LM51245G_OCTA_WRITE_FAST_BOOT_REG_CMD 0x17E8U /*!< Octa Write fast boot Register */ 186 #define MX25LM51245G_OCTA_ERASE_FAST_BOOT_REG_CMD 0x18E7U /*!< Octa Erase fast boot Register */ 187 #define MX25LM51245G_OCTA_READ_SECURITY_REG_CMD 0x2BD4U /*!< Octa Read security Register */ 188 #define MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD 0x2FD0U /*!< Octa Write security Register */ 189 #define MX25LM51245G_OCTA_READ_LOCK_REG_CMD 0x2DD2U /*!< Octa Read lock Register */ 190 #define MX25LM51245G_OCTA_WRITE_LOCK_REG_CMD 0x2CD3U /*!< Octa Write lock Register */ 191 #define MX25LM51245G_OCTA_READ_DPB_REG_CMD 0xE01FU /*!< Octa Read DPB register */ 192 #define MX25LM51245G_OCTA_WRITE_DPB_REG_CMD 0xE11EU /*!< Octa Write DPB register */ 193 #define MX25LM51245G_OCTA_READ_SPB_STATUS_CMD 0xE21DU /*!< Octa Read SPB status */ 194 #define MX25LM51245G_OCTA_WRITE_SPB_BIT_CMD 0xE31CU /*!< Octa SPB bit program */ 195 #define MX25LM51245G_OCTA_ERASE_ALL_SPB_CMD 0xE41BU /*!< Octa Erase all SPB bit */ 196 #define MX25LM51245G_OCTA_WRITE_PROTECT_SEL_CMD 0x6897U /*!< Octa Write Protect selection */ 197 #define MX25LM51245G_OCTA_GANG_BLOCK_LOCK_CMD 0x7E81U /*!< Octa Gang block lock: whole chip write protect */ 198 #define MX25LM51245G_OCTA_GANG_BLOCK_UNLOCK_CMD 0x9867U /*!< Octa Gang block unlock: whole chip write unprote*/ 199 #define MX25LM51245G_OCTA_READ_PASSWORD_REGISTER_CMD 0x27D8U /*!< Octa Read Password */ 200 #define MX25LM51245G_OCTA_WRITE_PASSWORD_REGISTER_CMD 0x28D7U /*!< Octa Write Password */ 201 #define MX25LM51245G_OCTA_PASSWORD_UNLOCK_CMD 0x29D6U /*!< Octa Unlock Password */ 202 203 /****************************************************************************** 204 * @brief MX25LM51245G Registers 205 ****************************************************************************/ 206 /* Status Register */ 207 #define MX25LM51245G_SR_WIP 0x01U /*!< Write in progress */ 208 #define MX25LM51245G_SR_WEL 0x02U /*!< Write enable latch */ 209 #define MX25LM51245G_SR_PB 0x3CU /*!< Block protected against program and erase operations */ 210 211 /* Configuration Register 1 */ 212 #define MX25LM51245G_CR1_ODS 0x07U /*!< Output driver strength */ 213 #define MX25LM51245G_CR1_TB 0x08U /*!< Top / bottom selected */ 214 #define MX25LM51245G_CR1_PBE 0x10U /*!< Preamble bit enable */ 215 216 /* Configuration Register 2 */ 217 /* Address : 0x00000000 */ 218 #define MX25LM51245G_CR2_REG1_ADDR 0x00000000U /*!< CR2 register address 0x00000000 */ 219 #define MX25LM51245G_CR2_SOPI 0x01U /*!< STR OPI Enable */ 220 #define MX25LM51245G_CR2_DOPI 0x02U /*!< DTR OPI Enable */ 221 /* Address : 0x00000200 */ 222 #define MX25LM51245G_CR2_REG2_ADDR 0x00000200U /*!< CR2 register address 0x00000200 */ 223 #define MX25LM51245G_CR2_DQSPRC 0x01U /*!< DTR DQS pre-cycle */ 224 #define MX25LM51245G_CR2_DOS 0x02U /*!< DQS on STR mode */ 225 /* Address : 0x00000300 */ 226 #define MX25LM51245G_CR2_REG3_ADDR 0x00000300U /*!< CR2 register address 0x00000300 */ 227 #define MX25LM51245G_CR2_DC 0x07U /*!< Dummy cycle */ 228 #define MX25LM51245G_CR2_DC_20_CYCLES 0x00U /*!< 20 Dummy cycles */ 229 #define MX25LM51245G_CR2_DC_18_CYCLES 0x01U /*!< 18 Dummy cycles */ 230 #define MX25LM51245G_CR2_DC_16_CYCLES 0x02U /*!< 16 Dummy cycles */ 231 #define MX25LM51245G_CR2_DC_14_CYCLES 0x03U /*!< 14 Dummy cycles */ 232 #define MX25LM51245G_CR2_DC_12_CYCLES 0x04U /*!< 12 Dummy cycles */ 233 #define MX25LM51245G_CR2_DC_10_CYCLES 0x05U /*!< 10 Dummy cycles */ 234 #define MX25LM51245G_CR2_DC_8_CYCLES 0x06U /*!< 8 Dummy cycles */ 235 #define MX25LM51245G_CR2_DC_6_CYCLES 0x07U /*!< 6 Dummy cycles */ 236 /* Address : 0x00000500 */ 237 #define MX25LM51245G_CR2_REG4_ADDR 0x00000500U /*!< CR2 register address 0x00000500 */ 238 #define MX25LM51245G_CR2_PPTSEL 0x01U /*!< Preamble pattern selection */ 239 /* Address : 0x40000000 */ 240 #define MX25LM51245G_CR2_REG5_ADDR 0x40000000U /*!< CR2 register address 0x40000000 */ 241 #define MX25LM51245G_CR2_DEFSOPI 0x01U /*!< Enable SOPI after power on reset */ 242 #define MX25LM51245G_CR2_DEFDOPI 0x02U /*!< Enable DOPI after power on reset */ 243 244 /* Security Register */ 245 #define MX25LM51245G_SECR_SOI 0x01U /*!< Secured OTP indicator */ 246 #define MX25LM51245G_SECR_LDSO 0x02U /*!< Lock-down secured OTP */ 247 #define MX25LM51245G_SECR_PSB 0x04U /*!< Program suspend bit */ 248 #define MX25LM51245G_SECR_ESB 0x08U /*!< Erase suspend bit */ 249 #define MX25LM51245G_SECR_P_FAIL 0x20U /*!< Program fail flag */ 250 #define MX25LM51245G_SECR_E_FAIL 0x40U /*!< Erase fail flag */ 251 #define MX25LM51245G_SECR_WPSEL 0x80U /*!< Write protection selection */ 252 253 /** 254 * @} 255 */ 256 257 /** @defgroup MX25LM51245G_Exported_Types MX25LM51245G Exported Types 258 * @{ 259 */ 260 typedef struct { 261 uint32_t FlashSize; /*!< Size of the flash */ 262 uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */ 263 uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */ 264 uint32_t EraseSubSectorSize; /*!< Size of subsector for the erase operation */ 265 uint32_t EraseSubSectorNumber; /*!< Number of subsector for the erase operation */ 266 uint32_t EraseSubSector1Size; /*!< Size of subsector 1 for the erase operation */ 267 uint32_t EraseSubSector1Number; /*!< Number of subsector 1 for the erase operation */ 268 uint32_t ProgPageSize; /*!< Size of pages for the program operation */ 269 uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */ 270 } MX25LM51245G_Info_t; 271 272 typedef enum { 273 MX25LM51245G_SPI_MODE = 0, /*!< 1-1-1 commands, Power on H/W default setting */ 274 MX25LM51245G_OPI_MODE /*!< 8-8-8 commands */ 275 } MX25LM51245G_Interface_t; 276 277 typedef enum { 278 MX25LM51245G_STR_TRANSFER = 0, /*!< Single Transfer Rate */ 279 MX25LM51245G_DTR_TRANSFER /*!< Double Transfer Rate */ 280 } MX25LM51245G_Transfer_t; 281 282 typedef enum { 283 MX25LM51245G_ERASE_4K = 0, /*!< 4K size Sector erase */ 284 MX25LM51245G_ERASE_64K, /*!< 64K size Block erase */ 285 MX25LM51245G_ERASE_BULK /*!< Whole bulk erase */ 286 } MX25LM51245G_Erase_t; 287 288 typedef enum { 289 MX25LM51245G_3BYTES_SIZE = 0, /*!< 3 Bytes address mode */ 290 MX25LM51245G_4BYTES_SIZE /*!< 4 Bytes address mode */ 291 } MX25LM51245G_AddressSize_t; 292 293 /** 294 * @} 295 */ 296 297 /** @defgroup MX25LM51245G_Exported_Functions MX25LM51245G Exported Functions 298 * @{ 299 */ 300 /* Function by commands combined */ 301 int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo); 302 int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 303 304 /* Read/Write Array Commands **************************************************/ 305 int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size); 306 int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size); 307 int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size); 308 int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size); 309 int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize); 310 int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 311 int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize); 312 int32_t MX25LM51245G_EnableMemoryMappedModeDTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode); 313 int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 314 int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 315 316 /* Register/Setting Commands **************************************************/ 317 int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 318 int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 319 int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); 320 int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); 321 int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); 322 int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); 323 int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value); 324 int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value); 325 int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value); 326 int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value); 327 328 /* ID/Security Commands *******************************************************/ 329 int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID); 330 331 /* Reset Commands *************************************************************/ 332 int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 333 int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 334 int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 335 int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate); 336 337 /** 338 * @} 339 */ 340 341 #ifdef __cplusplus 342 } 343 #endif 344 345 #endif /* MX25LM51245G_H */ 346 347 /** 348 * @} 349 */ 350 351 /** 352 * @} 353 */ 354 355 /** 356 * @} 357 */ 358 359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 360
