1 /*
2 * Copyright 2021-2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef FSL_MU_H_
8 #define FSL_MU_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup mu
14 * @{
15 */
16
17 /******************************************************************************
18 * Definitions
19 *****************************************************************************/
20
21 /*!
22 * @name Driver version
23 * @{
24 */
25 /*! @brief MU driver version. */
26 #define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
27 /*! @} */
28
29 #define MU_CORE_INTR(intr) ((uint32_t)(intr) << 0U)
30 #define MU_MISC_INTR(intr) ((uint32_t)(intr) << 8U)
31 #define MU_TX_INTR(intr) ((uint32_t)(intr) << 20U)
32 #define MU_RX_INTR(intr) ((uint32_t)(intr) << 24U)
33 #define MU_GI_INTR(intr) ((uint32_t)(intr) << 28U)
34
35 #define MU_GET_CORE_INTR(intrs) (((uint32_t)(intrs) >> 0U) & 0xFFUL)
36 #define MU_GET_TX_INTR(intrs) (((uint32_t)(intrs) >> 20U) & 0xFUL)
37 #define MU_GET_RX_INTR(intrs) (((uint32_t)(intrs) >> 24U) & 0xFUL)
38 #define MU_GET_GI_INTR(intrs) (((uint32_t)(intrs) >> 28U) & 0xFUL)
39
40 #define MU_CORE_FLAG(flag) ((uint32_t)(flag) << 0U)
41 #define MU_STAT_FLAG(flag) ((uint32_t)(flag) << 8U)
42 #define MU_TX_FLAG(flag) ((uint32_t)(flag) << 20U)
43 #define MU_RX_FLAG(flag) ((uint32_t)(flag) << 24U)
44 #define MU_GI_FLAG(flag) ((uint32_t)(flag) << 28U)
45
46 #define MU_GET_CORE_FLAG(flags) (((uint32_t)(flags) >> 0U) & 0xFFUL)
47 #define MU_GET_STAT_FLAG(flags) (((uint32_t)(flags) >> 8U) & 0xFFUL)
48 #define MU_GET_TX_FLAG(flags) (((uint32_t)(flags) >> 20U) & 0xFUL)
49 #define MU_GET_RX_FLAG(flags) (((uint32_t)(flags) >> 24U) & 0xFUL)
50 #define MU_GET_GI_FLAG(flags) (((uint32_t)(flags) >> 28U) & 0xFUL)
51
52 /* General Purpose Interrupts count. */
53 #ifndef FSL_FEATURE_MU_GPI_COUNT
54 #define FSL_FEATURE_MU_GPI_COUNT 4U
55 #endif
56
57 /*!
58 * @brief MU status flags.
59 */
60 enum _mu_status_flags
61 {
62 kMU_Tx0EmptyFlag = MU_TX_FLAG(1UL << 0U), /*!< TX0 empty. */
63 kMU_Tx1EmptyFlag = MU_TX_FLAG(1UL << 1U), /*!< TX1 empty. */
64 kMU_Tx2EmptyFlag = MU_TX_FLAG(1UL << 2U), /*!< TX2 empty. */
65 kMU_Tx3EmptyFlag = MU_TX_FLAG(1UL << 3U), /*!< TX3 empty. */
66
67 kMU_Rx0FullFlag = MU_RX_FLAG(1UL << 0U), /*!< RX0 full. */
68 kMU_Rx1FullFlag = MU_RX_FLAG(1UL << 1U), /*!< RX1 full. */
69 kMU_Rx2FullFlag = MU_RX_FLAG(1UL << 2U), /*!< RX2 full. */
70 kMU_Rx3FullFlag = MU_RX_FLAG(1UL << 3U), /*!< RX3 full. */
71
72 kMU_GenInt0Flag = MU_GI_FLAG(1UL << 0U), /*!< General purpose interrupt 0 pending. */
73 kMU_GenInt1Flag = MU_GI_FLAG(1UL << 1U), /*!< General purpose interrupt 1 pending. */
74 kMU_GenInt2Flag = MU_GI_FLAG(1UL << 2U), /*!< General purpose interrupt 2 pending. */
75 kMU_GenInt3Flag = MU_GI_FLAG(1UL << 3U), /*!< General purpose interrupt 3 pending. */
76
77 #if !(defined(FSL_FEATURE_MU_NO_CEP) && (0 != FSL_FEATURE_MU_NO_CEP))
78 kMU_CoreEventPendingFlag = MU_STAT_FLAG(MU_SR_CEP_MASK), /*!< The other core mode entry event pending. */
79 #endif
80 kMU_RxFullPendingFlag = MU_STAT_FLAG(MU_SR_RFP_MASK), /*!< Any RX full flag is pending. */
81 kMU_TxEmptyPendingFlag = MU_STAT_FLAG(MU_SR_TEP_MASK), /*!< Any TX empty flag is pending. */
82 kMU_GenIntPendingFlag = MU_STAT_FLAG(MU_SR_GIRP_MASK), /*!< Any general interrupt flag is pending. */
83 kMU_EventPendingFlag = MU_STAT_FLAG(MU_SR_EP_MASK), /*!< MU event pending. */
84 kMU_FlagsUpdatingFlag = MU_STAT_FLAG(MU_SR_FUP_MASK), /*!< MU flags update is on-going. */
85 kMU_MuInResetFlag = MU_STAT_FLAG(MU_SR_MURS_MASK), /*!< MU of any side is in reset. */
86
87 #if !(defined(FSL_FEATURE_MU_HAS_SR_MURIP) && (FSL_FEATURE_MU_HAS_SR_MURIP == 0))
88 kMU_MuResetInterruptFlag = MU_STAT_FLAG(MU_SR_MURIP_MASK), /*!< The other side initializes MU reset. */
89 #endif
90
91 #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS))
92 #if !(defined(FSL_FEATURE_MU_HAS_RUN_INT) && (FSL_FEATURE_MU_HAS_RUN_INT == 0))
93 kMU_OtherSideEnterRunInterruptFlag = MU_CORE_FLAG(MU_CSSR0_RUN_MASK), /*!< The other side enters run mode. */
94 #endif
95 #if !(defined(FSL_FEATURE_MU_HAS_HALT_INT) && (FSL_FEATURE_MU_HAS_HALT_INT == 0))
96 kMU_OtherSideEnterHaltInterruptFlag = MU_CORE_FLAG(MU_CSSR0_HALT_MASK), /*!< The other side enters halt mode. */
97 #endif
98 #if !(defined(FSL_FEATURE_MU_HAS_WAIT_INT) && (FSL_FEATURE_MU_HAS_WAIT_INT == 0))
99 kMU_OtherSideEnterWaitInterruptFlag = MU_CORE_FLAG(MU_CSSR0_WAIT_MASK), /*!< The other side enters wait mode. */
100 #endif
101 #if !(defined(FSL_FEATURE_MU_HAS_STOP_INT) && (FSL_FEATURE_MU_HAS_STOP_INT == 0))
102 kMU_OtherSideEnterStopInterruptFlag = MU_CORE_FLAG(MU_CSSR0_STOP_MASK), /*!< The other side enters stop mode. */
103 #endif
104
105 #if !(defined(FSL_FEATURE_MU_HAS_PD_INT) && (FSL_FEATURE_MU_HAS_PD_INT == 0))
106 /*! The other side enters power down mode. */
107 kMU_OtherSideEnterPowerDownInterruptFlag = MU_CORE_FLAG(MU_CSSR0_PD_MASK),
108 #endif
109
110 #if !(defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && (FSL_FEATURE_MU_HAS_RESET_ASSERT_INT == 0))
111 /*! The other core reset assert interrupt. */
112 kMU_ResetAssertInterruptFlag = MU_CORE_FLAG(MU_CSSR0_RAIP_MASK),
113 #endif
114
115 #if !(defined(FSL_FEATURE_MU_HAS_SR_HRIP) && (FSL_FEATURE_MU_HAS_SR_HRIP == 0))
116 /*! Current side has been hardware reset by the other side. */
117 kMU_HardwareResetInterruptFlag = MU_CORE_FLAG(MU_CSSR0_HRIP_MASK),
118 #endif
119 #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */
120 };
121
122 /*!
123 * @brief MU interrupt source to enable.
124 */
125 enum _mu_interrupt_enable
126 {
127 kMU_Tx0EmptyInterruptEnable = MU_TX_INTR(1UL << 0U), /*!< TX0 empty. */
128 kMU_Tx1EmptyInterruptEnable = MU_TX_INTR(1UL << 1U), /*!< TX1 empty. */
129 kMU_Tx2EmptyInterruptEnable = MU_TX_INTR(1UL << 2U), /*!< TX2 empty. */
130 kMU_Tx3EmptyInterruptEnable = MU_TX_INTR(1UL << 3U), /*!< TX3 empty. */
131
132 kMU_Rx0FullInterruptEnable = MU_RX_INTR(1UL << 0U), /*!< RX0 full. */
133 kMU_Rx1FullInterruptEnable = MU_RX_INTR(1UL << 1U), /*!< RX1 full. */
134 kMU_Rx2FullInterruptEnable = MU_RX_INTR(1UL << 2U), /*!< RX2 full. */
135 kMU_Rx3FullInterruptEnable = MU_RX_INTR(1UL << 3U), /*!< RX3 full. */
136
137 kMU_GenInt0InterruptEnable = MU_GI_INTR(1UL << 0U), /*!< General purpose interrupt 0. */
138 kMU_GenInt1InterruptEnable = MU_GI_INTR(1UL << 1U), /*!< General purpose interrupt 1. */
139 kMU_GenInt2InterruptEnable = MU_GI_INTR(1UL << 2U), /*!< General purpose interrupt 2. */
140 kMU_GenInt3InterruptEnable = MU_GI_INTR(1UL << 3U), /*!< General purpose interrupt 3. */
141
142 #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS))
143 #if !(defined(FSL_FEATURE_MU_HAS_RUN_INT) && (FSL_FEATURE_MU_HAS_RUN_INT == 0))
144 kMU_OtherSideEnterRunInterruptEnable = MU_CORE_INTR(MU_CIER0_RUNIE_MASK), /*!< The other side enters run mode. */
145 #endif
146 #if !(defined(FSL_FEATURE_MU_HAS_HALT_INT) && (FSL_FEATURE_MU_HAS_HALT_INT == 0))
147 kMU_OtherSideEnterHaltInterruptEnable = MU_CORE_INTR(MU_CIER0_HALTIE_MASK), /*!< The other side enters halt mode. */
148 #endif
149 #if !(defined(FSL_FEATURE_MU_HAS_WAIT_INT) && (FSL_FEATURE_MU_HAS_WAIT_INT == 0))
150 kMU_OtherSideEnterWaitInterruptEnable = MU_CORE_INTR(MU_CIER0_WAITIE_MASK), /*!< The other side enters wait mode. */
151 #endif
152 #if !(defined(FSL_FEATURE_MU_HAS_STOP_INT) && (FSL_FEATURE_MU_HAS_STOP_INT == 0))
153 kMU_OtherSideEnterStopInterruptEnable = MU_CORE_INTR(MU_CIER0_STOPIE_MASK), /*!< The other side enters stop mode. */
154 #endif
155
156 #if !(defined(FSL_FEATURE_MU_HAS_PD_INT) && (FSL_FEATURE_MU_HAS_PD_INT == 0))
157 /*! The other side enters power down mode. */
158 kMU_OtherSideEnterPowerDownInterruptEnable = MU_CORE_INTR(MU_CIER0_PDIE_MASK),
159 #endif
160
161 #if !(defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && (FSL_FEATURE_MU_HAS_RESET_ASSERT_INT == 0))
162 /*! The other core reset assert interrupt. */
163 kMU_ResetAssertInterruptEnable = MU_CORE_INTR(MU_CIER0_RAIE_MASK),
164 #endif
165
166 #if !(defined(FSL_FEATURE_MU_HAS_SR_HRIP) && (FSL_FEATURE_MU_HAS_SR_HRIP == 0))
167 /*! Current side has been hardware reset by the other side. */
168 kMU_HardwareResetInterruptEnable = MU_CORE_INTR(MU_CIER0_HRIE_MASK),
169 #endif
170 #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */
171
172 #if !(defined(FSL_FEATURE_MU_HAS_SR_MURIP) && (FSL_FEATURE_MU_HAS_SR_MURIP == 0))
173 kMU_MuResetInterruptEnable = MU_MISC_INTR(MU_CR_MURIE_MASK), /*!< The other side initializes MU reset. */
174 #endif
175 };
176
177 /*!
178 * @brief MU interrupt that could be triggered to the other core.
179 */
180 enum _mu_interrupt_trigger
181 {
182 kMU_GenInt0InterruptTrigger = MU_GI_INTR(1UL << 0U), /*!< General purpose interrupt 0. */
183 kMU_GenInt1InterruptTrigger = MU_GI_INTR(1UL << 1U), /*!< General purpose interrupt 1. */
184 kMU_GenInt2InterruptTrigger = MU_GI_INTR(1UL << 2U), /*!< General purpose interrupt 2. */
185 kMU_GenInt3InterruptTrigger = MU_GI_INTR(1UL << 3U), /*!< General purpose interrupt 3. */
186 };
187
188 #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS))
189 /*!
190 * @brief MU core status flags.
191 */
192 enum _mu_core_status_flags
193 {
194 #if !(defined(FSL_FEATURE_MU_HAS_RUN_INT) && (FSL_FEATURE_MU_HAS_RUN_INT == 0))
195 kMU_OtherSideEnterRunFlag = MU_CSSR0_RUN_MASK, /*!< The other side in run mode. */
196 #endif
197
198 #if !(defined(FSL_FEATURE_MU_HAS_HALT_INT) && (FSL_FEATURE_MU_HAS_HALT_INT == 0))
199 kMU_OtherSideEnterHaltFlag = MU_CSSR0_HALT_MASK, /*!< The other side in halt mode. */
200 #endif
201
202 #if !(defined(FSL_FEATURE_MU_HAS_WAIT_INT) && (FSL_FEATURE_MU_HAS_WAIT_INT == 0))
203 kMU_OtherSideEnterWaitFlag = MU_CSSR0_WAIT_MASK, /*!< The other side in wait mode. */
204 #endif
205
206 #if !(defined(FSL_FEATURE_MU_HAS_STOP_INT) && (FSL_FEATURE_MU_HAS_STOP_INT == 0))
207 kMU_OtherSideEnterStopFlag = MU_CSSR0_STOP_MASK, /*!< The other side in stop mode. */
208 #endif
209
210 #if !(defined(FSL_FEATURE_MU_HAS_PD_INT) && (FSL_FEATURE_MU_HAS_PD_INT == 0))
211 kMU_OtherSideEnterPowerDownFlag = MU_CSSR0_PD_MASK, /*!< The other side in power down mode. */
212 #endif
213
214 #if !(defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && (FSL_FEATURE_MU_HAS_RESET_ASSERT_INT == 0))
215 kMU_OtherSideEnterResetFlag = MU_CSSR0_RAIP_MASK, /*!< The other core entered reset. */
216 #endif
217
218 #if !(defined(FSL_FEATURE_MU_HAS_SR_HRIP) && (FSL_FEATURE_MU_HAS_SR_HRIP == 0))
219 kMU_HardwareResetFlag = MU_CSSR0_HRIP_MASK, /*!< Current side has been hardware reset by the other side. */
220 #endif
221 };
222 #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */
223
224 /*!
225 * @brief MU message register index.
226 */
227 typedef enum _mu_msg_reg_index
228 {
229 kMU_MsgReg0 = 0, /*!< Message register 0. */
230 kMU_MsgReg1, /*!< Message register 1. */
231 kMU_MsgReg2, /*!< Message register 2. */
232 kMU_MsgReg3, /*!< Message register 3. */
233 } mu_msg_reg_index_t;
234
235 #if (defined(FSL_FEATURE_MU_HAS_BOOT) && (0 == FSL_FEATURE_MU_HAS_BOOT))
236 /*!
237 * @brief The other core boot mode.
238 */
239 typedef enum _mu_core_boot_mode
240 {
241 kMU_CoreBootModeDummy = 0x0U, /*!< MU doesn't support boot mode selection, only for API compatibility. */
242 } mu_core_boot_mode_t;
243 #endif
244
245 /*!
246 * @brief MU general purpose interrupts
247 */
248 typedef enum _mu_general_purpose_interrupt
249 {
250 kMU_GeneralPurposeInterrupt0 = 1UL << 0U, /*!< General purpose interrupt 0 */
251 kMU_GeneralPurposeInterrupt1 = 1UL << 1U, /*!< General purpose interrupt 1 */
252 kMU_GeneralPurposeInterrupt2 = 1UL << 2U, /*!< General purpose interrupt 2 */
253 kMU_GeneralPurposeInterrupt3 = 1UL << 3U, /*!< General purpose interrupt 3 */
254 #if (FSL_FEATURE_MU_GPI_COUNT > 4U)
255 kMU_GeneralPurposeInterrupt4 = 1UL << 4U, /*!< General purpose interrupt 4 */
256 #endif
257 #if (FSL_FEATURE_MU_GPI_COUNT > 5U)
258 kMU_GeneralPurposeInterrupt5 = 1UL << 5U, /*!< General purpose interrupt 5 */
259 #endif
260 #if (FSL_FEATURE_MU_GPI_COUNT > 6U)
261 kMU_GeneralPurposeInterrupt6 = 1UL << 6U, /*!< General purpose interrupt 6 */
262 #endif
263 #if (FSL_FEATURE_MU_GPI_COUNT > 7U)
264 kMU_GeneralPurposeInterrupt7 = 1UL << 7U, /*!< General purpose interrupt 7 */
265 #endif
266 #if (FSL_FEATURE_MU_GPI_COUNT > 8U)
267 kMU_GeneralPurposeInterrupt8 = 1UL << 8U, /*!< General purpose interrupt 8 */
268 #endif
269 #if (FSL_FEATURE_MU_GPI_COUNT > 9U)
270 kMU_GeneralPurposeInterrupt9 = 1UL << 9U, /*!< General purpose interrupt 9 */
271 #endif
272 #if (FSL_FEATURE_MU_GPI_COUNT > 10U)
273 kMU_GeneralPurposeInterrupt10 = 1UL << 10U, /*!< General purpose interrupt 10 */
274 #endif
275 #if (FSL_FEATURE_MU_GPI_COUNT > 11U)
276 kMU_GeneralPurposeInterrupt11 = 1UL << 11U, /*!< General purpose interrupt 11 */
277 #endif
278 #if (FSL_FEATURE_MU_GPI_COUNT > 12U)
279 kMU_GeneralPurposeInterrupt12 = 1UL << 12U, /*!< General purpose interrupt 12 */
280 #endif
281 #if (FSL_FEATURE_MU_GPI_COUNT > 13U)
282 kMU_GeneralPurposeInterrupt13 = 1UL << 13U, /*!< General purpose interrupt 13 */
283 #endif
284 #if (FSL_FEATURE_MU_GPI_COUNT > 14U)
285 kMU_GeneralPurposeInterrupt14 = 1UL << 14U, /*!< General purpose interrupt 14 */
286 #endif
287 #if (FSL_FEATURE_MU_GPI_COUNT > 15U)
288 kMU_GeneralPurposeInterrupt15 = 1UL << 15U, /*!< General purpose interrupt 15 */
289 #endif
290 #if (FSL_FEATURE_MU_GPI_COUNT > 16U)
291 kMU_GeneralPurposeInterrupt16 = 1UL << 16U, /*!< General purpose interrupt 16 */
292 #endif
293 #if (FSL_FEATURE_MU_GPI_COUNT > 17U)
294 kMU_GeneralPurposeInterrupt17 = 1UL << 17U, /*!< General purpose interrupt 17 */
295 #endif
296 #if (FSL_FEATURE_MU_GPI_COUNT > 18U)
297 kMU_GeneralPurposeInterrupt18 = 1UL << 18U, /*!< General purpose interrupt 18 */
298 #endif
299 #if (FSL_FEATURE_MU_GPI_COUNT > 19U)
300 kMU_GeneralPurposeInterrupt19 = 1UL << 19U, /*!< General purpose interrupt 19 */
301 #endif
302 #if (FSL_FEATURE_MU_GPI_COUNT > 20U)
303 kMU_GeneralPurposeInterrupt20 = 1UL << 20U, /*!< General purpose interrupt 20 */
304 #endif
305 #if (FSL_FEATURE_MU_GPI_COUNT > 21U)
306 kMU_GeneralPurposeInterrupt21 = 1UL << 21U, /*!< General purpose interrupt 21 */
307 #endif
308 #if (FSL_FEATURE_MU_GPI_COUNT > 22U)
309 kMU_GeneralPurposeInterrupt22 = 1UL << 22U, /*!< General purpose interrupt 22 */
310 #endif
311 #if (FSL_FEATURE_MU_GPI_COUNT > 23U)
312 kMU_GeneralPurposeInterrupt23 = 1UL << 23U, /*!< General purpose interrupt 23 */
313 #endif
314 #if (FSL_FEATURE_MU_GPI_COUNT > 24U)
315 kMU_GeneralPurposeInterrupt24 = 1UL << 24U, /*!< General purpose interrupt 24 */
316 #endif
317 #if (FSL_FEATURE_MU_GPI_COUNT > 25U)
318 kMU_GeneralPurposeInterrupt25 = 1UL << 25U, /*!< General purpose interrupt 25 */
319 #endif
320 #if (FSL_FEATURE_MU_GPI_COUNT > 26U)
321 kMU_GeneralPurposeInterrupt26 = 1UL << 26U, /*!< General purpose interrupt 26 */
322 #endif
323 #if (FSL_FEATURE_MU_GPI_COUNT > 27U)
324 kMU_GeneralPurposeInterrupt27 = 1UL << 27U, /*!< General purpose interrupt 27 */
325 #endif
326 #if (FSL_FEATURE_MU_GPI_COUNT > 28U)
327 kMU_GeneralPurposeInterrupt28 = 1UL << 28U, /*!< General purpose interrupt 28 */
328 #endif
329 #if (FSL_FEATURE_MU_GPI_COUNT > 29U)
330 kMU_GeneralPurposeInterrupt29 = 1UL << 29U, /*!< General purpose interrupt 29 */
331 #endif
332 #if (FSL_FEATURE_MU_GPI_COUNT > 30U)
333 kMU_GeneralPurposeInterrupt30 = 1UL << 30U, /*!< General purpose interrupt 30 */
334 #endif
335 #if (FSL_FEATURE_MU_GPI_COUNT > 31U)
336 kMU_GeneralPurposeInterrupt31 = 1UL << 31U, /*!< General purpose interrupt 31 */
337 #endif
338 } mu_general_purpose_interrupt_t;
339
340 /*******************************************************************************
341 * API
342 ******************************************************************************/
343
344 #if defined(__cplusplus)
345 extern "C" {
346 #endif
347
348 /*!
349 * @name MU instance.
350 * @{
351 */
352
353 /*!
354 * @brief Get the MU instance index.
355 *
356 * @param base MU peripheral base address.
357 * @return MU instance index.
358 */
359 uint32_t MU_GetInstance(MU_Type *base);
360 /*! @} */
361
362 /*!
363 * @name MU initialization.
364 * @{
365 */
366 /*!
367 * @brief Initializes the MU module.
368 *
369 * This function enables the MU clock only.
370 *
371 * @param base MU peripheral base address.
372 */
373 void MU_Init(MU_Type *base);
374
375 /*!
376 * @brief De-initializes the MU module.
377 *
378 * This function disables the MU clock only.
379 *
380 * @param base MU peripheral base address.
381 */
382 void MU_Deinit(MU_Type *base);
383
384 /*! @} */
385
386 /*!
387 * @name MU Message
388 * @{
389 */
390
391 /*!
392 * @brief Writes a message to the TX register.
393 *
394 * This function writes a message to the specific TX register. It does not check
395 * whether the TX register is empty or not. The upper layer should make sure the TX
396 * register is empty before calling this function. This function can be used
397 * in ISR for better performance.
398 *
399 * @code
400 * while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty.
401 * MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL); Write message to the TX0 register.
402 * @endcode
403 *
404 * @param base MU peripheral base address.
405 * @param regIndex TX register index, see @ref mu_msg_reg_index_t.
406 * @param msg Message to send.
407 */
MU_SendMsgNonBlocking(MU_Type * base,uint32_t regIndex,uint32_t msg)408 static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)
409 {
410 assert(regIndex < MU_TR_COUNT);
411
412 base->TR[regIndex] = msg;
413 }
414
415 /*!
416 * @brief Blocks to send a message.
417 *
418 * This function waits until the TX register is empty and sends the message.
419 *
420 * @param base MU peripheral base address.
421 * @param regIndex MU message register, see @ref mu_msg_reg_index_t.
422 * @param msg Message to send.
423 */
424 void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg);
425
426 /*!
427 * @brief Reads a message from the RX register.
428 *
429 * This function reads a message from the specific RX register. It does not check
430 * whether the RX register is full or not. The upper layer should make sure the RX
431 * register is full before calling this function. This function can be used
432 * in ISR for better performance.
433 *
434 * @code
435 * uint32_t msg;
436 * while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
437 * {
438 * } Wait for the RX0 register full.
439 *
440 * msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0); Read message from RX0 register.
441 * @endcode
442 *
443 * @param base MU peripheral base address.
444 * @param regIndex RX register index, see @ref mu_msg_reg_index_t.
445 * @return The received message.
446 */
MU_ReceiveMsgNonBlocking(MU_Type * base,uint32_t regIndex)447 static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)
448 {
449 assert(regIndex < MU_TR_COUNT);
450
451 return base->RR[regIndex];
452 }
453
454 /*!
455 * @brief Blocks to receive a message.
456 *
457 * This function waits until the RX register is full and receives the message.
458 *
459 * @param base MU peripheral base address.
460 * @param regIndex MU message register, see @ref mu_msg_reg_index_t
461 * @return The received message.
462 */
463 uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex);
464
465 /*! @} */
466
467 /*!
468 * @name MU Flags
469 * @{
470 */
471
472 /*!
473 * @brief Sets the 3-bit MU flags reflect on the other MU side.
474 *
475 * This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed,
476 * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are
477 * updating to the other side. After the 3-bit MU flags are updated, the status flag
478 * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period,
479 * the flags cannot be changed. The upper layer should make sure the status flag
480 * \c kMU_FlagsUpdatingFlag is cleared before calling this function.
481 *
482 * @code
483 * while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
484 * {
485 * } Wait for previous MU flags updating.
486 *
487 * MU_SetFlagsNonBlocking(base, 0U); Set the mU flags.
488 * @endcode
489 *
490 * @param base MU peripheral base address.
491 * @param flags The 3-bit MU flags to set.
492 */
MU_SetFlagsNonBlocking(MU_Type * base,uint32_t flags)493 static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)
494 {
495 base->FCR = flags;
496 }
497
498 /*!
499 * @brief Blocks setting the 3-bit MU flags reflect on the other MU side.
500 *
501 * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed,
502 * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are
503 * updating to the other side. After the 3-bit MU flags are updated, the status flag
504 * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period,
505 * the flags cannot be changed. This function waits for the MU status flag
506 * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.
507 *
508 * @param base MU peripheral base address.
509 * @param flags The 3-bit MU flags to set.
510 */
511 void MU_SetFlags(MU_Type *base, uint32_t flags);
512
513 /*!
514 * @brief Gets the current value of the 3-bit MU flags set by the other side.
515 *
516 * This function gets the current 3-bit MU flags on the current side.
517 *
518 * @param base MU peripheral base address.
519 * @return flags Current value of the 3-bit flags.
520 */
MU_GetFlags(MU_Type * base)521 static inline uint32_t MU_GetFlags(MU_Type *base)
522 {
523 return base->FSR;
524 }
525
526 /*! @} */
527
528 /*!
529 * @name Status and Interrupt.
530 * @{
531 */
532
533 #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS))
534 /*!
535 * @brief Gets the MU core status flags.
536 *
537 * @param base MU peripheral base address.
538 * @return Bit mask of the MU status flags, see @ref _mu_core_status_flags.
539 */
MU_GetCoreStatusFlags(MU_Type * base)540 static inline uint32_t MU_GetCoreStatusFlags(MU_Type *base)
541 {
542 return base->CSR0;
543 }
544 #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */
545
546 /*!
547 * @brief Gets the MU status flags.
548 *
549 * This function returns the bit mask of the MU status flags. See _mu_status_flags.
550 *
551 * @code
552 * uint32_t flags;
553 * flags = MU_GetStatusFlags(base); Get all status flags.
554 * if (kMU_Tx0EmptyFlag & flags)
555 * {
556 * The TX0 register is empty. Message can be sent.
557 * MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
558 * }
559 * if (kMU_Tx1EmptyFlag & flags)
560 * {
561 * The TX1 register is empty. Message can be sent.
562 * MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
563 * }
564 * @endcode
565 *
566 * If there are more than 4 general purpose interrupts, use @ref MU_GetGeneralPurposeStatusFlags.
567 *
568 * @param base MU peripheral base address.
569 * @return Bit mask of the MU status flags, see _mu_status_flags.
570 */
571 uint32_t MU_GetStatusFlags(MU_Type *base);
572
573 /*!
574 * @brief Clears the specific MU status flags.
575 *
576 * This function clears the specific MU status flags. The flags to clear should
577 * be passed in as bit mask. See _mu_status_flags.
578 *
579 * @code
580 * Clear general interrupt 0 and general interrupt 1 pending flags.
581 * MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);
582 * @endcode
583 *
584 * If there are more than 4 general purpose interrupts, use @ref MU_ClearGeneralPurposeStatusFlags.
585 *
586 * @param base MU peripheral base address.
587 * @param flags Bit mask of the MU status flags. See _mu_status_flags. Only the
588 * following flags can be cleared by software, other flags are cleared by hardware:
589 * - #kMU_GenInt0Flag
590 * - #kMU_GenInt1Flag
591 * - #kMU_GenInt2Flag
592 * - #kMU_GenInt3Flag
593 * - #kMU_MuResetInterruptFlag
594 * - #kMU_OtherSideEnterRunInterruptFlag
595 * - #kMU_OtherSideEnterHaltInterruptFlag
596 * - #kMU_OtherSideEnterWaitInterruptFlag
597 * - #kMU_OtherSideEnterStopInterruptFlag
598 * - #kMU_OtherSideEnterPowerDownInterruptFlag
599 * - #kMU_ResetAssertInterruptFlag
600 * - #kMU_HardwareResetInterruptFlag
601 */
MU_ClearStatusFlags(MU_Type * base,uint32_t flags)602 static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)
603 {
604 uint32_t tmp;
605
606 /* General interrupt tmp. */
607 tmp = MU_GET_GI_FLAG(flags);
608 if (0U != tmp)
609 {
610 base->GSR = tmp;
611 }
612
613 #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS))
614 /* Core interrupt. */
615 tmp = MU_GET_CORE_FLAG(flags);
616 if (0U != tmp)
617 {
618 base->CSSR0 = tmp;
619 }
620 #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */
621
622 #if !(defined(FSL_FEATURE_MU_HAS_SR_MURIP) && (FSL_FEATURE_MU_HAS_SR_MURIP == 0))
623 /* kMU_MuResetInterruptFlag. */
624 if (0U != ((uint32_t)kMU_MuResetInterruptFlag & flags))
625 {
626 base->SR = MU_SR_MURIP_MASK;
627 }
628 #endif
629 }
630
631 /*!
632 * @brief Enables the specific MU interrupts.
633 *
634 * This function enables the specific MU interrupts. The interrupts to enable
635 * should be passed in as bit mask. See _mu_interrupt_enable.
636 *
637 * @code
638 * Enable general interrupt 0 and TX0 empty interrupt.
639 * MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
640 * @endcode
641 *
642 * If there are more than 4 general purpose interrupts, use @ref MU_EnableGeneralPurposeInterrupts.
643 *
644 * @param base MU peripheral base address.
645 * @param interrupts Bit mask of the MU interrupts. See _mu_interrupt_enable.
646 */
MU_EnableInterrupts(MU_Type * base,uint32_t interrupts)647 static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)
648 {
649 uint32_t tmp;
650
651 /* TX message interrupts. */
652 tmp = MU_GET_TX_INTR(interrupts);
653 if (0U != tmp)
654 {
655 base->TCR |= tmp;
656 }
657
658 /* RX message interrupts. */
659 tmp = MU_GET_RX_INTR(interrupts);
660 if (0U != tmp)
661 {
662 base->RCR |= tmp;
663 }
664
665 /* General purpose interrupts. */
666 tmp = MU_GET_GI_INTR(interrupts);
667 if (0U != tmp)
668 {
669 base->GIER |= tmp;
670 }
671
672 /* Core interrupts. */
673 tmp = MU_GET_CORE_INTR(interrupts);
674 if (0U != tmp)
675 {
676 base->CIER0 |= tmp;
677 }
678
679 #if !(defined(FSL_FEATURE_MU_HAS_SR_MURIP) && (FSL_FEATURE_MU_HAS_SR_MURIP == 0))
680 if (0U != ((uint32_t)kMU_MuResetInterruptEnable & interrupts))
681 {
682 base->CR |= MU_CR_MURIE_MASK;
683 }
684 #endif
685 }
686
687 /*!
688 * @brief Disables the specific MU interrupts.
689 *
690 * This function disables the specific MU interrupts. The interrupts to disable
691 * should be passed in as bit mask. See _mu_interrupt_enable.
692 *
693 * @code
694 * Disable general interrupt 0 and TX0 empty interrupt.
695 * MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);
696 * @endcode
697 *
698 * If there are more than 4 general purpose interrupts, use @ref MU_DisableGeneralPurposeInterrupts.
699 *
700 * @param base MU peripheral base address.
701 * @param interrupts Bit mask of the MU interrupts. See _mu_interrupt_enable.
702 */
MU_DisableInterrupts(MU_Type * base,uint32_t interrupts)703 static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)
704 {
705 uint32_t tmp;
706
707 /* TX message interrupts. */
708 tmp = MU_GET_TX_INTR(interrupts);
709 if (0U != tmp)
710 {
711 base->TCR &= ~tmp;
712 }
713
714 /* RX message interrupts. */
715 tmp = MU_GET_RX_INTR(interrupts);
716 if (0U != tmp)
717 {
718 base->RCR &= ~tmp;
719 }
720
721 /* General purpose interrupts. */
722 tmp = MU_GET_GI_INTR(interrupts);
723 if (0U != tmp)
724 {
725 base->GIER &= ~tmp;
726 }
727
728 /* Core interrupts. */
729 tmp = MU_GET_CORE_INTR(interrupts);
730 if (0U != tmp)
731 {
732 base->CIER0 &= ~tmp;
733 }
734
735 #if !(defined(FSL_FEATURE_MU_HAS_SR_MURIP) && (FSL_FEATURE_MU_HAS_SR_MURIP == 0))
736 if (0U != ((uint32_t)kMU_MuResetInterruptEnable & interrupts))
737 {
738 base->CR &= ~MU_CR_MURIE_MASK;
739 }
740 #endif
741 }
742
743 /*!
744 * @brief Triggers interrupts to the other core.
745 *
746 * This function triggers the specific interrupts to the other core. The interrupts
747 * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger.
748 * The MU should not trigger an interrupt to the other core when the previous interrupt
749 * has not been processed by the other core. This function checks whether the
750 * previous interrupts have been processed. If not, it returns an error.
751 *
752 * @code
753 * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
754 * {
755 * Previous general purpose interrupt 0 or general purpose interrupt 2
756 * has not been processed by the other core.
757 * }
758 * @endcode
759 *
760 * If there are more than 4 general purpose interrupts, use @ref MU_TriggerGeneralPurposeInterrupts.
761 *
762 * @param base MU peripheral base address.
763 * @param interrupts Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.
764 * @retval kStatus_Success Interrupts have been triggered successfully.
765 * @retval kStatus_Fail Previous interrupts have not been accepted.
766 */
767 status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts);
768
769 #if !(defined(FSL_FEATURE_MU_NO_NMI) && (0 != FSL_FEATURE_MU_NO_NMI))
770 /*!
771 * @brief Triggers NMI to the other core.
772 *
773 * This function triggers the NMI to the other core.
774 * The MU should not trigger NMI to the other core when the previous interrupt
775 * has not been processed by the other core. This function checks whether the
776 * previous interrupts have been processed. If not, it returns an error.
777 *
778 * @param base MU peripheral base address.
779 * @retval kStatus_Success Interrupts have been triggered successfully.
780 * @retval kStatus_Fail Previous interrupts have not been accepted.
781 */
782 status_t MU_TriggerNmi(MU_Type *base);
783
784 /*!
785 * @brief Clear non-maskable interrupt (NMI) sent by the other core.
786 *
787 * This function clears non-maskable interrupt (NMI) sent by the other core.
788 *
789 * @param base MU peripheral base address.
790 */
MU_ClearNmi(MU_Type * base)791 static inline void MU_ClearNmi(MU_Type *base)
792 {
793 base->CSSR0 = MU_CSSR0_NMIC_MASK;
794 }
795 #endif /* FSL_FEATURE_MU_NO_NMI */
796
797 /*! @} */
798
799 /*!
800 * @name MU general purpose interrupt
801 * @{
802 */
803
804 /*!
805 * @brief Enables the MU general purpose interrupts.
806 *
807 * This function enables the MU general purpose interrupts. The interrupts
808 * to enable should be passed in as bit mask of @ref mu_general_purpose_interrupt_t.
809 * The function @ref MU_EnableInterrupts only support general interrupt 0~3,
810 * this function supports all general interrupts.
811 *
812 * For example, to enable general purpose interrupt 0 and 3, use like this:
813 * @code
814 MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);
815 @endcode
816 *
817 * @param base MU peripheral base address.
818 * @param interrupts Bit mask of the MU general purpose interrupts,
819 * see @ref mu_general_purpose_interrupt_t.
820 */
MU_EnableGeneralPurposeInterrupts(MU_Type * base,uint32_t interrupts)821 static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)
822 {
823 base->GIER |= interrupts;
824 }
825
826 /*!
827 * @brief Disables the MU general purpose interrupts.
828 *
829 * This function disables the MU general purpose interrupts. The interrupts
830 * to disable should be passed in as bit mask of @ref mu_general_purpose_interrupt_t.
831 * The function @ref MU_DisableInterrupts only support general interrupt 0~3,
832 * this function supports all general interrupts.
833 *
834 * For example, to disable general purpose interrupt 0 and 3, use like this:
835 * @code
836 MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);
837 @endcode
838 *
839 * @param base MU peripheral base address.
840 * @param interrupts Bit mask of the MU general purpose interrupts.
841 * see @ref mu_general_purpose_interrupt_t.
842 */
MU_DisableGeneralPurposeInterrupts(MU_Type * base,uint32_t interrupts)843 static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)
844 {
845 base->GIER &= ~interrupts;
846 }
847
848 /*!
849 * @brief Gets the MU general purpose interrupt status flags.
850 *
851 * This function returns the bit mask of the MU general purpose interrupt status flags.
852 * @ref MU_GetStatusFlags can only get general purpose interrupt status 0~3,
853 * this function can get all general purpose interrupts status.
854 *
855 * This example shows to check whether general purpose interrupt 0 and 3 happened.
856 *
857 * @code
858 uint32_t flags;
859 flags = MU_GetGeneralPurposeStatusFlags(base);
860 if (kMU_GeneralPurposeInterrupt0 & flags)
861 {
862 }
863 if (kMU_GeneralPurposeInterrupt3 & flags)
864 {
865 }
866 @endcode
867 *
868 * @param base MU peripheral base address.
869 * @return Bit mask of the MU general purpose interrupt status flags.
870 */
MU_GetGeneralPurposeStatusFlags(MU_Type * base)871 static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)
872 {
873 return base->GSR;
874 }
875
876 /*!
877 * @brief Clear the MU general purpose interrupt status flags.
878 *
879 * This function clears the specific MU general purpose interrupt status flags. The flags to clear should
880 * be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.
881 *
882 * Example to clear general purpose interrupt 0 and general interrupt 1 pending flags.
883 * @code
884 MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);
885 @endcode
886 *
887 * @param base MU peripheral base address.
888 * @param flags Bit mask of the MU general purpose interrupt status flags.
889 * See @ref mu_general_purpose_interrupt_t.
890 */
MU_ClearGeneralPurposeStatusFlags(MU_Type * base,uint32_t flags)891 static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)
892 {
893 base->GSR = flags;
894 }
895
896 /*!
897 * @brief Triggers general purpose interrupts to the other core.
898 *
899 * This function triggers the specific general purpose interrupts to the other core.
900 * The interrupts to trigger are passed in as bit mask. See @ref mu_general_purpose_interrupt_t.
901 * The MU should not trigger an interrupt to the other core when the previous interrupt
902 * has not been processed by the other core. This function checks whether the
903 * previous interrupts have been processed. If not, it returns an error.
904 *
905 * @code
906 status_t status;
907 status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2);
908
909 if (kStatus_Success != status)
910 {
911 Previous general purpose interrupt 0 or general purpose interrupt 2
912 has not been processed by the other core.
913 }
914 @endcode
915 *
916 * @param base MU peripheral base address.
917 * @param interrupts Bit mask of the interrupts to trigger. See @ref mu_general_purpose_interrupt_t.
918 * @retval kStatus_Success Interrupts have been triggered successfully.
919 * @retval kStatus_Fail Previous interrupts have not been accepted.
920 */
921 status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts);
922
923 /*! @} */
924
925 /*!
926 * @name MU misc functions
927 * @{
928 */
929
930 #if !(defined(FSL_FEATURE_MU_HAS_BOOT) && (0 == FSL_FEATURE_MU_HAS_BOOT))
931 /*!
932 * @brief Boots the other core.
933 *
934 * This function boots the other core with a boot configuration.
935 *
936 * @param base MU peripheral base address.
937 * @param mode The other core boot mode.
938 */
939 void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode);
940 #endif /* FSL_FEATURE_MU_HAS_BOOT */
941
942 #if !(defined(FSL_FEATURE_MU_HAS_RSTH) && (0 == FSL_FEATURE_MU_HAS_RSTH))
943 /*!
944 * @brief Holds the other core reset.
945 *
946 * This function causes the other core to be held in reset following any reset event.
947 *
948 * @param base MU peripheral base address.
949 */
950 void MU_HoldOtherCoreReset(MU_Type *base);
951 #endif /* FSL_FEATURE_MU_HAS_RSTH */
952
953 /*!
954 * @brief Resets the MU for both A side and B side.
955 *
956 * This function resets the MU for both A side and B side. Before reset, it is
957 * recommended to interrupt processor B, because this function may affect the
958 * ongoing processor B programs.
959 *
960 * @param base MU peripheral base address.
961 */
MU_ResetBothSides(MU_Type * base)962 static inline void MU_ResetBothSides(MU_Type *base)
963 {
964 base->CR |= MU_CR_MUR_MASK;
965
966 while (0U != (base->SR & MU_SR_MURS_MASK))
967 {
968 }
969 }
970
971 #if !(defined(FSL_FEATURE_MU_NO_CLKE) && (0 != FSL_FEATURE_MU_NO_CLKE))
972 /*!
973 * @brief Enables or disables the clock on the other core.
974 *
975 * This function enables or disables the platform clock on the other core when
976 * that core enters a stop mode. If disabled, the platform clock for the other
977 * core is disabled when it enters stop mode. If enabled, the platform clock
978 * keeps running on the other core in stop mode, until this core also enters
979 * stop mode.
980 *
981 * @param base MU peripheral base address.
982 * @param enable Enable or disable the clock on the other core.
983 */
MU_SetClockOnOtherCoreEnable(MU_Type * base,bool enable)984 static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable)
985 {
986 if (enable)
987 {
988 base->CCR0 |= MU_CCR0_CLKE_MASK;
989 }
990 else
991 {
992 base->CCR0 &= ~MU_CCR0_CLKE_MASK;
993 }
994 }
995 #endif
996
997 #if !(defined(FSL_FEATURE_MU_HAS_HR) && (FSL_FEATURE_MU_HAS_HR == 0))
998 /*!
999 * @brief Hardware reset the other core.
1000 *
1001 * This function resets the other core, the other core could mask the
1002 * hardware reset by calling MU_MaskHardwareReset. The hardware reset
1003 * mask feature is only available for some platforms.
1004 * This function could be used together with MU_BootOtherCore to control the
1005 * other core reset workflow.
1006 *
1007 * Example 1: Reset the other core, and no hold reset
1008 * @code
1009 * MU_HardwareResetOtherCore(MU_A, true, false, bootMode);
1010 * @endcode
1011 * In this example, the core at MU side B will reset with the specified boot mode.
1012 *
1013 * Example 2: Reset the other core and hold it, then boot the other core later.
1014 * @code
1015 * Here the other core enters reset, and the reset is hold
1016 * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);
1017 * Current core boot the other core when necessary.
1018 * MU_BootOtherCore(MU_A, bootMode);
1019 * @endcode
1020 *
1021 * @note The feature waitReset, holdReset, and bootMode might be not supported
1022 * for some platforms. waitReset is only available for platforms that
1023 * FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and
1024 * FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available
1025 * for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0.
1026 * bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not
1027 * defined as 0.
1028 *
1029 * @param base MU peripheral base address.
1030 * @param waitReset Wait the other core enters reset. Only work when there is CSSR0[RAIP]
1031 * - true: Wait until the other core enters reset, if the other
1032 * core has masked the hardware reset, then this function will
1033 * be blocked.
1034 * - false: Don't wait the reset.
1035 * @param holdReset Hold the other core reset or not. Only work when there is CCR0[RSTH]
1036 * - true: Hold the other core in reset, this function returns
1037 * directly when the other core enters reset.
1038 * - false: Don't hold the other core in reset, this function
1039 * waits until the other core out of reset.
1040 * @param bootMode Boot mode of the other core, if @p holdReset is true, this
1041 * parameter is useless.
1042 */
1043 void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode);
1044 #endif /* FSL_FEATURE_MU_HAS_HR */
1045
1046 #if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM)
1047 /*!
1048 * @brief Mask hardware reset by the other core.
1049 *
1050 * The other core could call MU_HardwareResetOtherCore() to reset current core.
1051 * To mask the reset, call this function and pass in true.
1052 *
1053 * @param base MU peripheral base address.
1054 * @param mask Pass true to mask the hardware reset, pass false to unmask it.
1055 */
MU_MaskHardwareReset(MU_Type * base,bool mask)1056 static inline void MU_MaskHardwareReset(MU_Type *base, bool mask)
1057 {
1058 #if !(defined(FSL_FEATURE_MU_NO_NMI) && (0 != FSL_FEATURE_MU_NO_NMI))
1059 if (mask)
1060 {
1061 base->CCR0 |= (base->CCR0 & ~(MU_CCR0_HR_MASK | MU_CCR0_NMI_MASK)) | MU_CCR0_HRM_MASK;
1062 }
1063 else
1064 {
1065 base->CCR0 |= (base->CCR0 & ~(MU_CCR0_HR_MASK | MU_CCR0_NMI_MASK | MU_CCR0_HRM_MASK));
1066 }
1067 #else
1068 if (mask)
1069 {
1070 base->CCR0 |= (base->CCR0 & ~(MU_CCR0_HR_MASK)) | MU_CCR0_HRM_MASK;
1071 }
1072 else
1073 {
1074 base->CCR0 |= (base->CCR0 & ~(MU_CCR0_HR_MASK | MU_CCR0_HRM_MASK));
1075 }
1076 #endif
1077 }
1078 #endif /* FSL_FEATURE_MU_HAS_HRM */
1079
1080 /*! @} */
1081
1082 #if defined(__cplusplus)
1083 }
1084 #endif /*_cplusplus*/
1085 /*! @} */
1086
1087 #endif /* FSL_MU_H_*/
1088
