1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MC_CGM.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_MC_CGM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MC_CGM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MC_CGM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_CGM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_CGM_Peripheral_Access_Layer MC_CGM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_CGM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PCFS_SDUR; /**< PCFS Step Duration, offset: 0x0 */ 74 uint8_t RESERVED_0[132]; 75 __IO uint32_t PCFS_DIVC12; /**< PCFS Divider Change 12 Register, offset: 0x88, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3 (missing on MC_CGM_2, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 76 __IO uint32_t PCFS_DIVE12; /**< PCFS Divider End 12 Register, offset: 0x8C, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3 (missing on MC_CGM_2, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 77 __IO uint32_t PCFS_DIVS12; /**< PCFS Divider Start 12 Register, offset: 0x90, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3 (missing on MC_CGM_2, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 78 uint8_t RESERVED_1[24]; 79 __IO uint32_t PCFS_DIVC15; /**< PCFS Divider Change 15 Register, offset: 0xAC, available only on: MC_CGM_2, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_6) */ 80 __IO uint32_t PCFS_DIVE15; /**< PCFS Divider End 15 Register, offset: 0xB0, available only on: MC_CGM_2, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_6) */ 81 __IO uint32_t PCFS_DIVS15; /**< PCFS Divider Start 15 Register, offset: 0xB4, available only on: MC_CGM_2, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_6) */ 82 uint8_t RESERVED_2[288]; 83 __IO uint32_t PCFS_DIVC40; /**< PCFS Divider Change 40 Register, offset: 0x1D8, available only on: MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5) */ 84 __IO uint32_t PCFS_DIVE40; /**< PCFS Divider End 40 Register, offset: 0x1DC, available only on: MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5) */ 85 __IO uint32_t PCFS_DIVS40; /**< PCFS Divider Start 40 Register, offset: 0x1E0, available only on: MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5) */ 86 uint8_t RESERVED_3[284]; 87 __IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset: 0x300 */ 88 __I uint32_t MUX_0_CSS; /**< Clock Mux 0 Select Status Register, offset: 0x304 */ 89 __IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offset: 0x308, available only on: MC_CGM_5, MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4) */ 90 __IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offset: 0x30C, available only on: MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5) */ 91 uint8_t RESERVED_4[44]; 92 __I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, offset: 0x33C, available only on: MC_CGM_5, MC_CGM_6 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4) */ 93 __IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset: 0x340 */ 94 __I uint32_t MUX_1_CSS; /**< Clock Mux 1 Select Status Register, offset: 0x344 */ 95 __IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offset: 0x348 */ 96 __IO uint32_t MUX_1_DC_1; /**< Clock Mux 1 Divider 1 Control Register, offset: 0x34C, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 97 uint8_t RESERVED_5[44]; 98 __I uint32_t MUX_1_DIV_UPD_STAT; /**< Clock Mux 1 Divider Update Status Register, offset: 0x37C */ 99 __IO uint32_t MUX_2_CSC; /**< Clock Mux 2 Select Control Register, offset: 0x380, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_6) */ 100 __I uint32_t MUX_2_CSS; /**< Clock Mux 2 Select Status Register, offset: 0x384, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_6) */ 101 __IO uint32_t MUX_2_DC_0; /**< Clock Mux 2 Divider 0 Control Register, offset: 0x388, available only on: MC_CGM_0, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_6) */ 102 __IO uint32_t MUX_2_DC_1; /**< Clock Mux 2 Divider 1 Control Register, offset: 0x38C, available only on: MC_CGM_0, MC_CGM_3, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_5, MC_CGM_6) */ 103 __IO uint32_t MUX_2_DC_2; /**< Clock Mux 2 Divider 2 Control Register, offset: 0x390, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 104 __IO uint32_t MUX_2_DC_3; /**< Clock Mux 2 Divider 3 Control Register, offset: 0x394, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 105 __IO uint32_t MUX_2_DC_4; /**< Clock Mux 2 Divider 4 Control Register, offset: 0x398, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 106 __IO uint32_t MUX_2_DC_5; /**< Clock Mux 2 Divider 5 Control Register, offset: 0x39C, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 107 uint8_t RESERVED_6[28]; 108 __I uint32_t MUX_2_DIV_UPD_STAT; /**< Clock Mux 2 Divider Update Status Register, offset: 0x3BC, available only on: MC_CGM_0, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_6) */ 109 __IO uint32_t MUX_3_CSC; /**< Clock Mux 3 Select Control Register, offset: 0x3C0, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_6) */ 110 __I uint32_t MUX_3_CSS; /**< Clock Mux 3 Select Status Register, offset: 0x3C4, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_6) */ 111 __IO uint32_t MUX_3_DC_0; /**< Clock Mux 3 Divider 0 Control Register, offset: 0x3C8, available only on: MC_CGM_0, MC_CGM_3, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_5, MC_CGM_6) */ 112 __IO uint32_t MUX_3_DC_1; /**< Clock Mux 3 Divider 1 Control Register, offset: 0x3CC, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 113 __IO uint32_t MUX_3_DC_2; /**< Clock Mux 3 Divider 2 Control Register, offset: 0x3D0, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 114 __IO uint32_t MUX_3_DC_3; /**< Clock Mux 3 Divider 3 Control Register, offset: 0x3D4, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 115 __IO uint32_t MUX_3_DC_4; /**< Clock Mux 3 Divider 4 Control Register, offset: 0x3D8, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 116 __IO uint32_t MUX_3_DC_5; /**< Clock Mux 3 Divider 5 Control Register, offset: 0x3DC, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 117 __IO uint32_t MUX_3_DC_6; /**< Clock Mux 3 Divider 6 Control Register, offset: 0x3E0, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 118 __IO uint32_t MUX_3_DC_7; /**< Clock Mux 3 Divider 7 Control Register, offset: 0x3E4, available only on: MC_CGM_0, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 119 uint8_t RESERVED_7[20]; 120 __I uint32_t MUX_3_DIV_UPD_STAT; /**< Clock Mux 3 Divider Update Status Register, offset: 0x3FC, available only on: MC_CGM_0, MC_CGM_3, MC_CGM_4 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_5, MC_CGM_6) */ 121 __IO uint32_t MUX_4_CSC; /**< Clock Mux 4 Select Control Register, offset: 0x400, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_6) */ 122 __I uint32_t MUX_4_CSS; /**< Clock Mux 4 Select Status Register, offset: 0x404, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_6) */ 123 __IO uint32_t MUX_4_DC_0; /**< Clock Mux 4 Divider 0 Control Register, offset: 0x408, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_4, MC_CGM_6) */ 124 uint8_t RESERVED_8[48]; 125 __I uint32_t MUX_4_DIV_UPD_STAT; /**< Clock Mux 4 Divider Update Status Register, offset: 0x43C, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_3, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_4, MC_CGM_6) */ 126 __IO uint32_t MUX_5_CSC; /**< Clock Mux 5 Select Control Register, offset: 0x440, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_6) */ 127 __I uint32_t MUX_5_CSS; /**< Clock Mux 5 Select Status Register, offset: 0x444, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4, MC_CGM_5 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_6) */ 128 __IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offset: 0x448, available only on: MC_CGM_1, MC_CGM_5 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_6) */ 129 __IO uint32_t MUX_5_DC_1; /**< Clock Mux 5 Divider 1 Control Register, offset: 0x44C, available only on: MC_CGM_5 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_6) */ 130 __IO uint32_t MUX_5_DC_2; /**< Clock Mux 5 Divider 2 Control Register, offset: 0x450, available only on: MC_CGM_5 (missing on MC_CGM_0, MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_6) */ 131 uint8_t RESERVED_9[40]; 132 __I uint32_t MUX_5_DIV_UPD_STAT; /**< Clock Mux 5 Divider Update Status Register, offset: 0x47C, available only on: MC_CGM_1, MC_CGM_5 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_6) */ 133 __IO uint32_t MUX_6_CSC; /**< Clock Mux 6 Select Control Register, offset: 0x480, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 134 __I uint32_t MUX_6_CSS; /**< Clock Mux 6 Select Status Register, offset: 0x484, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 135 __IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offset: 0x488, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 136 __IO uint32_t MUX_6_DC_1; /**< Clock Mux 6 Divider 1 Control Register, offset: 0x48C, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 137 uint8_t RESERVED_10[44]; 138 __I uint32_t MUX_6_DIV_UPD_STAT; /**< Clock Mux 6 Divider Update Status Register, offset: 0x4BC, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 139 __IO uint32_t MUX_7_CSC; /**< Clock Mux 7 Select Control Register, offset: 0x4C0, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 140 __I uint32_t MUX_7_CSS; /**< Clock Mux 7 Select Status Register, offset: 0x4C4, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 141 __IO uint32_t MUX_7_DC_0; /**< Clock Mux 7 Divider 0 Control Register, offset: 0x4C8, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 142 __IO uint32_t MUX_7_DC_1; /**< Clock Mux 7 Divider 1 Control Register, offset: 0x4CC, available only on: MC_CGM_0, MC_CGM_1 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 143 __IO uint32_t MUX_7_DC_2; /**< Clock Mux 7 Divider 2 Control Register, offset: 0x4D0, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 144 uint8_t RESERVED_11[32]; 145 __IO uint32_t MUX_7_DIV_TRIG_CTRL; /**< Clock Mux 7 Divider Trigger Control Register, offset: 0x4F4, available only on: MC_CGM_0 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 146 __O uint32_t MUX_7_DIV_TRIG; /**< Clock Mux 7 Divider Trigger Register, offset: 0x4F8, available only on: MC_CGM_0 (missing on MC_CGM_1, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 147 __I uint32_t MUX_7_DIV_UPD_STAT; /**< Clock Mux 7 Divider Update Status Register, offset: 0x4FC, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 148 __IO uint32_t MUX_8_CSC; /**< Clock Mux 8 Select Control Register, offset: 0x500, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 149 __I uint32_t MUX_8_CSS; /**< Clock Mux 8 Select Status Register, offset: 0x504, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 150 __IO uint32_t MUX_8_DC_0; /**< Clock Mux 8 Divider 0 Control Register, offset: 0x508, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 151 __IO uint32_t MUX_8_DC_1; /**< Clock Mux 8 Divider 1 Control Register, offset: 0x50C, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 152 uint8_t RESERVED_12[44]; 153 __I uint32_t MUX_8_DIV_UPD_STAT; /**< Clock Mux 8 Divider Update Status Register, offset: 0x53C, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 154 __IO uint32_t MUX_9_CSC; /**< Clock Mux 9 Select Control Register, offset: 0x540, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 155 __I uint32_t MUX_9_CSS; /**< Clock Mux 9 Select Status Register, offset: 0x544, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 156 __IO uint32_t MUX_9_DC_0; /**< Clock Mux 9 Divider 0 Control Register, offset: 0x548, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 157 __IO uint32_t MUX_9_DC_1; /**< Clock Mux 9 Divider 1 Control Register, offset: 0x54C, available only on: MC_CGM_1, MC_CGM_4 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 158 __IO uint32_t MUX_9_DC_2; /**< Clock Mux 9 Divider 2 Control Register, offset: 0x550, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 159 uint8_t RESERVED_13[40]; 160 __I uint32_t MUX_9_DIV_UPD_STAT; /**< Clock Mux 9 Divider Update Status Register, offset: 0x57C, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 161 __IO uint32_t MUX_10_CSC; /**< Clock Mux 10 Select Control Register, offset: 0x580, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 162 __I uint32_t MUX_10_CSS; /**< Clock Mux 10 Select Status Register, offset: 0x584, available only on: MC_CGM_0, MC_CGM_1, MC_CGM_4 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 163 __IO uint32_t MUX_10_DC_0; /**< Clock Mux 10 Divider 0 Control Register, offset: 0x588, available only on: MC_CGM_0, MC_CGM_1 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 164 uint8_t RESERVED_14[48]; 165 __I uint32_t MUX_10_DIV_UPD_STAT; /**< Clock Mux 10 Divider Update Status Register, offset: 0x5BC, available only on: MC_CGM_0, MC_CGM_1 (missing on MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 166 __IO uint32_t MUX_11_CSC; /**< Clock Mux 11 Select Control Register, offset: 0x5C0, available only on: MC_CGM_1, MC_CGM_4 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 167 __I uint32_t MUX_11_CSS; /**< Clock Mux 11 Select Status Register, offset: 0x5C4, available only on: MC_CGM_1, MC_CGM_4 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_5, MC_CGM_6) */ 168 __IO uint32_t MUX_11_DC_0; /**< Clock Mux 11 Divider 0 Control Register, offset: 0x5C8, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 169 uint8_t RESERVED_15[48]; 170 __I uint32_t MUX_11_DIV_UPD_STAT; /**< Clock Mux 11 Divider Update Status Register, offset: 0x5FC, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 171 __IO uint32_t MUX_12_CSC; /**< Clock Mux 12 Select Control Register, offset: 0x600, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 172 __I uint32_t MUX_12_CSS; /**< Clock Mux 12 Select Status Register, offset: 0x604, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 173 __IO uint32_t MUX_12_DC_0; /**< Clock Mux 12 Divider 0 Control Register, offset: 0x608, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 174 uint8_t RESERVED_16[48]; 175 __I uint32_t MUX_12_DIV_UPD_STAT; /**< Clock Mux 12 Divider Update Status Register, offset: 0x63C, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 176 __IO uint32_t MUX_13_CSC; /**< Clock Mux 13 Select Control Register, offset: 0x640, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 177 __I uint32_t MUX_13_CSS; /**< Clock Mux 13 Select Status Register, offset: 0x644, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 178 uint8_t RESERVED_17[56]; 179 __IO uint32_t MUX_14_CSC; /**< Clock Mux 14 Select Control Register, offset: 0x680, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 180 __I uint32_t MUX_14_CSS; /**< Clock Mux 14 Select Status Register, offset: 0x684, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 181 __IO uint32_t MUX_14_DC_0; /**< Clock Mux 14 Divider 0 Control Register, offset: 0x688, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 182 uint8_t RESERVED_18[48]; 183 __I uint32_t MUX_14_DIV_UPD_STAT; /**< Clock Mux 14 Divider Update Status Register, offset: 0x6BC, available only on: MC_CGM_1 (missing on MC_CGM_0, MC_CGM_2, MC_CGM_3, MC_CGM_4, MC_CGM_5, MC_CGM_6) */ 184 } MC_CGM_Type, *MC_CGM_MemMapPtr; 185 186 /** Number of instances of the MC_CGM module. */ 187 #define MC_CGM_INSTANCE_COUNT (7u) 188 189 /* MC_CGM - Peripheral instance base addresses */ 190 /** Peripheral MC_CGM_0 base address */ 191 #define IP_MC_CGM_0_BASE (0x40030000u) 192 /** Peripheral MC_CGM_0 base pointer */ 193 #define IP_MC_CGM_0 ((MC_CGM_Type *)IP_MC_CGM_0_BASE) 194 /** Peripheral MC_CGM_1 base address */ 195 #define IP_MC_CGM_1_BASE (0x40830000u) 196 /** Peripheral MC_CGM_1 base pointer */ 197 #define IP_MC_CGM_1 ((MC_CGM_Type *)IP_MC_CGM_1_BASE) 198 /** Peripheral MC_CGM_2 base address */ 199 #define IP_MC_CGM_2_BASE (0x41030000u) 200 /** Peripheral MC_CGM_2 base pointer */ 201 #define IP_MC_CGM_2 ((MC_CGM_Type *)IP_MC_CGM_2_BASE) 202 /** Peripheral MC_CGM_3 base address */ 203 #define IP_MC_CGM_3_BASE (0x41830000u) 204 /** Peripheral MC_CGM_3 base pointer */ 205 #define IP_MC_CGM_3 ((MC_CGM_Type *)IP_MC_CGM_3_BASE) 206 /** Peripheral MC_CGM_4 base address */ 207 #define IP_MC_CGM_4_BASE (0x42030000u) 208 /** Peripheral MC_CGM_4 base pointer */ 209 #define IP_MC_CGM_4 ((MC_CGM_Type *)IP_MC_CGM_4_BASE) 210 /** Peripheral MC_CGM_5 base address */ 211 #define IP_MC_CGM_5_BASE (0x42830000u) 212 /** Peripheral MC_CGM_5 base pointer */ 213 #define IP_MC_CGM_5 ((MC_CGM_Type *)IP_MC_CGM_5_BASE) 214 /** Peripheral MC_CGM_6 base address */ 215 #define IP_MC_CGM_6_BASE (0x44030000u) 216 /** Peripheral MC_CGM_6 base pointer */ 217 #define IP_MC_CGM_6 ((MC_CGM_Type *)IP_MC_CGM_6_BASE) 218 /** Array initializer of MC_CGM peripheral base addresses */ 219 #define IP_MC_CGM_BASE_ADDRS { IP_MC_CGM_0_BASE, IP_MC_CGM_1_BASE, IP_MC_CGM_2_BASE, IP_MC_CGM_3_BASE, IP_MC_CGM_4_BASE, IP_MC_CGM_5_BASE, IP_MC_CGM_6_BASE } 220 /** Array initializer of MC_CGM peripheral base pointers */ 221 #define IP_MC_CGM_BASE_PTRS { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM_3, IP_MC_CGM_4, IP_MC_CGM_5, IP_MC_CGM_6 } 222 223 /* ---------------------------------------------------------------------------- 224 -- MC_CGM Register Masks 225 ---------------------------------------------------------------------------- */ 226 227 /*! 228 * @addtogroup MC_CGM_Register_Masks MC_CGM Register Masks 229 * @{ 230 */ 231 232 /*! @name PCFS_SDUR - PCFS Step Duration */ 233 /*! @{ */ 234 235 #define MC_CGM_PCFS_SDUR_SDUR_MASK (0xFFFFU) 236 #define MC_CGM_PCFS_SDUR_SDUR_SHIFT (0U) 237 #define MC_CGM_PCFS_SDUR_SDUR_WIDTH (16U) 238 #define MC_CGM_PCFS_SDUR_SDUR(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_SDUR_SDUR_SHIFT)) & MC_CGM_PCFS_SDUR_SDUR_MASK) 239 /*! @} */ 240 241 /*! @name PCFS_DIVC12 - PCFS Divider Change 12 Register */ 242 /*! @{ */ 243 244 #define MC_CGM_PCFS_DIVC12_RATE_MASK (0xFFU) 245 #define MC_CGM_PCFS_DIVC12_RATE_SHIFT (0U) 246 #define MC_CGM_PCFS_DIVC12_RATE_WIDTH (8U) 247 #define MC_CGM_PCFS_DIVC12_RATE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC12_RATE_SHIFT)) & MC_CGM_PCFS_DIVC12_RATE_MASK) 248 249 #define MC_CGM_PCFS_DIVC12_INIT_MASK (0xFFFF0000U) 250 #define MC_CGM_PCFS_DIVC12_INIT_SHIFT (16U) 251 #define MC_CGM_PCFS_DIVC12_INIT_WIDTH (16U) 252 #define MC_CGM_PCFS_DIVC12_INIT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC12_INIT_SHIFT)) & MC_CGM_PCFS_DIVC12_INIT_MASK) 253 /*! @} */ 254 255 /*! @name PCFS_DIVE12 - PCFS Divider End 12 Register */ 256 /*! @{ */ 257 258 #define MC_CGM_PCFS_DIVE12_DIVE_MASK (0xFFFFFU) 259 #define MC_CGM_PCFS_DIVE12_DIVE_SHIFT (0U) 260 #define MC_CGM_PCFS_DIVE12_DIVE_WIDTH (20U) 261 #define MC_CGM_PCFS_DIVE12_DIVE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVE12_DIVE_SHIFT)) & MC_CGM_PCFS_DIVE12_DIVE_MASK) 262 /*! @} */ 263 264 /*! @name PCFS_DIVS12 - PCFS Divider Start 12 Register */ 265 /*! @{ */ 266 267 #define MC_CGM_PCFS_DIVS12_DIVS_MASK (0xFFFFFU) 268 #define MC_CGM_PCFS_DIVS12_DIVS_SHIFT (0U) 269 #define MC_CGM_PCFS_DIVS12_DIVS_WIDTH (20U) 270 #define MC_CGM_PCFS_DIVS12_DIVS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVS12_DIVS_SHIFT)) & MC_CGM_PCFS_DIVS12_DIVS_MASK) 271 /*! @} */ 272 273 /*! @name PCFS_DIVC15 - PCFS Divider Change 15 Register */ 274 /*! @{ */ 275 276 #define MC_CGM_PCFS_DIVC15_RATE_MASK (0xFFU) 277 #define MC_CGM_PCFS_DIVC15_RATE_SHIFT (0U) 278 #define MC_CGM_PCFS_DIVC15_RATE_WIDTH (8U) 279 #define MC_CGM_PCFS_DIVC15_RATE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC15_RATE_SHIFT)) & MC_CGM_PCFS_DIVC15_RATE_MASK) 280 281 #define MC_CGM_PCFS_DIVC15_INIT_MASK (0xFFFF0000U) 282 #define MC_CGM_PCFS_DIVC15_INIT_SHIFT (16U) 283 #define MC_CGM_PCFS_DIVC15_INIT_WIDTH (16U) 284 #define MC_CGM_PCFS_DIVC15_INIT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC15_INIT_SHIFT)) & MC_CGM_PCFS_DIVC15_INIT_MASK) 285 /*! @} */ 286 287 /*! @name PCFS_DIVE15 - PCFS Divider End 15 Register */ 288 /*! @{ */ 289 290 #define MC_CGM_PCFS_DIVE15_DIVE_MASK (0xFFFFFU) 291 #define MC_CGM_PCFS_DIVE15_DIVE_SHIFT (0U) 292 #define MC_CGM_PCFS_DIVE15_DIVE_WIDTH (20U) 293 #define MC_CGM_PCFS_DIVE15_DIVE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVE15_DIVE_SHIFT)) & MC_CGM_PCFS_DIVE15_DIVE_MASK) 294 /*! @} */ 295 296 /*! @name PCFS_DIVS15 - PCFS Divider Start 15 Register */ 297 /*! @{ */ 298 299 #define MC_CGM_PCFS_DIVS15_DIVS_MASK (0xFFFFFU) 300 #define MC_CGM_PCFS_DIVS15_DIVS_SHIFT (0U) 301 #define MC_CGM_PCFS_DIVS15_DIVS_WIDTH (20U) 302 #define MC_CGM_PCFS_DIVS15_DIVS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVS15_DIVS_SHIFT)) & MC_CGM_PCFS_DIVS15_DIVS_MASK) 303 /*! @} */ 304 305 /*! @name PCFS_DIVC40 - PCFS Divider Change 40 Register */ 306 /*! @{ */ 307 308 #define MC_CGM_PCFS_DIVC40_RATE_MASK (0xFFU) 309 #define MC_CGM_PCFS_DIVC40_RATE_SHIFT (0U) 310 #define MC_CGM_PCFS_DIVC40_RATE_WIDTH (8U) 311 #define MC_CGM_PCFS_DIVC40_RATE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC40_RATE_SHIFT)) & MC_CGM_PCFS_DIVC40_RATE_MASK) 312 313 #define MC_CGM_PCFS_DIVC40_INIT_MASK (0xFFFF0000U) 314 #define MC_CGM_PCFS_DIVC40_INIT_SHIFT (16U) 315 #define MC_CGM_PCFS_DIVC40_INIT_WIDTH (16U) 316 #define MC_CGM_PCFS_DIVC40_INIT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC40_INIT_SHIFT)) & MC_CGM_PCFS_DIVC40_INIT_MASK) 317 /*! @} */ 318 319 /*! @name PCFS_DIVE40 - PCFS Divider End 40 Register */ 320 /*! @{ */ 321 322 #define MC_CGM_PCFS_DIVE40_DIVE_MASK (0xFFFFFU) 323 #define MC_CGM_PCFS_DIVE40_DIVE_SHIFT (0U) 324 #define MC_CGM_PCFS_DIVE40_DIVE_WIDTH (20U) 325 #define MC_CGM_PCFS_DIVE40_DIVE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVE40_DIVE_SHIFT)) & MC_CGM_PCFS_DIVE40_DIVE_MASK) 326 /*! @} */ 327 328 /*! @name PCFS_DIVS40 - PCFS Divider Start 40 Register */ 329 /*! @{ */ 330 331 #define MC_CGM_PCFS_DIVS40_DIVS_MASK (0xFFFFFU) 332 #define MC_CGM_PCFS_DIVS40_DIVS_SHIFT (0U) 333 #define MC_CGM_PCFS_DIVS40_DIVS_WIDTH (20U) 334 #define MC_CGM_PCFS_DIVS40_DIVS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVS40_DIVS_SHIFT)) & MC_CGM_PCFS_DIVS40_DIVS_MASK) 335 /*! @} */ 336 337 /*! @name MUX_0_CSC - Clock Mux 0 Select Control Register */ 338 /*! @{ */ 339 340 #define MC_CGM_MUX_0_CSC_RAMPUP_MASK (0x1U) 341 #define MC_CGM_MUX_0_CSC_RAMPUP_SHIFT (0U) 342 #define MC_CGM_MUX_0_CSC_RAMPUP_WIDTH (1U) 343 #define MC_CGM_MUX_0_CSC_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_RAMPUP_SHIFT)) & MC_CGM_MUX_0_CSC_RAMPUP_MASK) 344 345 #define MC_CGM_MUX_0_CSC_RAMPDOWN_MASK (0x2U) 346 #define MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT (1U) 347 #define MC_CGM_MUX_0_CSC_RAMPDOWN_WIDTH (1U) 348 #define MC_CGM_MUX_0_CSC_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT)) & MC_CGM_MUX_0_CSC_RAMPDOWN_MASK) 349 350 #define MC_CGM_MUX_0_CSC_CLK_SW_MASK (0x4U) 351 #define MC_CGM_MUX_0_CSC_CLK_SW_SHIFT (2U) 352 #define MC_CGM_MUX_0_CSC_CLK_SW_WIDTH (1U) 353 #define MC_CGM_MUX_0_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_0_CSC_CLK_SW_MASK) 354 355 #define MC_CGM_MUX_0_CSC_SAFE_SW_MASK (0x8U) 356 #define MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT (3U) 357 #define MC_CGM_MUX_0_CSC_SAFE_SW_WIDTH (1U) 358 #define MC_CGM_MUX_0_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_0_CSC_SAFE_SW_MASK) 359 360 #define MC_CGM_MUX_0_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ 361 #define MC_CGM_MUX_0_CSC_SELCTL_SHIFT (24U) 362 #define MC_CGM_MUX_0_CSC_SELCTL_WIDTH (6U) 363 #define MC_CGM_MUX_0_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_0_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ 364 /*! @} */ 365 366 /*! @name MUX_0_CSS - Clock Mux 0 Select Status Register */ 367 /*! @{ */ 368 369 #define MC_CGM_MUX_0_CSS_RAMPUP_MASK (0x1U) 370 #define MC_CGM_MUX_0_CSS_RAMPUP_SHIFT (0U) 371 #define MC_CGM_MUX_0_CSS_RAMPUP_WIDTH (1U) 372 #define MC_CGM_MUX_0_CSS_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_RAMPUP_SHIFT)) & MC_CGM_MUX_0_CSS_RAMPUP_MASK) 373 374 #define MC_CGM_MUX_0_CSS_RAMPDOWN_MASK (0x2U) 375 #define MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT (1U) 376 #define MC_CGM_MUX_0_CSS_RAMPDOWN_WIDTH (1U) 377 #define MC_CGM_MUX_0_CSS_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT)) & MC_CGM_MUX_0_CSS_RAMPDOWN_MASK) 378 379 #define MC_CGM_MUX_0_CSS_CLK_SW_MASK (0x4U) 380 #define MC_CGM_MUX_0_CSS_CLK_SW_SHIFT (2U) 381 #define MC_CGM_MUX_0_CSS_CLK_SW_WIDTH (1U) 382 #define MC_CGM_MUX_0_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_0_CSS_CLK_SW_MASK) 383 384 #define MC_CGM_MUX_0_CSS_SAFE_SW_MASK (0x8U) 385 #define MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT (3U) 386 #define MC_CGM_MUX_0_CSS_SAFE_SW_WIDTH (1U) 387 #define MC_CGM_MUX_0_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_0_CSS_SAFE_SW_MASK) 388 389 #define MC_CGM_MUX_0_CSS_SWIP_MASK (0x10000U) 390 #define MC_CGM_MUX_0_CSS_SWIP_SHIFT (16U) 391 #define MC_CGM_MUX_0_CSS_SWIP_WIDTH (1U) 392 #define MC_CGM_MUX_0_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SWIP_SHIFT)) & MC_CGM_MUX_0_CSS_SWIP_MASK) 393 394 #define MC_CGM_MUX_0_CSS_SWTRG_MASK (0xE0000U) 395 #define MC_CGM_MUX_0_CSS_SWTRG_SHIFT (17U) 396 #define MC_CGM_MUX_0_CSS_SWTRG_WIDTH (3U) 397 #define MC_CGM_MUX_0_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_0_CSS_SWTRG_MASK) 398 399 #define MC_CGM_MUX_0_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ 400 #define MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (24U) 401 #define MC_CGM_MUX_0_CSS_SELSTAT_WIDTH (6U) 402 #define MC_CGM_MUX_0_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_0_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ 403 /*! @} */ 404 405 /*! @name MUX_0_DC_0 - Clock Mux 0 Divider 0 Control Register */ 406 /*! @{ */ 407 408 #define MC_CGM_MUX_0_DC_0_DIV_MASK (0xFF0000U) 409 #define MC_CGM_MUX_0_DC_0_DIV_SHIFT (16U) 410 #define MC_CGM_MUX_0_DC_0_DIV_WIDTH (8U) 411 #define MC_CGM_MUX_0_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_0_DIV_SHIFT)) & MC_CGM_MUX_0_DC_0_DIV_MASK) 412 413 #define MC_CGM_MUX_0_DC_0_DE_MASK (0x80000000U) 414 #define MC_CGM_MUX_0_DC_0_DE_SHIFT (31U) 415 #define MC_CGM_MUX_0_DC_0_DE_WIDTH (1U) 416 #define MC_CGM_MUX_0_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_0_DE_SHIFT)) & MC_CGM_MUX_0_DC_0_DE_MASK) 417 /*! @} */ 418 419 /*! @name MUX_0_DC_1 - Clock Mux 0 Divider 1 Control Register */ 420 /*! @{ */ 421 422 #define MC_CGM_MUX_0_DC_1_DIV_MASK (0xFF0000U) 423 #define MC_CGM_MUX_0_DC_1_DIV_SHIFT (16U) 424 #define MC_CGM_MUX_0_DC_1_DIV_WIDTH (8U) 425 #define MC_CGM_MUX_0_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_1_DIV_SHIFT)) & MC_CGM_MUX_0_DC_1_DIV_MASK) 426 427 #define MC_CGM_MUX_0_DC_1_DE_MASK (0x80000000U) 428 #define MC_CGM_MUX_0_DC_1_DE_SHIFT (31U) 429 #define MC_CGM_MUX_0_DC_1_DE_WIDTH (1U) 430 #define MC_CGM_MUX_0_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_1_DE_SHIFT)) & MC_CGM_MUX_0_DC_1_DE_MASK) 431 /*! @} */ 432 433 /*! @name MUX_0_DIV_UPD_STAT - Clock Mux 0 Divider Update Status Register */ 434 /*! @{ */ 435 436 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 437 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 438 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 439 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK) 440 /*! @} */ 441 442 /*! @name MUX_1_CSC - Clock Mux 1 Select Control Register */ 443 /*! @{ */ 444 445 #define MC_CGM_MUX_1_CSC_CLK_SW_MASK (0x4U) 446 #define MC_CGM_MUX_1_CSC_CLK_SW_SHIFT (2U) 447 #define MC_CGM_MUX_1_CSC_CLK_SW_WIDTH (1U) 448 #define MC_CGM_MUX_1_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_1_CSC_CLK_SW_MASK) 449 450 #define MC_CGM_MUX_1_CSC_SAFE_SW_MASK (0x8U) 451 #define MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT (3U) 452 #define MC_CGM_MUX_1_CSC_SAFE_SW_WIDTH (1U) 453 #define MC_CGM_MUX_1_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_1_CSC_SAFE_SW_MASK) 454 455 #define MC_CGM_MUX_1_CSC_SELCTL_MASK (0xF000000U) 456 #define MC_CGM_MUX_1_CSC_SELCTL_SHIFT (24U) 457 #define MC_CGM_MUX_1_CSC_SELCTL_WIDTH (4U) 458 #define MC_CGM_MUX_1_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_1_CSC_SELCTL_MASK) 459 /*! @} */ 460 461 /*! @name MUX_1_CSS - Clock Mux 1 Select Status Register */ 462 /*! @{ */ 463 464 #define MC_CGM_MUX_1_CSS_CLK_SW_MASK (0x4U) 465 #define MC_CGM_MUX_1_CSS_CLK_SW_SHIFT (2U) 466 #define MC_CGM_MUX_1_CSS_CLK_SW_WIDTH (1U) 467 #define MC_CGM_MUX_1_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_1_CSS_CLK_SW_MASK) 468 469 #define MC_CGM_MUX_1_CSS_SAFE_SW_MASK (0x8U) 470 #define MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT (3U) 471 #define MC_CGM_MUX_1_CSS_SAFE_SW_WIDTH (1U) 472 #define MC_CGM_MUX_1_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_1_CSS_SAFE_SW_MASK) 473 474 #define MC_CGM_MUX_1_CSS_SWIP_MASK (0x10000U) 475 #define MC_CGM_MUX_1_CSS_SWIP_SHIFT (16U) 476 #define MC_CGM_MUX_1_CSS_SWIP_WIDTH (1U) 477 #define MC_CGM_MUX_1_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SWIP_SHIFT)) & MC_CGM_MUX_1_CSS_SWIP_MASK) 478 479 #define MC_CGM_MUX_1_CSS_SWTRG_MASK (0xE0000U) 480 #define MC_CGM_MUX_1_CSS_SWTRG_SHIFT (17U) 481 #define MC_CGM_MUX_1_CSS_SWTRG_WIDTH (3U) 482 #define MC_CGM_MUX_1_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_1_CSS_SWTRG_MASK) 483 484 #define MC_CGM_MUX_1_CSS_SELSTAT_MASK (0xF000000U) 485 #define MC_CGM_MUX_1_CSS_SELSTAT_SHIFT (24U) 486 #define MC_CGM_MUX_1_CSS_SELSTAT_WIDTH (4U) 487 #define MC_CGM_MUX_1_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_1_CSS_SELSTAT_MASK) 488 /*! @} */ 489 490 /*! @name MUX_1_DC_0 - Clock Mux 1 Divider 0 Control Register */ 491 /*! @{ */ 492 493 #define MC_CGM_MUX_1_DC_0_DIV_MASK (0xFF0000U) 494 #define MC_CGM_MUX_1_DC_0_DIV_SHIFT (16U) 495 #define MC_CGM_MUX_1_DC_0_DIV_WIDTH (8U) 496 #define MC_CGM_MUX_1_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_0_DIV_SHIFT)) & MC_CGM_MUX_1_DC_0_DIV_MASK) 497 498 #define MC_CGM_MUX_1_DC_0_DE_MASK (0x80000000U) 499 #define MC_CGM_MUX_1_DC_0_DE_SHIFT (31U) 500 #define MC_CGM_MUX_1_DC_0_DE_WIDTH (1U) 501 #define MC_CGM_MUX_1_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_0_DE_SHIFT)) & MC_CGM_MUX_1_DC_0_DE_MASK) 502 /*! @} */ 503 504 /*! @name MUX_1_DC_1 - Clock Mux 1 Divider 1 Control Register */ 505 /*! @{ */ 506 507 #define MC_CGM_MUX_1_DC_1_DIV_MASK (0xFF0000U) 508 #define MC_CGM_MUX_1_DC_1_DIV_SHIFT (16U) 509 #define MC_CGM_MUX_1_DC_1_DIV_WIDTH (8U) 510 #define MC_CGM_MUX_1_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_1_DIV_SHIFT)) & MC_CGM_MUX_1_DC_1_DIV_MASK) 511 512 #define MC_CGM_MUX_1_DC_1_DE_MASK (0x80000000U) 513 #define MC_CGM_MUX_1_DC_1_DE_SHIFT (31U) 514 #define MC_CGM_MUX_1_DC_1_DE_WIDTH (1U) 515 #define MC_CGM_MUX_1_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_1_DE_SHIFT)) & MC_CGM_MUX_1_DC_1_DE_MASK) 516 /*! @} */ 517 518 /*! @name MUX_1_DIV_UPD_STAT - Clock Mux 1 Divider Update Status Register */ 519 /*! @{ */ 520 521 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 522 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 523 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 524 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK) 525 /*! @} */ 526 527 /*! @name MUX_2_CSC - Clock Mux 2 Select Control Register */ 528 /*! @{ */ 529 530 #define MC_CGM_MUX_2_CSC_CLK_SW_MASK (0x4U) 531 #define MC_CGM_MUX_2_CSC_CLK_SW_SHIFT (2U) 532 #define MC_CGM_MUX_2_CSC_CLK_SW_WIDTH (1U) 533 #define MC_CGM_MUX_2_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_2_CSC_CLK_SW_MASK) 534 535 #define MC_CGM_MUX_2_CSC_SAFE_SW_MASK (0x8U) 536 #define MC_CGM_MUX_2_CSC_SAFE_SW_SHIFT (3U) 537 #define MC_CGM_MUX_2_CSC_SAFE_SW_WIDTH (1U) 538 #define MC_CGM_MUX_2_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_2_CSC_SAFE_SW_MASK) 539 540 #define MC_CGM_MUX_2_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 541 #define MC_CGM_MUX_2_CSC_SELCTL_SHIFT (24U) 542 #define MC_CGM_MUX_2_CSC_SELCTL_WIDTH (6U) 543 #define MC_CGM_MUX_2_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_2_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 544 /*! @} */ 545 546 /*! @name MUX_2_CSS - Clock Mux 2 Select Status Register */ 547 /*! @{ */ 548 549 #define MC_CGM_MUX_2_CSS_CLK_SW_MASK (0x4U) 550 #define MC_CGM_MUX_2_CSS_CLK_SW_SHIFT (2U) 551 #define MC_CGM_MUX_2_CSS_CLK_SW_WIDTH (1U) 552 #define MC_CGM_MUX_2_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_2_CSS_CLK_SW_MASK) 553 554 #define MC_CGM_MUX_2_CSS_SAFE_SW_MASK (0x8U) 555 #define MC_CGM_MUX_2_CSS_SAFE_SW_SHIFT (3U) 556 #define MC_CGM_MUX_2_CSS_SAFE_SW_WIDTH (1U) 557 #define MC_CGM_MUX_2_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_2_CSS_SAFE_SW_MASK) 558 559 #define MC_CGM_MUX_2_CSS_SWIP_MASK (0x10000U) 560 #define MC_CGM_MUX_2_CSS_SWIP_SHIFT (16U) 561 #define MC_CGM_MUX_2_CSS_SWIP_WIDTH (1U) 562 #define MC_CGM_MUX_2_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SWIP_SHIFT)) & MC_CGM_MUX_2_CSS_SWIP_MASK) 563 564 #define MC_CGM_MUX_2_CSS_SWTRG_MASK (0xE0000U) 565 #define MC_CGM_MUX_2_CSS_SWTRG_SHIFT (17U) 566 #define MC_CGM_MUX_2_CSS_SWTRG_WIDTH (3U) 567 #define MC_CGM_MUX_2_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_2_CSS_SWTRG_MASK) 568 569 #define MC_CGM_MUX_2_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 570 #define MC_CGM_MUX_2_CSS_SELSTAT_SHIFT (24U) 571 #define MC_CGM_MUX_2_CSS_SELSTAT_WIDTH (6U) 572 #define MC_CGM_MUX_2_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_2_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 573 /*! @} */ 574 575 /*! @name MUX_2_DC_0 - Clock Mux 2 Divider 0 Control Register */ 576 /*! @{ */ 577 578 #define MC_CGM_MUX_2_DC_0_DIV_MASK (0xFF0000U) 579 #define MC_CGM_MUX_2_DC_0_DIV_SHIFT (16U) 580 #define MC_CGM_MUX_2_DC_0_DIV_WIDTH (8U) 581 #define MC_CGM_MUX_2_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_0_DIV_SHIFT)) & MC_CGM_MUX_2_DC_0_DIV_MASK) 582 583 #define MC_CGM_MUX_2_DC_0_DE_MASK (0x80000000U) 584 #define MC_CGM_MUX_2_DC_0_DE_SHIFT (31U) 585 #define MC_CGM_MUX_2_DC_0_DE_WIDTH (1U) 586 #define MC_CGM_MUX_2_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_0_DE_SHIFT)) & MC_CGM_MUX_2_DC_0_DE_MASK) 587 /*! @} */ 588 589 /*! @name MUX_2_DC_1 - Clock Mux 2 Divider 1 Control Register */ 590 /*! @{ */ 591 592 #define MC_CGM_MUX_2_DC_1_DIV_MASK (0xFF0000U) 593 #define MC_CGM_MUX_2_DC_1_DIV_SHIFT (16U) 594 #define MC_CGM_MUX_2_DC_1_DIV_WIDTH (8U) 595 #define MC_CGM_MUX_2_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_1_DIV_SHIFT)) & MC_CGM_MUX_2_DC_1_DIV_MASK) 596 597 #define MC_CGM_MUX_2_DC_1_DE_MASK (0x80000000U) 598 #define MC_CGM_MUX_2_DC_1_DE_SHIFT (31U) 599 #define MC_CGM_MUX_2_DC_1_DE_WIDTH (1U) 600 #define MC_CGM_MUX_2_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_1_DE_SHIFT)) & MC_CGM_MUX_2_DC_1_DE_MASK) 601 /*! @} */ 602 603 /*! @name MUX_2_DC_2 - Clock Mux 2 Divider 2 Control Register */ 604 /*! @{ */ 605 606 #define MC_CGM_MUX_2_DC_2_DIV_FMT_MASK (0x3U) 607 #define MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT (0U) 608 #define MC_CGM_MUX_2_DC_2_DIV_FMT_WIDTH (2U) 609 #define MC_CGM_MUX_2_DC_2_DIV_FMT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT)) & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) 610 611 #define MC_CGM_MUX_2_DC_2_DIV_MASK (0x1FFF0000U) 612 #define MC_CGM_MUX_2_DC_2_DIV_SHIFT (16U) 613 #define MC_CGM_MUX_2_DC_2_DIV_WIDTH (13U) 614 #define MC_CGM_MUX_2_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_2_DIV_SHIFT)) & MC_CGM_MUX_2_DC_2_DIV_MASK) 615 616 #define MC_CGM_MUX_2_DC_2_DE_MASK (0x80000000U) 617 #define MC_CGM_MUX_2_DC_2_DE_SHIFT (31U) 618 #define MC_CGM_MUX_2_DC_2_DE_WIDTH (1U) 619 #define MC_CGM_MUX_2_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_2_DE_SHIFT)) & MC_CGM_MUX_2_DC_2_DE_MASK) 620 /*! @} */ 621 622 /*! @name MUX_2_DC_3 - Clock Mux 2 Divider 3 Control Register */ 623 /*! @{ */ 624 625 #define MC_CGM_MUX_2_DC_3_DIV_MASK (0xFF0000U) 626 #define MC_CGM_MUX_2_DC_3_DIV_SHIFT (16U) 627 #define MC_CGM_MUX_2_DC_3_DIV_WIDTH (8U) 628 #define MC_CGM_MUX_2_DC_3_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_3_DIV_SHIFT)) & MC_CGM_MUX_2_DC_3_DIV_MASK) 629 630 #define MC_CGM_MUX_2_DC_3_DE_MASK (0x80000000U) 631 #define MC_CGM_MUX_2_DC_3_DE_SHIFT (31U) 632 #define MC_CGM_MUX_2_DC_3_DE_WIDTH (1U) 633 #define MC_CGM_MUX_2_DC_3_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_3_DE_SHIFT)) & MC_CGM_MUX_2_DC_3_DE_MASK) 634 /*! @} */ 635 636 /*! @name MUX_2_DC_4 - Clock Mux 2 Divider 4 Control Register */ 637 /*! @{ */ 638 639 #define MC_CGM_MUX_2_DC_4_DIV_MASK (0xFF0000U) 640 #define MC_CGM_MUX_2_DC_4_DIV_SHIFT (16U) 641 #define MC_CGM_MUX_2_DC_4_DIV_WIDTH (8U) 642 #define MC_CGM_MUX_2_DC_4_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_4_DIV_SHIFT)) & MC_CGM_MUX_2_DC_4_DIV_MASK) 643 644 #define MC_CGM_MUX_2_DC_4_DE_MASK (0x80000000U) 645 #define MC_CGM_MUX_2_DC_4_DE_SHIFT (31U) 646 #define MC_CGM_MUX_2_DC_4_DE_WIDTH (1U) 647 #define MC_CGM_MUX_2_DC_4_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_4_DE_SHIFT)) & MC_CGM_MUX_2_DC_4_DE_MASK) 648 /*! @} */ 649 650 /*! @name MUX_2_DC_5 - Clock Mux 2 Divider 5 Control Register */ 651 /*! @{ */ 652 653 #define MC_CGM_MUX_2_DC_5_DIV_MASK (0xFF0000U) 654 #define MC_CGM_MUX_2_DC_5_DIV_SHIFT (16U) 655 #define MC_CGM_MUX_2_DC_5_DIV_WIDTH (8U) 656 #define MC_CGM_MUX_2_DC_5_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_5_DIV_SHIFT)) & MC_CGM_MUX_2_DC_5_DIV_MASK) 657 658 #define MC_CGM_MUX_2_DC_5_DE_MASK (0x80000000U) 659 #define MC_CGM_MUX_2_DC_5_DE_SHIFT (31U) 660 #define MC_CGM_MUX_2_DC_5_DE_WIDTH (1U) 661 #define MC_CGM_MUX_2_DC_5_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_5_DE_SHIFT)) & MC_CGM_MUX_2_DC_5_DE_MASK) 662 /*! @} */ 663 664 /*! @name MUX_2_DIV_UPD_STAT - Clock Mux 2 Divider Update Status Register */ 665 /*! @{ */ 666 667 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 668 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 669 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 670 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_MASK) 671 /*! @} */ 672 673 /*! @name MUX_3_CSC - Clock Mux 3 Select Control Register */ 674 /*! @{ */ 675 676 #define MC_CGM_MUX_3_CSC_CLK_SW_MASK (0x4U) 677 #define MC_CGM_MUX_3_CSC_CLK_SW_SHIFT (2U) 678 #define MC_CGM_MUX_3_CSC_CLK_SW_WIDTH (1U) 679 #define MC_CGM_MUX_3_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_3_CSC_CLK_SW_MASK) 680 681 #define MC_CGM_MUX_3_CSC_SAFE_SW_MASK (0x8U) 682 #define MC_CGM_MUX_3_CSC_SAFE_SW_SHIFT (3U) 683 #define MC_CGM_MUX_3_CSC_SAFE_SW_WIDTH (1U) 684 #define MC_CGM_MUX_3_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_3_CSC_SAFE_SW_MASK) 685 686 #define MC_CGM_MUX_3_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (4, 5, 6), largest definition used */ 687 #define MC_CGM_MUX_3_CSC_SELCTL_SHIFT (24U) 688 #define MC_CGM_MUX_3_CSC_SELCTL_WIDTH (6U) 689 #define MC_CGM_MUX_3_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_3_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (4, 5, 6), largest definition used */ 690 /*! @} */ 691 692 /*! @name MUX_3_CSS - Clock Mux 3 Select Status Register */ 693 /*! @{ */ 694 695 #define MC_CGM_MUX_3_CSS_CLK_SW_MASK (0x4U) 696 #define MC_CGM_MUX_3_CSS_CLK_SW_SHIFT (2U) 697 #define MC_CGM_MUX_3_CSS_CLK_SW_WIDTH (1U) 698 #define MC_CGM_MUX_3_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_3_CSS_CLK_SW_MASK) 699 700 #define MC_CGM_MUX_3_CSS_SAFE_SW_MASK (0x8U) 701 #define MC_CGM_MUX_3_CSS_SAFE_SW_SHIFT (3U) 702 #define MC_CGM_MUX_3_CSS_SAFE_SW_WIDTH (1U) 703 #define MC_CGM_MUX_3_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_3_CSS_SAFE_SW_MASK) 704 705 #define MC_CGM_MUX_3_CSS_SWIP_MASK (0x10000U) 706 #define MC_CGM_MUX_3_CSS_SWIP_SHIFT (16U) 707 #define MC_CGM_MUX_3_CSS_SWIP_WIDTH (1U) 708 #define MC_CGM_MUX_3_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SWIP_SHIFT)) & MC_CGM_MUX_3_CSS_SWIP_MASK) 709 710 #define MC_CGM_MUX_3_CSS_SWTRG_MASK (0xE0000U) 711 #define MC_CGM_MUX_3_CSS_SWTRG_SHIFT (17U) 712 #define MC_CGM_MUX_3_CSS_SWTRG_WIDTH (3U) 713 #define MC_CGM_MUX_3_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_3_CSS_SWTRG_MASK) 714 715 #define MC_CGM_MUX_3_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (4, 5, 6), largest definition used */ 716 #define MC_CGM_MUX_3_CSS_SELSTAT_SHIFT (24U) 717 #define MC_CGM_MUX_3_CSS_SELSTAT_WIDTH (6U) 718 #define MC_CGM_MUX_3_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_3_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (4, 5, 6), largest definition used */ 719 /*! @} */ 720 721 /*! @name MUX_3_DC_0 - Clock Mux 3 Divider 0 Control Register */ 722 /*! @{ */ 723 724 #define MC_CGM_MUX_3_DC_0_DIV_MASK (0x3FF0000U) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ 725 #define MC_CGM_MUX_3_DC_0_DIV_SHIFT (16U) 726 #define MC_CGM_MUX_3_DC_0_DIV_WIDTH (10U) 727 #define MC_CGM_MUX_3_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_0_DIV_SHIFT)) & MC_CGM_MUX_3_DC_0_DIV_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ 728 729 #define MC_CGM_MUX_3_DC_0_DE_MASK (0x80000000U) 730 #define MC_CGM_MUX_3_DC_0_DE_SHIFT (31U) 731 #define MC_CGM_MUX_3_DC_0_DE_WIDTH (1U) 732 #define MC_CGM_MUX_3_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_0_DE_SHIFT)) & MC_CGM_MUX_3_DC_0_DE_MASK) 733 /*! @} */ 734 735 /*! @name MUX_3_DC_1 - Clock Mux 3 Divider 1 Control Register */ 736 /*! @{ */ 737 738 #define MC_CGM_MUX_3_DC_1_DIV_MASK (0x3FF0000U) 739 #define MC_CGM_MUX_3_DC_1_DIV_SHIFT (16U) 740 #define MC_CGM_MUX_3_DC_1_DIV_WIDTH (10U) 741 #define MC_CGM_MUX_3_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_1_DIV_SHIFT)) & MC_CGM_MUX_3_DC_1_DIV_MASK) 742 743 #define MC_CGM_MUX_3_DC_1_DE_MASK (0x80000000U) 744 #define MC_CGM_MUX_3_DC_1_DE_SHIFT (31U) 745 #define MC_CGM_MUX_3_DC_1_DE_WIDTH (1U) 746 #define MC_CGM_MUX_3_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_1_DE_SHIFT)) & MC_CGM_MUX_3_DC_1_DE_MASK) 747 /*! @} */ 748 749 /*! @name MUX_3_DC_2 - Clock Mux 3 Divider 2 Control Register */ 750 /*! @{ */ 751 752 #define MC_CGM_MUX_3_DC_2_DIV_MASK (0x3FF0000U) 753 #define MC_CGM_MUX_3_DC_2_DIV_SHIFT (16U) 754 #define MC_CGM_MUX_3_DC_2_DIV_WIDTH (10U) 755 #define MC_CGM_MUX_3_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_2_DIV_SHIFT)) & MC_CGM_MUX_3_DC_2_DIV_MASK) 756 757 #define MC_CGM_MUX_3_DC_2_DE_MASK (0x80000000U) 758 #define MC_CGM_MUX_3_DC_2_DE_SHIFT (31U) 759 #define MC_CGM_MUX_3_DC_2_DE_WIDTH (1U) 760 #define MC_CGM_MUX_3_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_2_DE_SHIFT)) & MC_CGM_MUX_3_DC_2_DE_MASK) 761 /*! @} */ 762 763 /*! @name MUX_3_DC_3 - Clock Mux 3 Divider 3 Control Register */ 764 /*! @{ */ 765 766 #define MC_CGM_MUX_3_DC_3_DIV_MASK (0x3FF0000U) 767 #define MC_CGM_MUX_3_DC_3_DIV_SHIFT (16U) 768 #define MC_CGM_MUX_3_DC_3_DIV_WIDTH (10U) 769 #define MC_CGM_MUX_3_DC_3_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_3_DIV_SHIFT)) & MC_CGM_MUX_3_DC_3_DIV_MASK) 770 771 #define MC_CGM_MUX_3_DC_3_DE_MASK (0x80000000U) 772 #define MC_CGM_MUX_3_DC_3_DE_SHIFT (31U) 773 #define MC_CGM_MUX_3_DC_3_DE_WIDTH (1U) 774 #define MC_CGM_MUX_3_DC_3_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_3_DE_SHIFT)) & MC_CGM_MUX_3_DC_3_DE_MASK) 775 /*! @} */ 776 777 /*! @name MUX_3_DC_4 - Clock Mux 3 Divider 4 Control Register */ 778 /*! @{ */ 779 780 #define MC_CGM_MUX_3_DC_4_DIV_MASK (0x3FF0000U) 781 #define MC_CGM_MUX_3_DC_4_DIV_SHIFT (16U) 782 #define MC_CGM_MUX_3_DC_4_DIV_WIDTH (10U) 783 #define MC_CGM_MUX_3_DC_4_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_4_DIV_SHIFT)) & MC_CGM_MUX_3_DC_4_DIV_MASK) 784 785 #define MC_CGM_MUX_3_DC_4_DE_MASK (0x80000000U) 786 #define MC_CGM_MUX_3_DC_4_DE_SHIFT (31U) 787 #define MC_CGM_MUX_3_DC_4_DE_WIDTH (1U) 788 #define MC_CGM_MUX_3_DC_4_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_4_DE_SHIFT)) & MC_CGM_MUX_3_DC_4_DE_MASK) 789 /*! @} */ 790 791 /*! @name MUX_3_DC_5 - Clock Mux 3 Divider 5 Control Register */ 792 /*! @{ */ 793 794 #define MC_CGM_MUX_3_DC_5_DIV_MASK (0x3FF0000U) 795 #define MC_CGM_MUX_3_DC_5_DIV_SHIFT (16U) 796 #define MC_CGM_MUX_3_DC_5_DIV_WIDTH (10U) 797 #define MC_CGM_MUX_3_DC_5_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_5_DIV_SHIFT)) & MC_CGM_MUX_3_DC_5_DIV_MASK) 798 799 #define MC_CGM_MUX_3_DC_5_DE_MASK (0x80000000U) 800 #define MC_CGM_MUX_3_DC_5_DE_SHIFT (31U) 801 #define MC_CGM_MUX_3_DC_5_DE_WIDTH (1U) 802 #define MC_CGM_MUX_3_DC_5_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_5_DE_SHIFT)) & MC_CGM_MUX_3_DC_5_DE_MASK) 803 /*! @} */ 804 805 /*! @name MUX_3_DC_6 - Clock Mux 3 Divider 6 Control Register */ 806 /*! @{ */ 807 808 #define MC_CGM_MUX_3_DC_6_DIV_MASK (0x3FF0000U) 809 #define MC_CGM_MUX_3_DC_6_DIV_SHIFT (16U) 810 #define MC_CGM_MUX_3_DC_6_DIV_WIDTH (10U) 811 #define MC_CGM_MUX_3_DC_6_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_6_DIV_SHIFT)) & MC_CGM_MUX_3_DC_6_DIV_MASK) 812 813 #define MC_CGM_MUX_3_DC_6_DE_MASK (0x80000000U) 814 #define MC_CGM_MUX_3_DC_6_DE_SHIFT (31U) 815 #define MC_CGM_MUX_3_DC_6_DE_WIDTH (1U) 816 #define MC_CGM_MUX_3_DC_6_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_6_DE_SHIFT)) & MC_CGM_MUX_3_DC_6_DE_MASK) 817 /*! @} */ 818 819 /*! @name MUX_3_DC_7 - Clock Mux 3 Divider 7 Control Register */ 820 /*! @{ */ 821 822 #define MC_CGM_MUX_3_DC_7_DIV_MASK (0x3FF0000U) 823 #define MC_CGM_MUX_3_DC_7_DIV_SHIFT (16U) 824 #define MC_CGM_MUX_3_DC_7_DIV_WIDTH (10U) 825 #define MC_CGM_MUX_3_DC_7_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_7_DIV_SHIFT)) & MC_CGM_MUX_3_DC_7_DIV_MASK) 826 827 #define MC_CGM_MUX_3_DC_7_DE_MASK (0x80000000U) 828 #define MC_CGM_MUX_3_DC_7_DE_SHIFT (31U) 829 #define MC_CGM_MUX_3_DC_7_DE_WIDTH (1U) 830 #define MC_CGM_MUX_3_DC_7_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_7_DE_SHIFT)) & MC_CGM_MUX_3_DC_7_DE_MASK) 831 /*! @} */ 832 833 /*! @name MUX_3_DIV_UPD_STAT - Clock Mux 3 Divider Update Status Register */ 834 /*! @{ */ 835 836 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 837 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 838 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 839 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_MASK) 840 /*! @} */ 841 842 /*! @name MUX_4_CSC - Clock Mux 4 Select Control Register */ 843 /*! @{ */ 844 845 #define MC_CGM_MUX_4_CSC_CG_MASK (0x4U) 846 #define MC_CGM_MUX_4_CSC_CG_SHIFT (2U) 847 #define MC_CGM_MUX_4_CSC_CG_WIDTH (1U) 848 #define MC_CGM_MUX_4_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_CG_SHIFT)) & MC_CGM_MUX_4_CSC_CG_MASK) 849 850 #define MC_CGM_MUX_4_CSC_CLK_SW_MASK (0x4U) 851 #define MC_CGM_MUX_4_CSC_CLK_SW_SHIFT (2U) 852 #define MC_CGM_MUX_4_CSC_CLK_SW_WIDTH (1U) 853 #define MC_CGM_MUX_4_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_4_CSC_CLK_SW_MASK) 854 855 #define MC_CGM_MUX_4_CSC_FCG_MASK (0x8U) 856 #define MC_CGM_MUX_4_CSC_FCG_SHIFT (3U) 857 #define MC_CGM_MUX_4_CSC_FCG_WIDTH (1U) 858 #define MC_CGM_MUX_4_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_FCG_SHIFT)) & MC_CGM_MUX_4_CSC_FCG_MASK) 859 860 #define MC_CGM_MUX_4_CSC_SAFE_SW_MASK (0x8U) 861 #define MC_CGM_MUX_4_CSC_SAFE_SW_SHIFT (3U) 862 #define MC_CGM_MUX_4_CSC_SAFE_SW_WIDTH (1U) 863 #define MC_CGM_MUX_4_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_4_CSC_SAFE_SW_MASK) 864 865 #define MC_CGM_MUX_4_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 866 #define MC_CGM_MUX_4_CSC_SELCTL_SHIFT (24U) 867 #define MC_CGM_MUX_4_CSC_SELCTL_WIDTH (6U) 868 #define MC_CGM_MUX_4_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_4_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 869 /*! @} */ 870 871 /*! @name MUX_4_CSS - Clock Mux 4 Select Status Register */ 872 /*! @{ */ 873 874 #define MC_CGM_MUX_4_CSS_CLK_SW_MASK (0x4U) 875 #define MC_CGM_MUX_4_CSS_CLK_SW_SHIFT (2U) 876 #define MC_CGM_MUX_4_CSS_CLK_SW_WIDTH (1U) 877 #define MC_CGM_MUX_4_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_4_CSS_CLK_SW_MASK) 878 879 #define MC_CGM_MUX_4_CSS_SAFE_SW_MASK (0x8U) 880 #define MC_CGM_MUX_4_CSS_SAFE_SW_SHIFT (3U) 881 #define MC_CGM_MUX_4_CSS_SAFE_SW_WIDTH (1U) 882 #define MC_CGM_MUX_4_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_4_CSS_SAFE_SW_MASK) 883 884 #define MC_CGM_MUX_4_CSS_GRIP_MASK (0x10000U) 885 #define MC_CGM_MUX_4_CSS_GRIP_SHIFT (16U) 886 #define MC_CGM_MUX_4_CSS_GRIP_WIDTH (1U) 887 #define MC_CGM_MUX_4_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_GRIP_SHIFT)) & MC_CGM_MUX_4_CSS_GRIP_MASK) 888 889 #define MC_CGM_MUX_4_CSS_SWIP_MASK (0x10000U) 890 #define MC_CGM_MUX_4_CSS_SWIP_SHIFT (16U) 891 #define MC_CGM_MUX_4_CSS_SWIP_WIDTH (1U) 892 #define MC_CGM_MUX_4_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SWIP_SHIFT)) & MC_CGM_MUX_4_CSS_SWIP_MASK) 893 894 #define MC_CGM_MUX_4_CSS_CS_MASK (0x20000U) 895 #define MC_CGM_MUX_4_CSS_CS_SHIFT (17U) 896 #define MC_CGM_MUX_4_CSS_CS_WIDTH (1U) 897 #define MC_CGM_MUX_4_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_CS_SHIFT)) & MC_CGM_MUX_4_CSS_CS_MASK) 898 899 #define MC_CGM_MUX_4_CSS_SWTRG_MASK (0xE0000U) 900 #define MC_CGM_MUX_4_CSS_SWTRG_SHIFT (17U) 901 #define MC_CGM_MUX_4_CSS_SWTRG_WIDTH (3U) 902 #define MC_CGM_MUX_4_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_4_CSS_SWTRG_MASK) 903 904 #define MC_CGM_MUX_4_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 905 #define MC_CGM_MUX_4_CSS_SELSTAT_SHIFT (24U) 906 #define MC_CGM_MUX_4_CSS_SELSTAT_WIDTH (6U) 907 #define MC_CGM_MUX_4_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_4_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 908 /*! @} */ 909 910 /*! @name MUX_4_DC_0 - Clock Mux 4 Divider 0 Control Register */ 911 /*! @{ */ 912 913 #define MC_CGM_MUX_4_DC_0_DIV_MASK (0xFF0000U) 914 #define MC_CGM_MUX_4_DC_0_DIV_SHIFT (16U) 915 #define MC_CGM_MUX_4_DC_0_DIV_WIDTH (8U) 916 #define MC_CGM_MUX_4_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DC_0_DIV_SHIFT)) & MC_CGM_MUX_4_DC_0_DIV_MASK) 917 918 #define MC_CGM_MUX_4_DC_0_DE_MASK (0x80000000U) 919 #define MC_CGM_MUX_4_DC_0_DE_SHIFT (31U) 920 #define MC_CGM_MUX_4_DC_0_DE_WIDTH (1U) 921 #define MC_CGM_MUX_4_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DC_0_DE_SHIFT)) & MC_CGM_MUX_4_DC_0_DE_MASK) 922 /*! @} */ 923 924 /*! @name MUX_4_DIV_UPD_STAT - Clock Mux 4 Divider Update Status Register */ 925 /*! @{ */ 926 927 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 928 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 929 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 930 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_MASK) 931 /*! @} */ 932 933 /*! @name MUX_5_CSC - Clock Mux 5 Select Control Register */ 934 /*! @{ */ 935 936 #define MC_CGM_MUX_5_CSC_CLK_SW_MASK (0x4U) 937 #define MC_CGM_MUX_5_CSC_CLK_SW_SHIFT (2U) 938 #define MC_CGM_MUX_5_CSC_CLK_SW_WIDTH (1U) 939 #define MC_CGM_MUX_5_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_5_CSC_CLK_SW_MASK) 940 941 #define MC_CGM_MUX_5_CSC_SAFE_SW_MASK (0x8U) 942 #define MC_CGM_MUX_5_CSC_SAFE_SW_SHIFT (3U) 943 #define MC_CGM_MUX_5_CSC_SAFE_SW_WIDTH (1U) 944 #define MC_CGM_MUX_5_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_5_CSC_SAFE_SW_MASK) 945 946 #define MC_CGM_MUX_5_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 947 #define MC_CGM_MUX_5_CSC_SELCTL_SHIFT (24U) 948 #define MC_CGM_MUX_5_CSC_SELCTL_WIDTH (6U) 949 #define MC_CGM_MUX_5_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_5_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 950 /*! @} */ 951 952 /*! @name MUX_5_CSS - Clock Mux 5 Select Status Register */ 953 /*! @{ */ 954 955 #define MC_CGM_MUX_5_CSS_CLK_SW_MASK (0x4U) 956 #define MC_CGM_MUX_5_CSS_CLK_SW_SHIFT (2U) 957 #define MC_CGM_MUX_5_CSS_CLK_SW_WIDTH (1U) 958 #define MC_CGM_MUX_5_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_5_CSS_CLK_SW_MASK) 959 960 #define MC_CGM_MUX_5_CSS_SAFE_SW_MASK (0x8U) 961 #define MC_CGM_MUX_5_CSS_SAFE_SW_SHIFT (3U) 962 #define MC_CGM_MUX_5_CSS_SAFE_SW_WIDTH (1U) 963 #define MC_CGM_MUX_5_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_5_CSS_SAFE_SW_MASK) 964 965 #define MC_CGM_MUX_5_CSS_SWIP_MASK (0x10000U) 966 #define MC_CGM_MUX_5_CSS_SWIP_SHIFT (16U) 967 #define MC_CGM_MUX_5_CSS_SWIP_WIDTH (1U) 968 #define MC_CGM_MUX_5_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_SWIP_SHIFT)) & MC_CGM_MUX_5_CSS_SWIP_MASK) 969 970 #define MC_CGM_MUX_5_CSS_SWTRG_MASK (0xE0000U) 971 #define MC_CGM_MUX_5_CSS_SWTRG_SHIFT (17U) 972 #define MC_CGM_MUX_5_CSS_SWTRG_WIDTH (3U) 973 #define MC_CGM_MUX_5_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_5_CSS_SWTRG_MASK) 974 975 #define MC_CGM_MUX_5_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 976 #define MC_CGM_MUX_5_CSS_SELSTAT_SHIFT (24U) 977 #define MC_CGM_MUX_5_CSS_SELSTAT_WIDTH (6U) 978 #define MC_CGM_MUX_5_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_5_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 979 /*! @} */ 980 981 /*! @name MUX_5_DC_0 - Clock Mux 5 Divider 0 Control Register */ 982 /*! @{ */ 983 984 #define MC_CGM_MUX_5_DC_0_DIV_MASK (0xFF0000U) 985 #define MC_CGM_MUX_5_DC_0_DIV_SHIFT (16U) 986 #define MC_CGM_MUX_5_DC_0_DIV_WIDTH (8U) 987 #define MC_CGM_MUX_5_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_0_DIV_SHIFT)) & MC_CGM_MUX_5_DC_0_DIV_MASK) 988 989 #define MC_CGM_MUX_5_DC_0_DE_MASK (0x80000000U) 990 #define MC_CGM_MUX_5_DC_0_DE_SHIFT (31U) 991 #define MC_CGM_MUX_5_DC_0_DE_WIDTH (1U) 992 #define MC_CGM_MUX_5_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_0_DE_SHIFT)) & MC_CGM_MUX_5_DC_0_DE_MASK) 993 /*! @} */ 994 995 /*! @name MUX_5_DC_1 - Clock Mux 5 Divider 1 Control Register */ 996 /*! @{ */ 997 998 #define MC_CGM_MUX_5_DC_1_DIV_MASK (0xFF0000U) 999 #define MC_CGM_MUX_5_DC_1_DIV_SHIFT (16U) 1000 #define MC_CGM_MUX_5_DC_1_DIV_WIDTH (8U) 1001 #define MC_CGM_MUX_5_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_1_DIV_SHIFT)) & MC_CGM_MUX_5_DC_1_DIV_MASK) 1002 1003 #define MC_CGM_MUX_5_DC_1_DE_MASK (0x80000000U) 1004 #define MC_CGM_MUX_5_DC_1_DE_SHIFT (31U) 1005 #define MC_CGM_MUX_5_DC_1_DE_WIDTH (1U) 1006 #define MC_CGM_MUX_5_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_1_DE_SHIFT)) & MC_CGM_MUX_5_DC_1_DE_MASK) 1007 /*! @} */ 1008 1009 /*! @name MUX_5_DC_2 - Clock Mux 5 Divider 2 Control Register */ 1010 /*! @{ */ 1011 1012 #define MC_CGM_MUX_5_DC_2_DIV_MASK (0xFF0000U) 1013 #define MC_CGM_MUX_5_DC_2_DIV_SHIFT (16U) 1014 #define MC_CGM_MUX_5_DC_2_DIV_WIDTH (8U) 1015 #define MC_CGM_MUX_5_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_2_DIV_SHIFT)) & MC_CGM_MUX_5_DC_2_DIV_MASK) 1016 1017 #define MC_CGM_MUX_5_DC_2_DE_MASK (0x80000000U) 1018 #define MC_CGM_MUX_5_DC_2_DE_SHIFT (31U) 1019 #define MC_CGM_MUX_5_DC_2_DE_WIDTH (1U) 1020 #define MC_CGM_MUX_5_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_2_DE_SHIFT)) & MC_CGM_MUX_5_DC_2_DE_MASK) 1021 /*! @} */ 1022 1023 /*! @name MUX_5_DIV_UPD_STAT - Clock Mux 5 Divider Update Status Register */ 1024 /*! @{ */ 1025 1026 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1027 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1028 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1029 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_MASK) 1030 /*! @} */ 1031 1032 /*! @name MUX_6_CSC - Clock Mux 6 Select Control Register */ 1033 /*! @{ */ 1034 1035 #define MC_CGM_MUX_6_CSC_CG_MASK (0x4U) 1036 #define MC_CGM_MUX_6_CSC_CG_SHIFT (2U) 1037 #define MC_CGM_MUX_6_CSC_CG_WIDTH (1U) 1038 #define MC_CGM_MUX_6_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_CG_SHIFT)) & MC_CGM_MUX_6_CSC_CG_MASK) 1039 1040 #define MC_CGM_MUX_6_CSC_CLK_SW_MASK (0x4U) 1041 #define MC_CGM_MUX_6_CSC_CLK_SW_SHIFT (2U) 1042 #define MC_CGM_MUX_6_CSC_CLK_SW_WIDTH (1U) 1043 #define MC_CGM_MUX_6_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_6_CSC_CLK_SW_MASK) 1044 1045 #define MC_CGM_MUX_6_CSC_FCG_MASK (0x8U) 1046 #define MC_CGM_MUX_6_CSC_FCG_SHIFT (3U) 1047 #define MC_CGM_MUX_6_CSC_FCG_WIDTH (1U) 1048 #define MC_CGM_MUX_6_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_FCG_SHIFT)) & MC_CGM_MUX_6_CSC_FCG_MASK) 1049 1050 #define MC_CGM_MUX_6_CSC_SAFE_SW_MASK (0x8U) 1051 #define MC_CGM_MUX_6_CSC_SAFE_SW_SHIFT (3U) 1052 #define MC_CGM_MUX_6_CSC_SAFE_SW_WIDTH (1U) 1053 #define MC_CGM_MUX_6_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_6_CSC_SAFE_SW_MASK) 1054 1055 #define MC_CGM_MUX_6_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1056 #define MC_CGM_MUX_6_CSC_SELCTL_SHIFT (24U) 1057 #define MC_CGM_MUX_6_CSC_SELCTL_WIDTH (6U) 1058 #define MC_CGM_MUX_6_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_6_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1059 /*! @} */ 1060 1061 /*! @name MUX_6_CSS - Clock Mux 6 Select Status Register */ 1062 /*! @{ */ 1063 1064 #define MC_CGM_MUX_6_CSS_CLK_SW_MASK (0x4U) 1065 #define MC_CGM_MUX_6_CSS_CLK_SW_SHIFT (2U) 1066 #define MC_CGM_MUX_6_CSS_CLK_SW_WIDTH (1U) 1067 #define MC_CGM_MUX_6_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_6_CSS_CLK_SW_MASK) 1068 1069 #define MC_CGM_MUX_6_CSS_SAFE_SW_MASK (0x8U) 1070 #define MC_CGM_MUX_6_CSS_SAFE_SW_SHIFT (3U) 1071 #define MC_CGM_MUX_6_CSS_SAFE_SW_WIDTH (1U) 1072 #define MC_CGM_MUX_6_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_6_CSS_SAFE_SW_MASK) 1073 1074 #define MC_CGM_MUX_6_CSS_GRIP_MASK (0x10000U) 1075 #define MC_CGM_MUX_6_CSS_GRIP_SHIFT (16U) 1076 #define MC_CGM_MUX_6_CSS_GRIP_WIDTH (1U) 1077 #define MC_CGM_MUX_6_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_GRIP_SHIFT)) & MC_CGM_MUX_6_CSS_GRIP_MASK) 1078 1079 #define MC_CGM_MUX_6_CSS_SWIP_MASK (0x10000U) 1080 #define MC_CGM_MUX_6_CSS_SWIP_SHIFT (16U) 1081 #define MC_CGM_MUX_6_CSS_SWIP_WIDTH (1U) 1082 #define MC_CGM_MUX_6_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_SWIP_SHIFT)) & MC_CGM_MUX_6_CSS_SWIP_MASK) 1083 1084 #define MC_CGM_MUX_6_CSS_CS_MASK (0x20000U) 1085 #define MC_CGM_MUX_6_CSS_CS_SHIFT (17U) 1086 #define MC_CGM_MUX_6_CSS_CS_WIDTH (1U) 1087 #define MC_CGM_MUX_6_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_CS_SHIFT)) & MC_CGM_MUX_6_CSS_CS_MASK) 1088 1089 #define MC_CGM_MUX_6_CSS_SWTRG_MASK (0xE0000U) 1090 #define MC_CGM_MUX_6_CSS_SWTRG_SHIFT (17U) 1091 #define MC_CGM_MUX_6_CSS_SWTRG_WIDTH (3U) 1092 #define MC_CGM_MUX_6_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_6_CSS_SWTRG_MASK) 1093 1094 #define MC_CGM_MUX_6_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1095 #define MC_CGM_MUX_6_CSS_SELSTAT_SHIFT (24U) 1096 #define MC_CGM_MUX_6_CSS_SELSTAT_WIDTH (6U) 1097 #define MC_CGM_MUX_6_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_6_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1098 /*! @} */ 1099 1100 /*! @name MUX_6_DC_0 - Clock Mux 6 Divider 0 Control Register */ 1101 /*! @{ */ 1102 1103 #define MC_CGM_MUX_6_DC_0_DIV_MASK (0xFF0000U) 1104 #define MC_CGM_MUX_6_DC_0_DIV_SHIFT (16U) 1105 #define MC_CGM_MUX_6_DC_0_DIV_WIDTH (8U) 1106 #define MC_CGM_MUX_6_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_0_DIV_SHIFT)) & MC_CGM_MUX_6_DC_0_DIV_MASK) 1107 1108 #define MC_CGM_MUX_6_DC_0_DE_MASK (0x80000000U) 1109 #define MC_CGM_MUX_6_DC_0_DE_SHIFT (31U) 1110 #define MC_CGM_MUX_6_DC_0_DE_WIDTH (1U) 1111 #define MC_CGM_MUX_6_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_0_DE_SHIFT)) & MC_CGM_MUX_6_DC_0_DE_MASK) 1112 /*! @} */ 1113 1114 /*! @name MUX_6_DC_1 - Clock Mux 6 Divider 1 Control Register */ 1115 /*! @{ */ 1116 1117 #define MC_CGM_MUX_6_DC_1_DIV_MASK (0xFF0000U) 1118 #define MC_CGM_MUX_6_DC_1_DIV_SHIFT (16U) 1119 #define MC_CGM_MUX_6_DC_1_DIV_WIDTH (8U) 1120 #define MC_CGM_MUX_6_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_1_DIV_SHIFT)) & MC_CGM_MUX_6_DC_1_DIV_MASK) 1121 1122 #define MC_CGM_MUX_6_DC_1_DE_MASK (0x80000000U) 1123 #define MC_CGM_MUX_6_DC_1_DE_SHIFT (31U) 1124 #define MC_CGM_MUX_6_DC_1_DE_WIDTH (1U) 1125 #define MC_CGM_MUX_6_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_1_DE_SHIFT)) & MC_CGM_MUX_6_DC_1_DE_MASK) 1126 /*! @} */ 1127 1128 /*! @name MUX_6_DIV_UPD_STAT - Clock Mux 6 Divider Update Status Register */ 1129 /*! @{ */ 1130 1131 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1132 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1133 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1134 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_MASK) 1135 /*! @} */ 1136 1137 /*! @name MUX_7_CSC - Clock Mux 7 Select Control Register */ 1138 /*! @{ */ 1139 1140 #define MC_CGM_MUX_7_CSC_CLK_SW_MASK (0x4U) 1141 #define MC_CGM_MUX_7_CSC_CLK_SW_SHIFT (2U) 1142 #define MC_CGM_MUX_7_CSC_CLK_SW_WIDTH (1U) 1143 #define MC_CGM_MUX_7_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_7_CSC_CLK_SW_MASK) 1144 1145 #define MC_CGM_MUX_7_CSC_SAFE_SW_MASK (0x8U) 1146 #define MC_CGM_MUX_7_CSC_SAFE_SW_SHIFT (3U) 1147 #define MC_CGM_MUX_7_CSC_SAFE_SW_WIDTH (1U) 1148 #define MC_CGM_MUX_7_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_7_CSC_SAFE_SW_MASK) 1149 1150 #define MC_CGM_MUX_7_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1151 #define MC_CGM_MUX_7_CSC_SELCTL_SHIFT (24U) 1152 #define MC_CGM_MUX_7_CSC_SELCTL_WIDTH (6U) 1153 #define MC_CGM_MUX_7_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_7_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1154 /*! @} */ 1155 1156 /*! @name MUX_7_CSS - Clock Mux 7 Select Status Register */ 1157 /*! @{ */ 1158 1159 #define MC_CGM_MUX_7_CSS_CLK_SW_MASK (0x4U) 1160 #define MC_CGM_MUX_7_CSS_CLK_SW_SHIFT (2U) 1161 #define MC_CGM_MUX_7_CSS_CLK_SW_WIDTH (1U) 1162 #define MC_CGM_MUX_7_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_7_CSS_CLK_SW_MASK) 1163 1164 #define MC_CGM_MUX_7_CSS_SAFE_SW_MASK (0x8U) 1165 #define MC_CGM_MUX_7_CSS_SAFE_SW_SHIFT (3U) 1166 #define MC_CGM_MUX_7_CSS_SAFE_SW_WIDTH (1U) 1167 #define MC_CGM_MUX_7_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_7_CSS_SAFE_SW_MASK) 1168 1169 #define MC_CGM_MUX_7_CSS_SWIP_MASK (0x10000U) 1170 #define MC_CGM_MUX_7_CSS_SWIP_SHIFT (16U) 1171 #define MC_CGM_MUX_7_CSS_SWIP_WIDTH (1U) 1172 #define MC_CGM_MUX_7_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SWIP_SHIFT)) & MC_CGM_MUX_7_CSS_SWIP_MASK) 1173 1174 #define MC_CGM_MUX_7_CSS_SWTRG_MASK (0xE0000U) 1175 #define MC_CGM_MUX_7_CSS_SWTRG_SHIFT (17U) 1176 #define MC_CGM_MUX_7_CSS_SWTRG_WIDTH (3U) 1177 #define MC_CGM_MUX_7_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_7_CSS_SWTRG_MASK) 1178 1179 #define MC_CGM_MUX_7_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1180 #define MC_CGM_MUX_7_CSS_SELSTAT_SHIFT (24U) 1181 #define MC_CGM_MUX_7_CSS_SELSTAT_WIDTH (6U) 1182 #define MC_CGM_MUX_7_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_7_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1183 /*! @} */ 1184 1185 /*! @name MUX_7_DC_0 - Clock Mux 7 Divider 0 Control Register */ 1186 /*! @{ */ 1187 1188 #define MC_CGM_MUX_7_DC_0_DIV_MASK (0xFF0000U) 1189 #define MC_CGM_MUX_7_DC_0_DIV_SHIFT (16U) 1190 #define MC_CGM_MUX_7_DC_0_DIV_WIDTH (8U) 1191 #define MC_CGM_MUX_7_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_0_DIV_SHIFT)) & MC_CGM_MUX_7_DC_0_DIV_MASK) 1192 1193 #define MC_CGM_MUX_7_DC_0_DE_MASK (0x80000000U) 1194 #define MC_CGM_MUX_7_DC_0_DE_SHIFT (31U) 1195 #define MC_CGM_MUX_7_DC_0_DE_WIDTH (1U) 1196 #define MC_CGM_MUX_7_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_0_DE_SHIFT)) & MC_CGM_MUX_7_DC_0_DE_MASK) 1197 /*! @} */ 1198 1199 /*! @name MUX_7_DC_1 - Clock Mux 7 Divider 1 Control Register */ 1200 /*! @{ */ 1201 1202 #define MC_CGM_MUX_7_DC_1_DIV_MASK (0xFF0000U) 1203 #define MC_CGM_MUX_7_DC_1_DIV_SHIFT (16U) 1204 #define MC_CGM_MUX_7_DC_1_DIV_WIDTH (8U) 1205 #define MC_CGM_MUX_7_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_1_DIV_SHIFT)) & MC_CGM_MUX_7_DC_1_DIV_MASK) 1206 1207 #define MC_CGM_MUX_7_DC_1_DE_MASK (0x80000000U) 1208 #define MC_CGM_MUX_7_DC_1_DE_SHIFT (31U) 1209 #define MC_CGM_MUX_7_DC_1_DE_WIDTH (1U) 1210 #define MC_CGM_MUX_7_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_1_DE_SHIFT)) & MC_CGM_MUX_7_DC_1_DE_MASK) 1211 /*! @} */ 1212 1213 /*! @name MUX_7_DC_2 - Clock Mux 7 Divider 2 Control Register */ 1214 /*! @{ */ 1215 1216 #define MC_CGM_MUX_7_DC_2_DIV_MASK (0xFF0000U) 1217 #define MC_CGM_MUX_7_DC_2_DIV_SHIFT (16U) 1218 #define MC_CGM_MUX_7_DC_2_DIV_WIDTH (8U) 1219 #define MC_CGM_MUX_7_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_2_DIV_SHIFT)) & MC_CGM_MUX_7_DC_2_DIV_MASK) 1220 1221 #define MC_CGM_MUX_7_DC_2_DE_MASK (0x80000000U) 1222 #define MC_CGM_MUX_7_DC_2_DE_SHIFT (31U) 1223 #define MC_CGM_MUX_7_DC_2_DE_WIDTH (1U) 1224 #define MC_CGM_MUX_7_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_2_DE_SHIFT)) & MC_CGM_MUX_7_DC_2_DE_MASK) 1225 /*! @} */ 1226 1227 /*! @name MUX_7_DIV_TRIG_CTRL - Clock Mux 7 Divider Trigger Control Register */ 1228 /*! @{ */ 1229 1230 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_MASK (0x1U) 1231 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_SHIFT (0U) 1232 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_WIDTH (1U) 1233 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_SHIFT)) & MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_MASK) 1234 1235 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN_MASK (0x80000000U) 1236 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN_SHIFT (31U) 1237 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN_WIDTH (1U) 1238 #define MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN_SHIFT)) & MC_CGM_MUX_7_DIV_TRIG_CTRL_HHEN_MASK) 1239 /*! @} */ 1240 1241 /*! @name MUX_7_DIV_TRIG - Clock Mux 7 Divider Trigger Register */ 1242 /*! @{ */ 1243 1244 #define MC_CGM_MUX_7_DIV_TRIG_TRIGGER_MASK (0xFFFFFFFFU) 1245 #define MC_CGM_MUX_7_DIV_TRIG_TRIGGER_SHIFT (0U) 1246 #define MC_CGM_MUX_7_DIV_TRIG_TRIGGER_WIDTH (32U) 1247 #define MC_CGM_MUX_7_DIV_TRIG_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DIV_TRIG_TRIGGER_SHIFT)) & MC_CGM_MUX_7_DIV_TRIG_TRIGGER_MASK) 1248 /*! @} */ 1249 1250 /*! @name MUX_7_DIV_UPD_STAT - Clock Mux 7 Divider Update Status Register */ 1251 /*! @{ */ 1252 1253 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1254 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1255 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1256 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_MASK) 1257 /*! @} */ 1258 1259 /*! @name MUX_8_CSC - Clock Mux 8 Select Control Register */ 1260 /*! @{ */ 1261 1262 #define MC_CGM_MUX_8_CSC_CLK_SW_MASK (0x4U) 1263 #define MC_CGM_MUX_8_CSC_CLK_SW_SHIFT (2U) 1264 #define MC_CGM_MUX_8_CSC_CLK_SW_WIDTH (1U) 1265 #define MC_CGM_MUX_8_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_8_CSC_CLK_SW_MASK) 1266 1267 #define MC_CGM_MUX_8_CSC_SAFE_SW_MASK (0x8U) 1268 #define MC_CGM_MUX_8_CSC_SAFE_SW_SHIFT (3U) 1269 #define MC_CGM_MUX_8_CSC_SAFE_SW_WIDTH (1U) 1270 #define MC_CGM_MUX_8_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_8_CSC_SAFE_SW_MASK) 1271 1272 #define MC_CGM_MUX_8_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1273 #define MC_CGM_MUX_8_CSC_SELCTL_SHIFT (24U) 1274 #define MC_CGM_MUX_8_CSC_SELCTL_WIDTH (6U) 1275 #define MC_CGM_MUX_8_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_8_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1276 /*! @} */ 1277 1278 /*! @name MUX_8_CSS - Clock Mux 8 Select Status Register */ 1279 /*! @{ */ 1280 1281 #define MC_CGM_MUX_8_CSS_CLK_SW_MASK (0x4U) 1282 #define MC_CGM_MUX_8_CSS_CLK_SW_SHIFT (2U) 1283 #define MC_CGM_MUX_8_CSS_CLK_SW_WIDTH (1U) 1284 #define MC_CGM_MUX_8_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_8_CSS_CLK_SW_MASK) 1285 1286 #define MC_CGM_MUX_8_CSS_SAFE_SW_MASK (0x8U) 1287 #define MC_CGM_MUX_8_CSS_SAFE_SW_SHIFT (3U) 1288 #define MC_CGM_MUX_8_CSS_SAFE_SW_WIDTH (1U) 1289 #define MC_CGM_MUX_8_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_8_CSS_SAFE_SW_MASK) 1290 1291 #define MC_CGM_MUX_8_CSS_SWIP_MASK (0x10000U) 1292 #define MC_CGM_MUX_8_CSS_SWIP_SHIFT (16U) 1293 #define MC_CGM_MUX_8_CSS_SWIP_WIDTH (1U) 1294 #define MC_CGM_MUX_8_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SWIP_SHIFT)) & MC_CGM_MUX_8_CSS_SWIP_MASK) 1295 1296 #define MC_CGM_MUX_8_CSS_SWTRG_MASK (0xE0000U) 1297 #define MC_CGM_MUX_8_CSS_SWTRG_SHIFT (17U) 1298 #define MC_CGM_MUX_8_CSS_SWTRG_WIDTH (3U) 1299 #define MC_CGM_MUX_8_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_8_CSS_SWTRG_MASK) 1300 1301 #define MC_CGM_MUX_8_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1302 #define MC_CGM_MUX_8_CSS_SELSTAT_SHIFT (24U) 1303 #define MC_CGM_MUX_8_CSS_SELSTAT_WIDTH (6U) 1304 #define MC_CGM_MUX_8_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_8_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1305 /*! @} */ 1306 1307 /*! @name MUX_8_DC_0 - Clock Mux 8 Divider 0 Control Register */ 1308 /*! @{ */ 1309 1310 #define MC_CGM_MUX_8_DC_0_DIV_MASK (0xFF0000U) 1311 #define MC_CGM_MUX_8_DC_0_DIV_SHIFT (16U) 1312 #define MC_CGM_MUX_8_DC_0_DIV_WIDTH (8U) 1313 #define MC_CGM_MUX_8_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_0_DIV_SHIFT)) & MC_CGM_MUX_8_DC_0_DIV_MASK) 1314 1315 #define MC_CGM_MUX_8_DC_0_DE_MASK (0x80000000U) 1316 #define MC_CGM_MUX_8_DC_0_DE_SHIFT (31U) 1317 #define MC_CGM_MUX_8_DC_0_DE_WIDTH (1U) 1318 #define MC_CGM_MUX_8_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_0_DE_SHIFT)) & MC_CGM_MUX_8_DC_0_DE_MASK) 1319 /*! @} */ 1320 1321 /*! @name MUX_8_DC_1 - Clock Mux 8 Divider 1 Control Register */ 1322 /*! @{ */ 1323 1324 #define MC_CGM_MUX_8_DC_1_DIV_MASK (0xFF0000U) 1325 #define MC_CGM_MUX_8_DC_1_DIV_SHIFT (16U) 1326 #define MC_CGM_MUX_8_DC_1_DIV_WIDTH (8U) 1327 #define MC_CGM_MUX_8_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_1_DIV_SHIFT)) & MC_CGM_MUX_8_DC_1_DIV_MASK) 1328 1329 #define MC_CGM_MUX_8_DC_1_DE_MASK (0x80000000U) 1330 #define MC_CGM_MUX_8_DC_1_DE_SHIFT (31U) 1331 #define MC_CGM_MUX_8_DC_1_DE_WIDTH (1U) 1332 #define MC_CGM_MUX_8_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_1_DE_SHIFT)) & MC_CGM_MUX_8_DC_1_DE_MASK) 1333 /*! @} */ 1334 1335 /*! @name MUX_8_DIV_UPD_STAT - Clock Mux 8 Divider Update Status Register */ 1336 /*! @{ */ 1337 1338 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1339 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1340 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1341 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_MASK) 1342 /*! @} */ 1343 1344 /*! @name MUX_9_CSC - Clock Mux 9 Select Control Register */ 1345 /*! @{ */ 1346 1347 #define MC_CGM_MUX_9_CSC_CLK_SW_MASK (0x4U) 1348 #define MC_CGM_MUX_9_CSC_CLK_SW_SHIFT (2U) 1349 #define MC_CGM_MUX_9_CSC_CLK_SW_WIDTH (1U) 1350 #define MC_CGM_MUX_9_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_9_CSC_CLK_SW_MASK) 1351 1352 #define MC_CGM_MUX_9_CSC_SAFE_SW_MASK (0x8U) 1353 #define MC_CGM_MUX_9_CSC_SAFE_SW_SHIFT (3U) 1354 #define MC_CGM_MUX_9_CSC_SAFE_SW_WIDTH (1U) 1355 #define MC_CGM_MUX_9_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_9_CSC_SAFE_SW_MASK) 1356 1357 #define MC_CGM_MUX_9_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1358 #define MC_CGM_MUX_9_CSC_SELCTL_SHIFT (24U) 1359 #define MC_CGM_MUX_9_CSC_SELCTL_WIDTH (6U) 1360 #define MC_CGM_MUX_9_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_9_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1361 /*! @} */ 1362 1363 /*! @name MUX_9_CSS - Clock Mux 9 Select Status Register */ 1364 /*! @{ */ 1365 1366 #define MC_CGM_MUX_9_CSS_CLK_SW_MASK (0x4U) 1367 #define MC_CGM_MUX_9_CSS_CLK_SW_SHIFT (2U) 1368 #define MC_CGM_MUX_9_CSS_CLK_SW_WIDTH (1U) 1369 #define MC_CGM_MUX_9_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_9_CSS_CLK_SW_MASK) 1370 1371 #define MC_CGM_MUX_9_CSS_SAFE_SW_MASK (0x8U) 1372 #define MC_CGM_MUX_9_CSS_SAFE_SW_SHIFT (3U) 1373 #define MC_CGM_MUX_9_CSS_SAFE_SW_WIDTH (1U) 1374 #define MC_CGM_MUX_9_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_9_CSS_SAFE_SW_MASK) 1375 1376 #define MC_CGM_MUX_9_CSS_SWIP_MASK (0x10000U) 1377 #define MC_CGM_MUX_9_CSS_SWIP_SHIFT (16U) 1378 #define MC_CGM_MUX_9_CSS_SWIP_WIDTH (1U) 1379 #define MC_CGM_MUX_9_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SWIP_SHIFT)) & MC_CGM_MUX_9_CSS_SWIP_MASK) 1380 1381 #define MC_CGM_MUX_9_CSS_SWTRG_MASK (0xE0000U) 1382 #define MC_CGM_MUX_9_CSS_SWTRG_SHIFT (17U) 1383 #define MC_CGM_MUX_9_CSS_SWTRG_WIDTH (3U) 1384 #define MC_CGM_MUX_9_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_9_CSS_SWTRG_MASK) 1385 1386 #define MC_CGM_MUX_9_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1387 #define MC_CGM_MUX_9_CSS_SELSTAT_SHIFT (24U) 1388 #define MC_CGM_MUX_9_CSS_SELSTAT_WIDTH (6U) 1389 #define MC_CGM_MUX_9_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_9_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1390 /*! @} */ 1391 1392 /*! @name MUX_9_DC_0 - Clock Mux 9 Divider 0 Control Register */ 1393 /*! @{ */ 1394 1395 #define MC_CGM_MUX_9_DC_0_DIV_MASK (0xFF0000U) 1396 #define MC_CGM_MUX_9_DC_0_DIV_SHIFT (16U) 1397 #define MC_CGM_MUX_9_DC_0_DIV_WIDTH (8U) 1398 #define MC_CGM_MUX_9_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_0_DIV_SHIFT)) & MC_CGM_MUX_9_DC_0_DIV_MASK) 1399 1400 #define MC_CGM_MUX_9_DC_0_DE_MASK (0x80000000U) 1401 #define MC_CGM_MUX_9_DC_0_DE_SHIFT (31U) 1402 #define MC_CGM_MUX_9_DC_0_DE_WIDTH (1U) 1403 #define MC_CGM_MUX_9_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_0_DE_SHIFT)) & MC_CGM_MUX_9_DC_0_DE_MASK) 1404 /*! @} */ 1405 1406 /*! @name MUX_9_DC_1 - Clock Mux 9 Divider 1 Control Register */ 1407 /*! @{ */ 1408 1409 #define MC_CGM_MUX_9_DC_1_DIV_MASK (0xFF0000U) 1410 #define MC_CGM_MUX_9_DC_1_DIV_SHIFT (16U) 1411 #define MC_CGM_MUX_9_DC_1_DIV_WIDTH (8U) 1412 #define MC_CGM_MUX_9_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_1_DIV_SHIFT)) & MC_CGM_MUX_9_DC_1_DIV_MASK) 1413 1414 #define MC_CGM_MUX_9_DC_1_DE_MASK (0x80000000U) 1415 #define MC_CGM_MUX_9_DC_1_DE_SHIFT (31U) 1416 #define MC_CGM_MUX_9_DC_1_DE_WIDTH (1U) 1417 #define MC_CGM_MUX_9_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_1_DE_SHIFT)) & MC_CGM_MUX_9_DC_1_DE_MASK) 1418 /*! @} */ 1419 1420 /*! @name MUX_9_DC_2 - Clock Mux 9 Divider 2 Control Register */ 1421 /*! @{ */ 1422 1423 #define MC_CGM_MUX_9_DC_2_DIV_MASK (0xFF0000U) 1424 #define MC_CGM_MUX_9_DC_2_DIV_SHIFT (16U) 1425 #define MC_CGM_MUX_9_DC_2_DIV_WIDTH (8U) 1426 #define MC_CGM_MUX_9_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_2_DIV_SHIFT)) & MC_CGM_MUX_9_DC_2_DIV_MASK) 1427 1428 #define MC_CGM_MUX_9_DC_2_DE_MASK (0x80000000U) 1429 #define MC_CGM_MUX_9_DC_2_DE_SHIFT (31U) 1430 #define MC_CGM_MUX_9_DC_2_DE_WIDTH (1U) 1431 #define MC_CGM_MUX_9_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_2_DE_SHIFT)) & MC_CGM_MUX_9_DC_2_DE_MASK) 1432 /*! @} */ 1433 1434 /*! @name MUX_9_DIV_UPD_STAT - Clock Mux 9 Divider Update Status Register */ 1435 /*! @{ */ 1436 1437 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1438 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1439 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1440 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_MASK) 1441 /*! @} */ 1442 1443 /*! @name MUX_10_CSC - Clock Mux 10 Select Control Register */ 1444 /*! @{ */ 1445 1446 #define MC_CGM_MUX_10_CSC_CG_MASK (0x4U) 1447 #define MC_CGM_MUX_10_CSC_CG_SHIFT (2U) 1448 #define MC_CGM_MUX_10_CSC_CG_WIDTH (1U) 1449 #define MC_CGM_MUX_10_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_CG_SHIFT)) & MC_CGM_MUX_10_CSC_CG_MASK) 1450 1451 #define MC_CGM_MUX_10_CSC_CLK_SW_MASK (0x4U) 1452 #define MC_CGM_MUX_10_CSC_CLK_SW_SHIFT (2U) 1453 #define MC_CGM_MUX_10_CSC_CLK_SW_WIDTH (1U) 1454 #define MC_CGM_MUX_10_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_10_CSC_CLK_SW_MASK) 1455 1456 #define MC_CGM_MUX_10_CSC_FCG_MASK (0x8U) 1457 #define MC_CGM_MUX_10_CSC_FCG_SHIFT (3U) 1458 #define MC_CGM_MUX_10_CSC_FCG_WIDTH (1U) 1459 #define MC_CGM_MUX_10_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_FCG_SHIFT)) & MC_CGM_MUX_10_CSC_FCG_MASK) 1460 1461 #define MC_CGM_MUX_10_CSC_SAFE_SW_MASK (0x8U) 1462 #define MC_CGM_MUX_10_CSC_SAFE_SW_SHIFT (3U) 1463 #define MC_CGM_MUX_10_CSC_SAFE_SW_WIDTH (1U) 1464 #define MC_CGM_MUX_10_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_10_CSC_SAFE_SW_MASK) 1465 1466 #define MC_CGM_MUX_10_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1467 #define MC_CGM_MUX_10_CSC_SELCTL_SHIFT (24U) 1468 #define MC_CGM_MUX_10_CSC_SELCTL_WIDTH (6U) 1469 #define MC_CGM_MUX_10_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_10_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1470 /*! @} */ 1471 1472 /*! @name MUX_10_CSS - Clock Mux 10 Select Status Register */ 1473 /*! @{ */ 1474 1475 #define MC_CGM_MUX_10_CSS_CLK_SW_MASK (0x4U) 1476 #define MC_CGM_MUX_10_CSS_CLK_SW_SHIFT (2U) 1477 #define MC_CGM_MUX_10_CSS_CLK_SW_WIDTH (1U) 1478 #define MC_CGM_MUX_10_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_10_CSS_CLK_SW_MASK) 1479 1480 #define MC_CGM_MUX_10_CSS_SAFE_SW_MASK (0x8U) 1481 #define MC_CGM_MUX_10_CSS_SAFE_SW_SHIFT (3U) 1482 #define MC_CGM_MUX_10_CSS_SAFE_SW_WIDTH (1U) 1483 #define MC_CGM_MUX_10_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_10_CSS_SAFE_SW_MASK) 1484 1485 #define MC_CGM_MUX_10_CSS_GRIP_MASK (0x10000U) 1486 #define MC_CGM_MUX_10_CSS_GRIP_SHIFT (16U) 1487 #define MC_CGM_MUX_10_CSS_GRIP_WIDTH (1U) 1488 #define MC_CGM_MUX_10_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_GRIP_SHIFT)) & MC_CGM_MUX_10_CSS_GRIP_MASK) 1489 1490 #define MC_CGM_MUX_10_CSS_SWIP_MASK (0x10000U) 1491 #define MC_CGM_MUX_10_CSS_SWIP_SHIFT (16U) 1492 #define MC_CGM_MUX_10_CSS_SWIP_WIDTH (1U) 1493 #define MC_CGM_MUX_10_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SWIP_SHIFT)) & MC_CGM_MUX_10_CSS_SWIP_MASK) 1494 1495 #define MC_CGM_MUX_10_CSS_CS_MASK (0x20000U) 1496 #define MC_CGM_MUX_10_CSS_CS_SHIFT (17U) 1497 #define MC_CGM_MUX_10_CSS_CS_WIDTH (1U) 1498 #define MC_CGM_MUX_10_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_CS_SHIFT)) & MC_CGM_MUX_10_CSS_CS_MASK) 1499 1500 #define MC_CGM_MUX_10_CSS_SWTRG_MASK (0xE0000U) 1501 #define MC_CGM_MUX_10_CSS_SWTRG_SHIFT (17U) 1502 #define MC_CGM_MUX_10_CSS_SWTRG_WIDTH (3U) 1503 #define MC_CGM_MUX_10_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_10_CSS_SWTRG_MASK) 1504 1505 #define MC_CGM_MUX_10_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1506 #define MC_CGM_MUX_10_CSS_SELSTAT_SHIFT (24U) 1507 #define MC_CGM_MUX_10_CSS_SELSTAT_WIDTH (6U) 1508 #define MC_CGM_MUX_10_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_10_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1509 /*! @} */ 1510 1511 /*! @name MUX_10_DC_0 - Clock Mux 10 Divider 0 Control Register */ 1512 /*! @{ */ 1513 1514 #define MC_CGM_MUX_10_DC_0_DIV_MASK (0xFF0000U) 1515 #define MC_CGM_MUX_10_DC_0_DIV_SHIFT (16U) 1516 #define MC_CGM_MUX_10_DC_0_DIV_WIDTH (8U) 1517 #define MC_CGM_MUX_10_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DC_0_DIV_SHIFT)) & MC_CGM_MUX_10_DC_0_DIV_MASK) 1518 1519 #define MC_CGM_MUX_10_DC_0_DE_MASK (0x80000000U) 1520 #define MC_CGM_MUX_10_DC_0_DE_SHIFT (31U) 1521 #define MC_CGM_MUX_10_DC_0_DE_WIDTH (1U) 1522 #define MC_CGM_MUX_10_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DC_0_DE_SHIFT)) & MC_CGM_MUX_10_DC_0_DE_MASK) 1523 /*! @} */ 1524 1525 /*! @name MUX_10_DIV_UPD_STAT - Clock Mux 10 Divider Update Status Register */ 1526 /*! @{ */ 1527 1528 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1529 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1530 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1531 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_MASK) 1532 /*! @} */ 1533 1534 /*! @name MUX_11_CSC - Clock Mux 11 Select Control Register */ 1535 /*! @{ */ 1536 1537 #define MC_CGM_MUX_11_CSC_CLK_SW_MASK (0x4U) 1538 #define MC_CGM_MUX_11_CSC_CLK_SW_SHIFT (2U) 1539 #define MC_CGM_MUX_11_CSC_CLK_SW_WIDTH (1U) 1540 #define MC_CGM_MUX_11_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_11_CSC_CLK_SW_MASK) 1541 1542 #define MC_CGM_MUX_11_CSC_SAFE_SW_MASK (0x8U) 1543 #define MC_CGM_MUX_11_CSC_SAFE_SW_SHIFT (3U) 1544 #define MC_CGM_MUX_11_CSC_SAFE_SW_WIDTH (1U) 1545 #define MC_CGM_MUX_11_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_11_CSC_SAFE_SW_MASK) 1546 1547 #define MC_CGM_MUX_11_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1548 #define MC_CGM_MUX_11_CSC_SELCTL_SHIFT (24U) 1549 #define MC_CGM_MUX_11_CSC_SELCTL_WIDTH (6U) 1550 #define MC_CGM_MUX_11_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_11_CSC_SELCTL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1551 /*! @} */ 1552 1553 /*! @name MUX_11_CSS - Clock Mux 11 Select Status Register */ 1554 /*! @{ */ 1555 1556 #define MC_CGM_MUX_11_CSS_CLK_SW_MASK (0x4U) 1557 #define MC_CGM_MUX_11_CSS_CLK_SW_SHIFT (2U) 1558 #define MC_CGM_MUX_11_CSS_CLK_SW_WIDTH (1U) 1559 #define MC_CGM_MUX_11_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_11_CSS_CLK_SW_MASK) 1560 1561 #define MC_CGM_MUX_11_CSS_SAFE_SW_MASK (0x8U) 1562 #define MC_CGM_MUX_11_CSS_SAFE_SW_SHIFT (3U) 1563 #define MC_CGM_MUX_11_CSS_SAFE_SW_WIDTH (1U) 1564 #define MC_CGM_MUX_11_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_11_CSS_SAFE_SW_MASK) 1565 1566 #define MC_CGM_MUX_11_CSS_SWIP_MASK (0x10000U) 1567 #define MC_CGM_MUX_11_CSS_SWIP_SHIFT (16U) 1568 #define MC_CGM_MUX_11_CSS_SWIP_WIDTH (1U) 1569 #define MC_CGM_MUX_11_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_SWIP_SHIFT)) & MC_CGM_MUX_11_CSS_SWIP_MASK) 1570 1571 #define MC_CGM_MUX_11_CSS_SWTRG_MASK (0xE0000U) 1572 #define MC_CGM_MUX_11_CSS_SWTRG_SHIFT (17U) 1573 #define MC_CGM_MUX_11_CSS_SWTRG_WIDTH (3U) 1574 #define MC_CGM_MUX_11_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_11_CSS_SWTRG_MASK) 1575 1576 #define MC_CGM_MUX_11_CSS_SELSTAT_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1577 #define MC_CGM_MUX_11_CSS_SELSTAT_SHIFT (24U) 1578 #define MC_CGM_MUX_11_CSS_SELSTAT_WIDTH (6U) 1579 #define MC_CGM_MUX_11_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_11_CSS_SELSTAT_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ 1580 /*! @} */ 1581 1582 /*! @name MUX_11_DC_0 - Clock Mux 11 Divider 0 Control Register */ 1583 /*! @{ */ 1584 1585 #define MC_CGM_MUX_11_DC_0_DIV_MASK (0xFF0000U) 1586 #define MC_CGM_MUX_11_DC_0_DIV_SHIFT (16U) 1587 #define MC_CGM_MUX_11_DC_0_DIV_WIDTH (8U) 1588 #define MC_CGM_MUX_11_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DC_0_DIV_SHIFT)) & MC_CGM_MUX_11_DC_0_DIV_MASK) 1589 1590 #define MC_CGM_MUX_11_DC_0_DE_MASK (0x80000000U) 1591 #define MC_CGM_MUX_11_DC_0_DE_SHIFT (31U) 1592 #define MC_CGM_MUX_11_DC_0_DE_WIDTH (1U) 1593 #define MC_CGM_MUX_11_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DC_0_DE_SHIFT)) & MC_CGM_MUX_11_DC_0_DE_MASK) 1594 /*! @} */ 1595 1596 /*! @name MUX_11_DIV_UPD_STAT - Clock Mux 11 Divider Update Status Register */ 1597 /*! @{ */ 1598 1599 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1600 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1601 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1602 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_MASK) 1603 /*! @} */ 1604 1605 /*! @name MUX_12_CSC - Clock Mux 12 Select Control Register */ 1606 /*! @{ */ 1607 1608 #define MC_CGM_MUX_12_CSC_CLK_SW_MASK (0x4U) 1609 #define MC_CGM_MUX_12_CSC_CLK_SW_SHIFT (2U) 1610 #define MC_CGM_MUX_12_CSC_CLK_SW_WIDTH (1U) 1611 #define MC_CGM_MUX_12_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_12_CSC_CLK_SW_MASK) 1612 1613 #define MC_CGM_MUX_12_CSC_SAFE_SW_MASK (0x8U) 1614 #define MC_CGM_MUX_12_CSC_SAFE_SW_SHIFT (3U) 1615 #define MC_CGM_MUX_12_CSC_SAFE_SW_WIDTH (1U) 1616 #define MC_CGM_MUX_12_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_12_CSC_SAFE_SW_MASK) 1617 1618 #define MC_CGM_MUX_12_CSC_SELCTL_MASK (0x3F000000U) 1619 #define MC_CGM_MUX_12_CSC_SELCTL_SHIFT (24U) 1620 #define MC_CGM_MUX_12_CSC_SELCTL_WIDTH (6U) 1621 #define MC_CGM_MUX_12_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_12_CSC_SELCTL_MASK) 1622 /*! @} */ 1623 1624 /*! @name MUX_12_CSS - Clock Mux 12 Select Status Register */ 1625 /*! @{ */ 1626 1627 #define MC_CGM_MUX_12_CSS_CLK_SW_MASK (0x4U) 1628 #define MC_CGM_MUX_12_CSS_CLK_SW_SHIFT (2U) 1629 #define MC_CGM_MUX_12_CSS_CLK_SW_WIDTH (1U) 1630 #define MC_CGM_MUX_12_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_12_CSS_CLK_SW_MASK) 1631 1632 #define MC_CGM_MUX_12_CSS_SAFE_SW_MASK (0x8U) 1633 #define MC_CGM_MUX_12_CSS_SAFE_SW_SHIFT (3U) 1634 #define MC_CGM_MUX_12_CSS_SAFE_SW_WIDTH (1U) 1635 #define MC_CGM_MUX_12_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_12_CSS_SAFE_SW_MASK) 1636 1637 #define MC_CGM_MUX_12_CSS_SWIP_MASK (0x10000U) 1638 #define MC_CGM_MUX_12_CSS_SWIP_SHIFT (16U) 1639 #define MC_CGM_MUX_12_CSS_SWIP_WIDTH (1U) 1640 #define MC_CGM_MUX_12_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSS_SWIP_SHIFT)) & MC_CGM_MUX_12_CSS_SWIP_MASK) 1641 1642 #define MC_CGM_MUX_12_CSS_SWTRG_MASK (0xE0000U) 1643 #define MC_CGM_MUX_12_CSS_SWTRG_SHIFT (17U) 1644 #define MC_CGM_MUX_12_CSS_SWTRG_WIDTH (3U) 1645 #define MC_CGM_MUX_12_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_12_CSS_SWTRG_MASK) 1646 1647 #define MC_CGM_MUX_12_CSS_SELSTAT_MASK (0x3F000000U) 1648 #define MC_CGM_MUX_12_CSS_SELSTAT_SHIFT (24U) 1649 #define MC_CGM_MUX_12_CSS_SELSTAT_WIDTH (6U) 1650 #define MC_CGM_MUX_12_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_12_CSS_SELSTAT_MASK) 1651 /*! @} */ 1652 1653 /*! @name MUX_12_DC_0 - Clock Mux 12 Divider 0 Control Register */ 1654 /*! @{ */ 1655 1656 #define MC_CGM_MUX_12_DC_0_DIV_MASK (0xFF0000U) 1657 #define MC_CGM_MUX_12_DC_0_DIV_SHIFT (16U) 1658 #define MC_CGM_MUX_12_DC_0_DIV_WIDTH (8U) 1659 #define MC_CGM_MUX_12_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_DC_0_DIV_SHIFT)) & MC_CGM_MUX_12_DC_0_DIV_MASK) 1660 1661 #define MC_CGM_MUX_12_DC_0_DE_MASK (0x80000000U) 1662 #define MC_CGM_MUX_12_DC_0_DE_SHIFT (31U) 1663 #define MC_CGM_MUX_12_DC_0_DE_WIDTH (1U) 1664 #define MC_CGM_MUX_12_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_DC_0_DE_SHIFT)) & MC_CGM_MUX_12_DC_0_DE_MASK) 1665 /*! @} */ 1666 1667 /*! @name MUX_12_DIV_UPD_STAT - Clock Mux 12 Divider Update Status Register */ 1668 /*! @{ */ 1669 1670 #define MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1671 #define MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1672 #define MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1673 #define MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_12_DIV_UPD_STAT_DIV_STAT_MASK) 1674 /*! @} */ 1675 1676 /*! @name MUX_13_CSC - Clock Mux 13 Select Control Register */ 1677 /*! @{ */ 1678 1679 #define MC_CGM_MUX_13_CSC_CLK_SW_MASK (0x4U) 1680 #define MC_CGM_MUX_13_CSC_CLK_SW_SHIFT (2U) 1681 #define MC_CGM_MUX_13_CSC_CLK_SW_WIDTH (1U) 1682 #define MC_CGM_MUX_13_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_13_CSC_CLK_SW_MASK) 1683 1684 #define MC_CGM_MUX_13_CSC_SAFE_SW_MASK (0x8U) 1685 #define MC_CGM_MUX_13_CSC_SAFE_SW_SHIFT (3U) 1686 #define MC_CGM_MUX_13_CSC_SAFE_SW_WIDTH (1U) 1687 #define MC_CGM_MUX_13_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_13_CSC_SAFE_SW_MASK) 1688 1689 #define MC_CGM_MUX_13_CSC_SELCTL_MASK (0x3F000000U) 1690 #define MC_CGM_MUX_13_CSC_SELCTL_SHIFT (24U) 1691 #define MC_CGM_MUX_13_CSC_SELCTL_WIDTH (6U) 1692 #define MC_CGM_MUX_13_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_13_CSC_SELCTL_MASK) 1693 /*! @} */ 1694 1695 /*! @name MUX_13_CSS - Clock Mux 13 Select Status Register */ 1696 /*! @{ */ 1697 1698 #define MC_CGM_MUX_13_CSS_CLK_SW_MASK (0x4U) 1699 #define MC_CGM_MUX_13_CSS_CLK_SW_SHIFT (2U) 1700 #define MC_CGM_MUX_13_CSS_CLK_SW_WIDTH (1U) 1701 #define MC_CGM_MUX_13_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_13_CSS_CLK_SW_MASK) 1702 1703 #define MC_CGM_MUX_13_CSS_SAFE_SW_MASK (0x8U) 1704 #define MC_CGM_MUX_13_CSS_SAFE_SW_SHIFT (3U) 1705 #define MC_CGM_MUX_13_CSS_SAFE_SW_WIDTH (1U) 1706 #define MC_CGM_MUX_13_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_13_CSS_SAFE_SW_MASK) 1707 1708 #define MC_CGM_MUX_13_CSS_SWIP_MASK (0x10000U) 1709 #define MC_CGM_MUX_13_CSS_SWIP_SHIFT (16U) 1710 #define MC_CGM_MUX_13_CSS_SWIP_WIDTH (1U) 1711 #define MC_CGM_MUX_13_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSS_SWIP_SHIFT)) & MC_CGM_MUX_13_CSS_SWIP_MASK) 1712 1713 #define MC_CGM_MUX_13_CSS_SWTRG_MASK (0xE0000U) 1714 #define MC_CGM_MUX_13_CSS_SWTRG_SHIFT (17U) 1715 #define MC_CGM_MUX_13_CSS_SWTRG_WIDTH (3U) 1716 #define MC_CGM_MUX_13_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_13_CSS_SWTRG_MASK) 1717 1718 #define MC_CGM_MUX_13_CSS_SELSTAT_MASK (0x3F000000U) 1719 #define MC_CGM_MUX_13_CSS_SELSTAT_SHIFT (24U) 1720 #define MC_CGM_MUX_13_CSS_SELSTAT_WIDTH (6U) 1721 #define MC_CGM_MUX_13_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_13_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_13_CSS_SELSTAT_MASK) 1722 /*! @} */ 1723 1724 /*! @name MUX_14_CSC - Clock Mux 14 Select Control Register */ 1725 /*! @{ */ 1726 1727 #define MC_CGM_MUX_14_CSC_CLK_SW_MASK (0x4U) 1728 #define MC_CGM_MUX_14_CSC_CLK_SW_SHIFT (2U) 1729 #define MC_CGM_MUX_14_CSC_CLK_SW_WIDTH (1U) 1730 #define MC_CGM_MUX_14_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_14_CSC_CLK_SW_MASK) 1731 1732 #define MC_CGM_MUX_14_CSC_SAFE_SW_MASK (0x8U) 1733 #define MC_CGM_MUX_14_CSC_SAFE_SW_SHIFT (3U) 1734 #define MC_CGM_MUX_14_CSC_SAFE_SW_WIDTH (1U) 1735 #define MC_CGM_MUX_14_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_14_CSC_SAFE_SW_MASK) 1736 1737 #define MC_CGM_MUX_14_CSC_SELCTL_MASK (0x3F000000U) 1738 #define MC_CGM_MUX_14_CSC_SELCTL_SHIFT (24U) 1739 #define MC_CGM_MUX_14_CSC_SELCTL_WIDTH (6U) 1740 #define MC_CGM_MUX_14_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_14_CSC_SELCTL_MASK) 1741 /*! @} */ 1742 1743 /*! @name MUX_14_CSS - Clock Mux 14 Select Status Register */ 1744 /*! @{ */ 1745 1746 #define MC_CGM_MUX_14_CSS_CLK_SW_MASK (0x4U) 1747 #define MC_CGM_MUX_14_CSS_CLK_SW_SHIFT (2U) 1748 #define MC_CGM_MUX_14_CSS_CLK_SW_WIDTH (1U) 1749 #define MC_CGM_MUX_14_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_14_CSS_CLK_SW_MASK) 1750 1751 #define MC_CGM_MUX_14_CSS_SAFE_SW_MASK (0x8U) 1752 #define MC_CGM_MUX_14_CSS_SAFE_SW_SHIFT (3U) 1753 #define MC_CGM_MUX_14_CSS_SAFE_SW_WIDTH (1U) 1754 #define MC_CGM_MUX_14_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_14_CSS_SAFE_SW_MASK) 1755 1756 #define MC_CGM_MUX_14_CSS_SWIP_MASK (0x10000U) 1757 #define MC_CGM_MUX_14_CSS_SWIP_SHIFT (16U) 1758 #define MC_CGM_MUX_14_CSS_SWIP_WIDTH (1U) 1759 #define MC_CGM_MUX_14_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSS_SWIP_SHIFT)) & MC_CGM_MUX_14_CSS_SWIP_MASK) 1760 1761 #define MC_CGM_MUX_14_CSS_SWTRG_MASK (0xE0000U) 1762 #define MC_CGM_MUX_14_CSS_SWTRG_SHIFT (17U) 1763 #define MC_CGM_MUX_14_CSS_SWTRG_WIDTH (3U) 1764 #define MC_CGM_MUX_14_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_14_CSS_SWTRG_MASK) 1765 1766 #define MC_CGM_MUX_14_CSS_SELSTAT_MASK (0x3F000000U) 1767 #define MC_CGM_MUX_14_CSS_SELSTAT_SHIFT (24U) 1768 #define MC_CGM_MUX_14_CSS_SELSTAT_WIDTH (6U) 1769 #define MC_CGM_MUX_14_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_14_CSS_SELSTAT_MASK) 1770 /*! @} */ 1771 1772 /*! @name MUX_14_DC_0 - Clock Mux 14 Divider 0 Control Register */ 1773 /*! @{ */ 1774 1775 #define MC_CGM_MUX_14_DC_0_DIV_MASK (0xFF0000U) 1776 #define MC_CGM_MUX_14_DC_0_DIV_SHIFT (16U) 1777 #define MC_CGM_MUX_14_DC_0_DIV_WIDTH (8U) 1778 #define MC_CGM_MUX_14_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_DC_0_DIV_SHIFT)) & MC_CGM_MUX_14_DC_0_DIV_MASK) 1779 1780 #define MC_CGM_MUX_14_DC_0_DE_MASK (0x80000000U) 1781 #define MC_CGM_MUX_14_DC_0_DE_SHIFT (31U) 1782 #define MC_CGM_MUX_14_DC_0_DE_WIDTH (1U) 1783 #define MC_CGM_MUX_14_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_DC_0_DE_SHIFT)) & MC_CGM_MUX_14_DC_0_DE_MASK) 1784 /*! @} */ 1785 1786 /*! @name MUX_14_DIV_UPD_STAT - Clock Mux 14 Divider Update Status Register */ 1787 /*! @{ */ 1788 1789 #define MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1790 #define MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1791 #define MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1792 #define MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_14_DIV_UPD_STAT_DIV_STAT_MASK) 1793 /*! @} */ 1794 1795 /*! 1796 * @} 1797 */ /* end of group MC_CGM_Register_Masks */ 1798 1799 /*! 1800 * @} 1801 */ /* end of group MC_CGM_Peripheral_Access_Layer */ 1802 1803 #endif /* #if !defined(S32Z2_MC_CGM_H_) */ 1804
