1 /* 2 * Copyright (c) 2016-2019 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __MUSCA_S1_PLATFORM_REGS__ 18 #define __MUSCA_S1_PLATFORM_REGS__ 19 20 #include <stdint.h> 21 #include "platform_base_address.h" 22 23 /* sysinfo memory mapped register access structure */ 24 struct sysinfo_t { 25 volatile uint32_t sysversion; /* (R/ ) 0x000 System version */ 26 volatile uint32_t sysconfig; /* (R/ ) 0x004 System configuration */ 27 volatile uint32_t reserved0[1010]; /* 0x010-0xFCC Reserved */ 28 volatile uint32_t pidr4; /* (R/ ) 0xFD0 Peripheral ID 4 */ 29 volatile uint32_t reserved1[3]; /* 0xFD4-0xFDC Reserved */ 30 volatile uint32_t pidr0; /* (R/ ) 0xFE0 Peripheral ID 0 */ 31 volatile uint32_t pidr1; /* (R/ ) 0xFE4 Peripheral ID 1 */ 32 volatile uint32_t pidr2; /* (R/ ) 0xFE8 Peripheral ID 2 */ 33 volatile uint32_t pidr3; /* (R/ ) 0xFEC Peripheral ID 3 */ 34 volatile uint32_t cidr0; /* (R/ ) 0xFF0 Component ID 0 */ 35 volatile uint32_t cidr1; /* (R/ ) 0xFF4 Component ID 1 */ 36 volatile uint32_t cidr2; /* (R/ ) 0xFF8 Component ID 2 */ 37 volatile uint32_t cidr3; /* (R/ ) 0xFFC Component ID 3 */ 38 }; 39 40 /* Secure System Control (SYSCTRL) Alias */ 41 #define CMSDK_SYSCTRL_BASE_S MUSCA_S1_SYSTEM_CTRL_S_BASE 42 43 /* sysctrl memory mapped register access structure */ 44 struct sysctrl_t { 45 /* (R/ ) 0x000 Secure Debug Configuration Status Register*/ 46 volatile uint32_t secdbgstat; 47 /* ( /W) 0x004 Secure Debug Configuration Set Register */ 48 volatile uint32_t secdbgset; 49 /* ( /W) 0x008 Secure Debug Configuration Clear Register */ 50 volatile uint32_t secdbgclr; 51 /* (R/W) 0x00C System Control Security Control Register */ 52 volatile uint32_t scsecctrl; 53 /* (R/W) 0x010 Fast Clock Divider Configuration Register */ 54 volatile uint32_t fclk_div; 55 /* (R/W) 0x014 System Clock Divider Configuration Register */ 56 volatile uint32_t sysclk_div; 57 /* (R/W) 0x018 Clock Forces */ 58 volatile uint32_t clockforce; 59 /* 0x01C-0x0FC Reserved */ 60 volatile uint32_t reserved0[57]; 61 /* (R/W) 0x100 Reset syndrome */ 62 volatile uint32_t resetsyndrome; 63 /* (R/W) 0x104 Reset MASK */ 64 volatile uint32_t resetmask; 65 /* ( /W) 0x108 Software Reset */ 66 volatile uint32_t swreset; 67 /* (R/W) 0x10C General Purpose Retention Register */ 68 volatile uint32_t gretreg; 69 /* (R/W) 0x110 Initial Secure Reset Vector Register For CPU 0 */ 70 volatile uint32_t initsvtor0; 71 /* (R/W) 0x114 Initial Secure Reset Vector Register For CPU 1*/ 72 volatile uint32_t initsvtor1; 73 /* (R/W) 0x118 CPU Boot wait control after reset */ 74 volatile uint32_t cpuwait; 75 /* (R/W) 0x11C NMI Enable */ 76 volatile uint32_t nmi_enable; 77 /* (R/W) 0x120 CPU WIC Request and Acknowledgement */ 78 volatile uint32_t wicctrl; 79 /* (R/W) 0x124 External Wakeup Control */ 80 volatile uint32_t ewctrl; 81 /* 0x128-0x1FC Reserved */ 82 volatile uint32_t reserved2[54]; 83 /* (R/W) 0x200 Power Control Dependency Matrix 84 * PD_SYS Power Domain Sensitivity.*/ 85 volatile uint32_t pdcm_pd_sys_sense; 86 /* 0x204-0x208 Reserved */ 87 volatile uint32_t reserved3[2]; 88 /* (R/W) 0x20C Power Control Dependency Matrix 89 * PD_SRAM0 Power Domain Sensitivity.*/ 90 volatile uint32_t pdcm_pd_sram0_sense; 91 /* (R/W) 0x210 Power Control Dependency Matrix 92 * PD_SRAM1 Power Domain Sensitivity.*/ 93 volatile uint32_t pdcm_pd_sram1_sense; 94 /* 0x214(R/W) Power Control Dependency Matrix 95 * PD_SRAM2 Power Domain Sensitivity.*/ 96 volatile uint32_t pdcm_pd_sram2_sense; 97 /* (R/W) 0x218 Power Control Dependency Matrix 98 * PD_SRAM3 Power Domain Sensitivity.*/ 99 volatile uint32_t pdcm_pd_sram3_sense; 100 /* 0x21C-0xFCC Reserved */ 101 volatile uint32_t reserved4[877]; 102 /* (R/ ) 0xFD0 Peripheral ID 4 */ 103 volatile uint32_t pidr4; 104 /* 0xFD4-0xFDC Reserved */ 105 volatile uint32_t reserved5[3]; 106 /* (R/ ) 0xFE0 Peripheral ID 0 */ 107 volatile uint32_t pidr0; 108 /* (R/ ) 0xFE4 Peripheral ID 1 */ 109 volatile uint32_t pidr1; 110 /* (R/ ) 0xFE8 Peripheral ID 2 */ 111 volatile uint32_t pidr2; 112 /* (R/ ) 0xFEC Peripheral ID 3 */ 113 volatile uint32_t pidr3; 114 /* (R/ ) 0xFF0 Component ID 0 */ 115 volatile uint32_t cidr0; 116 /* (R/ ) 0xFF4 Component ID 1 */ 117 volatile uint32_t cidr1; 118 /* (R/ ) 0xFF8 Component ID 2 */ 119 volatile uint32_t cidr2; 120 /* (R/ ) 0xFFC Component ID 3 */ 121 volatile uint32_t cidr3; 122 }; 123 124 /* Secure Privilege Control */ 125 #define CMSDK_SPCTRL ((struct spctrl_def*)MUSCA_S1_SPCTRL_S_BASE) 126 127 /* SPCTRL memory mapped register access structure */ 128 struct spctrl_def { 129 /* (R/W) 0x000 Secure Configuration Control Register */ 130 volatile uint32_t spcsecctrl; 131 /* (R/W) 0x004 Bus Access wait control after reset.*/ 132 volatile uint32_t buswait; 133 /* 0x008-0x00C Reserved */ 134 volatile uint32_t reserved1[2]; 135 /* (R/W) 0x010Security Violation Response Configuration register.*/ 136 volatile uint32_t secrespcfg; 137 /* (R/W) 0x014 Non Secure Callable Configuration for IDAU. */ 138 volatile uint32_t nsccfg; 139 /* 0x018 Reserved */ 140 volatile uint32_t reserved2; 141 /* (R/W) 0x01C Secure MPC Interrupt Status. */ 142 volatile uint32_t secmpcintstat; 143 /* (R/W) 0x020 Secure PPC Interrupt Status. */ 144 volatile uint32_t secppcintstat; 145 /* (R/W) 0x024 Secure PPC Interrupt Clear. */ 146 volatile uint32_t secppcintclr; 147 /* (R/W) 0x28 Secure PPC Interrupt Enable. */ 148 volatile uint32_t secppcinten; 149 /* 0x02C-0x03C Reserved */ 150 volatile uint32_t reserved3[5]; 151 /* (R/W) 0x040 Bridge Buffer Error Interrupt Status. */ 152 volatile uint32_t brgintstat; 153 /* (R/W) 0x044 Bridge Buffer Error Interrupt Clear. */ 154 volatile uint32_t brgintclr; 155 /* (R/W) 0x048 Bridge Buffer Error Interrupt Enable. */ 156 volatile uint32_t brginten; 157 /* 0x04C-0x05C Reserved */ 158 volatile uint32_t reserved4[5]; 159 /* (R/W) 0x060 Expansion 0 Non_Secure Access 160 * AHB slave Peripheral Protection Control */ 161 volatile uint32_t ahbnsppcexp0; 162 /* 0x064-0x06C Reserved */ 163 volatile uint32_t reserved5[3]; 164 /* (R/W) 0x070 Non-Secure Access 165 * APB slave Peripheral Protection Control #0 */ 166 volatile uint32_t apbnsppc0; 167 /* (R/W) 0x074 Non-Secure Access 168 * APB slave Peripheral Protection Control #1 */ 169 volatile uint32_t apbnsppc1; 170 /* 0x078-0x07C Reserved */ 171 volatile uint32_t reserved6[2]; 172 /* (R/W) 0x080 Expansion 0 Non_Secure Access 173 * APB slave Peripheral Protection Control */ 174 volatile uint32_t apbnsppcexp0; 175 /* (R/W) 0x084 Expansion 1 Non_Secure Access 176 * APB slave Peripheral Protection Control */ 177 volatile uint32_t apbnsppcexp1; 178 /* 0x088-0x08C Reserved */ 179 volatile uint32_t reserved7[2]; 180 /* (R/W) 0x090 Secure Unprivileged Access 181 * AHB slave Peripheral Protection Control #0. */ 182 volatile uint32_t ahbspppc0; 183 /* 0x094-0x09C Reserved */ 184 volatile uint32_t reserved8[3]; 185 /* (R/W) 0x0A0 Expansion 0 Secure Unprivileged Access 186 * AHB slave Peripheral Protection Control. */ 187 volatile uint32_t ahbspppcexp0; 188 /* 0x0A4-0x0AC Reserved */ 189 volatile uint32_t reserved9[3]; 190 /* (R/W) 0x0B0 Secure Unprivileged Access 191 * APB slave Peripheral Protection Control #0 */ 192 volatile uint32_t apbspppc0; 193 /* (R/W) 0x0B4 Secure Unprivileged Access 194 * APB slave Peripheral Protection Control #1 */ 195 volatile uint32_t apbspppc1; 196 /* 0x0B8-0x0BC Reserved */ 197 volatile uint32_t reserved10[2]; 198 /* (R/W) 0x0C0 Expansion 0 Secure Unprivileged Access 199 * APB slave Peripheral Protection Control */ 200 volatile uint32_t apbspppcexp0; 201 /* (R/W) 0x0C4 Expansion 1 Secure Unprivileged Access 202 * APB slave Peripheral Protection Control */ 203 volatile uint32_t apbspppcexp1; 204 /* 0x0C8-0xFCC Reserved */ 205 volatile uint32_t reserved11[962]; 206 /* (R/W) 0xFD0 Peripheral ID 4 */ 207 volatile uint32_t pid4; 208 /* 0xFD4-0xFDC Reserved */ 209 volatile uint32_t reserved12[3]; 210 /* (R/W) 0xFE0 Peripheral ID 0 */ 211 volatile uint32_t pid0; 212 /* (R/W) 0xFE4 Peripheral ID 1 */ 213 volatile uint32_t pid1; 214 /* (R/W) 0xFE8 Peripheral ID 2 */ 215 volatile uint32_t pid2; 216 /* (R/W) 0xFEC Peripheral ID 3 */ 217 volatile uint32_t pid3; 218 /* (R/W) 0xFF0 Component ID 0 */ 219 volatile uint32_t cid0; 220 /* (R/W) 0xFF4 Component ID 1 */ 221 volatile uint32_t cid1; 222 /* (R/W) 0xFF8 Component ID 2 */ 223 volatile uint32_t cid2; 224 /* (R/W) 0xFFC Component ID 3 */ 225 volatile uint32_t cid3; 226 }; 227 228 /* Secure PPC interrupt position mask */ 229 #define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0) 230 #define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1) 231 #define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4) 232 #define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5) 233 #define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6) 234 #define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7) 235 #define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20) 236 #define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21) 237 #define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22) 238 #define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23) 239 240 /* Non-Secure Privilege Control */ 241 #define CMSDK_NSPCTRL ((struct nspctrl_def*)MUSCA_S1_NSPCTRL_NS_BASE) 242 243 /* NSPCTRL memory mapped register access structure */ 244 struct nspctrl_def { 245 /* 0x000-0x09C Reserved */ 246 volatile uint32_t reserved1[40]; 247 /* (R/W) 0x0A0 Expansion 0 Non-Secure Unprivileged Access 248 * AHB slave Peripheral Protection Control */ 249 volatile uint32_t ahbnspppcexp0; 250 /* 0x0A4-0x0AC Reserved */ 251 volatile uint32_t reserved2[3]; 252 /* (R/W) 0x0B0 Non-Secure Unprivileged Access 253 * APB slave Peripheral Protection Control #0 */ 254 volatile uint32_t apbnspppc0; 255 /* (R/W) 0x0B4 Non-Secure Unprivileged Access 256 * APB slave Peripheral Protection Control #1 */ 257 volatile uint32_t apbnspppc1; 258 /* 0x0B8-0x0BC Reserved */ 259 volatile uint32_t reserved3[2]; 260 /* (R/W) 0x0C0 Expansion 0 Non-Secure Unprivileged Access 261 * APB slave Peripheral Protection Control */ 262 volatile uint32_t apbnspppcexp0; 263 /* (R/W) 0x0C4 Expansion 1 Non-Secure Unprivileged Access 264 * APB slave Peripheral Protection Control */ 265 volatile uint32_t apbnspppcexp1; 266 /* 0x0C8-0xFCC Reserved */ 267 volatile uint32_t reserved4[962]; 268 /* (R/W) 0xFD0 Peripheral ID 4 */ 269 volatile uint32_t pidr4; 270 /* 0xFD4-0xFDC Reserved */ 271 volatile uint32_t reserved5[3]; 272 /* (R/W) 0xFE0 Peripheral ID 0 */ 273 volatile uint32_t pidr0; 274 /* (R/W) 0xFE4 Peripheral ID 1 */ 275 volatile uint32_t pidr1; 276 /* (R/W) 0xFE8 Peripheral ID 2 */ 277 volatile uint32_t pidr2; 278 /* (R/W) 0xFEC Peripheral ID 3 */ 279 volatile uint32_t pidr3; 280 /* (R/W) 0xFF0 Component ID 0 */ 281 volatile uint32_t cidr0; 282 /* (R/W) 0xFF4 Component ID 1 */ 283 volatile uint32_t cidr1; 284 /* (R/W) 0xFF8 Component ID 2 */ 285 volatile uint32_t cidr2; 286 /* (R/W) 0xFFC Component ID 3 */ 287 volatile uint32_t cidr3; 288 }; 289 290 /* ARM APB PPC0 peripherals definition */ 291 #define CMSDK_TIMER0_APB_PPC_POS 0U 292 #define CMSDK_TIMER1_APB_PPC_POS 1U 293 #define CMSDK_DTIMER_APB_PPC_POS 2U 294 #define CMSDK_MHU0_APB_PPC_POS 3U 295 #define CMSDK_MHU1_APB_PPC_POS 4U 296 /* The bits 31:5 are reserved */ 297 298 /* ARM APB PPC1 peripherals definition */ 299 #define CMSDK_S32K_TIMER_PPC_POS 0U 300 /* The bits 31:1 are reserved */ 301 302 /* ARM AHB PPC0 peripherals definition */ 303 /* The bits 31:0 are reserved */ 304 305 /* ARM AHB PPCEXP0 peripherals definition */ 306 #define MUSCA_S1_GPIO_AHB_PPC_POS 1U 307 /* The bits 31:1 are reserved */ 308 309 /* ARM AHB PPCEXP1 peripherals definition */ 310 /* The bits 31:0 are reserved */ 311 312 /* ARM AHB PPCEXP2 peripherals definition */ 313 /* The bits 31:0 are reserved */ 314 315 /* ARM AHB PPCEXP3 peripherals definition */ 316 /* The bits 31:0 are reserved */ 317 318 /* ARM APB PPCEXP0 peripherals definition */ 319 #define MUSCA_S1_QSPI_MPC_APB_PPC_POS 0U 320 #define MUSCA_S1_SRAM_MPC_APB_PPC_POS 1U 321 #define MUSCA_S1_MRAM_MPC_APB_PPC_POS 2U 322 323 /* ARM APB PPCEXP1 peripherals definition */ 324 #define MUSCA_S1_UART0_APB_PPC_POS 0U 325 #define MUSCA_S1_UART1_APB_PPC_POS 1U 326 #define MUSCA_S1_SPI_APB_PPC_POS 2U 327 #define MUSCA_S1_I2C0_APB_PPC_POS 3U 328 #define MUSCA_S1_I2C1_APB_PPC_POS 4U 329 #define MUSCA_S1_I2S_APB_PPC_POS 5U 330 #define MUSCA_S1_PWM0_APB_PPC_POS 6U 331 #define MUSCA_S1_RTC_APB_PPC_POS 7U 332 #define MUSCA_S1_PVT_APB_PPC_POS 8U 333 #define MUSCA_S1_QSPI_APB_PPC_POS 9U 334 #define MUSCA_S1_GPTIMER0_APB_PPC_POS 10U 335 #define MUSCA_S1_SCC_APB_PPC_POS 11U 336 #define MUSCA_S1_GPTIMER1_APB_PPC_POS 12U 337 #define MUSCA_S1_PWM1_APB_PPC_POS 13U 338 #define MUSCA_S1_PWM2_APB_PPC_POS 14U 339 340 #endif /* __MUSCA_S1_PLATFORM_REGS__ */ 341
