1 /*
2  * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef __MUSCA_B1_PLATFORM_REGS_H__
18 #define __MUSCA_B1_PLATFORM_REGS_H__
19 
20 #include <stdint.h>
21 #include "platform_base_address.h"
22 
23 /* System info memory mapped register access structure */
24 struct sysinfo_t {
25     volatile uint32_t sysversion;       /* (R/ ) System version */
26     volatile uint32_t sysconfig;        /* (R/ ) System configuration */
27     volatile uint32_t reserved0[1008];
28     volatile uint32_t pidr4;            /* (R/ ) Peripheral ID 4 */
29     volatile uint32_t reserved1[3];
30     volatile uint32_t pidr0;            /* (R/ ) Peripheral ID 0 */
31     volatile uint32_t pidr1;            /* (R/ ) Peripheral ID 1 */
32     volatile uint32_t pidr2;            /* (R/ ) Peripheral ID 2 */
33     volatile uint32_t pidr3;            /* (R/ ) Peripheral ID 3 */
34     volatile uint32_t cidr0;            /* (R/ ) Component ID 0 */
35     volatile uint32_t cidr1;            /* (R/ ) Component ID 1 */
36     volatile uint32_t cidr2;            /* (R/ ) Component ID 2 */
37     volatile uint32_t cidr3;            /* (R/ ) Component ID 3 */
38 };
39 
40 /* Secure System Control (SYSCTRL) alias */
41 #define CMSDK_SYSCTRL_BASE_S  MUSCA_B1_SYSTEM_CTRL_S_BASE
42 
43 /* System control memory mapped register access structure */
44 struct sysctrl_t {
45     volatile uint32_t secdbgstat;             /* (R/ ) Secure Debug Configuration
46                                                *       Status Register*/
47     volatile uint32_t secdbgset;              /* ( /W) Secure Debug Configuration
48                                                *       Set Register */
49     volatile uint32_t secdbgclr;              /* ( /W) Secure Debug Configuration
50                                                *       Clear Register */
51     volatile uint32_t scsecctrl;              /* (R/W) System Control Security
52                                                *       Control Register */
53     volatile uint32_t fclk_div;               /* (R/W) Fast Clock Divider
54                                                *       Configuration Register */
55     volatile uint32_t sysclk_div;             /* (R/W) System Clock Divider
56                                                *       Configuration Register */
57     volatile uint32_t clockforce;             /* (R/W) Clock Forces */
58     volatile uint32_t reserved1[57];
59     volatile uint32_t resetsyndrome;          /* (R/W) Reset syndrome */
60     volatile uint32_t resetmask;              /* (R/W) Reset MASK */
61     volatile uint32_t swreset;                /* ( /W) Software Reset */
62     volatile uint32_t gretreg;                /* (R/W) General Purpose Retention
63                                                *       Register */
64     volatile uint32_t initsvtor0;             /* (R/W) Initial Secure Reset Vector
65                                                *       Register For CPU 0 */
66     volatile uint32_t initsvtor1;             /* (R/W) Initial Secure Reset
67                                                *       Vector Register For CPU 1*/
68     volatile uint32_t cpuwait;                /* (R/W) CPU Boot wait control
69                                                *       after reset */
70     volatile uint32_t nmi_enable;             /* (R/W) NMI Enable Register.*/
71     volatile uint32_t wicctrl;                /* (R/W) CPU WIC Request and
72                                                *       Acknowledgement */
73     volatile uint32_t ewctrl;                 /* (R/W) External Wakeup Control */
74     volatile uint32_t reserved2[54];
75     volatile uint32_t pdcm_pd_sys_sense;      /* (R/W) Power Control Dependency
76                                                *       Matrix PD_SYS
77                                                *       Power Domain Sensitivity.*/
78     volatile uint32_t reserved3[2];
79     volatile uint32_t pdcm_pd_sram0_sense;    /* (R/W) Power Control Dependency
80                                                *       Matrix PD_SRAM0 Power
81                                                *       Domain Sensitivity.*/
82     volatile uint32_t pdcm_pd_sram1_sense;    /* (R/W) Power Control Dependency
83                                                *       Matrix PD_SRAM1 Power
84                                                *       Domain Sensitivity.*/
85     volatile uint32_t pdcm_pd_sram2_sense;    /* (R/W) Power Control Dependency
86                                                *       Matrix PD_SRAM2 Power
87                                                *       Domain Sensitivity.*/
88     volatile uint32_t pdcm_pd_sram3_sense;    /* (R/W) Power Control Dependency
89                                                *       Matrix PD_SRAM3 Power
90                                                *       Domain Sensitivity.*/
91     volatile uint32_t reserved4[877];
92     volatile uint32_t pidr4;                  /* (R/ ) Peripheral ID 4 */
93     volatile uint32_t reserved5[3];
94     volatile uint32_t pidr0;                  /* (R/ ) Peripheral ID 0 */
95     volatile uint32_t pidr1;                  /* (R/ ) Peripheral ID 1 */
96     volatile uint32_t pidr2;                  /* (R/ ) Peripheral ID 2 */
97     volatile uint32_t pidr3;                  /* (R/ ) Peripheral ID 3 */
98     volatile uint32_t cidr0;                  /* (R/ ) Component ID 0 */
99     volatile uint32_t cidr1;                  /* (R/ ) Component ID 1 */
100     volatile uint32_t cidr2;                  /* (R/ ) Component ID 2 */
101     volatile uint32_t cidr3;                  /* (R/ ) Component ID 3 */
102 };
103 
104 /* Secure Privilege Control */
105 #define CMSDK_SPCTRL  ((struct spctrl_def*)MUSCA_B1_SPCTRL_S_BASE)
106 
107 /* SPCTRL memory mapped register access structure */
108 struct spctrl_def {
109     volatile uint32_t spcsecctrl;             /* (R/W) Secure Configuration Control
110                                                        Register */
111     volatile uint32_t buswait;                /* (R/W) Bus Access wait control after reset.*/
112     volatile uint32_t reserved[2];
113     volatile uint32_t secrespcfg;             /* (R/W) Security Violation Response
114                                                *       Configuration register.*/
115     volatile uint32_t nsccfg;                 /* (R/W) Non Secure Callable Configuration
116                                                *       for IDAU. */
117     volatile uint32_t reserved2;
118     volatile uint32_t secmpcintstat;          /* (R/W) Secure MPC Interrupt Status. */
119     volatile uint32_t secppcintstat;          /* (R/W) Secure PPC Interrupt Status. */
120     volatile uint32_t secppcintclr;           /* (R/W) Secure PPC Interrupt Clear. */
121     volatile uint32_t secppcinten;            /* (R/W) Secure PPC Interrupt Enable. */
122     volatile uint32_t reserved3;
123     volatile uint32_t secmscintstat;          /* (R/W) Secure MSC Interrupt Status. */
124     volatile uint32_t secmscintclr;           /* (R/W) Secure MSC Interrupt Clear. */
125     volatile uint32_t secmscinten;            /* (R/W) Secure MSC Interrupt Enable. */
126     volatile uint32_t reserved4;
127     volatile uint32_t brgintstat;             /* (R/W) Bridge Buffer Error Interrupt Status. */
128     volatile uint32_t brgintclr;              /* (R/W) Bridge Buffer Error Interrupt Clear. */
129     volatile uint32_t brginten;               /* (R/W) Bridge Buffer Error Interrupt Enable. */
130     volatile uint32_t reserved5;
131     volatile uint32_t ahbnsppc0;              /* (R/W) Non-Secure Access AHB slave Peripheral
132                                                *       Protection Control #0 */
133     volatile uint32_t reserved6[3];
134     volatile uint32_t ahbnsppcexp0;           /* (R/W) Expansion 0 Non_Secure Access AHB slave
135                                                *       Peripheral Protection Control */
136     volatile uint32_t ahbnsppcexp1;           /* (R/W) Expansion 1 Non_Secure Access AHB slave
137                                                *       Peripheral Protection Control */
138     volatile uint32_t ahbnsppcexp2;           /* (R/W) Expansion 2 Non_Secure Access AHB slave
139                                                *       Peripheral Protection Control */
140     volatile uint32_t ahbnsppcexp3;           /* (R/W) Expansion 3 Non_Secure Access AHB slave
141                                                *       Peripheral Protection Control */
142     volatile uint32_t apbnsppc0;              /* (R/W) Non-Secure Access APB slave Peripheral
143                                                *       Protection Control #0 */
144     volatile uint32_t apbnsppc1;              /* (R/W) Non-Secure Access APB slave Peripheral
145                                                *       Protection Control #1 */
146     volatile uint32_t reserved7[2];
147     volatile uint32_t apbnsppcexp0;           /* (R/W) Expansion 0 Non_Secure Access APB slave
148                                                *       Peripheral Protection Control */
149     volatile uint32_t apbnsppcexp1;           /* (R/W) Expansion 1 Non_Secure Access APB slave
150                                                *       Peripheral Protection Control */
151     volatile uint32_t apbnsppcexp2;           /* (R/W) Expansion 2 Non_Secure Access APB slave
152                                                *       Peripheral Protection Control */
153     volatile uint32_t apbnsppcexp3;           /* (R/W) Expansion 3 Non_Secure Access APB slave
154                                                *       Peripheral Protection Control */
155     volatile uint32_t ahbspppc0;              /* (R/W) Secure Unprivileged Access AHB slave
156                                                *       Peripheral Protection Control #0. */
157     volatile uint32_t reserved8[3];
158     volatile uint32_t ahbspppcexp0;           /* (R/W) Expansion 0 Secure Unprivileged Access
159                                                *       AHB slave Peripheral Protection Control. */
160     volatile uint32_t ahbspppcexp1;           /* (R/W) Expansion 1 Secure Unprivileged Access
161                                                *       AHB slave Peripheral Protection Control. */
162     volatile uint32_t ahbspppcexp2;           /* (R/W) Expansion 2 Secure Unprivileged Access
163                                                *       AHB slave Peripheral Protection Control. */
164     volatile uint32_t ahbspppcexp3;           /* (R/W) Expansion 3 Secure Unprivileged Access
165                                                *       AHB slave Peripheral Protection Control. */
166     volatile uint32_t apbspppc0;              /* (R/W) Secure Unprivileged Access APB slave
167                                                *       Peripheral Protection Control #0 */
168     volatile uint32_t apbspppc1;              /* (R/W) Secure Unprivileged Access APB slave
169                                                *       Peripheral Protection Control #1 */
170     volatile uint32_t reserved9[2];
171     volatile uint32_t apbspppcexp0;           /* (R/W) Expansion 0 Secure Unprivileged Access
172                                                *       APB slave Peripheral Protection Control */
173     volatile uint32_t apbspppcexp1;           /* (R/W) Expansion 1 Secure Unprivileged Access
174                                                *       APB slave Peripheral Protection Control */
175     volatile uint32_t apbspppcexp2;           /* (R/W) Expansion 2 Secure Unprivileged Access
176                                                *       APB slave Peripheral Protection Control */
177     volatile uint32_t apbspppcexp3;           /* (R/W) Expansion 3 Secure Unprivileged Access
178                                                *       APB slave Peripheral Protection Control */
179     volatile uint32_t nsmscexp;               /* (R/W) Expansion MSC Non-Secure Configuration */
180     volatile uint32_t reserved10[959];
181     volatile uint32_t pid4;                   /* (R/W) Peripheral ID 4 */
182     volatile uint32_t pid5;                   /* (R/W) Peripheral ID 5 */
183     volatile uint32_t pid6;                   /* (R/W) Peripheral ID 6 */
184     volatile uint32_t pid7;                   /* (R/W) Peripheral ID 7 */
185     volatile uint32_t pid0;                   /* (R/W) Peripheral ID 0 */
186     volatile uint32_t pid1;                   /* (R/W) Peripheral ID 1 */
187     volatile uint32_t pid2;                   /* (R/W) Peripheral ID 2 */
188     volatile uint32_t pid3;                   /* (R/W) Peripheral ID 3 */
189     volatile uint32_t cid0;                   /* (R/W) Component ID 0 */
190     volatile uint32_t cid1;                   /* (R/W) Component ID 1 */
191     volatile uint32_t cid2;                   /* (R/W) Component ID 2 */
192     volatile uint32_t cid3;                   /* (R/W) Component ID 3 */
193 };
194 
195 /* PPC interrupt position mask */
196 #define CMSDK_APB_PPC0_INT_POS_MASK     (1UL << 0)
197 #define CMSDK_APB_PPC1_INT_POS_MASK     (1UL << 1)
198 #define CMSDK_APB_PPCEXP0_INT_POS_MASK  (1UL << 4)
199 #define CMSDK_APB_PPCEXP1_INT_POS_MASK  (1UL << 5)
200 #define CMSDK_APB_PPCEXP2_INT_POS_MASK  (1UL << 6)
201 #define CMSDK_APB_PPCEXP3_INT_POS_MASK  (1UL << 7)
202 #define CMSDK_AHB_PPCEXP0_INT_POS_MASK  (1UL << 20)
203 #define CMSDK_AHB_PPCEXP1_INT_POS_MASK  (1UL << 21)
204 #define CMSDK_AHB_PPCEXP2_INT_POS_MASK  (1UL << 22)
205 #define CMSDK_AHB_PPCEXP3_INT_POS_MASK  (1UL << 23)
206 
207 /* Non-Secure Privilege Control */
208 #define CMSDK_NSPCTRL  ((struct nspctrl_def*)MUSCA_B1_NSPCTRL_NS_BASE)
209 
210 /* NSPCTRL memory mapped register access structure */
211 struct nspctrl_def {
212     volatile uint32_t reserved[36];
213     volatile uint32_t ahbnspppc0;              /* (R/W) Non-Secure Unprivileged Access AHB slave
214                                                 *       Peripheral Protection Control #0 */
215     volatile uint32_t reserved3[3];
216     volatile uint32_t ahbnspppcexp0;           /* (R/W) Expansion 0 Non-Secure Unprivileged Access
217                                                 *       AHB slave Peripheral Protection Control */
218     volatile uint32_t ahbnspppcexp1;           /* (R/W) Expansion 1 Non-Secure Unprivileged Access
219                                                 *       AHB slave Peripheral Protection Control */
220     volatile uint32_t ahbnspppcexp2;           /* (R/W) Expansion 2 Non-Secure Unprivileged Access
221                                                 *       AHB slave Peripheral Protection Control */
222     volatile uint32_t ahbnspppcexp3;           /* (R/W) Expansion 3 Non-Secure Unprivileged Access
223                                                 *       AHB slave Peripheral Protection Control */
224     volatile uint32_t apbnspppc0;              /* (R/W) Non-Secure Unprivileged Access APB slave
225                                                 *       Peripheral Protection Control #0 */
226     volatile uint32_t apbnspppc1;              /* (R/W) Non-Secure Unprivileged Access APB slave
227                                                 *       Peripheral Protection Control #1 */
228     volatile uint32_t reserved4[2];
229     volatile uint32_t apbnspppcexp0;           /* (R/W) Expansion 0 Non-Secure Unprivileged Access
230                                                 *       APB slave Peripheral Protection Control */
231     volatile uint32_t apbnspppcexp1;           /* (R/W) Expansion 1 Non-Secure Unprivileged Access
232                                                 *       APB slave Peripheral Protection Control */
233     volatile uint32_t apbnspppcexp2;           /* (R/W) Expansion 2 Non-Secure Unprivileged Access
234                                                 *       APB slave Peripheral Protection Control */
235     volatile uint32_t apbnspppcexp3;           /* (R/W) Expansion 3 Non-Secure Unprivileged Access
236                                                 *       APB slave Peripheral Protection Control */
237     volatile uint32_t reserved5[960];
238     volatile uint32_t pidr4;                   /* (R/W) Peripheral ID 3 */
239     volatile uint32_t reserved7;
240     volatile uint32_t reserved8;
241     volatile uint32_t reserved9;
242     volatile uint32_t pidr0;                   /* (R/W) Peripheral ID 0 */
243     volatile uint32_t pidr1;                   /* (R/W) Peripheral ID 1 */
244     volatile uint32_t pidr2;                   /* (R/W) Peripheral ID 2 */
245     volatile uint32_t pidr3;                   /* (R/W) Peripheral ID 3 */
246     volatile uint32_t cidr0;                   /* (R/W) Component ID 0 */
247     volatile uint32_t cidr1;                   /* (R/W) Component ID 1 */
248     volatile uint32_t cidr2;                   /* (R/W) Component ID 2 */
249     volatile uint32_t cidr3;                   /* (R/W) Component ID 3 */
250 };
251 
252 /* SSE-200 specific PPC bit definitions */
253 
254 /* ARM APB PPC0 peripherals definition */
255 #define CMSDK_TIMER0_APB_PPC_POS             0U
256 #define CMSDK_TIMER1_APB_PPC_POS             1U
257 #define CMSDK_DTIMER_APB_PPC_POS             2U
258 #define CMSDK_MHU0_APB_PPC_POS               3U
259 #define CMSDK_MHU1_APB_PPC_POS               4U
260 /* The bits 31:5 are reserved */
261 /* End ARM APB PPC0 peripherals definition */
262 
263 /* ARM APB PPC1 peripherals definition */
264 #define CMSDK_S32K_TIMER_PPC_POS             0U
265 /* The bits 31:1 are reserved */
266 /* End ARM APB PPC1 peripherals definition */
267 
268 /* ARM AHB PPC0 peripherals definition */
269 /* The bits 31:0 are reserved */
270 /* End of ARM AHB PPC0 peripherals definition */
271 
272 /* Musca B1 specific PPC bit definitions */
273 
274 /* ARM AHB PPCEXP0 peripherals definition */
275 /* Bit 0 is reserved */
276 #define MUSCA_B1_GPIO_AHB_PPC_POS            1U
277 /* The bits 31:2 are reserved */
278 /* End of ARM AHB PPCEXP0 peripherals definition */
279 
280 /* ARM AHB PPCEXP1 peripherals definition */
281 /* The bits 31:0 are reserved */
282 /* End of ARM AHB PPCEXP1 peripherals definition */
283 
284 /* ARM AHB PPCEXP2 peripherals definition */
285 /* The bits 31:0 are reserved */
286 /* End of ARM AHB PPCEXP2 peripherals definition */
287 
288 /* ARM AHB PPCEXP3 peripherals definition */
289 /* The bits 31:0 are reserved */
290 /* End of ARM AHB PPCEXP3 peripherals definition */
291 
292 /* ARM APB PPCEXP0 peripherals definition */
293 #define MUSCA_B1_EFLASH0_CTRL_APB_PPC_POS    0U
294 #define MUSCA_B1_EFLASH1_CTRL_APB_PPC_POS    1U
295 #define MUSCA_B1_QSPI_APB_PPC_POS            2U
296 #define MUSCA_B1_EFLASH0_MPC_APB_PPC_POS     3U
297 #define MUSCA_B1_EFLASH1_MPC_APB_PPC_POS     4U
298 #define MUSCA_B1_SRAM_MPC_APB_PPC_POS        5U
299 #define MUSCA_B1_QSPI_MPC_APB_PPC_POS        6U
300 #define MUSCA_B1_CI_MHU0_S_APB_PPC_POS       7U
301 #define MUSCA_B1_CI_MHU0_R_APB_PPC_POS       8U
302 /* The bits 13:9 are reserved. */
303 #define MUSCA_B1_CI_MPC_APB_PPC_POS         14U
304 /* The bits 31:15 are reserved */
305 /* End of ARM APB PPCEXP0 peripherals definition */
306 
307 /* ARM APB PPCEXP1 peripherals definition */
308 /* Bit 0 is reserved. */
309 #define MUSCA_B1_PWM0_APB_PPC_POS            1U
310 #define MUSCA_B1_PWM1_APB_PPC_POS            2U
311 #define MUSCA_B1_PWM2_APB_PPC_POS            3U
312 #define MUSCA_B1_I2S_APB_PPC_POS             4U
313 #define MUSCA_B1_UART0_APB_PPC_POS           5U
314 #define MUSCA_B1_UART1_APB_PPC_POS           6U
315 /* Bit 7 is reserved. */
316 #define MUSCA_B1_I2C0_APB_PPC_POS            8U
317 #define MUSCA_B1_I2C1_APB_PPC_POS            9U
318 #define MUSCA_B1_SPI_APB_PPC_POS            10U
319 #define MUSCA_B1_SCC_APB_PPC_POS            11U
320 #define MUSCA_B1_GPTIMER_APB_PPC_POS        12U
321 #define MUSCA_B1_RTC_APB_PPC_POS            13U
322 #define MUSCA_B1_PVT_APB_PPC_POS            14U
323 #define MUSCA_B1_SDIO_APB_PPC_POS           15U
324 /* The bits 31:16 are reserved */
325 /* End of ARM APB PPCEXP1 peripherals definition */
326 
327 #endif /* __MUSCA_B1_PLATFORM_REGS_H__ */
328