1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1176AVM8A_cm4
4 **                          MIMXRT1176CVM8A_cm4
5 **                          MIMXRT1176DVMAA_cm4
6 **
7 **     Compilers:           Freescale C/C++ for Embedded ARM
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    IMXRT1170RM, Rev 1, 02/2021
14 **     Version:             rev. 1.0, 2020-12-29
15 **     Build:               b210607
16 **
17 **     Abstract:
18 **         CMSIS Peripheral Access Layer for MIMXRT1176_cm4
19 **
20 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016-2021 NXP
22 **     All rights reserved.
23 **
24 **     SPDX-License-Identifier: BSD-3-Clause
25 **
26 **     http:                 www.nxp.com
27 **     mail:                 support@nxp.com
28 **
29 **     Revisions:
30 **     - rev. 0.1 (2018-03-05)
31 **         Initial version.
32 **     - rev. 1.0 (2020-12-29)
33 **         Update header files to align with IMXRT1170RM Rev.0.
34 **
35 ** ###################################################################
36 */
37 
38 /*!
39  * @file MIMXRT1176_cm4.h
40  * @version 1.0
41  * @date 2020-12-29
42  * @brief CMSIS Peripheral Access Layer for MIMXRT1176_cm4
43  *
44  * CMSIS Peripheral Access Layer for MIMXRT1176_cm4
45  */
46 
47 #ifndef _MIMXRT1176_CM4_H_
48 #define _MIMXRT1176_CM4_H_                       /**< Symbol preventing repeated inclusion */
49 
50 /** Memory map major version (memory maps with equal major version number are
51  * compatible) */
52 #define MCU_MEM_MAP_VERSION 0x0100U
53 /** Memory map minor version */
54 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
55 
56 /* ----------------------------------------------------------------------------
57    --
58    ---------------------------------------------------------------------------- */
59 
60 /* Extra XRDC2 definition */
61 #define XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd))
62 #define XRDC2_GET_MRC(mem) ((mem) >> 5U)
63 #define XRDC2_GET_MRGD(mem) ((mem) & 31U)
64 #define XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac))
65 #define XRDC2_GET_PAC(periph) ((periph) >> 8U)
66 #define XRDC2_GET_PDAC(periph) ((periph) & 255U)
67 
68 
69 
70 /* ----------------------------------------------------------------------------
71    -- Interrupt vector numbers
72    ---------------------------------------------------------------------------- */
73 
74 /*!
75  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
76  * @{
77  */
78 
79 /** Interrupt Number Definitions */
80 #define NUMBER_OF_INT_VECTORS 234                /**< Number of interrupts in the Vector table */
81 
82 typedef enum IRQn {
83   /* Auxiliary constants */
84   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
85 
86   /* Core interrupts */
87   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
88   HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
89   MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
90   BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
91   UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
92   SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
93   DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
94   PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
95   SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
96 
97   /* Device specific interrupts */
98   DMA0_DMA16_IRQn              = 0,                /**< DMA channel 0/16 transfer complete */
99   DMA1_DMA17_IRQn              = 1,                /**< DMA channel 1/17 transfer complete */
100   DMA2_DMA18_IRQn              = 2,                /**< DMA channel 2/18 transfer complete */
101   DMA3_DMA19_IRQn              = 3,                /**< DMA channel 3/19 transfer complete */
102   DMA4_DMA20_IRQn              = 4,                /**< DMA channel 4/20 transfer complete */
103   DMA5_DMA21_IRQn              = 5,                /**< DMA channel 5/21 transfer complete */
104   DMA6_DMA22_IRQn              = 6,                /**< DMA channel 6/22 transfer complete */
105   DMA7_DMA23_IRQn              = 7,                /**< DMA channel 7/23 transfer complete */
106   DMA8_DMA24_IRQn              = 8,                /**< DMA channel 8/24 transfer complete */
107   DMA9_DMA25_IRQn              = 9,                /**< DMA channel 9/25 transfer complete */
108   DMA10_DMA26_IRQn             = 10,               /**< DMA channel 10/26 transfer complete */
109   DMA11_DMA27_IRQn             = 11,               /**< DMA channel 11/27 transfer complete */
110   DMA12_DMA28_IRQn             = 12,               /**< DMA channel 12/28 transfer complete */
111   DMA13_DMA29_IRQn             = 13,               /**< DMA channel 13/29 transfer complete */
112   DMA14_DMA30_IRQn             = 14,               /**< DMA channel 14/30 transfer complete */
113   DMA15_DMA31_IRQn             = 15,               /**< DMA channel 15/31 transfer complete */
114   DMA_ERROR_IRQn               = 16,               /**< DMA error interrupt channels 0-15 / 16-31 */
115   Reserved33_IRQn              = 17,               /**< Reserved interrupt */
116   Reserved34_IRQn              = 18,               /**< Reserved interrupt */
117   CORE_IRQn                    = 19,               /**< CorePlatform exception IRQ */
118   LPUART1_IRQn                 = 20,               /**< LPUART1 TX interrupt and RX interrupt */
119   LPUART2_IRQn                 = 21,               /**< LPUART2 TX interrupt and RX interrupt */
120   LPUART3_IRQn                 = 22,               /**< LPUART3 TX interrupt and RX interrupt */
121   LPUART4_IRQn                 = 23,               /**< LPUART4 TX interrupt and RX interrupt */
122   LPUART5_IRQn                 = 24,               /**< LPUART5 TX interrupt and RX interrupt */
123   LPUART6_IRQn                 = 25,               /**< LPUART6 TX interrupt and RX interrupt */
124   LPUART7_IRQn                 = 26,               /**< LPUART7 TX interrupt and RX interrupt */
125   LPUART8_IRQn                 = 27,               /**< LPUART8 TX interrupt and RX interrupt */
126   LPUART9_IRQn                 = 28,               /**< LPUART9 TX interrupt and RX interrupt */
127   LPUART10_IRQn                = 29,               /**< LPUART10 TX interrupt and RX interrupt */
128   LPUART11_IRQn                = 30,               /**< LPUART11 TX interrupt and RX interrupt */
129   LPUART12_IRQn                = 31,               /**< LPUART12 TX interrupt and RX interrupt */
130   LPI2C1_IRQn                  = 32,               /**< LPI2C1 interrupt */
131   LPI2C2_IRQn                  = 33,               /**< LPI2C2 interrupt */
132   LPI2C3_IRQn                  = 34,               /**< LPI2C3 interrupt */
133   LPI2C4_IRQn                  = 35,               /**< LPI2C4 interrupt */
134   LPI2C5_IRQn                  = 36,               /**< LPI2C5 interrupt */
135   LPI2C6_IRQn                  = 37,               /**< LPI2C6 interrupt */
136   LPSPI1_IRQn                  = 38,               /**< LPSPI1 interrupt request line to the core */
137   LPSPI2_IRQn                  = 39,               /**< LPSPI2 interrupt request line to the core */
138   LPSPI3_IRQn                  = 40,               /**< LPSPI3 interrupt request line to the core */
139   LPSPI4_IRQn                  = 41,               /**< LPSPI4 interrupt request line to the core */
140   LPSPI5_IRQn                  = 42,               /**< LPSPI5 interrupt request line to the core */
141   LPSPI6_IRQn                  = 43,               /**< LPSPI6 interrupt request line to the core */
142   CAN1_IRQn                    = 44,               /**< CAN1 interrupt */
143   CAN1_ERROR_IRQn              = 45,               /**< CAN1 error interrupt */
144   CAN2_IRQn                    = 46,               /**< CAN2 interrupt */
145   CAN2_ERROR_IRQn              = 47,               /**< CAN2 error interrupt */
146   CAN3_IRQn                    = 48,               /**< CAN3 interrupt */
147   CAN3_ERROR_IRQn              = 49,               /**< CAN3 erro interrupt */
148   Reserved66_IRQn              = 50,               /**< Reserved interrupt */
149   KPP_IRQn                     = 51,               /**< Keypad nterrupt */
150   Reserved68_IRQn              = 52,               /**< Reserved interrupt */
151   GPR_IRQ_IRQn                 = 53,               /**< GPR interrupt */
152   eLCDIF_IRQn                  = 54,               /**< eLCDIF interrupt */
153   LCDIFv2_IRQn                 = 55,               /**< LCDIFv2 interrupt */
154   CSI_IRQn                     = 56,               /**< CSI interrupt */
155   PXP_IRQn                     = 57,               /**< PXP interrupt */
156   MIPI_CSI_IRQn                = 58,               /**< MIPI_CSI interrupt */
157   MIPI_DSI_IRQn                = 59,               /**< MIPI_DSI interrupt */
158   GPU2D_IRQn                   = 60,               /**< GPU2D interrupt */
159   GPIO12_Combined_0_15_IRQn    = 61,               /**< Combined interrupt indication for GPIO12 signal 0 throughout 15 */
160   GPIO12_Combined_16_31_IRQn   = 62,               /**< Combined interrupt indication for GPIO13 signal 16 throughout 31 */
161   DAC_IRQn                     = 63,               /**< DAC interrupt */
162   KEY_MANAGER_IRQn             = 64,               /**< PUF interrupt */
163   WDOG2_IRQn                   = 65,               /**< WDOG2 interrupt */
164   SNVS_HP_NON_TZ_IRQn          = 66,               /**< SRTC Consolidated Interrupt. Non TZ */
165   SNVS_HP_TZ_IRQn              = 67,               /**< SRTC Security Interrupt. TZ */
166   SNVS_PULSE_EVENT_IRQn        = 68,               /**< ON-OFF button press shorter than 5 secs (pulse event) */
167   CAAM_IRQ0_IRQn               = 69,               /**< CAAM interrupt queue for JQ0 */
168   CAAM_IRQ1_IRQn               = 70,               /**< CAAM interrupt queue for JQ1 */
169   CAAM_IRQ2_IRQn               = 71,               /**< CAAM interrupt queue for JQ2 */
170   CAAM_IRQ3_IRQn               = 72,               /**< CAAM interrupt queue for JQ3 */
171   CAAM_RECORVE_ERRPR_IRQn      = 73,               /**< CAAM interrupt for recoverable error */
172   CAAM_RTIC_IRQn               = 74,               /**< CAAM interrupt for RTIC */
173   CDOG_IRQn                    = 75,               /**< CDOG interrupt */
174   SAI1_IRQn                    = 76,               /**< SAI1 interrupt */
175   SAI2_IRQn                    = 77,               /**< SAI1 interrupt */
176   SAI3_RX_IRQn                 = 78,               /**< SAI3 interrupt */
177   SAI3_TX_IRQn                 = 79,               /**< SAI3 interrupt */
178   SAI4_RX_IRQn                 = 80,               /**< SAI4 interrupt */
179   SAI4_TX_IRQn                 = 81,               /**< SAI4 interrupt */
180   SPDIF_IRQn                   = 82,               /**< SPDIF interrupt */
181   TMPSNS_INT_IRQn              = 83,               /**< TMPSNS interrupt */
182   TMPSNS_LOW_HIGH_IRQn         = 84,               /**< TMPSNS low high interrupt */
183   TMPSNS_PANIC_IRQn            = 85,               /**< TMPSNS panic interrupt */
184   LPSR_LP8_BROWNOUT_IRQn       = 86,               /**< LPSR 1p8 brownout interrupt */
185   LPSR_LP0_BROWNOUT_IRQn       = 87,               /**< LPSR 1p0 brownout interrupt */
186   ADC1_IRQn                    = 88,               /**< ADC1 interrupt */
187   ADC2_IRQn                    = 89,               /**< ADC2 interrupt */
188   USBPHY1_IRQn                 = 90,               /**< USBPHY1 interrupt */
189   USBPHY2_IRQn                 = 91,               /**< USBPHY2 interrupt */
190   RDC_IRQn                     = 92,               /**< RDC interrupt */
191   GPIO13_Combined_0_31_IRQn    = 93,               /**< Combined interrupt indication for GPIO13 signal 0 throughout 31 */
192   Reserved110_IRQn             = 94,               /**< Reserved interrupt */
193   DCIC1_IRQn                   = 95,               /**< DCIC1 interrupt */
194   DCIC2_IRQn                   = 96,               /**< DCIC2 interrupt */
195   ASRC_IRQn                    = 97,               /**< ASRC interrupt */
196   FLEXRAM_ECC_IRQn             = 98,               /**< FlexRAM ECC fatal interrupt */
197   GPIO7_8_9_10_11_IRQn         = 99,               /**< GPIO7, GPIO8, GPIO9, GPIO10, GPIO11 interrupt */
198   GPIO1_Combined_0_15_IRQn     = 100,              /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
199   GPIO1_Combined_16_31_IRQn    = 101,              /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
200   GPIO2_Combined_0_15_IRQn     = 102,              /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
201   GPIO2_Combined_16_31_IRQn    = 103,              /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
202   GPIO3_Combined_0_15_IRQn     = 104,              /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
203   GPIO3_Combined_16_31_IRQn    = 105,              /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
204   GPIO4_Combined_0_15_IRQn     = 106,              /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
205   GPIO4_Combined_16_31_IRQn    = 107,              /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
206   GPIO5_Combined_0_15_IRQn     = 108,              /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
207   GPIO5_Combined_16_31_IRQn    = 109,              /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
208   FLEXIO1_IRQn                 = 110,              /**< FLEXIO1 interrupt */
209   FLEXIO2_IRQn                 = 111,              /**< FLEXIO2 interrupt */
210   WDOG1_IRQn                   = 112,              /**< WDOG1 interrupt */
211   RTWDOG4_IRQn                 = 113,              /**< RTWDOG4 interrupt */
212   EWM_IRQn                     = 114,              /**< EWM interrupt */
213   OCOTP_READ_FUSE_ERROR_IRQn   = 115,              /**< OCOTP read fuse error interrupt */
214   OCOTP_READ_DONE_ERROR_IRQn   = 116,              /**< OCOTP read fuse done interrupt */
215   GPC_IRQn                     = 117,              /**< GPC interrupt */
216   MUB_IRQn                     = 118,              /**< MUB interrupt */
217   GPT1_IRQn                    = 119,              /**< GPT1 interrupt */
218   GPT2_IRQn                    = 120,              /**< GPT2 interrupt */
219   GPT3_IRQn                    = 121,              /**< GPT3 interrupt */
220   GPT4_IRQn                    = 122,              /**< GPT4 interrupt */
221   GPT5_IRQn                    = 123,              /**< GPT5 interrupt */
222   GPT6_IRQn                    = 124,              /**< GPT6 interrupt */
223   PWM1_0_IRQn                  = 125,              /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
224   PWM1_1_IRQn                  = 126,              /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
225   PWM1_2_IRQn                  = 127,              /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
226   PWM1_3_IRQn                  = 128,              /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
227   PWM1_FAULT_IRQn              = 129,              /**< PWM1 fault or reload error interrupt */
228   FLEXSPI1_IRQn                = 130,              /**< FlexSPI1 interrupt */
229   FLEXSPI2_IRQn                = 131,              /**< FlexSPI2 interrupt */
230   SEMC_IRQn                    = 132,              /**< SEMC interrupt */
231   USDHC1_IRQn                  = 133,              /**< USDHC1 interrupt */
232   USDHC2_IRQn                  = 134,              /**< USDHC2 interrupt */
233   USB_OTG2_IRQn                = 135,              /**< USBO2 USB OTG2 */
234   USB_OTG1_IRQn                = 136,              /**< USBO2 USB OTG1 */
235   ENET_IRQn                    = 137,              /**< ENET interrupt */
236   ENET_1588_Timer_IRQn         = 138,              /**< ENET_1588_Timer interrupt */
237   ENET_1G_MAC0_Tx_Rx_1_IRQn    = 139,              /**< ENET 1G MAC0 transmit/receive 1 */
238   ENET_1G_MAC0_Tx_Rx_2_IRQn    = 140,              /**< ENET 1G MAC0 transmit/receive 2 */
239   ENET_1G_IRQn                 = 141,              /**< ENET 1G interrupt */
240   ENET_1G_1588_Timer_IRQn      = 142,              /**< ENET_1G_1588_Timer interrupt */
241   XBAR1_IRQ_0_1_IRQn           = 143,              /**< XBAR1 interrupt */
242   XBAR1_IRQ_2_3_IRQn           = 144,              /**< XBAR1 interrupt */
243   ADC_ETC_IRQ0_IRQn            = 145,              /**< ADCETC IRQ0 interrupt */
244   ADC_ETC_IRQ1_IRQn            = 146,              /**< ADCETC IRQ1 interrupt */
245   ADC_ETC_IRQ2_IRQn            = 147,              /**< ADCETC IRQ2 interrupt */
246   ADC_ETC_IRQ3_IRQn            = 148,              /**< ADCETC IRQ3 interrupt */
247   ADC_ETC_ERROR_IRQ_IRQn       = 149,              /**< ADCETC Error IRQ interrupt */
248   Reserved166_IRQn             = 150,              /**< Reserved interrupt */
249   Reserved167_IRQn             = 151,              /**< Reserved interrupt */
250   Reserved168_IRQn             = 152,              /**< Reserved interrupt */
251   Reserved169_IRQn             = 153,              /**< Reserved interrupt */
252   Reserved170_IRQn             = 154,              /**< Reserved interrupt */
253   PIT1_IRQn                    = 155,              /**< PIT1 interrupt */
254   PIT2_IRQn                    = 156,              /**< PIT2 interrupt */
255   ACMP1_IRQn                   = 157,              /**< ACMP interrupt */
256   ACMP2_IRQn                   = 158,              /**< ACMP interrupt */
257   ACMP3_IRQn                   = 159,              /**< ACMP interrupt */
258   ACMP4_IRQn                   = 160,              /**< ACMP interrupt */
259   Reserved177_IRQn             = 161,              /**< Reserved interrupt */
260   Reserved178_IRQn             = 162,              /**< Reserved interrupt */
261   Reserved179_IRQn             = 163,              /**< Reserved interrupt */
262   Reserved180_IRQn             = 164,              /**< Reserved interrupt */
263   ENC1_IRQn                    = 165,              /**< ENC1 interrupt */
264   ENC2_IRQn                    = 166,              /**< ENC2 interrupt */
265   ENC3_IRQn                    = 167,              /**< ENC3 interrupt */
266   ENC4_IRQn                    = 168,              /**< ENC4 interrupt */
267   Reserved185_IRQn             = 169,              /**< Reserved interrupt */
268   Reserved186_IRQn             = 170,              /**< Reserved interrupt */
269   TMR1_IRQn                    = 171,              /**< TMR1 interrupt */
270   TMR2_IRQn                    = 172,              /**< TMR2 interrupt */
271   TMR3_IRQn                    = 173,              /**< TMR3 interrupt */
272   TMR4_IRQn                    = 174,              /**< TMR4 interrupt */
273   SEMA4_CP0_IRQn               = 175,              /**< SEMA4 CP0 interrupt */
274   SEMA4_CP1_IRQn               = 176,              /**< SEMA4 CP1 interrupt */
275   PWM2_0_IRQn                  = 177,              /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
276   PWM2_1_IRQn                  = 178,              /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
277   PWM2_2_IRQn                  = 179,              /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
278   PWM2_3_IRQn                  = 180,              /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
279   PWM2_FAULT_IRQn              = 181,              /**< PWM2 fault or reload error interrupt */
280   PWM3_0_IRQn                  = 182,              /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
281   PWM3_1_IRQn                  = 183,              /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
282   PWM3_2_IRQn                  = 184,              /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
283   PWM3_3_IRQn                  = 185,              /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
284   PWM3_FAULT_IRQn              = 186,              /**< PWM3 fault or reload error interrupt */
285   PWM4_0_IRQn                  = 187,              /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
286   PWM4_1_IRQn                  = 188,              /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
287   PWM4_2_IRQn                  = 189,              /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
288   PWM4_3_IRQn                  = 190,              /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
289   PWM4_FAULT_IRQn              = 191,              /**< PWM4 fault or reload error interrupt */
290   Reserved208_IRQn             = 192,              /**< Reserved interrupt */
291   Reserved209_IRQn             = 193,              /**< Reserved interrupt */
292   Reserved210_IRQn             = 194,              /**< Reserved interrupt */
293   Reserved211_IRQn             = 195,              /**< Reserved interrupt */
294   Reserved212_IRQn             = 196,              /**< Reserved interrupt */
295   Reserved213_IRQn             = 197,              /**< Reserved interrupt */
296   Reserved214_IRQn             = 198,              /**< Reserved interrupt */
297   Reserved215_IRQn             = 199,              /**< Reserved interrupt */
298   HWVAD_EVENT_IRQn             = 200,              /**< HWVAD event interrupt */
299   HWVAD_ERROR_IRQn             = 201,              /**< HWVAD error interrupt */
300   PDM_EVENT_IRQn               = 202,              /**< PDM event interrupt */
301   PDM_ERROR_IRQn               = 203,              /**< PDM error interrupt */
302   EMVSIM1_IRQn                 = 204,              /**< EMVSIM1 interrupt */
303   EMVSIM2_IRQn                 = 205,              /**< EMVSIM2 interrupt */
304   MECC1_INT_IRQn               = 206,              /**< MECC1 int */
305   MECC1_FATAL_INT_IRQn         = 207,              /**< MECC1 fatal int */
306   MECC2_INT_IRQn               = 208,              /**< MECC2 int */
307   MECC2_FATAL_INT_IRQn         = 209,              /**< MECC2 fatal int */
308   XECC_FLEXSPI1_INT_IRQn       = 210,              /**< XECC int */
309   XECC_FLEXSPI1_FATAL_INT_IRQn = 211,              /**< XECC fatal int */
310   XECC_FLEXSPI2_INT_IRQn       = 212,              /**< XECC int */
311   XECC_FLEXSPI2_FATAL_INT_IRQn = 213,              /**< XECC fatal int */
312   XECC_SEMC_INT_IRQn           = 214,              /**< XECC int */
313   XECC_SEMC_FATAL_INT_IRQn     = 215,              /**< XECC fatal int */
314   ENET_QOS_IRQn                = 216,              /**< ENET_QOS interrupt */
315   ENET_QOS_PMT_IRQn            = 217               /**< ENET_QOS_PMT interrupt */
316 } IRQn_Type;
317 
318 /*!
319  * @}
320  */ /* end of group Interrupt_vector_numbers */
321 
322 
323 /* ----------------------------------------------------------------------------
324    -- Cortex M4 Core Configuration
325    ---------------------------------------------------------------------------- */
326 
327 /*!
328  * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
329  * @{
330  */
331 
332 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
333 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
334 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
335 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
336 
337 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
338 #include "system_MIMXRT1176_cm4.h"     /* Device specific configuration file */
339 
340 /*!
341  * @}
342  */ /* end of group Cortex_Core_Configuration */
343 
344 
345 /* ----------------------------------------------------------------------------
346    -- Mapping Information
347    ---------------------------------------------------------------------------- */
348 
349 /*!
350  * @addtogroup Mapping_Information Mapping Information
351  * @{
352  */
353 
354 /** Mapping Information */
355 /*!
356  * @addtogroup rdc_mapping
357  * @{
358  */
359 
360 /*******************************************************************************
361  * Definitions
362  ******************************************************************************/
363 
364 /*!
365  * @brief Structure for the RDC mapping
366  *
367  * Defines the structure for the RDC resource collections.
368  */
369 /*
370  * Domain of these masters are not assigned by RDC
371  * CM7, CM7_DMA: Always use domain ID 0.
372  * CM4, CM4_DMA: Use domain ID 0 in single core case, 1 in dual core case.
373  * CAAM: Defined in CAAM mst_a[x]icid[10]
374  * LCDIFv2: Defined in LCDIF2 user bit[0]
375  * SSARC: Defined in SSARC user bit[0]
376  */
377 
378 typedef enum _rdc_master
379 {
380     kRDC_Master_ENET_1G_TX          = 1U,          /**< ENET_1G_TX */
381     kRDC_Master_ENET_1G_RX          = 2U,          /**< ENET_1G_RX */
382     kRDC_Master_ENET                = 3U,          /**< ENET */
383     kRDC_Master_ENET_QOS            = 4U,          /**< ENET_QOS */
384     kRDC_Master_USDHC1              = 5U,          /**< USDHC1 */
385     kRDC_Master_USDHC2              = 6U,          /**< USDHC2 */
386     kRDC_Master_USB                 = 7U,          /**< USB */
387     kRDC_Master_GPU                 = 8U,          /**< GPU */
388     kRDC_Master_PXP                 = 9U,          /**< PXP */
389     kRDC_Master_LCDIF               = 10U,         /**< LCDIF */
390     kRDC_Master_CSI                 = 11U,         /**< CSI */
391 } rdc_master_t;
392 
393 typedef enum _rdc_mem
394 {
395     kRDC_Mem_MRC0_0                 = 0U,
396     kRDC_Mem_MRC0_1                 = 1U,
397     kRDC_Mem_MRC0_2                 = 2U,
398     kRDC_Mem_MRC0_3                 = 3U,
399     kRDC_Mem_MRC0_4                 = 4U,
400     kRDC_Mem_MRC0_5                 = 5U,
401     kRDC_Mem_MRC0_6                 = 6U,
402     kRDC_Mem_MRC0_7                 = 7U,
403     kRDC_Mem_MRC1_0                 = 8U,
404     kRDC_Mem_MRC1_1                 = 9U,
405     kRDC_Mem_MRC1_2                 = 10U,
406     kRDC_Mem_MRC1_3                 = 11U,
407     kRDC_Mem_MRC1_4                 = 12U,
408     kRDC_Mem_MRC1_5                 = 13U,
409     kRDC_Mem_MRC1_6                 = 14U,
410     kRDC_Mem_MRC1_7                 = 15U,
411     kRDC_Mem_MRC2_0                 = 16U,
412     kRDC_Mem_MRC2_1                 = 17U,
413     kRDC_Mem_MRC2_2                 = 18U,
414     kRDC_Mem_MRC2_3                 = 19U,
415     kRDC_Mem_MRC2_4                 = 20U,
416     kRDC_Mem_MRC2_5                 = 21U,
417     kRDC_Mem_MRC2_6                 = 22U,
418     kRDC_Mem_MRC2_7                 = 23U,
419     kRDC_Mem_MRC3_0                 = 24U,
420     kRDC_Mem_MRC3_1                 = 25U,
421     kRDC_Mem_MRC3_2                 = 26U,
422     kRDC_Mem_MRC3_3                 = 27U,
423     kRDC_Mem_MRC3_4                 = 28U,
424     kRDC_Mem_MRC3_5                 = 29U,
425     kRDC_Mem_MRC3_6                 = 30U,
426     kRDC_Mem_MRC3_7                 = 31U,
427     kRDC_Mem_MRC4_0                 = 32U,
428     kRDC_Mem_MRC4_1                 = 33U,
429     kRDC_Mem_MRC4_2                 = 34U,
430     kRDC_Mem_MRC4_3                 = 35U,
431     kRDC_Mem_MRC4_4                 = 36U,
432     kRDC_Mem_MRC4_5                 = 37U,
433     kRDC_Mem_MRC4_6                 = 38U,
434     kRDC_Mem_MRC4_7                 = 39U,
435     kRDC_Mem_MRC5_0                 = 40U,
436     kRDC_Mem_MRC5_1                 = 41U,
437     kRDC_Mem_MRC5_2                 = 42U,
438     kRDC_Mem_MRC5_3                 = 43U,
439     kRDC_Mem_MRC6_0                 = 44U,
440     kRDC_Mem_MRC6_1                 = 45U,
441     kRDC_Mem_MRC6_2                 = 46U,
442     kRDC_Mem_MRC6_3                 = 47U,
443     kRDC_Mem_MRC7_0                 = 48U,
444     kRDC_Mem_MRC7_1                 = 49U,
445     kRDC_Mem_MRC7_2                 = 50U,
446     kRDC_Mem_MRC7_3                 = 51U,
447     kRDC_Mem_MRC7_4                 = 52U,
448     kRDC_Mem_MRC7_5                 = 53U,
449     kRDC_Mem_MRC7_6                 = 54U,
450     kRDC_Mem_MRC7_7                 = 55U,
451     kRDC_Mem_MRC8_0                 = 56U,
452     kRDC_Mem_MRC8_1                 = 57U,
453     kRDC_Mem_MRC8_2                 = 58U,
454 } rdc_mem_t;
455 
456 typedef enum _rdc_periph
457 {
458     kRDC_Periph_MTR                 = 0U,          /**< MTR */
459     kRDC_Periph_MECC1               = 1U,          /**< MECC1 */
460     kRDC_Periph_MECC2               = 2U,          /**< MECC2 */
461     kRDC_Periph_FLEXSPI1            = 3U,          /**< FlexSPI1 */
462     kRDC_Periph_FLEXSPI2            = 4U,          /**< FlexSPI2 */
463     kRDC_Periph_SEMC                = 5U,          /**< SEMC */
464     kRDC_Periph_CM7_IMXRT           = 6U,          /**< CM7_IMXRT */
465     kRDC_Periph_EWM                 = 7U,          /**< EWM */
466     kRDC_Periph_WDOG1               = 8U,          /**< WDOG1 */
467     kRDC_Periph_WDOG2               = 9U,          /**< WDOG2 */
468     kRDC_Periph_WDOG3               = 10U,         /**< WDOG3 */
469     kRDC_Periph_AOI_XBAR            = 11U,         /**< AOI_XBAR */
470     kRDC_Periph_ADC_ETC             = 12U,         /**< ADC_ETC */
471     kRDC_Periph_CAAM_1              = 13U,         /**< CAAM_1 */
472     kRDC_Periph_ADC1                = 14U,         /**< ADC1 */
473     kRDC_Periph_ADC2                = 15U,         /**< ADC2 */
474     kRDC_Periph_TSC_DIG             = 16U,         /**< TSC_DIG */
475     kRDC_Periph_DAC                 = 17U,         /**< DAC */
476     kRDC_Periph_IEE                 = 18U,         /**< IEE */
477     kRDC_Periph_DMAMUX              = 19U,         /**< DMAMUX */
478     kRDC_Periph_EDMA                = 19U,         /**< EDMA */
479     kRDC_Periph_LPUART1             = 20U,         /**< LPUART1 */
480     kRDC_Periph_LPUART2             = 21U,         /**< LPUART2 */
481     kRDC_Periph_LPUART3             = 22U,         /**< LPUART3 */
482     kRDC_Periph_LPUART4             = 23U,         /**< LPUART4 */
483     kRDC_Periph_LPUART5             = 24U,         /**< LPUART5 */
484     kRDC_Periph_LPUART6             = 25U,         /**< LPUART6 */
485     kRDC_Periph_LPUART7             = 26U,         /**< LPUART7 */
486     kRDC_Periph_LPUART8             = 27U,         /**< LPUART8 */
487     kRDC_Periph_LPUART9             = 28U,         /**< LPUART9 */
488     kRDC_Periph_LPUART10            = 29U,         /**< LPUART10 */
489     kRDC_Periph_FLEXIO1             = 30U,         /**< FlexIO1 */
490     kRDC_Periph_FLEXIO2             = 31U,         /**< FlexIO2 */
491     kRDC_Periph_CAN1                = 32U,         /**< CAN1 */
492     kRDC_Periph_CAN2                = 33U,         /**< CAN2 */
493     kRDC_Periph_PIT1                = 34U,         /**< PIT1 */
494     kRDC_Periph_KPP                 = 35U,         /**< KPP */
495     kRDC_Periph_IOMUXC_GPR          = 36U,         /**< IOMUXC_GPR */
496     kRDC_Periph_IOMUXC              = 37U,         /**< IOMUXC */
497     kRDC_Periph_GPT1                = 38U,         /**< GPT1 */
498     kRDC_Periph_GPT2                = 39U,         /**< GPT2 */
499     kRDC_Periph_GPT3                = 40U,         /**< GPT3 */
500     kRDC_Periph_GPT4                = 41U,         /**< GPT4 */
501     kRDC_Periph_GPT5                = 42U,         /**< GPT5 */
502     kRDC_Periph_GPT6                = 43U,         /**< GPT6 */
503     kRDC_Periph_LPI2C1              = 44U,         /**< LPI2C1 */
504     kRDC_Periph_LPI2C2              = 45U,         /**< LPI2C2 */
505     kRDC_Periph_LPI2C3              = 46U,         /**< LPI2C3 */
506     kRDC_Periph_LPI2C4              = 47U,         /**< LPI2C4 */
507     kRDC_Periph_LPSPI1              = 48U,         /**< LPSPI1 */
508     kRDC_Periph_LPSPI2              = 49U,         /**< LPSPI2 */
509     kRDC_Periph_LPSPI3              = 50U,         /**< LPSPI3 */
510     kRDC_Periph_LPSPI4              = 51U,         /**< LPSPI4 */
511     kRDC_Periph_GPIO_1_6            = 52U,         /**< GPIO_1_6 */
512     kRDC_Periph_CCM_OBS             = 53U,         /**< CCM_OBS */
513     kRDC_Periph_SIM1                = 54U,         /**< SIM1 */
514     kRDC_Periph_SIM2                = 55U,         /**< SIM2 */
515     kRDC_Periph_QTIMER1             = 56U,         /**< QTimer1 */
516     kRDC_Periph_QTIMER2             = 57U,         /**< QTimer2 */
517     kRDC_Periph_QTIMER3             = 58U,         /**< QTimer3 */
518     kRDC_Periph_QTIMER4             = 59U,         /**< QTimer4 */
519     kRDC_Periph_ENC1                = 60U,         /**< ENC1 */
520     kRDC_Periph_ENC2                = 61U,         /**< ENC2 */
521     kRDC_Periph_ENC3                = 62U,         /**< ENC3 */
522     kRDC_Periph_ENC4                = 63U,         /**< ENC4 */
523     kRDC_Periph_FLEXPWM1            = 64U,         /**< FLEXPWM1 */
524     kRDC_Periph_FLEXPWM2            = 65U,         /**< FLEXPWM2 */
525     kRDC_Periph_FLEXPWM3            = 66U,         /**< FLEXPWM3 */
526     kRDC_Periph_FLEXPWM4            = 67U,         /**< FLEXPWM4 */
527     kRDC_Periph_CAAM_2              = 68U,         /**< CAAM_2 */
528     kRDC_Periph_CAAM_3              = 69U,         /**< CAAM_3 */
529     kRDC_Periph_ACMP1               = 70U,         /**< ACMP1 */
530     kRDC_Periph_ACMP2               = 71U,         /**< ACMP2 */
531     kRDC_Periph_ACMP3               = 72U,         /**< ACMP3 */
532     kRDC_Periph_ACMP4               = 73U,         /**< ACMP4 */
533     kRDC_Periph_CAAM                = 74U,         /**< CAAM */
534     kRDC_Periph_SPDIF               = 75U,         /**< SPDIF */
535     kRDC_Periph_SAI1                = 76U,         /**< SAI1 */
536     kRDC_Periph_SAI2                = 77U,         /**< SAI2 */
537     kRDC_Periph_SAI3                = 78U,         /**< SAI3 */
538     kRDC_Periph_ASRC                = 79U,         /**< ASRC */
539     kRDC_Periph_USDHC1              = 80U,         /**< USDHC1 */
540     kRDC_Periph_USDHC2              = 81U,         /**< USDHC2 */
541     kRDC_Periph_ENET_1G             = 82U,         /**< ENET_1G */
542     kRDC_Periph_ENET                = 83U,         /**< ENET */
543     kRDC_Periph_USB_PL301           = 84U,         /**< USB_PL301 */
544     kRDC_Periph_USBPHY2             = 85U,         /**< USBPHY2 */
545     kRDC_Periph_USB_OTG2            = 85U,         /**< USB_OTG2 */
546     kRDC_Periph_USBPHY1             = 86U,         /**< USBPHY1 */
547     kRDC_Periph_USB_OTG1            = 86U,         /**< USB_OTG1 */
548     kRDC_Periph_ENET_QOS            = 87U,         /**< ENET_QOS */
549     kRDC_Periph_CAAM_5              = 88U,         /**< CAAM_5 */
550     kRDC_Periph_CSI                 = 89U,         /**< CSI */
551     kRDC_Periph_LCDIF1              = 90U,         /**< LCDIF1 */
552     kRDC_Periph_LCDIF2              = 91U,         /**< LCDIF2 */
553     kRDC_Periph_MIPI_DSI            = 92U,         /**< MIPI_DSI */
554     kRDC_Periph_MIPI_CSI            = 93U,         /**< MIPI_CSI */
555     kRDC_Periph_PXP                 = 94U,         /**< PXP */
556     kRDC_Periph_VIDEO_MUX           = 95U,         /**< VIDEO_MUX */
557     kRDC_Periph_PGMC_SRC_GPC        = 96U,         /**< PGMC_SRC_GPC */
558     kRDC_Periph_IOMUXC_LPSR         = 97U,         /**< IOMUXC_LPSR */
559     kRDC_Periph_IOMUXC_LPSR_GPR     = 98U,         /**< IOMUXC_LPSR_GPR */
560     kRDC_Periph_WDOG4               = 99U,         /**< WDOG4 */
561     kRDC_Periph_DMAMUX_LPSR         = 100U,        /**< DMAMUX_LPSR */
562     kRDC_Periph_EDMA_LPSR           = 100U,        /**< EDMA_LPSR */
563     kRDC_Periph_Reserved            = 101U,        /**< Reserved */
564     kRDC_Periph_MIC                 = 102U,        /**< MIC */
565     kRDC_Periph_LPUART11            = 103U,        /**< LPUART11 */
566     kRDC_Periph_LPUART12            = 104U,        /**< LPUART12 */
567     kRDC_Periph_LPSPI5              = 105U,        /**< LPSPI5 */
568     kRDC_Periph_LPSPI6              = 106U,        /**< LPSPI6 */
569     kRDC_Periph_LPI2C5              = 107U,        /**< LPI2C5 */
570     kRDC_Periph_LPI2C6              = 108U,        /**< LPI2C6 */
571     kRDC_Periph_CAN3                = 109U,        /**< CAN3 */
572     kRDC_Periph_SAI4                = 110U,        /**< SAI4 */
573     kRDC_Periph_SEMA1               = 111U,        /**< SEMA1 */
574     kRDC_Periph_GPIO_7_12           = 112U,        /**< GPIO_7_12 */
575     kRDC_Periph_KEY_MANAGER         = 113U,        /**< KEY_MANAGER */
576     kRDC_Periph_ANATOP              = 114U,        /**< ANATOP */
577     kRDC_Periph_SNVS_HP_WRAPPER     = 115U,        /**< SNVS_HP_WRAPPER */
578     kRDC_Periph_IOMUXC_SNVS         = 116U,        /**< IOMUXC_SNVS */
579     kRDC_Periph_IOMUXC_SNVS_GPR     = 117U,        /**< IOMUXC_SNVS_GPR */
580     kRDC_Periph_SNVS_SRAM           = 118U,        /**< SNVS_SRAM */
581     kRDC_Periph_GPIO13              = 119U,        /**< GPIO13 */
582     kRDC_Periph_ROMCP               = 120U,        /**< ROMCP */
583     kRDC_Periph_DCDC                = 121U,        /**< DCDC */
584     kRDC_Periph_OCOTP_CTRL_WRAPPER  = 122U,        /**< OCOTP_CTRL_WRAPPER */
585     kRDC_Periph_PIT2                = 123U,        /**< PIT2 */
586     kRDC_Periph_SSARC               = 124U,        /**< SSARC */
587     kRDC_Periph_CCM                 = 125U,        /**< CCM */
588     kRDC_Periph_CAAM_6              = 126U,        /**< CAAM_6 */
589     kRDC_Periph_CAAM_7              = 127U,        /**< CAAM_7 */
590 } rdc_periph_t;
591 
592 /* @} */
593 
594 typedef enum _xbar_input_signal
595 {
596     kXBARA1_InputLogicLow           = 0|0x100U,    /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
597     kXBARA1_InputLogicHigh          = 1|0x100U,    /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
598     kXBARA1_InputRESERVED2          = 2|0x100U,    /**< XBARA1_IN2 input is reserved. */
599     kXBARA1_InputRESERVED3          = 3|0x100U,    /**< XBARA1_IN3 input is reserved. */
600     kXBARA1_InputIomuxXbarInout04   = 4|0x100U,    /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
601     kXBARA1_InputIomuxXbarInout05   = 5|0x100U,    /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
602     kXBARA1_InputIomuxXbarInout06   = 6|0x100U,    /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
603     kXBARA1_InputIomuxXbarInout07   = 7|0x100U,    /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
604     kXBARA1_InputIomuxXbarInout08   = 8|0x100U,    /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
605     kXBARA1_InputIomuxXbarInout09   = 9|0x100U,    /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
606     kXBARA1_InputIomuxXbarInout10   = 10|0x100U,   /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
607     kXBARA1_InputIomuxXbarInout11   = 11|0x100U,   /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
608     kXBARA1_InputIomuxXbarInout12   = 12|0x100U,   /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
609     kXBARA1_InputIomuxXbarInout13   = 13|0x100U,   /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
610     kXBARA1_InputIomuxXbarInout14   = 14|0x100U,   /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
611     kXBARA1_InputIomuxXbarInout15   = 15|0x100U,   /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
612     kXBARA1_InputIomuxXbarInout16   = 16|0x100U,   /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
613     kXBARA1_InputIomuxXbarInout17   = 17|0x100U,   /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
614     kXBARA1_InputIomuxXbarInout18   = 18|0x100U,   /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
615     kXBARA1_InputIomuxXbarInout19   = 19|0x100U,   /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
616     kXBARA1_InputIomuxXbarInout20   = 20|0x100U,   /**< IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input. */
617     kXBARA1_InputIomuxXbarInout21   = 21|0x100U,   /**< IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input. */
618     kXBARA1_InputIomuxXbarInout22   = 22|0x100U,   /**< IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input. */
619     kXBARA1_InputIomuxXbarInout23   = 23|0x100U,   /**< IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input. */
620     kXBARA1_InputIomuxXbarInout24   = 24|0x100U,   /**< IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input. */
621     kXBARA1_InputIomuxXbarInout25   = 25|0x100U,   /**< IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input. */
622     kXBARA1_InputIomuxXbarInout26   = 26|0x100U,   /**< IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input. */
623     kXBARA1_InputIomuxXbarInout27   = 27|0x100U,   /**< IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input. */
624     kXBARA1_InputIomuxXbarInout28   = 28|0x100U,   /**< IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input. */
625     kXBARA1_InputIomuxXbarInout29   = 29|0x100U,   /**< IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input. */
626     kXBARA1_InputIomuxXbarInout30   = 30|0x100U,   /**< IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input. */
627     kXBARA1_InputIomuxXbarInout31   = 31|0x100U,   /**< IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input. */
628     kXBARA1_InputIomuxXbarInout32   = 32|0x100U,   /**< IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input. */
629     kXBARA1_InputIomuxXbarInout33   = 33|0x100U,   /**< IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input. */
630     kXBARA1_InputIomuxXbarInout34   = 34|0x100U,   /**< IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input. */
631     kXBARA1_InputIomuxXbarInout35   = 35|0x100U,   /**< IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input. */
632     kXBARA1_InputIomuxXbarInout36   = 36|0x100U,   /**< IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input. */
633     kXBARA1_InputIomuxXbarInout37   = 37|0x100U,   /**< IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input. */
634     kXBARA1_InputIomuxXbarInout38   = 38|0x100U,   /**< IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input. */
635     kXBARA1_InputIomuxXbarInout39   = 39|0x100U,   /**< IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input. */
636     kXBARA1_InputIomuxXbarInout40   = 40|0x100U,   /**< IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input. */
637     kXBARA1_InputRESERVED41         = 41|0x100U,   /**< XBARA1_IN41 input is reserved. */
638     kXBARA1_InputAcmp1Out           = 42|0x100U,   /**< ACMP1_OUT output assigned to XBARA1_IN42 input. */
639     kXBARA1_InputAcmp2Out           = 43|0x100U,   /**< ACMP2_OUT output assigned to XBARA1_IN43 input. */
640     kXBARA1_InputAcmp3Out           = 44|0x100U,   /**< ACMP3_OUT output assigned to XBARA1_IN44 input. */
641     kXBARA1_InputAcmp4Out           = 45|0x100U,   /**< ACMP4_OUT output assigned to XBARA1_IN45 input. */
642     kXBARA1_InputRESERVED46         = 46|0x100U,   /**< XBARA1_IN46 input is reserved. */
643     kXBARA1_InputRESERVED47         = 47|0x100U,   /**< XBARA1_IN47 input is reserved. */
644     kXBARA1_InputRESERVED48         = 48|0x100U,   /**< XBARA1_IN48 input is reserved. */
645     kXBARA1_InputRESERVED49         = 49|0x100U,   /**< XBARA1_IN49 input is reserved. */
646     kXBARA1_InputQtimer1Timer0      = 50|0x100U,   /**< QTIMER1_TIMER0 output assigned to XBARA1_IN50 input. */
647     kXBARA1_InputQtimer1Timer1      = 51|0x100U,   /**< QTIMER1_TIMER1 output assigned to XBARA1_IN51 input. */
648     kXBARA1_InputQtimer1Timer2      = 52|0x100U,   /**< QTIMER1_TIMER2 output assigned to XBARA1_IN52 input. */
649     kXBARA1_InputQtimer1Timer3      = 53|0x100U,   /**< QTIMER1_TIMER3 output assigned to XBARA1_IN53 input. */
650     kXBARA1_InputQtimer2Timer0      = 54|0x100U,   /**< QTIMER2_TIMER0 output assigned to XBARA1_IN54 input. */
651     kXBARA1_InputQtimer2Timer1      = 55|0x100U,   /**< QTIMER2_TIMER1 output assigned to XBARA1_IN55 input. */
652     kXBARA1_InputQtimer2Timer2      = 56|0x100U,   /**< QTIMER2_TIMER2 output assigned to XBARA1_IN56 input. */
653     kXBARA1_InputQtimer2Timer3      = 57|0x100U,   /**< QTIMER2_TIMER3 output assigned to XBARA1_IN57 input. */
654     kXBARA1_InputQtimer3Timer0      = 58|0x100U,   /**< QTIMER3_TIMER0 output assigned to XBARA1_IN58 input. */
655     kXBARA1_InputQtimer3Timer1      = 59|0x100U,   /**< QTIMER3_TIMER1 output assigned to XBARA1_IN59 input. */
656     kXBARA1_InputQtimer3Timer2      = 60|0x100U,   /**< QTIMER3_TIMER2 output assigned to XBARA1_IN60 input. */
657     kXBARA1_InputQtimer3Timer3      = 61|0x100U,   /**< QTIMER3_TIMER3 output assigned to XBARA1_IN61 input. */
658     kXBARA1_InputQtimer4Timer0      = 62|0x100U,   /**< QTIMER4_TIMER0 output assigned to XBARA1_IN62 input. */
659     kXBARA1_InputQtimer4Timer1      = 63|0x100U,   /**< QTIMER4_TIMER1 output assigned to XBARA1_IN63 input. */
660     kXBARA1_InputQtimer4Timer2      = 64|0x100U,   /**< QTIMER4_TIMER2 output assigned to XBARA1_IN64 input. */
661     kXBARA1_InputQtimer4Timer3      = 65|0x100U,   /**< QTIMER4_TIMER3 output assigned to XBARA1_IN65 input. */
662     kXBARA1_InputRESERVED66         = 66|0x100U,   /**< XBARA1_IN66 input is reserved. */
663     kXBARA1_InputRESERVED67         = 67|0x100U,   /**< XBARA1_IN67 input is reserved. */
664     kXBARA1_InputRESERVED68         = 68|0x100U,   /**< XBARA1_IN68 input is reserved. */
665     kXBARA1_InputRESERVED69         = 69|0x100U,   /**< XBARA1_IN69 input is reserved. */
666     kXBARA1_InputRESERVED70         = 70|0x100U,   /**< XBARA1_IN70 input is reserved. */
667     kXBARA1_InputRESERVED71         = 71|0x100U,   /**< XBARA1_IN71 input is reserved. */
668     kXBARA1_InputRESERVED72         = 72|0x100U,   /**< XBARA1_IN72 input is reserved. */
669     kXBARA1_InputRESERVED73         = 73|0x100U,   /**< XBARA1_IN73 input is reserved. */
670     kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input. */
671     kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input. */
672     kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input. */
673     kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input. */
674     kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input. */
675     kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input. */
676     kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input. */
677     kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input. */
678     kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input. */
679     kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input. */
680     kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input. */
681     kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input. */
682     kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input. */
683     kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input. */
684     kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input. */
685     kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input. */
686     kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input. */
687     kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input. */
688     kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input. */
689     kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input. */
690     kXBARA1_InputRESERVED94         = 94|0x100U,   /**< XBARA1_IN94 input is reserved. */
691     kXBARA1_InputRESERVED95         = 95|0x100U,   /**< XBARA1_IN95 input is reserved. */
692     kXBARA1_InputRESERVED96         = 96|0x100U,   /**< XBARA1_IN96 input is reserved. */
693     kXBARA1_InputRESERVED97         = 97|0x100U,   /**< XBARA1_IN97 input is reserved. */
694     kXBARA1_InputRESERVED98         = 98|0x100U,   /**< XBARA1_IN98 input is reserved. */
695     kXBARA1_InputRESERVED99         = 99|0x100U,   /**< XBARA1_IN99 input is reserved. */
696     kXBARA1_InputRESERVED100        = 100|0x100U,  /**< XBARA1_IN100 input is reserved. */
697     kXBARA1_InputRESERVED101        = 101|0x100U,  /**< XBARA1_IN101 input is reserved. */
698     kXBARA1_InputPit1Trigger0       = 102|0x100U,  /**< PIT1_TRIGGER0 output assigned to XBARA1_IN102 input. */
699     kXBARA1_InputPit1Trigger1       = 103|0x100U,  /**< PIT1_TRIGGER1 output assigned to XBARA1_IN103 input. */
700     kXBARA1_InputPit1Trigger2       = 104|0x100U,  /**< PIT1_TRIGGER2 output assigned to XBARA1_IN104 input. */
701     kXBARA1_InputPit1Trigger3       = 105|0x100U,  /**< PIT1_TRIGGER3 output assigned to XBARA1_IN105 input. */
702     kXBARA1_InputDec1PosMatch       = 106|0x100U,  /**< DEC1_POS_MATCH output assigned to XBARA1_IN106 input. */
703     kXBARA1_InputDec2PosMatch       = 107|0x100U,  /**< DEC2_POS_MATCH output assigned to XBARA1_IN107 input. */
704     kXBARA1_InputDec3PosMatch       = 108|0x100U,  /**< DEC3_POS_MATCH output assigned to XBARA1_IN108 input. */
705     kXBARA1_InputDec4PosMatch       = 109|0x100U,  /**< DEC4_POS_MATCH output assigned to XBARA1_IN109 input. */
706     kXBARA1_InputRESERVED110        = 110|0x100U,  /**< XBARA1_IN110 input is reserved. */
707     kXBARA1_InputRESERVED111        = 111|0x100U,  /**< XBARA1_IN111 input is reserved. */
708     kXBARA1_InputDmaDone0           = 112|0x100U,  /**< DMA_DONE0 output assigned to XBARA1_IN112 input. */
709     kXBARA1_InputDmaDone1           = 113|0x100U,  /**< DMA_DONE1 output assigned to XBARA1_IN113 input. */
710     kXBARA1_InputDmaDone2           = 114|0x100U,  /**< DMA_DONE2 output assigned to XBARA1_IN114 input. */
711     kXBARA1_InputDmaDone3           = 115|0x100U,  /**< DMA_DONE3 output assigned to XBARA1_IN115 input. */
712     kXBARA1_InputDmaDone4           = 116|0x100U,  /**< DMA_DONE4 output assigned to XBARA1_IN116 input. */
713     kXBARA1_InputDmaDone5           = 117|0x100U,  /**< DMA_DONE5 output assigned to XBARA1_IN117 input. */
714     kXBARA1_InputDmaDone6           = 118|0x100U,  /**< DMA_DONE6 output assigned to XBARA1_IN118 input. */
715     kXBARA1_InputDmaDone7           = 119|0x100U,  /**< DMA_DONE7 output assigned to XBARA1_IN119 input. */
716     kXBARA1_InputDmaLpsrDone0       = 120|0x100U,  /**< DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input. */
717     kXBARA1_InputDmaLpsrDone1       = 121|0x100U,  /**< DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input. */
718     kXBARA1_InputDmaLpsrDone2       = 122|0x100U,  /**< DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input. */
719     kXBARA1_InputDmaLpsrDone3       = 123|0x100U,  /**< DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input. */
720     kXBARA1_InputDmaLpsrDone4       = 124|0x100U,  /**< DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input. */
721     kXBARA1_InputDmaLpsrDone5       = 125|0x100U,  /**< DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input. */
722     kXBARA1_InputDmaLpsrDone6       = 126|0x100U,  /**< DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input. */
723     kXBARA1_InputDmaLpsrDone7       = 127|0x100U,  /**< DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input. */
724     kXBARA1_InputAoi1Out0           = 128|0x100U,  /**< AOI1_OUT0 output assigned to XBARA1_IN128 input. */
725     kXBARA1_InputAoi1Out1           = 129|0x100U,  /**< AOI1_OUT1 output assigned to XBARA1_IN129 input. */
726     kXBARA1_InputAoi1Out2           = 130|0x100U,  /**< AOI1_OUT2 output assigned to XBARA1_IN130 input. */
727     kXBARA1_InputAoi1Out3           = 131|0x100U,  /**< AOI1_OUT3 output assigned to XBARA1_IN131 input. */
728     kXBARA1_InputAoi2Out0           = 132|0x100U,  /**< AOI2_OUT0 output assigned to XBARA1_IN132 input. */
729     kXBARA1_InputAoi2Out1           = 133|0x100U,  /**< AOI2_OUT1 output assigned to XBARA1_IN133 input. */
730     kXBARA1_InputAoi2Out2           = 134|0x100U,  /**< AOI2_OUT2 output assigned to XBARA1_IN134 input. */
731     kXBARA1_InputAoi2Out3           = 135|0x100U,  /**< AOI2_OUT3 output assigned to XBARA1_IN135 input. */
732     kXBARA1_InputAdcEtc0Coco0       = 136|0x100U,  /**< ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input. */
733     kXBARA1_InputAdcEtc0Coco1       = 137|0x100U,  /**< ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input. */
734     kXBARA1_InputAdcEtc0Coco2       = 138|0x100U,  /**< ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input. */
735     kXBARA1_InputAdcEtc0Coco3       = 139|0x100U,  /**< ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input. */
736     kXBARA1_InputAdcEtc1Coco0       = 140|0x100U,  /**< ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input. */
737     kXBARA1_InputAdcEtc1Coco1       = 141|0x100U,  /**< ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input. */
738     kXBARA1_InputAdcEtc1Coco2       = 142|0x100U,  /**< ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input. */
739     kXBARA1_InputAdcEtc1Coco3       = 143|0x100U,  /**< ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input. */
740     kXBARB2_InputLogicLow           = 0|0x200U,    /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
741     kXBARB2_InputLogicHigh          = 1|0x200U,    /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
742     kXBARB2_InputAcmp1Out           = 2|0x200U,    /**< ACMP1_OUT output assigned to XBARB2_IN2 input. */
743     kXBARB2_InputAcmp2Out           = 3|0x200U,    /**< ACMP2_OUT output assigned to XBARB2_IN3 input. */
744     kXBARB2_InputAcmp3Out           = 4|0x200U,    /**< ACMP3_OUT output assigned to XBARB2_IN4 input. */
745     kXBARB2_InputAcmp4Out           = 5|0x200U,    /**< ACMP4_OUT output assigned to XBARB2_IN5 input. */
746     kXBARB2_InputRESERVED6          = 6|0x200U,    /**< XBARB2_IN6 input is reserved. */
747     kXBARB2_InputRESERVED7          = 7|0x200U,    /**< XBARB2_IN7 input is reserved. */
748     kXBARB2_InputRESERVED8          = 8|0x200U,    /**< XBARB2_IN8 input is reserved. */
749     kXBARB2_InputRESERVED9          = 9|0x200U,    /**< XBARB2_IN9 input is reserved. */
750     kXBARB2_InputQtimer1Timer0      = 10|0x200U,   /**< QTIMER1_TIMER0 output assigned to XBARB2_IN10 input. */
751     kXBARB2_InputQtimer1Timer1      = 11|0x200U,   /**< QTIMER1_TIMER1 output assigned to XBARB2_IN11 input. */
752     kXBARB2_InputQtimer1Timer2      = 12|0x200U,   /**< QTIMER1_TIMER2 output assigned to XBARB2_IN12 input. */
753     kXBARB2_InputQtimer1Timer3      = 13|0x200U,   /**< QTIMER1_TIMER3 output assigned to XBARB2_IN13 input. */
754     kXBARB2_InputQtimer2Timer0      = 14|0x200U,   /**< QTIMER2_TIMER0 output assigned to XBARB2_IN14 input. */
755     kXBARB2_InputQtimer2Timer1      = 15|0x200U,   /**< QTIMER2_TIMER1 output assigned to XBARB2_IN15 input. */
756     kXBARB2_InputQtimer2Timer2      = 16|0x200U,   /**< QTIMER2_TIMER2 output assigned to XBARB2_IN16 input. */
757     kXBARB2_InputQtimer2Timer3      = 17|0x200U,   /**< QTIMER2_TIMER3 output assigned to XBARB2_IN17 input. */
758     kXBARB2_InputQtimer3Timer0      = 18|0x200U,   /**< QTIMER3_TIMER0 output assigned to XBARB2_IN18 input. */
759     kXBARB2_InputQtimer3Timer1      = 19|0x200U,   /**< QTIMER3_TIMER1 output assigned to XBARB2_IN19 input. */
760     kXBARB2_InputQtimer3Timer2      = 20|0x200U,   /**< QTIMER3_TIMER2 output assigned to XBARB2_IN20 input. */
761     kXBARB2_InputQtimer3Timer3      = 21|0x200U,   /**< QTIMER3_TIMER3 output assigned to XBARB2_IN21 input. */
762     kXBARB2_InputQtimer4Timer0      = 22|0x200U,   /**< QTIMER4_TIMER0 output assigned to XBARB2_IN22 input. */
763     kXBARB2_InputQtimer4Timer1      = 23|0x200U,   /**< QTIMER4_TIMER1 output assigned to XBARB2_IN23 input. */
764     kXBARB2_InputQtimer4Timer2      = 24|0x200U,   /**< QTIMER4_TIMER2 output assigned to XBARB2_IN24 input. */
765     kXBARB2_InputQtimer4Timer3      = 25|0x200U,   /**< QTIMER4_TIMER3 output assigned to XBARB2_IN25 input. */
766     kXBARB2_InputRESERVED26         = 26|0x200U,   /**< XBARB2_IN26 input is reserved. */
767     kXBARB2_InputRESERVED27         = 27|0x200U,   /**< XBARB2_IN27 input is reserved. */
768     kXBARB2_InputRESERVED28         = 28|0x200U,   /**< XBARB2_IN28 input is reserved. */
769     kXBARB2_InputRESERVED29         = 29|0x200U,   /**< XBARB2_IN29 input is reserved. */
770     kXBARB2_InputRESERVED30         = 30|0x200U,   /**< XBARB2_IN30 input is reserved. */
771     kXBARB2_InputRESERVED31         = 31|0x200U,   /**< XBARB2_IN31 input is reserved. */
772     kXBARB2_InputRESERVED32         = 32|0x200U,   /**< XBARB2_IN32 input is reserved. */
773     kXBARB2_InputRESERVED33         = 33|0x200U,   /**< XBARB2_IN33 input is reserved. */
774     kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
775     kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
776     kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input. */
777     kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input. */
778     kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input. */
779     kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input. */
780     kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input. */
781     kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input. */
782     kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input. */
783     kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input. */
784     kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input. */
785     kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input. */
786     kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input. */
787     kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input. */
788     kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input. */
789     kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input. */
790     kXBARB2_InputRESERVED50         = 50|0x200U,   /**< XBARB2_IN50 input is reserved. */
791     kXBARB2_InputRESERVED51         = 51|0x200U,   /**< XBARB2_IN51 input is reserved. */
792     kXBARB2_InputRESERVED52         = 52|0x200U,   /**< XBARB2_IN52 input is reserved. */
793     kXBARB2_InputRESERVED53         = 53|0x200U,   /**< XBARB2_IN53 input is reserved. */
794     kXBARB2_InputRESERVED54         = 54|0x200U,   /**< XBARB2_IN54 input is reserved. */
795     kXBARB2_InputRESERVED55         = 55|0x200U,   /**< XBARB2_IN55 input is reserved. */
796     kXBARB2_InputRESERVED56         = 56|0x200U,   /**< XBARB2_IN56 input is reserved. */
797     kXBARB2_InputRESERVED57         = 57|0x200U,   /**< XBARB2_IN57 input is reserved. */
798     kXBARB2_InputPit1Trigger0       = 58|0x200U,   /**< PIT1_TRIGGER0 output assigned to XBARB2_IN58 input. */
799     kXBARB2_InputPit1Trigger1       = 59|0x200U,   /**< PIT1_TRIGGER1 output assigned to XBARB2_IN59 input. */
800     kXBARB2_InputAdcEtc0Coco0       = 60|0x200U,   /**< ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input. */
801     kXBARB2_InputAdcEtc0Coco1       = 61|0x200U,   /**< ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input. */
802     kXBARB2_InputAdcEtc0Coco2       = 62|0x200U,   /**< ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input. */
803     kXBARB2_InputAdcEtc0Coco3       = 63|0x200U,   /**< ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input. */
804     kXBARB2_InputAdcEtc1Coco0       = 64|0x200U,   /**< ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input. */
805     kXBARB2_InputAdcEtc1Coco1       = 65|0x200U,   /**< ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input. */
806     kXBARB2_InputAdcEtc1Coco2       = 66|0x200U,   /**< ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input. */
807     kXBARB2_InputAdcEtc1Coco3       = 67|0x200U,   /**< ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input. */
808     kXBARB2_InputRESERVED68         = 68|0x200U,   /**< XBARB2_IN68 input is reserved. */
809     kXBARB2_InputRESERVED69         = 69|0x200U,   /**< XBARB2_IN69 input is reserved. */
810     kXBARB2_InputRESERVED70         = 70|0x200U,   /**< XBARB2_IN70 input is reserved. */
811     kXBARB2_InputRESERVED71         = 71|0x200U,   /**< XBARB2_IN71 input is reserved. */
812     kXBARB2_InputRESERVED72         = 72|0x200U,   /**< XBARB2_IN72 input is reserved. */
813     kXBARB2_InputRESERVED73         = 73|0x200U,   /**< XBARB2_IN73 input is reserved. */
814     kXBARB2_InputRESERVED74         = 74|0x200U,   /**< XBARB2_IN74 input is reserved. */
815     kXBARB2_InputRESERVED75         = 75|0x200U,   /**< XBARB2_IN75 input is reserved. */
816     kXBARB2_InputDec1PosMatch       = 76|0x200U,   /**< DEC1_POS_MATCH output assigned to XBARB2_IN76 input. */
817     kXBARB2_InputDec2PosMatch       = 77|0x200U,   /**< DEC2_POS_MATCH output assigned to XBARB2_IN77 input. */
818     kXBARB2_InputDec3PosMatch       = 78|0x200U,   /**< DEC3_POS_MATCH output assigned to XBARB2_IN78 input. */
819     kXBARB2_InputDec4PosMatch       = 79|0x200U,   /**< DEC4_POS_MATCH output assigned to XBARB2_IN79 input. */
820     kXBARB2_InputRESERVED80         = 80|0x200U,   /**< XBARB2_IN80 input is reserved. */
821     kXBARB2_InputRESERVED81         = 81|0x200U,   /**< XBARB2_IN81 input is reserved. */
822     kXBARB2_InputDmaDone0           = 82|0x200U,   /**< DMA_DONE0 output assigned to XBARB2_IN82 input. */
823     kXBARB2_InputDmaDone1           = 83|0x200U,   /**< DMA_DONE1 output assigned to XBARB2_IN83 input. */
824     kXBARB2_InputDmaDone2           = 84|0x200U,   /**< DMA_DONE2 output assigned to XBARB2_IN84 input. */
825     kXBARB2_InputDmaDone3           = 85|0x200U,   /**< DMA_DONE3 output assigned to XBARB2_IN85 input. */
826     kXBARB2_InputDmaDone4           = 86|0x200U,   /**< DMA_DONE4 output assigned to XBARB2_IN86 input. */
827     kXBARB2_InputDmaDone5           = 87|0x200U,   /**< DMA_DONE5 output assigned to XBARB2_IN87 input. */
828     kXBARB2_InputDmaDone6           = 88|0x200U,   /**< DMA_DONE6 output assigned to XBARB2_IN88 input. */
829     kXBARB2_InputDmaDone7           = 89|0x200U,   /**< DMA_DONE7 output assigned to XBARB2_IN89 input. */
830     kXBARB2_InputDmaLpsrDone0       = 90|0x200U,   /**< DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input. */
831     kXBARB2_InputDmaLpsrDone1       = 91|0x200U,   /**< DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input. */
832     kXBARB2_InputDmaLpsrDone2       = 92|0x200U,   /**< DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input. */
833     kXBARB2_InputDmaLpsrDone3       = 93|0x200U,   /**< DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input. */
834     kXBARB2_InputDmaLpsrDone4       = 94|0x200U,   /**< DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input. */
835     kXBARB2_InputDmaLpsrDone5       = 95|0x200U,   /**< DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input. */
836     kXBARB2_InputDmaLpsrDone6       = 96|0x200U,   /**< DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input. */
837     kXBARB2_InputDmaLpsrDone7       = 97|0x200U,   /**< DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input. */
838     kXBARB3_InputLogicLow           = 0|0x300U,    /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
839     kXBARB3_InputLogicHigh          = 1|0x300U,    /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
840     kXBARB3_InputAcmp1Out           = 2|0x300U,    /**< ACMP1_OUT output assigned to XBARB3_IN2 input. */
841     kXBARB3_InputAcmp2Out           = 3|0x300U,    /**< ACMP2_OUT output assigned to XBARB3_IN3 input. */
842     kXBARB3_InputAcmp3Out           = 4|0x300U,    /**< ACMP3_OUT output assigned to XBARB3_IN4 input. */
843     kXBARB3_InputAcmp4Out           = 5|0x300U,    /**< ACMP4_OUT output assigned to XBARB3_IN5 input. */
844     kXBARB3_InputRESERVED6          = 6|0x300U,    /**< XBARB3_IN6 input is reserved. */
845     kXBARB3_InputRESERVED7          = 7|0x300U,    /**< XBARB3_IN7 input is reserved. */
846     kXBARB3_InputRESERVED8          = 8|0x300U,    /**< XBARB3_IN8 input is reserved. */
847     kXBARB3_InputRESERVED9          = 9|0x300U,    /**< XBARB3_IN9 input is reserved. */
848     kXBARB3_InputQtimer1Timer0      = 10|0x300U,   /**< QTIMER1_TIMER0 output assigned to XBARB3_IN10 input. */
849     kXBARB3_InputQtimer1Timer1      = 11|0x300U,   /**< QTIMER1_TIMER1 output assigned to XBARB3_IN11 input. */
850     kXBARB3_InputQtimer1Timer2      = 12|0x300U,   /**< QTIMER1_TIMER2 output assigned to XBARB3_IN12 input. */
851     kXBARB3_InputQtimer1Timer3      = 13|0x300U,   /**< QTIMER1_TIMER3 output assigned to XBARB3_IN13 input. */
852     kXBARB3_InputQtimer2Timer0      = 14|0x300U,   /**< QTIMER2_TIMER0 output assigned to XBARB3_IN14 input. */
853     kXBARB3_InputQtimer2Timer1      = 15|0x300U,   /**< QTIMER2_TIMER1 output assigned to XBARB3_IN15 input. */
854     kXBARB3_InputQtimer2Timer2      = 16|0x300U,   /**< QTIMER2_TIMER2 output assigned to XBARB3_IN16 input. */
855     kXBARB3_InputQtimer2Timer3      = 17|0x300U,   /**< QTIMER2_TIMER3 output assigned to XBARB3_IN17 input. */
856     kXBARB3_InputQtimer3Timer0      = 18|0x300U,   /**< QTIMER3_TIMER0 output assigned to XBARB3_IN18 input. */
857     kXBARB3_InputQtimer3Timer1      = 19|0x300U,   /**< QTIMER3_TIMER1 output assigned to XBARB3_IN19 input. */
858     kXBARB3_InputQtimer3Timer2      = 20|0x300U,   /**< QTIMER3_TIMER2 output assigned to XBARB3_IN20 input. */
859     kXBARB3_InputQtimer3Timer3      = 21|0x300U,   /**< QTIMER3_TIMER3 output assigned to XBARB3_IN21 input. */
860     kXBARB3_InputQtimer4Timer0      = 22|0x300U,   /**< QTIMER4_TIMER0 output assigned to XBARB3_IN22 input. */
861     kXBARB3_InputQtimer4Timer1      = 23|0x300U,   /**< QTIMER4_TIMER1 output assigned to XBARB3_IN23 input. */
862     kXBARB3_InputQtimer4Timer2      = 24|0x300U,   /**< QTIMER4_TIMER2 output assigned to XBARB3_IN24 input. */
863     kXBARB3_InputQtimer4Timer3      = 25|0x300U,   /**< QTIMER4_TIMER3 output assigned to XBARB3_IN25 input. */
864     kXBARB3_InputRESERVED26         = 26|0x300U,   /**< XBARB3_IN26 input is reserved. */
865     kXBARB3_InputRESERVED27         = 27|0x300U,   /**< XBARB3_IN27 input is reserved. */
866     kXBARB3_InputRESERVED28         = 28|0x300U,   /**< XBARB3_IN28 input is reserved. */
867     kXBARB3_InputRESERVED29         = 29|0x300U,   /**< XBARB3_IN29 input is reserved. */
868     kXBARB3_InputRESERVED30         = 30|0x300U,   /**< XBARB3_IN30 input is reserved. */
869     kXBARB3_InputRESERVED31         = 31|0x300U,   /**< XBARB3_IN31 input is reserved. */
870     kXBARB3_InputRESERVED32         = 32|0x300U,   /**< XBARB3_IN32 input is reserved. */
871     kXBARB3_InputRESERVED33         = 33|0x300U,   /**< XBARB3_IN33 input is reserved. */
872     kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
873     kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
874     kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input. */
875     kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input. */
876     kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input. */
877     kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input. */
878     kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input. */
879     kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input. */
880     kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input. */
881     kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input. */
882     kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input. */
883     kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input. */
884     kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input. */
885     kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input. */
886     kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input. */
887     kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input. */
888     kXBARB3_InputRESERVED50         = 50|0x300U,   /**< XBARB3_IN50 input is reserved. */
889     kXBARB3_InputRESERVED51         = 51|0x300U,   /**< XBARB3_IN51 input is reserved. */
890     kXBARB3_InputRESERVED52         = 52|0x300U,   /**< XBARB3_IN52 input is reserved. */
891     kXBARB3_InputRESERVED53         = 53|0x300U,   /**< XBARB3_IN53 input is reserved. */
892     kXBARB3_InputRESERVED54         = 54|0x300U,   /**< XBARB3_IN54 input is reserved. */
893     kXBARB3_InputRESERVED55         = 55|0x300U,   /**< XBARB3_IN55 input is reserved. */
894     kXBARB3_InputRESERVED56         = 56|0x300U,   /**< XBARB3_IN56 input is reserved. */
895     kXBARB3_InputRESERVED57         = 57|0x300U,   /**< XBARB3_IN57 input is reserved. */
896     kXBARB3_InputPit1Trigger0       = 58|0x300U,   /**< PIT1_TRIGGER0 output assigned to XBARB3_IN58 input. */
897     kXBARB3_InputPit1Trigger1       = 59|0x300U,   /**< PIT1_TRIGGER1 output assigned to XBARB3_IN59 input. */
898     kXBARB3_InputAdcEtc0Coco0       = 60|0x300U,   /**< ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input. */
899     kXBARB3_InputAdcEtc0Coco1       = 61|0x300U,   /**< ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input. */
900     kXBARB3_InputAdcEtc0Coco2       = 62|0x300U,   /**< ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input. */
901     kXBARB3_InputAdcEtc0Coco3       = 63|0x300U,   /**< ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input. */
902     kXBARB3_InputAdcEtc1Coco0       = 64|0x300U,   /**< ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input. */
903     kXBARB3_InputAdcEtc1Coco1       = 65|0x300U,   /**< ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input. */
904     kXBARB3_InputAdcEtc1Coco2       = 66|0x300U,   /**< ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input. */
905     kXBARB3_InputAdcEtc1Coco3       = 67|0x300U,   /**< ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input. */
906     kXBARB3_InputRESERVED68         = 68|0x300U,   /**< XBARB3_IN68 input is reserved. */
907     kXBARB3_InputRESERVED69         = 69|0x300U,   /**< XBARB3_IN69 input is reserved. */
908     kXBARB3_InputRESERVED70         = 70|0x300U,   /**< XBARB3_IN70 input is reserved. */
909     kXBARB3_InputRESERVED71         = 71|0x300U,   /**< XBARB3_IN71 input is reserved. */
910     kXBARB3_InputRESERVED72         = 72|0x300U,   /**< XBARB3_IN72 input is reserved. */
911     kXBARB3_InputRESERVED73         = 73|0x300U,   /**< XBARB3_IN73 input is reserved. */
912     kXBARB3_InputRESERVED74         = 74|0x300U,   /**< XBARB3_IN74 input is reserved. */
913     kXBARB3_InputRESERVED75         = 75|0x300U,   /**< XBARB3_IN75 input is reserved. */
914     kXBARB3_InputDec1PosMatch       = 76|0x300U,   /**< DEC1_POS_MATCH output assigned to XBARB3_IN76 input. */
915     kXBARB3_InputDec2PosMatch       = 77|0x300U,   /**< DEC2_POS_MATCH output assigned to XBARB3_IN77 input. */
916     kXBARB3_InputDec3PosMatch       = 78|0x300U,   /**< DEC3_POS_MATCH output assigned to XBARB3_IN78 input. */
917     kXBARB3_InputDec4PosMatch       = 79|0x300U,   /**< DEC4_POS_MATCH output assigned to XBARB3_IN79 input. */
918     kXBARB3_InputRESERVED80         = 80|0x300U,   /**< XBARB3_IN80 input is reserved. */
919     kXBARB3_InputRESERVED81         = 81|0x300U,   /**< XBARB3_IN81 input is reserved. */
920     kXBARB3_InputDmaDone0           = 82|0x300U,   /**< DMA_DONE0 output assigned to XBARB3_IN82 input. */
921     kXBARB3_InputDmaDone1           = 83|0x300U,   /**< DMA_DONE1 output assigned to XBARB3_IN83 input. */
922     kXBARB3_InputDmaDone2           = 84|0x300U,   /**< DMA_DONE2 output assigned to XBARB3_IN84 input. */
923     kXBARB3_InputDmaDone3           = 85|0x300U,   /**< DMA_DONE3 output assigned to XBARB3_IN85 input. */
924     kXBARB3_InputDmaDone4           = 86|0x300U,   /**< DMA_DONE4 output assigned to XBARB3_IN86 input. */
925     kXBARB3_InputDmaDone5           = 87|0x300U,   /**< DMA_DONE5 output assigned to XBARB3_IN87 input. */
926     kXBARB3_InputDmaDone6           = 88|0x300U,   /**< DMA_DONE6 output assigned to XBARB3_IN88 input. */
927     kXBARB3_InputDmaDone7           = 89|0x300U,   /**< DMA_DONE7 output assigned to XBARB3_IN89 input. */
928     kXBARB3_InputDmaLpsrDone0       = 90|0x300U,   /**< DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input. */
929     kXBARB3_InputDmaLpsrDone1       = 91|0x300U,   /**< DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input. */
930     kXBARB3_InputDmaLpsrDone2       = 92|0x300U,   /**< DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input. */
931     kXBARB3_InputDmaLpsrDone3       = 93|0x300U,   /**< DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input. */
932     kXBARB3_InputDmaLpsrDone4       = 94|0x300U,   /**< DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input. */
933     kXBARB3_InputDmaLpsrDone5       = 95|0x300U,   /**< DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input. */
934     kXBARB3_InputDmaLpsrDone6       = 96|0x300U,   /**< DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input. */
935     kXBARB3_InputDmaLpsrDone7       = 97|0x300U,   /**< DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input. */
936 } xbar_input_signal_t;
937 
938 typedef enum _xbar_output_signal
939 {
940     kXBARA1_OutputDmaChMuxReq81     = 0|0x100U,    /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81 */
941     kXBARA1_OutputDmaChMuxReq82     = 1|0x100U,    /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82 */
942     kXBARA1_OutputDmaChMuxReq83     = 2|0x100U,    /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83 */
943     kXBARA1_OutputDmaChMuxReq84     = 3|0x100U,    /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84 */
944     kXBARA1_OutputIomuxXbarInout04  = 4|0x100U,    /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
945     kXBARA1_OutputIomuxXbarInout05  = 5|0x100U,    /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
946     kXBARA1_OutputIomuxXbarInout06  = 6|0x100U,    /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
947     kXBARA1_OutputIomuxXbarInout07  = 7|0x100U,    /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
948     kXBARA1_OutputIomuxXbarInout08  = 8|0x100U,    /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
949     kXBARA1_OutputIomuxXbarInout09  = 9|0x100U,    /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
950     kXBARA1_OutputIomuxXbarInout10  = 10|0x100U,   /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
951     kXBARA1_OutputIomuxXbarInout11  = 11|0x100U,   /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
952     kXBARA1_OutputIomuxXbarInout12  = 12|0x100U,   /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
953     kXBARA1_OutputIomuxXbarInout13  = 13|0x100U,   /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
954     kXBARA1_OutputIomuxXbarInout14  = 14|0x100U,   /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
955     kXBARA1_OutputIomuxXbarInout15  = 15|0x100U,   /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
956     kXBARA1_OutputIomuxXbarInout16  = 16|0x100U,   /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
957     kXBARA1_OutputIomuxXbarInout17  = 17|0x100U,   /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
958     kXBARA1_OutputIomuxXbarInout18  = 18|0x100U,   /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
959     kXBARA1_OutputIomuxXbarInout19  = 19|0x100U,   /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
960     kXBARA1_OutputIomuxXbarInout20  = 20|0x100U,   /**< XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20 */
961     kXBARA1_OutputIomuxXbarInout21  = 21|0x100U,   /**< XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21 */
962     kXBARA1_OutputIomuxXbarInout22  = 22|0x100U,   /**< XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22 */
963     kXBARA1_OutputIomuxXbarInout23  = 23|0x100U,   /**< XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23 */
964     kXBARA1_OutputIomuxXbarInout24  = 24|0x100U,   /**< XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24 */
965     kXBARA1_OutputIomuxXbarInout25  = 25|0x100U,   /**< XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25 */
966     kXBARA1_OutputIomuxXbarInout26  = 26|0x100U,   /**< XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26 */
967     kXBARA1_OutputIomuxXbarInout27  = 27|0x100U,   /**< XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27 */
968     kXBARA1_OutputIomuxXbarInout28  = 28|0x100U,   /**< XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28 */
969     kXBARA1_OutputIomuxXbarInout29  = 29|0x100U,   /**< XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29 */
970     kXBARA1_OutputIomuxXbarInout30  = 30|0x100U,   /**< XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30 */
971     kXBARA1_OutputIomuxXbarInout31  = 31|0x100U,   /**< XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31 */
972     kXBARA1_OutputIomuxXbarInout32  = 32|0x100U,   /**< XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32 */
973     kXBARA1_OutputIomuxXbarInout33  = 33|0x100U,   /**< XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33 */
974     kXBARA1_OutputIomuxXbarInout34  = 34|0x100U,   /**< XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34 */
975     kXBARA1_OutputIomuxXbarInout35  = 35|0x100U,   /**< XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35 */
976     kXBARA1_OutputIomuxXbarInout36  = 36|0x100U,   /**< XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36 */
977     kXBARA1_OutputIomuxXbarInout37  = 37|0x100U,   /**< XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37 */
978     kXBARA1_OutputIomuxXbarInout38  = 38|0x100U,   /**< XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38 */
979     kXBARA1_OutputIomuxXbarInout39  = 39|0x100U,   /**< XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39 */
980     kXBARA1_OutputIomuxXbarInout40  = 40|0x100U,   /**< XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40 */
981     kXBARA1_OutputAcmp1Sample       = 41|0x100U,   /**< XBARA1_OUT41 output assigned to ACMP1_SAMPLE */
982     kXBARA1_OutputAcmp2Sample       = 42|0x100U,   /**< XBARA1_OUT42 output assigned to ACMP2_SAMPLE */
983     kXBARA1_OutputAcmp3Sample       = 43|0x100U,   /**< XBARA1_OUT43 output assigned to ACMP3_SAMPLE */
984     kXBARA1_OutputAcmp4Sample       = 44|0x100U,   /**< XBARA1_OUT44 output assigned to ACMP4_SAMPLE */
985     kXBARA1_OutputRESERVED45        = 45|0x100U,   /**< XBARA1_OUT45 output is reserved. */
986     kXBARA1_OutputRESERVED46        = 46|0x100U,   /**< XBARA1_OUT46 output is reserved. */
987     kXBARA1_OutputRESERVED47        = 47|0x100U,   /**< XBARA1_OUT47 output is reserved. */
988     kXBARA1_OutputRESERVED48        = 48|0x100U,   /**< XBARA1_OUT48 output is reserved. */
989     kXBARA1_OutputFlexpwm1Pwm0Exta  = 49|0x100U,   /**< XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA */
990     kXBARA1_OutputFlexpwm1Pwm1Exta  = 50|0x100U,   /**< XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA */
991     kXBARA1_OutputFlexpwm1Pwm2Exta  = 51|0x100U,   /**< XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA */
992     kXBARA1_OutputFlexpwm1Pwm3Exta  = 52|0x100U,   /**< XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA */
993     kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC */
994     kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC */
995     kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC */
996     kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC */
997     kXBARA1_OutputFlexpwm1ExtClk    = 57|0x100U,   /**< XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK */
998     kXBARA1_OutputFlexpwm1Fault0    = 58|0x100U,   /**< XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0 */
999     kXBARA1_OutputFlexpwm1Fault1    = 59|0x100U,   /**< XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1 */
1000     kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U,   /**< XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2 */
1001     kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U,   /**< XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3 */
1002     kXBARA1_OutputFlexpwm1ExtForce  = 62|0x100U,   /**< XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */
1003     kXBARA1_OutputFlexpwm2Pwm0Exta  = 63|0x100U,   /**< XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA */
1004     kXBARA1_OutputFlexpwm2Pwm1Exta  = 64|0x100U,   /**< XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA */
1005     kXBARA1_OutputFlexpwm2Pwm2Exta  = 65|0x100U,   /**< XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA */
1006     kXBARA1_OutputFlexpwm2Pwm3Exta  = 66|0x100U,   /**< XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA */
1007     kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC */
1008     kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC */
1009     kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC */
1010     kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC */
1011     kXBARA1_OutputFlexpwm2ExtClk    = 71|0x100U,   /**< XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK */
1012     kXBARA1_OutputFlexpwm2Fault0    = 72|0x100U,   /**< XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0 */
1013     kXBARA1_OutputFlexpwm2Fault1    = 73|0x100U,   /**< XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1 */
1014     kXBARA1_OutputFlexpwm2ExtForce  = 74|0x100U,   /**< XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */
1015     kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U,   /**< XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA */
1016     kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U,   /**< XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA */
1017     kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U,   /**< XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA */
1018     kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U,   /**< XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA */
1019     kXBARA1_OutputFlexpwm34ExtClk   = 79|0x100U,   /**< XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK */
1020     kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC */
1021     kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC */
1022     kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC */
1023     kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC */
1024     kXBARA1_OutputFlexpwm3Fault0    = 84|0x100U,   /**< XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0 */
1025     kXBARA1_OutputFlexpwm3Fault1    = 85|0x100U,   /**< XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1 */
1026     kXBARA1_OutputFlexpwm3ExtForce  = 86|0x100U,   /**< XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */
1027     kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC */
1028     kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC */
1029     kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC */
1030     kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC */
1031     kXBARA1_OutputFlexpwm4Fault0    = 91|0x100U,   /**< XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0 */
1032     kXBARA1_OutputFlexpwm4Fault1    = 92|0x100U,   /**< XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1 */
1033     kXBARA1_OutputFlexpwm4ExtForce  = 93|0x100U,   /**< XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */
1034     kXBARA1_OutputRESERVED94        = 94|0x100U,   /**< XBARA1_OUT94 output is reserved. */
1035     kXBARA1_OutputRESERVED95        = 95|0x100U,   /**< XBARA1_OUT95 output is reserved. */
1036     kXBARA1_OutputRESERVED96        = 96|0x100U,   /**< XBARA1_OUT96 output is reserved. */
1037     kXBARA1_OutputRESERVED97        = 97|0x100U,   /**< XBARA1_OUT97 output is reserved. */
1038     kXBARA1_OutputRESERVED98        = 98|0x100U,   /**< XBARA1_OUT98 output is reserved. */
1039     kXBARA1_OutputRESERVED99        = 99|0x100U,   /**< XBARA1_OUT99 output is reserved. */
1040     kXBARA1_OutputRESERVED100       = 100|0x100U,  /**< XBARA1_OUT100 output is reserved. */
1041     kXBARA1_OutputRESERVED101       = 101|0x100U,  /**< XBARA1_OUT101 output is reserved. */
1042     kXBARA1_OutputRESERVED102       = 102|0x100U,  /**< XBARA1_OUT102 output is reserved. */
1043     kXBARA1_OutputRESERVED103       = 103|0x100U,  /**< XBARA1_OUT103 output is reserved. */
1044     kXBARA1_OutputRESERVED104       = 104|0x100U,  /**< XBARA1_OUT104 output is reserved. */
1045     kXBARA1_OutputRESERVED105       = 105|0x100U,  /**< XBARA1_OUT105 output is reserved. */
1046     kXBARA1_OutputRESERVED106       = 106|0x100U,  /**< XBARA1_OUT106 output is reserved. */
1047     kXBARA1_OutputRESERVED107       = 107|0x100U,  /**< XBARA1_OUT107 output is reserved. */
1048     kXBARA1_OutputDec1Phasea        = 108|0x100U,  /**< XBARA1_OUT108 output assigned to DEC1_PHASEA */
1049     kXBARA1_OutputDec1Phaseb        = 109|0x100U,  /**< XBARA1_OUT109 output assigned to DEC1_PHASEB */
1050     kXBARA1_OutputDec1Index         = 110|0x100U,  /**< XBARA1_OUT110 output assigned to DEC1_INDEX */
1051     kXBARA1_OutputDec1Home          = 111|0x100U,  /**< XBARA1_OUT111 output assigned to DEC1_HOME */
1052     kXBARA1_OutputDec1Trigger       = 112|0x100U,  /**< XBARA1_OUT112 output assigned to DEC1_TRIGGER */
1053     kXBARA1_OutputDec2Phasea        = 113|0x100U,  /**< XBARA1_OUT113 output assigned to DEC2_PHASEA */
1054     kXBARA1_OutputDec2Phaseb        = 114|0x100U,  /**< XBARA1_OUT114 output assigned to DEC2_PHASEB */
1055     kXBARA1_OutputDec2Index         = 115|0x100U,  /**< XBARA1_OUT115 output assigned to DEC2_INDEX */
1056     kXBARA1_OutputDec2Home          = 116|0x100U,  /**< XBARA1_OUT116 output assigned to DEC2_HOME */
1057     kXBARA1_OutputDec2Trigger       = 117|0x100U,  /**< XBARA1_OUT117 output assigned to DEC2_TRIGGER */
1058     kXBARA1_OutputDec3Phasea        = 118|0x100U,  /**< XBARA1_OUT118 output assigned to DEC3_PHASEA */
1059     kXBARA1_OutputDec3Phaseb        = 119|0x100U,  /**< XBARA1_OUT119 output assigned to DEC3_PHASEB */
1060     kXBARA1_OutputDec3Index         = 120|0x100U,  /**< XBARA1_OUT120 output assigned to DEC3_INDEX */
1061     kXBARA1_OutputDec3Home          = 121|0x100U,  /**< XBARA1_OUT121 output assigned to DEC3_HOME */
1062     kXBARA1_OutputDec3Trigger       = 122|0x100U,  /**< XBARA1_OUT122 output assigned to DEC3_TRIGGER */
1063     kXBARA1_OutputDec4Phasea        = 123|0x100U,  /**< XBARA1_OUT123 output assigned to DEC4_PHASEA */
1064     kXBARA1_OutputDec4Phaseb        = 124|0x100U,  /**< XBARA1_OUT124 output assigned to DEC4_PHASEB */
1065     kXBARA1_OutputDec4Index         = 125|0x100U,  /**< XBARA1_OUT125 output assigned to DEC4_INDEX */
1066     kXBARA1_OutputDec4Home          = 126|0x100U,  /**< XBARA1_OUT126 output assigned to DEC4_HOME */
1067     kXBARA1_OutputDec4Trigger       = 127|0x100U,  /**< XBARA1_OUT127 output assigned to DEC4_TRIGGER */
1068     kXBARA1_OutputRESERVED128       = 128|0x100U,  /**< XBARA1_OUT128 output is reserved. */
1069     kXBARA1_OutputRESERVED129       = 129|0x100U,  /**< XBARA1_OUT129 output is reserved. */
1070     kXBARA1_OutputRESERVED130       = 130|0x100U,  /**< XBARA1_OUT130 output is reserved. */
1071     kXBARA1_OutputRESERVED131       = 131|0x100U,  /**< XBARA1_OUT131 output is reserved. */
1072     kXBARA1_OutputCan1              = 132|0x100U,  /**< XBARA1_OUT132 output assigned to CAN1 */
1073     kXBARA1_OutputCan2              = 133|0x100U,  /**< XBARA1_OUT133 output assigned to CAN2 */
1074     kXBARA1_OutputRESERVED134       = 134|0x100U,  /**< XBARA1_OUT134 output is reserved. */
1075     kXBARA1_OutputRESERVED135       = 135|0x100U,  /**< XBARA1_OUT135 output is reserved. */
1076     kXBARA1_OutputRESERVED136       = 136|0x100U,  /**< XBARA1_OUT136 output is reserved. */
1077     kXBARA1_OutputRESERVED137       = 137|0x100U,  /**< XBARA1_OUT137 output is reserved. */
1078     kXBARA1_OutputQtimer1Timer0     = 138|0x100U,  /**< XBARA1_OUT138 output assigned to QTIMER1_TIMER0 */
1079     kXBARA1_OutputQtimer1Timer1     = 139|0x100U,  /**< XBARA1_OUT139 output assigned to QTIMER1_TIMER1 */
1080     kXBARA1_OutputQtimer1Timer2     = 140|0x100U,  /**< XBARA1_OUT140 output assigned to QTIMER1_TIMER2 */
1081     kXBARA1_OutputQtimer1Timer3     = 141|0x100U,  /**< XBARA1_OUT141 output assigned to QTIMER1_TIMER3 */
1082     kXBARA1_OutputQtimer2Timer0     = 142|0x100U,  /**< XBARA1_OUT142 output assigned to QTIMER2_TIMER0 */
1083     kXBARA1_OutputQtimer2Timer1     = 143|0x100U,  /**< XBARA1_OUT143 output assigned to QTIMER2_TIMER1 */
1084     kXBARA1_OutputQtimer2Timer2     = 144|0x100U,  /**< XBARA1_OUT144 output assigned to QTIMER2_TIMER2 */
1085     kXBARA1_OutputQtimer2Timer3     = 145|0x100U,  /**< XBARA1_OUT145 output assigned to QTIMER2_TIMER3 */
1086     kXBARA1_OutputQtimer3Timer0     = 146|0x100U,  /**< XBARA1_OUT146 output assigned to QTIMER3_TIMER0 */
1087     kXBARA1_OutputQtimer3Timer1     = 147|0x100U,  /**< XBARA1_OUT147 output assigned to QTIMER3_TIMER1 */
1088     kXBARA1_OutputQtimer3Timer2     = 148|0x100U,  /**< XBARA1_OUT148 output assigned to QTIMER3_TIMER2 */
1089     kXBARA1_OutputQtimer3Timer3     = 149|0x100U,  /**< XBARA1_OUT149 output assigned to QTIMER3_TIMER3 */
1090     kXBARA1_OutputQtimer4Timer0     = 150|0x100U,  /**< XBARA1_OUT150 output assigned to QTIMER4_TIMER0 */
1091     kXBARA1_OutputQtimer4Timer1     = 151|0x100U,  /**< XBARA1_OUT151 output assigned to QTIMER4_TIMER1 */
1092     kXBARA1_OutputQtimer4Timer2     = 152|0x100U,  /**< XBARA1_OUT152 output assigned to QTIMER4_TIMER2 */
1093     kXBARA1_OutputQtimer4Timer3     = 153|0x100U,  /**< XBARA1_OUT153 output assigned to QTIMER4_TIMER3 */
1094     kXBARA1_OutputEwmEwmIn          = 154|0x100U,  /**< XBARA1_OUT154 output assigned to EWM_EWM_IN */
1095     kXBARA1_OutputAdcEtc0Coco0      = 155|0x100U,  /**< XBARA1_OUT155 output assigned to ADC_ETC0_COCO0 */
1096     kXBARA1_OutputAdcEtc0Coco1      = 156|0x100U,  /**< XBARA1_OUT156 output assigned to ADC_ETC0_COCO1 */
1097     kXBARA1_OutputAdcEtc0Coco2      = 157|0x100U,  /**< XBARA1_OUT157 output assigned to ADC_ETC0_COCO2 */
1098     kXBARA1_OutputAdcEtc0Coco3      = 158|0x100U,  /**< XBARA1_OUT158 output assigned to ADC_ETC0_COCO3 */
1099     kXBARA1_OutputAdcEtc1Coco0      = 159|0x100U,  /**< XBARA1_OUT159 output assigned to ADC_ETC1_COCO0 */
1100     kXBARA1_OutputAdcEtc1Coco1      = 160|0x100U,  /**< XBARA1_OUT160 output assigned to ADC_ETC1_COCO1 */
1101     kXBARA1_OutputAdcEtc1Coco2      = 161|0x100U,  /**< XBARA1_OUT161 output assigned to ADC_ETC1_COCO2 */
1102     kXBARA1_OutputAdcEtc1Coco3      = 162|0x100U,  /**< XBARA1_OUT162 output assigned to ADC_ETC1_COCO3 */
1103     kXBARA1_OutputRESERVED163       = 163|0x100U,  /**< XBARA1_OUT163 output is reserved. */
1104     kXBARA1_OutputRESERVED164       = 164|0x100U,  /**< XBARA1_OUT164 output is reserved. */
1105     kXBARA1_OutputRESERVED165       = 165|0x100U,  /**< XBARA1_OUT165 output is reserved. */
1106     kXBARA1_OutputRESERVED166       = 166|0x100U,  /**< XBARA1_OUT166 output is reserved. */
1107     kXBARA1_OutputRESERVED167       = 167|0x100U,  /**< XBARA1_OUT167 output is reserved. */
1108     kXBARA1_OutputRESERVED168       = 168|0x100U,  /**< XBARA1_OUT168 output is reserved. */
1109     kXBARA1_OutputRESERVED169       = 169|0x100U,  /**< XBARA1_OUT169 output is reserved. */
1110     kXBARA1_OutputRESERVED170       = 170|0x100U,  /**< XBARA1_OUT170 output is reserved. */
1111     kXBARA1_OutputFlexio1TrigIn0    = 171|0x100U,  /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0 */
1112     kXBARA1_OutputFlexio1TrigIn1    = 172|0x100U,  /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1 */
1113     kXBARA1_OutputFlexio2TrigIn0    = 173|0x100U,  /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0 */
1114     kXBARA1_OutputFlexio2TrigIn1    = 174|0x100U,  /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1 */
1115     kXBARB2_OutputAoi1In00          = 0|0x200U,    /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1116     kXBARB2_OutputAoi1In01          = 1|0x200U,    /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1117     kXBARB2_OutputAoi1In02          = 2|0x200U,    /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1118     kXBARB2_OutputAoi1In03          = 3|0x200U,    /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1119     kXBARB2_OutputAoi1In04          = 4|0x200U,    /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1120     kXBARB2_OutputAoi1In05          = 5|0x200U,    /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1121     kXBARB2_OutputAoi1In06          = 6|0x200U,    /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1122     kXBARB2_OutputAoi1In07          = 7|0x200U,    /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1123     kXBARB2_OutputAoi1In08          = 8|0x200U,    /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1124     kXBARB2_OutputAoi1In09          = 9|0x200U,    /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1125     kXBARB2_OutputAoi1In10          = 10|0x200U,   /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1126     kXBARB2_OutputAoi1In11          = 11|0x200U,   /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1127     kXBARB2_OutputAoi1In12          = 12|0x200U,   /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1128     kXBARB2_OutputAoi1In13          = 13|0x200U,   /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1129     kXBARB2_OutputAoi1In14          = 14|0x200U,   /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1130     kXBARB2_OutputAoi1In15          = 15|0x200U,   /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1131     kXBARB3_OutputAoi2In00          = 0|0x300U,    /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1132     kXBARB3_OutputAoi2In01          = 1|0x300U,    /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1133     kXBARB3_OutputAoi2In02          = 2|0x300U,    /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1134     kXBARB3_OutputAoi2In03          = 3|0x300U,    /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1135     kXBARB3_OutputAoi2In04          = 4|0x300U,    /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1136     kXBARB3_OutputAoi2In05          = 5|0x300U,    /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1137     kXBARB3_OutputAoi2In06          = 6|0x300U,    /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1138     kXBARB3_OutputAoi2In07          = 7|0x300U,    /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1139     kXBARB3_OutputAoi2In08          = 8|0x300U,    /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1140     kXBARB3_OutputAoi2In09          = 9|0x300U,    /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1141     kXBARB3_OutputAoi2In10          = 10|0x300U,   /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1142     kXBARB3_OutputAoi2In11          = 11|0x300U,   /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1143     kXBARB3_OutputAoi2In12          = 12|0x300U,   /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1144     kXBARB3_OutputAoi2In13          = 13|0x300U,   /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1145     kXBARB3_OutputAoi2In14          = 14|0x300U,   /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1146     kXBARB3_OutputAoi2In15          = 15|0x300U,   /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1147 } xbar_output_signal_t;
1148 
1149 /*!
1150  * @addtogroup edma_request
1151  * @{
1152  */
1153 
1154 /*******************************************************************************
1155  * Definitions
1156  ******************************************************************************/
1157 
1158 /*!
1159  * @brief Structure for the DMA hardware request
1160  *
1161  * Defines the structure for the DMA hardware request collections. The user can configure the
1162  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
1163  * of the hardware request varies according  to the to SoC.
1164  */
1165 typedef enum _dma_request_source
1166 {
1167     kDmaRequestMuxFlexIO1Request2Request3 = 1|0x100U, /**< FlexIO1 Request2 and Request3 */
1168     kDmaRequestMuxFlexIO1Request4Request5 = 2|0x100U, /**< FlexIO1 Request4 and Request5 */
1169     kDmaRequestMuxFlexIO1Request6Request7 = 3|0x100U, /**< FlexIO1 Request6 and Request7 */
1170     kDmaRequestMuxFlexIO2Request0Request1 = 4|0x100U, /**< FlexIO2 Request0 and Request1 */
1171     kDmaRequestMuxFlexIO2Request2Request3 = 5|0x100U, /**< FlexIO2 Request2 and Request3 */
1172     kDmaRequestMuxFlexIO2Request4Request5 = 6|0x100U, /**< FlexIO2 Request4 and Request5 */
1173     kDmaRequestMuxFlexIO2Request6Request7 = 7|0x100U, /**< FlexIO2 Request6 and Request7 */
1174     kDmaRequestMuxLPUART1Tx         = 8|0x100U,    /**< LPUART1 Transmit */
1175     kDmaRequestMuxLPUART1Rx         = 9|0x100U,    /**< LPUART1 Receive */
1176     kDmaRequestMuxLPUART2Tx         = 10|0x100U,   /**< LPUART2 Transmit */
1177     kDmaRequestMuxLPUART2Rx         = 11|0x100U,   /**< LPUART2 Receive */
1178     kDmaRequestMuxLPUART3Tx         = 12|0x100U,   /**< LPUART3 Transmit */
1179     kDmaRequestMuxLPUART3Rx         = 13|0x100U,   /**< LPUART3 Receive */
1180     kDmaRequestMuxLPUART4Tx         = 14|0x100U,   /**< LPUART4 Transmit */
1181     kDmaRequestMuxLPUART4Rx         = 15|0x100U,   /**< LPUART4 Receive */
1182     kDmaRequestMuxLPUART5Tx         = 16|0x100U,   /**< LPUART5 Transmit */
1183     kDmaRequestMuxLPUART5Rx         = 17|0x100U,   /**< LPUART5 Receive */
1184     kDmaRequestMuxLPUART6Tx         = 18|0x100U,   /**< LPUART6 Transmit */
1185     kDmaRequestMuxLPUART6Rx         = 19|0x100U,   /**< LPUART6 Receive */
1186     kDmaRequestMuxLPUART7Tx         = 20|0x100U,   /**< LPUART7 Transmit */
1187     kDmaRequestMuxLPUART7Rx         = 21|0x100U,   /**< LPUART7 Receive */
1188     kDmaRequestMuxLPUART8Tx         = 22|0x100U,   /**< LPUART8 Transmit */
1189     kDmaRequestMuxLPUART8Rx         = 23|0x100U,   /**< LPUART8 Receive */
1190     kDmaRequestMuxLPUART9Tx         = 24|0x100U,   /**< LPUART9 Transmit */
1191     kDmaRequestMuxLPUART9Rx         = 25|0x100U,   /**< LPUART9 Receive */
1192     kDmaRequestMuxLPUART10Tx        = 26|0x100U,   /**< LPUART10 Transmit */
1193     kDmaRequestMuxLPUART10Rx        = 27|0x100U,   /**< LPUART10 Receive */
1194     kDmaRequestMuxLPUART11Tx        = 28|0x100U,   /**< LPUART11 Transmit */
1195     kDmaRequestMuxLPUART11Rx        = 29|0x100U,   /**< LPUART11 Receive */
1196     kDmaRequestMuxLPUART12Tx        = 30|0x100U,   /**< LPUART12 Transmit */
1197     kDmaRequestMuxLPUART12Rx        = 31|0x100U,   /**< LPUART12 Receive */
1198     kDmaRequestMuxCSI               = 32|0x100U,   /**< CSI */
1199     kDmaRequestMuxPxp               = 33|0x100U,   /**< PXP */
1200     kDmaRequestMuxeLCDIF            = 34|0x100U,   /**< eLCDIF */
1201     kDmaRequestMuxLCDIFv2           = 35|0x100U,   /**< LCDIFv2 */
1202     kDmaRequestMuxLPSPI1Rx          = 36|0x100U,   /**< LPSPI1 Receive */
1203     kDmaRequestMuxLPSPI1Tx          = 37|0x100U,   /**< LPSPI1 Transmit */
1204     kDmaRequestMuxLPSPI2Rx          = 38|0x100U,   /**< LPSPI2 Receive */
1205     kDmaRequestMuxLPSPI2Tx          = 39|0x100U,   /**< LPSPI2 Transmit */
1206     kDmaRequestMuxLPSPI3Rx          = 40|0x100U,   /**< LPSPI3 Receive */
1207     kDmaRequestMuxLPSPI3Tx          = 41|0x100U,   /**< LPSPI3 Transmit */
1208     kDmaRequestMuxLPSPI4Rx          = 42|0x100U,   /**< LPSPI4 Receive */
1209     kDmaRequestMuxLPSPI4Tx          = 43|0x100U,   /**< LPSPI4 Transmit */
1210     kDmaRequestMuxLPSPI5Rx          = 44|0x100U,   /**< LPSPI5 Receive */
1211     kDmaRequestMuxLPSPI5Tx          = 45|0x100U,   /**< LPSPI5 Transmit */
1212     kDmaRequestMuxLPSPI6Rx          = 46|0x100U,   /**< LPSPI6 Receive */
1213     kDmaRequestMuxLPSPI6Tx          = 47|0x100U,   /**< LPSPI6 Transmit */
1214     kDmaRequestMuxLPI2C1            = 48|0x100U,   /**< LPI2C1 */
1215     kDmaRequestMuxLPI2C2            = 49|0x100U,   /**< LPI2C2 */
1216     kDmaRequestMuxLPI2C3            = 50|0x100U,   /**< LPI2C3 */
1217     kDmaRequestMuxLPI2C4            = 51|0x100U,   /**< LPI2C4 */
1218     kDmaRequestMuxLPI2C5            = 52|0x100U,   /**< LPI2C5 */
1219     kDmaRequestMuxLPI2C6            = 53|0x100U,   /**< LPI2C6 */
1220     kDmaRequestMuxSai1Rx            = 54|0x100U,   /**< SAI1 Receive */
1221     kDmaRequestMuxSai1Tx            = 55|0x100U,   /**< SAI1 Transmit */
1222     kDmaRequestMuxSai2Rx            = 56|0x100U,   /**< SAI2 Receive */
1223     kDmaRequestMuxSai2Tx            = 57|0x100U,   /**< SAI2 Transmit */
1224     kDmaRequestMuxSai3Rx            = 58|0x100U,   /**< SAI3 Receive */
1225     kDmaRequestMuxSai3Tx            = 59|0x100U,   /**< SAI3 Transmit */
1226     kDmaRequestMuxSai4Rx            = 60|0x100U,   /**< SAI4 Receive */
1227     kDmaRequestMuxSai4Tx            = 61|0x100U,   /**< SAI4 Transmit */
1228     kDmaRequestMuxSpdifRx           = 62|0x100U,   /**< SPDIF Receive */
1229     kDmaRequestMuxSpdifTx           = 63|0x100U,   /**< SPDIF Transmit */
1230     kDmaRequestMuxADC_ETC           = 64|0x100U,   /**< ADC_ETC */
1231     kDmaRequestMuxFlexIO1Request0Request1 = 65|0x100U, /**< FlexIO1 Request0 and Request1 */
1232     kDmaRequestMuxADC1              = 66|0x100U,   /**< ADC1 */
1233     kDmaRequestMuxADC2              = 67|0x100U,   /**< ADC2 */
1234     kDmaRequestMuxACMP1             = 69|0x100U,   /**< ACMP1 */
1235     kDmaRequestMuxACMP2             = 70|0x100U,   /**< ACMP2 */
1236     kDmaRequestMuxACMP3             = 71|0x100U,   /**< ACMP3 */
1237     kDmaRequestMuxACMP4             = 72|0x100U,   /**< ACMP4 */
1238     kDmaRequestMuxFlexSPI1Rx        = 77|0x100U,   /**< FlexSPI1 Receive */
1239     kDmaRequestMuxFlexSPI1Tx        = 78|0x100U,   /**< FlexSPI1 Transmit */
1240     kDmaRequestMuxFlexSPI2Rx        = 79|0x100U,   /**< FlexSPI2 Receive */
1241     kDmaRequestMuxFlexSPI2Tx        = 80|0x100U,   /**< FlexSPI2 Transmit */
1242     kDmaRequestMuxXBAR1Request0     = 81|0x100U,   /**< XBAR1 Request 0 */
1243     kDmaRequestMuxXBAR1Request1     = 82|0x100U,   /**< XBAR1 Request 1 */
1244     kDmaRequestMuxXBAR1Request2     = 83|0x100U,   /**< XBAR1 Request 2 */
1245     kDmaRequestMuxXBAR1Request3     = 84|0x100U,   /**< XBAR1 Request 3 */
1246     kDmaRequestMuxFlexPWM1CaptureSub0 = 85|0x100U, /**< FlexPWM1 Capture sub-module0 */
1247     kDmaRequestMuxFlexPWM1CaptureSub1 = 86|0x100U, /**< FlexPWM1 Capture sub-module1 */
1248     kDmaRequestMuxFlexPWM1CaptureSub2 = 87|0x100U, /**< FlexPWM1 Capture sub-module2 */
1249     kDmaRequestMuxFlexPWM1CaptureSub3 = 88|0x100U, /**< FlexPWM1 Capture sub-module3 */
1250     kDmaRequestMuxFlexPWM1ValueSub0 = 89|0x100U,   /**< FlexPWM1 Value sub-module 0 */
1251     kDmaRequestMuxFlexPWM1ValueSub1 = 90|0x100U,   /**< FlexPWM1 Value sub-module 1 */
1252     kDmaRequestMuxFlexPWM1ValueSub2 = 91|0x100U,   /**< FlexPWM1 Value sub-module 2 */
1253     kDmaRequestMuxFlexPWM1ValueSub3 = 92|0x100U,   /**< FlexPWM1 Value sub-module 3 */
1254     kDmaRequestMuxFlexPWM2CaptureSub0 = 93|0x100U, /**< FlexPWM2 Capture sub-module0 */
1255     kDmaRequestMuxFlexPWM2CaptureSub1 = 94|0x100U, /**< FlexPWM2 Capture sub-module1 */
1256     kDmaRequestMuxFlexPWM2CaptureSub2 = 95|0x100U, /**< FlexPWM2 Capture sub-module2 */
1257     kDmaRequestMuxFlexPWM2CaptureSub3 = 96|0x100U, /**< FlexPWM2 Capture sub-module3 */
1258     kDmaRequestMuxFlexPWM2ValueSub0 = 97|0x100U,   /**< FlexPWM2 Value sub-module 0 */
1259     kDmaRequestMuxFlexPWM2ValueSub1 = 98|0x100U,   /**< FlexPWM2 Value sub-module 1 */
1260     kDmaRequestMuxFlexPWM2ValueSub2 = 99|0x100U,   /**< FlexPWM2 Value sub-module 2 */
1261     kDmaRequestMuxFlexPWM2ValueSub3 = 100|0x100U,  /**< FlexPWM2 Value sub-module 3 */
1262     kDmaRequestMuxFlexPWM3CaptureSub0 = 101|0x100U, /**< FlexPWM3 Capture sub-module0 */
1263     kDmaRequestMuxFlexPWM3CaptureSub1 = 102|0x100U, /**< FlexPWM3 Capture sub-module1 */
1264     kDmaRequestMuxFlexPWM3CaptureSub2 = 103|0x100U, /**< FlexPWM3 Capture sub-module2 */
1265     kDmaRequestMuxFlexPWM3CaptureSub3 = 104|0x100U, /**< FlexPWM3 Capture sub-module3 */
1266     kDmaRequestMuxFlexPWM3ValueSub0 = 105|0x100U,  /**< FlexPWM3 Value sub-module 0 */
1267     kDmaRequestMuxFlexPWM3ValueSub1 = 106|0x100U,  /**< FlexPWM3 Value sub-module 1 */
1268     kDmaRequestMuxFlexPWM3ValueSub2 = 107|0x100U,  /**< FlexPWM3 Value sub-module 2 */
1269     kDmaRequestMuxFlexPWM3ValueSub3 = 108|0x100U,  /**< FlexPWM3 Value sub-module 3 */
1270     kDmaRequestMuxFlexPWM4CaptureSub0 = 109|0x100U, /**< FlexPWM4 Capture sub-module0 */
1271     kDmaRequestMuxFlexPWM4CaptureSub1 = 110|0x100U, /**< FlexPWM4 Capture sub-module1 */
1272     kDmaRequestMuxFlexPWM4CaptureSub2 = 111|0x100U, /**< FlexPWM4 Capture sub-module2 */
1273     kDmaRequestMuxFlexPWM4CaptureSub3 = 112|0x100U, /**< FlexPWM4 Capture sub-module3 */
1274     kDmaRequestMuxFlexPWM4ValueSub0 = 113|0x100U,  /**< FlexPWM4 Value sub-module 0 */
1275     kDmaRequestMuxFlexPWM4ValueSub1 = 114|0x100U,  /**< FlexPWM4 Value sub-module 1 */
1276     kDmaRequestMuxFlexPWM4ValueSub2 = 115|0x100U,  /**< FlexPWM4 Value sub-module 2 */
1277     kDmaRequestMuxFlexPWM4ValueSub3 = 116|0x100U,  /**< FlexPWM4 Value sub-module 3 */
1278     kDmaRequestMuxQTIMER1CaptTimer0 = 133|0x100U,  /**< TMR1 Capture timer 0 */
1279     kDmaRequestMuxQTIMER1CaptTimer1 = 134|0x100U,  /**< TMR1 Capture timer 1 */
1280     kDmaRequestMuxQTIMER1CaptTimer2 = 135|0x100U,  /**< TMR1 Capture timer 2 */
1281     kDmaRequestMuxQTIMER1CaptTimer3 = 136|0x100U,  /**< TMR1 Capture timer 3 */
1282     kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 137|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
1283     kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 138|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
1284     kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 139|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
1285     kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 140|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
1286     kDmaRequestMuxQTIMER2CaptTimer0 = 141|0x100U,  /**< TMR2 Capture timer 0 */
1287     kDmaRequestMuxQTIMER2CaptTimer1 = 142|0x100U,  /**< TMR2 Capture timer 1 */
1288     kDmaRequestMuxQTIMER2CaptTimer2 = 143|0x100U,  /**< TMR2 Capture timer 2 */
1289     kDmaRequestMuxQTIMER2CaptTimer3 = 144|0x100U,  /**< TMR2 Capture timer 3 */
1290     kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 145|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
1291     kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 146|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
1292     kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 147|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
1293     kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 148|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
1294     kDmaRequestMuxQTIMER3CaptTimer0 = 149|0x100U,  /**< TMR3 Capture timer 0 */
1295     kDmaRequestMuxQTIMER3CaptTimer1 = 150|0x100U,  /**< TMR3 Capture timer 1 */
1296     kDmaRequestMuxQTIMER3CaptTimer2 = 151|0x100U,  /**< TMR3 Capture timer 2 */
1297     kDmaRequestMuxQTIMER3CaptTimer3 = 152|0x100U,  /**< TMR3 Capture timer 3 */
1298     kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 153|0x100U, /**< TMR3 cmpld1 in timer 0 or cmpld2 in timer 1 */
1299     kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 154|0x100U, /**< TMR3 cmpld1 in timer 1 or cmpld2 in timer 0 */
1300     kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 155|0x100U, /**< TMR3 cmpld1 in timer 2 or cmpld2 in timer 3 */
1301     kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 156|0x100U, /**< TMR3 cmpld1 in timer 3 or cmpld2 in timer 2 */
1302     kDmaRequestMuxQTIMER4CaptTimer0 = 157|0x100U,  /**< TMR4 Capture timer 0 */
1303     kDmaRequestMuxQTIMER4CaptTimer1 = 158|0x100U,  /**< TMR4 Capture timer 1 */
1304     kDmaRequestMuxQTIMER4CaptTimer2 = 159|0x100U,  /**< TMR4 Capture timer 2 */
1305     kDmaRequestMuxQTIMER4CaptTimer3 = 160|0x100U,  /**< TMR4 Capture timer 3 */
1306     kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 161|0x100U, /**< TMR4 cmpld1 in timer 0 or cmpld2 in timer 1 */
1307     kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 162|0x100U, /**< TMR4 cmpld1 in timer 1 or cmpld2 in timer 0 */
1308     kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 163|0x100U, /**< TMR4 cmpld1 in timer 2 or cmpld2 in timer 3 */
1309     kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 164|0x100U, /**< TMR4 cmpld1 in timer 3 or cmpld2 in timer 2 */
1310     kDmaRequestMuxPdm               = 181|0x100U,  /**< PDM */
1311     kDmaRequestMuxEnetTimer0        = 182|0x100U,  /**< ENET Timer0 */
1312     kDmaRequestMuxEnetTimer1        = 183|0x100U,  /**< ENET Timer1 */
1313     kDmaRequestMuxEnet1GTimer0      = 184|0x100U,  /**< ENET 1G Timer0 */
1314     kDmaRequestMuxEnet1GTimer1      = 185|0x100U,  /**< ENET 1G Timer1 */
1315     kDmaRequestMuxCAN1              = 186|0x100U,  /**< CAN1 */
1316     kDmaRequestMuxCAN2              = 187|0x100U,  /**< CAN2 */
1317     kDmaRequestMuxCAN3              = 188|0x100U,  /**< CAN3 */
1318     kDmaRequestMuxDAC               = 189|0x100U,  /**< DAC */
1319     kDmaRequestMuxASRCRequest1      = 191|0x100U,  /**< ASRC request 1 pair A input request */
1320     kDmaRequestMuxASRCRequest2      = 192|0x100U,  /**< ASRC request 2 pair B input request */
1321     kDmaRequestMuxASRCRequest3      = 193|0x100U,  /**< ASRC request 3 pair C input request */
1322     kDmaRequestMuxASRCRequest4      = 194|0x100U,  /**< ASRC request 4 pair A output request */
1323     kDmaRequestMuxASRCRequest5      = 195|0x100U,  /**< ASRC request 5 pair B output request */
1324     kDmaRequestMuxASRCRequest6      = 196|0x100U,  /**< ASRC request 6 pair C output request */
1325     kDmaRequestMuxEmvsim1Tx         = 197|0x100U,  /**< Emvsim1 Transmit */
1326     kDmaRequestMuxEmvsim1Rx         = 198|0x100U,  /**< Emvsim1 Receive */
1327     kDmaRequestMuxEmvsim2Tx         = 199|0x100U,  /**< Emvsim2 Transmit */
1328     kDmaRequestMuxEmvsim2Rx         = 200|0x100U,  /**< Emvsim2 Receive */
1329     kDmaRequestMuxEnetQosTimer0     = 201|0x100U,  /**< ENET_QOS Timer0 */
1330     kDmaRequestMuxEnetQosTimer1     = 202|0x100U,  /**< ENET_QOS Timer1 */
1331 } dma_request_source_t;
1332 
1333 /* @} */
1334 
1335 /*!
1336  * @addtogroup iomuxc_lpsr_pads
1337  * @{ */
1338 
1339 /*******************************************************************************
1340  * Definitions
1341 *******************************************************************************/
1342 
1343 /*!
1344  * @brief Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD
1345  *
1346  * Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.
1347  */
1348 typedef enum _iomuxc_lpsr_sw_mux_ctl_pad
1349 {
1350     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
1351     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
1352     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
1353     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
1354     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
1355     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
1356     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
1357     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
1358     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
1359     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
1360     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
1361     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
1362     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
1363     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
1364     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
1365     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
1366 } iomuxc_lpsr_sw_mux_ctl_pad_t;
1367 
1368 /* @} */
1369 
1370 /*!
1371  * @addtogroup iomuxc_lpsr_pads
1372  * @{ */
1373 
1374 /*******************************************************************************
1375  * Definitions
1376 *******************************************************************************/
1377 
1378 /*!
1379  * @brief Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD
1380  *
1381  * Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.
1382  */
1383 typedef enum _iomuxc_lpsr_sw_pad_ctl_pad
1384 {
1385     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
1386     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
1387     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
1388     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
1389     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
1390     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
1391     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
1392     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
1393     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
1394     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
1395     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
1396     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
1397     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
1398     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
1399     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
1400     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
1401 } iomuxc_lpsr_sw_pad_ctl_pad_t;
1402 
1403 /* @} */
1404 
1405 /*!
1406  * @brief Enumeration for the IOMUXC_LPSR select input
1407  *
1408  * Defines the enumeration for the IOMUXC_LPSR select input collections.
1409  */
1410 typedef enum _iomuxc_lpsr_select_input
1411 {
1412     kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U, /**< IOMUXC select input index */
1413     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U, /**< IOMUXC select input index */
1414     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U, /**< IOMUXC select input index */
1415     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U, /**< IOMUXC select input index */
1416     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U, /**< IOMUXC select input index */
1417     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U, /**< IOMUXC select input index */
1418     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U, /**< IOMUXC select input index */
1419     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U, /**< IOMUXC select input index */
1420     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U, /**< IOMUXC select input index */
1421     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U, /**< IOMUXC select input index */
1422     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U, /**< IOMUXC select input index */
1423     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U, /**< IOMUXC select input index */
1424     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U, /**< IOMUXC select input index */
1425     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U, /**< IOMUXC select input index */
1426     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U, /**< IOMUXC select input index */
1427     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U, /**< IOMUXC select input index */
1428     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U, /**< IOMUXC select input index */
1429     kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U, /**< IOMUXC select input index */
1430     kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U, /**< IOMUXC select input index */
1431     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
1432     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U, /**< IOMUXC select input index */
1433     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U, /**< IOMUXC select input index */
1434     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
1435     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
1436 } iomuxc_lpsr_select_input_t;
1437 
1438 /*!
1439  * @addtogroup ssarc_mapping
1440  * @{
1441  */
1442 
1443 /*******************************************************************************
1444  * Definitions
1445  ******************************************************************************/
1446 
1447 /*!
1448  * @brief Structure for the SSARC mapping
1449  *
1450  * The name of power domain.
1451  */
1452 
1453 typedef enum _ssarc_power_domain_name
1454 {
1455     kSSARC_MEGAMIXPowerDomain       = 0U,          /**< MEGAMIX Power Domain, request from BPC0. */
1456     kSSARC_DISPLAYMIXPowerDomain    = 1U,          /**< DISPLAYMIX Power Domain, request from BPC1. */
1457     kSSARC_WAKEUPMIXPowerDomain     = 2U,          /**< WAKEUPMIX Power Domain, request from BPC2. */
1458     kSSARC_LPSRMIXPowerDomain       = 3U,          /**< LPSRMIX Power Domain, request from BPC3. */
1459     kSSARC_PowerDomain4             = 4U,          /**< MIPI PHY Power Domain, request from BPC4. */
1460     kSSARC_PowerDomain5             = 5U,          /**< Virtual power domain, request from BPC5. */
1461     kSSARC_PowerDomain6             = 6U,          /**< Virtual power domain, request from BPC6. */
1462     kSSARC_PowerDomain7             = 7U,          /**< Virtual power domain, request from BPC7. */
1463 } ssarc_power_domain_name_t;
1464 
1465  /*
1466  * @brief The name of cpu domain.
1467  */
1468 typedef enum _ssarc_cpu_domain_name
1469 {
1470     kSSARC_CM7Core                  = 0U,          /**< CM7 Core domain. */
1471     kSSARC_CM4Core                  = 1U,          /**< CM4 Core domain. */
1472 } ssarc_cpu_domain_name_t;
1473 
1474 /* @} */
1475 
1476 /*!
1477  * @addtogroup xrdc2_mapping
1478  * @{
1479  */
1480 
1481 /*******************************************************************************
1482  * Definitions
1483  ******************************************************************************/
1484 
1485 /*!
1486  * @brief Structure for the XRDC2 mapping
1487  *
1488  * Defines the structure for the XRDC2 resource collections.
1489  */
1490 
1491 typedef enum _xrdc2_master
1492 {
1493     kXRDC2_Master_M7_AHB            = 0U,          /**< M7 AHB */
1494     kXRDC2_Master_M4_AHBC           = 0U,          /**< M4 AHBC */
1495     kXRDC2_Master_M7_AXI            = 1U,          /**< M7 AXI */
1496     kXRDC2_Master_M4_AHBS           = 1U,          /**< M4 AHBS */
1497     kXRDC2_Master_CAAM              = 2U,          /**< CAAM */
1498     kXRDC2_Master_CSI               = 3U,          /**< CSI */
1499     kXRDC2_Master_M7_EDMA           = 4U,          /**< M7 EDMA */
1500     kXRDC2_Master_M4_EDMA           = 4U,          /**< M4 EDMA */
1501     kXRDC2_Master_ENET              = 5U,          /**< ENET */
1502     kXRDC2_Master_ENET_1G_RX        = 6U,          /**< ENET_1G_RX */
1503     kXRDC2_Master_ENET_1G_TX        = 7U,          /**< ENET_1G_TX */
1504     kXRDC2_Master_ENET_QOS          = 8U,          /**< ENET_QOS */
1505     kXRDC2_Master_GPU               = 9U,          /**< GPU */
1506     kXRDC2_Master_LCDIF             = 10U,         /**< LCDIF */
1507     kXRDC2_Master_LCDIFV2           = 11U,         /**< LCDIFV2 */
1508     kXRDC2_Master_PXP               = 12U,         /**< PXP */
1509     kXRDC2_Master_SSARC             = 14U,         /**< SSARC */
1510     kXRDC2_Master_USB               = 15U,         /**< USB */
1511     kXRDC2_Master_USDHC1            = 16U,         /**< USDHC1 */
1512     kXRDC2_Master_USDHC2            = 17U,         /**< USDHC2 */
1513 } xrdc2_master_t;
1514 
1515 typedef enum _xrdc2_mem
1516 {
1517     kXRDC2_Mem_CAAM_Region0         = XRDC2_MAKE_MEM(0, 0), /**< MRC0 Memory 0 */
1518     kXRDC2_Mem_CAAM_Region1         = XRDC2_MAKE_MEM(0, 1), /**< MRC0 Memory 1 */
1519     kXRDC2_Mem_CAAM_Region2         = XRDC2_MAKE_MEM(0, 2), /**< MRC0 Memory 2 */
1520     kXRDC2_Mem_CAAM_Region3         = XRDC2_MAKE_MEM(0, 3), /**< MRC0 Memory 3 */
1521     kXRDC2_Mem_CAAM_Region4         = XRDC2_MAKE_MEM(0, 4), /**< MRC0 Memory 4 */
1522     kXRDC2_Mem_CAAM_Region5         = XRDC2_MAKE_MEM(0, 5), /**< MRC0 Memory 5 */
1523     kXRDC2_Mem_CAAM_Region6         = XRDC2_MAKE_MEM(0, 6), /**< MRC0 Memory 6 */
1524     kXRDC2_Mem_CAAM_Region7         = XRDC2_MAKE_MEM(0, 7), /**< MRC0 Memory 7 */
1525     kXRDC2_Mem_CAAM_Region8         = XRDC2_MAKE_MEM(0, 8), /**< MRC0 Memory 8 */
1526     kXRDC2_Mem_CAAM_Region9         = XRDC2_MAKE_MEM(0, 9), /**< MRC0 Memory 9 */
1527     kXRDC2_Mem_CAAM_Region10        = XRDC2_MAKE_MEM(0, 10), /**< MRC0 Memory 10 */
1528     kXRDC2_Mem_CAAM_Region11        = XRDC2_MAKE_MEM(0, 11), /**< MRC0 Memory 11 */
1529     kXRDC2_Mem_CAAM_Region12        = XRDC2_MAKE_MEM(0, 12), /**< MRC0 Memory 12 */
1530     kXRDC2_Mem_CAAM_Region13        = XRDC2_MAKE_MEM(0, 13), /**< MRC0 Memory 13 */
1531     kXRDC2_Mem_CAAM_Region14        = XRDC2_MAKE_MEM(0, 14), /**< MRC0 Memory 14 */
1532     kXRDC2_Mem_CAAM_Region15        = XRDC2_MAKE_MEM(0, 15), /**< MRC0 Memory 15 */
1533     kXRDC2_Mem_FLEXSPI1_Region0     = XRDC2_MAKE_MEM(1, 0), /**< MRC1 Memory 0 */
1534     kXRDC2_Mem_FLEXSPI1_Region1     = XRDC2_MAKE_MEM(1, 1), /**< MRC1 Memory 1 */
1535     kXRDC2_Mem_FLEXSPI1_Region2     = XRDC2_MAKE_MEM(1, 2), /**< MRC1 Memory 2 */
1536     kXRDC2_Mem_FLEXSPI1_Region3     = XRDC2_MAKE_MEM(1, 3), /**< MRC1 Memory 3 */
1537     kXRDC2_Mem_FLEXSPI1_Region4     = XRDC2_MAKE_MEM(1, 4), /**< MRC1 Memory 4 */
1538     kXRDC2_Mem_FLEXSPI1_Region5     = XRDC2_MAKE_MEM(1, 5), /**< MRC1 Memory 5 */
1539     kXRDC2_Mem_FLEXSPI1_Region6     = XRDC2_MAKE_MEM(1, 6), /**< MRC1 Memory 6 */
1540     kXRDC2_Mem_FLEXSPI1_Region7     = XRDC2_MAKE_MEM(1, 7), /**< MRC1 Memory 7 */
1541     kXRDC2_Mem_FLEXSPI1_Region8     = XRDC2_MAKE_MEM(1, 8), /**< MRC1 Memory 8 */
1542     kXRDC2_Mem_FLEXSPI1_Region9     = XRDC2_MAKE_MEM(1, 9), /**< MRC1 Memory 9 */
1543     kXRDC2_Mem_FLEXSPI1_Region10    = XRDC2_MAKE_MEM(1, 10), /**< MRC1 Memory 10 */
1544     kXRDC2_Mem_FLEXSPI1_Region11    = XRDC2_MAKE_MEM(1, 11), /**< MRC1 Memory 11 */
1545     kXRDC2_Mem_FLEXSPI1_Region12    = XRDC2_MAKE_MEM(1, 12), /**< MRC1 Memory 12 */
1546     kXRDC2_Mem_FLEXSPI1_Region13    = XRDC2_MAKE_MEM(1, 13), /**< MRC1 Memory 13 */
1547     kXRDC2_Mem_FLEXSPI1_Region14    = XRDC2_MAKE_MEM(1, 14), /**< MRC1 Memory 14 */
1548     kXRDC2_Mem_FLEXSPI1_Region15    = XRDC2_MAKE_MEM(1, 15), /**< MRC1 Memory 15 */
1549     kXRDC2_Mem_FLEXSPI2_Region0     = XRDC2_MAKE_MEM(2, 0), /**< MRC2 Memory 0 */
1550     kXRDC2_Mem_FLEXSPI2_Region1     = XRDC2_MAKE_MEM(2, 1), /**< MRC2 Memory 1 */
1551     kXRDC2_Mem_FLEXSPI2_Region2     = XRDC2_MAKE_MEM(2, 2), /**< MRC2 Memory 2 */
1552     kXRDC2_Mem_FLEXSPI2_Region3     = XRDC2_MAKE_MEM(2, 3), /**< MRC2 Memory 3 */
1553     kXRDC2_Mem_FLEXSPI2_Region4     = XRDC2_MAKE_MEM(2, 4), /**< MRC2 Memory 4 */
1554     kXRDC2_Mem_FLEXSPI2_Region5     = XRDC2_MAKE_MEM(2, 5), /**< MRC2 Memory 5 */
1555     kXRDC2_Mem_FLEXSPI2_Region6     = XRDC2_MAKE_MEM(2, 6), /**< MRC2 Memory 6 */
1556     kXRDC2_Mem_FLEXSPI2_Region7     = XRDC2_MAKE_MEM(2, 7), /**< MRC2 Memory 7 */
1557     kXRDC2_Mem_FLEXSPI2_Region8     = XRDC2_MAKE_MEM(2, 8), /**< MRC2 Memory 8 */
1558     kXRDC2_Mem_FLEXSPI2_Region9     = XRDC2_MAKE_MEM(2, 9), /**< MRC2 Memory 9 */
1559     kXRDC2_Mem_FLEXSPI2_Region10    = XRDC2_MAKE_MEM(2, 10), /**< MRC2 Memory 10 */
1560     kXRDC2_Mem_FLEXSPI2_Region11    = XRDC2_MAKE_MEM(2, 11), /**< MRC2 Memory 11 */
1561     kXRDC2_Mem_FLEXSPI2_Region12    = XRDC2_MAKE_MEM(2, 12), /**< MRC2 Memory 12 */
1562     kXRDC2_Mem_FLEXSPI2_Region13    = XRDC2_MAKE_MEM(2, 13), /**< MRC2 Memory 13 */
1563     kXRDC2_Mem_FLEXSPI2_Region14    = XRDC2_MAKE_MEM(2, 14), /**< MRC2 Memory 14 */
1564     kXRDC2_Mem_FLEXSPI2_Region15    = XRDC2_MAKE_MEM(2, 15), /**< MRC2 Memory 15 */
1565     kXRDC2_Mem_M4LMEM_Region0       = XRDC2_MAKE_MEM(3, 0), /**< MRC3 Memory 0 */
1566     kXRDC2_Mem_M4LMEM_Region1       = XRDC2_MAKE_MEM(3, 1), /**< MRC3 Memory 1 */
1567     kXRDC2_Mem_M4LMEM_Region2       = XRDC2_MAKE_MEM(3, 2), /**< MRC3 Memory 2 */
1568     kXRDC2_Mem_M4LMEM_Region3       = XRDC2_MAKE_MEM(3, 3), /**< MRC3 Memory 3 */
1569     kXRDC2_Mem_M4LMEM_Region4       = XRDC2_MAKE_MEM(3, 4), /**< MRC3 Memory 4 */
1570     kXRDC2_Mem_M4LMEM_Region5       = XRDC2_MAKE_MEM(3, 5), /**< MRC3 Memory 5 */
1571     kXRDC2_Mem_M4LMEM_Region6       = XRDC2_MAKE_MEM(3, 6), /**< MRC3 Memory 6 */
1572     kXRDC2_Mem_M4LMEM_Region7       = XRDC2_MAKE_MEM(3, 7), /**< MRC3 Memory 7 */
1573     kXRDC2_Mem_M4LMEM_Region8       = XRDC2_MAKE_MEM(3, 8), /**< MRC3 Memory 8 */
1574     kXRDC2_Mem_M4LMEM_Region9       = XRDC2_MAKE_MEM(3, 9), /**< MRC3 Memory 9 */
1575     kXRDC2_Mem_M4LMEM_Region10      = XRDC2_MAKE_MEM(3, 10), /**< MRC3 Memory 10 */
1576     kXRDC2_Mem_M4LMEM_Region11      = XRDC2_MAKE_MEM(3, 11), /**< MRC3 Memory 11 */
1577     kXRDC2_Mem_M4LMEM_Region12      = XRDC2_MAKE_MEM(3, 12), /**< MRC3 Memory 12 */
1578     kXRDC2_Mem_M4LMEM_Region13      = XRDC2_MAKE_MEM(3, 13), /**< MRC3 Memory 13 */
1579     kXRDC2_Mem_M4LMEM_Region14      = XRDC2_MAKE_MEM(3, 14), /**< MRC3 Memory 14 */
1580     kXRDC2_Mem_M4LMEM_Region15      = XRDC2_MAKE_MEM(3, 15), /**< MRC3 Memory 15 */
1581     kXRDC2_Mem_M7OC_Region0         = XRDC2_MAKE_MEM(4, 0), /**< MRC4 Memory 0 */
1582     kXRDC2_Mem_M7OC_Region1         = XRDC2_MAKE_MEM(4, 1), /**< MRC4 Memory 1 */
1583     kXRDC2_Mem_M7OC_Region2         = XRDC2_MAKE_MEM(4, 2), /**< MRC4 Memory 2 */
1584     kXRDC2_Mem_M7OC_Region3         = XRDC2_MAKE_MEM(4, 3), /**< MRC4 Memory 3 */
1585     kXRDC2_Mem_M7OC_Region4         = XRDC2_MAKE_MEM(4, 4), /**< MRC4 Memory 4 */
1586     kXRDC2_Mem_M7OC_Region5         = XRDC2_MAKE_MEM(4, 5), /**< MRC4 Memory 5 */
1587     kXRDC2_Mem_M7OC_Region6         = XRDC2_MAKE_MEM(4, 6), /**< MRC4 Memory 6 */
1588     kXRDC2_Mem_M7OC_Region7         = XRDC2_MAKE_MEM(4, 7), /**< MRC4 Memory 7 */
1589     kXRDC2_Mem_M7OC_Region8         = XRDC2_MAKE_MEM(4, 8), /**< MRC4 Memory 8 */
1590     kXRDC2_Mem_M7OC_Region9         = XRDC2_MAKE_MEM(4, 9), /**< MRC4 Memory 9 */
1591     kXRDC2_Mem_M7OC_Region10        = XRDC2_MAKE_MEM(4, 10), /**< MRC4 Memory 10 */
1592     kXRDC2_Mem_M7OC_Region11        = XRDC2_MAKE_MEM(4, 11), /**< MRC4 Memory 11 */
1593     kXRDC2_Mem_M7OC_Region12        = XRDC2_MAKE_MEM(4, 12), /**< MRC4 Memory 12 */
1594     kXRDC2_Mem_M7OC_Region13        = XRDC2_MAKE_MEM(4, 13), /**< MRC4 Memory 13 */
1595     kXRDC2_Mem_M7OC_Region14        = XRDC2_MAKE_MEM(4, 14), /**< MRC4 Memory 14 */
1596     kXRDC2_Mem_M7OC_Region15        = XRDC2_MAKE_MEM(4, 15), /**< MRC4 Memory 15 */
1597     kXRDC2_Mem_MECC1_Region0        = XRDC2_MAKE_MEM(5, 0), /**< MRC5 Memory 0 */
1598     kXRDC2_Mem_MECC1_Region1        = XRDC2_MAKE_MEM(5, 1), /**< MRC5 Memory 1 */
1599     kXRDC2_Mem_MECC1_Region2        = XRDC2_MAKE_MEM(5, 2), /**< MRC5 Memory 2 */
1600     kXRDC2_Mem_MECC1_Region3        = XRDC2_MAKE_MEM(5, 3), /**< MRC5 Memory 3 */
1601     kXRDC2_Mem_MECC1_Region4        = XRDC2_MAKE_MEM(5, 4), /**< MRC5 Memory 4 */
1602     kXRDC2_Mem_MECC1_Region5        = XRDC2_MAKE_MEM(5, 5), /**< MRC5 Memory 5 */
1603     kXRDC2_Mem_MECC1_Region6        = XRDC2_MAKE_MEM(5, 6), /**< MRC5 Memory 6 */
1604     kXRDC2_Mem_MECC1_Region7        = XRDC2_MAKE_MEM(5, 7), /**< MRC5 Memory 7 */
1605     kXRDC2_Mem_MECC1_Region8        = XRDC2_MAKE_MEM(5, 8), /**< MRC5 Memory 8 */
1606     kXRDC2_Mem_MECC1_Region9        = XRDC2_MAKE_MEM(5, 9), /**< MRC5 Memory 9 */
1607     kXRDC2_Mem_MECC1_Region10       = XRDC2_MAKE_MEM(5, 10), /**< MRC5 Memory 10 */
1608     kXRDC2_Mem_MECC1_Region11       = XRDC2_MAKE_MEM(5, 11), /**< MRC5 Memory 11 */
1609     kXRDC2_Mem_MECC1_Region12       = XRDC2_MAKE_MEM(5, 12), /**< MRC5 Memory 12 */
1610     kXRDC2_Mem_MECC1_Region13       = XRDC2_MAKE_MEM(5, 13), /**< MRC5 Memory 13 */
1611     kXRDC2_Mem_MECC1_Region14       = XRDC2_MAKE_MEM(5, 14), /**< MRC5 Memory 14 */
1612     kXRDC2_Mem_MECC1_Region15       = XRDC2_MAKE_MEM(5, 15), /**< MRC5 Memory 15 */
1613     kXRDC2_Mem_MECC2_Region0        = XRDC2_MAKE_MEM(6, 0), /**< MRC6 Memory 0 */
1614     kXRDC2_Mem_MECC2_Region1        = XRDC2_MAKE_MEM(6, 1), /**< MRC6 Memory 1 */
1615     kXRDC2_Mem_MECC2_Region2        = XRDC2_MAKE_MEM(6, 2), /**< MRC6 Memory 2 */
1616     kXRDC2_Mem_MECC2_Region3        = XRDC2_MAKE_MEM(6, 3), /**< MRC6 Memory 3 */
1617     kXRDC2_Mem_MECC2_Region4        = XRDC2_MAKE_MEM(6, 4), /**< MRC6 Memory 4 */
1618     kXRDC2_Mem_MECC2_Region5        = XRDC2_MAKE_MEM(6, 5), /**< MRC6 Memory 5 */
1619     kXRDC2_Mem_MECC2_Region6        = XRDC2_MAKE_MEM(6, 6), /**< MRC6 Memory 6 */
1620     kXRDC2_Mem_MECC2_Region7        = XRDC2_MAKE_MEM(6, 7), /**< MRC6 Memory 7 */
1621     kXRDC2_Mem_MECC2_Region8        = XRDC2_MAKE_MEM(6, 8), /**< MRC6 Memory 8 */
1622     kXRDC2_Mem_MECC2_Region9        = XRDC2_MAKE_MEM(6, 9), /**< MRC6 Memory 9 */
1623     kXRDC2_Mem_MECC2_Region10       = XRDC2_MAKE_MEM(6, 10), /**< MRC6 Memory 10 */
1624     kXRDC2_Mem_MECC2_Region11       = XRDC2_MAKE_MEM(6, 11), /**< MRC6 Memory 11 */
1625     kXRDC2_Mem_MECC2_Region12       = XRDC2_MAKE_MEM(6, 12), /**< MRC6 Memory 12 */
1626     kXRDC2_Mem_MECC2_Region13       = XRDC2_MAKE_MEM(6, 13), /**< MRC6 Memory 13 */
1627     kXRDC2_Mem_MECC2_Region14       = XRDC2_MAKE_MEM(6, 14), /**< MRC6 Memory 14 */
1628     kXRDC2_Mem_MECC2_Region15       = XRDC2_MAKE_MEM(6, 15), /**< MRC6 Memory 15 */
1629     kXRDC2_Mem_SEMC_Region0         = XRDC2_MAKE_MEM(7, 0), /**< MRC7 Memory 0 */
1630     kXRDC2_Mem_SEMC_Region1         = XRDC2_MAKE_MEM(7, 1), /**< MRC7 Memory 1 */
1631     kXRDC2_Mem_SEMC_Region2         = XRDC2_MAKE_MEM(7, 2), /**< MRC7 Memory 2 */
1632     kXRDC2_Mem_SEMC_Region3         = XRDC2_MAKE_MEM(7, 3), /**< MRC7 Memory 3 */
1633     kXRDC2_Mem_SEMC_Region4         = XRDC2_MAKE_MEM(7, 4), /**< MRC7 Memory 4 */
1634     kXRDC2_Mem_SEMC_Region5         = XRDC2_MAKE_MEM(7, 5), /**< MRC7 Memory 5 */
1635     kXRDC2_Mem_SEMC_Region6         = XRDC2_MAKE_MEM(7, 6), /**< MRC7 Memory 6 */
1636     kXRDC2_Mem_SEMC_Region7         = XRDC2_MAKE_MEM(7, 7), /**< MRC7 Memory 7 */
1637     kXRDC2_Mem_SEMC_Region8         = XRDC2_MAKE_MEM(7, 8), /**< MRC7 Memory 8 */
1638     kXRDC2_Mem_SEMC_Region9         = XRDC2_MAKE_MEM(7, 9), /**< MRC7 Memory 9 */
1639     kXRDC2_Mem_SEMC_Region10        = XRDC2_MAKE_MEM(7, 10), /**< MRC7 Memory 10 */
1640     kXRDC2_Mem_SEMC_Region11        = XRDC2_MAKE_MEM(7, 11), /**< MRC7 Memory 11 */
1641     kXRDC2_Mem_SEMC_Region12        = XRDC2_MAKE_MEM(7, 12), /**< MRC7 Memory 12 */
1642     kXRDC2_Mem_SEMC_Region13        = XRDC2_MAKE_MEM(7, 13), /**< MRC7 Memory 13 */
1643     kXRDC2_Mem_SEMC_Region14        = XRDC2_MAKE_MEM(7, 14), /**< MRC7 Memory 14 */
1644     kXRDC2_Mem_SEMC_Region15        = XRDC2_MAKE_MEM(7, 15), /**< MRC7 Memory 15 */
1645 } xrdc2_mem_t;
1646 
1647 typedef enum _xrdc2_mem_slot
1648 {
1649     kXRDC2_MemSlot_GPV0             = 0U,          /**< GPV0 */
1650     kXRDC2_MemSlot_GPV1             = 1U,          /**< GPV1 */
1651     kXRDC2_MemSlot_GPV2             = 2U,          /**< GPV2 */
1652     kXRDC2_MemSlot_ROMCP            = 3U,          /**< ROMCP */
1653 } xrdc2_mem_slot_t;
1654 
1655 typedef enum _xrdc2_periph
1656 {
1657     kXRDC2_Periph_ACMP4             = XRDC2_MAKE_PERIPH(0, 108), /**< ACMP4 */
1658     kXRDC2_Periph_ACMP3             = XRDC2_MAKE_PERIPH(0, 107), /**< ACMP3 */
1659     kXRDC2_Periph_ACMP2             = XRDC2_MAKE_PERIPH(0, 106), /**< ACMP2 */
1660     kXRDC2_Periph_ACMP1             = XRDC2_MAKE_PERIPH(0, 105), /**< ACMP1 */
1661     kXRDC2_Periph_FLEXPWM4          = XRDC2_MAKE_PERIPH(0, 102), /**< FLEXPWM4 */
1662     kXRDC2_Periph_FLEXPWM3          = XRDC2_MAKE_PERIPH(0, 101), /**< FLEXPWM3 */
1663     kXRDC2_Periph_FLEXPWM2          = XRDC2_MAKE_PERIPH(0, 100), /**< FLEXPWM2 */
1664     kXRDC2_Periph_FLEXPWM1          = XRDC2_MAKE_PERIPH(0, 99 ), /**< FLEXPWM1 */
1665     kXRDC2_Periph_ENC4              = XRDC2_MAKE_PERIPH(0, 96 ), /**< ENC4 */
1666     kXRDC2_Periph_ENC3              = XRDC2_MAKE_PERIPH(0, 95 ), /**< ENC3 */
1667     kXRDC2_Periph_ENC2              = XRDC2_MAKE_PERIPH(0, 94 ), /**< ENC2 */
1668     kXRDC2_Periph_ENC1              = XRDC2_MAKE_PERIPH(0, 93 ), /**< ENC1 */
1669     kXRDC2_Periph_QTIMER4           = XRDC2_MAKE_PERIPH(0, 90 ), /**< QTIMER4 */
1670     kXRDC2_Periph_QTIMER3           = XRDC2_MAKE_PERIPH(0, 89 ), /**< QTIMER3 */
1671     kXRDC2_Periph_QTIMER2           = XRDC2_MAKE_PERIPH(0, 88 ), /**< QTIMER2 */
1672     kXRDC2_Periph_QTIMER1           = XRDC2_MAKE_PERIPH(0, 87 ), /**< QTIMER1 */
1673     kXRDC2_Periph_SIM2              = XRDC2_MAKE_PERIPH(0, 86 ), /**< SIM2 */
1674     kXRDC2_Periph_SIM1              = XRDC2_MAKE_PERIPH(0, 85 ), /**< SIM1 */
1675     kXRDC2_Periph_CCM_OBS           = XRDC2_MAKE_PERIPH(0, 84 ), /**< CCM_OBS */
1676     kXRDC2_Periph_GPIO6             = XRDC2_MAKE_PERIPH(0, 80 ), /**< GPIO6 */
1677     kXRDC2_Periph_GPIO5             = XRDC2_MAKE_PERIPH(0, 79 ), /**< GPIO5 */
1678     kXRDC2_Periph_GPIO4             = XRDC2_MAKE_PERIPH(0, 78 ), /**< GPIO4 */
1679     kXRDC2_Periph_GPIO3             = XRDC2_MAKE_PERIPH(0, 77 ), /**< GPIO3 */
1680     kXRDC2_Periph_GPIO2             = XRDC2_MAKE_PERIPH(0, 76 ), /**< GPIO2 */
1681     kXRDC2_Periph_GPIO1             = XRDC2_MAKE_PERIPH(0, 75 ), /**< GPIO1 */
1682     kXRDC2_Periph_LPSPI4            = XRDC2_MAKE_PERIPH(0, 72 ), /**< LPSPI4 */
1683     kXRDC2_Periph_LPSPI3            = XRDC2_MAKE_PERIPH(0, 71 ), /**< LPSPI3 */
1684     kXRDC2_Periph_LPSPI2            = XRDC2_MAKE_PERIPH(0, 70 ), /**< LPSPI2 */
1685     kXRDC2_Periph_LPSPI1            = XRDC2_MAKE_PERIPH(0, 69 ), /**< LPSPI1 */
1686     kXRDC2_Periph_LPI2C4            = XRDC2_MAKE_PERIPH(0, 68 ), /**< LPI2C4 */
1687     kXRDC2_Periph_LPI2C3            = XRDC2_MAKE_PERIPH(0, 67 ), /**< LPI2C3 */
1688     kXRDC2_Periph_LPI2C2            = XRDC2_MAKE_PERIPH(0, 66 ), /**< LPI2C2 */
1689     kXRDC2_Periph_LPI2C1            = XRDC2_MAKE_PERIPH(0, 65 ), /**< LPI2C1 */
1690     kXRDC2_Periph_GPT6              = XRDC2_MAKE_PERIPH(0, 64 ), /**< GPT6 */
1691     kXRDC2_Periph_GPT5              = XRDC2_MAKE_PERIPH(0, 63 ), /**< GPT5 */
1692     kXRDC2_Periph_GPT4              = XRDC2_MAKE_PERIPH(0, 62 ), /**< GPT4 */
1693     kXRDC2_Periph_GPT3              = XRDC2_MAKE_PERIPH(0, 61 ), /**< GPT3 */
1694     kXRDC2_Periph_GPT2              = XRDC2_MAKE_PERIPH(0, 60 ), /**< GPT2 */
1695     kXRDC2_Periph_GPT1              = XRDC2_MAKE_PERIPH(0, 59 ), /**< GPT1 */
1696     kXRDC2_Periph_IOMUXC            = XRDC2_MAKE_PERIPH(0, 58 ), /**< IOMUXC */
1697     kXRDC2_Periph_IOMUXC_GPR        = XRDC2_MAKE_PERIPH(0, 57 ), /**< IOMUXC_GPR */
1698     kXRDC2_Periph_KPP               = XRDC2_MAKE_PERIPH(0, 56 ), /**< KPP */
1699     kXRDC2_Periph_PIT1              = XRDC2_MAKE_PERIPH(0, 54 ), /**< PIT1 */
1700     kXRDC2_Periph_SEMC              = XRDC2_MAKE_PERIPH(0, 53 ), /**< SEMC */
1701     kXRDC2_Periph_FLEXSPI2          = XRDC2_MAKE_PERIPH(0, 52 ), /**< FLEXSPI2 */
1702     kXRDC2_Periph_FLEXSPI1          = XRDC2_MAKE_PERIPH(0, 51 ), /**< FLEXSPI1 */
1703     kXRDC2_Periph_CAN2              = XRDC2_MAKE_PERIPH(0, 50 ), /**< CAN2 */
1704     kXRDC2_Periph_CAN1              = XRDC2_MAKE_PERIPH(0, 49 ), /**< CAN1 */
1705     kXRDC2_Periph_AOI2              = XRDC2_MAKE_PERIPH(0, 47 ), /**< AOI2 */
1706     kXRDC2_Periph_AOI1              = XRDC2_MAKE_PERIPH(0, 46 ), /**< AOI1 */
1707     kXRDC2_Periph_FLEXIO2           = XRDC2_MAKE_PERIPH(0, 44 ), /**< FLEXIO2 */
1708     kXRDC2_Periph_FLEXIO1           = XRDC2_MAKE_PERIPH(0, 43 ), /**< FLEXIO1 */
1709     kXRDC2_Periph_LPUART10          = XRDC2_MAKE_PERIPH(0, 40 ), /**< LPUART10 */
1710     kXRDC2_Periph_LPUART9           = XRDC2_MAKE_PERIPH(0, 39 ), /**< LPUART9 */
1711     kXRDC2_Periph_LPUART8           = XRDC2_MAKE_PERIPH(0, 38 ), /**< LPUART8 */
1712     kXRDC2_Periph_LPUART7           = XRDC2_MAKE_PERIPH(0, 37 ), /**< LPUART7 */
1713     kXRDC2_Periph_LPUART6           = XRDC2_MAKE_PERIPH(0, 36 ), /**< LPUART6 */
1714     kXRDC2_Periph_LPUART5           = XRDC2_MAKE_PERIPH(0, 35 ), /**< LPUART5 */
1715     kXRDC2_Periph_LPUART4           = XRDC2_MAKE_PERIPH(0, 34 ), /**< LPUART4 */
1716     kXRDC2_Periph_LPUART3           = XRDC2_MAKE_PERIPH(0, 33 ), /**< LPUART3 */
1717     kXRDC2_Periph_LPUART2           = XRDC2_MAKE_PERIPH(0, 32 ), /**< LPUART2 */
1718     kXRDC2_Periph_LPUART1           = XRDC2_MAKE_PERIPH(0, 31 ), /**< LPUART1 */
1719     kXRDC2_Periph_DMA_CH_MUX        = XRDC2_MAKE_PERIPH(0, 29 ), /**< DMA_CH_MUX */
1720     kXRDC2_Periph_EDMA              = XRDC2_MAKE_PERIPH(0, 28 ), /**< EDMA */
1721     kXRDC2_Periph_IEE               = XRDC2_MAKE_PERIPH(0, 27 ), /**< IEE */
1722     kXRDC2_Periph_DAC               = XRDC2_MAKE_PERIPH(0, 25 ), /**< DAC */
1723     kXRDC2_Periph_TSC_DIG           = XRDC2_MAKE_PERIPH(0, 23 ), /**< TSC_DIG */
1724     kXRDC2_Periph_ADC2              = XRDC2_MAKE_PERIPH(0, 21 ), /**< ADC2 */
1725     kXRDC2_Periph_ADC1              = XRDC2_MAKE_PERIPH(0, 20 ), /**< ADC1 */
1726     kXRDC2_Periph_ADC_ETC           = XRDC2_MAKE_PERIPH(0, 18 ), /**< ADC_ETC */
1727     kXRDC2_Periph_XBAR3             = XRDC2_MAKE_PERIPH(0, 17 ), /**< XBAR3 */
1728     kXRDC2_Periph_XBAR2             = XRDC2_MAKE_PERIPH(0, 16 ), /**< XBAR2 */
1729     kXRDC2_Periph_XBAR1             = XRDC2_MAKE_PERIPH(0, 15 ), /**< XBAR1 */
1730     kXRDC2_Periph_WDOG3             = XRDC2_MAKE_PERIPH(0, 14 ), /**< WDOG3 */
1731     kXRDC2_Periph_WDOG2             = XRDC2_MAKE_PERIPH(0, 13 ), /**< WDOG2 */
1732     kXRDC2_Periph_WDOG1             = XRDC2_MAKE_PERIPH(0, 12 ), /**< WDOG1 */
1733     kXRDC2_Periph_EWM               = XRDC2_MAKE_PERIPH(0, 11 ), /**< EWM */
1734     kXRDC2_Periph_FLEXRAM           = XRDC2_MAKE_PERIPH(0, 10 ), /**< FLEXRAM */
1735     kXRDC2_Periph_XECC_SEMC         = XRDC2_MAKE_PERIPH(0, 9  ), /**< XECC_SEMC */
1736     kXRDC2_Periph_XECC_FLEXSPI2     = XRDC2_MAKE_PERIPH(0, 8  ), /**< XECC_FLEXSPI2 */
1737     kXRDC2_Periph_XECC_FLEXSPI1     = XRDC2_MAKE_PERIPH(0, 7  ), /**< XECC_FLEXSPI1 */
1738     kXRDC2_Periph_MECC2             = XRDC2_MAKE_PERIPH(0, 6  ), /**< MECC2 */
1739     kXRDC2_Periph_MECC1             = XRDC2_MAKE_PERIPH(0, 5  ), /**< MECC1 */
1740     kXRDC2_Periph_MTR               = XRDC2_MAKE_PERIPH(0, 4  ), /**< MTR */
1741     kXRDC2_Periph_SFA               = XRDC2_MAKE_PERIPH(0, 3  ), /**< SFA */
1742     kXRDC2_Periph_CAAM_DEBUG_3      = XRDC2_MAKE_PERIPH(1, 51 ), /**< CAAM_DEBUG_3 */
1743     kXRDC2_Periph_CAAM_DEBUG_2      = XRDC2_MAKE_PERIPH(1, 50 ), /**< CAAM_DEBUG_2 */
1744     kXRDC2_Periph_CAAM_DEBUG_1      = XRDC2_MAKE_PERIPH(1, 49 ), /**< CAAM_DEBUG_1 */
1745     kXRDC2_Periph_CAAM_DEBUG_0      = XRDC2_MAKE_PERIPH(1, 48 ), /**< CAAM_DEBUG_0 */
1746     kXRDC2_Periph_CAAM_RTIC_3       = XRDC2_MAKE_PERIPH(1, 43 ), /**< CAAM_RTIC_3 */
1747     kXRDC2_Periph_CAAM_RTIC_2       = XRDC2_MAKE_PERIPH(1, 42 ), /**< CAAM_RTIC_2 */
1748     kXRDC2_Periph_CAAM_RTIC_1       = XRDC2_MAKE_PERIPH(1, 41 ), /**< CAAM_RTIC_1 */
1749     kXRDC2_Periph_CAAM_RTIC_0       = XRDC2_MAKE_PERIPH(1, 40 ), /**< CAAM_RTIC_0 */
1750     kXRDC2_Periph_CAAM_JR3_3        = XRDC2_MAKE_PERIPH(1, 35 ), /**< CAAM_JR3_3 */
1751     kXRDC2_Periph_CAAM_JR3_2        = XRDC2_MAKE_PERIPH(1, 34 ), /**< CAAM_JR3_2 */
1752     kXRDC2_Periph_CAAM_JR3_1        = XRDC2_MAKE_PERIPH(1, 33 ), /**< CAAM_JR3_1 */
1753     kXRDC2_Periph_CAAM_JR3_0        = XRDC2_MAKE_PERIPH(1, 32 ), /**< CAAM_JR3_0 */
1754     kXRDC2_Periph_CAAM_JR2_3        = XRDC2_MAKE_PERIPH(1, 31 ), /**< CAAM_JR2_3 */
1755     kXRDC2_Periph_CAAM_JR2_2        = XRDC2_MAKE_PERIPH(1, 30 ), /**< CAAM_JR2_2 */
1756     kXRDC2_Periph_CAAM_JR2_1        = XRDC2_MAKE_PERIPH(1, 29 ), /**< CAAM_JR2_1 */
1757     kXRDC2_Periph_CAAM_JR2_0        = XRDC2_MAKE_PERIPH(1, 28 ), /**< CAAM_JR2_0 */
1758     kXRDC2_Periph_CAAM_JR1_3        = XRDC2_MAKE_PERIPH(1, 27 ), /**< CAAM_JR1_3 */
1759     kXRDC2_Periph_CAAM_JR1_2        = XRDC2_MAKE_PERIPH(1, 26 ), /**< CAAM_JR1_2 */
1760     kXRDC2_Periph_CAAM_JR1_1        = XRDC2_MAKE_PERIPH(1, 25 ), /**< CAAM_JR1_1 */
1761     kXRDC2_Periph_CAAM_JR1_0        = XRDC2_MAKE_PERIPH(1, 24 ), /**< CAAM_JR1_0 */
1762     kXRDC2_Periph_CAAM_JR0_3        = XRDC2_MAKE_PERIPH(1, 23 ), /**< CAAM_JR0_3 */
1763     kXRDC2_Periph_CAAM_JR0_2        = XRDC2_MAKE_PERIPH(1, 22 ), /**< CAAM_JR0_2 */
1764     kXRDC2_Periph_CAAM_JR0_1        = XRDC2_MAKE_PERIPH(1, 21 ), /**< CAAM_JR0_1 */
1765     kXRDC2_Periph_CAAM_JR0_0        = XRDC2_MAKE_PERIPH(1, 20 ), /**< CAAM_JR0_0 */
1766     kXRDC2_Periph_CAAM_GENERAL_3    = XRDC2_MAKE_PERIPH(1, 19 ), /**< CAAM_GENERAL_3 */
1767     kXRDC2_Periph_CAAM_GENERAL_2    = XRDC2_MAKE_PERIPH(1, 18 ), /**< CAAM_GENERAL_2 */
1768     kXRDC2_Periph_CAAM_GENERAL_1    = XRDC2_MAKE_PERIPH(1, 17 ), /**< CAAM_GENERAL_1 */
1769     kXRDC2_Periph_CAAM_GENERAL_0    = XRDC2_MAKE_PERIPH(1, 16 ), /**< CAAM_GENERAL_0 */
1770     kXRDC2_Periph_ENET_QOS          = XRDC2_MAKE_PERIPH(1, 15 ), /**< ENET_QOS */
1771     kXRDC2_Periph_USBPHY2           = XRDC2_MAKE_PERIPH(1, 14 ), /**< USBPHY2 */
1772     kXRDC2_Periph_USBPHY1           = XRDC2_MAKE_PERIPH(1, 13 ), /**< USBPHY1 */
1773     kXRDC2_Periph_USB_OTG           = XRDC2_MAKE_PERIPH(1, 12 ), /**< USB_OTG */
1774     kXRDC2_Periph_USB_OTG2          = XRDC2_MAKE_PERIPH(1, 11 ), /**< USB_OTG2 */
1775     kXRDC2_Periph_USB_PL301         = XRDC2_MAKE_PERIPH(1, 10 ), /**< USB_PL301 */
1776     kXRDC2_Periph_ENET              = XRDC2_MAKE_PERIPH(1, 9  ), /**< ENET */
1777     kXRDC2_Periph_ENET_1G           = XRDC2_MAKE_PERIPH(1, 8  ), /**< ENET_1G */
1778     kXRDC2_Periph_USDHC2            = XRDC2_MAKE_PERIPH(1, 7  ), /**< USDHC2 */
1779     kXRDC2_Periph_USDHC1            = XRDC2_MAKE_PERIPH(1, 6  ), /**< USDHC1 */
1780     kXRDC2_Periph_ASRC              = XRDC2_MAKE_PERIPH(1, 5  ), /**< ASRC */
1781     kXRDC2_Periph_SAI3              = XRDC2_MAKE_PERIPH(1, 3  ), /**< SAI3 */
1782     kXRDC2_Periph_SAI2              = XRDC2_MAKE_PERIPH(1, 2  ), /**< SAI2 */
1783     kXRDC2_Periph_SAI1              = XRDC2_MAKE_PERIPH(1, 1  ), /**< SAI1 */
1784     kXRDC2_Periph_SPDIF             = XRDC2_MAKE_PERIPH(1, 0  ), /**< SPDIF */
1785     kXRDC2_Periph_VIDEO_MUX         = XRDC2_MAKE_PERIPH(2, 6  ), /**< VIDEO_MUX */
1786     kXRDC2_Periph_PXP               = XRDC2_MAKE_PERIPH(2, 5  ), /**< PXP */
1787     kXRDC2_Periph_MIPI_CSI          = XRDC2_MAKE_PERIPH(2, 4  ), /**< MIPI_CSI */
1788     kXRDC2_Periph_MIPI_DSI          = XRDC2_MAKE_PERIPH(2, 3  ), /**< MIPI_DSI */
1789     kXRDC2_Periph_LCDIFV2           = XRDC2_MAKE_PERIPH(2, 2  ), /**< LCDIFV2 */
1790     kXRDC2_Periph_LCDIF             = XRDC2_MAKE_PERIPH(2, 1  ), /**< LCDIF */
1791     kXRDC2_Periph_CSI               = XRDC2_MAKE_PERIPH(2, 0  ), /**< CSI */
1792     kXRDC2_Periph_XRDC2_MGR_M7_3    = XRDC2_MAKE_PERIPH(3, 59 ), /**< XRDC2_MGR_M7_3 */
1793     kXRDC2_Periph_XRDC2_MGR_M7_2    = XRDC2_MAKE_PERIPH(3, 58 ), /**< XRDC2_MGR_M7_2 */
1794     kXRDC2_Periph_XRDC2_MGR_M7_1    = XRDC2_MAKE_PERIPH(3, 57 ), /**< XRDC2_MGR_M7_1 */
1795     kXRDC2_Periph_XRDC2_MGR_M7_0    = XRDC2_MAKE_PERIPH(3, 56 ), /**< XRDC2_MGR_M7_0 */
1796     kXRDC2_Periph_XRDC2_MGR_M4_3    = XRDC2_MAKE_PERIPH(3, 55 ), /**< XRDC2_MGR_M4_3 */
1797     kXRDC2_Periph_XRDC2_MGR_M4_2    = XRDC2_MAKE_PERIPH(3, 54 ), /**< XRDC2_MGR_M4_2 */
1798     kXRDC2_Periph_XRDC2_MGR_M4_1    = XRDC2_MAKE_PERIPH(3, 53 ), /**< XRDC2_MGR_M4_1 */
1799     kXRDC2_Periph_XRDC2_MGR_M4_0    = XRDC2_MAKE_PERIPH(3, 52 ), /**< XRDC2_MGR_M4_0 */
1800     kXRDC2_Periph_SEMA2             = XRDC2_MAKE_PERIPH(3, 51 ), /**< SEMA2 */
1801     kXRDC2_Periph_SEMA_HS           = XRDC2_MAKE_PERIPH(3, 50 ), /**< SEMA_HS */
1802     kXRDC2_Periph_CCM_1             = XRDC2_MAKE_PERIPH(3, 49 ), /**< CCM_1 */
1803     kXRDC2_Periph_CCM_0             = XRDC2_MAKE_PERIPH(3, 48 ), /**< CCM_0 */
1804     kXRDC2_Periph_SSARC_LP          = XRDC2_MAKE_PERIPH(3, 46 ), /**< SSARC_LP */
1805     kXRDC2_Periph_SSARC_HP          = XRDC2_MAKE_PERIPH(3, 45 ), /**< SSARC_HP */
1806     kXRDC2_Periph_PIT2              = XRDC2_MAKE_PERIPH(3, 44 ), /**< PIT2 */
1807     kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ), /**< OCOTP_CTRL_WRAPPER */
1808     kXRDC2_Periph_DCDC              = XRDC2_MAKE_PERIPH(3, 42 ), /**< DCDC */
1809     kXRDC2_Periph_ROMCP             = XRDC2_MAKE_PERIPH(3, 41 ), /**< ROMCP */
1810     kXRDC2_Periph_GPIO13            = XRDC2_MAKE_PERIPH(3, 40 ), /**< GPIO13 */
1811     kXRDC2_Periph_SNVS_SRAM         = XRDC2_MAKE_PERIPH(3, 39 ), /**< SNVS_SRAM */
1812     kXRDC2_Periph_IOMUXC_SNVS_GPR   = XRDC2_MAKE_PERIPH(3, 38 ), /**< IOMUXC_SNVS_GPR */
1813     kXRDC2_Periph_IOMUXC_SNVS       = XRDC2_MAKE_PERIPH(3, 37 ), /**< IOMUXC_SNVS */
1814     kXRDC2_Periph_SNVS_HP_WRAPPER   = XRDC2_MAKE_PERIPH(3, 36 ), /**< SNVS_HP_WRAPPER */
1815     kXRDC2_Periph_PGMC              = XRDC2_MAKE_PERIPH(3, 34 ), /**< PGMC */
1816     kXRDC2_Periph_ANATOP            = XRDC2_MAKE_PERIPH(3, 33 ), /**< ANATOP */
1817     kXRDC2_Periph_KEY_MANAGER       = XRDC2_MAKE_PERIPH(3, 32 ), /**< KEY_MANAGER */
1818     kXRDC2_Periph_RDC               = XRDC2_MAKE_PERIPH(3, 30 ), /**< RDC */
1819     kXRDC2_Periph_GPIO12            = XRDC2_MAKE_PERIPH(3, 28 ), /**< GPIO12 */
1820     kXRDC2_Periph_GPIO11            = XRDC2_MAKE_PERIPH(3, 27 ), /**< GPIO11 */
1821     kXRDC2_Periph_GPIO10            = XRDC2_MAKE_PERIPH(3, 26 ), /**< GPIO10 */
1822     kXRDC2_Periph_GPIO9             = XRDC2_MAKE_PERIPH(3, 25 ), /**< GPIO9 */
1823     kXRDC2_Periph_GPIO8             = XRDC2_MAKE_PERIPH(3, 24 ), /**< GPIO8 */
1824     kXRDC2_Periph_GPIO7             = XRDC2_MAKE_PERIPH(3, 23 ), /**< GPIO7 */
1825     kXRDC2_Periph_MU_B              = XRDC2_MAKE_PERIPH(3, 19 ), /**< MU_B */
1826     kXRDC2_Periph_MU_A              = XRDC2_MAKE_PERIPH(3, 18 ), /**< MU_A */
1827     kXRDC2_Periph_SEMA1             = XRDC2_MAKE_PERIPH(3, 17 ), /**< SEMA1 */
1828     kXRDC2_Periph_SAI4              = XRDC2_MAKE_PERIPH(3, 16 ), /**< SAI4 */
1829     kXRDC2_Periph_CAN3              = XRDC2_MAKE_PERIPH(3, 15 ), /**< CAN3 */
1830     kXRDC2_Periph_LPI2C6            = XRDC2_MAKE_PERIPH(3, 14 ), /**< LPI2C6 */
1831     kXRDC2_Periph_LPI2C5            = XRDC2_MAKE_PERIPH(3, 13 ), /**< LPI2C5 */
1832     kXRDC2_Periph_LPSPI6            = XRDC2_MAKE_PERIPH(3, 12 ), /**< LPSPI6 */
1833     kXRDC2_Periph_LPSPI5            = XRDC2_MAKE_PERIPH(3, 11 ), /**< LPSPI5 */
1834     kXRDC2_Periph_LPUART12          = XRDC2_MAKE_PERIPH(3, 10 ), /**< LPUART12 */
1835     kXRDC2_Periph_LPUART11          = XRDC2_MAKE_PERIPH(3, 9  ), /**< LPUART11 */
1836     kXRDC2_Periph_MIC               = XRDC2_MAKE_PERIPH(3, 8  ), /**< MIC */
1837     kXRDC2_Periph_DMA_CH_MUX_LPSR   = XRDC2_MAKE_PERIPH(3, 6  ), /**< DMA_CH_MUX_LPSR */
1838     kXRDC2_Periph_EDMA_LPSR         = XRDC2_MAKE_PERIPH(3, 5  ), /**< EDMA_LPSR */
1839     kXRDC2_Periph_WDOG4             = XRDC2_MAKE_PERIPH(3, 4  ), /**< WDOG4 */
1840     kXRDC2_Periph_IOMUXC_LPSR_GPR   = XRDC2_MAKE_PERIPH(3, 3  ), /**< IOMUXC_LPSR_GPR */
1841     kXRDC2_Periph_IOMUXC_LPSR       = XRDC2_MAKE_PERIPH(3, 2  ), /**< IOMUXC_LPSR */
1842     kXRDC2_Periph_SRC               = XRDC2_MAKE_PERIPH(3, 1  ), /**< SRC */
1843     kXRDC2_Periph_GPC               = XRDC2_MAKE_PERIPH(3, 0  ), /**< GPC */
1844     kXRDC2_Periph_GPU               = XRDC2_MAKE_PERIPH(4, 0  ), /**< GPU */
1845 } xrdc2_periph_t;
1846 
1847 /* @} */
1848 
1849 /*!
1850  * @addtogroup iomuxc_pads
1851  * @{ */
1852 
1853 /*******************************************************************************
1854  * Definitions
1855 *******************************************************************************/
1856 
1857 /*!
1858  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
1859  *
1860  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
1861  */
1862 typedef enum _iomuxc_sw_mux_ctl_pad
1863 {
1864     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1865     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1866     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1867     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1868     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1869     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1870     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1871     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1872     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1873     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1874     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1875     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1876     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1877     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1878     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1879     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1880     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1881     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1882     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1883     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1884     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1885     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1886     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1887     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1888     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1889     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1890     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1891     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1892     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1893     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1894     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1895     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1896     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1897     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1898     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1899     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1900     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1901     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1902     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1903     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1904     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1905     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1906     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1907     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1908     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1909     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1910     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1911     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1912     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1913     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1914     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1915     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1916     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1917     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1918     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1919     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1920     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1921     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1922     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1923     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1924     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1925     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1926     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1927     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1928     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1929     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1930     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1931     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1932     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1933     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1934     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1935     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1936     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1937     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1938     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1939     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1940     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1941     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1942     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1943     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1944     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1945     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1946     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1947     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1948     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1949     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1950     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1951     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1952     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1953     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1954     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1955     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1956     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1957     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1958     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1959     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1960     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1961     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1962     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1963     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1964     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1965     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1966     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1967     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1968     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1969     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1970     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1971     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1972     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1973     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1974     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1975     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1976     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1977     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1978     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1979     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1980     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1981     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
1982     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
1983     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
1984     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
1985     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
1986     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
1987     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
1988     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
1989     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
1990     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
1991     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
1992     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
1993     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
1994     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
1995     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
1996     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
1997     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
1998     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
1999     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
2000     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
2001     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
2002     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
2003     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
2004     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
2005     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_MUX_CTL_PAD index */
2006     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_MUX_CTL_PAD index */
2007     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_MUX_CTL_PAD index */
2008     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_MUX_CTL_PAD index */
2009 } iomuxc_sw_mux_ctl_pad_t;
2010 
2011 /* @} */
2012 
2013 /*!
2014  * @addtogroup iomuxc_pads
2015  * @{ */
2016 
2017 /*******************************************************************************
2018  * Definitions
2019 *******************************************************************************/
2020 
2021 /*!
2022  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
2023  *
2024  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
2025  */
2026 typedef enum _iomuxc_sw_pad_ctl_pad
2027 {
2028     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2029     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2030     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2031     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2032     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2033     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2034     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2035     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2036     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2037     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2038     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2039     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2040     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2041     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2042     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2043     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2044     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2045     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2046     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2047     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2048     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2049     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2050     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2051     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2052     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2053     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2054     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2055     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2056     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2057     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2058     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2059     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2060     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2061     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2062     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2063     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2064     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2065     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2066     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2067     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2068     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2069     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2070     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2071     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2072     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2073     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2074     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2075     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2076     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2077     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2078     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2079     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2080     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2081     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2082     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2083     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2084     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2085     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2086     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2087     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2088     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2089     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2090     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2091     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2092     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2093     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2094     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2095     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2096     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2097     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2098     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2099     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2100     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2101     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2102     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2103     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2104     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2105     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2106     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2107     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2108     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2109     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2110     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2111     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2112     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2113     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2114     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2115     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2116     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2117     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2118     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2119     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2120     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2121     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2122     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2123     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2124     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2125     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2126     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2127     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2128     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2129     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2130     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2131     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2132     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2133     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2134     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2135     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2136     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2137     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2138     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2139     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2140     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2141     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2142     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2143     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2144     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2145     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
2146     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
2147     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
2148     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
2149     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
2150     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
2151     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
2152     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
2153     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
2154     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
2155     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
2156     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
2157     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
2158     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
2159     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
2160     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
2161     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
2162     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
2163     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
2164     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
2165     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
2166     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
2167     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
2168     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
2169     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
2170     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
2171     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
2172     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
2173 } iomuxc_sw_pad_ctl_pad_t;
2174 
2175 /* @} */
2176 
2177 /*!
2178  * @brief Enumeration for the IOMUXC select input
2179  *
2180  * Defines the enumeration for the IOMUXC select input collections.
2181  */
2182 typedef enum _iomuxc_select_input
2183 {
2184     kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U,         /**< IOMUXC select input index */
2185     kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U,         /**< IOMUXC select input index */
2186     kIOMUXC_CCM_ENET_QOS_REF_CLK_SELECT_INPUT = 2U, /**< IOMUXC select input index */
2187     kIOMUXC_CCM_ENET_QOS_TX_CLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
2188     kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U,   /**< IOMUXC select input index */
2189     kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U,      /**< IOMUXC select input index */
2190     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U,  /**< IOMUXC select input index */
2191     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U,  /**< IOMUXC select input index */
2192     kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U,      /**< IOMUXC select input index */
2193     kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U,     /**< IOMUXC select input index */
2194     kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U,    /**< IOMUXC select input index */
2195     kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U, /**< IOMUXC select input index */
2196     kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U,  /**< IOMUXC select input index */
2197     kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
2198     kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U, /**< IOMUXC select input index */
2199     kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U, /**< IOMUXC select input index */
2200     kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U, /**< IOMUXC select input index */
2201     kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U, /**< IOMUXC select input index */
2202     kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U,  /**< IOMUXC select input index */
2203     kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
2204     kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U, /**< IOMUXC select input index */
2205     kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 21U, /**< IOMUXC select input index */
2206     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 = 22U, /**< IOMUXC select input index */
2207     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 = 23U, /**< IOMUXC select input index */
2208     kIOMUXC_ENET_QOS_PHY_RXDV_I_SELECT_INPUT = 24U, /**< IOMUXC select input index */
2209     kIOMUXC_ENET_QOS_PHY_RXER_I_SELECT_INPUT = 25U, /**< IOMUXC select input index */
2210     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U,    /**< IOMUXC select input index */
2211     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U,    /**< IOMUXC select input index */
2212     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U,    /**< IOMUXC select input index */
2213     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U,    /**< IOMUXC select input index */
2214     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U,    /**< IOMUXC select input index */
2215     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U,    /**< IOMUXC select input index */
2216     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U,    /**< IOMUXC select input index */
2217     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U,    /**< IOMUXC select input index */
2218     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U,    /**< IOMUXC select input index */
2219     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U,    /**< IOMUXC select input index */
2220     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U,    /**< IOMUXC select input index */
2221     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U,    /**< IOMUXC select input index */
2222     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U,    /**< IOMUXC select input index */
2223     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U,    /**< IOMUXC select input index */
2224     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U,    /**< IOMUXC select input index */
2225     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U,    /**< IOMUXC select input index */
2226     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U,    /**< IOMUXC select input index */
2227     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U,    /**< IOMUXC select input index */
2228     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U,    /**< IOMUXC select input index */
2229     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U,    /**< IOMUXC select input index */
2230     kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U,  /**< IOMUXC select input index */
2231     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U, /**< IOMUXC select input index */
2232     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U, /**< IOMUXC select input index */
2233     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U, /**< IOMUXC select input index */
2234     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U, /**< IOMUXC select input index */
2235     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U, /**< IOMUXC select input index */
2236     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U, /**< IOMUXC select input index */
2237     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U, /**< IOMUXC select input index */
2238     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U, /**< IOMUXC select input index */
2239     kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U,  /**< IOMUXC select input index */
2240     kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U,  /**< IOMUXC select input index */
2241     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U, /**< IOMUXC select input index */
2242     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U, /**< IOMUXC select input index */
2243     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U, /**< IOMUXC select input index */
2244     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U, /**< IOMUXC select input index */
2245     kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U,  /**< IOMUXC select input index */
2246     kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U,        /**< IOMUXC select input index */
2247     kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U,        /**< IOMUXC select input index */
2248     kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U,         /**< IOMUXC select input index */
2249     kIOMUXC_KPP_COL_SELECT_INPUT_6  = 65U,         /**< IOMUXC select input index */
2250     kIOMUXC_KPP_COL_SELECT_INPUT_7  = 66U,         /**< IOMUXC select input index */
2251     kIOMUXC_KPP_ROW_SELECT_INPUT_6  = 67U,         /**< IOMUXC select input index */
2252     kIOMUXC_KPP_ROW_SELECT_INPUT_7  = 68U,         /**< IOMUXC select input index */
2253     kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U,   /**< IOMUXC select input index */
2254     kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U,   /**< IOMUXC select input index */
2255     kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U,   /**< IOMUXC select input index */
2256     kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U,   /**< IOMUXC select input index */
2257     kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U,   /**< IOMUXC select input index */
2258     kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U,   /**< IOMUXC select input index */
2259     kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U,   /**< IOMUXC select input index */
2260     kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U,   /**< IOMUXC select input index */
2261     kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U, /**< IOMUXC select input index */
2262     kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U,   /**< IOMUXC select input index */
2263     kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U,   /**< IOMUXC select input index */
2264     kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U,   /**< IOMUXC select input index */
2265     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U, /**< IOMUXC select input index */
2266     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U, /**< IOMUXC select input index */
2267     kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U,   /**< IOMUXC select input index */
2268     kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U,   /**< IOMUXC select input index */
2269     kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U,   /**< IOMUXC select input index */
2270     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U, /**< IOMUXC select input index */
2271     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U, /**< IOMUXC select input index */
2272     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U, /**< IOMUXC select input index */
2273     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U, /**< IOMUXC select input index */
2274     kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U,   /**< IOMUXC select input index */
2275     kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U,   /**< IOMUXC select input index */
2276     kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U,   /**< IOMUXC select input index */
2277     kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U, /**< IOMUXC select input index */
2278     kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U,   /**< IOMUXC select input index */
2279     kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U,   /**< IOMUXC select input index */
2280     kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U,   /**< IOMUXC select input index */
2281     kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U, /**< IOMUXC select input index */
2282     kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U, /**< IOMUXC select input index */
2283     kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U, /**< IOMUXC select input index */
2284     kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U, /**< IOMUXC select input index */
2285     kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U, /**< IOMUXC select input index */
2286     kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U, /**< IOMUXC select input index */
2287     kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U, /**< IOMUXC select input index */
2288     kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U, /**< IOMUXC select input index */
2289     kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U, /**< IOMUXC select input index */
2290     kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U, /**< IOMUXC select input index */
2291     kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U, /**< IOMUXC select input index */
2292     kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U, /**< IOMUXC select input index */
2293     kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U, /**< IOMUXC select input index */
2294     kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U, /**< IOMUXC select input index */
2295     kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U, /**< IOMUXC select input index */
2296     kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U, /**< IOMUXC select input index */
2297     kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U, /**< IOMUXC select input index */
2298     kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U, /**< IOMUXC select input index */
2299     kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U, /**< IOMUXC select input index */
2300     kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U, /**< IOMUXC select input index */
2301     kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U, /**< IOMUXC select input index */
2302     kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U,   /**< IOMUXC select input index */
2303     kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U, /**< IOMUXC select input index */
2304     kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U,   /**< IOMUXC select input index */
2305     kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U,   /**< IOMUXC select input index */
2306     kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U,   /**< IOMUXC select input index */
2307     kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U,       /**< IOMUXC select input index */
2308     kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U, /**< IOMUXC select input index */
2309     kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U, /**< IOMUXC select input index */
2310     kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U,       /**< IOMUXC select input index */
2311     kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U, /**< IOMUXC select input index */
2312     kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U, /**< IOMUXC select input index */
2313     kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U,   /**< IOMUXC select input index */
2314     kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U,       /**< IOMUXC select input index */
2315     kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U,        /**< IOMUXC select input index */
2316     kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U,    /**< IOMUXC select input index */
2317     kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U,    /**< IOMUXC select input index */
2318     kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U, /**< IOMUXC select input index */
2319     kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U,  /**< IOMUXC select input index */
2320     kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U, /**< IOMUXC select input index */
2321     kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U,  /**< IOMUXC select input index */
2322     kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U,       /**< IOMUXC select input index */
2323     kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U,       /**< IOMUXC select input index */
2324     kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U,       /**< IOMUXC select input index */
2325     kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U,       /**< IOMUXC select input index */
2326     kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U,       /**< IOMUXC select input index */
2327     kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U,       /**< IOMUXC select input index */
2328     kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U,       /**< IOMUXC select input index */
2329     kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U,       /**< IOMUXC select input index */
2330     kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U,       /**< IOMUXC select input index */
2331     kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U,       /**< IOMUXC select input index */
2332     kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U,       /**< IOMUXC select input index */
2333     kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U,       /**< IOMUXC select input index */
2334     kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U,       /**< IOMUXC select input index */
2335     kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U,       /**< IOMUXC select input index */
2336     kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U,       /**< IOMUXC select input index */
2337     kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U,       /**< IOMUXC select input index */
2338 } iomuxc_select_input_t;
2339 
2340 
2341 /*!
2342  * @}
2343  */ /* end of group Mapping_Information */
2344 
2345 
2346 /* ----------------------------------------------------------------------------
2347    -- Device Peripheral Access Layer
2348    ---------------------------------------------------------------------------- */
2349 
2350 /*!
2351  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
2352  * @{
2353  */
2354 
2355 
2356 /*
2357 ** Start of section using anonymous unions
2358 */
2359 
2360 #if defined(__ARMCC_VERSION)
2361   #if (__ARMCC_VERSION >= 6010050)
2362     #pragma clang diagnostic push
2363   #else
2364     #pragma push
2365     #pragma anon_unions
2366   #endif
2367 #elif defined(__CWCC__)
2368   #pragma push
2369   #pragma cpp_extensions on
2370 #elif defined(__GNUC__)
2371   /* anonymous unions are enabled by default */
2372 #elif defined(__IAR_SYSTEMS_ICC__)
2373   #pragma language=extended
2374 #else
2375   #error Not supported compiler type
2376 #endif
2377 
2378 /* ----------------------------------------------------------------------------
2379    -- ADC Peripheral Access Layer
2380    ---------------------------------------------------------------------------- */
2381 
2382 /*!
2383  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
2384  * @{
2385  */
2386 
2387 /** ADC - Register Layout Typedef */
2388 typedef struct {
2389   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
2390   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
2391        uint8_t RESERVED_0[8];
2392   __IO uint32_t CTRL;                              /**< LPADC Control Register, offset: 0x10 */
2393   __IO uint32_t STAT;                              /**< LPADC Status Register, offset: 0x14 */
2394   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
2395   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
2396   __IO uint32_t CFG;                               /**< LPADC Configuration Register, offset: 0x20 */
2397   __IO uint32_t PAUSE;                             /**< LPADC Pause Register, offset: 0x24 */
2398        uint8_t RESERVED_1[8];
2399   __IO uint32_t FCTRL;                             /**< LPADC FIFO Control Register, offset: 0x30 */
2400   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
2401        uint8_t RESERVED_2[136];
2402   __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
2403        uint8_t RESERVED_3[32];
2404   struct {                                         /* offset: 0x100, array step: 0x8 */
2405     __IO uint32_t CMDL;                              /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
2406     __IO uint32_t CMDH;                              /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
2407   } CMD[15];
2408        uint8_t RESERVED_4[136];
2409   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
2410        uint8_t RESERVED_5[240];
2411   __I  uint32_t RESFIFO;                           /**< LPADC Data Result FIFO Register, offset: 0x300 */
2412 } ADC_Type;
2413 
2414 /* ----------------------------------------------------------------------------
2415    -- ADC Register Masks
2416    ---------------------------------------------------------------------------- */
2417 
2418 /*!
2419  * @addtogroup ADC_Register_Masks ADC Register Masks
2420  * @{
2421  */
2422 
2423 /*! @name VERID - Version ID Register */
2424 /*! @{ */
2425 
2426 #define ADC_VERID_RES_MASK                       (0x1U)
2427 #define ADC_VERID_RES_SHIFT                      (0U)
2428 /*! RES - Resolution
2429  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
2430  *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
2431  */
2432 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
2433 
2434 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
2435 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
2436 /*! DIFFEN - Differential Supported
2437  *  0b0..Differential operation not supported.
2438  *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
2439  */
2440 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
2441 
2442 #define ADC_VERID_MVI_MASK                       (0x8U)
2443 #define ADC_VERID_MVI_SHIFT                      (3U)
2444 /*! MVI - Multi Vref Implemented
2445  *  0b0..Single voltage reference input supported.
2446  *  0b1..Multiple voltage reference inputs supported.
2447  */
2448 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
2449 
2450 #define ADC_VERID_CSW_MASK                       (0x70U)
2451 #define ADC_VERID_CSW_SHIFT                      (4U)
2452 /*! CSW - Channel Scale Width
2453  *  0b000..Channel scaling not supported.
2454  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
2455  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
2456  */
2457 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
2458 
2459 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
2460 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
2461 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
2462  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
2463  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
2464  */
2465 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
2466 
2467 #define ADC_VERID_IADCKI_MASK                    (0x200U)
2468 #define ADC_VERID_IADCKI_SHIFT                   (9U)
2469 /*! IADCKI - Internal LPADC Clock implemented
2470  *  0b0..Internal clock source not implemented.
2471  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
2472  */
2473 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
2474 
2475 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
2476 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
2477 /*! CALOFSI - Calibration Offset Function Implemented
2478  *  0b0..Offset calibration and offset trimming not implemented.
2479  *  0b1..Offset calibration and offset trimming implemented.
2480  */
2481 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
2482 
2483 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
2484 #define ADC_VERID_MINOR_SHIFT                    (16U)
2485 /*! MINOR - Minor Version Number
2486  */
2487 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
2488 
2489 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
2490 #define ADC_VERID_MAJOR_SHIFT                    (24U)
2491 /*! MAJOR - Major Version Number
2492  */
2493 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
2494 /*! @} */
2495 
2496 /*! @name PARAM - Parameter Register */
2497 /*! @{ */
2498 
2499 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
2500 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
2501 /*! TRIG_NUM - Trigger Number
2502  *  0b00001000..8 hardware triggers implemented
2503  */
2504 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
2505 
2506 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
2507 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
2508 /*! FIFOSIZE - Result FIFO Depth
2509  *  0b00010000..Result FIFO depth = 16 datawords.
2510  */
2511 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
2512 
2513 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
2514 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
2515 /*! CV_NUM - Compare Value Number
2516  *  0b00000100..4 compare value registers implemented
2517  */
2518 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
2519 
2520 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
2521 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
2522 /*! CMD_NUM - Command Buffer Number
2523  *  0b00001111..15 command buffers implemented
2524  */
2525 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
2526 /*! @} */
2527 
2528 /*! @name CTRL - LPADC Control Register */
2529 /*! @{ */
2530 
2531 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
2532 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
2533 /*! ADCEN - LPADC Enable
2534  *  0b0..LPADC is disabled.
2535  *  0b1..LPADC is enabled.
2536  */
2537 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
2538 
2539 #define ADC_CTRL_RST_MASK                        (0x2U)
2540 #define ADC_CTRL_RST_SHIFT                       (1U)
2541 /*! RST - Software Reset
2542  *  0b0..LPADC logic is not reset.
2543  *  0b1..LPADC logic is reset.
2544  */
2545 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
2546 
2547 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
2548 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
2549 /*! DOZEN - Doze Enable
2550  *  0b0..LPADC is enabled in Doze mode.
2551  *  0b1..LPADC is disabled in Doze mode.
2552  */
2553 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
2554 
2555 #define ADC_CTRL_TRIG_SRC_MASK                   (0x18U)
2556 #define ADC_CTRL_TRIG_SRC_SHIFT                  (3U)
2557 /*! TRIG_SRC - Hardware trigger source selection
2558  *  0b00..ADC_ETC hw trigger , and HW trigger are enabled
2559  *  0b01..ADC_ETC hw trigger is enabled
2560  *  0b10..HW trigger is enabled
2561  *  0b11..Reserved
2562  */
2563 #define ADC_CTRL_TRIG_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
2564 
2565 #define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
2566 #define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
2567 /*! RSTFIFO - Reset FIFO
2568  *  0b0..No effect.
2569  *  0b1..FIFO is reset.
2570  */
2571 #define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
2572 /*! @} */
2573 
2574 /*! @name STAT - LPADC Status Register */
2575 /*! @{ */
2576 
2577 #define ADC_STAT_RDY_MASK                        (0x1U)
2578 #define ADC_STAT_RDY_SHIFT                       (0U)
2579 /*! RDY - Result FIFO Ready Flag
2580  *  0b0..Result FIFO data level not above watermark level.
2581  *  0b1..Result FIFO holding data above watermark level.
2582  */
2583 #define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
2584 
2585 #define ADC_STAT_FOF_MASK                        (0x2U)
2586 #define ADC_STAT_FOF_SHIFT                       (1U)
2587 /*! FOF - Result FIFO Overflow Flag
2588  *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
2589  *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
2590  */
2591 #define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
2592 
2593 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x100U)
2594 #define ADC_STAT_ADC_ACTIVE_SHIFT                (8U)
2595 /*! ADC_ACTIVE - ADC Active
2596  *  0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed.
2597  *  0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.
2598  */
2599 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
2600 
2601 #define ADC_STAT_TRGACT_MASK                     (0x70000U)
2602 #define ADC_STAT_TRGACT_SHIFT                    (16U)
2603 /*! TRGACT - Trigger Active
2604  *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
2605  *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
2606  *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
2607  *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
2608  */
2609 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
2610 
2611 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
2612 #define ADC_STAT_CMDACT_SHIFT                    (24U)
2613 /*! CMDACT - Command Active
2614  *  0b0000..No command is currently in progress.
2615  *  0b0001..Command 1 currently being executed.
2616  *  0b0010..Command 2 currently being executed.
2617  *  0b0011-0b1111..Associated command number is currently being executed.
2618  */
2619 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
2620 /*! @} */
2621 
2622 /*! @name IE - Interrupt Enable Register */
2623 /*! @{ */
2624 
2625 #define ADC_IE_FWMIE_MASK                        (0x1U)
2626 #define ADC_IE_FWMIE_SHIFT                       (0U)
2627 /*! FWMIE - FIFO Watermark Interrupt Enable
2628  *  0b0..FIFO watermark interrupts are not enabled.
2629  *  0b1..FIFO watermark interrupts are enabled.
2630  */
2631 #define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
2632 
2633 #define ADC_IE_FOFIE_MASK                        (0x2U)
2634 #define ADC_IE_FOFIE_SHIFT                       (1U)
2635 /*! FOFIE - Result FIFO Overflow Interrupt Enable
2636  *  0b0..FIFO overflow interrupts are not enabled.
2637  *  0b1..FIFO overflow interrupts are enabled.
2638  */
2639 #define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
2640 /*! @} */
2641 
2642 /*! @name DE - DMA Enable Register */
2643 /*! @{ */
2644 
2645 #define ADC_DE_FWMDE_MASK                        (0x1U)
2646 #define ADC_DE_FWMDE_SHIFT                       (0U)
2647 /*! FWMDE - FIFO Watermark DMA Enable
2648  *  0b0..DMA request disabled.
2649  *  0b1..DMA request enabled.
2650  */
2651 #define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
2652 /*! @} */
2653 
2654 /*! @name CFG - LPADC Configuration Register */
2655 /*! @{ */
2656 
2657 #define ADC_CFG_TPRICTRL_MASK                    (0x1U)
2658 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
2659 /*! TPRICTRL - LPADC trigger priority control
2660  *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
2661  *       the new command specified by the trigger is started.
2662  *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed
2663  *       (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
2664  *       trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
2665  *       conversion.
2666  */
2667 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
2668 
2669 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
2670 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
2671 /*! PWRSEL - Power Configuration Select
2672  *  0b00..Level 1 (Lowest power setting)
2673  *  0b01..Level 2
2674  *  0b10..Level 3
2675  *  0b11..Level 4 (Highest power setting)
2676  */
2677 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
2678 
2679 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
2680 #define ADC_CFG_REFSEL_SHIFT                     (6U)
2681 /*! REFSEL - Voltage Reference Selection
2682  *  0b00..(Default) Option 1 setting.
2683  *  0b01..Option 2 setting.
2684  *  0b10..Option 3 setting.
2685  *  0b11..Reserved
2686  */
2687 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
2688 
2689 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
2690 #define ADC_CFG_PUDLY_SHIFT                      (16U)
2691 /*! PUDLY - Power Up Delay
2692  */
2693 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
2694 
2695 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
2696 #define ADC_CFG_PWREN_SHIFT                      (28U)
2697 /*! PWREN - LPADC Analog Pre-Enable
2698  *  0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
2699  *  0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the
2700  *       cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
2701  *       detected trigger does not begin ADC operation until the power up delay time has passed.
2702  */
2703 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
2704 /*! @} */
2705 
2706 /*! @name PAUSE - LPADC Pause Register */
2707 /*! @{ */
2708 
2709 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
2710 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
2711 /*! PAUSEDLY - Pause Delay
2712  */
2713 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
2714 
2715 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
2716 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
2717 /*! PAUSEEN - PAUSE Option Enable
2718  *  0b0..Pause operation disabled
2719  *  0b1..Pause operation enabled
2720  */
2721 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
2722 /*! @} */
2723 
2724 /*! @name FCTRL - LPADC FIFO Control Register */
2725 /*! @{ */
2726 
2727 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
2728 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
2729 /*! FCOUNT - Result FIFO counter
2730  *  0b00000..No data stored in FIFO
2731  *  0b00001..1 dataword stored in FIFO
2732  *  0b00010..2 datawords stored in FIFO
2733  *  0b00100..4 datawords stored in FIFO
2734  *  0b01000..8 datawords stored in FIFO
2735  *  0b10000..16 datawords stored in FIFO
2736  */
2737 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
2738 
2739 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
2740 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
2741 /*! FWMARK - Watermark level selection
2742  *  0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion
2743  *  0b0001..Generates STAT[RDY] flag after 2nd successful conversion
2744  *  0b0010..Generates STAT[RDY] flag after 3rd successful conversion
2745  *  0b0011..Generates STAT[RDY] flag after 4th successful conversion
2746  *  0b0100..Generates STAT[RDY] flag after 5th successful conversion
2747  *  0b0101..Generates STAT[RDY] flag after 6th successful conversion
2748  *  0b0110..Generates STAT[RDY] flag after 7th successful conversion
2749  *  0b0111..Generates STAT[RDY] flag after 8th successful conversion
2750  *  0b1000..Generates STAT[RDY] flag after 9th successful conversion
2751  *  0b1001..Generates STAT[RDY] flag after 10th successful conversion
2752  *  0b1010..Generates STAT[RDY] flag after 11th successful conversion
2753  *  0b1011..Generates STAT[RDY] flag after 12th successful conversion
2754  *  0b1100..Generates STAT[RDY] flag after 13th successful conversion
2755  *  0b1101..Generates STAT[RDY] flag after 14th successful conversion
2756  *  0b1110..Generates STAT[RDY] flag after 15th successful conversion
2757  *  0b1111..Generates STAT[RDY] flag after 16th successful conversion
2758  */
2759 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
2760 /*! @} */
2761 
2762 /*! @name SWTRIG - Software Trigger Register */
2763 /*! @{ */
2764 
2765 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
2766 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
2767 /*! SWT0 - Software trigger 0 event
2768  *  0b0..No trigger 0 event generated.
2769  *  0b1..Trigger 0 event generated.
2770  */
2771 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
2772 
2773 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
2774 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
2775 /*! SWT1 - Software trigger 1 event
2776  *  0b0..No trigger 1 event generated.
2777  *  0b1..Trigger 1 event generated.
2778  */
2779 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
2780 
2781 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
2782 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
2783 /*! SWT2 - Software trigger 2 event
2784  *  0b0..No trigger 2 event generated.
2785  *  0b1..Trigger 2 event generated.
2786  */
2787 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
2788 
2789 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
2790 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
2791 /*! SWT3 - Software trigger 3 event
2792  *  0b0..No trigger 3 event generated.
2793  *  0b1..Trigger 3 event generated.
2794  */
2795 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
2796 
2797 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
2798 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
2799 /*! SWT4 - Software trigger 4 event
2800  *  0b0..No trigger 4 event generated.
2801  *  0b1..Trigger 4 event generated.
2802  */
2803 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
2804 
2805 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
2806 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
2807 /*! SWT5 - Software trigger 5 event
2808  *  0b0..No trigger 5 event generated.
2809  *  0b1..Trigger 5 event generated.
2810  */
2811 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
2812 
2813 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
2814 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
2815 /*! SWT6 - Software trigger 6 event
2816  *  0b0..No trigger 6 event generated.
2817  *  0b1..Trigger 6 event generated.
2818  */
2819 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
2820 
2821 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
2822 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
2823 /*! SWT7 - Software trigger 7 event
2824  *  0b0..No trigger 7 event generated.
2825  *  0b1..Trigger 7 event generated.
2826  */
2827 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
2828 /*! @} */
2829 
2830 /*! @name TCTRL - Trigger Control Register */
2831 /*! @{ */
2832 
2833 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
2834 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
2835 /*! HTEN - Trigger enable
2836  *  0b0..Hardware trigger source disabled
2837  *  0b1..Hardware trigger source enabled
2838  */
2839 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
2840 
2841 #define ADC_TCTRL_CMD_SEL_MASK                   (0x2U)
2842 #define ADC_TCTRL_CMD_SEL_SHIFT                  (1U)
2843 /*! CMD_SEL
2844  *  0b0..TCTRLa[TCMD] will determine the command
2845  *  0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is
2846  *       then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].
2847  */
2848 #define ADC_TCTRL_CMD_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
2849 
2850 #define ADC_TCTRL_TPRI_MASK                      (0x700U)
2851 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
2852 /*! TPRI - Trigger priority setting
2853  *  0b000..Set to highest priority, Level 1
2854  *  0b001-0b110..Set to corresponding priority level
2855  *  0b111..Set to lowest priority, Level 8
2856  */
2857 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
2858 
2859 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
2860 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
2861 /*! TDLY - Trigger delay select
2862  */
2863 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
2864 
2865 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
2866 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
2867 /*! TCMD - Trigger command select
2868  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
2869  *  0b0001..CMD1 is executed
2870  *  0b0010-0b1110..Corresponding CMD is executed
2871  *  0b1111..CMD15 is executed
2872  */
2873 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
2874 /*! @} */
2875 
2876 /* The count of ADC_TCTRL */
2877 #define ADC_TCTRL_COUNT                          (8U)
2878 
2879 /*! @name CMDL - LPADC Command Low Buffer Register */
2880 /*! @{ */
2881 
2882 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
2883 #define ADC_CMDL_ADCH_SHIFT                      (0U)
2884 /*! ADCH - Input channel select
2885  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
2886  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
2887  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
2888  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
2889  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
2890  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
2891  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
2892  */
2893 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
2894 
2895 #define ADC_CMDL_ABSEL_MASK                      (0x20U)
2896 #define ADC_CMDL_ABSEL_SHIFT                     (5U)
2897 /*! ABSEL - A-side vs. B-side Select
2898  *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
2899  *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
2900  */
2901 #define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
2902 
2903 #define ADC_CMDL_DIFF_MASK                       (0x40U)
2904 #define ADC_CMDL_DIFF_SHIFT                      (6U)
2905 /*! DIFF - Differential Mode Enable
2906  *  0b0..Single-ended mode.
2907  *  0b1..Differential mode.
2908  */
2909 #define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
2910 
2911 #define ADC_CMDL_CSCALE_MASK                     (0x2000U)
2912 #define ADC_CMDL_CSCALE_SHIFT                    (13U)
2913 /*! CSCALE - Channel Scale
2914  *  0b0..Scale selected analog channel (Factor of 30/64)
2915  *  0b1..(Default) Full scale (Factor of 1)
2916  */
2917 #define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
2918 /*! @} */
2919 
2920 /* The count of ADC_CMDL */
2921 #define ADC_CMDL_COUNT                           (15U)
2922 
2923 /*! @name CMDH - LPADC Command High Buffer Register */
2924 /*! @{ */
2925 
2926 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
2927 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
2928 /*! CMPEN - Compare Function Enable
2929  *  0b00..Compare disabled.
2930  *  0b01..Reserved
2931  *  0b10..Compare enabled. Store on true.
2932  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
2933  */
2934 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
2935 
2936 #define ADC_CMDH_LWI_MASK                        (0x80U)
2937 #define ADC_CMDH_LWI_SHIFT                       (7U)
2938 /*! LWI - Loop with Increment
2939  *  0b0..Auto channel increment disabled
2940  *  0b1..Auto channel increment enabled
2941  */
2942 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
2943 
2944 #define ADC_CMDH_STS_MASK                        (0x700U)
2945 #define ADC_CMDH_STS_SHIFT                       (8U)
2946 /*! STS - Sample Time Select
2947  *  0b000..Minimum sample time of 3 ADCK cycles.
2948  *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
2949  *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
2950  *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
2951  *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
2952  *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
2953  *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
2954  *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
2955  */
2956 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
2957 
2958 #define ADC_CMDH_AVGS_MASK                       (0x7000U)
2959 #define ADC_CMDH_AVGS_SHIFT                      (12U)
2960 /*! AVGS - Hardware Average Select
2961  *  0b000..Single conversion.
2962  *  0b001..2 conversions averaged.
2963  *  0b010..4 conversions averaged.
2964  *  0b011..8 conversions averaged.
2965  *  0b100..16 conversions averaged.
2966  *  0b101..32 conversions averaged.
2967  *  0b110..64 conversions averaged.
2968  *  0b111..128 conversions averaged.
2969  */
2970 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
2971 
2972 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
2973 #define ADC_CMDH_LOOP_SHIFT                      (16U)
2974 /*! LOOP - Loop Count Select
2975  *  0b0000..Looping not enabled. Command executes 1 time.
2976  *  0b0001..Loop 1 time. Command executes 2 times.
2977  *  0b0010..Loop 2 times. Command executes 3 times.
2978  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
2979  *  0b1111..Loop 15 times. Command executes 16 times.
2980  */
2981 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
2982 
2983 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
2984 #define ADC_CMDH_NEXT_SHIFT                      (24U)
2985 /*! NEXT - Next Command Select
2986  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
2987  *          trigger pending, begin command associated with lower priority trigger.
2988  *  0b0001..Select CMD1 command buffer register as next command.
2989  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
2990  *  0b1111..Select CMD15 command buffer register as next command.
2991  */
2992 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
2993 /*! @} */
2994 
2995 /* The count of ADC_CMDH */
2996 #define ADC_CMDH_COUNT                           (15U)
2997 
2998 /*! @name CV - Compare Value Register */
2999 /*! @{ */
3000 
3001 #define ADC_CV_CVL_MASK                          (0xFFFFU)
3002 #define ADC_CV_CVL_SHIFT                         (0U)
3003 /*! CVL - Compare Value Low
3004  */
3005 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
3006 
3007 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
3008 #define ADC_CV_CVH_SHIFT                         (16U)
3009 /*! CVH - Compare Value High.
3010  */
3011 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
3012 /*! @} */
3013 
3014 /* The count of ADC_CV */
3015 #define ADC_CV_COUNT                             (4U)
3016 
3017 /*! @name RESFIFO - LPADC Data Result FIFO Register */
3018 /*! @{ */
3019 
3020 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
3021 #define ADC_RESFIFO_D_SHIFT                      (0U)
3022 /*! D - Data result
3023  */
3024 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
3025 
3026 #define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
3027 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
3028 /*! TSRC - Trigger Source
3029  *  0b000..Trigger source 0 initiated this conversion.
3030  *  0b001..Trigger source 1 initiated this conversion.
3031  *  0b010-0b110..Corresponding trigger source initiated this conversion.
3032  *  0b111..Trigger source 7 initiated this conversion.
3033  */
3034 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
3035 
3036 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
3037 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
3038 /*! LOOPCNT - Loop count value
3039  *  0b0000..Result is from initial conversion in command.
3040  *  0b0001..Result is from second conversion in command.
3041  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
3042  *  0b1111..Result is from 16th conversion in command.
3043  */
3044 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
3045 
3046 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
3047 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
3048 /*! CMDSRC - Command Buffer Source
3049  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
3050  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
3051  *  0b0001..CMD1 buffer used as control settings for this conversion.
3052  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
3053  *  0b1111..CMD15 buffer used as control settings for this conversion.
3054  */
3055 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
3056 
3057 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
3058 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
3059 /*! VALID - FIFO entry is valid
3060  *  0b0..FIFO is empty. Discard any read from RESFIFO.
3061  *  0b1..FIFO record read from RESFIFO is valid.
3062  */
3063 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
3064 /*! @} */
3065 
3066 
3067 /*!
3068  * @}
3069  */ /* end of group ADC_Register_Masks */
3070 
3071 
3072 /* ADC - Peripheral instance base addresses */
3073 /** Peripheral LPADC1 base address */
3074 #define LPADC1_BASE                              (0x40050000u)
3075 /** Peripheral LPADC1 base pointer */
3076 #define LPADC1                                   ((ADC_Type *)LPADC1_BASE)
3077 /** Peripheral LPADC2 base address */
3078 #define LPADC2_BASE                              (0x40054000u)
3079 /** Peripheral LPADC2 base pointer */
3080 #define LPADC2                                   ((ADC_Type *)LPADC2_BASE)
3081 /** Array initializer of ADC peripheral base addresses */
3082 #define ADC_BASE_ADDRS                           { 0u, LPADC1_BASE, LPADC2_BASE }
3083 /** Array initializer of ADC peripheral base pointers */
3084 #define ADC_BASE_PTRS                            { (ADC_Type *)0u, LPADC1, LPADC2 }
3085 /** Interrupt vectors for the ADC peripheral type */
3086 #define ADC_IRQS                                 { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
3087 
3088 /*!
3089  * @}
3090  */ /* end of group ADC_Peripheral_Access_Layer */
3091 
3092 
3093 /* ----------------------------------------------------------------------------
3094    -- ADC_ETC Peripheral Access Layer
3095    ---------------------------------------------------------------------------- */
3096 
3097 /*!
3098  * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
3099  * @{
3100  */
3101 
3102 /** ADC_ETC - Register Layout Typedef */
3103 typedef struct {
3104   __IO uint32_t CTRL;                              /**< ADC_ETC Global Control Register, offset: 0x0 */
3105   __IO uint32_t DONE0_1_IRQ;                       /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
3106   __IO uint32_t DONE2_3_ERR_IRQ;                   /**< ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8 */
3107   __IO uint32_t DMA_CTRL;                          /**< ETC DMA control Register, offset: 0xC */
3108   struct {                                         /* offset: 0x10, array step: 0x28 */
3109     __IO uint32_t TRIGn_CTRL;                        /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
3110     __IO uint32_t TRIGn_COUNTER;                     /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
3111     __IO uint32_t TRIGn_CHAIN_1_0;                   /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
3112     __IO uint32_t TRIGn_CHAIN_3_2;                   /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
3113     __IO uint32_t TRIGn_CHAIN_5_4;                   /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
3114     __IO uint32_t TRIGn_CHAIN_7_6;                   /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
3115     __I  uint32_t TRIGn_RESULT_1_0;                  /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
3116     __I  uint32_t TRIGn_RESULT_3_2;                  /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
3117     __I  uint32_t TRIGn_RESULT_5_4;                  /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
3118     __I  uint32_t TRIGn_RESULT_7_6;                  /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
3119   } TRIG[8];
3120 } ADC_ETC_Type;
3121 
3122 /* ----------------------------------------------------------------------------
3123    -- ADC_ETC Register Masks
3124    ---------------------------------------------------------------------------- */
3125 
3126 /*!
3127  * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
3128  * @{
3129  */
3130 
3131 /*! @name CTRL - ADC_ETC Global Control Register */
3132 /*! @{ */
3133 
3134 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK            (0xFFU)
3135 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT           (0U)
3136 /*! TRIG_ENABLE
3137  *  0b00000000..disable all 8 external XBAR triggers.
3138  *  0b00000001..enable external XBAR trigger0.
3139  *  0b00000010..enable external XBAR trigger1.
3140  *  0b00000011..enable external XBAR trigger0 and trigger1.
3141  *  0b11111111..enable all 8 external XBAR triggers.
3142  */
3143 #define ADC_ETC_CTRL_TRIG_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
3144 
3145 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK            (0xFF0000U)
3146 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT           (16U)
3147 #define ADC_ETC_CTRL_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
3148 
3149 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK           (0x20000000U)
3150 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT          (29U)
3151 /*! DMA_MODE_SEL
3152  *  0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared.
3153  *  0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only.
3154  */
3155 #define ADC_ETC_CTRL_DMA_MODE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
3156 
3157 #define ADC_ETC_CTRL_SOFTRST_MASK                (0x80000000U)
3158 #define ADC_ETC_CTRL_SOFTRST_SHIFT               (31U)
3159 /*! SOFTRST
3160  *  0b0..ADC_ETC works normally.
3161  *  0b1..All registers inside ADC_ETC will be reset to the default value.
3162  */
3163 #define ADC_ETC_CTRL_SOFTRST(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
3164 /*! @} */
3165 
3166 /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
3167 /*! @{ */
3168 
3169 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK     (0x1U)
3170 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT    (0U)
3171 /*! TRIG0_DONE0
3172  *  0b0..No TRIG0_DONE0 interrupt detected
3173  *  0b1..TRIG0_DONE0 interrupt detected
3174  */
3175 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
3176 
3177 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK     (0x2U)
3178 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT    (1U)
3179 /*! TRIG1_DONE0
3180  *  0b0..No TRIG1_DONE0 interrupt detected
3181  *  0b1..TRIG1_DONE0 interrupt detected
3182  */
3183 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
3184 
3185 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK     (0x4U)
3186 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT    (2U)
3187 /*! TRIG2_DONE0
3188  *  0b0..No TRIG2_DONE0 interrupt detected
3189  *  0b1..TRIG2_DONE0 interrupt detected
3190  */
3191 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
3192 
3193 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK     (0x8U)
3194 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT    (3U)
3195 /*! TRIG3_DONE0
3196  *  0b0..No TRIG3_DONE0 interrupt detected
3197  *  0b1..TRIG3_DONE0 interrupt detected
3198  */
3199 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
3200 
3201 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK     (0x10U)
3202 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT    (4U)
3203 /*! TRIG4_DONE0
3204  *  0b0..No TRIG4_DONE0 interrupt detected
3205  *  0b1..TRIG4_DONE0 interrupt detected
3206  */
3207 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
3208 
3209 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK     (0x20U)
3210 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT    (5U)
3211 /*! TRIG5_DONE0
3212  *  0b0..No TRIG5_DONE0 interrupt detected
3213  *  0b1..TRIG5_DONE0 interrupt detected
3214  */
3215 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
3216 
3217 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK     (0x40U)
3218 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT    (6U)
3219 /*! TRIG6_DONE0
3220  *  0b0..No TRIG6_DONE0 interrupt detected
3221  *  0b1..TRIG6_DONE0 interrupt detected
3222  */
3223 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
3224 
3225 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK     (0x80U)
3226 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT    (7U)
3227 /*! TRIG7_DONE0
3228  *  0b0..No TRIG7_DONE0 interrupt detected
3229  *  0b1..TRIG7_DONE0 interrupt detected
3230  */
3231 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
3232 
3233 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK     (0x10000U)
3234 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT    (16U)
3235 /*! TRIG0_DONE1
3236  *  0b0..No TRIG0_DONE1 interrupt detected
3237  *  0b1..TRIG0_DONE1 interrupt detected
3238  */
3239 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
3240 
3241 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK     (0x20000U)
3242 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT    (17U)
3243 /*! TRIG1_DONE1
3244  *  0b0..No TRIG1_DONE1 interrupt detected
3245  *  0b1..TRIG1_DONE1 interrupt detected
3246  */
3247 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
3248 
3249 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK     (0x40000U)
3250 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT    (18U)
3251 /*! TRIG2_DONE1
3252  *  0b0..No TRIG2_DONE1 interrupt detected
3253  *  0b1..TRIG2_DONE1 interrupt detected
3254  */
3255 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
3256 
3257 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK     (0x80000U)
3258 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT    (19U)
3259 /*! TRIG3_DONE1
3260  *  0b0..No TRIG3_DONE1 interrupt detected
3261  *  0b1..TRIG3_DONE1 interrupt detected
3262  */
3263 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
3264 
3265 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK     (0x100000U)
3266 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT    (20U)
3267 /*! TRIG4_DONE1
3268  *  0b0..No TRIG4_DONE1 interrupt detected
3269  *  0b1..TRIG4_DONE1 interrupt detected
3270  */
3271 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
3272 
3273 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK     (0x200000U)
3274 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT    (21U)
3275 /*! TRIG5_DONE1
3276  *  0b0..No TRIG5_DONE1 interrupt detected
3277  *  0b1..TRIG5_DONE1 interrupt detected
3278  */
3279 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
3280 
3281 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK     (0x400000U)
3282 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT    (22U)
3283 /*! TRIG6_DONE1
3284  *  0b0..No TRIG6_DONE1 interrupt detected
3285  *  0b1..TRIG6_DONE1 interrupt detected
3286  */
3287 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
3288 
3289 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK     (0x800000U)
3290 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT    (23U)
3291 /*! TRIG7_DONE1
3292  *  0b0..No TRIG7_DONE1 interrupt detected
3293  *  0b1..TRIG7_DONE1 interrupt detected
3294  */
3295 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
3296 /*! @} */
3297 
3298 /*! @name DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register */
3299 /*! @{ */
3300 
3301 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
3302 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
3303 /*! TRIG0_DONE2
3304  *  0b0..No TRIG0_DONE2 interrupt detected
3305  *  0b1..TRIG0_DONE2 interrupt detected
3306  */
3307 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
3308 
3309 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
3310 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
3311 /*! TRIG1_DONE2
3312  *  0b0..No TRIG1_DONE2 interrupt detected
3313  *  0b1..TRIG1_DONE2 interrupt detected
3314  */
3315 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
3316 
3317 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
3318 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
3319 /*! TRIG2_DONE2
3320  *  0b0..No TRIG2_DONE2 interrupt detected
3321  *  0b1..TRIG2_DONE2 interrupt detected
3322  */
3323 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
3324 
3325 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
3326 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
3327 /*! TRIG3_DONE2
3328  *  0b0..No TRIG3_DONE2 interrupt detected
3329  *  0b1..TRIG3_DONE2 interrupt detected
3330  */
3331 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
3332 
3333 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
3334 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
3335 /*! TRIG4_DONE2
3336  *  0b0..No TRIG4_DONE2 interrupt detected
3337  *  0b1..TRIG4_DONE2 interrupt detected
3338  */
3339 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
3340 
3341 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
3342 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
3343 /*! TRIG5_DONE2
3344  *  0b0..No TRIG5_DONE2 interrupt detected
3345  *  0b1..TRIG5_DONE2 interrupt detected
3346  */
3347 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
3348 
3349 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
3350 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
3351 /*! TRIG6_DONE2
3352  *  0b0..No TRIG6_DONE2 interrupt detected
3353  *  0b1..TRIG6_DONE2 interrupt detected
3354  */
3355 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
3356 
3357 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
3358 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
3359 /*! TRIG7_DONE2
3360  *  0b0..No TRIG7_DONE2 interrupt detected
3361  *  0b1..TRIG7_DONE2 interrupt detected
3362  */
3363 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
3364 
3365 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
3366 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
3367 /*! TRIG0_DONE3
3368  *  0b0..No TRIG0_DONE3 interrupt detected
3369  *  0b1..TRIG0_DONE3 interrupt detected
3370  */
3371 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
3372 
3373 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
3374 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
3375 /*! TRIG1_DONE3
3376  *  0b0..No TRIG1_DONE3 interrupt detected
3377  *  0b1..TRIG1_DONE3 interrupt detected
3378  */
3379 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK)
3380 
3381 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
3382 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
3383 /*! TRIG2_DONE3
3384  *  0b0..No TRIG2_DONE3 interrupt detected
3385  *  0b1..TRIG2_DONE3 interrupt detected
3386  */
3387 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK)
3388 
3389 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
3390 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
3391 /*! TRIG3_DONE3
3392  *  0b0..No TRIG3_DONE3 interrupt detected
3393  *  0b1..TRIG3_DONE3 interrupt detected
3394  */
3395 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK)
3396 
3397 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
3398 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
3399 /*! TRIG4_DONE3
3400  *  0b0..No TRIG4_DONE3 interrupt detected
3401  *  0b1..TRIG4_DONE3 interrupt detected
3402  */
3403 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK)
3404 
3405 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
3406 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
3407 /*! TRIG5_DONE3
3408  *  0b0..No TRIG5_DONE3 interrupt detected
3409  *  0b1..TRIG5_DONE3 interrupt detected
3410  */
3411 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK)
3412 
3413 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
3414 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
3415 /*! TRIG6_DONE3
3416  *  0b0..No TRIG6_DONE3 interrupt detected
3417  *  0b1..TRIG6_DONE3 interrupt detected
3418  */
3419 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK)
3420 
3421 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
3422 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
3423 /*! TRIG7_DONE3
3424  *  0b0..No TRIG7_DONE3 interrupt detected
3425  *  0b1..TRIG7_DONE3 interrupt detected
3426  */
3427 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK)
3428 
3429 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK   (0x10000U)
3430 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT  (16U)
3431 /*! TRIG0_ERR
3432  *  0b0..No TRIG0_ERR interrupt detected
3433  *  0b1..TRIG0_ERR interrupt detected
3434  */
3435 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
3436 
3437 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK   (0x20000U)
3438 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT  (17U)
3439 /*! TRIG1_ERR
3440  *  0b0..No TRIG1_ERR interrupt detected
3441  *  0b1..TRIG1_ERR interrupt detected
3442  */
3443 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
3444 
3445 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK   (0x40000U)
3446 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT  (18U)
3447 /*! TRIG2_ERR
3448  *  0b0..No TRIG2_ERR interrupt detected
3449  *  0b1..TRIG2_ERR interrupt detected
3450  */
3451 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
3452 
3453 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK   (0x80000U)
3454 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT  (19U)
3455 /*! TRIG3_ERR
3456  *  0b0..No TRIG3_ERR interrupt detected
3457  *  0b1..TRIG3_ERR interrupt detected
3458  */
3459 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
3460 
3461 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK   (0x100000U)
3462 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT  (20U)
3463 /*! TRIG4_ERR
3464  *  0b0..No TRIG4_ERR interrupt detected
3465  *  0b1..TRIG4_ERR interrupt detected
3466  */
3467 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
3468 
3469 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK   (0x200000U)
3470 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT  (21U)
3471 /*! TRIG5_ERR
3472  *  0b0..No TRIG5_ERR interrupt detected
3473  *  0b1..TRIG5_ERR interrupt detected
3474  */
3475 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
3476 
3477 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK   (0x400000U)
3478 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT  (22U)
3479 /*! TRIG6_ERR
3480  *  0b0..No TRIG6_ERR interrupt detected
3481  *  0b1..TRIG6_ERR interrupt detected
3482  */
3483 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
3484 
3485 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK   (0x800000U)
3486 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT  (23U)
3487 /*! TRIG7_ERR
3488  *  0b0..No TRIG7_ERR interrupt detected
3489  *  0b1..TRIG7_ERR interrupt detected
3490  */
3491 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
3492 /*! @} */
3493 
3494 /*! @name DMA_CTRL - ETC DMA control Register */
3495 /*! @{ */
3496 
3497 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK       (0x1U)
3498 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT      (0U)
3499 /*! TRIG0_ENABLE
3500  *  0b0..TRIG0 DMA request disabled.
3501  *  0b1..TRIG0 DMA request enabled.
3502  */
3503 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
3504 
3505 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK       (0x2U)
3506 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT      (1U)
3507 /*! TRIG1_ENABLE
3508  *  0b0..TRIG1 DMA request disabled.
3509  *  0b1..TRIG1 DMA request enabled.
3510  */
3511 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
3512 
3513 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK       (0x4U)
3514 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT      (2U)
3515 /*! TRIG2_ENABLE
3516  *  0b0..TRIG2 DMA request disabled.
3517  *  0b1..TRIG2 DMA request enabled.
3518  */
3519 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
3520 
3521 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK       (0x8U)
3522 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT      (3U)
3523 /*! TRIG3_ENABLE
3524  *  0b0..TRIG3 DMA request disabled.
3525  *  0b1..TRIG3 DMA request enabled.
3526  */
3527 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
3528 
3529 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK       (0x10U)
3530 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT      (4U)
3531 /*! TRIG4_ENABLE
3532  *  0b0..TRIG4 DMA request disabled.
3533  *  0b1..TRIG4 DMA request enabled.
3534  */
3535 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
3536 
3537 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK       (0x20U)
3538 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT      (5U)
3539 /*! TRIG5_ENABLE
3540  *  0b0..TRIG5 DMA request disabled.
3541  *  0b1..TRIG5 DMA request enabled.
3542  */
3543 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
3544 
3545 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK       (0x40U)
3546 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT      (6U)
3547 /*! TRIG6_ENABLE
3548  *  0b0..TRIG6 DMA request disabled.
3549  *  0b1..TRIG6 DMA request enabled.
3550  */
3551 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
3552 
3553 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK       (0x80U)
3554 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT      (7U)
3555 /*! TRIG7_ENABLE
3556  *  0b0..TRIG7 DMA request disabled.
3557  *  0b1..TRIG7 DMA request enabled.
3558  */
3559 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
3560 
3561 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK          (0x10000U)
3562 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT         (16U)
3563 /*! TRIG0_REQ
3564  *  0b0..TRIG0_REQ not detected.
3565  *  0b1..TRIG0_REQ detected.
3566  */
3567 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
3568 
3569 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK          (0x20000U)
3570 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT         (17U)
3571 /*! TRIG1_REQ
3572  *  0b0..TRIG1_REQ not detected.
3573  *  0b1..TRIG1_REQ detected.
3574  */
3575 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
3576 
3577 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK          (0x40000U)
3578 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT         (18U)
3579 /*! TRIG2_REQ
3580  *  0b0..TRIG2_REQ not detected.
3581  *  0b1..TRIG2_REQ detected.
3582  */
3583 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
3584 
3585 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK          (0x80000U)
3586 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT         (19U)
3587 /*! TRIG3_REQ
3588  *  0b0..TRIG3_REQ not detected.
3589  *  0b1..TRIG3_REQ detected.
3590  */
3591 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
3592 
3593 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK          (0x100000U)
3594 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT         (20U)
3595 /*! TRIG4_REQ
3596  *  0b0..TRIG4_REQ not detected.
3597  *  0b1..TRIG4_REQ detected.
3598  */
3599 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
3600 
3601 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK          (0x200000U)
3602 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT         (21U)
3603 /*! TRIG5_REQ
3604  *  0b0..TRIG5_REQ not detected.
3605  *  0b1..TRIG5_REQ detected.
3606  */
3607 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
3608 
3609 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK          (0x400000U)
3610 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT         (22U)
3611 /*! TRIG6_REQ
3612  *  0b0..TRIG6_REQ not detected.
3613  *  0b1..TRIG6_REQ detected.
3614  */
3615 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
3616 
3617 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK          (0x800000U)
3618 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT         (23U)
3619 /*! TRIG7_REQ
3620  *  0b0..TRIG7_REQ not detected.
3621  *  0b1..TRIG7_REQ detected.
3622  */
3623 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
3624 /*! @} */
3625 
3626 /*! @name TRIGn_CTRL - ETC_TRIG Control Register */
3627 /*! @{ */
3628 
3629 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK          (0x1U)
3630 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT         (0U)
3631 /*! SW_TRIG
3632  *  0b0..No software trigger event generated.
3633  *  0b1..Software trigger event generated.
3634  */
3635 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
3636 
3637 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK        (0x10U)
3638 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT       (4U)
3639 /*! TRIG_MODE
3640  *  0b0..Hardware trigger. The softerware trigger will be ignored.
3641  *  0b1..Software trigger. The hardware trigger will be ignored.
3642  */
3643 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
3644 
3645 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK       (0x700U)
3646 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT      (8U)
3647 /*! TRIG_CHAIN
3648  *  0b000..Trigger chain length is 1
3649  *  0b001..Trigger chain length is 2
3650  *  0b010..Trigger chain length is 3
3651  *  0b011..Trigger chain length is 4
3652  *  0b100..Trigger chain length is 5
3653  *  0b101..Trigger chain length is 6
3654  *  0b110..Trigger chain length is 7
3655  *  0b111..Trigger chain length is 8
3656  */
3657 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
3658 
3659 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK    (0x7000U)
3660 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT   (12U)
3661 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
3662 
3663 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK        (0x10000U)
3664 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT       (16U)
3665 /*! SYNC_MODE
3666  *  0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently.
3667  *  0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously.
3668  */
3669 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
3670 
3671 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK      (0xFF000000U)
3672 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT     (24U)
3673 /*! CHAINx_DONE
3674  *  0b00000000..segment x done not detected.
3675  *  0b00000001..segment x done detected.
3676  */
3677 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
3678 /*! @} */
3679 
3680 /* The count of ADC_ETC_TRIGn_CTRL */
3681 #define ADC_ETC_TRIGn_CTRL_COUNT                 (8U)
3682 
3683 /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
3684 /*! @{ */
3685 
3686 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK    (0xFFFFU)
3687 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT   (0U)
3688 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
3689 
3690 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
3691 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
3692 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
3693 /*! @} */
3694 
3695 /* The count of ADC_ETC_TRIGn_COUNTER */
3696 #define ADC_ETC_TRIGn_COUNTER_COUNT              (8U)
3697 
3698 /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
3699 /*! @{ */
3700 
3701 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK       (0xFU)
3702 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT      (0U)
3703 /*! CSEL0
3704  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3705  *  0b0001..ADC CMD1 selected.
3706  *  0b0010..ADC CMD2 selected.
3707  *  0b0011..ADC CMD3 selected.
3708  *  0b0100..ADC CMD4 selected.
3709  *  0b0101..ADC CMD5 selected.
3710  *  0b0110..ADC CMD6 selected.
3711  *  0b0111..ADC CMD7 selected.
3712  *  0b1000..ADC CMD8 selected.
3713  *  0b1001..ADC CMD9 selected.
3714  *  0b1010..ADC CMD10 selected.
3715  *  0b1011..ADC CMD11 selected.
3716  *  0b1100..ADC CMD12 selected.
3717  *  0b1101..ADC CMD13 selected.
3718  *  0b1110..ADC CMD14 selected.
3719  *  0b1111..ADC CMD15 selected.
3720  */
3721 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
3722 
3723 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK       (0xFF0U)
3724 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT      (4U)
3725 /*! HWTS0
3726  *  0b00000000..no trigger selected
3727  *  0b00000001..ADC TRIG0 selected
3728  *  0b00000010..ADC TRIG1 selected
3729  *  0b00000100..ADC TRIG2 selected
3730  *  0b00001000..ADC TRIG3 selected
3731  *  0b00010000..ADC TRIG4 selected
3732  *  0b00100000..ADC TRIG5 selected
3733  *  0b01000000..ADC TRIG6 selected
3734  *  0b10000000..ADC TRIG7 selected
3735  */
3736 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
3737 
3738 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK        (0x1000U)
3739 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT       (12U)
3740 /*! B2B0
3741  *  0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached
3742  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3743  */
3744 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
3745 
3746 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK         (0x6000U)
3747 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT        (13U)
3748 /*! IE0
3749  *  0b00..Generate interrupt on Done0 when segment 0 finish.
3750  *  0b01..Generate interrupt on Done1 when segment 0 finish.
3751  *  0b10..Generate interrupt on Done2 when segment 0 finish.
3752  *  0b11..Generate interrupt on Done3 when segment 0 finish.
3753  */
3754 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
3755 
3756 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK      (0x8000U)
3757 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT     (15U)
3758 /*! IE0_EN
3759  *  0b0..Interrupt DONE disabled.
3760  *  0b1..Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0.
3761  */
3762 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
3763 
3764 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK       (0xF0000U)
3765 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT      (16U)
3766 /*! CSEL1
3767  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3768  *  0b0001..ADC CMD1 selected.
3769  *  0b0010..ADC CMD2 selected.
3770  *  0b0011..ADC CMD3 selected.
3771  *  0b0100..ADC CMD4 selected.
3772  *  0b0101..ADC CMD5 selected.
3773  *  0b0110..ADC CMD6 selected.
3774  *  0b0111..ADC CMD7 selected.
3775  *  0b1000..ADC CMD8 selected.
3776  *  0b1001..ADC CMD9 selected.
3777  *  0b1010..ADC CMD10 selected.
3778  *  0b1011..ADC CMD11 selected.
3779  *  0b1100..ADC CMD12 selected.
3780  *  0b1101..ADC CMD13 selected.
3781  *  0b1110..ADC CMD14 selected.
3782  *  0b1111..ADC CMD15 selected.
3783  */
3784 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
3785 
3786 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK       (0xFF00000U)
3787 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT      (20U)
3788 /*! HWTS1
3789  *  0b00000000..no trigger selected
3790  *  0b00000001..ADC TRIG0 selected
3791  *  0b00000010..ADC TRIG1 selected
3792  *  0b00000100..ADC TRIG2 selected
3793  *  0b00001000..ADC TRIG3 selected
3794  *  0b00010000..ADC TRIG4 selected
3795  *  0b00100000..ADC TRIG5 selected
3796  *  0b01000000..ADC TRIG6 selected
3797  *  0b10000000..ADC TRIG7 selected
3798  */
3799 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
3800 
3801 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK        (0x10000000U)
3802 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT       (28U)
3803 /*! B2B1
3804  *  0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached
3805  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3806  */
3807 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
3808 
3809 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK         (0x60000000U)
3810 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT        (29U)
3811 /*! IE1
3812  *  0b00..Generate interrupt on Done0 when Segment 1 finish.
3813  *  0b01..Generate interrupt on Done1 when Segment 1 finish.
3814  *  0b10..Generate interrupt on Done2 when Segment 1 finish.
3815  *  0b11..Generate interrupt on Done3 when Segment 1 finish.
3816  */
3817 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
3818 
3819 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK      (0x80000000U)
3820 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT     (31U)
3821 /*! IE1_EN
3822  *  0b0..Interrupt DONE disabled.
3823  *  0b1..Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1.
3824  */
3825 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
3826 /*! @} */
3827 
3828 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
3829 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT            (8U)
3830 
3831 /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
3832 /*! @{ */
3833 
3834 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK       (0xFU)
3835 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT      (0U)
3836 /*! CSEL2
3837  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3838  *  0b0001..ADC CMD1 selected.
3839  *  0b0010..ADC CMD2 selected.
3840  *  0b0011..ADC CMD3 selected.
3841  *  0b0100..ADC CMD4 selected.
3842  *  0b0101..ADC CMD5 selected.
3843  *  0b0110..ADC CMD6 selected.
3844  *  0b0111..ADC CMD7 selected.
3845  *  0b1000..ADC CMD8 selected.
3846  *  0b1001..ADC CMD9 selected.
3847  *  0b1010..ADC CMD10 selected.
3848  *  0b1011..ADC CMD11 selected.
3849  *  0b1100..ADC CMD12 selected.
3850  *  0b1101..ADC CMD13 selected.
3851  *  0b1110..ADC CMD14 selected.
3852  *  0b1111..ADC CMD15 selected.
3853  */
3854 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
3855 
3856 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK       (0xFF0U)
3857 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT      (4U)
3858 /*! HWTS2
3859  *  0b00000000..no trigger selected
3860  *  0b00000001..ADC TRIG0 selected
3861  *  0b00000010..ADC TRIG1 selected
3862  *  0b00000100..ADC TRIG2 selected
3863  *  0b00001000..ADC TRIG3 selected
3864  *  0b00010000..ADC TRIG4 selected
3865  *  0b00100000..ADC TRIG5 selected
3866  *  0b01000000..ADC TRIG6 selected
3867  *  0b10000000..ADC TRIG7 selected
3868  */
3869 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
3870 
3871 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK        (0x1000U)
3872 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT       (12U)
3873 /*! B2B2
3874  *  0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached
3875  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3876  */
3877 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
3878 
3879 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK         (0x6000U)
3880 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT        (13U)
3881 /*! IE2
3882  *  0b00..Generate interrupt on Done0 when segment 2 finish.
3883  *  0b01..Generate interrupt on Done1 when segment 2 finish.
3884  *  0b10..Generate interrupt on Done2 when segment 2 finish.
3885  *  0b11..Generate interrupt on Done3 when segment 2 finish.
3886  */
3887 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
3888 
3889 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK      (0x8000U)
3890 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT     (15U)
3891 /*! IE2_EN
3892  *  0b0..Interrupt DONE disabled.
3893  *  0b1..Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2.
3894  */
3895 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
3896 
3897 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK       (0xF0000U)
3898 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT      (16U)
3899 /*! CSEL3
3900  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3901  *  0b0001..ADC CMD1 selected.
3902  *  0b0010..ADC CMD2 selected.
3903  *  0b0011..ADC CMD3 selected.
3904  *  0b0100..ADC CMD4 selected.
3905  *  0b0101..ADC CMD5 selected.
3906  *  0b0110..ADC CMD6 selected.
3907  *  0b0111..ADC CMD7 selected.
3908  *  0b1000..ADC CMD8 selected.
3909  *  0b1001..ADC CMD9 selected.
3910  *  0b1010..ADC CMD10 selected.
3911  *  0b1011..ADC CMD11 selected.
3912  *  0b1100..ADC CMD12 selected.
3913  *  0b1101..ADC CMD13 selected.
3914  *  0b1110..ADC CMD14 selected.
3915  *  0b1111..ADC CMD15 selected.
3916  */
3917 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
3918 
3919 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK       (0xFF00000U)
3920 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT      (20U)
3921 /*! HWTS3
3922  *  0b00000000..no trigger selected
3923  *  0b00000001..ADC TRIG0 selected
3924  *  0b00000010..ADC TRIG1 selected
3925  *  0b00000100..ADC TRIG2 selected
3926  *  0b00001000..ADC TRIG3 selected
3927  *  0b00010000..ADC TRIG4 selected
3928  *  0b00100000..ADC TRIG5 selected
3929  *  0b01000000..ADC TRIG6 selected
3930  *  0b10000000..ADC TRIG7 selected
3931  */
3932 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
3933 
3934 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK        (0x10000000U)
3935 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT       (28U)
3936 /*! B2B3
3937  *  0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached
3938  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3939  */
3940 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
3941 
3942 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK         (0x60000000U)
3943 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT        (29U)
3944 /*! IE3
3945  *  0b00..Generate interrupt on Done0 when segment 3 finish.
3946  *  0b01..Generate interrupt on Done1 when segment 3 finish.
3947  *  0b10..Generate interrupt on Done2 when segment 3 finish.
3948  *  0b11..Generate interrupt on Done3 when segment 3 finish.
3949  */
3950 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
3951 
3952 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK      (0x80000000U)
3953 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT     (31U)
3954 /*! IE3_EN
3955  *  0b0..Interrupt DONE disabled.
3956  *  0b1..Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3.
3957  */
3958 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
3959 /*! @} */
3960 
3961 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
3962 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT            (8U)
3963 
3964 /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
3965 /*! @{ */
3966 
3967 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK       (0xFU)
3968 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT      (0U)
3969 /*! CSEL4
3970  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3971  *  0b0001..ADC CMD1 selected.
3972  *  0b0010..ADC CMD2 selected.
3973  *  0b0011..ADC CMD3 selected.
3974  *  0b0100..ADC CMD4 selected.
3975  *  0b0101..ADC CMD5 selected.
3976  *  0b0110..ADC CMD6 selected.
3977  *  0b0111..ADC CMD7 selected.
3978  *  0b1000..ADC CMD8 selected.
3979  *  0b1001..ADC CMD9 selected.
3980  *  0b1010..ADC CMD10 selected.
3981  *  0b1011..ADC CMD11 selected.
3982  *  0b1100..ADC CMD12 selected.
3983  *  0b1101..ADC CMD13 selected.
3984  *  0b1110..ADC CMD14 selected.
3985  *  0b1111..ADC CMD15 selected.
3986  */
3987 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
3988 
3989 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK       (0xFF0U)
3990 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT      (4U)
3991 /*! HWTS4
3992  *  0b00000000..no trigger selected
3993  *  0b00000001..ADC TRIG0 selected
3994  *  0b00000010..ADC TRIG1 selected
3995  *  0b00000100..ADC TRIG2 selected
3996  *  0b00001000..ADC TRIG3 selected
3997  *  0b00010000..ADC TRIG4 selected
3998  *  0b00100000..ADC TRIG5 selected
3999  *  0b01000000..ADC TRIG6 selected
4000  *  0b10000000..ADC TRIG7 selected
4001  */
4002 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
4003 
4004 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK        (0x1000U)
4005 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT       (12U)
4006 /*! B2B4
4007  *  0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached
4008  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4009  */
4010 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
4011 
4012 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK         (0x6000U)
4013 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT        (13U)
4014 /*! IE4
4015  *  0b00..Generate interrupt on Done0 when segment 4 finish.
4016  *  0b01..Generate interrupt on Done1 when segment 4 finish.
4017  *  0b10..Generate interrupt on Done2 when segment 4 finish.
4018  *  0b11..Generate interrupt on Done3 when segment 4 finish.
4019  */
4020 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
4021 
4022 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK      (0x8000U)
4023 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT     (15U)
4024 /*! IE4_EN
4025  *  0b0..Interrupt DONE disabled.
4026  *  0b1..Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4.
4027  */
4028 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
4029 
4030 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK       (0xF0000U)
4031 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT      (16U)
4032 /*! CSEL5
4033  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4034  *  0b0001..ADC CMD1 selected.
4035  *  0b0010..ADC CMD2 selected.
4036  *  0b0011..ADC CMD3 selected.
4037  *  0b0100..ADC CMD4 selected.
4038  *  0b0101..ADC CMD5 selected.
4039  *  0b0110..ADC CMD6 selected.
4040  *  0b0111..ADC CMD7 selected.
4041  *  0b1000..ADC CMD8 selected.
4042  *  0b1001..ADC CMD9 selected.
4043  *  0b1010..ADC CMD10 selected.
4044  *  0b1011..ADC CMD11 selected.
4045  *  0b1100..ADC CMD12 selected.
4046  *  0b1101..ADC CMD13 selected.
4047  *  0b1110..ADC CMD14 selected.
4048  *  0b1111..ADC CMD15 selected.
4049  */
4050 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
4051 
4052 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK       (0xFF00000U)
4053 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT      (20U)
4054 /*! HWTS5
4055  *  0b00000000..no trigger selected
4056  *  0b00000001..ADC TRIG0 selected
4057  *  0b00000010..ADC TRIG1 selected
4058  *  0b00000100..ADC TRIG2 selected
4059  *  0b00001000..ADC TRIG3 selected
4060  *  0b00010000..ADC TRIG4 selected
4061  *  0b00100000..ADC TRIG5 selected
4062  *  0b01000000..ADC TRIG6 selected
4063  *  0b10000000..ADC TRIG7 selected
4064  */
4065 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
4066 
4067 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK        (0x10000000U)
4068 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT       (28U)
4069 /*! B2B5
4070  *  0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached
4071  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4072  */
4073 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
4074 
4075 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK         (0x60000000U)
4076 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT        (29U)
4077 /*! IE5
4078  *  0b00..Generate interrupt on Done0 when segment 5 finish.
4079  *  0b01..Generate interrupt on Done1 when segment 5 finish.
4080  *  0b10..Generate interrupt on Done2 when segment 5 finish.
4081  *  0b11..Generate interrupt on Done3 when segment 5 finish.
4082  */
4083 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
4084 
4085 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK      (0x80000000U)
4086 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT     (31U)
4087 /*! IE5_EN
4088  *  0b0..Interrupt DONE disabled.
4089  *  0b1..Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5.
4090  */
4091 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
4092 /*! @} */
4093 
4094 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
4095 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT            (8U)
4096 
4097 /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
4098 /*! @{ */
4099 
4100 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK       (0xFU)
4101 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT      (0U)
4102 /*! CSEL6
4103  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4104  *  0b0001..ADC CMD1 selected.
4105  *  0b0010..ADC CMD2 selected.
4106  *  0b0011..ADC CMD3 selected.
4107  *  0b0100..ADC CMD4 selected.
4108  *  0b0101..ADC CMD5 selected.
4109  *  0b0110..ADC CMD6 selected.
4110  *  0b0111..ADC CMD7 selected.
4111  *  0b1000..ADC CMD8 selected.
4112  *  0b1001..ADC CMD9 selected.
4113  *  0b1010..ADC CMD10 selected.
4114  *  0b1011..ADC CMD11 selected.
4115  *  0b1100..ADC CMD12 selected.
4116  *  0b1101..ADC CMD13 selected.
4117  *  0b1110..ADC CMD14 selected.
4118  *  0b1111..ADC CMD15 selected.
4119  */
4120 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
4121 
4122 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK       (0xFF0U)
4123 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT      (4U)
4124 /*! HWTS6
4125  *  0b00000000..no trigger selected
4126  *  0b00000001..ADC TRIG0 selected
4127  *  0b00000010..ADC TRIG1 selected
4128  *  0b00000100..ADC TRIG2 selected
4129  *  0b00001000..ADC TRIG3 selected
4130  *  0b00010000..ADC TRIG4 selected
4131  *  0b00100000..ADC TRIG5 selected
4132  *  0b01000000..ADC TRIG6 selected
4133  *  0b10000000..ADC TRIG7 selected
4134  */
4135 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
4136 
4137 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK        (0x1000U)
4138 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT       (12U)
4139 /*! B2B6
4140  *  0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached
4141  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4142  */
4143 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
4144 
4145 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK         (0x6000U)
4146 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT        (13U)
4147 /*! IE6
4148  *  0b00..Generate interrupt on Done0 when segment 6 finish.
4149  *  0b01..Generate interrupt on Done1 when segment 6 finish.
4150  *  0b10..Generate interrupt on Done2 when segment 6 finish.
4151  *  0b11..Generate interrupt on Done3 when segment 6 finish.
4152  */
4153 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
4154 
4155 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK      (0x8000U)
4156 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT     (15U)
4157 /*! IE6_EN
4158  *  0b0..Interrupt DONE disabled.
4159  *  0b1..Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6.
4160  */
4161 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
4162 
4163 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK       (0xF0000U)
4164 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT      (16U)
4165 /*! CSEL7
4166  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4167  *  0b0001..ADC CMD1 selected.
4168  *  0b0010..ADC CMD2 selected.
4169  *  0b0011..ADC CMD3 selected.
4170  *  0b0100..ADC CMD4 selected.
4171  *  0b0101..ADC CMD5 selected.
4172  *  0b0110..ADC CMD6 selected.
4173  *  0b0111..ADC CMD7 selected.
4174  *  0b1000..ADC CMD8 selected.
4175  *  0b1001..ADC CMD9 selected.
4176  *  0b1010..ADC CMD10 selected.
4177  *  0b1011..ADC CMD11 selected.
4178  *  0b1100..ADC CMD12 selected.
4179  *  0b1101..ADC CMD13 selected.
4180  *  0b1110..ADC CMD14 selected.
4181  *  0b1111..ADC CMD15 selected.
4182  */
4183 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
4184 
4185 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK       (0xFF00000U)
4186 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT      (20U)
4187 /*! HWTS7
4188  *  0b00000000..no trigger selected
4189  *  0b00000001..ADC TRIG0 selected
4190  *  0b00000010..ADC TRIG1 selected
4191  *  0b00000100..ADC TRIG2 selected
4192  *  0b00001000..ADC TRIG3 selected
4193  *  0b00010000..ADC TRIG4 selected
4194  *  0b00100000..ADC TRIG5 selected
4195  *  0b01000000..ADC TRIG6 selected
4196  *  0b10000000..ADC TRIG7 selected
4197  */
4198 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
4199 
4200 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK        (0x10000000U)
4201 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT       (28U)
4202 /*! B2B7
4203  *  0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached
4204  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4205  */
4206 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
4207 
4208 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK         (0x60000000U)
4209 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT        (29U)
4210 /*! IE7
4211  *  0b00..Generate interrupt on Done0 when segment 7 finish.
4212  *  0b01..Generate interrupt on Done1 when segment 7 finish.
4213  *  0b10..Generate interrupt on Done2 when segment 7 finish.
4214  *  0b11..Generate interrupt on Done3 when segment 7 finish.
4215  */
4216 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
4217 
4218 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK      (0x80000000U)
4219 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT     (31U)
4220 /*! IE7_EN
4221  *  0b0..Interrupt DONE disabled.
4222  *  0b1..Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7.
4223  */
4224 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
4225 /*! @} */
4226 
4227 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
4228 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT            (8U)
4229 
4230 /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
4231 /*! @{ */
4232 
4233 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK      (0xFFFU)
4234 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT     (0U)
4235 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
4236 
4237 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK      (0xFFF0000U)
4238 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT     (16U)
4239 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
4240 /*! @} */
4241 
4242 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
4243 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT           (8U)
4244 
4245 /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
4246 /*! @{ */
4247 
4248 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK      (0xFFFU)
4249 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT     (0U)
4250 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
4251 
4252 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK      (0xFFF0000U)
4253 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT     (16U)
4254 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
4255 /*! @} */
4256 
4257 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
4258 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT           (8U)
4259 
4260 /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
4261 /*! @{ */
4262 
4263 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK      (0xFFFU)
4264 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT     (0U)
4265 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
4266 
4267 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK      (0xFFF0000U)
4268 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT     (16U)
4269 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
4270 /*! @} */
4271 
4272 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
4273 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT           (8U)
4274 
4275 /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
4276 /*! @{ */
4277 
4278 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK      (0xFFFU)
4279 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT     (0U)
4280 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
4281 
4282 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK      (0xFFF0000U)
4283 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT     (16U)
4284 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
4285 /*! @} */
4286 
4287 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
4288 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT           (8U)
4289 
4290 
4291 /*!
4292  * @}
4293  */ /* end of group ADC_ETC_Register_Masks */
4294 
4295 
4296 /* ADC_ETC - Peripheral instance base addresses */
4297 /** Peripheral ADC_ETC base address */
4298 #define ADC_ETC_BASE                             (0x40048000u)
4299 /** Peripheral ADC_ETC base pointer */
4300 #define ADC_ETC                                  ((ADC_ETC_Type *)ADC_ETC_BASE)
4301 /** Array initializer of ADC_ETC peripheral base addresses */
4302 #define ADC_ETC_BASE_ADDRS                       { ADC_ETC_BASE }
4303 /** Array initializer of ADC_ETC peripheral base pointers */
4304 #define ADC_ETC_BASE_PTRS                        { ADC_ETC }
4305 /** Interrupt vectors for the ADC_ETC peripheral type */
4306 #define ADC_ETC_IRQS                             { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
4307 #define ADC_ETC_FAULT_IRQS                       { ADC_ETC_ERROR_IRQ_IRQn }
4308 
4309 /*!
4310  * @}
4311  */ /* end of group ADC_ETC_Peripheral_Access_Layer */
4312 
4313 
4314 /* ----------------------------------------------------------------------------
4315    -- ANADIG_LDO_SNVS Peripheral Access Layer
4316    ---------------------------------------------------------------------------- */
4317 
4318 /*!
4319  * @addtogroup ANADIG_LDO_SNVS_Peripheral_Access_Layer ANADIG_LDO_SNVS Peripheral Access Layer
4320  * @{
4321  */
4322 
4323 /** ANADIG_LDO_SNVS - Register Layout Typedef */
4324 typedef struct {
4325        uint8_t RESERVED_0[1296];
4326   __IO uint32_t PMU_LDO_LPSR_ANA;                  /**< PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510 */
4327        uint8_t RESERVED_1[12];
4328   __IO uint32_t PMU_LDO_LPSR_DIG_2;                /**< PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520 */
4329        uint8_t RESERVED_2[12];
4330   __IO uint32_t PMU_LDO_LPSR_DIG;                  /**< PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530 */
4331 } ANADIG_LDO_SNVS_Type;
4332 
4333 /* ----------------------------------------------------------------------------
4334    -- ANADIG_LDO_SNVS Register Masks
4335    ---------------------------------------------------------------------------- */
4336 
4337 /*!
4338  * @addtogroup ANADIG_LDO_SNVS_Register_Masks ANADIG_LDO_SNVS Register Masks
4339  * @{
4340  */
4341 
4342 /*! @name PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER */
4343 /*! @{ */
4344 
4345 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U)
4346 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U)
4347 /*! REG_LP_EN - reg_lp_en
4348  */
4349 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK)
4350 
4351 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U)
4352 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U)
4353 /*! REG_DISABLE - reg_disable
4354  */
4355 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK)
4356 
4357 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
4358 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
4359 /*! PULL_DOWN_2MA_EN - pull_down_2ma_en
4360  */
4361 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK)
4362 
4363 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U)
4364 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U)
4365 /*! LPSR_ANA_CONTROL_MODE - LPSR_ANA_CONTROL_MODE
4366  *  0b0..SW Control
4367  *  0b1..HW Control
4368  */
4369 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK)
4370 
4371 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U)
4372 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U)
4373 /*! BYPASS_MODE_EN - bypass_mode_en
4374  */
4375 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK)
4376 
4377 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U)
4378 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U)
4379 /*! STANDBY_EN - standby_en
4380  */
4381 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK)
4382 
4383 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
4384 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
4385 /*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en
4386  */
4387 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
4388 
4389 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U)
4390 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U)
4391 /*! TRACK_MODE_EN - Track Mode Enable
4392  *  0b0..Normal use
4393  *  0b1..Switch preparation
4394  */
4395 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK)
4396 
4397 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
4398 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
4399 /*! PULL_DOWN_20UA_EN - pull_down_20ua_en
4400  */
4401 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK)
4402 /*! @} */
4403 
4404 /*! @name PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER */
4405 /*! @{ */
4406 
4407 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U)
4408 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U)
4409 /*! VOLTAGE_STEP_INC - voltage_step_inc
4410  */
4411 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK)
4412 /*! @} */
4413 
4414 /*! @name PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER */
4415 /*! @{ */
4416 
4417 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U)
4418 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U)
4419 /*! REG_EN - ENABLE_ILIMIT
4420  */
4421 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK)
4422 
4423 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U)
4424 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U)
4425 /*! LPSR_DIG_CONTROL_MODE - LPSR_DIG_CONTROL_MODE
4426  *  0b0..SW Control
4427  *  0b1..HW Control
4428  */
4429 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK)
4430 
4431 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U)
4432 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U)
4433 /*! STANDBY_EN - standby_en
4434  */
4435 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK)
4436 
4437 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U)
4438 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U)
4439 /*! TRACKING_MODE - tracking_mode
4440  */
4441 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK)
4442 
4443 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U)
4444 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U)
4445 /*! BYPASS_MODE - bypass_mode
4446  */
4447 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK)
4448 
4449 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
4450 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U)
4451 /*! VOLTAGE_SELECT - VOLTAGE_SELECT
4452  *  0b00000..Stable Voltage (range)
4453  *  0b00001..Stable Voltage (range)
4454  *  0b00010..Stable Voltage (range)
4455  *  0b00011..Stable Voltage (range)
4456  *  0b00100..Stable Voltage (range)
4457  *  0b00101..Stable Voltage (range)
4458  *  0b00110..Stable Voltage (range)
4459  *  0b00111..Stable Voltage (range)
4460  *  0b01000..Stable Voltage (range)
4461  *  0b01001..Stable Voltage (range)
4462  *  0b01010..Stable Voltage (range)
4463  *  0b01011..Stable Voltage (range)
4464  *  0b01100..Stable Voltage (range)
4465  *  0b01101..Stable Voltage (range)
4466  *  0b01110..Stable Voltage (range)
4467  *  0b01111..Stable Voltage (range)
4468  *  0b10000..Stable Voltage (range)
4469  *  0b10001..Stable Voltage (range)
4470  *  0b10010..Stable Voltage (range)
4471  *  0b10011..Stable Voltage (range)
4472  *  0b10100..Stable Voltage (range)
4473  *  0b10101..Stable Voltage (range)
4474  *  0b10110..Stable Voltage (range)
4475  *  0b10111..Stable Voltage (range)
4476  *  0b11000..Stable Voltage (range)
4477  *  0b11001..Stable Voltage (range)
4478  *  0b11010..Stable Voltage (range)
4479  *  0b11011..Stable Voltage (range)
4480  *  0b11100..Stable Voltage (range)
4481  *  0b11101..Stable Voltage (range)
4482  *  0b11110..Stable Voltage (range)
4483  *  0b11111..Stable Voltage (range)
4484  */
4485 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK)
4486 /*! @} */
4487 
4488 
4489 /*!
4490  * @}
4491  */ /* end of group ANADIG_LDO_SNVS_Register_Masks */
4492 
4493 
4494 /* ANADIG_LDO_SNVS - Peripheral instance base addresses */
4495 /** Peripheral ANADIG_LDO_SNVS base address */
4496 #define ANADIG_LDO_SNVS_BASE                     (0x40C84000u)
4497 /** Peripheral ANADIG_LDO_SNVS base pointer */
4498 #define ANADIG_LDO_SNVS                          ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
4499 /** Array initializer of ANADIG_LDO_SNVS peripheral base addresses */
4500 #define ANADIG_LDO_SNVS_BASE_ADDRS               { ANADIG_LDO_SNVS_BASE }
4501 /** Array initializer of ANADIG_LDO_SNVS peripheral base pointers */
4502 #define ANADIG_LDO_SNVS_BASE_PTRS                { ANADIG_LDO_SNVS }
4503 
4504 /*!
4505  * @}
4506  */ /* end of group ANADIG_LDO_SNVS_Peripheral_Access_Layer */
4507 
4508 
4509 /* ----------------------------------------------------------------------------
4510    -- ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4511    ---------------------------------------------------------------------------- */
4512 
4513 /*!
4514  * @addtogroup ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4515  * @{
4516  */
4517 
4518 /** ANADIG_LDO_SNVS_DIG - Register Layout Typedef */
4519 typedef struct {
4520        uint8_t RESERVED_0[1344];
4521   __IO uint32_t PMU_LDO_SNVS_DIG;                  /**< PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540 */
4522 } ANADIG_LDO_SNVS_DIG_Type;
4523 
4524 /* ----------------------------------------------------------------------------
4525    -- ANADIG_LDO_SNVS_DIG Register Masks
4526    ---------------------------------------------------------------------------- */
4527 
4528 /*!
4529  * @addtogroup ANADIG_LDO_SNVS_DIG_Register_Masks ANADIG_LDO_SNVS_DIG Register Masks
4530  * @{
4531  */
4532 
4533 /*! @name PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER */
4534 /*! @{ */
4535 
4536 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U)
4537 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U)
4538 /*! REG_LP_EN - REG_LP_EN
4539  */
4540 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK)
4541 
4542 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U)
4543 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U)
4544 /*! TEST_OVERRIDE - test_override
4545  */
4546 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK)
4547 
4548 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U)
4549 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U)
4550 /*! REG_EN - REG_EN
4551  */
4552 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK)
4553 /*! @} */
4554 
4555 
4556 /*!
4557  * @}
4558  */ /* end of group ANADIG_LDO_SNVS_DIG_Register_Masks */
4559 
4560 
4561 /* ANADIG_LDO_SNVS_DIG - Peripheral instance base addresses */
4562 /** Peripheral ANADIG_LDO_SNVS_DIG base address */
4563 #define ANADIG_LDO_SNVS_DIG_BASE                 (0x40C84000u)
4564 /** Peripheral ANADIG_LDO_SNVS_DIG base pointer */
4565 #define ANADIG_LDO_SNVS_DIG                      ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
4566 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base addresses */
4567 #define ANADIG_LDO_SNVS_DIG_BASE_ADDRS           { ANADIG_LDO_SNVS_DIG_BASE }
4568 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base pointers */
4569 #define ANADIG_LDO_SNVS_DIG_BASE_PTRS            { ANADIG_LDO_SNVS_DIG }
4570 
4571 /*!
4572  * @}
4573  */ /* end of group ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer */
4574 
4575 
4576 /* ----------------------------------------------------------------------------
4577    -- ANADIG_MISC Peripheral Access Layer
4578    ---------------------------------------------------------------------------- */
4579 
4580 /*!
4581  * @addtogroup ANADIG_MISC_Peripheral_Access_Layer ANADIG_MISC Peripheral Access Layer
4582  * @{
4583  */
4584 
4585 /** ANADIG_MISC - Register Layout Typedef */
4586 typedef struct {
4587        uint8_t RESERVED_0[2048];
4588   __I  uint32_t MISC_DIFPROG;                      /**< Chip Silicon Version Register, offset: 0x800 */
4589        uint8_t RESERVED_1[28];
4590   __IO uint32_t VDDSOC_AI_CTRL;                    /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x820 */
4591        uint8_t RESERVED_2[12];
4592   __IO uint32_t VDDSOC_AI_WDATA;                   /**< VDDSOC_AI_WDATA_REGISTER, offset: 0x830 */
4593        uint8_t RESERVED_3[12];
4594   __I  uint32_t VDDSOC_AI_RDATA;                   /**< VDDSOC_AI_RDATA_REGISTER, offset: 0x840 */
4595        uint8_t RESERVED_4[12];
4596   __IO uint32_t VDDSOC2PLL_AI_CTRL_1G;             /**< VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850 */
4597        uint8_t RESERVED_5[12];
4598   __IO uint32_t VDDSOC2PLL_AI_WDATA_1G;            /**< VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860 */
4599        uint8_t RESERVED_6[12];
4600   __I  uint32_t VDDSOC2PLL_AI_RDATA_1G;            /**< VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870 */
4601        uint8_t RESERVED_7[12];
4602   __IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO;          /**< VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880 */
4603        uint8_t RESERVED_8[12];
4604   __IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO;         /**< VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890 */
4605        uint8_t RESERVED_9[12];
4606   __I  uint32_t VDDSOC2PLL_AI_RDATA_AUDIO;         /**< VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0 */
4607        uint8_t RESERVED_10[12];
4608   __IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO;          /**< VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0 */
4609        uint8_t RESERVED_11[12];
4610   __IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO;         /**< VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0 */
4611        uint8_t RESERVED_12[12];
4612   __I  uint32_t VDDSOC2PLL_AI_RDATA_VIDEO;         /**< VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0 */
4613        uint8_t RESERVED_13[12];
4614   __IO uint32_t VDDLPSR_AI_CTRL;                   /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0 */
4615        uint8_t RESERVED_14[12];
4616   __IO uint32_t VDDLPSR_AI_WDATA;                  /**< VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0 */
4617        uint8_t RESERVED_15[12];
4618   __I  uint32_t VDDLPSR_AI_RDATA_REFTOP;           /**< VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900 */
4619        uint8_t RESERVED_16[12];
4620   __I  uint32_t VDDLPSR_AI_RDATA_TMPSNS;           /**< VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910 */
4621        uint8_t RESERVED_17[12];
4622   __IO uint32_t VDDLPSR_AI400M_CTRL;               /**< VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920 */
4623        uint8_t RESERVED_18[12];
4624   __IO uint32_t VDDLPSR_AI400M_WDATA;              /**< VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930 */
4625        uint8_t RESERVED_19[12];
4626   __I  uint32_t VDDLPSR_AI400M_RDATA;              /**< VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940 */
4627 } ANADIG_MISC_Type;
4628 
4629 /* ----------------------------------------------------------------------------
4630    -- ANADIG_MISC Register Masks
4631    ---------------------------------------------------------------------------- */
4632 
4633 /*!
4634  * @addtogroup ANADIG_MISC_Register_Masks ANADIG_MISC Register Masks
4635  * @{
4636  */
4637 
4638 /*! @name MISC_DIFPROG - Chip Silicon Version Register */
4639 /*! @{ */
4640 
4641 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK     (0xFFFFFFFFU)
4642 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT    (0U)
4643 /*! CHIPID - Chip ID
4644  */
4645 #define ANADIG_MISC_MISC_DIFPROG_CHIPID(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
4646 /*! @} */
4647 
4648 /*! @name VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4649 /*! @{ */
4650 
4651 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)
4652 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)
4653 /*! VDDSOC_AI_ADDR - VDDSOC_AI_ADDR
4654  */
4655 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)
4656 
4657 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)
4658 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)
4659 /*! VDDSOC_AIRWB - VDDSOC_AIRWB
4660  */
4661 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)
4662 /*! @} */
4663 
4664 /*! @name VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER */
4665 /*! @{ */
4666 
4667 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)
4668 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)
4669 /*! VDDSOC_AI_WDATA - VDDSOC_AI_WDATA
4670  */
4671 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)
4672 /*! @} */
4673 
4674 /*! @name VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER */
4675 /*! @{ */
4676 
4677 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)
4678 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)
4679 /*! VDDSOC_AI_RDATA - VDDSOC_AI_RDATA
4680  */
4681 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)
4682 /*! @} */
4683 
4684 /*! @name VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER */
4685 /*! @{ */
4686 
4687 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)
4688 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)
4689 /*! VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G
4690  */
4691 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)
4692 
4693 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)
4694 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)
4695 /*! VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G
4696  */
4697 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)
4698 
4699 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)
4700 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)
4701 /*! VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G
4702  */
4703 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)
4704 
4705 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)
4706 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)
4707 /*! VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G
4708  */
4709 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)
4710 /*! @} */
4711 
4712 /*! @name VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER */
4713 /*! @{ */
4714 
4715 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)
4716 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)
4717 /*! VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G
4718  */
4719 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)
4720 /*! @} */
4721 
4722 /*! @name VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER */
4723 /*! @{ */
4724 
4725 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)
4726 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)
4727 /*! VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G
4728  */
4729 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)
4730 /*! @} */
4731 
4732 /*! @name VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER */
4733 /*! @{ */
4734 
4735 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)
4736 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)
4737 /*! VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO
4738  */
4739 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)
4740 
4741 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)
4742 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)
4743 /*! VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO
4744  */
4745 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)
4746 
4747 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)
4748 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)
4749 /*! VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO
4750  */
4751 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)
4752 
4753 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)
4754 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)
4755 /*! VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB
4756  */
4757 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)
4758 /*! @} */
4759 
4760 /*! @name VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER */
4761 /*! @{ */
4762 
4763 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)
4764 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)
4765 /*! VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO
4766  */
4767 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)
4768 /*! @} */
4769 
4770 /*! @name VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER */
4771 /*! @{ */
4772 
4773 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)
4774 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)
4775 /*! VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO
4776  */
4777 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)
4778 /*! @} */
4779 
4780 /*! @name VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER */
4781 /*! @{ */
4782 
4783 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)
4784 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)
4785 /*! VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO
4786  */
4787 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)
4788 
4789 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)
4790 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)
4791 /*! VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO
4792  */
4793 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)
4794 
4795 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)
4796 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)
4797 /*! VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO
4798  */
4799 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)
4800 
4801 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)
4802 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)
4803 /*! VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO
4804  */
4805 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)
4806 /*! @} */
4807 
4808 /*! @name VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER */
4809 /*! @{ */
4810 
4811 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)
4812 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)
4813 /*! VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO
4814  */
4815 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)
4816 /*! @} */
4817 
4818 /*! @name VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER */
4819 /*! @{ */
4820 
4821 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)
4822 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)
4823 /*! VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO
4824  */
4825 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)
4826 /*! @} */
4827 
4828 /*! @name VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4829 /*! @{ */
4830 
4831 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)
4832 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)
4833 /*! VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR
4834  */
4835 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)
4836 
4837 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)
4838 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)
4839 /*! VDDLPSR_AIRWB - VDDLPSR_AIRWB
4840  */
4841 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)
4842 /*! @} */
4843 
4844 /*! @name VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER */
4845 /*! @{ */
4846 
4847 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)
4848 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)
4849 /*! VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA
4850  */
4851 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)
4852 /*! @} */
4853 
4854 /*! @name VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER */
4855 /*! @{ */
4856 
4857 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)
4858 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)
4859 /*! VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP
4860  */
4861 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)
4862 /*! @} */
4863 
4864 /*! @name VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER */
4865 /*! @{ */
4866 
4867 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)
4868 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)
4869 /*! VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS
4870  */
4871 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)
4872 /*! @} */
4873 
4874 /*! @name VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER */
4875 /*! @{ */
4876 
4877 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)
4878 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)
4879 /*! VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR
4880  */
4881 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)
4882 
4883 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)
4884 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)
4885 /*! VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M
4886  */
4887 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)
4888 
4889 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)
4890 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)
4891 /*! VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M
4892  */
4893 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)
4894 
4895 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)
4896 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)
4897 /*! VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB
4898  */
4899 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)
4900 /*! @} */
4901 
4902 /*! @name VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER */
4903 /*! @{ */
4904 
4905 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)
4906 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)
4907 /*! VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA
4908  */
4909 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)
4910 /*! @} */
4911 
4912 /*! @name VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER */
4913 /*! @{ */
4914 
4915 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)
4916 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)
4917 /*! VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA
4918  */
4919 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)
4920 /*! @} */
4921 
4922 
4923 /*!
4924  * @}
4925  */ /* end of group ANADIG_MISC_Register_Masks */
4926 
4927 
4928 /* ANADIG_MISC - Peripheral instance base addresses */
4929 /** Peripheral ANADIG_MISC base address */
4930 #define ANADIG_MISC_BASE                         (0x40C84000u)
4931 /** Peripheral ANADIG_MISC base pointer */
4932 #define ANADIG_MISC                              ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
4933 /** Array initializer of ANADIG_MISC peripheral base addresses */
4934 #define ANADIG_MISC_BASE_ADDRS                   { ANADIG_MISC_BASE }
4935 /** Array initializer of ANADIG_MISC peripheral base pointers */
4936 #define ANADIG_MISC_BASE_PTRS                    { ANADIG_MISC }
4937 
4938 /*!
4939  * @}
4940  */ /* end of group ANADIG_MISC_Peripheral_Access_Layer */
4941 
4942 
4943 /* ----------------------------------------------------------------------------
4944    -- ANADIG_OSC Peripheral Access Layer
4945    ---------------------------------------------------------------------------- */
4946 
4947 /*!
4948  * @addtogroup ANADIG_OSC_Peripheral_Access_Layer ANADIG_OSC Peripheral Access Layer
4949  * @{
4950  */
4951 
4952 /** ANADIG_OSC - Register Layout Typedef */
4953 typedef struct {
4954        uint8_t RESERVED_0[16];
4955   __IO uint32_t OSC_48M_CTRL;                      /**< 48MHz RCOSC Control Register, offset: 0x10 */
4956        uint8_t RESERVED_1[12];
4957   __IO uint32_t OSC_24M_CTRL;                      /**< 24MHz OSC Control Register, offset: 0x20 */
4958        uint8_t RESERVED_2[28];
4959   __I  uint32_t OSC_400M_CTRL0;                    /**< 400MHz RCOSC Control0 Register, offset: 0x40 */
4960        uint8_t RESERVED_3[12];
4961   __IO uint32_t OSC_400M_CTRL1;                    /**< 400MHz RCOSC Control1 Register, offset: 0x50 */
4962        uint8_t RESERVED_4[12];
4963   __IO uint32_t OSC_400M_CTRL2;                    /**< 400MHz RCOSC Control2 Register, offset: 0x60 */
4964        uint8_t RESERVED_5[92];
4965   __IO uint32_t OSC_16M_CTRL;                      /**< 16MHz RCOSC Control Register, offset: 0xC0 */
4966 } ANADIG_OSC_Type;
4967 
4968 /* ----------------------------------------------------------------------------
4969    -- ANADIG_OSC Register Masks
4970    ---------------------------------------------------------------------------- */
4971 
4972 /*!
4973  * @addtogroup ANADIG_OSC_Register_Masks ANADIG_OSC Register Masks
4974  * @{
4975  */
4976 
4977 /*! @name OSC_48M_CTRL - 48MHz RCOSC Control Register */
4978 /*! @{ */
4979 
4980 #define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK         (0x2U)
4981 #define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT        (1U)
4982 /*! TEN - 48MHz RCOSC Enable
4983  *  0b0..Power down
4984  *  0b1..Power up
4985  */
4986 #define ANADIG_OSC_OSC_48M_CTRL_TEN(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
4987 
4988 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U)
4989 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U)
4990 /*! RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable
4991  *  0b0..Disable
4992  *  0b1..Enable
4993  */
4994 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
4995 
4996 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U)
4997 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U)
4998 /*! RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode
4999  *  0b0..Software mode (default)
5000  *  0b1..GPC mode (Setpoint)
5001  */
5002 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
5003 
5004 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U)
5005 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U)
5006 /*! RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode
5007  *  0b0..Software mode (default)
5008  *  0b1..GPC mode (Setpoint)
5009  */
5010 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)
5011 /*! @} */
5012 
5013 /*! @name OSC_24M_CTRL - 24MHz OSC Control Register */
5014 /*! @{ */
5015 
5016 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK  (0x1U)
5017 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U)
5018 /*! BYPASS_CLK - 24MHz OSC Bypass Clock
5019  */
5020 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
5021 
5022 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
5023 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT  (1U)
5024 /*! BYPASS_EN - 24MHz OSC Bypass Enable
5025  *  0b0..Disable
5026  *  0b1..Enable
5027  */
5028 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
5029 
5030 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK       (0x4U)
5031 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT      (2U)
5032 /*! LP_EN - 24MHz OSC Low-Power Mode Enable
5033  *  0b0..High Gain mode (HP)
5034  *  0b1..Low-power mode (LP)
5035  */
5036 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
5037 
5038 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
5039 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
5040 /*! OSC_COMP_MODE - 24MHz OSC Comparator Mode
5041  *  0b0..Single-ended mode (default)
5042  *  0b1..Differential mode (test mode)
5043  */
5044 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
5045 
5046 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK      (0x10U)
5047 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT     (4U)
5048 /*! OSC_EN - 24MHz OSC Enable
5049  *  0b0..Disable
5050  *  0b1..Enable
5051  */
5052 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
5053 
5054 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
5055 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
5056 /*! OSC_24M_GATE - 24MHz OSC Gate Control
5057  *  0b0..Not Gated
5058  *  0b1..Gated
5059  */
5060 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
5061 
5062 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
5063 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
5064 /*! OSC_24M_STABLE - 24MHz OSC Stable
5065  *  0b0..Not Stable
5066  *  0b1..Stable
5067  */
5068 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
5069 
5070 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
5071 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
5072 /*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode
5073  *  0b0..Software mode (default)
5074  *  0b1..GPC mode (Setpoint)
5075  */
5076 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
5077 /*! @} */
5078 
5079 /*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */
5080 /*! @{ */
5081 
5082 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
5083 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
5084 /*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY
5085  */
5086 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
5087 /*! @} */
5088 
5089 /*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */
5090 /*! @{ */
5091 
5092 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK       (0x1U)
5093 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT      (0U)
5094 /*! PWD - Power down control for 400MHz RCOSC
5095  *  0b0..No Power down
5096  *  0b1..Power down
5097  */
5098 #define ANADIG_OSC_OSC_400M_CTRL1_PWD(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
5099 
5100 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
5101 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
5102 /*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC
5103  *  0b0..Not Gated
5104  *  0b1..Gated
5105  */
5106 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
5107 
5108 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
5109 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
5110 /*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode
5111  *  0b0..Software mode (default)
5112  *  0b1..GPC mode (Setpoint)
5113  */
5114 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
5115 /*! @} */
5116 
5117 /*! @name OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register */
5118 /*! @{ */
5119 
5120 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U)
5121 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U)
5122 /*! ENABLE_CLK - Clock enable
5123  *  0b0..Clock is disabled before entering GPC mode
5124  *  0b1..Clock is enabled before entering GPC mode
5125  */
5126 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
5127 
5128 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK  (0x400U)
5129 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
5130 /*! TUNE_BYP - Bypass tuning logic
5131  *  0b0..Use the output of tuning logic to run the oscillator
5132  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
5133  */
5134 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
5135 
5136 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
5137 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
5138 /*! OSC_TUNE_VAL - Oscillator Tune Value
5139  */
5140 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)
5141 /*! @} */
5142 
5143 /*! @name OSC_16M_CTRL - 16MHz RCOSC Control Register */
5144 /*! @{ */
5145 
5146 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U)
5147 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U)
5148 /*! EN_IRC4M16M - Enable Clock Output
5149  *  0b0..Disable
5150  *  0b1..Enable
5151  */
5152 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
5153 
5154 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U)
5155 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U)
5156 /*! EN_POWER_SAVE - Power Save Enable
5157  *  0b0..Disable
5158  *  0b1..Enable
5159  */
5160 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
5161 
5162 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U)
5163 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U)
5164 /*! SOURCE_SEL_16M - Source select
5165  *  0b0..16MHz Oscillator
5166  *  0b1..24MHz Oscillator
5167  */
5168 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
5169 
5170 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U)
5171 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U)
5172 /*! RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator
5173  *  0b0..Software mode (default)
5174  *  0b1..GPC mode (Setpoint)
5175  */
5176 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)
5177 /*! @} */
5178 
5179 
5180 /*!
5181  * @}
5182  */ /* end of group ANADIG_OSC_Register_Masks */
5183 
5184 
5185 /* ANADIG_OSC - Peripheral instance base addresses */
5186 /** Peripheral ANADIG_OSC base address */
5187 #define ANADIG_OSC_BASE                          (0x40C84000u)
5188 /** Peripheral ANADIG_OSC base pointer */
5189 #define ANADIG_OSC                               ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
5190 /** Array initializer of ANADIG_OSC peripheral base addresses */
5191 #define ANADIG_OSC_BASE_ADDRS                    { ANADIG_OSC_BASE }
5192 /** Array initializer of ANADIG_OSC peripheral base pointers */
5193 #define ANADIG_OSC_BASE_PTRS                     { ANADIG_OSC }
5194 
5195 /*!
5196  * @}
5197  */ /* end of group ANADIG_OSC_Peripheral_Access_Layer */
5198 
5199 
5200 /* ----------------------------------------------------------------------------
5201    -- ANADIG_PLL Peripheral Access Layer
5202    ---------------------------------------------------------------------------- */
5203 
5204 /*!
5205  * @addtogroup ANADIG_PLL_Peripheral_Access_Layer ANADIG_PLL Peripheral Access Layer
5206  * @{
5207  */
5208 
5209 /** ANADIG_PLL - Register Layout Typedef */
5210 typedef struct {
5211        uint8_t RESERVED_0[512];
5212   __IO uint32_t ARM_PLL_CTRL;                      /**< ARM_PLL_CTRL_REGISTER, offset: 0x200 */
5213        uint8_t RESERVED_1[12];
5214   __IO uint32_t SYS_PLL3_CTRL;                     /**< SYS_PLL3_CTRL_REGISTER, offset: 0x210 */
5215        uint8_t RESERVED_2[12];
5216   __IO uint32_t SYS_PLL3_UPDATE;                   /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x220 */
5217        uint8_t RESERVED_3[12];
5218   __IO uint32_t SYS_PLL3_PFD;                      /**< SYS_PLL3_PFD_REGISTER, offset: 0x230 */
5219        uint8_t RESERVED_4[12];
5220   __IO uint32_t SYS_PLL2_CTRL;                     /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */
5221        uint8_t RESERVED_5[12];
5222   __IO uint32_t SYS_PLL2_UPDATE;                   /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x250 */
5223        uint8_t RESERVED_6[12];
5224   __IO uint32_t SYS_PLL2_SS;                       /**< SYS_PLL2_SS_REGISTER, offset: 0x260 */
5225        uint8_t RESERVED_7[12];
5226   __IO uint32_t SYS_PLL2_PFD;                      /**< SYS_PLL2_PFD_REGISTER, offset: 0x270 */
5227        uint8_t RESERVED_8[44];
5228   __IO uint32_t SYS_PLL2_MFD;                      /**< SYS_PLL2_MFD_REGISTER, offset: 0x2A0 */
5229        uint8_t RESERVED_9[12];
5230   __IO uint32_t SYS_PLL1_SS;                       /**< SYS_PLL1_SS_REGISTER, offset: 0x2B0 */
5231        uint8_t RESERVED_10[12];
5232   __IO uint32_t SYS_PLL1_CTRL;                     /**< SYS_PLL1_CTRL_REGISTER, offset: 0x2C0 */
5233        uint8_t RESERVED_11[12];
5234   __IO uint32_t SYS_PLL1_DENOMINATOR;              /**< SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0 */
5235        uint8_t RESERVED_12[12];
5236   __IO uint32_t SYS_PLL1_NUMERATOR;                /**< SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0 */
5237        uint8_t RESERVED_13[12];
5238   __IO uint32_t SYS_PLL1_DIV_SELECT;               /**< SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0 */
5239        uint8_t RESERVED_14[12];
5240   __IO uint32_t PLL_AUDIO_CTRL;                    /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x300 */
5241        uint8_t RESERVED_15[12];
5242   __IO uint32_t PLL_AUDIO_SS;                      /**< PLL_AUDIO_SS_REGISTER, offset: 0x310 */
5243        uint8_t RESERVED_16[12];
5244   __IO uint32_t PLL_AUDIO_DENOMINATOR;             /**< PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320 */
5245        uint8_t RESERVED_17[12];
5246   __IO uint32_t PLL_AUDIO_NUMERATOR;               /**< PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330 */
5247        uint8_t RESERVED_18[12];
5248   __IO uint32_t PLL_AUDIO_DIV_SELECT;              /**< PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340 */
5249        uint8_t RESERVED_19[12];
5250   __IO uint32_t PLL_VIDEO_CTRL;                    /**< PLL_VIDEO_CTRL_REGISTER, offset: 0x350 */
5251        uint8_t RESERVED_20[12];
5252   __IO uint32_t PLL_VIDEO_SS;                      /**< PLL_VIDEO_SS_REGISTER, offset: 0x360 */
5253        uint8_t RESERVED_21[12];
5254   __IO uint32_t PLL_VIDEO_DENOMINATOR;             /**< PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370 */
5255        uint8_t RESERVED_22[12];
5256   __IO uint32_t PLL_VIDEO_NUMERATOR;               /**< PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380 */
5257        uint8_t RESERVED_23[12];
5258   __IO uint32_t PLL_VIDEO_DIV_SELECT;              /**< PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390 */
5259 } ANADIG_PLL_Type;
5260 
5261 /* ----------------------------------------------------------------------------
5262    -- ANADIG_PLL Register Masks
5263    ---------------------------------------------------------------------------- */
5264 
5265 /*!
5266  * @addtogroup ANADIG_PLL_Register_Masks ANADIG_PLL Register Masks
5267  * @{
5268  */
5269 
5270 /*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */
5271 /*! @{ */
5272 
5273 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK  (0xFFU)
5274 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
5275 /*! DIV_SELECT - DIV_SELECT
5276  */
5277 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
5278 
5279 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
5280 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
5281 /*! HOLD_RING_OFF - PLL Start up initialization
5282  *  0b0..Normal operation
5283  *  0b1..Initialize PLL start up
5284  */
5285 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
5286 
5287 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK     (0x2000U)
5288 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT    (13U)
5289 /*! POWERUP - Powers up the PLL.
5290  *  0b1..Power Up the PLL
5291  *  0b0..Power down the PLL
5292  */
5293 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
5294 
5295 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK  (0x4000U)
5296 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
5297 /*! ENABLE_CLK - Enable the clock output.
5298  *  0b0..Disable the clock
5299  *  0b1..Enable the clock
5300  */
5301 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
5302 
5303 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
5304 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
5305 /*! POST_DIV_SEL - POST_DIV_SEL
5306  *  0b00..Divide by 2
5307  *  0b01..Divide by 4
5308  *  0b10..Divide by 8
5309  *  0b11..Divide by 1
5310  */
5311 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
5312 
5313 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK      (0x20000U)
5314 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT     (17U)
5315 /*! BYPASS - Bypass the pll.
5316  *  0b1..Bypass Mode
5317  *  0b0..Function mode
5318  */
5319 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
5320 
5321 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
5322 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
5323 /*! ARM_PLL_STABLE - ARM_PLL_STABLE
5324  *  0b1..ARM PLL is stable
5325  *  0b0..ARM PLL is not stable
5326  */
5327 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
5328 
5329 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
5330 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
5331 /*! ARM_PLL_GATE - ARM_PLL_GATE
5332  *  0b1..Clock is gated
5333  *  0b0..Clock is not gated
5334  */
5335 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
5336 
5337 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
5338 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
5339 /*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode
5340  *  0b0..Software Mode (Default)
5341  *  0b1..GPC Mode
5342  */
5343 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
5344 /*! @} */
5345 
5346 /*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */
5347 /*! @{ */
5348 
5349 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
5350 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
5351 /*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate
5352  */
5353 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
5354 
5355 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
5356 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
5357 /*! PLL_REG_EN - Enable Internal PLL Regulator
5358  */
5359 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
5360 
5361 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
5362 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
5363 /*! HOLD_RING_OFF - PLL Start up initialization
5364  *  0b0..Normal operation
5365  *  0b1..Initialize PLL start up
5366  */
5367 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
5368 
5369 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
5370 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
5371 /*! ENABLE_CLK - Enable the clock output.
5372  *  0b0..Disable the clock
5373  *  0b1..Enable the clock
5374  */
5375 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
5376 
5377 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK     (0x10000U)
5378 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT    (16U)
5379 /*! BYPASS - BYPASS
5380  *  0b1..Bypass Mode
5381  *  0b0..Function mode
5382  */
5383 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
5384 
5385 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK    (0x200000U)
5386 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT   (21U)
5387 /*! POWERUP - Powers up the PLL.
5388  *  0b1..Power Up the PLL
5389  *  0b0..Power down the PLL
5390  */
5391 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
5392 
5393 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
5394 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
5395 /*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE
5396  *  0b0..Software Mode (Default)
5397  *  0b1..GPC Mode
5398  */
5399 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
5400 
5401 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
5402 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
5403 /*! SYS_PLL3_STABLE - SYS_PLL3_STABLE
5404  */
5405 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
5406 
5407 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
5408 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
5409 /*! SYS_PLL3_GATE - SYS_PLL3_GATE
5410  *  0b1..Clock is gated
5411  *  0b0..Clock is not gated
5412  */
5413 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
5414 
5415 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
5416 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
5417 /*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode
5418  *  0b0..Software Mode (Default)
5419  *  0b1..GPC Mode
5420  */
5421 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
5422 /*! @} */
5423 
5424 /*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */
5425 /*! @{ */
5426 
5427 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
5428 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
5429 /*! PFD0_UPDATE - PFD0_OVERRIDE
5430  */
5431 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
5432 
5433 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
5434 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
5435 /*! PFD1_UPDATE - PFD1_OVERRIDE
5436  */
5437 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
5438 
5439 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
5440 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
5441 /*! PFD2_UPDATE - PFD2_OVERRIDE
5442  */
5443 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
5444 
5445 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
5446 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
5447 /*! PFD3_UPDATE - PFD3_UPDATE
5448  */
5449 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
5450 
5451 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5452 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5453 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5454  *  0b0..Software Mode (Default)
5455  *  0b1..GPC Mode
5456  */
5457 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
5458 
5459 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5460 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5461 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5462  *  0b0..Software Mode (Default)
5463  *  0b1..GPC Mode
5464  */
5465 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
5466 
5467 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
5468 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
5469 /*! PDF2_CONTROL_MODE - pdf2_control_mode
5470  *  0b0..Software Mode (Default)
5471  *  0b1..GPC Mode
5472  */
5473 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)
5474 
5475 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5476 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5477 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5478  *  0b0..Software Mode (Default)
5479  *  0b1..GPC Mode
5480  */
5481 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
5482 /*! @} */
5483 
5484 /*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */
5485 /*! @{ */
5486 
5487 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK   (0x3FU)
5488 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT  (0U)
5489 /*! PFD0_FRAC - PFD0_FRAC
5490  */
5491 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
5492 
5493 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
5494 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
5495 /*! PFD0_STABLE - PFD0_STABLE
5496  */
5497 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
5498 
5499 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5500 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5501 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
5502  *  0b1..Fractional divider clock (reference ref_pfd0) is off (power savings
5503  *  0b0..ref_pfd0 fractional divider clock is enabled
5504  */
5505 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
5506 
5507 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK   (0x3F00U)
5508 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT  (8U)
5509 /*! PFD1_FRAC - PFD1_FRAC
5510  */
5511 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
5512 
5513 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
5514 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
5515 /*! PFD1_STABLE - PFD1_STABLE
5516  */
5517 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
5518 
5519 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5520 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5521 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
5522  *  0b1..Fractional divider clock (reference ref_pfd1) is off (power savings)
5523  *  0b0..ref_pfd1 fractional divider clock is enabled
5524  */
5525 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
5526 
5527 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5528 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT  (16U)
5529 /*! PFD2_FRAC - PFD2_FRAC
5530  */
5531 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
5532 
5533 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
5534 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
5535 /*! PFD2_STABLE - PFD2_STABLE
5536  */
5537 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
5538 
5539 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5540 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5541 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
5542  *  0b1..Fractional divider clock (reference ref_pfd2) is off (power savings)
5543  *  0b0..ref_pfd2 fractional divider clock is enabled
5544  */
5545 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
5546 
5547 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5548 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT  (24U)
5549 /*! PFD3_FRAC - PFD3_FRAC
5550  */
5551 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
5552 
5553 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
5554 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
5555 /*! PFD3_STABLE - PFD3_STABLE
5556  */
5557 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
5558 
5559 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5560 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5561 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
5562  *  0b1..Fractional divider clock (reference ref_pfd3) is off (power savings)
5563  *  0b0..ref_pfd3 fractional divider clock is enabled
5564  */
5565 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
5566 /*! @} */
5567 
5568 /*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */
5569 /*! @{ */
5570 
5571 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
5572 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
5573 /*! PLL_REG_EN - Enable Internal PLL Regulator
5574  */
5575 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
5576 
5577 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
5578 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
5579 /*! HOLD_RING_OFF - PLL Start up initialization
5580  *  0b0..Normal operation
5581  *  0b1..Initialize PLL start up
5582  */
5583 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
5584 
5585 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
5586 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
5587 /*! ENABLE_CLK - Enable the clock output.
5588  *  0b0..Disable the clock
5589  *  0b1..Enable the clock
5590  */
5591 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
5592 
5593 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK     (0x10000U)
5594 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT    (16U)
5595 /*! BYPASS - Bypass the pll.
5596  *  0b1..Bypass Mode
5597  *  0b0..Function mode
5598  */
5599 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
5600 
5601 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
5602 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
5603 /*! DITHER_ENABLE - DITHER_ENABLE
5604  *  0b0..Disable Dither
5605  *  0b1..Enable Dither
5606  */
5607 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
5608 
5609 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
5610 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
5611 /*! PFD_OFFSET_EN - PFD_OFFSET_EN
5612  */
5613 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
5614 
5615 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
5616 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
5617 /*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE
5618  */
5619 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
5620 
5621 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK    (0x800000U)
5622 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT   (23U)
5623 /*! POWERUP - Powers up the PLL.
5624  *  0b1..Power Up the PLL
5625  *  0b0..Power down the PLL
5626  */
5627 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
5628 
5629 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
5630 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
5631 /*! SYS_PLL2_STABLE - SYS_PLL2_STABLE
5632  */
5633 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
5634 
5635 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
5636 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
5637 /*! SYS_PLL2_GATE - SYS_PLL2_GATE
5638  *  0b1..Clock is gated
5639  *  0b0..Clock is not gated
5640  */
5641 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
5642 
5643 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
5644 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
5645 /*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode
5646  *  0b0..Software Mode (Default)
5647  *  0b1..GPC Mode
5648  */
5649 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
5650 /*! @} */
5651 
5652 /*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */
5653 /*! @{ */
5654 
5655 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
5656 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
5657 /*! PFD0_UPDATE - PFD0_UPDATE
5658  */
5659 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
5660 
5661 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
5662 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
5663 /*! PFD1_UPDATE - PFD1_UPDATE
5664  */
5665 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
5666 
5667 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
5668 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
5669 /*! PFD2_UPDATE - PFD2_UPDATE
5670  */
5671 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
5672 
5673 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
5674 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
5675 /*! PFD3_UPDATE - PFD3_UPDATE
5676  */
5677 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
5678 
5679 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5680 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5681 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5682  *  0b0..Software Mode (Default)
5683  *  0b1..GPC Mode
5684  */
5685 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
5686 
5687 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5688 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5689 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5690  *  0b0..Software Mode (Default)
5691  *  0b1..GPC Mode
5692  */
5693 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
5694 
5695 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
5696 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
5697 /*! PFD2_CONTROL_MODE - pfd2_control_mode
5698  *  0b0..Software Mode (Default)
5699  *  0b1..GPC Mode
5700  */
5701 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
5702 
5703 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5704 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5705 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5706  *  0b0..Software Mode (Default)
5707  *  0b1..GPC Mode
5708  */
5709 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
5710 /*! @} */
5711 
5712 /*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */
5713 /*! @{ */
5714 
5715 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK         (0x7FFFU)
5716 #define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT        (0U)
5717 /*! STEP - STEP
5718  */
5719 #define ANADIG_PLL_SYS_PLL2_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
5720 
5721 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK       (0x8000U)
5722 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT      (15U)
5723 /*! ENABLE - ENABLE
5724  *  0b1..Enable Spread Spectrum
5725  *  0b0..Disable Spread Spectrum
5726  */
5727 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
5728 
5729 #define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK         (0xFFFF0000U)
5730 #define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT        (16U)
5731 /*! STOP - STOP
5732  */
5733 #define ANADIG_PLL_SYS_PLL2_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
5734 /*! @} */
5735 
5736 /*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */
5737 /*! @{ */
5738 
5739 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK   (0x3FU)
5740 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT  (0U)
5741 /*! PFD0_FRAC - PFD0_FRAC
5742  */
5743 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
5744 
5745 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
5746 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
5747 /*! PFD0_STABLE - PFD0_STABLE
5748  */
5749 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
5750 
5751 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5752 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5753 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
5754  */
5755 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
5756 
5757 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK   (0x3F00U)
5758 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT  (8U)
5759 /*! PFD1_FRAC - PFD1_FRAC
5760  */
5761 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
5762 
5763 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
5764 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
5765 /*! PFD1_STABLE - PFD1_STABLE
5766  */
5767 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
5768 
5769 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5770 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5771 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
5772  */
5773 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
5774 
5775 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5776 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT  (16U)
5777 /*! PFD2_FRAC - PFD2_FRAC
5778  */
5779 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
5780 
5781 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
5782 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
5783 /*! PFD2_STABLE - PFD2_STABLE
5784  */
5785 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
5786 
5787 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5788 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5789 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
5790  */
5791 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
5792 
5793 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5794 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT  (24U)
5795 /*! PFD3_FRAC - PFD3_FRAC
5796  */
5797 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
5798 
5799 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
5800 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
5801 /*! PFD3_STABLE - PFD3_STABLE
5802  */
5803 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
5804 
5805 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5806 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5807 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
5808  */
5809 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
5810 /*! @} */
5811 
5812 /*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */
5813 /*! @{ */
5814 
5815 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK         (0x3FFFFFFFU)
5816 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT        (0U)
5817 /*! MFD - Denominator
5818  */
5819 #define ANADIG_PLL_SYS_PLL2_MFD_MFD(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
5820 /*! @} */
5821 
5822 /*! @name SYS_PLL1_SS - SYS_PLL1_SS_REGISTER */
5823 /*! @{ */
5824 
5825 #define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK         (0x7FFFU)
5826 #define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT        (0U)
5827 /*! STEP - STEP
5828  */
5829 #define ANADIG_PLL_SYS_PLL1_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)
5830 
5831 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK       (0x8000U)
5832 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT      (15U)
5833 /*! ENABLE - ENABLE
5834  *  0b1..Enable Spread Spectrum
5835  *  0b0..Disable Spread Spectrum
5836  */
5837 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)
5838 
5839 #define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK         (0xFFFF0000U)
5840 #define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT        (16U)
5841 /*! STOP - STOP
5842  */
5843 #define ANADIG_PLL_SYS_PLL1_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)
5844 /*! @} */
5845 
5846 /*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */
5847 /*! @{ */
5848 
5849 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
5850 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
5851 /*! ENABLE_CLK - ENABLE_CLK
5852  */
5853 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
5854 
5855 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
5856 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
5857 /*! SYS_PLL1_GATE - SYS_PLL1_GATE
5858  *  0b1..Gate the output
5859  *  0b0..No gate
5860  */
5861 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
5862 
5863 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
5864 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
5865 /*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2
5866  */
5867 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
5868 
5869 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
5870 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
5871 /*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5
5872  */
5873 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
5874 
5875 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
5876 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
5877 /*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE
5878  *  0b0..Software Mode (Default)
5879  *  0b1..GPC Mode
5880  */
5881 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
5882 
5883 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
5884 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
5885 /*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE
5886  *  0b0..Software Mode (Default)
5887  *  0b1..GPC Mode
5888  */
5889 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
5890 
5891 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
5892 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
5893 /*! SYS_PLL1_STABLE - SYS_PLL1_STABLE
5894  */
5895 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
5896 
5897 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
5898 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
5899 /*! SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY
5900  */
5901 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)
5902 
5903 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
5904 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
5905 /*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE
5906  *  0b0..Software Mode (Default)
5907  *  0b1..GPC Mode
5908  */
5909 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
5910 /*! @} */
5911 
5912 /*! @name SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER */
5913 /*! @{ */
5914 
5915 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
5916 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
5917 /*! DENOM - DENOM
5918  */
5919 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)
5920 /*! @} */
5921 
5922 /*! @name SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER */
5923 /*! @{ */
5924 
5925 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
5926 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT  (0U)
5927 /*! NUM - NUM
5928  */
5929 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)
5930 /*! @} */
5931 
5932 /*! @name SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER */
5933 /*! @{ */
5934 
5935 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
5936 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
5937 /*! DIV_SELECT - DIV_SELECT
5938  */
5939 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)
5940 /*! @} */
5941 
5942 /*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */
5943 /*! @{ */
5944 
5945 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
5946 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
5947 /*! ENABLE_CLK - ENABLE_CLK
5948  */
5949 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
5950 
5951 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
5952 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
5953 /*! PLL_AUDIO_GATE - PLL_AUDIO_GATE
5954  *  0b1..Gate the output
5955  *  0b0..No gate
5956  */
5957 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
5958 
5959 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
5960 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
5961 /*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE
5962  */
5963 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
5964 
5965 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
5966 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
5967 /*! PLL_AUDIO_AI_BUSY - pll_audio_ai_busy
5968  */
5969 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)
5970 
5971 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
5972 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
5973 /*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode
5974  *  0b0..Software Mode (Default)
5975  *  0b1..GPC Mode
5976  */
5977 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
5978 /*! @} */
5979 
5980 /*! @name PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER */
5981 /*! @{ */
5982 
5983 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK        (0x7FFFU)
5984 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT       (0U)
5985 /*! STEP - STEP
5986  */
5987 #define ANADIG_PLL_PLL_AUDIO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)
5988 
5989 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK      (0x8000U)
5990 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT     (15U)
5991 /*! ENABLE - ENABLE
5992  *  0b1..Enable Spread Spectrum
5993  *  0b0..Disable Spread Spectrum
5994  */
5995 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)
5996 
5997 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK        (0xFFFF0000U)
5998 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT       (16U)
5999 /*! STOP - STOP
6000  */
6001 #define ANADIG_PLL_PLL_AUDIO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)
6002 /*! @} */
6003 
6004 /*! @name PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER */
6005 /*! @{ */
6006 
6007 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6008 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
6009 /*! DENOM - DENOM
6010  */
6011 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)
6012 /*! @} */
6013 
6014 /*! @name PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER */
6015 /*! @{ */
6016 
6017 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
6018 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
6019 /*! NUM - NUM
6020  */
6021 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)
6022 /*! @} */
6023 
6024 /*! @name PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER */
6025 /*! @{ */
6026 
6027 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6028 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6029 /*! PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT
6030  */
6031 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)
6032 /*! @} */
6033 
6034 /*! @name PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER */
6035 /*! @{ */
6036 
6037 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
6038 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
6039 /*! ENABLE_CLK - ENABLE_CLK
6040  */
6041 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)
6042 
6043 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
6044 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
6045 /*! PLL_VIDEO_GATE - PLL_VIDEO_GATE
6046  *  0b1..Gate the output
6047  *  0b0..No gate
6048  */
6049 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)
6050 
6051 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
6052 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
6053 /*! PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr
6054  */
6055 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)
6056 
6057 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
6058 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
6059 /*! PLL_VIDEO_STABLE - PLL_VIDEO_STABLE
6060  */
6061 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)
6062 
6063 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
6064 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
6065 /*! PLL_VIDEO_AI_BUSY - pll_video_ai_busy
6066  */
6067 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)
6068 
6069 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
6070 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
6071 /*! PLL_VIDEO_CONTROL_MODE - pll_video_control_mode
6072  *  0b0..Software Mode (Default)
6073  *  0b1..GPC Mode
6074  */
6075 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)
6076 /*! @} */
6077 
6078 /*! @name PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER */
6079 /*! @{ */
6080 
6081 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK        (0x7FFFU)
6082 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT       (0U)
6083 /*! STEP - STEP
6084  */
6085 #define ANADIG_PLL_PLL_VIDEO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)
6086 
6087 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK      (0x8000U)
6088 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT     (15U)
6089 /*! ENABLE - ENABLE
6090  *  0b1..Enable Spread Spectrum
6091  *  0b0..Disable Spread Spectrum
6092  */
6093 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)
6094 
6095 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK        (0xFFFF0000U)
6096 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT       (16U)
6097 /*! STOP - STOP
6098  */
6099 #define ANADIG_PLL_PLL_VIDEO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)
6100 /*! @} */
6101 
6102 /*! @name PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER */
6103 /*! @{ */
6104 
6105 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6106 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
6107 /*! DENOM - DENOM
6108  */
6109 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)
6110 /*! @} */
6111 
6112 /*! @name PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER */
6113 /*! @{ */
6114 
6115 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
6116 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
6117 /*! NUM - NUM
6118  */
6119 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)
6120 /*! @} */
6121 
6122 /*! @name PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER */
6123 /*! @{ */
6124 
6125 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
6126 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
6127 /*! DIV_SELECT - DIV_SELECT
6128  */
6129 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)
6130 /*! @} */
6131 
6132 
6133 /*!
6134  * @}
6135  */ /* end of group ANADIG_PLL_Register_Masks */
6136 
6137 
6138 /* ANADIG_PLL - Peripheral instance base addresses */
6139 /** Peripheral ANADIG_PLL base address */
6140 #define ANADIG_PLL_BASE                          (0x40C84000u)
6141 /** Peripheral ANADIG_PLL base pointer */
6142 #define ANADIG_PLL                               ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
6143 /** Array initializer of ANADIG_PLL peripheral base addresses */
6144 #define ANADIG_PLL_BASE_ADDRS                    { ANADIG_PLL_BASE }
6145 /** Array initializer of ANADIG_PLL peripheral base pointers */
6146 #define ANADIG_PLL_BASE_PTRS                     { ANADIG_PLL }
6147 
6148 /*!
6149  * @}
6150  */ /* end of group ANADIG_PLL_Peripheral_Access_Layer */
6151 
6152 
6153 /* ----------------------------------------------------------------------------
6154    -- ANADIG_PMU Peripheral Access Layer
6155    ---------------------------------------------------------------------------- */
6156 
6157 /*!
6158  * @addtogroup ANADIG_PMU_Peripheral_Access_Layer ANADIG_PMU Peripheral Access Layer
6159  * @{
6160  */
6161 
6162 /** ANADIG_PMU - Register Layout Typedef */
6163 typedef struct {
6164        uint8_t RESERVED_0[1280];
6165   __IO uint32_t PMU_LDO_PLL;                       /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */
6166        uint8_t RESERVED_1[76];
6167   __IO uint32_t PMU_BIAS_CTRL;                     /**< PMU_BIAS_CTRL_REGISTER, offset: 0x550 */
6168        uint8_t RESERVED_2[12];
6169   __IO uint32_t PMU_BIAS_CTRL2;                    /**< PMU_BIAS_CTRL2_REGISTER, offset: 0x560 */
6170        uint8_t RESERVED_3[12];
6171   __IO uint32_t PMU_REF_CTRL;                      /**< PMU_REF_CTRL_REGISTER, offset: 0x570 */
6172        uint8_t RESERVED_4[12];
6173   __IO uint32_t PMU_POWER_DETECT_CTRL;             /**< PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580 */
6174        uint8_t RESERVED_5[124];
6175   __IO uint32_t LDO_PLL_ENABLE_SP;                 /**< LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600 */
6176        uint8_t RESERVED_6[12];
6177   __IO uint32_t LDO_LPSR_ANA_ENABLE_SP;            /**< LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610 */
6178        uint8_t RESERVED_7[12];
6179   __IO uint32_t LDO_LPSR_ANA_LP_MODE_SP;           /**< LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620 */
6180        uint8_t RESERVED_8[12];
6181   __IO uint32_t LDO_LPSR_ANA_TRACKING_EN_SP;       /**< LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630 */
6182        uint8_t RESERVED_9[12];
6183   __IO uint32_t LDO_LPSR_ANA_BYPASS_EN_SP;         /**< LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640 */
6184        uint8_t RESERVED_10[12];
6185   __IO uint32_t LDO_LPSR_ANA_STBY_EN_SP;           /**< LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650 */
6186        uint8_t RESERVED_11[12];
6187   __IO uint32_t LDO_LPSR_DIG_ENABLE_SP;            /**< LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660 */
6188        uint8_t RESERVED_12[12];
6189   __IO uint32_t LDO_LPSR_DIG_TRG_SP0;              /**< LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670 */
6190        uint8_t RESERVED_13[12];
6191   __IO uint32_t LDO_LPSR_DIG_TRG_SP1;              /**< LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680 */
6192        uint8_t RESERVED_14[12];
6193   __IO uint32_t LDO_LPSR_DIG_TRG_SP2;              /**< LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690 */
6194        uint8_t RESERVED_15[12];
6195   __IO uint32_t LDO_LPSR_DIG_TRG_SP3;              /**< LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0 */
6196        uint8_t RESERVED_16[12];
6197   __IO uint32_t LDO_LPSR_DIG_LP_MODE_SP;           /**< LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0 */
6198        uint8_t RESERVED_17[12];
6199   __IO uint32_t LDO_LPSR_DIG_TRACKING_EN_SP;       /**< LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0 */
6200        uint8_t RESERVED_18[12];
6201   __IO uint32_t LDO_LPSR_DIG_BYPASS_EN_SP;         /**< LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0 */
6202        uint8_t RESERVED_19[12];
6203   __IO uint32_t LDO_LPSR_DIG_STBY_EN_SP;           /**< LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0 */
6204        uint8_t RESERVED_20[12];
6205   __IO uint32_t BANDGAP_ENABLE_SP;                 /**< BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0 */
6206        uint8_t RESERVED_21[12];
6207   __IO uint32_t FBB_M7_ENABLE_SP;                  /**< FBB_M7_ENABLE_SP_REGISTER, offset: 0x700 */
6208        uint8_t RESERVED_22[12];
6209   __IO uint32_t RBB_SOC_ENABLE_SP;                 /**< RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710 */
6210        uint8_t RESERVED_23[12];
6211   __IO uint32_t RBB_LPSR_ENABLE_SP;                /**< RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720 */
6212        uint8_t RESERVED_24[12];
6213   __IO uint32_t BANDGAP_STBY_EN_SP;                /**< BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730 */
6214        uint8_t RESERVED_25[12];
6215   __IO uint32_t PLL_LDO_STBY_EN_SP;                /**< PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740 */
6216        uint8_t RESERVED_26[12];
6217   __IO uint32_t FBB_M7_STBY_EN_SP;                 /**< FBB_M7_STBY_EN_SP_REGISTER, offset: 0x750 */
6218        uint8_t RESERVED_27[12];
6219   __IO uint32_t RBB_SOC_STBY_EN_SP;                /**< RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760 */
6220        uint8_t RESERVED_28[12];
6221   __IO uint32_t RBB_LPSR_STBY_EN_SP;               /**< RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770 */
6222        uint8_t RESERVED_29[12];
6223   __IO uint32_t FBB_M7_CONFIGURE;                  /**< FBB_M7_CONFIGURE_REGISTER, offset: 0x780 */
6224        uint8_t RESERVED_30[12];
6225   __IO uint32_t RBB_LPSR_CONFIGURE;                /**< RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790 */
6226        uint8_t RESERVED_31[12];
6227   __IO uint32_t RBB_SOC_CONFIGURE;                 /**< RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0 */
6228        uint8_t RESERVED_32[12];
6229   __I  uint32_t REFTOP_OTP_TRIM_VALUE;             /**< REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0 */
6230        uint8_t RESERVED_33[28];
6231   __I  uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE;       /**< LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0 */
6232 } ANADIG_PMU_Type;
6233 
6234 /* ----------------------------------------------------------------------------
6235    -- ANADIG_PMU Register Masks
6236    ---------------------------------------------------------------------------- */
6237 
6238 /*!
6239  * @addtogroup ANADIG_PMU_Register_Masks ANADIG_PMU Register Masks
6240  * @{
6241  */
6242 
6243 /*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */
6244 /*! @{ */
6245 
6246 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U)
6247 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U)
6248 /*! LDO_PLL_ENABLE - LDO_PLL_ENABLE
6249  */
6250 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK)
6251 
6252 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
6253 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
6254 /*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE
6255  *  0b0..SW Control
6256  *  0b1..HW Control
6257  */
6258 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
6259 
6260 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U)
6261 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U)
6262 /*! LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle
6263  */
6264 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK)
6265 
6266 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U)
6267 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U)
6268 /*! LDO_PLL_AI_BUSY - ldo_pll_busy
6269  */
6270 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK)
6271 /*! @} */
6272 
6273 /*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */
6274 /*! @{ */
6275 
6276 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
6277 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
6278 /*! WB_CFG_1P8 - wb_cfg_1p8
6279  */
6280 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
6281 
6282 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
6283 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
6284 /*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8
6285  *  0b0..VDD_LV1
6286  *  0b1..VDD_LV2
6287  */
6288 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
6289 /*! @} */
6290 
6291 /*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */
6292 /*! @{ */
6293 
6294 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU)
6295 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U)
6296 /*! WB_TST_MD - TMOD_wb_tst_md_1p8
6297  */
6298 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK)
6299 
6300 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U)
6301 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U)
6302 /*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8
6303  *  0b001..No BB
6304  *  0b010..BB
6305  *  0b100..BB
6306  */
6307 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
6308 
6309 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
6310 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
6311 /*! WB_ADJ_1P8 - wb_adj_1p8
6312  *  0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF
6313  *  0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF
6314  *  0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF
6315  *  0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF
6316  *  0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF
6317  *  0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF
6318  *  0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF
6319  *  0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF
6320  *  0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF
6321  *  0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF
6322  *  0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF
6323  *  0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF
6324  *  0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF
6325  *  0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF
6326  *  0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF
6327  *  0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
6328  */
6329 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
6330 
6331 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK (0x200000U)
6332 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT (21U)
6333 /*! FBB_M7_CONTROL_MODE - FBB_M7_CONTROL_MODE
6334  *  0b0..SW Control
6335  *  0b1..HW Control
6336  */
6337 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
6338 
6339 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U)
6340 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U)
6341 /*! RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE
6342  *  0b0..SW Control
6343  *  0b1..HW Control
6344  */
6345 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK)
6346 
6347 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U)
6348 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U)
6349 /*! RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE
6350  *  0b0..SW Control
6351  *  0b1..HW Control
6352  */
6353 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK)
6354 
6355 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK     (0x1000000U)
6356 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT    (24U)
6357 /*! WB_EN - wb_en
6358  */
6359 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
6360 
6361 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U)
6362 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U)
6363 /*! WB_TST_DIG_OUT - Digital output
6364  */
6365 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK)
6366 
6367 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK     (0x4000000U)
6368 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT    (26U)
6369 /*! WB_OK - Digital Output pin.
6370  */
6371 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
6372 /*! @} */
6373 
6374 /*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */
6375 /*! @{ */
6376 
6377 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U)
6378 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U)
6379 /*! REF_AI_TOGGLE - ref_ai_toggle
6380  */
6381 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK)
6382 
6383 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U)
6384 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U)
6385 /*! REF_AI_BUSY - ref_ai_busy
6386  */
6387 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK)
6388 
6389 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK  (0x4U)
6390 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U)
6391 /*! REF_ENABLE - REF_ENABLE
6392  */
6393 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK)
6394 
6395 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
6396 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
6397 /*! REF_CONTROL_MODE - REF_CONTROL_MODE
6398  *  0b0..SW Control
6399  *  0b1..HW Control
6400  */
6401 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
6402 
6403 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
6404 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
6405 /*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer
6406  */
6407 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
6408 /*! @} */
6409 
6410 /*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */
6411 /*! @{ */
6412 
6413 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U)
6414 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U)
6415 /*! CKGB_LPSR1P0 - ckgb_lpsr1p0
6416  */
6417 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK)
6418 /*! @} */
6419 
6420 /*! @name LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER */
6421 /*! @{ */
6422 
6423 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6424 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6425 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6426  *  0b0..ON
6427  *  0b1..OFF
6428  */
6429 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6430 
6431 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6432 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6433 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6434  *  0b0..ON
6435  *  0b1..OFF
6436  */
6437 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6438 
6439 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6440 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6441 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6442  *  0b0..ON
6443  *  0b1..OFF
6444  */
6445 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6446 
6447 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6448 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6449 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6450  *  0b0..ON
6451  *  0b1..OFF
6452  */
6453 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6454 
6455 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6456 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6457 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6458  *  0b0..ON
6459  *  0b1..OFF
6460  */
6461 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6462 
6463 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6464 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6465 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6466  *  0b0..ON
6467  *  0b1..OFF
6468  */
6469 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6470 
6471 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6472 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6473 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6474  *  0b0..ON
6475  *  0b1..OFF
6476  */
6477 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6478 
6479 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6480 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6481 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6482  *  0b0..ON
6483  *  0b1..OFF
6484  */
6485 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6486 
6487 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6488 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6489 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6490  *  0b0..ON
6491  *  0b1..OFF
6492  */
6493 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6494 
6495 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6496 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6497 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6498  *  0b0..ON
6499  *  0b1..OFF
6500  */
6501 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6502 
6503 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6504 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6505 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6506  *  0b0..ON
6507  *  0b1..OFF
6508  */
6509 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6510 
6511 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6512 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6513 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6514  *  0b0..ON
6515  *  0b1..OFF
6516  */
6517 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6518 
6519 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6520 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6521 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6522  *  0b0..ON
6523  *  0b1..OFF
6524  */
6525 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6526 
6527 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6528 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6529 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6530  *  0b0..ON
6531  *  0b1..OFF
6532  */
6533 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6534 
6535 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6536 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6537 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6538  *  0b0..ON
6539  *  0b1..OFF
6540  */
6541 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6542 
6543 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6544 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6545 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6546  *  0b0..ON
6547  *  0b1..OFF
6548  */
6549 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6550 /*! @} */
6551 
6552 /*! @name LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER */
6553 /*! @{ */
6554 
6555 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6556 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6557 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6558  *  0b0..ON
6559  *  0b1..OFF
6560  */
6561 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6562 
6563 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6564 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6565 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6566  *  0b0..ON
6567  *  0b1..OFF
6568  */
6569 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6570 
6571 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6572 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6573 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6574  *  0b0..ON
6575  *  0b1..OFF
6576  */
6577 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6578 
6579 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6580 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6581 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6582  *  0b0..ON
6583  *  0b1..OFF
6584  */
6585 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6586 
6587 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6588 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6589 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6590  *  0b0..ON
6591  *  0b1..OFF
6592  */
6593 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6594 
6595 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6596 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6597 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6598  *  0b0..ON
6599  *  0b1..OFF
6600  */
6601 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6602 
6603 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6604 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6605 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6606  *  0b0..ON
6607  *  0b1..OFF
6608  */
6609 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6610 
6611 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6612 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6613 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6614  *  0b0..ON
6615  *  0b1..OFF
6616  */
6617 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6618 
6619 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6620 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6621 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6622  *  0b0..ON
6623  *  0b1..OFF
6624  */
6625 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6626 
6627 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6628 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6629 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6630  *  0b0..ON
6631  *  0b1..OFF
6632  */
6633 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6634 
6635 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6636 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6637 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6638  *  0b0..ON
6639  *  0b1..OFF
6640  */
6641 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6642 
6643 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6644 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6645 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6646  *  0b0..ON
6647  *  0b1..OFF
6648  */
6649 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6650 
6651 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6652 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6653 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6654  *  0b0..ON
6655  *  0b1..OFF
6656  */
6657 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6658 
6659 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6660 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6661 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6662  *  0b0..ON
6663  *  0b1..OFF
6664  */
6665 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6666 
6667 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6668 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6669 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6670  *  0b0..ON
6671  *  0b1..OFF
6672  */
6673 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6674 
6675 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6676 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6677 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6678  *  0b0..ON
6679  *  0b1..OFF
6680  */
6681 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6682 /*! @} */
6683 
6684 /*! @name LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER */
6685 /*! @{ */
6686 
6687 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
6688 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
6689 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
6690  *  0b0..LP
6691  *  0b1..HP
6692  */
6693 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
6694 
6695 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
6696 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
6697 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
6698  *  0b0..LP
6699  *  0b1..HP
6700  */
6701 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
6702 
6703 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U)
6704 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U)
6705 /*! LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2
6706  *  0b0..LP
6707  *  0b1..HP
6708  */
6709 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK)
6710 
6711 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U)
6712 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U)
6713 /*! LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3
6714  *  0b0..LP
6715  *  0b1..HP
6716  */
6717 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK)
6718 
6719 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U)
6720 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U)
6721 /*! LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4
6722  *  0b0..LP
6723  *  0b1..HP
6724  */
6725 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK)
6726 
6727 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U)
6728 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U)
6729 /*! LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5
6730  *  0b0..LP
6731  *  0b1..HP
6732  */
6733 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK)
6734 
6735 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U)
6736 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U)
6737 /*! LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6
6738  *  0b0..LP
6739  *  0b1..HP
6740  */
6741 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK)
6742 
6743 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U)
6744 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U)
6745 /*! LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7
6746  *  0b0..LP
6747  *  0b1..HP
6748  */
6749 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK)
6750 
6751 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U)
6752 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U)
6753 /*! LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8
6754  *  0b0..LP
6755  *  0b1..HP
6756  */
6757 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK)
6758 
6759 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U)
6760 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U)
6761 /*! LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9
6762  *  0b0..LP
6763  *  0b1..HP
6764  */
6765 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK)
6766 
6767 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U)
6768 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U)
6769 /*! LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10
6770  *  0b0..LP
6771  *  0b1..HP
6772  */
6773 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK)
6774 
6775 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U)
6776 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U)
6777 /*! LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11
6778  *  0b0..LP
6779  *  0b1..HP
6780  */
6781 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK)
6782 
6783 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U)
6784 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U)
6785 /*! LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12
6786  *  0b0..LP
6787  *  0b1..HP
6788  */
6789 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK)
6790 
6791 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U)
6792 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U)
6793 /*! LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13
6794  *  0b0..LP
6795  *  0b1..HP
6796  */
6797 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK)
6798 
6799 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U)
6800 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U)
6801 /*! LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14
6802  *  0b0..LP
6803  *  0b1..HP
6804  */
6805 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK)
6806 
6807 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U)
6808 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U)
6809 /*! LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15
6810  *  0b0..LP
6811  *  0b1..HP
6812  */
6813 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK)
6814 /*! @} */
6815 
6816 /*! @name LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER */
6817 /*! @{ */
6818 
6819 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
6820 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
6821 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
6822  *  0b0..Disabled
6823  *  0b1..Enabled
6824  */
6825 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
6826 
6827 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
6828 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
6829 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
6830  *  0b0..Disabled
6831  *  0b1..Enabled
6832  */
6833 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
6834 
6835 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
6836 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
6837 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
6838  *  0b0..Disabled
6839  *  0b1..Enabled
6840  */
6841 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
6842 
6843 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
6844 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
6845 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
6846  *  0b0..Disabled
6847  *  0b1..Enabled
6848  */
6849 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
6850 
6851 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
6852 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
6853 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
6854  *  0b0..Disabled
6855  *  0b1..Enabled
6856  */
6857 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
6858 
6859 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
6860 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
6861 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
6862  *  0b0..Disabled
6863  *  0b1..Enabled
6864  */
6865 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
6866 
6867 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
6868 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
6869 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
6870  *  0b0..Disabled
6871  *  0b1..Enabled
6872  */
6873 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
6874 
6875 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
6876 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
6877 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
6878  *  0b0..Disabled
6879  *  0b1..Enabled
6880  */
6881 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
6882 
6883 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
6884 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
6885 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
6886  *  0b0..Disabled
6887  *  0b1..Enabled
6888  */
6889 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
6890 
6891 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
6892 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
6893 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
6894  *  0b0..Disabled
6895  *  0b1..Enabled
6896  */
6897 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
6898 
6899 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
6900 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
6901 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
6902  *  0b0..Disabled
6903  *  0b1..Enabled
6904  */
6905 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
6906 
6907 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
6908 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
6909 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
6910  *  0b0..Disabled
6911  *  0b1..Enabled
6912  */
6913 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
6914 
6915 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
6916 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
6917 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
6918  *  0b0..Disabled
6919  *  0b1..Enabled
6920  */
6921 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
6922 
6923 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
6924 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
6925 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
6926  *  0b0..Disabled
6927  *  0b1..Enabled
6928  */
6929 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
6930 
6931 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
6932 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
6933 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
6934  *  0b0..Disabled
6935  *  0b1..Enabled
6936  */
6937 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
6938 
6939 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
6940 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
6941 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
6942  *  0b0..Disabled
6943  *  0b1..Enabled
6944  */
6945 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
6946 /*! @} */
6947 
6948 /*! @name LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER */
6949 /*! @{ */
6950 
6951 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
6952 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
6953 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
6954  *  0b0..Disabled
6955  *  0b1..Enabled
6956  */
6957 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
6958 
6959 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
6960 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
6961 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
6962  *  0b0..Disabled
6963  *  0b1..Enabled
6964  */
6965 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
6966 
6967 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
6968 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
6969 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
6970  *  0b0..Disabled
6971  *  0b1..Enabled
6972  */
6973 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
6974 
6975 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
6976 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
6977 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
6978  *  0b0..Disabled
6979  *  0b1..Enabled
6980  */
6981 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
6982 
6983 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
6984 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
6985 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
6986  *  0b0..Disabled
6987  *  0b1..Enabled
6988  */
6989 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
6990 
6991 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
6992 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
6993 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
6994  *  0b0..Disabled
6995  *  0b1..Enabled
6996  */
6997 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
6998 
6999 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7000 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7001 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
7002  *  0b0..Disabled
7003  *  0b1..Enabled
7004  */
7005 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7006 
7007 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7008 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7009 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
7010  *  0b0..Disabled
7011  *  0b1..Enabled
7012  */
7013 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7014 
7015 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7016 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7017 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT
7018  *  0b0..Disabled
7019  *  0b1..Enabled
7020  */
7021 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7022 
7023 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7024 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7025 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
7026  *  0b0..Disabled
7027  *  0b1..Enabled
7028  */
7029 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7030 
7031 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7032 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7033 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
7034  *  0b0..Disabled
7035  *  0b1..Enabled
7036  */
7037 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7038 
7039 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7040 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7041 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
7042  *  0b0..Disabled
7043  *  0b1..Enabled
7044  */
7045 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7046 
7047 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7048 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7049 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
7050  *  0b0..Disabled
7051  *  0b1..Enabled
7052  */
7053 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7054 
7055 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7056 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7057 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
7058  *  0b0..Disabled
7059  *  0b1..Enabled
7060  */
7061 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7062 
7063 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7064 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7065 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
7066  *  0b0..Disabled
7067  *  0b1..Enabled
7068  */
7069 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7070 
7071 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7072 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7073 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
7074  *  0b0..Disabled
7075  *  0b1..Enabled
7076  */
7077 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7078 /*! @} */
7079 
7080 /*! @name LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER */
7081 /*! @{ */
7082 
7083 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7084 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7085 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
7086  *  0b0..Disabled
7087  *  0b1..Enabled
7088  */
7089 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7090 
7091 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7092 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7093 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
7094  *  0b0..Disabled
7095  *  0b1..Enabled
7096  */
7097 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7098 
7099 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7100 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7101 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
7102  *  0b0..Disabled
7103  *  0b1..Enabled
7104  */
7105 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7106 
7107 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7108 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7109 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7110  *  0b0..Disabled
7111  *  0b1..Enabled
7112  */
7113 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7114 
7115 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7116 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7117 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7118  *  0b0..Disabled
7119  *  0b1..Enabled
7120  */
7121 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7122 
7123 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7124 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7125 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7126  *  0b0..Disabled
7127  *  0b1..Enabled
7128  */
7129 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7130 
7131 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7132 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7133 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7134  *  0b0..Disabled
7135  *  0b1..Enabled
7136  */
7137 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7138 
7139 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7140 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7141 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7142  *  0b0..Disabled
7143  *  0b1..Enabled
7144  */
7145 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7146 
7147 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7148 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7149 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7150  *  0b0..Disabled
7151  *  0b1..Enabled
7152  */
7153 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7154 
7155 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7156 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7157 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7158  *  0b0..Disabled
7159  *  0b1..Enabled
7160  */
7161 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7162 
7163 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7164 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7165 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7166  *  0b0..Disabled
7167  *  0b1..Enabled
7168  */
7169 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7170 
7171 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7172 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7173 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7174  *  0b0..Disabled
7175  *  0b1..Enabled
7176  */
7177 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7178 
7179 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7180 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7181 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7182  *  0b0..Disabled
7183  *  0b1..Enabled
7184  */
7185 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7186 
7187 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7188 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7189 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7190  *  0b0..Disabled
7191  *  0b1..Enabled
7192  */
7193 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7194 
7195 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7196 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7197 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
7198  *  0b0..Disabled
7199  *  0b1..Enabled
7200  */
7201 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7202 
7203 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7204 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7205 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
7206  *  0b0..Disabled
7207  *  0b1..Enabled
7208  */
7209 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7210 /*! @} */
7211 
7212 /*! @name LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER */
7213 /*! @{ */
7214 
7215 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7216 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7217 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
7218  *  0b0..ON
7219  *  0b1..OFF
7220  */
7221 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7222 
7223 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7224 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7225 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
7226  *  0b0..ON
7227  *  0b1..OFF
7228  */
7229 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
7230 
7231 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
7232 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
7233 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
7234  *  0b0..ON
7235  *  0b1..OFF
7236  */
7237 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
7238 
7239 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
7240 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
7241 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
7242  *  0b0..ON
7243  *  0b1..OFF
7244  */
7245 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
7246 
7247 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
7248 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
7249 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
7250  *  0b0..ON
7251  *  0b1..OFF
7252  */
7253 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
7254 
7255 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
7256 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
7257 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
7258  *  0b0..ON
7259  *  0b1..OFF
7260  */
7261 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
7262 
7263 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
7264 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
7265 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
7266  *  0b0..ON
7267  *  0b1..OFF
7268  */
7269 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
7270 
7271 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
7272 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
7273 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
7274  *  0b0..ON
7275  *  0b1..OFF
7276  */
7277 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
7278 
7279 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
7280 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
7281 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
7282  *  0b0..ON
7283  *  0b1..OFF
7284  */
7285 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
7286 
7287 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
7288 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
7289 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
7290  *  0b0..ON
7291  *  0b1..OFF
7292  */
7293 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
7294 
7295 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
7296 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
7297 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
7298  *  0b0..ON
7299  *  0b1..OFF
7300  */
7301 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
7302 
7303 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
7304 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
7305 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
7306  *  0b0..ON
7307  *  0b1..OFF
7308  */
7309 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
7310 
7311 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
7312 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
7313 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
7314  *  0b0..ON
7315  *  0b1..OFF
7316  */
7317 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
7318 
7319 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
7320 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
7321 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
7322  *  0b0..ON
7323  *  0b1..OFF
7324  */
7325 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
7326 
7327 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
7328 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
7329 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
7330  *  0b0..ON
7331  *  0b1..OFF
7332  */
7333 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
7334 
7335 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
7336 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
7337 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
7338  *  0b0..ON
7339  *  0b1..OFF
7340  */
7341 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
7342 /*! @} */
7343 
7344 /*! @name LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER */
7345 /*! @{ */
7346 
7347 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU)
7348 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U)
7349 /*! VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0
7350  */
7351 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK)
7352 
7353 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U)
7354 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U)
7355 /*! VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1
7356  */
7357 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK)
7358 
7359 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U)
7360 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U)
7361 /*! VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2
7362  */
7363 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK)
7364 
7365 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U)
7366 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U)
7367 /*! VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3
7368  */
7369 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK)
7370 /*! @} */
7371 
7372 /*! @name LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER */
7373 /*! @{ */
7374 
7375 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU)
7376 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U)
7377 /*! VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4
7378  */
7379 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK)
7380 
7381 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U)
7382 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U)
7383 /*! VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5
7384  */
7385 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK)
7386 
7387 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U)
7388 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U)
7389 /*! VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6
7390  */
7391 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK)
7392 
7393 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U)
7394 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U)
7395 /*! VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7
7396  */
7397 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK)
7398 /*! @} */
7399 
7400 /*! @name LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER */
7401 /*! @{ */
7402 
7403 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU)
7404 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U)
7405 /*! VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8
7406  */
7407 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK)
7408 
7409 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U)
7410 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U)
7411 /*! VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9
7412  */
7413 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK)
7414 
7415 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U)
7416 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U)
7417 /*! VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10
7418  */
7419 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK)
7420 
7421 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U)
7422 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U)
7423 /*! VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11
7424  */
7425 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK)
7426 /*! @} */
7427 
7428 /*! @name LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER */
7429 /*! @{ */
7430 
7431 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU)
7432 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U)
7433 /*! VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12
7434  */
7435 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK)
7436 
7437 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U)
7438 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U)
7439 /*! VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13
7440  */
7441 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK)
7442 
7443 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U)
7444 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U)
7445 /*! VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14
7446  */
7447 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK)
7448 
7449 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U)
7450 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U)
7451 /*! VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15
7452  */
7453 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK)
7454 /*! @} */
7455 
7456 /*! @name LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER */
7457 /*! @{ */
7458 
7459 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
7460 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
7461 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
7462  *  0b0..LP
7463  *  0b1..HP
7464  */
7465 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
7466 
7467 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
7468 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
7469 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
7470  *  0b0..LP
7471  *  0b1..HP
7472  */
7473 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
7474 
7475 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U)
7476 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U)
7477 /*! LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2
7478  *  0b0..LP
7479  *  0b1..HP
7480  */
7481 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK)
7482 
7483 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U)
7484 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U)
7485 /*! LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3
7486  *  0b0..LP
7487  *  0b1..HP
7488  */
7489 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK)
7490 
7491 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U)
7492 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U)
7493 /*! LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4
7494  *  0b0..LP
7495  *  0b1..HP
7496  */
7497 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK)
7498 
7499 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U)
7500 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U)
7501 /*! LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5
7502  *  0b0..LP
7503  *  0b1..HP
7504  */
7505 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK)
7506 
7507 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U)
7508 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U)
7509 /*! LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6
7510  *  0b0..LP
7511  *  0b1..HP
7512  */
7513 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK)
7514 
7515 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U)
7516 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U)
7517 /*! LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7
7518  *  0b0..LP
7519  *  0b1..HP
7520  */
7521 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK)
7522 
7523 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U)
7524 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U)
7525 /*! LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8
7526  *  0b0..LP
7527  *  0b1..HP
7528  */
7529 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK)
7530 
7531 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U)
7532 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U)
7533 /*! LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9
7534  *  0b0..LP
7535  *  0b1..HP
7536  */
7537 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK)
7538 
7539 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U)
7540 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U)
7541 /*! LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10
7542  *  0b0..LP
7543  *  0b1..HP
7544  */
7545 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK)
7546 
7547 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U)
7548 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U)
7549 /*! LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11
7550  *  0b0..LP
7551  *  0b1..HP
7552  */
7553 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK)
7554 
7555 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U)
7556 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U)
7557 /*! LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12
7558  *  0b0..LP
7559  *  0b1..HP
7560  */
7561 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK)
7562 
7563 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U)
7564 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U)
7565 /*! LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13
7566  *  0b0..LP
7567  *  0b1..HP
7568  */
7569 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK)
7570 
7571 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U)
7572 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U)
7573 /*! LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14
7574  *  0b0..LP
7575  *  0b1..HP
7576  */
7577 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK)
7578 
7579 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U)
7580 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U)
7581 /*! LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15
7582  *  0b0..LP
7583  *  0b1..HP
7584  */
7585 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK)
7586 /*! @} */
7587 
7588 /*! @name LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER */
7589 /*! @{ */
7590 
7591 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
7592 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
7593 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
7594  *  0b0..Disabled
7595  *  0b1..Enabled
7596  */
7597 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
7598 
7599 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
7600 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
7601 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
7602  *  0b0..Disabled
7603  *  0b1..Enabled
7604  */
7605 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
7606 
7607 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
7608 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
7609 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
7610  *  0b0..Disabled
7611  *  0b1..Enabled
7612  */
7613 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
7614 
7615 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
7616 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
7617 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
7618  *  0b0..Disabled
7619  *  0b1..Enabled
7620  */
7621 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
7622 
7623 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
7624 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
7625 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
7626  *  0b0..Disabled
7627  *  0b1..Enabled
7628  */
7629 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
7630 
7631 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
7632 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
7633 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
7634  *  0b0..Disabled
7635  *  0b1..Enabled
7636  */
7637 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
7638 
7639 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
7640 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
7641 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
7642  *  0b0..Disabled
7643  *  0b1..Enabled
7644  */
7645 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
7646 
7647 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
7648 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
7649 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
7650  *  0b0..Disabled
7651  *  0b1..Enabled
7652  */
7653 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
7654 
7655 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
7656 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
7657 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
7658  *  0b0..Disabled
7659  *  0b1..Enabled
7660  */
7661 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
7662 
7663 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
7664 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
7665 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
7666  *  0b0..Disabled
7667  *  0b1..Enabled
7668  */
7669 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
7670 
7671 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
7672 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
7673 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
7674  *  0b0..Disabled
7675  *  0b1..Enabled
7676  */
7677 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
7678 
7679 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
7680 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
7681 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
7682  *  0b0..Disabled
7683  *  0b1..Enabled
7684  */
7685 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
7686 
7687 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
7688 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
7689 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
7690  *  0b0..Disabled
7691  *  0b1..Enabled
7692  */
7693 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
7694 
7695 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
7696 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
7697 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
7698  *  0b0..Disabled
7699  *  0b1..Enabled
7700  */
7701 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
7702 
7703 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
7704 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
7705 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
7706  *  0b0..Disabled
7707  *  0b1..Enabled
7708  */
7709 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
7710 
7711 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
7712 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
7713 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
7714  *  0b0..Disabled
7715  *  0b1..Enabled
7716  */
7717 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
7718 /*! @} */
7719 
7720 /*! @name LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER */
7721 /*! @{ */
7722 
7723 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
7724 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
7725 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
7726  *  0b0..Disabled
7727  *  0b1..Enabled
7728  */
7729 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
7730 
7731 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
7732 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
7733 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
7734  *  0b0..Disabled
7735  *  0b1..Enabled
7736  */
7737 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
7738 
7739 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
7740 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
7741 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
7742  *  0b0..Disabled
7743  *  0b1..Enabled
7744  */
7745 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
7746 
7747 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
7748 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
7749 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
7750  *  0b0..Disabled
7751  *  0b1..Enabled
7752  */
7753 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
7754 
7755 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
7756 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
7757 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
7758  *  0b0..Disabled
7759  *  0b1..Enabled
7760  */
7761 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7762 
7763 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7764 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7765 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
7766  *  0b0..Disabled
7767  *  0b1..Enabled
7768  */
7769 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7770 
7771 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7772 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7773 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
7774  *  0b0..Disabled
7775  *  0b1..Enabled
7776  */
7777 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7778 
7779 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7780 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7781 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
7782  *  0b0..Disabled
7783  *  0b1..Enabled
7784  */
7785 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7786 
7787 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7788 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7789 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8
7790  *  0b0..Disabled
7791  *  0b1..Enabled
7792  */
7793 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7794 
7795 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7796 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7797 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
7798  *  0b0..Disabled
7799  *  0b1..Enabled
7800  */
7801 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7802 
7803 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7804 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7805 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
7806  *  0b0..Disabled
7807  *  0b1..Enabled
7808  */
7809 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7810 
7811 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7812 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7813 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
7814  *  0b0..Disabled
7815  *  0b1..Enabled
7816  */
7817 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7818 
7819 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7820 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7821 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
7822  *  0b0..Disabled
7823  *  0b1..Enabled
7824  */
7825 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7826 
7827 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7828 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7829 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
7830  *  0b0..Disabled
7831  *  0b1..Enabled
7832  */
7833 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7834 
7835 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7836 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7837 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
7838  *  0b0..Disabled
7839  *  0b1..Enabled
7840  */
7841 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7842 
7843 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7844 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7845 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
7846  *  0b0..Disabled
7847  *  0b1..Enabled
7848  */
7849 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7850 /*! @} */
7851 
7852 /*! @name LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER */
7853 /*! @{ */
7854 
7855 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7856 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7857 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
7858  *  0b0..Disabled
7859  *  0b1..Enabled
7860  */
7861 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7862 
7863 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7864 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7865 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
7866  *  0b0..Disabled
7867  *  0b1..Enabled
7868  */
7869 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7870 
7871 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7872 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7873 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
7874  *  0b0..Disabled
7875  *  0b1..Enabled
7876  */
7877 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7878 
7879 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7880 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7881 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7882  *  0b0..Disabled
7883  *  0b1..Enabled
7884  */
7885 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7886 
7887 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7888 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7889 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7890  *  0b0..Disabled
7891  *  0b1..Enabled
7892  */
7893 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7894 
7895 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7896 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7897 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7898  *  0b0..Disabled
7899  *  0b1..Enabled
7900  */
7901 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7902 
7903 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7904 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7905 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7906  *  0b0..Disabled
7907  *  0b1..Enabled
7908  */
7909 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7910 
7911 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7912 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7913 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7914  *  0b0..Disabled
7915  *  0b1..Enabled
7916  */
7917 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7918 
7919 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7920 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7921 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7922  *  0b0..Disabled
7923  *  0b1..Enabled
7924  */
7925 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7926 
7927 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7928 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7929 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7930  *  0b0..Disabled
7931  *  0b1..Enabled
7932  */
7933 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7934 
7935 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7936 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7937 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7938  *  0b0..Disabled
7939  *  0b1..Enabled
7940  */
7941 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7942 
7943 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7944 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7945 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7946  *  0b0..Disabled
7947  *  0b1..Enabled
7948  */
7949 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7950 
7951 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7952 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7953 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7954  *  0b0..Disabled
7955  *  0b1..Enabled
7956  */
7957 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7958 
7959 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7960 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7961 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7962  *  0b0..Disabled
7963  *  0b1..Enabled
7964  */
7965 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7966 
7967 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7968 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7969 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
7970  *  0b0..Disabled
7971  *  0b1..Enabled
7972  */
7973 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7974 
7975 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7976 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7977 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
7978  *  0b0..Disabled
7979  *  0b1..Enabled
7980  */
7981 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7982 /*! @} */
7983 
7984 /*! @name BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER */
7985 /*! @{ */
7986 
7987 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7988 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7989 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
7990  *  0b0..ON
7991  *  0b1..OFF
7992  */
7993 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7994 
7995 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7996 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7997 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
7998  *  0b0..ON
7999  *  0b1..OFF
8000  */
8001 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8002 
8003 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8004 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8005 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8006  *  0b0..ON
8007  *  0b1..OFF
8008  */
8009 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8010 
8011 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8012 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8013 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8014  *  0b0..ON
8015  *  0b1..OFF
8016  */
8017 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8018 
8019 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8020 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8021 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8022  *  0b0..ON
8023  *  0b1..OFF
8024  */
8025 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8026 
8027 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8028 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8029 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8030  *  0b0..ON
8031  *  0b1..OFF
8032  */
8033 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8034 
8035 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8036 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8037 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5
8038  *  0b0..ON
8039  *  0b1..OFF
8040  */
8041 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8042 
8043 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8044 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8045 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8046  *  0b0..ON
8047  *  0b1..OFF
8048  */
8049 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8050 
8051 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8052 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8053 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8054  *  0b0..ON
8055  *  0b1..OFF
8056  */
8057 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8058 
8059 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8060 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8061 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8062  *  0b0..ON
8063  *  0b1..OFF
8064  */
8065 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8066 
8067 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8068 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8069 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8070  *  0b0..ON
8071  *  0b1..OFF
8072  */
8073 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8074 
8075 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8076 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8077 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8078  *  0b0..ON
8079  *  0b1..OFF
8080  */
8081 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8082 
8083 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8084 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8085 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8086  *  0b0..ON
8087  *  0b1..OFF
8088  */
8089 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8090 
8091 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8092 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8093 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8094  *  0b0..ON
8095  *  0b1..OFF
8096  */
8097 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8098 
8099 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8100 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8101 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8102  *  0b0..ON
8103  *  0b1..OFF
8104  */
8105 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8106 
8107 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8108 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8109 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8110  *  0b0..ON
8111  *  0b1..OFF
8112  */
8113 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8114 /*! @} */
8115 
8116 /*! @name FBB_M7_ENABLE_SP - FBB_M7_ENABLE_SP_REGISTER */
8117 /*! @{ */
8118 
8119 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8120 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8121 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8122  *  0b0..ON
8123  *  0b1..OFF
8124  */
8125 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8126 
8127 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8128 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8129 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8130  *  0b0..ON
8131  *  0b1..OFF
8132  */
8133 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8134 
8135 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8136 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8137 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8138  *  0b0..ON
8139  *  0b1..OFF
8140  */
8141 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8142 
8143 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8144 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8145 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8146  *  0b0..ON
8147  *  0b1..OFF
8148  */
8149 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8150 
8151 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8152 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8153 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8154  *  0b0..ON
8155  *  0b1..OFF
8156  */
8157 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8158 
8159 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8160 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8161 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8162  *  0b0..ON
8163  *  0b1..OFF
8164  */
8165 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8166 
8167 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8168 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8169 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8170  *  0b0..ON
8171  *  0b1..OFF
8172  */
8173 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8174 
8175 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8176 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8177 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8178  *  0b0..ON
8179  *  0b1..OFF
8180  */
8181 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8182 
8183 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8184 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8185 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8186  *  0b0..ON
8187  *  0b1..OFF
8188  */
8189 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8190 
8191 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8192 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8193 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8194  *  0b0..ON
8195  *  0b1..OFF
8196  */
8197 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8198 
8199 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8200 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8201 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8202  *  0b0..ON
8203  *  0b1..OFF
8204  */
8205 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8206 
8207 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8208 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8209 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8210  *  0b0..ON
8211  *  0b1..OFF
8212  */
8213 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8214 
8215 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8216 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8217 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8218  *  0b0..ON
8219  *  0b1..OFF
8220  */
8221 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8222 
8223 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8224 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8225 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8226  *  0b0..ON
8227  *  0b1..OFF
8228  */
8229 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8230 
8231 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8232 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8233 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8234  *  0b0..ON
8235  *  0b1..OFF
8236  */
8237 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8238 
8239 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8240 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8241 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8242  *  0b0..ON
8243  *  0b1..OFF
8244  */
8245 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8246 /*! @} */
8247 
8248 /*! @name RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER */
8249 /*! @{ */
8250 
8251 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8252 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8253 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8254  *  0b0..ON
8255  *  0b1..OFF
8256  */
8257 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8258 
8259 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8260 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8261 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8262  *  0b0..ON
8263  *  0b1..OFF
8264  */
8265 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8266 
8267 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8268 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8269 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8270  *  0b0..ON
8271  *  0b1..OFF
8272  */
8273 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8274 
8275 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8276 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8277 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8278  *  0b0..ON
8279  *  0b1..OFF
8280  */
8281 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8282 
8283 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8284 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8285 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8286  *  0b0..ON
8287  *  0b1..OFF
8288  */
8289 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8290 
8291 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8292 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8293 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8294  *  0b0..ON
8295  *  0b1..OFF
8296  */
8297 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8298 
8299 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8300 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8301 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8302  *  0b0..ON
8303  *  0b1..OFF
8304  */
8305 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8306 
8307 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8308 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8309 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8310  *  0b0..ON
8311  *  0b1..OFF
8312  */
8313 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8314 
8315 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8316 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8317 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8318  *  0b0..ON
8319  *  0b1..OFF
8320  */
8321 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8322 
8323 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8324 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8325 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8326  *  0b0..ON
8327  *  0b1..OFF
8328  */
8329 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8330 
8331 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8332 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8333 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8334  *  0b0..ON
8335  *  0b1..OFF
8336  */
8337 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8338 
8339 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8340 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8341 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8342  *  0b0..ON
8343  *  0b1..OFF
8344  */
8345 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8346 
8347 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8348 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8349 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8350  *  0b0..ON
8351  *  0b1..OFF
8352  */
8353 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8354 
8355 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8356 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8357 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8358  *  0b0..ON
8359  *  0b1..OFF
8360  */
8361 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8362 
8363 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8364 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8365 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8366  *  0b0..ON
8367  *  0b1..OFF
8368  */
8369 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8370 
8371 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8372 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8373 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8374  *  0b0..ON
8375  *  0b1..OFF
8376  */
8377 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8378 /*! @} */
8379 
8380 /*! @name RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER */
8381 /*! @{ */
8382 
8383 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8384 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8385 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8386  *  0b0..ON
8387  *  0b1..OFF
8388  */
8389 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8390 
8391 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8392 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8393 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8394  *  0b0..ON
8395  *  0b1..OFF
8396  */
8397 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8398 
8399 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8400 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8401 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8402  *  0b0..ON
8403  *  0b1..OFF
8404  */
8405 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8406 
8407 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8408 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8409 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8410  *  0b0..ON
8411  *  0b1..OFF
8412  */
8413 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8414 
8415 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8416 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8417 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8418  *  0b0..ON
8419  *  0b1..OFF
8420  */
8421 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8422 
8423 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8424 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8425 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8426  *  0b0..ON
8427  *  0b1..OFF
8428  */
8429 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8430 
8431 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8432 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8433 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8434  *  0b0..ON
8435  *  0b1..OFF
8436  */
8437 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8438 
8439 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8440 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8441 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8442  *  0b0..ON
8443  *  0b1..OFF
8444  */
8445 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8446 
8447 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8448 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8449 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8450  *  0b0..ON
8451  *  0b1..OFF
8452  */
8453 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8454 
8455 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8456 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8457 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8458  *  0b0..ON
8459  *  0b1..OFF
8460  */
8461 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8462 
8463 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8464 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8465 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8466  *  0b0..ON
8467  *  0b1..OFF
8468  */
8469 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8470 
8471 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8472 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8473 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8474  *  0b0..ON
8475  *  0b1..OFF
8476  */
8477 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8478 
8479 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8480 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8481 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8482  *  0b0..ON
8483  *  0b1..OFF
8484  */
8485 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8486 
8487 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8488 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8489 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8490  *  0b0..ON
8491  *  0b1..OFF
8492  */
8493 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8494 
8495 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8496 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8497 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8498  *  0b0..ON
8499  *  0b1..OFF
8500  */
8501 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8502 
8503 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8504 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8505 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8506  *  0b0..ON
8507  *  0b1..OFF
8508  */
8509 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8510 /*! @} */
8511 
8512 /*! @name BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER */
8513 /*! @{ */
8514 
8515 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8516 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8517 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT
8518  *  0b0..Disabled
8519  *  0b1..Enabled
8520  */
8521 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8522 
8523 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8524 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8525 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT
8526  *  0b0..Disabled
8527  *  0b1..Enabled
8528  */
8529 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8530 
8531 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8532 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8533 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT
8534  *  0b0..Disabled
8535  *  0b1..Enabled
8536  */
8537 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8538 
8539 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8540 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8541 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT
8542  *  0b0..Disabled
8543  *  0b1..Enabled
8544  */
8545 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8546 
8547 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8548 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8549 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT
8550  *  0b0..Disabled
8551  *  0b1..Enabled
8552  */
8553 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8554 
8555 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8556 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8557 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT
8558  *  0b0..Disabled
8559  *  0b1..Enabled
8560  */
8561 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8562 
8563 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8564 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8565 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT
8566  *  0b0..Disabled
8567  *  0b1..Enabled
8568  */
8569 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8570 
8571 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8572 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8573 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT
8574  *  0b0..Disabled
8575  *  0b1..Enabled
8576  */
8577 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8578 
8579 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8580 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8581 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT
8582  *  0b0..Disabled
8583  *  0b1..Enabled
8584  */
8585 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8586 
8587 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8588 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8589 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT
8590  *  0b0..Disabled
8591  *  0b1..Enabled
8592  */
8593 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8594 
8595 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8596 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8597 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT
8598  *  0b0..Disabled
8599  *  0b1..Enabled
8600  */
8601 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8602 
8603 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8604 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8605 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT
8606  *  0b0..Disabled
8607  *  0b1..Enabled
8608  */
8609 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8610 
8611 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8612 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8613 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT
8614  *  0b0..Disabled
8615  *  0b1..Enabled
8616  */
8617 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8618 
8619 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8620 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8621 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT
8622  *  0b0..Disabled
8623  *  0b1..Enabled
8624  */
8625 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8626 
8627 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8628 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8629 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT
8630  *  0b0..Disabled
8631  *  0b1..Enabled
8632  */
8633 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8634 
8635 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8636 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8637 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT
8638  *  0b0..Disabled
8639  *  0b1..Enabled
8640  */
8641 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8642 /*! @} */
8643 
8644 /*! @name PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER */
8645 /*! @{ */
8646 
8647 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8648 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8649 /*! STBY_EN_SETPOINT0 - Standby mode
8650  *  0b0..Disabled
8651  *  0b1..Enabled
8652  */
8653 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8654 
8655 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8656 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8657 /*! STBY_EN_SETPOINT1 - Standby mode
8658  *  0b0..Disabled
8659  *  0b1..Enabled
8660  */
8661 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8662 
8663 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8664 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8665 /*! STBY_EN_SETPOINT2 - Standby mode
8666  *  0b0..Disabled
8667  *  0b1..Enabled
8668  */
8669 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8670 
8671 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8672 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8673 /*! STBY_EN_SETPOINT3 - Standby mode
8674  *  0b0..Disabled
8675  *  0b1..Enabled
8676  */
8677 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8678 
8679 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8680 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8681 /*! STBY_EN_SETPOINT4 - Standby mode
8682  *  0b0..Disabled
8683  *  0b1..Enabled
8684  */
8685 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8686 
8687 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8688 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8689 /*! STBY_EN_SETPOINT5 - Standby mode
8690  *  0b0..Disabled
8691  *  0b1..Enabled
8692  */
8693 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8694 
8695 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8696 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8697 /*! STBY_EN_SETPOINT6 - Standby mode
8698  *  0b0..Disabled
8699  *  0b1..Enabled
8700  */
8701 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8702 
8703 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8704 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8705 /*! STBY_EN_SETPOINT7 - Standby mode
8706  *  0b0..Disabled
8707  *  0b1..Enabled
8708  */
8709 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8710 
8711 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8712 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8713 /*! STBY_EN_SETPOINT8 - Standby mode
8714  *  0b0..Disabled
8715  *  0b1..Enabled
8716  */
8717 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8718 
8719 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8720 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8721 /*! STBY_EN_SETPOINT9 - Standby mode
8722  *  0b0..Disabled
8723  *  0b1..Enabled
8724  */
8725 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8726 
8727 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8728 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8729 /*! STBY_EN_SETPOINT10 - Standby mode
8730  *  0b0..Disabled
8731  *  0b1..Enabled
8732  */
8733 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8734 
8735 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8736 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8737 /*! STBY_EN_SETPOINT11 - Standby mode
8738  *  0b0..Disabled
8739  *  0b1..Enabled
8740  */
8741 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8742 
8743 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8744 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8745 /*! STBY_EN_SETPOINT12 - Standby mode
8746  *  0b0..Disabled
8747  *  0b1..Enabled
8748  */
8749 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8750 
8751 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8752 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8753 /*! STBY_EN_SETPOINT13 - Standby mode
8754  *  0b0..Disabled
8755  *  0b1..Enabled
8756  */
8757 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8758 
8759 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8760 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8761 /*! STBY_EN_SETPOINT14 - Standby mode
8762  *  0b0..Disabled
8763  *  0b1..Enabled
8764  */
8765 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8766 
8767 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8768 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8769 /*! STBY_EN_SETPOINT15 - Standby mode
8770  *  0b0..Disabled
8771  *  0b1..Enabled
8772  */
8773 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8774 /*! @} */
8775 
8776 /*! @name FBB_M7_STBY_EN_SP - FBB_M7_STBY_EN_SP_REGISTER */
8777 /*! @{ */
8778 
8779 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8780 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8781 /*! STBY_EN_SETPOINT0 - Standby mode
8782  *  0b0..Disabled
8783  *  0b1..Enabled
8784  */
8785 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8786 
8787 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8788 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8789 /*! STBY_EN_SETPOINT1 - Standby mode
8790  *  0b0..Disabled
8791  *  0b1..Enabled
8792  */
8793 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8794 
8795 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8796 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8797 /*! STBY_EN_SETPOINT2 - Standby mode
8798  *  0b0..Disabled
8799  *  0b1..Enabled
8800  */
8801 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8802 
8803 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8804 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8805 /*! STBY_EN_SETPOINT3 - Standby mode
8806  *  0b0..Disabled
8807  *  0b1..Enabled
8808  */
8809 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8810 
8811 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8812 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8813 /*! STBY_EN_SETPOINT4 - Standby mode
8814  *  0b0..Disabled
8815  *  0b1..Enabled
8816  */
8817 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8818 
8819 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8820 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8821 /*! STBY_EN_SETPOINT5 - Standby mode
8822  *  0b0..Disabled
8823  *  0b1..Enabled
8824  */
8825 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8826 
8827 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8828 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8829 /*! STBY_EN_SETPOINT6 - Standby mode
8830  *  0b0..Disabled
8831  *  0b1..Enabled
8832  */
8833 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8834 
8835 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8836 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8837 /*! STBY_EN_SETPOINT7 - Standby mode
8838  *  0b0..Disabled
8839  *  0b1..Enabled
8840  */
8841 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8842 
8843 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8844 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8845 /*! STBY_EN_SETPOINT8 - Standby mode
8846  *  0b0..Disabled
8847  *  0b1..Enabled
8848  */
8849 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8850 
8851 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8852 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8853 /*! STBY_EN_SETPOINT9 - Standby mode
8854  *  0b0..Disabled
8855  *  0b1..Enabled
8856  */
8857 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8858 
8859 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8860 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8861 /*! STBY_EN_SETPOINT10 - Standby mode
8862  *  0b0..Disabled
8863  *  0b1..Enabled
8864  */
8865 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8866 
8867 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8868 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8869 /*! STBY_EN_SETPOINT11 - Standby mode
8870  *  0b0..Disabled
8871  *  0b1..Enabled
8872  */
8873 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8874 
8875 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8876 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8877 /*! STBY_EN_SETPOINT12 - Standby mode
8878  *  0b0..Disabled
8879  *  0b1..Enabled
8880  */
8881 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8882 
8883 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8884 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8885 /*! STBY_EN_SETPOINT13 - Standby mode
8886  *  0b0..Disabled
8887  *  0b1..Enabled
8888  */
8889 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8890 
8891 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8892 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8893 /*! STBY_EN_SETPOINT14 - Standby mode
8894  *  0b0..Disabled
8895  *  0b1..Enabled
8896  */
8897 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8898 
8899 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8900 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8901 /*! STBY_EN_SETPOINT15 - Standby mode
8902  *  0b0..Disabled
8903  *  0b1..Enabled
8904  */
8905 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8906 /*! @} */
8907 
8908 /*! @name RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER */
8909 /*! @{ */
8910 
8911 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8912 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8913 /*! STBY_EN_SETPOINT0 - Standby mode
8914  *  0b0..Disabled
8915  *  0b1..Enabled
8916  */
8917 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8918 
8919 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8920 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8921 /*! STBY_EN_SETPOINT1 - Standby mode
8922  *  0b0..Disabled
8923  *  0b1..Enabled
8924  */
8925 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8926 
8927 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8928 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8929 /*! STBY_EN_SETPOINT2 - Standby mode
8930  *  0b0..Disabled
8931  *  0b1..Enabled
8932  */
8933 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8934 
8935 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8936 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8937 /*! STBY_EN_SETPOINT3 - Standby mode
8938  *  0b0..Disabled
8939  *  0b1..Enabled
8940  */
8941 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8942 
8943 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8944 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8945 /*! STBY_EN_SETPOINT4 - Standby mode
8946  *  0b0..Disabled
8947  *  0b1..Enabled
8948  */
8949 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8950 
8951 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8952 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8953 /*! STBY_EN_SETPOINT5 - Standby mode
8954  *  0b0..Disabled
8955  *  0b1..Enabled
8956  */
8957 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8958 
8959 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8960 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8961 /*! STBY_EN_SETPOINT6 - Standby mode
8962  *  0b0..Disabled
8963  *  0b1..Enabled
8964  */
8965 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8966 
8967 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8968 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8969 /*! STBY_EN_SETPOINT7 - Standby mode
8970  *  0b0..Disabled
8971  *  0b1..Enabled
8972  */
8973 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8974 
8975 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8976 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8977 /*! STBY_EN_SETPOINT8 - Standby mode
8978  *  0b0..Disabled
8979  *  0b1..Enabled
8980  */
8981 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8982 
8983 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8984 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8985 /*! STBY_EN_SETPOINT9 - Standby mode
8986  *  0b0..Disabled
8987  *  0b1..Enabled
8988  */
8989 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8990 
8991 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8992 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8993 /*! STBY_EN_SETPOINT10 - Standby mode
8994  *  0b0..Disabled
8995  *  0b1..Enabled
8996  */
8997 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8998 
8999 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
9000 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
9001 /*! STBY_EN_SETPOINT11 - Standby mode
9002  *  0b0..Disabled
9003  *  0b1..Enabled
9004  */
9005 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
9006 
9007 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
9008 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
9009 /*! STBY_EN_SETPOINT12 - Standby mode
9010  *  0b0..Disabled
9011  *  0b1..Enabled
9012  */
9013 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
9014 
9015 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
9016 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
9017 /*! STBY_EN_SETPOINT13 - Standby mode
9018  *  0b0..Disabled
9019  *  0b1..Enabled
9020  */
9021 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
9022 
9023 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
9024 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
9025 /*! STBY_EN_SETPOINT14 - Standby mode
9026  *  0b0..Disabled
9027  *  0b1..Enabled
9028  */
9029 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
9030 
9031 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
9032 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
9033 /*! STBY_EN_SETPOINT15 - Standby mode
9034  *  0b0..Disabled
9035  *  0b1..Enabled
9036  */
9037 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
9038 /*! @} */
9039 
9040 /*! @name RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER */
9041 /*! @{ */
9042 
9043 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
9044 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
9045 /*! STBY_EN_SETPOINT0 - Standby mode
9046  *  0b0..Disabled
9047  *  0b1..Enabled
9048  */
9049 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
9050 
9051 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
9052 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
9053 /*! STBY_EN_SETPOINT1 - Standby mode
9054  *  0b0..Disabled
9055  *  0b1..Enabled
9056  */
9057 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
9058 
9059 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
9060 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
9061 /*! STBY_EN_SETPOINT2 - Standby mode
9062  *  0b0..Disabled
9063  *  0b1..Enabled
9064  */
9065 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
9066 
9067 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
9068 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
9069 /*! STBY_EN_SETPOINT3 - Standby mode
9070  *  0b0..Disabled
9071  *  0b1..Enabled
9072  */
9073 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
9074 
9075 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
9076 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
9077 /*! STBY_EN_SETPOINT4 - Standby mode
9078  *  0b0..Disabled
9079  *  0b1..Enabled
9080  */
9081 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
9082 
9083 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
9084 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
9085 /*! STBY_EN_SETPOINT5 - Standby mode
9086  *  0b0..Disabled
9087  *  0b1..Enabled
9088  */
9089 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
9090 
9091 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
9092 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
9093 /*! STBY_EN_SETPOINT6 - Standby mode
9094  *  0b0..Disabled
9095  *  0b1..Enabled
9096  */
9097 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
9098 
9099 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
9100 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
9101 /*! STBY_EN_SETPOINT7 - Standby mode
9102  *  0b0..Disabled
9103  *  0b1..Enabled
9104  */
9105 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
9106 
9107 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
9108 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
9109 /*! STBY_EN_SETPOINT8 - Standby mode
9110  *  0b0..Disabled
9111  *  0b1..Enabled
9112  */
9113 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
9114 
9115 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
9116 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
9117 /*! STBY_EN_SETPOINT9 - Standby mode
9118  *  0b0..Disabled
9119  *  0b1..Enabled
9120  */
9121 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
9122 
9123 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
9124 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
9125 /*! STBY_EN_SETPOINT10 - Standby mode
9126  *  0b0..Disabled
9127  *  0b1..Enabled
9128  */
9129 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
9130 
9131 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
9132 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
9133 /*! STBY_EN_SETPOINT11 - Standby mode
9134  *  0b0..Disabled
9135  *  0b1..Enabled
9136  */
9137 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
9138 
9139 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
9140 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
9141 /*! STBY_EN_SETPOINT12 - Standby mode
9142  *  0b0..Disabled
9143  *  0b1..Enabled
9144  */
9145 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
9146 
9147 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
9148 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
9149 /*! STBY_EN_SETPOINT13 - Standby mode
9150  *  0b0..Disabled
9151  *  0b1..Enabled
9152  */
9153 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
9154 
9155 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
9156 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
9157 /*! STBY_EN_SETPOINT14 - Standby mode
9158  *  0b0..Disabled
9159  *  0b1..Enabled
9160  */
9161 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
9162 
9163 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
9164 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
9165 /*! STBY_EN_SETPOINT15 - Standby mode
9166  *  0b0..Disabled
9167  *  0b1..Enabled
9168  */
9169 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
9170 /*! @} */
9171 
9172 /*! @name FBB_M7_CONFIGURE - FBB_M7_CONFIGURE_REGISTER */
9173 /*! @{ */
9174 
9175 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9176 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9177 /*! WB_CFG_PW - wb_cfg_pw
9178  */
9179 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK)
9180 
9181 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9182 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9183 /*! WB_CFG_NW - wb_cfg_nw
9184  */
9185 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK)
9186 
9187 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9188 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9189 /*! OSCILLATOR_BITS - oscillator_bits
9190  */
9191 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK)
9192 
9193 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9194 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9195 /*! REGULATOR_STRENGTH - regulator_strength
9196  */
9197 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK)
9198 /*! @} */
9199 
9200 /*! @name RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER */
9201 /*! @{ */
9202 
9203 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9204 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9205 /*! WB_CFG_PW - wb_cfg_pw
9206  */
9207 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK)
9208 
9209 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9210 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9211 /*! WB_CFG_NW - wb_cfg_nw
9212  */
9213 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK)
9214 
9215 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9216 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9217 /*! OSCILLATOR_BITS - oscillator_bits
9218  */
9219 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK)
9220 
9221 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9222 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9223 /*! REGULATOR_STRENGTH - regulator_strength
9224  */
9225 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK)
9226 /*! @} */
9227 
9228 /*! @name RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER */
9229 /*! @{ */
9230 
9231 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9232 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9233 /*! WB_CFG_PW - wb_cfg_pw
9234  */
9235 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK)
9236 
9237 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9238 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9239 /*! WB_CFG_NW - wb_cfg_nw
9240  */
9241 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK)
9242 
9243 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9244 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9245 /*! OSCILLATOR_BITS - oscillator_bits
9246  */
9247 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK)
9248 
9249 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9250 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9251 /*! REGULATOR_STRENGTH - regulator_strength
9252  */
9253 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK)
9254 /*! @} */
9255 
9256 /*! @name REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER */
9257 /*! @{ */
9258 
9259 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U)
9260 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U)
9261 /*! REFTOP_IBZTCADJ - REFTOP_IBZTCADJ
9262  */
9263 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK)
9264 
9265 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U)
9266 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U)
9267 /*! REFTOP_VBGADJ - REFTOP_VBGADJ
9268  */
9269 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK)
9270 
9271 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U)
9272 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U)
9273 /*! REFTOP_TRIM_EN - REFTOP_TRIM_EN
9274  */
9275 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK)
9276 /*! @} */
9277 
9278 /*! @name LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER */
9279 /*! @{ */
9280 
9281 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U)
9282 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U)
9283 /*! LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM
9284  */
9285 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK)
9286 
9287 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U)
9288 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U)
9289 /*! LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN
9290  */
9291 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK)
9292 /*! @} */
9293 
9294 
9295 /*!
9296  * @}
9297  */ /* end of group ANADIG_PMU_Register_Masks */
9298 
9299 
9300 /* ANADIG_PMU - Peripheral instance base addresses */
9301 /** Peripheral ANADIG_PMU base address */
9302 #define ANADIG_PMU_BASE                          (0x40C84000u)
9303 /** Peripheral ANADIG_PMU base pointer */
9304 #define ANADIG_PMU                               ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
9305 /** Array initializer of ANADIG_PMU peripheral base addresses */
9306 #define ANADIG_PMU_BASE_ADDRS                    { ANADIG_PMU_BASE }
9307 /** Array initializer of ANADIG_PMU peripheral base pointers */
9308 #define ANADIG_PMU_BASE_PTRS                     { ANADIG_PMU }
9309 
9310 /*!
9311  * @}
9312  */ /* end of group ANADIG_PMU_Peripheral_Access_Layer */
9313 
9314 
9315 /* ----------------------------------------------------------------------------
9316    -- ANADIG_TEMPSENSOR Peripheral Access Layer
9317    ---------------------------------------------------------------------------- */
9318 
9319 /*!
9320  * @addtogroup ANADIG_TEMPSENSOR_Peripheral_Access_Layer ANADIG_TEMPSENSOR Peripheral Access Layer
9321  * @{
9322  */
9323 
9324 /** ANADIG_TEMPSENSOR - Register Layout Typedef */
9325 typedef struct {
9326        uint8_t RESERVED_0[1024];
9327   __IO uint32_t TEMPSENSOR;                        /**< Tempsensor Register, offset: 0x400 */
9328        uint8_t RESERVED_1[44];
9329   __I  uint32_t TEMPSNS_OTP_TRIM_VALUE;            /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430 */
9330 } ANADIG_TEMPSENSOR_Type;
9331 
9332 /* ----------------------------------------------------------------------------
9333    -- ANADIG_TEMPSENSOR Register Masks
9334    ---------------------------------------------------------------------------- */
9335 
9336 /*!
9337  * @addtogroup ANADIG_TEMPSENSOR_Register_Masks ANADIG_TEMPSENSOR Register Masks
9338  * @{
9339  */
9340 
9341 /*! @name TEMPSENSOR - Tempsensor Register */
9342 /*! @{ */
9343 
9344 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U)
9345 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U)
9346 /*! TEMPSNS_AI_TOGGLE - AI toggle
9347  */
9348 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK)
9349 
9350 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U)
9351 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U)
9352 /*! TEMPSNS_AI_BUSY - AI Busy monitor
9353  */
9354 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK)
9355 /*! @} */
9356 
9357 /*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */
9358 /*! @{ */
9359 
9360 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
9361 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
9362 /*! TEMPSNS_TEMP_VAL - Temperature Value at 25C
9363  */
9364 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK)
9365 /*! @} */
9366 
9367 
9368 /*!
9369  * @}
9370  */ /* end of group ANADIG_TEMPSENSOR_Register_Masks */
9371 
9372 
9373 /* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
9374 /** Peripheral ANADIG_TEMPSENSOR base address */
9375 #define ANADIG_TEMPSENSOR_BASE                   (0x40C84000u)
9376 /** Peripheral ANADIG_TEMPSENSOR base pointer */
9377 #define ANADIG_TEMPSENSOR                        ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
9378 /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
9379 #define ANADIG_TEMPSENSOR_BASE_ADDRS             { ANADIG_TEMPSENSOR_BASE }
9380 /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
9381 #define ANADIG_TEMPSENSOR_BASE_PTRS              { ANADIG_TEMPSENSOR }
9382 
9383 /*!
9384  * @}
9385  */ /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
9386 
9387 
9388 /* ----------------------------------------------------------------------------
9389    -- AOI Peripheral Access Layer
9390    ---------------------------------------------------------------------------- */
9391 
9392 /*!
9393  * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
9394  * @{
9395  */
9396 
9397 /** AOI - Register Layout Typedef */
9398 typedef struct {
9399   struct {                                         /* offset: 0x0, array step: 0x4 */
9400     __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
9401     __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
9402   } BFCRT[4];
9403 } AOI_Type;
9404 
9405 /* ----------------------------------------------------------------------------
9406    -- AOI Register Masks
9407    ---------------------------------------------------------------------------- */
9408 
9409 /*!
9410  * @addtogroup AOI_Register_Masks AOI Register Masks
9411  * @{
9412  */
9413 
9414 /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
9415 /*! @{ */
9416 
9417 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
9418 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
9419 /*! PT1_DC - Product term 1, D input configuration
9420  *  0b00..Force the D input in this product term to a logical zero
9421  *  0b01..Pass the D input in this product term
9422  *  0b10..Complement the D input in this product term
9423  *  0b11..Force the D input in this product term to a logical one
9424  */
9425 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
9426 
9427 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
9428 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
9429 /*! PT1_CC - Product term 1, C input configuration
9430  *  0b00..Force the C input in this product term to a logical zero
9431  *  0b01..Pass the C input in this product term
9432  *  0b10..Complement the C input in this product term
9433  *  0b11..Force the C input in this product term to a logical one
9434  */
9435 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
9436 
9437 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
9438 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
9439 /*! PT1_BC - Product term 1, B input configuration
9440  *  0b00..Force the B input in this product term to a logical zero
9441  *  0b01..Pass the B input in this product term
9442  *  0b10..Complement the B input in this product term
9443  *  0b11..Force the B input in this product term to a logical one
9444  */
9445 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
9446 
9447 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
9448 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
9449 /*! PT1_AC - Product term 1, A input configuration
9450  *  0b00..Force the A input in this product term to a logical zero
9451  *  0b01..Pass the A input in this product term
9452  *  0b10..Complement the A input in this product term
9453  *  0b11..Force the A input in this product term to a logical one
9454  */
9455 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
9456 
9457 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
9458 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
9459 /*! PT0_DC - Product term 0, D input configuration
9460  *  0b00..Force the D input in this product term to a logical zero
9461  *  0b01..Pass the D input in this product term
9462  *  0b10..Complement the D input in this product term
9463  *  0b11..Force the D input in this product term to a logical one
9464  */
9465 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
9466 
9467 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
9468 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
9469 /*! PT0_CC - Product term 0, C input configuration
9470  *  0b00..Force the C input in this product term to a logical zero
9471  *  0b01..Pass the C input in this product term
9472  *  0b10..Complement the C input in this product term
9473  *  0b11..Force the C input in this product term to a logical one
9474  */
9475 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
9476 
9477 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
9478 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
9479 /*! PT0_BC - Product term 0, B input configuration
9480  *  0b00..Force the B input in this product term to a logical zero
9481  *  0b01..Pass the B input in this product term
9482  *  0b10..Complement the B input in this product term
9483  *  0b11..Force the B input in this product term to a logical one
9484  */
9485 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
9486 
9487 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
9488 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
9489 /*! PT0_AC - Product term 0, A input configuration
9490  *  0b00..Force the A input in this product term to a logical zero
9491  *  0b01..Pass the A input in this product term
9492  *  0b10..Complement the A input in this product term
9493  *  0b11..Force the A input in this product term to a logical one
9494  */
9495 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
9496 /*! @} */
9497 
9498 /* The count of AOI_BFCRT01 */
9499 #define AOI_BFCRT01_COUNT                        (4U)
9500 
9501 /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
9502 /*! @{ */
9503 
9504 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
9505 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
9506 /*! PT3_DC - Product term 3, D input configuration
9507  *  0b00..Force the D input in this product term to a logical zero
9508  *  0b01..Pass the D input in this product term
9509  *  0b10..Complement the D input in this product term
9510  *  0b11..Force the D input in this product term to a logical one
9511  */
9512 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
9513 
9514 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
9515 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
9516 /*! PT3_CC - Product term 3, C input configuration
9517  *  0b00..Force the C input in this product term to a logical zero
9518  *  0b01..Pass the C input in this product term
9519  *  0b10..Complement the C input in this product term
9520  *  0b11..Force the C input in this product term to a logical one
9521  */
9522 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
9523 
9524 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
9525 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
9526 /*! PT3_BC - Product term 3, B input configuration
9527  *  0b00..Force the B input in this product term to a logical zero
9528  *  0b01..Pass the B input in this product term
9529  *  0b10..Complement the B input in this product term
9530  *  0b11..Force the B input in this product term to a logical one
9531  */
9532 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
9533 
9534 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
9535 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
9536 /*! PT3_AC - Product term 3, A input configuration
9537  *  0b00..Force the A input in this product term to a logical zero
9538  *  0b01..Pass the A input in this product term
9539  *  0b10..Complement the A input in this product term
9540  *  0b11..Force the A input in this product term to a logical one
9541  */
9542 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
9543 
9544 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
9545 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
9546 /*! PT2_DC - Product term 2, D input configuration
9547  *  0b00..Force the D input in this product term to a logical zero
9548  *  0b01..Pass the D input in this product term
9549  *  0b10..Complement the D input in this product term
9550  *  0b11..Force the D input in this product term to a logical one
9551  */
9552 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
9553 
9554 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
9555 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
9556 /*! PT2_CC - Product term 2, C input configuration
9557  *  0b00..Force the C input in this product term to a logical zero
9558  *  0b01..Pass the C input in this product term
9559  *  0b10..Complement the C input in this product term
9560  *  0b11..Force the C input in this product term to a logical one
9561  */
9562 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
9563 
9564 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
9565 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
9566 /*! PT2_BC - Product term 2, B input configuration
9567  *  0b00..Force the B input in this product term to a logical zero
9568  *  0b01..Pass the B input in this product term
9569  *  0b10..Complement the B input in this product term
9570  *  0b11..Force the B input in this product term to a logical one
9571  */
9572 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
9573 
9574 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
9575 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
9576 /*! PT2_AC - Product term 2, A input configuration
9577  *  0b00..Force the A input in this product term to a logical zero
9578  *  0b01..Pass the A input in this product term
9579  *  0b10..Complement the A input in this product term
9580  *  0b11..Force the A input in this product term to a logical one
9581  */
9582 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
9583 /*! @} */
9584 
9585 /* The count of AOI_BFCRT23 */
9586 #define AOI_BFCRT23_COUNT                        (4U)
9587 
9588 
9589 /*!
9590  * @}
9591  */ /* end of group AOI_Register_Masks */
9592 
9593 
9594 /* AOI - Peripheral instance base addresses */
9595 /** Peripheral AOI1 base address */
9596 #define AOI1_BASE                                (0x400B8000u)
9597 /** Peripheral AOI1 base pointer */
9598 #define AOI1                                     ((AOI_Type *)AOI1_BASE)
9599 /** Peripheral AOI2 base address */
9600 #define AOI2_BASE                                (0x400BC000u)
9601 /** Peripheral AOI2 base pointer */
9602 #define AOI2                                     ((AOI_Type *)AOI2_BASE)
9603 /** Array initializer of AOI peripheral base addresses */
9604 #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE }
9605 /** Array initializer of AOI peripheral base pointers */
9606 #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2 }
9607 
9608 /*!
9609  * @}
9610  */ /* end of group AOI_Peripheral_Access_Layer */
9611 
9612 
9613 /* ----------------------------------------------------------------------------
9614    -- ASRC Peripheral Access Layer
9615    ---------------------------------------------------------------------------- */
9616 
9617 /*!
9618  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
9619  * @{
9620  */
9621 
9622 /** ASRC - Register Layout Typedef */
9623 typedef struct {
9624   __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
9625   __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
9626        uint8_t RESERVED_0[4];
9627   __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
9628   __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
9629   __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
9630   __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
9631   __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
9632   __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
9633        uint8_t RESERVED_1[28];
9634   __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
9635   __IO uint32_t ASRTFR1;                           /**< ASRC Task Queue FIFO Register 1, offset: 0x54 */
9636        uint8_t RESERVED_2[4];
9637   __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
9638   __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
9639   __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
9640   __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
9641   __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
9642   __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
9643   __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
9644        uint8_t RESERVED_3[8];
9645   __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
9646   __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
9647   __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
9648   __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
9649   __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
9650   __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
9651   __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
9652   __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
9653   __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
9654   __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
9655   __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
9656   __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
9657   __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
9658   __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
9659        uint8_t RESERVED_4[8];
9660   __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
9661 } ASRC_Type;
9662 
9663 /* ----------------------------------------------------------------------------
9664    -- ASRC Register Masks
9665    ---------------------------------------------------------------------------- */
9666 
9667 /*!
9668  * @addtogroup ASRC_Register_Masks ASRC Register Masks
9669  * @{
9670  */
9671 
9672 /*! @name ASRCTR - ASRC Control Register */
9673 /*! @{ */
9674 
9675 #define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
9676 #define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
9677 /*! ASRCEN - ASRCEN
9678  *  0b0..operation of ASRC disabled
9679  *  0b1..operation ASRC is enabled
9680  */
9681 #define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
9682 
9683 #define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
9684 #define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
9685 /*! ASREA - ASREA
9686  *  0b0..operation of conversion A is disabled
9687  *  0b1..operation of conversion A is enabled
9688  */
9689 #define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
9690 
9691 #define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
9692 #define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
9693 /*! ASREB - ASREB
9694  *  0b0..operation of conversion B is disabled
9695  *  0b1..operation of conversion B is enabled
9696  */
9697 #define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
9698 
9699 #define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
9700 #define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
9701 /*! ASREC - ASREC
9702  *  0b0..operation of conversion C is disabled
9703  *  0b1..operation of conversion C is enabled
9704  */
9705 #define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
9706 
9707 #define ASRC_ASRCTR_SRST_MASK                    (0x10U)
9708 #define ASRC_ASRCTR_SRST_SHIFT                   (4U)
9709 /*! SRST - SRST
9710  *  0b0..ASRC Software reset cleared
9711  *  0b1..ASRC Software reset generated. NOTE: This is a self-clear bit
9712  */
9713 #define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
9714 
9715 #define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
9716 #define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
9717 /*! IDRA - IDRA
9718  *  0b0..ASRC internal measured ratio is used
9719  *  0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used
9720  */
9721 #define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
9722 
9723 #define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
9724 #define ASRC_ASRCTR_USRA_SHIFT                   (14U)
9725 /*! USRA - USRA
9726  *  0b1..Use ratio as the input to ASRC for pair A
9727  *  0b0..Do not use ratio as the input to ASRC for pair A
9728  */
9729 #define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
9730 
9731 #define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
9732 #define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
9733 /*! IDRB - IDRB
9734  *  0b0..ASRC internal measured ratio is used
9735  *  0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used
9736  */
9737 #define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
9738 
9739 #define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
9740 #define ASRC_ASRCTR_USRB_SHIFT                   (16U)
9741 /*! USRB - USRB
9742  *  0b1..Use ratio as the input to ASRC for pair B
9743  *  0b0..Do not use ratio as the input to ASRC for pair B
9744  */
9745 #define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
9746 
9747 #define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
9748 #define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
9749 /*! IDRC - IDRC
9750  *  0b0..ASRC internal measured ratio is used
9751  *  0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used
9752  */
9753 #define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
9754 
9755 #define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
9756 #define ASRC_ASRCTR_USRC_SHIFT                   (18U)
9757 /*! USRC - USRC
9758  *  0b1..Use ratio as the input to ASRC for pair C
9759  *  0b0..Do not use ratio as the input to ASRC for pair C
9760  */
9761 #define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
9762 
9763 #define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
9764 #define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
9765 /*! ATSA - ATSA
9766  *  0b1..Pair A automatically updates its pre-processing and post-processing options
9767  *  0b0..Pair A does not automatically update its pre-processing and post-processing options
9768  */
9769 #define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
9770 
9771 #define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
9772 #define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
9773 /*! ATSB - ATSB
9774  *  0b1..Pair B automatically updates its pre-processing and post-processing options
9775  *  0b0..Pair B does not automatically update its pre-processing and post-processing options
9776  */
9777 #define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
9778 
9779 #define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
9780 #define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
9781 /*! ATSC - ATSC
9782  *  0b1..Pair C automatically updates its pre-processing and post-processing options
9783  *  0b0..Pair C does not automatically update its pre-processing and post-processing options
9784  */
9785 #define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
9786 /*! @} */
9787 
9788 /*! @name ASRIER - ASRC Interrupt Enable Register */
9789 /*! @{ */
9790 
9791 #define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
9792 #define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
9793 /*! ADIEA - ADIEA
9794  *  0b1..interrupt enabled
9795  *  0b0..interrupt disabled
9796  */
9797 #define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
9798 
9799 #define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
9800 #define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
9801 /*! ADIEB - ADIEB
9802  *  0b1..interrupt enabled
9803  *  0b0..interrupt disabled
9804  */
9805 #define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
9806 
9807 #define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
9808 #define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
9809 /*! ADIEC - ADIEC
9810  *  0b1..interrupt enabled
9811  *  0b0..interrupt disabled
9812  */
9813 #define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
9814 
9815 #define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
9816 #define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
9817 /*! ADOEA - ADOEA
9818  *  0b1..interrupt enabled
9819  *  0b0..interrupt disabled
9820  */
9821 #define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
9822 
9823 #define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
9824 #define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
9825 /*! ADOEB - ADOEB
9826  *  0b1..interrupt enabled
9827  *  0b0..interrupt disabled
9828  */
9829 #define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
9830 
9831 #define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
9832 #define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
9833 /*! ADOEC - ADOEC
9834  *  0b1..interrupt enabled
9835  *  0b0..interrupt disabled
9836  */
9837 #define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
9838 
9839 #define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
9840 #define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
9841 /*! AOLIE - AOLIE
9842  *  0b1..interrupt enabled
9843  *  0b0..interrupt disabled
9844  */
9845 #define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
9846 
9847 #define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
9848 #define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
9849 /*! AFPWE - AFPWE
9850  *  0b1..interrupt enabled
9851  *  0b0..interrupt disabled
9852  */
9853 #define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
9854 /*! @} */
9855 
9856 /*! @name ASRCNCR - ASRC Channel Number Configuration Register */
9857 /*! @{ */
9858 
9859 #define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
9860 #define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
9861 /*! ANCA - ANCA
9862  *  0b0000..0 channels in A (Pair A is disabled)
9863  *  0b0001..1 channel in A
9864  *  0b0010..2 channels in A
9865  *  0b0011..3 channels in A
9866  *  0b0100..4 channels in A
9867  *  0b0101..5 channels in A
9868  *  0b0110..6 channels in A
9869  *  0b0111..7 channels in A
9870  *  0b1000..8 channels in A
9871  *  0b1001..9 channels in A
9872  *  0b1010..10 channels in A
9873  *  0b1011-0b1111..Should not be used.
9874  */
9875 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
9876 
9877 #define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
9878 #define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
9879 /*! ANCB - ANCB
9880  *  0b0000..0 channels in B (Pair B is disabled)
9881  *  0b0001..1 channel in B
9882  *  0b0010..2 channels in B
9883  *  0b0011..3 channels in B
9884  *  0b0100..4 channels in B
9885  *  0b0101..5 channels in B
9886  *  0b0110..6 channels in B
9887  *  0b0111..7 channels in B
9888  *  0b1000..8 channels in B
9889  *  0b1001..9 channels in B
9890  *  0b1010..10 channels in B
9891  *  0b1011-0b1111..Should not be used.
9892  */
9893 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
9894 
9895 #define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
9896 #define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
9897 /*! ANCC - ANCC
9898  *  0b0000..0 channels in C (Pair C is disabled)
9899  *  0b0001..1 channel in C
9900  *  0b0010..2 channels in C
9901  *  0b0011..3 channels in C
9902  *  0b0100..4 channels in C
9903  *  0b0101..5 channels in C
9904  *  0b0110..6 channels in C
9905  *  0b0111..7 channels in C
9906  *  0b1000..8 channels in C
9907  *  0b1001..9 channels in C
9908  *  0b1010..10 channels in C
9909  *  0b1011-0b1111..Should not be used.
9910  */
9911 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
9912 /*! @} */
9913 
9914 /*! @name ASRCFG - ASRC Filter Configuration Status Register */
9915 /*! @{ */
9916 
9917 #define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
9918 #define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
9919 /*! PREMODA - PREMODA
9920  *  0b00..Select Upsampling-by-2
9921  *  0b01..Select Direct-Connection
9922  *  0b10..Select Downsampling-by-2
9923  *  0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use.
9924  */
9925 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
9926 
9927 #define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
9928 #define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
9929 /*! POSTMODA - POSTMODA
9930  *  0b00..Select Upsampling-by-2
9931  *  0b01..Select Direct-Connection
9932  *  0b10..Select Downsampling-by-2
9933  *  0b11..Reserved.
9934  */
9935 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
9936 
9937 #define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
9938 #define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
9939 /*! PREMODB - PREMODB
9940  *  0b00..Select Upsampling-by-2
9941  *  0b01..Select Direct-Connection
9942  *  0b10..Select Downsampling-by-2
9943  *  0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use.
9944  */
9945 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
9946 
9947 #define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
9948 #define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
9949 /*! POSTMODB - POSTMODB
9950  *  0b00..Select Upsampling-by-2
9951  *  0b01..Select Direct-Connection
9952  *  0b10..Select Downsampling-by-2
9953  *  0b11..Reserved.
9954  */
9955 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
9956 
9957 #define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
9958 #define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
9959 /*! PREMODC - PREMODC
9960  *  0b00..Select Upsampling-by-2
9961  *  0b01..Select Direct-Connection
9962  *  0b10..Select Downsampling-by-2
9963  *  0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use.
9964  */
9965 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
9966 
9967 #define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
9968 #define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
9969 /*! POSTMODC - POSTMODC
9970  *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
9971  *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
9972  *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
9973  *  0b11..Reserved.
9974  */
9975 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
9976 
9977 #define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
9978 #define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
9979 /*! NDPRA - NDPRA
9980  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9981  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
9982  */
9983 #define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
9984 
9985 #define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
9986 #define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
9987 /*! NDPRB - NDPRB
9988  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9989  *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
9990  */
9991 #define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
9992 
9993 #define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
9994 #define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
9995 /*! NDPRC - NDPRC
9996  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9997  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
9998  */
9999 #define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
10000 
10001 #define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
10002 #define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
10003 /*! INIRQA - INIRQA
10004  *  0b0..Initialization for Conversion Pair A not served
10005  *  0b1..Initialization for Conversion Pair A served
10006  */
10007 #define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
10008 
10009 #define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
10010 #define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
10011 /*! INIRQB - INIRQB
10012  *  0b0..Initialization for Conversion Pair B not served
10013  *  0b1..Initialization for Conversion Pair B served
10014  */
10015 #define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
10016 
10017 #define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
10018 #define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
10019 /*! INIRQC - INIRQC
10020  *  0b0..Initialization for Conversion Pair C not served
10021  *  0b1..Initialization for Conversion Pair C served
10022  */
10023 #define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
10024 /*! @} */
10025 
10026 /*! @name ASRCSR - ASRC Clock Source Register */
10027 /*! @{ */
10028 
10029 #define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
10030 #define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
10031 /*! AICSA - AICSA
10032  *  0b0000..bit clock 0
10033  *  0b0001..bit clock 1
10034  *  0b0010..bit clock 2
10035  *  0b0011..bit clock 3
10036  *  0b0100..bit clock 4
10037  *  0b0101..bit clock 5
10038  *  0b0110..bit clock 6
10039  *  0b0111..bit clock 7
10040  *  0b1000..bit clock 8
10041  *  0b1001..bit clock 9
10042  *  0b1010..bit clock A
10043  *  0b1011..bit clock B
10044  *  0b1100..bit clock C
10045  *  0b1101..bit clock D
10046  *  0b1110..bit clock E
10047  *  0b1111..clock disabled, connected to zero
10048  */
10049 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
10050 
10051 #define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
10052 #define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
10053 /*! AICSB - AICSB
10054  *  0b0000..bit clock 0
10055  *  0b0001..bit clock 1
10056  *  0b0010..bit clock 2
10057  *  0b0011..bit clock 3
10058  *  0b0100..bit clock 4
10059  *  0b0101..bit clock 5
10060  *  0b0110..bit clock 6
10061  *  0b0111..bit clock 7
10062  *  0b1000..bit clock 8
10063  *  0b1001..bit clock 9
10064  *  0b1010..bit clock A
10065  *  0b1011..bit clock B
10066  *  0b1100..bit clock C
10067  *  0b1101..bit clock D
10068  *  0b1110..bit clock E
10069  *  0b1111..clock disabled, connected to zero
10070  */
10071 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
10072 
10073 #define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
10074 #define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
10075 /*! AICSC - AICSC
10076  *  0b0000..bit clock 0
10077  *  0b0001..bit clock 1
10078  *  0b0010..bit clock 2
10079  *  0b0011..bit clock 3
10080  *  0b0100..bit clock 4
10081  *  0b0101..bit clock 5
10082  *  0b0110..bit clock 6
10083  *  0b0111..bit clock 7
10084  *  0b1000..bit clock 8
10085  *  0b1001..bit clock 9
10086  *  0b1010..bit clock A
10087  *  0b1011..bit clock B
10088  *  0b1100..bit clock C
10089  *  0b1101..bit clock D
10090  *  0b1110..bit clock E
10091  *  0b1111..clock disabled, connected to zero
10092  */
10093 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
10094 
10095 #define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
10096 #define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
10097 /*! AOCSA - AOCSA
10098  *  0b0000..bit clock 0
10099  *  0b0001..bit clock 1
10100  *  0b0010..bit clock 2
10101  *  0b0011..bit clock 3
10102  *  0b0100..bit clock 4
10103  *  0b0101..bit clock 5
10104  *  0b0110..bit clock 6
10105  *  0b0111..bit clock 7
10106  *  0b1000..bit clock 8
10107  *  0b1001..bit clock 9
10108  *  0b1010..bit clock A
10109  *  0b1011..bit clock B
10110  *  0b1100..bit clock C
10111  *  0b1101..bit clock D
10112  *  0b1110..bit clock E
10113  *  0b1111..clock disabled, connected to zero
10114  */
10115 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
10116 
10117 #define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
10118 #define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
10119 /*! AOCSB - AOCSB
10120  *  0b0000..bit clock 0
10121  *  0b0001..bit clock 1
10122  *  0b0010..bit clock 2
10123  *  0b0011..bit clock 3
10124  *  0b0100..bit clock 4
10125  *  0b0101..bit clock 5
10126  *  0b0110..bit clock 6
10127  *  0b0111..bit clock 7
10128  *  0b1000..bit clock 8
10129  *  0b1001..bit clock 9
10130  *  0b1010..bit clock A
10131  *  0b1011..bit clock B
10132  *  0b1100..bit clock C
10133  *  0b1101..bit clock D
10134  *  0b1110..bit clock E
10135  *  0b1111..clock disabled, connected to zero
10136  */
10137 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
10138 
10139 #define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
10140 #define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
10141 /*! AOCSC - AOCSC
10142  *  0b0000..bit clock 0
10143  *  0b0001..bit clock 1
10144  *  0b0010..bit clock 2
10145  *  0b0011..bit clock 3
10146  *  0b0100..bit clock 4
10147  *  0b0101..bit clock 5
10148  *  0b0110..bit clock 6
10149  *  0b0111..bit clock 7
10150  *  0b1000..bit clock 8
10151  *  0b1001..bit clock 9
10152  *  0b1010..bit clock A
10153  *  0b1011..bit clock B
10154  *  0b1100..bit clock C
10155  *  0b1101..bit clock D
10156  *  0b1110..bit clock E
10157  *  0b1111..clock disabled, connected to zero
10158  */
10159 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
10160 /*! @} */
10161 
10162 /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
10163 /*! @{ */
10164 
10165 #define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
10166 #define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
10167 /*! AICPA - AICPA
10168  */
10169 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
10170 
10171 #define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
10172 #define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
10173 /*! AICDA - AICDA
10174  */
10175 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
10176 
10177 #define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
10178 #define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
10179 /*! AICPB - AICPB
10180  */
10181 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
10182 
10183 #define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
10184 #define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
10185 /*! AICDB - AICDB
10186  */
10187 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
10188 
10189 #define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
10190 #define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
10191 /*! AOCPA - AOCPA
10192  */
10193 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
10194 
10195 #define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
10196 #define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
10197 /*! AOCDA - AOCDA
10198  */
10199 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
10200 
10201 #define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
10202 #define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
10203 /*! AOCPB - AOCPB
10204  */
10205 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
10206 
10207 #define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
10208 #define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
10209 /*! AOCDB - AOCDB
10210  */
10211 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
10212 /*! @} */
10213 
10214 /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
10215 /*! @{ */
10216 
10217 #define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
10218 #define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
10219 /*! AICPC - AICPC
10220  */
10221 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
10222 
10223 #define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
10224 #define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
10225 /*! AICDC - AICDC
10226  */
10227 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
10228 
10229 #define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
10230 #define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
10231 /*! AOCPC - AOCPC
10232  */
10233 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
10234 
10235 #define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
10236 #define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
10237 /*! AOCDC - AOCDC
10238  */
10239 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
10240 /*! @} */
10241 
10242 /*! @name ASRSTR - ASRC Status Register */
10243 /*! @{ */
10244 
10245 #define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
10246 #define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
10247 /*! AIDEA - AIDEA
10248  *  0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1
10249  *  0b0..The threshold has been met and no data input A interrupt is generated
10250  */
10251 #define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
10252 
10253 #define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
10254 #define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
10255 /*! AIDEB - AIDEB
10256  *  0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1
10257  *  0b0..The threshold has been met and no data input B interrupt is generated
10258  */
10259 #define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
10260 
10261 #define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
10262 #define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
10263 /*! AIDEC - AIDEC
10264  *  0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1
10265  *  0b0..The threshold has been met and no data input C interrupt is generated
10266  */
10267 #define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
10268 
10269 #define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
10270 #define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
10271 /*! AODFA - AODFA
10272  *  0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1
10273  *  0b0..The threshold has not yet been met and no data output A interrupt is generated
10274  */
10275 #define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
10276 
10277 #define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
10278 #define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
10279 /*! AODFB - AODFB
10280  *  0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1
10281  *  0b0..The threshold has not yet been met and no data output B interrupt is generated
10282  */
10283 #define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
10284 
10285 #define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
10286 #define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
10287 /*! AODFC - AODFC
10288  *  0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1
10289  *  0b0..The threshold has not yet been met and no data output C interrupt is generated
10290  */
10291 #define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
10292 
10293 #define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
10294 #define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
10295 /*! AOLE - AOLE
10296  *  0b1..Task rate is too high
10297  *  0b0..No overload
10298  */
10299 #define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
10300 
10301 #define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
10302 #define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
10303 /*! FPWT - FPWT
10304  *  0b0..ASRC is not in wait state
10305  *  0b1..ASRC is in wait state
10306  */
10307 #define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
10308 
10309 #define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
10310 #define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
10311 /*! AIDUA - AIDUA
10312  *  0b0..No Underflow in Input data buffer A
10313  *  0b1..Underflow in Input data buffer A
10314  */
10315 #define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
10316 
10317 #define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
10318 #define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
10319 /*! AIDUB - AIDUB
10320  *  0b0..No Underflow in Input data buffer B
10321  *  0b1..Underflow in Input data buffer B
10322  */
10323 #define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
10324 
10325 #define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
10326 #define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
10327 /*! AIDUC - AIDUC
10328  *  0b0..No Underflow in Input data buffer C
10329  *  0b1..Underflow in Input data buffer C
10330  */
10331 #define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
10332 
10333 #define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
10334 #define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
10335 /*! AODOA - AODOA
10336  *  0b0..No Overflow in Output data buffer A
10337  *  0b1..Overflow in Output data buffer A
10338  */
10339 #define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
10340 
10341 #define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
10342 #define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
10343 /*! AODOB - AODOB
10344  *  0b0..No Overflow in Output data buffer B
10345  *  0b1..Overflow in Output data buffer B
10346  */
10347 #define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
10348 
10349 #define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
10350 #define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
10351 /*! AODOC - AODOC
10352  *  0b0..No Overflow in Output data buffer C
10353  *  0b1..Overflow in Output data buffer C
10354  */
10355 #define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
10356 
10357 #define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
10358 #define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
10359 /*! AIOLA - AIOLA
10360  *  0b0..Pair A input task is not oveloaded
10361  *  0b1..Pair A input task is oveloaded
10362  */
10363 #define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
10364 
10365 #define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
10366 #define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
10367 /*! AIOLB - AIOLB
10368  *  0b0..Pair B input task is not oveloaded
10369  *  0b1..Pair B input task is oveloaded
10370  */
10371 #define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
10372 
10373 #define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
10374 #define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
10375 /*! AIOLC - AIOLC
10376  *  0b0..Pair C input task is not oveloaded
10377  *  0b1..Pair C input task is oveloaded
10378  */
10379 #define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
10380 
10381 #define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
10382 #define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
10383 /*! AOOLA - AOOLA
10384  *  0b0..Pair A output task is not oveloaded
10385  *  0b1..Pair A output task is oveloaded
10386  */
10387 #define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
10388 
10389 #define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
10390 #define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
10391 /*! AOOLB - AOOLB
10392  *  0b0..Pair B output task is not oveloaded
10393  *  0b1..Pair B output task is oveloaded
10394  */
10395 #define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
10396 
10397 #define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
10398 #define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
10399 /*! AOOLC - AOOLC
10400  *  0b0..Pair C output task is not oveloaded
10401  *  0b1..Pair C output task is oveloaded
10402  */
10403 #define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
10404 
10405 #define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
10406 #define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
10407 /*! ATQOL - ATQOL
10408  *  0b0..Task queue FIFO logic is not oveloaded
10409  *  0b1..Task queue FIFO logic is oveloaded
10410  */
10411 #define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
10412 
10413 #define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
10414 #define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
10415 /*! DSLCNT - DSLCNT
10416  *  0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO
10417  *  0b1..New DSL counter information is stored in the internal ASRC FIFO
10418  */
10419 #define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
10420 /*! @} */
10421 
10422 /*! @name ASRPM - ASRC Parameter Register n */
10423 /*! @{ */
10424 
10425 #define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
10426 #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
10427 /*! PARAMETER_VALUE - PARAMETER_VALUE
10428  */
10429 #define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
10430 /*! @} */
10431 
10432 /* The count of ASRC_ASRPM */
10433 #define ASRC_ASRPM_COUNT                         (5U)
10434 
10435 /*! @name ASRTFR1 - ASRC Task Queue FIFO Register 1 */
10436 /*! @{ */
10437 
10438 #define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
10439 #define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
10440 /*! TF_BASE - TF_BASE
10441  */
10442 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
10443 
10444 #define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
10445 #define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
10446 /*! TF_FILL - TF_FILL
10447  */
10448 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
10449 /*! @} */
10450 
10451 /*! @name ASRCCR - ASRC Channel Counter Register */
10452 /*! @{ */
10453 
10454 #define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
10455 #define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
10456 /*! ACIA - ACIA
10457  */
10458 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
10459 
10460 #define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
10461 #define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
10462 /*! ACIB - ACIB
10463  */
10464 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
10465 
10466 #define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
10467 #define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
10468 /*! ACIC - ACIC
10469  */
10470 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
10471 
10472 #define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
10473 #define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
10474 /*! ACOA - ACOA
10475  */
10476 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
10477 
10478 #define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
10479 #define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
10480 /*! ACOB - ACOB
10481  */
10482 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
10483 
10484 #define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
10485 #define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
10486 /*! ACOC - ACOC
10487  */
10488 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
10489 /*! @} */
10490 
10491 /*! @name ASRDIA - ASRC Data Input Register for Pair x */
10492 /*! @{ */
10493 
10494 #define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
10495 #define ASRC_ASRDIA_DATA_SHIFT                   (0U)
10496 /*! DATA - DATA
10497  */
10498 #define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
10499 /*! @} */
10500 
10501 /*! @name ASRDOA - ASRC Data Output Register for Pair x */
10502 /*! @{ */
10503 
10504 #define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
10505 #define ASRC_ASRDOA_DATA_SHIFT                   (0U)
10506 /*! DATA - DATA
10507  */
10508 #define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
10509 /*! @} */
10510 
10511 /*! @name ASRDIB - ASRC Data Input Register for Pair x */
10512 /*! @{ */
10513 
10514 #define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
10515 #define ASRC_ASRDIB_DATA_SHIFT                   (0U)
10516 /*! DATA - DATA
10517  */
10518 #define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
10519 /*! @} */
10520 
10521 /*! @name ASRDOB - ASRC Data Output Register for Pair x */
10522 /*! @{ */
10523 
10524 #define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
10525 #define ASRC_ASRDOB_DATA_SHIFT                   (0U)
10526 /*! DATA - DATA
10527  */
10528 #define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
10529 /*! @} */
10530 
10531 /*! @name ASRDIC - ASRC Data Input Register for Pair x */
10532 /*! @{ */
10533 
10534 #define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
10535 #define ASRC_ASRDIC_DATA_SHIFT                   (0U)
10536 /*! DATA - DATA
10537  */
10538 #define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
10539 /*! @} */
10540 
10541 /*! @name ASRDOC - ASRC Data Output Register for Pair x */
10542 /*! @{ */
10543 
10544 #define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
10545 #define ASRC_ASRDOC_DATA_SHIFT                   (0U)
10546 /*! DATA - DATA
10547  */
10548 #define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
10549 /*! @} */
10550 
10551 /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
10552 /*! @{ */
10553 
10554 #define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
10555 #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
10556 /*! IDRATIOA_H - IDRATIOA_H
10557  */
10558 #define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
10559 /*! @} */
10560 
10561 /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
10562 /*! @{ */
10563 
10564 #define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
10565 #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
10566 /*! IDRATIOA_L - IDRATIOA_L
10567  */
10568 #define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
10569 /*! @} */
10570 
10571 /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
10572 /*! @{ */
10573 
10574 #define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
10575 #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
10576 /*! IDRATIOB_H - IDRATIOB_H
10577  */
10578 #define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
10579 /*! @} */
10580 
10581 /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
10582 /*! @{ */
10583 
10584 #define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
10585 #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
10586 /*! IDRATIOB_L - IDRATIOB_L
10587  */
10588 #define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
10589 /*! @} */
10590 
10591 /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
10592 /*! @{ */
10593 
10594 #define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
10595 #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
10596 /*! IDRATIOC_H - IDRATIOC_H
10597  */
10598 #define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
10599 /*! @} */
10600 
10601 /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
10602 /*! @{ */
10603 
10604 #define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
10605 #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
10606 /*! IDRATIOC_L - IDRATIOC_L
10607  */
10608 #define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
10609 /*! @} */
10610 
10611 /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
10612 /*! @{ */
10613 
10614 #define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
10615 #define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
10616 /*! ASR76K - ASR76K
10617  */
10618 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
10619 /*! @} */
10620 
10621 /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
10622 /*! @{ */
10623 
10624 #define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
10625 #define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
10626 /*! ASR56K - ASR56K
10627  */
10628 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
10629 /*! @} */
10630 
10631 /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
10632 /*! @{ */
10633 
10634 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
10635 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
10636 /*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
10637  */
10638 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
10639 
10640 #define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
10641 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
10642 /*! RSYNOFA - RSYNOFA
10643  *  0b1..Force ASRCCR[ACOA]=0
10644  *  0b0..Do not touch ASRCCR[ACOA]
10645  */
10646 #define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
10647 
10648 #define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
10649 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
10650 /*! RSYNIFA - RSYNIFA
10651  *  0b1..Force ASRCCR[ACIA]=0
10652  *  0b0..Do not touch ASRCCR[ACIA]
10653  */
10654 #define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
10655 
10656 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
10657 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
10658 /*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
10659  */
10660 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
10661 
10662 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
10663 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
10664 /*! BYPASSPOLYA - BYPASSPOLYA
10665  *  0b1..Bypass polyphase filtering.
10666  *  0b0..Don't bypass polyphase filtering.
10667  */
10668 #define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
10669 
10670 #define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
10671 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
10672 /*! BUFSTALLA - BUFSTALLA
10673  *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
10674  *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
10675  */
10676 #define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
10677 
10678 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
10679 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
10680 /*! EXTTHRSHA - EXTTHRSHA
10681  *  0b1..Use external defined thresholds.
10682  *  0b0..Use default thresholds.
10683  */
10684 #define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
10685 
10686 #define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
10687 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
10688 /*! ZEROBUFA - ZEROBUFA
10689  *  0b1..Don't zeroize the buffer
10690  *  0b0..Zeroize the buffer
10691  */
10692 #define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
10693 /*! @} */
10694 
10695 /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
10696 /*! @{ */
10697 
10698 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
10699 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
10700 /*! INFIFO_FILLA - INFIFO_FILLA
10701  */
10702 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
10703 
10704 #define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
10705 #define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
10706 /*! IAEA - IAEA
10707  *  0b1..Input FIFO is near empty for Pair A
10708  *  0b0..Input FIFO is not near empty for Pair A
10709  */
10710 #define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
10711 
10712 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
10713 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
10714 /*! OUTFIFO_FILLA - OUTFIFO_FILLA
10715  */
10716 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
10717 
10718 #define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
10719 #define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
10720 /*! OAFA - OAFA
10721  *  0b1..Output FIFO is near full for Pair A
10722  *  0b0..Output FIFO is not near full for Pair A
10723  */
10724 #define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
10725 /*! @} */
10726 
10727 /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
10728 /*! @{ */
10729 
10730 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
10731 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
10732 /*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
10733  */
10734 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
10735 
10736 #define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
10737 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
10738 /*! RSYNOFB - RSYNOFB
10739  *  0b1..Force ASRCCR[ACOB]=0
10740  *  0b0..Do not touch ASRCCR[ACOB]
10741  */
10742 #define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
10743 
10744 #define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
10745 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
10746 /*! RSYNIFB - RSYNIFB
10747  *  0b1..Force ASRCCR[ACIB]=0
10748  *  0b0..Do not touch ASRCCR[ACIB]
10749  */
10750 #define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
10751 
10752 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
10753 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
10754 /*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
10755  */
10756 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
10757 
10758 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
10759 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
10760 /*! BYPASSPOLYB - BYPASSPOLYB
10761  *  0b1..Bypass polyphase filtering.
10762  *  0b0..Don't bypass polyphase filtering.
10763  */
10764 #define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
10765 
10766 #define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
10767 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
10768 /*! BUFSTALLB - BUFSTALLB
10769  *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
10770  *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
10771  */
10772 #define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
10773 
10774 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
10775 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
10776 /*! EXTTHRSHB - EXTTHRSHB
10777  *  0b1..Use external defined thresholds.
10778  *  0b0..Use default thresholds.
10779  */
10780 #define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
10781 
10782 #define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
10783 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
10784 /*! ZEROBUFB - ZEROBUFB
10785  *  0b1..Don't zeroize the buffer
10786  *  0b0..Zeroize the buffer
10787  */
10788 #define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
10789 /*! @} */
10790 
10791 /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
10792 /*! @{ */
10793 
10794 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
10795 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
10796 /*! INFIFO_FILLB - INFIFO_FILLB
10797  */
10798 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
10799 
10800 #define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
10801 #define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
10802 /*! IAEB - IAEB
10803  *  0b1..Input FIFO is near empty for Pair B
10804  *  0b0..Input FIFO is not near empty for Pair B
10805  */
10806 #define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
10807 
10808 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
10809 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
10810 /*! OUTFIFO_FILLB - OUTFIFO_FILLB
10811  */
10812 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
10813 
10814 #define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
10815 #define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
10816 /*! OAFB - OAFB
10817  *  0b1..Output FIFO is near full for Pair B
10818  *  0b0..Output FIFO is not near full for Pair B
10819  */
10820 #define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
10821 /*! @} */
10822 
10823 /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
10824 /*! @{ */
10825 
10826 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
10827 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
10828 /*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
10829  */
10830 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
10831 
10832 #define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
10833 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
10834 /*! RSYNOFC - RSYNOFC
10835  *  0b1..Force ASRCCR[ACOC]=0
10836  *  0b0..Do not touch ASRCCR[ACOC]
10837  */
10838 #define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
10839 
10840 #define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
10841 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
10842 /*! RSYNIFC - RSYNIFC
10843  *  0b1..Force ASRCCR[ACIC]=0
10844  *  0b0..Do not touch ASRCCR[ACIC]
10845  */
10846 #define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
10847 
10848 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
10849 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
10850 /*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
10851  */
10852 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
10853 
10854 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
10855 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
10856 /*! BYPASSPOLYC - BYPASSPOLYC
10857  *  0b1..Bypass polyphase filtering.
10858  *  0b0..Don't bypass polyphase filtering.
10859  */
10860 #define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
10861 
10862 #define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
10863 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
10864 /*! BUFSTALLC - BUFSTALLC
10865  *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
10866  *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
10867  */
10868 #define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
10869 
10870 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
10871 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
10872 /*! EXTTHRSHC - EXTTHRSHC
10873  *  0b1..Use external defined thresholds.
10874  *  0b0..Use default thresholds.
10875  */
10876 #define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
10877 
10878 #define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
10879 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
10880 /*! ZEROBUFC - ZEROBUFC
10881  *  0b1..Don't zeroize the buffer
10882  *  0b0..Zeroize the buffer
10883  */
10884 #define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
10885 /*! @} */
10886 
10887 /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
10888 /*! @{ */
10889 
10890 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
10891 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
10892 /*! INFIFO_FILLC - INFIFO_FILLC
10893  */
10894 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
10895 
10896 #define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
10897 #define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
10898 /*! IAEC - IAEC
10899  *  0b1..Input FIFO is near empty for Pair C
10900  *  0b0..Input FIFO is not near empty for Pair C
10901  */
10902 #define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
10903 
10904 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
10905 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
10906 /*! OUTFIFO_FILLC - OUTFIFO_FILLC
10907  */
10908 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
10909 
10910 #define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
10911 #define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
10912 /*! OAFC - OAFC
10913  *  0b1..Output FIFO is near full for Pair C
10914  *  0b0..Output FIFO is not near full for Pair C
10915  */
10916 #define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
10917 /*! @} */
10918 
10919 /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
10920 /*! @{ */
10921 
10922 #define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
10923 #define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
10924 /*! OW16 - OW16
10925  *  0b1..16-bit output data
10926  *  0b0..24-bit output data.
10927  */
10928 #define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
10929 
10930 #define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
10931 #define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
10932 /*! OSGN - OSGN
10933  *  0b1..Sign extension.
10934  *  0b0..No sign extension.
10935  */
10936 #define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
10937 
10938 #define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
10939 #define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
10940 /*! OMSB - OMSB
10941  *  0b1..MSB aligned.
10942  *  0b0..LSB aligned.
10943  */
10944 #define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
10945 
10946 #define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
10947 #define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
10948 /*! IMSB - IMSB
10949  *  0b1..MSB aligned.
10950  *  0b0..LSB aligned.
10951  */
10952 #define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
10953 
10954 #define ASRC_ASRMCR1_IWD_MASK                    (0x600U)
10955 #define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
10956 /*! IWD - IWD
10957  *  0b00..24-bit audio data.
10958  *  0b01..16-bit audio data.
10959  *  0b10..8-bit audio data.
10960  *  0b11..Reserved.
10961  */
10962 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
10963 /*! @} */
10964 
10965 /* The count of ASRC_ASRMCR1 */
10966 #define ASRC_ASRMCR1_COUNT                       (3U)
10967 
10968 
10969 /*!
10970  * @}
10971  */ /* end of group ASRC_Register_Masks */
10972 
10973 
10974 /* ASRC - Peripheral instance base addresses */
10975 /** Peripheral ASRC base address */
10976 #define ASRC_BASE                                (0x40414000u)
10977 /** Peripheral ASRC base pointer */
10978 #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
10979 /** Array initializer of ASRC peripheral base addresses */
10980 #define ASRC_BASE_ADDRS                          { ASRC_BASE }
10981 /** Array initializer of ASRC peripheral base pointers */
10982 #define ASRC_BASE_PTRS                           { ASRC }
10983 /** Interrupt vectors for the ASRC peripheral type */
10984 #define ASRC_IRQS                                { ASRC_IRQn }
10985 
10986 /*!
10987  * @}
10988  */ /* end of group ASRC_Peripheral_Access_Layer */
10989 
10990 
10991 /* ----------------------------------------------------------------------------
10992    -- AUDIO_PLL Peripheral Access Layer
10993    ---------------------------------------------------------------------------- */
10994 
10995 /*!
10996  * @addtogroup AUDIO_PLL_Peripheral_Access_Layer AUDIO_PLL Peripheral Access Layer
10997  * @{
10998  */
10999 
11000 /** AUDIO_PLL - Register Layout Typedef */
11001 typedef struct {
11002   struct {                                         /* offset: 0x0 */
11003     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
11004     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
11005     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
11006     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
11007   } CTRL0;
11008   struct {                                         /* offset: 0x10 */
11009     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
11010     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
11011     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
11012     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
11013   } SPREAD_SPECTRUM;
11014   struct {                                         /* offset: 0x20 */
11015     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
11016     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
11017     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
11018     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
11019   } NUMERATOR;
11020   struct {                                         /* offset: 0x30 */
11021     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
11022     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
11023     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
11024     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
11025   } DENOMINATOR;
11026 } AUDIO_PLL_Type;
11027 
11028 /* ----------------------------------------------------------------------------
11029    -- AUDIO_PLL Register Masks
11030    ---------------------------------------------------------------------------- */
11031 
11032 /*!
11033  * @addtogroup AUDIO_PLL_Register_Masks AUDIO_PLL Register Masks
11034  * @{
11035  */
11036 
11037 /*! @name CTRL0 - Fractional PLL Control Register */
11038 /*! @{ */
11039 
11040 #define AUDIO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
11041 #define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
11042 /*! DIV_SELECT - DIV_SELECT
11043  */
11044 #define AUDIO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK)
11045 
11046 #define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
11047 #define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
11048 /*! ENABLE_ALT - ENABLE_ALT
11049  *  0b0..Disable the alternate clock output
11050  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
11051  */
11052 #define AUDIO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK)
11053 
11054 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
11055 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
11056 /*! HOLD_RING_OFF - PLL Start up initialization
11057  *  0b0..Normal operation
11058  *  0b1..Initialize PLL start up
11059  */
11060 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK)
11061 
11062 #define AUDIO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
11063 #define AUDIO_PLL_CTRL0_POWERUP_SHIFT            (14U)
11064 /*! POWERUP - POWERUP
11065  *  0b1..Power Up the PLL
11066  *  0b0..Power down the PLL
11067  */
11068 #define AUDIO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK)
11069 
11070 #define AUDIO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
11071 #define AUDIO_PLL_CTRL0_ENABLE_SHIFT             (15U)
11072 /*! ENABLE - ENABLE
11073  *  0b1..Enable the clock output
11074  *  0b0..Disable the clock output
11075  */
11076 #define AUDIO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK)
11077 
11078 #define AUDIO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
11079 #define AUDIO_PLL_CTRL0_BYPASS_SHIFT             (16U)
11080 /*! BYPASS - BYPASS
11081  *  0b1..Bypass the PLL
11082  *  0b0..No Bypass
11083  */
11084 #define AUDIO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK)
11085 
11086 #define AUDIO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
11087 #define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
11088 /*! DITHER_EN - DITHER_EN
11089  *  0b0..Disable Dither
11090  *  0b1..Enable Dither
11091  */
11092 #define AUDIO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK)
11093 
11094 #define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
11095 #define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
11096 /*! BIAS_TRIM - BIAS_TRIM
11097  */
11098 #define AUDIO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK)
11099 
11100 #define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
11101 #define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
11102 /*! PLL_REG_EN - PLL_REG_EN
11103  */
11104 #define AUDIO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK)
11105 
11106 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
11107 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
11108 /*! POST_DIV_SEL - Post Divide Select
11109  *  0b000..Divide by 1
11110  *  0b001..Divide by 2
11111  *  0b010..Divide by 4
11112  *  0b011..Divide by 8
11113  *  0b100..Divide by 16
11114  *  0b101..Divide by 32
11115  */
11116 #define AUDIO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
11117 
11118 #define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
11119 #define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
11120 /*! BIAS_SELECT - BIAS_SELECT
11121  *  0b0..Used in SoCs with a bias current of 10uA
11122  *  0b1..Used in SoCs with a bias current of 2uA
11123  */
11124 #define AUDIO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK)
11125 /*! @} */
11126 
11127 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
11128 /*! @{ */
11129 
11130 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
11131 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
11132 /*! STEP - Step
11133  */
11134 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK)
11135 
11136 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
11137 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
11138 /*! ENABLE - Enable
11139  */
11140 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
11141 
11142 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
11143 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
11144 /*! STOP - Stop
11145  */
11146 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK)
11147 /*! @} */
11148 
11149 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
11150 /*! @{ */
11151 
11152 #define AUDIO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
11153 #define AUDIO_PLL_NUMERATOR_NUM_SHIFT            (0U)
11154 /*! NUM - Numerator
11155  */
11156 #define AUDIO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK)
11157 /*! @} */
11158 
11159 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
11160 /*! @{ */
11161 
11162 #define AUDIO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
11163 #define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
11164 /*! DENOM - Denominator
11165  */
11166 #define AUDIO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK)
11167 /*! @} */
11168 
11169 
11170 /*!
11171  * @}
11172  */ /* end of group AUDIO_PLL_Register_Masks */
11173 
11174 
11175 /* AUDIO_PLL - Peripheral instance base addresses */
11176 /** Peripheral AUDIO_PLL base address */
11177 #define AUDIO_PLL_BASE                           (0u)
11178 /** Peripheral AUDIO_PLL base pointer */
11179 #define AUDIO_PLL                                ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
11180 /** Array initializer of AUDIO_PLL peripheral base addresses */
11181 #define AUDIO_PLL_BASE_ADDRS                     { AUDIO_PLL_BASE }
11182 /** Array initializer of AUDIO_PLL peripheral base pointers */
11183 #define AUDIO_PLL_BASE_PTRS                      { AUDIO_PLL }
11184 
11185 /*!
11186  * @}
11187  */ /* end of group AUDIO_PLL_Peripheral_Access_Layer */
11188 
11189 
11190 /* ----------------------------------------------------------------------------
11191    -- CAAM Peripheral Access Layer
11192    ---------------------------------------------------------------------------- */
11193 
11194 /*!
11195  * @addtogroup CAAM_Peripheral_Access_Layer CAAM Peripheral Access Layer
11196  * @{
11197  */
11198 
11199 /** CAAM - Register Layout Typedef */
11200 typedef struct {
11201        uint8_t RESERVED_0[4];
11202   __IO uint32_t MCFGR;                             /**< Master Configuration Register, offset: 0x4 */
11203   __IO uint32_t PAGE0_SDID;                        /**< Page 0 SDID Register, offset: 0x8 */
11204   __IO uint32_t SCFGR;                             /**< Security Configuration Register, offset: 0xC */
11205   struct {                                         /* offset: 0x10, array step: 0x8 */
11206     __IO uint32_t JRDID_MS;                          /**< Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8 */
11207     __IO uint32_t JRDID_LS;                          /**< Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8 */
11208   } JRADID[4];
11209        uint8_t RESERVED_1[40];
11210   __IO uint32_t DEBUGCTL;                          /**< Debug Control Register, offset: 0x58 */
11211   __IO uint32_t JRSTARTR;                          /**< Job Ring Start Register, offset: 0x5C */
11212   __IO uint32_t RTIC_OWN;                          /**< RTIC OWN Register, offset: 0x60 */
11213   struct {                                         /* offset: 0x64, array step: 0x8 */
11214     __IO uint32_t RTIC_DID;                          /**< RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8 */
11215          uint8_t RESERVED_0[4];
11216   } RTICADID[4];
11217        uint8_t RESERVED_2[16];
11218   __IO uint32_t DECORSR;                           /**< DECO Request Source Register, offset: 0x94 */
11219        uint8_t RESERVED_3[4];
11220   __IO uint32_t DECORR;                            /**< DECO Request Register, offset: 0x9C */
11221   struct {                                         /* offset: 0xA0, array step: 0x8 */
11222     __IO uint32_t DECODID_MS;                        /**< DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8 */
11223     __IO uint32_t DECODID_LS;                        /**< DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8 */
11224   } DECONDID[1];
11225        uint8_t RESERVED_4[120];
11226   __IO uint32_t DAR;                               /**< DECO Availability Register, offset: 0x120 */
11227   __O  uint32_t DRR;                               /**< DECO Reset Register, offset: 0x124 */
11228        uint8_t RESERVED_5[92];
11229   struct {                                         /* offset: 0x184, array step: 0x8 */
11230     __IO uint32_t JRSMVBAR;                          /**< Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8 */
11231          uint8_t RESERVED_0[4];
11232   } JRNSMVBAR[4];
11233        uint8_t RESERVED_6[124];
11234   __IO uint32_t PBSL;                              /**< Peak Bandwidth Smoothing Limit Register, offset: 0x220 */
11235        uint8_t RESERVED_7[28];
11236   struct {                                         /* offset: 0x240, array step: 0x10 */
11237     __I  uint32_t DMA_AIDL_MAP_MS;                   /**< DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10 */
11238     __I  uint32_t DMA_AIDL_MAP_LS;                   /**< DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10 */
11239     __I  uint32_t DMA_AIDM_MAP_MS;                   /**< DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10 */
11240     __I  uint32_t DMA_AIDM_MAP_LS;                   /**< DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10 */
11241   } AID_CNTS[1];
11242   __I  uint32_t DMA0_AID_ENB;                      /**< DMA0 AXI ID Enable Register, offset: 0x250 */
11243        uint8_t RESERVED_8[12];
11244   __IO uint64_t DMA0_ARD_TC;                       /**< DMA0 AXI Read Timing Check Register, offset: 0x260 */
11245        uint8_t RESERVED_9[4];
11246   __IO uint32_t DMA0_ARD_LAT;                      /**< DMA0 Read Timing Check Latency Register, offset: 0x26C */
11247   __IO uint64_t DMA0_AWR_TC;                       /**< DMA0 AXI Write Timing Check Register, offset: 0x270 */
11248        uint8_t RESERVED_10[4];
11249   __IO uint32_t DMA0_AWR_LAT;                      /**< DMA0 Write Timing Check Latency Register, offset: 0x27C */
11250        uint8_t RESERVED_11[128];
11251   __IO uint8_t MPPKR[64];                          /**< Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1 */
11252        uint8_t RESERVED_12[64];
11253   __IO uint8_t MPMR[32];                           /**< Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1 */
11254        uint8_t RESERVED_13[32];
11255   __I  uint8_t MPTESTR[32];                        /**< Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1 */
11256        uint8_t RESERVED_14[24];
11257   __I  uint32_t MPECC;                             /**< Manufacturing Protection ECC Register, offset: 0x3F8 */
11258        uint8_t RESERVED_15[4];
11259   __IO uint32_t JDKEKR[8];                         /**< Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4 */
11260   __IO uint32_t TDKEKR[8];                         /**< Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4 */
11261   __IO uint32_t TDSKR[8];                          /**< Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4 */
11262        uint8_t RESERVED_16[128];
11263   __IO uint64_t SKNR;                              /**< Secure Key Nonce Register, offset: 0x4E0 */
11264        uint8_t RESERVED_17[36];
11265   __I  uint32_t DMA_STA;                           /**< DMA Status Register, offset: 0x50C */
11266   __I  uint32_t DMA_X_AID_7_4_MAP;                 /**< DMA_X_AID_7_4_MAP, offset: 0x510 */
11267   __I  uint32_t DMA_X_AID_3_0_MAP;                 /**< DMA_X_AID_3_0_MAP, offset: 0x514 */
11268   __I  uint32_t DMA_X_AID_15_12_MAP;               /**< DMA_X_AID_15_12_MAP, offset: 0x518 */
11269   __I  uint32_t DMA_X_AID_11_8_MAP;                /**< DMA_X_AID_11_8_MAP, offset: 0x51C */
11270        uint8_t RESERVED_18[4];
11271   __I  uint32_t DMA_X_AID_15_0_EN;                 /**< DMA_X AXI ID Map Enable Register, offset: 0x524 */
11272        uint8_t RESERVED_19[8];
11273   __IO uint32_t DMA_X_ARTC_CTL;                    /**< DMA_X AXI Read Timing Check Control Register, offset: 0x530 */
11274   __IO uint32_t DMA_X_ARTC_LC;                     /**< DMA_X AXI Read Timing Check Late Count Register, offset: 0x534 */
11275   __IO uint32_t DMA_X_ARTC_SC;                     /**< DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538 */
11276   __IO uint32_t DMA_X_ARTC_LAT;                    /**< DMA_X Read Timing Check Latency Register, offset: 0x53C */
11277   __IO uint32_t DMA_X_AWTC_CTL;                    /**< DMA_X AXI Write Timing Check Control Register, offset: 0x540 */
11278   __IO uint32_t DMA_X_AWTC_LC;                     /**< DMA_X AXI Write Timing Check Late Count Register, offset: 0x544 */
11279   __IO uint32_t DMA_X_AWTC_SC;                     /**< DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548 */
11280   __IO uint32_t DMA_X_AWTC_LAT;                    /**< DMA_X Write Timing Check Latency Register, offset: 0x54C */
11281        uint8_t RESERVED_20[176];
11282   __IO uint32_t RTMCTL;                            /**< RNG TRNG Miscellaneous Control Register, offset: 0x600 */
11283   __IO uint32_t RTSCMISC;                          /**< RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604 */
11284   __IO uint32_t RTPKRRNG;                          /**< RNG TRNG Poker Range Register, offset: 0x608 */
11285   union {                                          /* offset: 0x60C */
11286     __IO uint32_t RTPKRMAX;                          /**< RNG TRNG Poker Maximum Limit Register, offset: 0x60C */
11287     __I  uint32_t RTPKRSQ;                           /**< RNG TRNG Poker Square Calculation Result Register, offset: 0x60C */
11288   };
11289   __IO uint32_t RTSDCTL;                           /**< RNG TRNG Seed Control Register, offset: 0x610 */
11290   union {                                          /* offset: 0x614 */
11291     __IO uint32_t RTSBLIM;                           /**< RNG TRNG Sparse Bit Limit Register, offset: 0x614 */
11292     __I  uint32_t RTTOTSAM;                          /**< RNG TRNG Total Samples Register, offset: 0x614 */
11293   };
11294   __IO uint32_t RTFRQMIN;                          /**< RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618 */
11295   union {                                          /* offset: 0x61C */
11296     struct {                                         /* offset: 0x61C */
11297       __I  uint32_t RTFRQCNT;                          /**< RNG TRNG Frequency Count Register, offset: 0x61C */
11298       __I  uint32_t RTSCMC;                            /**< RNG TRNG Statistical Check Monobit Count Register, offset: 0x620 */
11299       __I  uint32_t RTSCR1C;                           /**< RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624 */
11300       __I  uint32_t RTSCR2C;                           /**< RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628 */
11301       __I  uint32_t RTSCR3C;                           /**< RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C */
11302       __I  uint32_t RTSCR4C;                           /**< RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630 */
11303       __I  uint32_t RTSCR5C;                           /**< RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634 */
11304       __I  uint32_t RTSCR6PC;                          /**< RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638 */
11305     } COUNT;
11306     struct {                                         /* offset: 0x61C */
11307       __IO uint32_t RTFRQMAX;                          /**< RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C */
11308       __IO uint32_t RTSCML;                            /**< RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620 */
11309       __IO uint32_t RTSCR1L;                           /**< RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624 */
11310       __IO uint32_t RTSCR2L;                           /**< RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628 */
11311       __IO uint32_t RTSCR3L;                           /**< RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C */
11312       __IO uint32_t RTSCR4L;                           /**< RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630 */
11313       __IO uint32_t RTSCR5L;                           /**< RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634 */
11314       __IO uint32_t RTSCR6PL;                          /**< RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638 */
11315     } LIMIT;
11316   };
11317   __I  uint32_t RTSTATUS;                          /**< RNG TRNG Status Register, offset: 0x63C */
11318   __I  uint32_t RTENT[16];                         /**< RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4 */
11319   __I  uint32_t RTPKRCNT10;                        /**< RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680 */
11320   __I  uint32_t RTPKRCNT32;                        /**< RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684 */
11321   __I  uint32_t RTPKRCNT54;                        /**< RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688 */
11322   __I  uint32_t RTPKRCNT76;                        /**< RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C */
11323   __I  uint32_t RTPKRCNT98;                        /**< RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690 */
11324   __I  uint32_t RTPKRCNTBA;                        /**< RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694 */
11325   __I  uint32_t RTPKRCNTDC;                        /**< RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698 */
11326   __I  uint32_t RTPKRCNTFE;                        /**< RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C */
11327        uint8_t RESERVED_21[32];
11328   __I  uint32_t RDSTA;                             /**< RNG DRNG Status Register, offset: 0x6C0 */
11329        uint8_t RESERVED_22[12];
11330   __I  uint32_t RDINT0;                            /**< RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0 */
11331   __I  uint32_t RDINT1;                            /**< RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4 */
11332        uint8_t RESERVED_23[8];
11333   __IO uint32_t RDHCNTL;                           /**< RNG DRNG Hash Control Register, offset: 0x6E0 */
11334   __I  uint32_t RDHDIG;                            /**< RNG DRNG Hash Digest Register, offset: 0x6E4 */
11335   __O  uint32_t RDHBUF;                            /**< RNG DRNG Hash Buffer Register, offset: 0x6E8 */
11336        uint8_t RESERVED_24[788];
11337   struct {                                         /* offset: 0xA00, array step: 0x10 */
11338     __I  uint32_t PX_SDID_PG0;                       /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */
11339     __IO uint32_t PX_SMAPR_PG0;                      /**< Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10 */
11340     __IO uint32_t PX_SMAG2_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10 */
11341     __IO uint32_t PX_SMAG1_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10 */
11342   } PX_PG0[16];
11343   __IO uint32_t REIS;                              /**< Recoverable Error Interrupt Status, offset: 0xB00 */
11344   __IO uint32_t REIE;                              /**< Recoverable Error Interrupt Enable, offset: 0xB04 */
11345   __I  uint32_t REIF;                              /**< Recoverable Error Interrupt Force, offset: 0xB08 */
11346   __IO uint32_t REIH;                              /**< Recoverable Error Interrupt Halt, offset: 0xB0C */
11347        uint8_t RESERVED_25[192];
11348   __IO uint32_t SMWPJRR[4];                        /**< Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4 */
11349        uint8_t RESERVED_26[4];
11350   __O  uint32_t SMCR_PG0;                          /**< Secure Memory Command Register, offset: 0xBE4 */
11351        uint8_t RESERVED_27[4];
11352   __I  uint32_t SMCSR_PG0;                         /**< Secure Memory Command Status Register, offset: 0xBEC */
11353        uint8_t RESERVED_28[8];
11354   __I  uint32_t CAAMVID_MS_TRAD;                   /**< CAAM Version ID Register, most-significant half, offset: 0xBF8 */
11355   __I  uint32_t CAAMVID_LS_TRAD;                   /**< CAAM Version ID Register, least-significant half, offset: 0xBFC */
11356   struct {                                         /* offset: 0xC00, array step: 0x20 */
11357     __I  uint64_t HT_JD_ADDR;                        /**< Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20 */
11358     __I  uint64_t HT_SD_ADDR;                        /**< Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20 */
11359     __I  uint32_t HT_JQ_CTRL_MS;                     /**< Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20 */
11360     __I  uint32_t HT_JQ_CTRL_LS;                     /**< Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20 */
11361          uint8_t RESERVED_0[4];
11362     __I  uint32_t HT_STATUS;                         /**< Holding Tank Status, array offset: 0xC1C, array step: 0x20 */
11363   } HTA[1];
11364        uint8_t RESERVED_29[4];
11365   __IO uint32_t JQ_DEBUG_SEL;                      /**< Job Queue Debug Select Register, offset: 0xC24 */
11366        uint8_t RESERVED_30[404];
11367   __I  uint32_t JRJIDU_LS;                         /**< Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC */
11368   __I  uint32_t JRJDJIFBC;                         /**< Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0 */
11369   __I  uint32_t JRJDJIF;                           /**< Job Ring Job-Done Job ID FIFO, offset: 0xDC4 */
11370        uint8_t RESERVED_31[28];
11371   __I  uint32_t JRJDS1;                            /**< Job Ring Job-Done Source 1, offset: 0xDE4 */
11372        uint8_t RESERVED_32[24];
11373   __I  uint64_t JRJDDA[1];                         /**< Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8 */
11374        uint8_t RESERVED_33[408];
11375   __I  uint32_t CRNR_MS;                           /**< CHA Revision Number Register, most-significant half, offset: 0xFA0 */
11376   __I  uint32_t CRNR_LS;                           /**< CHA Revision Number Register, least-significant half, offset: 0xFA4 */
11377   __I  uint32_t CTPR_MS;                           /**< Compile Time Parameters Register, most-significant half, offset: 0xFA8 */
11378   __I  uint32_t CTPR_LS;                           /**< Compile Time Parameters Register, least-significant half, offset: 0xFAC */
11379        uint8_t RESERVED_34[4];
11380   __I  uint32_t SMSTA;                             /**< Secure Memory Status Register, offset: 0xFB4 */
11381        uint8_t RESERVED_35[4];
11382   __I  uint32_t SMPO;                              /**< Secure Memory Partition Owners Register, offset: 0xFBC */
11383   __I  uint64_t FAR;                               /**< Fault Address Register, offset: 0xFC0 */
11384   __I  uint32_t FADID;                             /**< Fault Address DID Register, offset: 0xFC8 */
11385   __I  uint32_t FADR;                              /**< Fault Address Detail Register, offset: 0xFCC */
11386        uint8_t RESERVED_36[4];
11387   __I  uint32_t CSTA;                              /**< CAAM Status Register, offset: 0xFD4 */
11388   __I  uint32_t SMVID_MS;                          /**< Secure Memory Version ID Register, most-significant half, offset: 0xFD8 */
11389   __I  uint32_t SMVID_LS;                          /**< Secure Memory Version ID Register, least-significant half, offset: 0xFDC */
11390   __I  uint32_t RVID;                              /**< RTIC Version ID Register, offset: 0xFE0 */
11391   __I  uint32_t CCBVID;                            /**< CHA Cluster Block Version ID Register, offset: 0xFE4 */
11392   __I  uint32_t CHAVID_MS;                         /**< CHA Version ID Register, most-significant half, offset: 0xFE8 */
11393   __I  uint32_t CHAVID_LS;                         /**< CHA Version ID Register, least-significant half, offset: 0xFEC */
11394   __I  uint32_t CHANUM_MS;                         /**< CHA Number Register, most-significant half, offset: 0xFF0 */
11395   __I  uint32_t CHANUM_LS;                         /**< CHA Number Register, least-significant half, offset: 0xFF4 */
11396   __I  uint32_t CAAMVID_MS;                        /**< CAAM Version ID Register, most-significant half, offset: 0xFF8 */
11397   __I  uint32_t CAAMVID_LS;                        /**< CAAM Version ID Register, least-significant half, offset: 0xFFC */
11398        uint8_t RESERVED_37[61440];
11399   struct {                                         /* offset: 0x10000, array step: 0x10000 */
11400     __IO uint64_t IRBAR_JR;                          /**< Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000 */
11401          uint8_t RESERVED_0[4];
11402     __IO uint32_t IRSR_JR;                           /**< Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000 */
11403          uint8_t RESERVED_1[4];
11404     __IO uint32_t IRSAR_JR;                          /**< Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000 */
11405          uint8_t RESERVED_2[4];
11406     __IO uint32_t IRJAR_JR;                          /**< Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000 */
11407     __IO uint64_t ORBAR_JR;                          /**< Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000 */
11408          uint8_t RESERVED_3[4];
11409     __IO uint32_t ORSR_JR;                           /**< Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000 */
11410          uint8_t RESERVED_4[4];
11411     __IO uint32_t ORJRR_JR;                          /**< Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000 */
11412          uint8_t RESERVED_5[4];
11413     __IO uint32_t ORSFR_JR;                          /**< Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000 */
11414          uint8_t RESERVED_6[4];
11415     __I  uint32_t JRSTAR_JR;                         /**< Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000 */
11416          uint8_t RESERVED_7[4];
11417     __IO uint32_t JRINTR_JR;                         /**< Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000 */
11418     __IO uint32_t JRCFGR_JR_MS;                      /**< Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000 */
11419     __IO uint32_t JRCFGR_JR_LS;                      /**< Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000 */
11420          uint8_t RESERVED_8[4];
11421     __IO uint32_t IRRIR_JR;                          /**< Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000 */
11422          uint8_t RESERVED_9[4];
11423     __IO uint32_t ORWIR_JR;                          /**< Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000 */
11424          uint8_t RESERVED_10[4];
11425     __O  uint32_t JRCR_JR;                           /**< Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000 */
11426          uint8_t RESERVED_11[1684];
11427     __I  uint32_t JRAAV;                             /**< Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000 */
11428          uint8_t RESERVED_12[248];
11429     __I  uint64_t JRAAA[4];                          /**< Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8 */
11430          uint8_t RESERVED_13[480];
11431     struct {                                         /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11432       __I  uint32_t PX_SDID_JR;                        /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11433       __IO uint32_t PX_SMAPR_JR;                       /**< Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10 */
11434       __IO uint32_t PX_SMAG2_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10 */
11435       __IO uint32_t PX_SMAG1_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10 */
11436     } PX_JR[16];
11437          uint8_t RESERVED_14[228];
11438     __O  uint32_t SMCR_JR;                           /**< Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000 */
11439          uint8_t RESERVED_15[4];
11440     __I  uint32_t SMCSR_JR;                          /**< Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000 */
11441          uint8_t RESERVED_16[528];
11442     __I  uint32_t REIR0JR;                           /**< Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000 */
11443          uint8_t RESERVED_17[4];
11444     __I  uint64_t REIR2JR;                           /**< Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000 */
11445     __I  uint32_t REIR4JR;                           /**< Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000 */
11446     __I  uint32_t REIR5JR;                           /**< Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000 */
11447          uint8_t RESERVED_18[392];
11448     __I  uint32_t CRNR_MS_JR;                        /**< CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000 */
11449     __I  uint32_t CRNR_LS_JR;                        /**< CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000 */
11450     __I  uint32_t CTPR_MS_JR;                        /**< Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000 */
11451     __I  uint32_t CTPR_LS_JR;                        /**< Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000 */
11452          uint8_t RESERVED_19[4];
11453     __I  uint32_t SMSTA_JR;                          /**< Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000 */
11454          uint8_t RESERVED_20[4];
11455     __I  uint32_t SMPO_JR;                           /**< Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000 */
11456     __I  uint64_t FAR_JR;                            /**< Fault Address Register, array offset: 0x10FC0, array step: 0x10000 */
11457     __I  uint32_t FADID_JR;                          /**< Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000 */
11458     __I  uint32_t FADR_JR;                           /**< Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000 */
11459          uint8_t RESERVED_21[4];
11460     __I  uint32_t CSTA_JR;                           /**< CAAM Status Register, array offset: 0x10FD4, array step: 0x10000 */
11461     __I  uint32_t SMVID_MS_JR;                       /**< Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000 */
11462     __I  uint32_t SMVID_LS_JR;                       /**< Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000 */
11463     __I  uint32_t RVID_JR;                           /**< RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000 */
11464     __I  uint32_t CCBVID_JR;                         /**< CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000 */
11465     __I  uint32_t CHAVID_MS_JR;                      /**< CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000 */
11466     __I  uint32_t CHAVID_LS_JR;                      /**< CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000 */
11467     __I  uint32_t CHANUM_MS_JR;                      /**< CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000 */
11468     __I  uint32_t CHANUM_LS_JR;                      /**< CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000 */
11469     __I  uint32_t CAAMVID_MS_JR;                     /**< CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000 */
11470     __I  uint32_t CAAMVID_LS_JR;                     /**< CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000 */
11471          uint8_t RESERVED_22[61440];
11472   } JOBRING[4];
11473        uint8_t RESERVED_38[65540];
11474   __I  uint32_t RSTA;                              /**< RTIC Status Register, offset: 0x60004 */
11475        uint8_t RESERVED_39[4];
11476   __IO uint32_t RCMD;                              /**< RTIC Command Register, offset: 0x6000C */
11477        uint8_t RESERVED_40[4];
11478   __IO uint32_t RCTL;                              /**< RTIC Control Register, offset: 0x60014 */
11479        uint8_t RESERVED_41[4];
11480   __IO uint32_t RTHR;                              /**< RTIC Throttle Register, offset: 0x6001C */
11481        uint8_t RESERVED_42[8];
11482   __IO uint64_t RWDOG;                             /**< RTIC Watchdog Timer, offset: 0x60028 */
11483        uint8_t RESERVED_43[4];
11484   __IO uint32_t REND;                              /**< RTIC Endian Register, offset: 0x60034 */
11485        uint8_t RESERVED_44[200];
11486   struct {                                         /* offset: 0x60100, array step: index*0x20, index2*0x10 */
11487     __IO uint64_t RMA;                               /**< RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10 */
11488          uint8_t RESERVED_0[4];
11489     __IO uint32_t RML;                               /**< RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10 */
11490   } RM[4][2];
11491        uint8_t RESERVED_45[128];
11492   __IO uint32_t RMD[4][2][32];                     /**< RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4 */
11493        uint8_t RESERVED_46[2048];
11494   __I  uint32_t REIR0RTIC;                         /**< Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00 */
11495        uint8_t RESERVED_47[4];
11496   __I  uint64_t REIR2RTIC;                         /**< Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08 */
11497   __I  uint32_t REIR4RTIC;                         /**< Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10 */
11498   __I  uint32_t REIR5RTIC;                         /**< Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14 */
11499        uint8_t RESERVED_48[392];
11500   __I  uint32_t CRNR_MS_RTIC;                      /**< CHA Revision Number Register, most-significant half, offset: 0x60FA0 */
11501   __I  uint32_t CRNR_LS_RTIC;                      /**< CHA Revision Number Register, least-significant half, offset: 0x60FA4 */
11502   __I  uint32_t CTPR_MS_RTIC;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x60FA8 */
11503   __I  uint32_t CTPR_LS_RTIC;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x60FAC */
11504        uint8_t RESERVED_49[4];
11505   __I  uint32_t SMSTA_RTIC;                        /**< Secure Memory Status Register, offset: 0x60FB4 */
11506        uint8_t RESERVED_50[8];
11507   __I  uint64_t FAR_RTIC;                          /**< Fault Address Register, offset: 0x60FC0 */
11508   __I  uint32_t FADID_RTIC;                        /**< Fault Address DID Register, offset: 0x60FC8 */
11509   __I  uint32_t FADR_RTIC;                         /**< Fault Address Detail Register, offset: 0x60FCC */
11510        uint8_t RESERVED_51[4];
11511   __I  uint32_t CSTA_RTIC;                         /**< CAAM Status Register, offset: 0x60FD4 */
11512   __I  uint32_t SMVID_MS_RTIC;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x60FD8 */
11513   __I  uint32_t SMVID_LS_RTIC;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x60FDC */
11514   __I  uint32_t RVID_RTIC;                         /**< RTIC Version ID Register, offset: 0x60FE0 */
11515   __I  uint32_t CCBVID_RTIC;                       /**< CHA Cluster Block Version ID Register, offset: 0x60FE4 */
11516   __I  uint32_t CHAVID_MS_RTIC;                    /**< CHA Version ID Register, most-significant half, offset: 0x60FE8 */
11517   __I  uint32_t CHAVID_LS_RTIC;                    /**< CHA Version ID Register, least-significant half, offset: 0x60FEC */
11518   __I  uint32_t CHANUM_MS_RTIC;                    /**< CHA Number Register, most-significant half, offset: 0x60FF0 */
11519   __I  uint32_t CHANUM_LS_RTIC;                    /**< CHA Number Register, least-significant half, offset: 0x60FF4 */
11520   __I  uint32_t CAAMVID_MS_RTIC;                   /**< CAAM Version ID Register, most-significant half, offset: 0x60FF8 */
11521   __I  uint32_t CAAMVID_LS_RTIC;                   /**< CAAM Version ID Register, least-significant half, offset: 0x60FFC */
11522        uint8_t RESERVED_52[126976];
11523   struct {                                         /* offset: 0x80000, array step: 0xE3C */
11524          uint8_t RESERVED_0[4];
11525     union {                                          /* offset: 0x80004, array step: 0xE3C */
11526       __IO uint32_t CC1MR;                             /**< CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11527       __IO uint32_t CC1MR_PK;                          /**< CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11528       __IO uint32_t CC1MR_RNG;                         /**< CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C */
11529     };
11530          uint8_t RESERVED_1[4];
11531     __IO uint32_t CC1KSR;                            /**< CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C */
11532     __IO uint64_t CC1DSR;                            /**< CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C */
11533          uint8_t RESERVED_2[4];
11534     __IO uint32_t CC1ICVSR;                          /**< CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C */
11535          uint8_t RESERVED_3[20];
11536     __O  uint32_t CCCTRL;                            /**< CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C */
11537          uint8_t RESERVED_4[4];
11538     __IO uint32_t CICTL;                             /**< CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C */
11539          uint8_t RESERVED_5[4];
11540     __O  uint32_t CCWR;                              /**< CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C */
11541     __I  uint32_t CCSTA_MS;                          /**< CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C */
11542     __I  uint32_t CCSTA_LS;                          /**< CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C */
11543          uint8_t RESERVED_6[12];
11544     __IO uint32_t CC1AADSZR;                         /**< CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C */
11545          uint8_t RESERVED_7[4];
11546     __IO uint32_t CC1IVSZR;                          /**< CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C */
11547          uint8_t RESERVED_8[28];
11548     __IO uint32_t CPKASZR;                           /**< PKHA A Size Register, array offset: 0x80084, array step: 0xE3C */
11549          uint8_t RESERVED_9[4];
11550     __IO uint32_t CPKBSZR;                           /**< PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C */
11551          uint8_t RESERVED_10[4];
11552     __IO uint32_t CPKNSZR;                           /**< PKHA N Size Register, array offset: 0x80094, array step: 0xE3C */
11553          uint8_t RESERVED_11[4];
11554     __IO uint32_t CPKESZR;                           /**< PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C */
11555          uint8_t RESERVED_12[96];
11556     __IO uint32_t CC1CTXR[16];                       /**< CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4 */
11557          uint8_t RESERVED_13[192];
11558     __IO uint32_t CC1KR[8];                          /**< CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4 */
11559          uint8_t RESERVED_14[484];
11560     __IO uint32_t CC2MR;                             /**< CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C */
11561          uint8_t RESERVED_15[4];
11562     __IO uint32_t CC2KSR;                            /**< CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C */
11563     __IO uint64_t CC2DSR;                            /**< CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C */
11564          uint8_t RESERVED_16[4];
11565     __IO uint32_t CC2ICVSZR;                         /**< CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C */
11566          uint8_t RESERVED_17[224];
11567     __IO uint32_t CC2CTXR[18];                       /**< CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4 */
11568          uint8_t RESERVED_18[184];
11569     __IO uint32_t CC2KEYR[32];                       /**< CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4 */
11570          uint8_t RESERVED_19[320];
11571     __I  uint32_t CFIFOSTA;                          /**< CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C */
11572          uint8_t RESERVED_20[12];
11573     union {                                          /* offset: 0x807D0, array step: 0xE3C */
11574       __O  uint32_t CNFIFO;                            /**< CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C */
11575       __O  uint32_t CNFIFO_2;                          /**< CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C */
11576     };
11577          uint8_t RESERVED_21[12];
11578     __O  uint32_t CIFIFO;                            /**< CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C */
11579          uint8_t RESERVED_22[12];
11580     __I  uint64_t COFIFO;                            /**< CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C */
11581          uint8_t RESERVED_23[8];
11582     __IO uint32_t DJQCR_MS;                          /**< DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C */
11583     __I  uint32_t DJQCR_LS;                          /**< DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C */
11584     __I  uint64_t DDAR;                              /**< DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C */
11585     __I  uint32_t DOPSTA_MS;                         /**< DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C */
11586     __I  uint32_t DOPSTA_LS;                         /**< DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C */
11587          uint8_t RESERVED_24[8];
11588     __I  uint32_t DPDIDSR;                           /**< DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C */
11589     __I  uint32_t DODIDSR;                           /**< DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C */
11590          uint8_t RESERVED_25[24];
11591     struct {                                         /* offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11592       __IO uint32_t DMTH_MS;                           /**< DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11593       __IO uint32_t DMTH_LS;                           /**< DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8 */
11594     } DDMTHB[4];
11595          uint8_t RESERVED_26[32];
11596     struct {                                         /* offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11597       __IO uint32_t DGTR_0;                            /**< DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11598       __IO uint32_t DGTR_1;                            /**< DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10 */
11599       __IO uint32_t DGTR_2;                            /**< DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10 */
11600       __IO uint32_t DGTR_3;                            /**< DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10 */
11601     } DDGTR[1];
11602          uint8_t RESERVED_27[112];
11603     struct {                                         /* offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11604       __IO uint32_t DSTR_0;                            /**< DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11605       __IO uint32_t DSTR_1;                            /**< DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10 */
11606       __IO uint32_t DSTR_2;                            /**< DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10 */
11607       __IO uint32_t DSTR_3;                            /**< DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10 */
11608     } DDSTR[1];
11609          uint8_t RESERVED_28[240];
11610     __IO uint32_t DDESB[64];                         /**< DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4 */
11611          uint8_t RESERVED_29[768];
11612     __I  uint32_t DDJR;                              /**< DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C */
11613     __I  uint32_t DDDR;                              /**< DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C */
11614     __I  uint64_t DDJP;                              /**< DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C */
11615     __I  uint64_t DSDP;                              /**< DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C */
11616     __I  uint32_t DDDR_MS;                           /**< DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C */
11617     __I  uint32_t DDDR_LS;                           /**< DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C */
11618     __IO uint32_t SOL;                               /**< Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C */
11619     __IO uint32_t VSOL;                              /**< Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C */
11620     __IO uint32_t SIL;                               /**< Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C */
11621     __IO uint32_t VSIL;                              /**< Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C */
11622     __IO uint32_t DPOVRD;                            /**< Protocol Override Register, array offset: 0x80E30, array step: 0xE3C */
11623     __IO uint32_t UVSOL;                             /**< Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C */
11624     __IO uint32_t UVSIL;                             /**< Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C */
11625   } DC[1];
11626        uint8_t RESERVED_53[356];
11627   __I  uint32_t CRNR_MS_DC01;                      /**< CHA Revision Number Register, most-significant half, offset: 0x80FA0 */
11628   __I  uint32_t CRNR_LS_DC01;                      /**< CHA Revision Number Register, least-significant half, offset: 0x80FA4 */
11629   __I  uint32_t CTPR_MS_DC01;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x80FA8 */
11630   __I  uint32_t CTPR_LS_DC01;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x80FAC */
11631        uint8_t RESERVED_54[4];
11632   __I  uint32_t SMSTA_DC01;                        /**< Secure Memory Status Register, offset: 0x80FB4 */
11633        uint8_t RESERVED_55[8];
11634   __I  uint64_t FAR_DC01;                          /**< Fault Address Register, offset: 0x80FC0 */
11635   __I  uint32_t FADID_DC01;                        /**< Fault Address DID Register, offset: 0x80FC8 */
11636   __I  uint32_t FADR_DC01;                         /**< Fault Address Detail Register, offset: 0x80FCC */
11637        uint8_t RESERVED_56[4];
11638   __I  uint32_t CSTA_DC01;                         /**< CAAM Status Register, offset: 0x80FD4 */
11639   __I  uint32_t SMVID_MS_DC01;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x80FD8 */
11640   __I  uint32_t SMVID_LS_DC01;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x80FDC */
11641   __I  uint32_t RVID_DC01;                         /**< RTIC Version ID Register, offset: 0x80FE0 */
11642   __I  uint32_t CCBVID_DC01;                       /**< CHA Cluster Block Version ID Register, offset: 0x80FE4 */
11643   __I  uint32_t CHAVID_MS_DC01;                    /**< CHA Version ID Register, most-significant half, offset: 0x80FE8 */
11644   __I  uint32_t CHAVID_LS_DC01;                    /**< CHA Version ID Register, least-significant half, offset: 0x80FEC */
11645   __I  uint32_t CHANUM_MS_DC01;                    /**< CHA Number Register, most-significant half, offset: 0x80FF0 */
11646   __I  uint32_t CHANUM_LS_DC01;                    /**< CHA Number Register, least-significant half, offset: 0x80FF4 */
11647   __I  uint32_t CAAMVID_MS_DC01;                   /**< CAAM Version ID Register, most-significant half, offset: 0x80FF8 */
11648   __I  uint32_t CAAMVID_LS_DC01;                   /**< CAAM Version ID Register, least-significant half, offset: 0x80FFC */
11649 } CAAM_Type;
11650 
11651 /* ----------------------------------------------------------------------------
11652    -- CAAM Register Masks
11653    ---------------------------------------------------------------------------- */
11654 
11655 /*!
11656  * @addtogroup CAAM_Register_Masks CAAM Register Masks
11657  * @{
11658  */
11659 
11660 /*! @name MCFGR - Master Configuration Register */
11661 /*! @{ */
11662 
11663 #define CAAM_MCFGR_NORMAL_BURST_MASK             (0x1U)
11664 #define CAAM_MCFGR_NORMAL_BURST_SHIFT            (0U)
11665 /*! NORMAL_BURST
11666  *  0b0..Aligned 32 byte burst size target
11667  *  0b1..Aligned 64 byte burst size target
11668  */
11669 #define CAAM_MCFGR_NORMAL_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK)
11670 
11671 #define CAAM_MCFGR_LARGE_BURST_MASK              (0x4U)
11672 #define CAAM_MCFGR_LARGE_BURST_SHIFT             (2U)
11673 #define CAAM_MCFGR_LARGE_BURST(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK)
11674 
11675 #define CAAM_MCFGR_AXIPIPE_MASK                  (0xF0U)
11676 #define CAAM_MCFGR_AXIPIPE_SHIFT                 (4U)
11677 #define CAAM_MCFGR_AXIPIPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK)
11678 
11679 #define CAAM_MCFGR_AWCACHE_MASK                  (0xF00U)
11680 #define CAAM_MCFGR_AWCACHE_SHIFT                 (8U)
11681 #define CAAM_MCFGR_AWCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK)
11682 
11683 #define CAAM_MCFGR_ARCACHE_MASK                  (0xF000U)
11684 #define CAAM_MCFGR_ARCACHE_SHIFT                 (12U)
11685 #define CAAM_MCFGR_ARCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK)
11686 
11687 #define CAAM_MCFGR_PS_MASK                       (0x10000U)
11688 #define CAAM_MCFGR_PS_SHIFT                      (16U)
11689 /*! PS
11690  *  0b0..Pointers fit in one 32-bit word (pointers are 32-bit addresses).
11691  *  0b1..Pointers require two 32-bit words (pointers are 36-bit addresses).
11692  */
11693 #define CAAM_MCFGR_PS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK)
11694 
11695 #define CAAM_MCFGR_DWT_MASK                      (0x80000U)
11696 #define CAAM_MCFGR_DWT_SHIFT                     (19U)
11697 #define CAAM_MCFGR_DWT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK)
11698 
11699 #define CAAM_MCFGR_WRHD_MASK                     (0x8000000U)
11700 #define CAAM_MCFGR_WRHD_SHIFT                    (27U)
11701 #define CAAM_MCFGR_WRHD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK)
11702 
11703 #define CAAM_MCFGR_DMA_RST_MASK                  (0x10000000U)
11704 #define CAAM_MCFGR_DMA_RST_SHIFT                 (28U)
11705 #define CAAM_MCFGR_DMA_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK)
11706 
11707 #define CAAM_MCFGR_WDF_MASK                      (0x20000000U)
11708 #define CAAM_MCFGR_WDF_SHIFT                     (29U)
11709 #define CAAM_MCFGR_WDF(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK)
11710 
11711 #define CAAM_MCFGR_WDE_MASK                      (0x40000000U)
11712 #define CAAM_MCFGR_WDE_SHIFT                     (30U)
11713 #define CAAM_MCFGR_WDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK)
11714 
11715 #define CAAM_MCFGR_SWRST_MASK                    (0x80000000U)
11716 #define CAAM_MCFGR_SWRST_SHIFT                   (31U)
11717 #define CAAM_MCFGR_SWRST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK)
11718 /*! @} */
11719 
11720 /*! @name PAGE0_SDID - Page 0 SDID Register */
11721 /*! @{ */
11722 
11723 #define CAAM_PAGE0_SDID_SDID_MASK                (0x7FFFU)
11724 #define CAAM_PAGE0_SDID_SDID_SHIFT               (0U)
11725 #define CAAM_PAGE0_SDID_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK)
11726 /*! @} */
11727 
11728 /*! @name SCFGR - Security Configuration Register */
11729 /*! @{ */
11730 
11731 #define CAAM_SCFGR_PRIBLOB_MASK                  (0x3U)
11732 #define CAAM_SCFGR_PRIBLOB_SHIFT                 (0U)
11733 /*! PRIBLOB
11734  *  0b00..Private secure boot software blobs
11735  *  0b01..Private provisioning type 1 blobs
11736  *  0b10..Private provisioning type 2 blobs
11737  *  0b11..Normal operation blobs
11738  */
11739 #define CAAM_SCFGR_PRIBLOB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK)
11740 
11741 #define CAAM_SCFGR_RNGSH0_MASK                   (0x200U)
11742 #define CAAM_SCFGR_RNGSH0_SHIFT                  (9U)
11743 /*! RNGSH0
11744  *  0b0..When RNGSH0 is 0, RNG DRNG State Handle 0 can be instantiated in any mode. RNGSH0 is set to 0 only for testing.
11745  *  0b1..When RNGSH0 is 1, RNG DRNG State Handle 0 cannot be instantiated in deterministic (test) mode. RNGSHO
11746  *       should be set to 1 before the RNG is instantiated. If it is currently instantiated in a deterministic mode,
11747  *       it will be un-instantiated. Once this bit has been written to a 1, it cannot be changed to a 0 until the
11748  *       next power on reset.
11749  */
11750 #define CAAM_SCFGR_RNGSH0(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK)
11751 
11752 #define CAAM_SCFGR_LCK_TRNG_MASK                 (0x800U)
11753 #define CAAM_SCFGR_LCK_TRNG_SHIFT                (11U)
11754 #define CAAM_SCFGR_LCK_TRNG(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK)
11755 
11756 #define CAAM_SCFGR_VIRT_EN_MASK                  (0x8000U)
11757 #define CAAM_SCFGR_VIRT_EN_SHIFT                 (15U)
11758 /*! VIRT_EN
11759  *  0b0..Disable job ring virtualization
11760  *  0b1..Enable job ring virtualization
11761  */
11762 #define CAAM_SCFGR_VIRT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK)
11763 
11764 #define CAAM_SCFGR_MPMRL_MASK                    (0x4000000U)
11765 #define CAAM_SCFGR_MPMRL_SHIFT                   (26U)
11766 #define CAAM_SCFGR_MPMRL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK)
11767 
11768 #define CAAM_SCFGR_MPPKRC_MASK                   (0x8000000U)
11769 #define CAAM_SCFGR_MPPKRC_SHIFT                  (27U)
11770 #define CAAM_SCFGR_MPPKRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK)
11771 
11772 #define CAAM_SCFGR_MPCURVE_MASK                  (0xF0000000U)
11773 #define CAAM_SCFGR_MPCURVE_SHIFT                 (28U)
11774 #define CAAM_SCFGR_MPCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK)
11775 /*! @} */
11776 
11777 /*! @name JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half */
11778 /*! @{ */
11779 
11780 #define CAAM_JRDID_MS_PRIM_DID_MASK              (0xFU)
11781 #define CAAM_JRDID_MS_PRIM_DID_SHIFT             (0U)
11782 #define CAAM_JRDID_MS_PRIM_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK)
11783 
11784 #define CAAM_JRDID_MS_PRIM_TZ_MASK               (0x10U)
11785 #define CAAM_JRDID_MS_PRIM_TZ_SHIFT              (4U)
11786 #define CAAM_JRDID_MS_PRIM_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK)
11787 
11788 #define CAAM_JRDID_MS_SDID_MS_MASK               (0x7FE0U)
11789 #define CAAM_JRDID_MS_SDID_MS_SHIFT              (5U)
11790 #define CAAM_JRDID_MS_SDID_MS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK)
11791 
11792 #define CAAM_JRDID_MS_TZ_OWN_MASK                (0x8000U)
11793 #define CAAM_JRDID_MS_TZ_OWN_SHIFT               (15U)
11794 #define CAAM_JRDID_MS_TZ_OWN(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK)
11795 
11796 #define CAAM_JRDID_MS_AMTD_MASK                  (0x10000U)
11797 #define CAAM_JRDID_MS_AMTD_SHIFT                 (16U)
11798 #define CAAM_JRDID_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK)
11799 
11800 #define CAAM_JRDID_MS_LAMTD_MASK                 (0x20000U)
11801 #define CAAM_JRDID_MS_LAMTD_SHIFT                (17U)
11802 #define CAAM_JRDID_MS_LAMTD(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK)
11803 
11804 #define CAAM_JRDID_MS_PRIM_ICID_MASK             (0x3FF80000U)
11805 #define CAAM_JRDID_MS_PRIM_ICID_SHIFT            (19U)
11806 #define CAAM_JRDID_MS_PRIM_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK)
11807 
11808 #define CAAM_JRDID_MS_USE_OUT_MASK               (0x40000000U)
11809 #define CAAM_JRDID_MS_USE_OUT_SHIFT              (30U)
11810 #define CAAM_JRDID_MS_USE_OUT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK)
11811 
11812 #define CAAM_JRDID_MS_LDID_MASK                  (0x80000000U)
11813 #define CAAM_JRDID_MS_LDID_SHIFT                 (31U)
11814 #define CAAM_JRDID_MS_LDID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK)
11815 /*! @} */
11816 
11817 /* The count of CAAM_JRDID_MS */
11818 #define CAAM_JRDID_MS_COUNT                      (4U)
11819 
11820 /*! @name JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half */
11821 /*! @{ */
11822 
11823 #define CAAM_JRDID_LS_OUT_DID_MASK               (0xFU)
11824 #define CAAM_JRDID_LS_OUT_DID_SHIFT              (0U)
11825 #define CAAM_JRDID_LS_OUT_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK)
11826 
11827 #define CAAM_JRDID_LS_OUT_ICID_MASK              (0x3FF80000U)
11828 #define CAAM_JRDID_LS_OUT_ICID_SHIFT             (19U)
11829 #define CAAM_JRDID_LS_OUT_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK)
11830 /*! @} */
11831 
11832 /* The count of CAAM_JRDID_LS */
11833 #define CAAM_JRDID_LS_COUNT                      (4U)
11834 
11835 /*! @name DEBUGCTL - Debug Control Register */
11836 /*! @{ */
11837 
11838 #define CAAM_DEBUGCTL_STOP_MASK                  (0x10000U)
11839 #define CAAM_DEBUGCTL_STOP_SHIFT                 (16U)
11840 #define CAAM_DEBUGCTL_STOP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK)
11841 
11842 #define CAAM_DEBUGCTL_STOP_ACK_MASK              (0x20000U)
11843 #define CAAM_DEBUGCTL_STOP_ACK_SHIFT             (17U)
11844 #define CAAM_DEBUGCTL_STOP_ACK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK)
11845 /*! @} */
11846 
11847 /*! @name JRSTARTR - Job Ring Start Register */
11848 /*! @{ */
11849 
11850 #define CAAM_JRSTARTR_Start_JR0_MASK             (0x1U)
11851 #define CAAM_JRSTARTR_Start_JR0_SHIFT            (0U)
11852 /*! Start_JR0
11853  *  0b0..Stop Mode. The JR0DID register and the SMVBA register for Job Ring 0 can be written but the IRBAR, IRSR,
11854  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 are NOT accessible. If Job Ring 0 is
11855  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), the JR0DID and SMVBA register can be written only via a
11856  *       bus transaction that has ns=0.
11857  *  0b1..Start Mode. The JR0DID register and the SMVBA register for Job Ring 0 CANNOT be written but the IRBAR,
11858  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 ARE accessible. If Job Ring 0 is
11859  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11860  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0.
11861  */
11862 #define CAAM_JRSTARTR_Start_JR0(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK)
11863 
11864 #define CAAM_JRSTARTR_Start_JR1_MASK             (0x2U)
11865 #define CAAM_JRSTARTR_Start_JR1_SHIFT            (1U)
11866 /*! Start_JR1
11867  *  0b0..Stop Mode. The JR1DID register and the SMVBA register for Job Ring 1 can be written but the IRBAR, IRSR,
11868  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 are NOT accessible. If Job Ring 1 is
11869  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), the JR1DID and SMVBA register can be written only via a
11870  *       bus transaction that has ns=0.
11871  *  0b1..Start Mode. The JR1DID register and the SMVBA register for Job Ring 1 CANNOT be written but the IRBAR,
11872  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 ARE accessible. If Job Ring 1 is
11873  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11874  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0.
11875  */
11876 #define CAAM_JRSTARTR_Start_JR1(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK)
11877 
11878 #define CAAM_JRSTARTR_Start_JR2_MASK             (0x4U)
11879 #define CAAM_JRSTARTR_Start_JR2_SHIFT            (2U)
11880 /*! Start_JR2
11881  *  0b0..Stop Mode. The JR2DID register and the SMVBA register for Job Ring 2 can be written but the IRBAR, IRSR,
11882  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 are NOT accessible. If Job Ring 2 is
11883  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), the JR2DID and SMVBA register can be written only via a
11884  *       bus transaction that has ns=0.
11885  *  0b1..Start Mode. The JR2DID register and the SMVBA register for Job Ring 2 CANNOT be written but the IRBAR,
11886  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 ARE accessible. If Job Ring 2 is
11887  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11888  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0.
11889  */
11890 #define CAAM_JRSTARTR_Start_JR2(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK)
11891 
11892 #define CAAM_JRSTARTR_Start_JR3_MASK             (0x8U)
11893 #define CAAM_JRSTARTR_Start_JR3_SHIFT            (3U)
11894 /*! Start_JR3
11895  *  0b0..Stop Mode. The JR3DID register and the SMVBA register for Job Ring 3 can be written but the IRBAR, IRSR,
11896  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 are NOT accessible. If Job Ring 3 is
11897  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), the JR3DID and SMVBA register can be written only via a
11898  *       bus transaction that has ns=0.
11899  *  0b1..Start Mode. The JR3DID register and the SMVBA register for Job Ring 3 CANNOT be written but the IRBAR,
11900  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 ARE accessible. If Job Ring 3 is
11901  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11902  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 3 can be written only via a bus transaction that has ns=0.
11903  */
11904 #define CAAM_JRSTARTR_Start_JR3(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK)
11905 /*! @} */
11906 
11907 /*! @name RTIC_OWN - RTIC OWN Register */
11908 /*! @{ */
11909 
11910 #define CAAM_RTIC_OWN_ROWN_DID_MASK              (0xFU)
11911 #define CAAM_RTIC_OWN_ROWN_DID_SHIFT             (0U)
11912 /*! ROWN_DID - RTIC Owner's DID
11913  */
11914 #define CAAM_RTIC_OWN_ROWN_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK)
11915 
11916 #define CAAM_RTIC_OWN_ROWN_TZ_MASK               (0x10U)
11917 #define CAAM_RTIC_OWN_ROWN_TZ_SHIFT              (4U)
11918 #define CAAM_RTIC_OWN_ROWN_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK)
11919 
11920 #define CAAM_RTIC_OWN_LCK_MASK                   (0x80000000U)
11921 #define CAAM_RTIC_OWN_LCK_SHIFT                  (31U)
11922 #define CAAM_RTIC_OWN_LCK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK)
11923 /*! @} */
11924 
11925 /*! @name RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D */
11926 /*! @{ */
11927 
11928 #define CAAM_RTIC_DID_RTIC_DID_MASK              (0xFU)
11929 #define CAAM_RTIC_DID_RTIC_DID_SHIFT             (0U)
11930 #define CAAM_RTIC_DID_RTIC_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK)
11931 
11932 #define CAAM_RTIC_DID_RTIC_TZ_MASK               (0x10U)
11933 #define CAAM_RTIC_DID_RTIC_TZ_SHIFT              (4U)
11934 #define CAAM_RTIC_DID_RTIC_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK)
11935 
11936 #define CAAM_RTIC_DID_RTIC_ICID_MASK             (0x3FF80000U)
11937 #define CAAM_RTIC_DID_RTIC_ICID_SHIFT            (19U)
11938 #define CAAM_RTIC_DID_RTIC_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK)
11939 /*! @} */
11940 
11941 /* The count of CAAM_RTIC_DID */
11942 #define CAAM_RTIC_DID_COUNT                      (4U)
11943 
11944 /*! @name DECORSR - DECO Request Source Register */
11945 /*! @{ */
11946 
11947 #define CAAM_DECORSR_JR_MASK                     (0x3U)
11948 #define CAAM_DECORSR_JR_SHIFT                    (0U)
11949 #define CAAM_DECORSR_JR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK)
11950 
11951 #define CAAM_DECORSR_VALID_MASK                  (0x80000000U)
11952 #define CAAM_DECORSR_VALID_SHIFT                 (31U)
11953 #define CAAM_DECORSR_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK)
11954 /*! @} */
11955 
11956 /*! @name DECORR - DECO Request Register */
11957 /*! @{ */
11958 
11959 #define CAAM_DECORR_RQD0_MASK                    (0x1U)
11960 #define CAAM_DECORR_RQD0_SHIFT                   (0U)
11961 #define CAAM_DECORR_RQD0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK)
11962 
11963 #define CAAM_DECORR_DEN0_MASK                    (0x10000U)
11964 #define CAAM_DECORR_DEN0_SHIFT                   (16U)
11965 #define CAAM_DECORR_DEN0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK)
11966 /*! @} */
11967 
11968 /*! @name DECODID_MS - DECO0 DID Register - most significant half */
11969 /*! @{ */
11970 
11971 #define CAAM_DECODID_MS_DPRIM_DID_MASK           (0xFU)
11972 #define CAAM_DECODID_MS_DPRIM_DID_SHIFT          (0U)
11973 /*! DPRIM_DID - DECO Owner
11974  */
11975 #define CAAM_DECODID_MS_DPRIM_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK)
11976 
11977 #define CAAM_DECODID_MS_D_NS_MASK                (0x10U)
11978 #define CAAM_DECODID_MS_D_NS_SHIFT               (4U)
11979 #define CAAM_DECODID_MS_D_NS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK)
11980 
11981 #define CAAM_DECODID_MS_LCK_MASK                 (0x80000000U)
11982 #define CAAM_DECODID_MS_LCK_SHIFT                (31U)
11983 #define CAAM_DECODID_MS_LCK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK)
11984 /*! @} */
11985 
11986 /* The count of CAAM_DECODID_MS */
11987 #define CAAM_DECODID_MS_COUNT                    (1U)
11988 
11989 /*! @name DECODID_LS - DECO0 DID Register - least significant half */
11990 /*! @{ */
11991 
11992 #define CAAM_DECODID_LS_DSEQ_DID_MASK            (0xFU)
11993 #define CAAM_DECODID_LS_DSEQ_DID_SHIFT           (0U)
11994 #define CAAM_DECODID_LS_DSEQ_DID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK)
11995 
11996 #define CAAM_DECODID_LS_DSEQ_NS_MASK             (0x10U)
11997 #define CAAM_DECODID_LS_DSEQ_NS_SHIFT            (4U)
11998 #define CAAM_DECODID_LS_DSEQ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK)
11999 
12000 #define CAAM_DECODID_LS_DNSEQ_DID_MASK           (0xF0000U)
12001 #define CAAM_DECODID_LS_DNSEQ_DID_SHIFT          (16U)
12002 #define CAAM_DECODID_LS_DNSEQ_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK)
12003 
12004 #define CAAM_DECODID_LS_DNONSEQ_NS_MASK          (0x100000U)
12005 #define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT         (20U)
12006 #define CAAM_DECODID_LS_DNONSEQ_NS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK)
12007 /*! @} */
12008 
12009 /* The count of CAAM_DECODID_LS */
12010 #define CAAM_DECODID_LS_COUNT                    (1U)
12011 
12012 /*! @name DAR - DECO Availability Register */
12013 /*! @{ */
12014 
12015 #define CAAM_DAR_NYA0_MASK                       (0x1U)
12016 #define CAAM_DAR_NYA0_SHIFT                      (0U)
12017 #define CAAM_DAR_NYA0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK)
12018 /*! @} */
12019 
12020 /*! @name DRR - DECO Reset Register */
12021 /*! @{ */
12022 
12023 #define CAAM_DRR_RST0_MASK                       (0x1U)
12024 #define CAAM_DRR_RST0_SHIFT                      (0U)
12025 #define CAAM_DRR_RST0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK)
12026 /*! @} */
12027 
12028 /*! @name JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register */
12029 /*! @{ */
12030 
12031 #define CAAM_JRSMVBAR_SMVBA_MASK                 (0xFFFFFFFFU)
12032 #define CAAM_JRSMVBAR_SMVBA_SHIFT                (0U)
12033 #define CAAM_JRSMVBAR_SMVBA(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK)
12034 /*! @} */
12035 
12036 /* The count of CAAM_JRSMVBAR */
12037 #define CAAM_JRSMVBAR_COUNT                      (4U)
12038 
12039 /*! @name PBSL - Peak Bandwidth Smoothing Limit Register */
12040 /*! @{ */
12041 
12042 #define CAAM_PBSL_PBSL_MASK                      (0x7FU)
12043 #define CAAM_PBSL_PBSL_SHIFT                     (0U)
12044 #define CAAM_PBSL_PBSL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK)
12045 /*! @} */
12046 
12047 /*! @name DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS */
12048 /*! @{ */
12049 
12050 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK       (0xFFU)
12051 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT      (0U)
12052 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK)
12053 
12054 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK       (0xFF00U)
12055 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT      (8U)
12056 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK)
12057 
12058 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK       (0xFF0000U)
12059 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT      (16U)
12060 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK)
12061 
12062 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK       (0xFF000000U)
12063 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT      (24U)
12064 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK)
12065 /*! @} */
12066 
12067 /* The count of CAAM_DMA_AIDL_MAP_MS */
12068 #define CAAM_DMA_AIDL_MAP_MS_COUNT               (1U)
12069 
12070 /*! @name DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS */
12071 /*! @{ */
12072 
12073 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK       (0xFFU)
12074 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT      (0U)
12075 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK)
12076 
12077 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK       (0xFF00U)
12078 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT      (8U)
12079 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK)
12080 
12081 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK       (0xFF0000U)
12082 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT      (16U)
12083 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK)
12084 
12085 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK       (0xFF000000U)
12086 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT      (24U)
12087 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK)
12088 /*! @} */
12089 
12090 /* The count of CAAM_DMA_AIDL_MAP_LS */
12091 #define CAAM_DMA_AIDL_MAP_LS_COUNT               (1U)
12092 
12093 /*! @name DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS */
12094 /*! @{ */
12095 
12096 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK      (0xFFU)
12097 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT     (0U)
12098 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK)
12099 
12100 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK      (0xFF00U)
12101 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT     (8U)
12102 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK)
12103 
12104 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK      (0xFF0000U)
12105 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT     (16U)
12106 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK)
12107 
12108 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK      (0xFF000000U)
12109 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT     (24U)
12110 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK)
12111 /*! @} */
12112 
12113 /* The count of CAAM_DMA_AIDM_MAP_MS */
12114 #define CAAM_DMA_AIDM_MAP_MS_COUNT               (1U)
12115 
12116 /*! @name DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS */
12117 /*! @{ */
12118 
12119 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK       (0xFFU)
12120 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT      (0U)
12121 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK)
12122 
12123 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK       (0xFF00U)
12124 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT      (8U)
12125 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK)
12126 
12127 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK      (0xFF0000U)
12128 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT     (16U)
12129 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK)
12130 
12131 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK      (0xFF000000U)
12132 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT     (24U)
12133 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK)
12134 /*! @} */
12135 
12136 /* The count of CAAM_DMA_AIDM_MAP_LS */
12137 #define CAAM_DMA_AIDM_MAP_LS_COUNT               (1U)
12138 
12139 /*! @name DMA0_AID_ENB - DMA0 AXI ID Enable Register */
12140 /*! @{ */
12141 
12142 #define CAAM_DMA0_AID_ENB_AID0E_MASK             (0x1U)
12143 #define CAAM_DMA0_AID_ENB_AID0E_SHIFT            (0U)
12144 #define CAAM_DMA0_AID_ENB_AID0E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK)
12145 
12146 #define CAAM_DMA0_AID_ENB_AID1E_MASK             (0x2U)
12147 #define CAAM_DMA0_AID_ENB_AID1E_SHIFT            (1U)
12148 #define CAAM_DMA0_AID_ENB_AID1E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK)
12149 
12150 #define CAAM_DMA0_AID_ENB_AID2E_MASK             (0x4U)
12151 #define CAAM_DMA0_AID_ENB_AID2E_SHIFT            (2U)
12152 #define CAAM_DMA0_AID_ENB_AID2E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK)
12153 
12154 #define CAAM_DMA0_AID_ENB_AID3E_MASK             (0x8U)
12155 #define CAAM_DMA0_AID_ENB_AID3E_SHIFT            (3U)
12156 #define CAAM_DMA0_AID_ENB_AID3E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK)
12157 
12158 #define CAAM_DMA0_AID_ENB_AID4E_MASK             (0x10U)
12159 #define CAAM_DMA0_AID_ENB_AID4E_SHIFT            (4U)
12160 #define CAAM_DMA0_AID_ENB_AID4E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK)
12161 
12162 #define CAAM_DMA0_AID_ENB_AID5E_MASK             (0x20U)
12163 #define CAAM_DMA0_AID_ENB_AID5E_SHIFT            (5U)
12164 #define CAAM_DMA0_AID_ENB_AID5E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK)
12165 
12166 #define CAAM_DMA0_AID_ENB_AID6E_MASK             (0x40U)
12167 #define CAAM_DMA0_AID_ENB_AID6E_SHIFT            (6U)
12168 #define CAAM_DMA0_AID_ENB_AID6E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK)
12169 
12170 #define CAAM_DMA0_AID_ENB_AID7E_MASK             (0x80U)
12171 #define CAAM_DMA0_AID_ENB_AID7E_SHIFT            (7U)
12172 #define CAAM_DMA0_AID_ENB_AID7E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK)
12173 
12174 #define CAAM_DMA0_AID_ENB_AID8E_MASK             (0x100U)
12175 #define CAAM_DMA0_AID_ENB_AID8E_SHIFT            (8U)
12176 #define CAAM_DMA0_AID_ENB_AID8E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK)
12177 
12178 #define CAAM_DMA0_AID_ENB_AID9E_MASK             (0x200U)
12179 #define CAAM_DMA0_AID_ENB_AID9E_SHIFT            (9U)
12180 #define CAAM_DMA0_AID_ENB_AID9E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK)
12181 
12182 #define CAAM_DMA0_AID_ENB_AID10E_MASK            (0x400U)
12183 #define CAAM_DMA0_AID_ENB_AID10E_SHIFT           (10U)
12184 #define CAAM_DMA0_AID_ENB_AID10E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK)
12185 
12186 #define CAAM_DMA0_AID_ENB_AID11E_MASK            (0x800U)
12187 #define CAAM_DMA0_AID_ENB_AID11E_SHIFT           (11U)
12188 #define CAAM_DMA0_AID_ENB_AID11E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK)
12189 
12190 #define CAAM_DMA0_AID_ENB_AID12E_MASK            (0x1000U)
12191 #define CAAM_DMA0_AID_ENB_AID12E_SHIFT           (12U)
12192 #define CAAM_DMA0_AID_ENB_AID12E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK)
12193 
12194 #define CAAM_DMA0_AID_ENB_AID13E_MASK            (0x2000U)
12195 #define CAAM_DMA0_AID_ENB_AID13E_SHIFT           (13U)
12196 #define CAAM_DMA0_AID_ENB_AID13E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK)
12197 
12198 #define CAAM_DMA0_AID_ENB_AID14E_MASK            (0x4000U)
12199 #define CAAM_DMA0_AID_ENB_AID14E_SHIFT           (14U)
12200 #define CAAM_DMA0_AID_ENB_AID14E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK)
12201 
12202 #define CAAM_DMA0_AID_ENB_AID15E_MASK            (0x8000U)
12203 #define CAAM_DMA0_AID_ENB_AID15E_SHIFT           (15U)
12204 #define CAAM_DMA0_AID_ENB_AID15E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK)
12205 /*! @} */
12206 
12207 /*! @name DMA0_ARD_TC - DMA0 AXI Read Timing Check Register */
12208 /*! @{ */
12209 
12210 #define CAAM_DMA0_ARD_TC_ARSC_MASK               (0xFFFFFU)
12211 #define CAAM_DMA0_ARD_TC_ARSC_SHIFT              (0U)
12212 #define CAAM_DMA0_ARD_TC_ARSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK)
12213 
12214 #define CAAM_DMA0_ARD_TC_ARLC_MASK               (0xFFFFF000000U)
12215 #define CAAM_DMA0_ARD_TC_ARLC_SHIFT              (24U)
12216 #define CAAM_DMA0_ARD_TC_ARLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK)
12217 
12218 #define CAAM_DMA0_ARD_TC_ARL_MASK                (0xFFF000000000000U)
12219 #define CAAM_DMA0_ARD_TC_ARL_SHIFT               (48U)
12220 #define CAAM_DMA0_ARD_TC_ARL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK)
12221 
12222 #define CAAM_DMA0_ARD_TC_ARTL_MASK               (0x1000000000000000U)
12223 #define CAAM_DMA0_ARD_TC_ARTL_SHIFT              (60U)
12224 #define CAAM_DMA0_ARD_TC_ARTL(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK)
12225 
12226 #define CAAM_DMA0_ARD_TC_ARTT_MASK               (0x2000000000000000U)
12227 #define CAAM_DMA0_ARD_TC_ARTT_SHIFT              (61U)
12228 #define CAAM_DMA0_ARD_TC_ARTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK)
12229 
12230 #define CAAM_DMA0_ARD_TC_ARCT_MASK               (0x4000000000000000U)
12231 #define CAAM_DMA0_ARD_TC_ARCT_SHIFT              (62U)
12232 #define CAAM_DMA0_ARD_TC_ARCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK)
12233 
12234 #define CAAM_DMA0_ARD_TC_ARTCE_MASK              (0x8000000000000000U)
12235 #define CAAM_DMA0_ARD_TC_ARTCE_SHIFT             (63U)
12236 #define CAAM_DMA0_ARD_TC_ARTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK)
12237 /*! @} */
12238 
12239 /*! @name DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register */
12240 /*! @{ */
12241 
12242 #define CAAM_DMA0_ARD_LAT_SARL_MASK              (0xFFFFFFFFU)
12243 #define CAAM_DMA0_ARD_LAT_SARL_SHIFT             (0U)
12244 #define CAAM_DMA0_ARD_LAT_SARL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK)
12245 /*! @} */
12246 
12247 /*! @name DMA0_AWR_TC - DMA0 AXI Write Timing Check Register */
12248 /*! @{ */
12249 
12250 #define CAAM_DMA0_AWR_TC_AWSC_MASK               (0xFFFFFU)
12251 #define CAAM_DMA0_AWR_TC_AWSC_SHIFT              (0U)
12252 #define CAAM_DMA0_AWR_TC_AWSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK)
12253 
12254 #define CAAM_DMA0_AWR_TC_AWLC_MASK               (0xFFFFF000000U)
12255 #define CAAM_DMA0_AWR_TC_AWLC_SHIFT              (24U)
12256 #define CAAM_DMA0_AWR_TC_AWLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK)
12257 
12258 #define CAAM_DMA0_AWR_TC_AWL_MASK                (0xFFF000000000000U)
12259 #define CAAM_DMA0_AWR_TC_AWL_SHIFT               (48U)
12260 #define CAAM_DMA0_AWR_TC_AWL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK)
12261 
12262 #define CAAM_DMA0_AWR_TC_AWTT_MASK               (0x2000000000000000U)
12263 #define CAAM_DMA0_AWR_TC_AWTT_SHIFT              (61U)
12264 #define CAAM_DMA0_AWR_TC_AWTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK)
12265 
12266 #define CAAM_DMA0_AWR_TC_AWCT_MASK               (0x4000000000000000U)
12267 #define CAAM_DMA0_AWR_TC_AWCT_SHIFT              (62U)
12268 #define CAAM_DMA0_AWR_TC_AWCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK)
12269 
12270 #define CAAM_DMA0_AWR_TC_AWTCE_MASK              (0x8000000000000000U)
12271 #define CAAM_DMA0_AWR_TC_AWTCE_SHIFT             (63U)
12272 #define CAAM_DMA0_AWR_TC_AWTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK)
12273 /*! @} */
12274 
12275 /*! @name DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register */
12276 /*! @{ */
12277 
12278 #define CAAM_DMA0_AWR_LAT_SAWL_MASK              (0xFFFFFFFFU)
12279 #define CAAM_DMA0_AWR_LAT_SAWL_SHIFT             (0U)
12280 #define CAAM_DMA0_AWR_LAT_SAWL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK)
12281 /*! @} */
12282 
12283 /*! @name MPPKR - Manufacturing Protection Private Key Register */
12284 /*! @{ */
12285 
12286 #define CAAM_MPPKR_MPPrivK_MASK                  (0xFFU)
12287 #define CAAM_MPPKR_MPPrivK_SHIFT                 (0U)
12288 #define CAAM_MPPKR_MPPrivK(x)                    (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK)
12289 /*! @} */
12290 
12291 /* The count of CAAM_MPPKR */
12292 #define CAAM_MPPKR_COUNT                         (64U)
12293 
12294 /*! @name MPMR - Manufacturing Protection Message Register */
12295 /*! @{ */
12296 
12297 #define CAAM_MPMR_MPMSG_MASK                     (0xFFU)
12298 #define CAAM_MPMR_MPMSG_SHIFT                    (0U)
12299 #define CAAM_MPMR_MPMSG(x)                       (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK)
12300 /*! @} */
12301 
12302 /* The count of CAAM_MPMR */
12303 #define CAAM_MPMR_COUNT                          (32U)
12304 
12305 /*! @name MPTESTR - Manufacturing Protection Test Register */
12306 /*! @{ */
12307 
12308 #define CAAM_MPTESTR_TEST_VALUE_MASK             (0xFFU)
12309 #define CAAM_MPTESTR_TEST_VALUE_SHIFT            (0U)
12310 #define CAAM_MPTESTR_TEST_VALUE(x)               (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK)
12311 /*! @} */
12312 
12313 /* The count of CAAM_MPTESTR */
12314 #define CAAM_MPTESTR_COUNT                       (32U)
12315 
12316 /*! @name MPECC - Manufacturing Protection ECC Register */
12317 /*! @{ */
12318 
12319 #define CAAM_MPECC_MP_SYNDROME_MASK              (0x1FF0000U)
12320 #define CAAM_MPECC_MP_SYNDROME_SHIFT             (16U)
12321 /*! MP_SYNDROME
12322  *  0b000000000..The MP Key in the SFP passes the ECC check.
12323  *  0b000000001-0b111111111..The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome.
12324  */
12325 #define CAAM_MPECC_MP_SYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK)
12326 
12327 #define CAAM_MPECC_MP_ZERO_MASK                  (0x8000000U)
12328 #define CAAM_MPECC_MP_ZERO_SHIFT                 (27U)
12329 /*! MP_ZERO
12330  *  0b0..The MP Key in the SFP has a non-zero value.
12331  *  0b1..The MP Key in the SFP is all zeros (unprogrammed).
12332  */
12333 #define CAAM_MPECC_MP_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK)
12334 /*! @} */
12335 
12336 /*! @name JDKEKR - Job Descriptor Key Encryption Key Register */
12337 /*! @{ */
12338 
12339 #define CAAM_JDKEKR_JDKEK_MASK                   (0xFFFFFFFFU)
12340 #define CAAM_JDKEKR_JDKEK_SHIFT                  (0U)
12341 #define CAAM_JDKEKR_JDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK)
12342 /*! @} */
12343 
12344 /* The count of CAAM_JDKEKR */
12345 #define CAAM_JDKEKR_COUNT                        (8U)
12346 
12347 /*! @name TDKEKR - Trusted Descriptor Key Encryption Key Register */
12348 /*! @{ */
12349 
12350 #define CAAM_TDKEKR_TDKEK_MASK                   (0xFFFFFFFFU)
12351 #define CAAM_TDKEKR_TDKEK_SHIFT                  (0U)
12352 #define CAAM_TDKEKR_TDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK)
12353 /*! @} */
12354 
12355 /* The count of CAAM_TDKEKR */
12356 #define CAAM_TDKEKR_COUNT                        (8U)
12357 
12358 /*! @name TDSKR - Trusted Descriptor Signing Key Register */
12359 /*! @{ */
12360 
12361 #define CAAM_TDSKR_TDSK_MASK                     (0xFFFFFFFFU)
12362 #define CAAM_TDSKR_TDSK_SHIFT                    (0U)
12363 #define CAAM_TDSKR_TDSK(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK)
12364 /*! @} */
12365 
12366 /* The count of CAAM_TDSKR */
12367 #define CAAM_TDSKR_COUNT                         (8U)
12368 
12369 /*! @name SKNR - Secure Key Nonce Register */
12370 /*! @{ */
12371 
12372 #define CAAM_SKNR_SK_NONCE_LS_MASK               (0xFFFFFFFFU)
12373 #define CAAM_SKNR_SK_NONCE_LS_SHIFT              (0U)
12374 #define CAAM_SKNR_SK_NONCE_LS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK)
12375 
12376 #define CAAM_SKNR_SK_NONCE_MS_MASK               (0x7FFF00000000U)
12377 #define CAAM_SKNR_SK_NONCE_MS_SHIFT              (32U)
12378 #define CAAM_SKNR_SK_NONCE_MS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK)
12379 /*! @} */
12380 
12381 /*! @name DMA_STA - DMA Status Register */
12382 /*! @{ */
12383 
12384 #define CAAM_DMA_STA_DMA0_ETIF_MASK              (0x1FU)
12385 #define CAAM_DMA_STA_DMA0_ETIF_SHIFT             (0U)
12386 #define CAAM_DMA_STA_DMA0_ETIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK)
12387 
12388 #define CAAM_DMA_STA_DMA0_ITIF_MASK              (0x20U)
12389 #define CAAM_DMA_STA_DMA0_ITIF_SHIFT             (5U)
12390 #define CAAM_DMA_STA_DMA0_ITIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK)
12391 
12392 #define CAAM_DMA_STA_DMA0_IDLE_MASK              (0x80U)
12393 #define CAAM_DMA_STA_DMA0_IDLE_SHIFT             (7U)
12394 #define CAAM_DMA_STA_DMA0_IDLE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK)
12395 /*! @} */
12396 
12397 /*! @name DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP */
12398 /*! @{ */
12399 
12400 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK     (0xFFU)
12401 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT    (0U)
12402 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK)
12403 
12404 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK     (0xFF00U)
12405 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT    (8U)
12406 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK)
12407 
12408 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK     (0xFF0000U)
12409 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT    (16U)
12410 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK)
12411 
12412 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK     (0xFF000000U)
12413 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT    (24U)
12414 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK)
12415 /*! @} */
12416 
12417 /*! @name DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP */
12418 /*! @{ */
12419 
12420 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK     (0xFFU)
12421 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT    (0U)
12422 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK)
12423 
12424 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK     (0xFF00U)
12425 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT    (8U)
12426 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK)
12427 
12428 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK     (0xFF0000U)
12429 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT    (16U)
12430 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK)
12431 
12432 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK     (0xFF000000U)
12433 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT    (24U)
12434 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK)
12435 /*! @} */
12436 
12437 /*! @name DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP */
12438 /*! @{ */
12439 
12440 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK  (0xFFU)
12441 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U)
12442 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK)
12443 
12444 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK  (0xFF00U)
12445 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U)
12446 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK)
12447 
12448 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK  (0xFF0000U)
12449 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U)
12450 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK)
12451 
12452 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK  (0xFF000000U)
12453 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U)
12454 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK)
12455 /*! @} */
12456 
12457 /*! @name DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP */
12458 /*! @{ */
12459 
12460 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK    (0xFFU)
12461 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT   (0U)
12462 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK)
12463 
12464 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK    (0xFF00U)
12465 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT   (8U)
12466 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK)
12467 
12468 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK   (0xFF0000U)
12469 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT  (16U)
12470 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK)
12471 
12472 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK   (0xFF000000U)
12473 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT  (24U)
12474 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK)
12475 /*! @} */
12476 
12477 /*! @name DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register */
12478 /*! @{ */
12479 
12480 #define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK        (0x1U)
12481 #define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT       (0U)
12482 #define CAAM_DMA_X_AID_15_0_EN_AID0E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK)
12483 
12484 #define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK        (0x2U)
12485 #define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT       (1U)
12486 #define CAAM_DMA_X_AID_15_0_EN_AID1E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK)
12487 
12488 #define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK        (0x4U)
12489 #define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT       (2U)
12490 #define CAAM_DMA_X_AID_15_0_EN_AID2E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK)
12491 
12492 #define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK        (0x8U)
12493 #define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT       (3U)
12494 #define CAAM_DMA_X_AID_15_0_EN_AID3E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK)
12495 
12496 #define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK        (0x10U)
12497 #define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT       (4U)
12498 #define CAAM_DMA_X_AID_15_0_EN_AID4E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK)
12499 
12500 #define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK        (0x20U)
12501 #define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT       (5U)
12502 #define CAAM_DMA_X_AID_15_0_EN_AID5E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK)
12503 
12504 #define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK        (0x40U)
12505 #define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT       (6U)
12506 #define CAAM_DMA_X_AID_15_0_EN_AID6E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK)
12507 
12508 #define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK        (0x80U)
12509 #define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT       (7U)
12510 #define CAAM_DMA_X_AID_15_0_EN_AID7E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK)
12511 
12512 #define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK        (0x100U)
12513 #define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT       (8U)
12514 #define CAAM_DMA_X_AID_15_0_EN_AID8E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK)
12515 
12516 #define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK        (0x200U)
12517 #define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT       (9U)
12518 #define CAAM_DMA_X_AID_15_0_EN_AID9E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK)
12519 
12520 #define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK       (0x400U)
12521 #define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT      (10U)
12522 #define CAAM_DMA_X_AID_15_0_EN_AID10E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK)
12523 
12524 #define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK       (0x800U)
12525 #define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT      (11U)
12526 #define CAAM_DMA_X_AID_15_0_EN_AID11E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK)
12527 
12528 #define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK       (0x1000U)
12529 #define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT      (12U)
12530 #define CAAM_DMA_X_AID_15_0_EN_AID12E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK)
12531 
12532 #define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK       (0x2000U)
12533 #define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT      (13U)
12534 #define CAAM_DMA_X_AID_15_0_EN_AID13E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK)
12535 
12536 #define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK       (0x4000U)
12537 #define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT      (14U)
12538 #define CAAM_DMA_X_AID_15_0_EN_AID14E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK)
12539 
12540 #define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK       (0x8000U)
12541 #define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT      (15U)
12542 #define CAAM_DMA_X_AID_15_0_EN_AID15E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK)
12543 /*! @} */
12544 
12545 /*! @name DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register */
12546 /*! @{ */
12547 
12548 #define CAAM_DMA_X_ARTC_CTL_ART_MASK             (0xFFFU)
12549 #define CAAM_DMA_X_ARTC_CTL_ART_SHIFT            (0U)
12550 #define CAAM_DMA_X_ARTC_CTL_ART(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK)
12551 
12552 #define CAAM_DMA_X_ARTC_CTL_ARL_MASK             (0xFFF0000U)
12553 #define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT            (16U)
12554 #define CAAM_DMA_X_ARTC_CTL_ARL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK)
12555 
12556 #define CAAM_DMA_X_ARTC_CTL_ARTL_MASK            (0x10000000U)
12557 #define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT           (28U)
12558 #define CAAM_DMA_X_ARTC_CTL_ARTL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK)
12559 
12560 #define CAAM_DMA_X_ARTC_CTL_ARTT_MASK            (0x20000000U)
12561 #define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT           (29U)
12562 #define CAAM_DMA_X_ARTC_CTL_ARTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK)
12563 
12564 #define CAAM_DMA_X_ARTC_CTL_ARCT_MASK            (0x40000000U)
12565 #define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT           (30U)
12566 #define CAAM_DMA_X_ARTC_CTL_ARCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK)
12567 
12568 #define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK           (0x80000000U)
12569 #define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT          (31U)
12570 #define CAAM_DMA_X_ARTC_CTL_ARTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK)
12571 /*! @} */
12572 
12573 /*! @name DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register */
12574 /*! @{ */
12575 
12576 #define CAAM_DMA_X_ARTC_LC_ARLC_MASK             (0xFFFFFU)
12577 #define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT            (0U)
12578 #define CAAM_DMA_X_ARTC_LC_ARLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK)
12579 /*! @} */
12580 
12581 /*! @name DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register */
12582 /*! @{ */
12583 
12584 #define CAAM_DMA_X_ARTC_SC_ARSC_MASK             (0xFFFFFU)
12585 #define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT            (0U)
12586 #define CAAM_DMA_X_ARTC_SC_ARSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK)
12587 /*! @} */
12588 
12589 /*! @name DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register */
12590 /*! @{ */
12591 
12592 #define CAAM_DMA_X_ARTC_LAT_SARL_MASK            (0xFFFFFFFFU)
12593 #define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT           (0U)
12594 #define CAAM_DMA_X_ARTC_LAT_SARL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK)
12595 /*! @} */
12596 
12597 /*! @name DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register */
12598 /*! @{ */
12599 
12600 #define CAAM_DMA_X_AWTC_CTL_AWT_MASK             (0xFFFU)
12601 #define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT            (0U)
12602 #define CAAM_DMA_X_AWTC_CTL_AWT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK)
12603 
12604 #define CAAM_DMA_X_AWTC_CTL_AWL_MASK             (0xFFF0000U)
12605 #define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT            (16U)
12606 #define CAAM_DMA_X_AWTC_CTL_AWL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK)
12607 
12608 #define CAAM_DMA_X_AWTC_CTL_AWTT_MASK            (0x20000000U)
12609 #define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT           (29U)
12610 #define CAAM_DMA_X_AWTC_CTL_AWTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK)
12611 
12612 #define CAAM_DMA_X_AWTC_CTL_AWCT_MASK            (0x40000000U)
12613 #define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT           (30U)
12614 #define CAAM_DMA_X_AWTC_CTL_AWCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK)
12615 
12616 #define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK           (0x80000000U)
12617 #define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT          (31U)
12618 #define CAAM_DMA_X_AWTC_CTL_AWTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK)
12619 /*! @} */
12620 
12621 /*! @name DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register */
12622 /*! @{ */
12623 
12624 #define CAAM_DMA_X_AWTC_LC_AWLC_MASK             (0xFFFFFU)
12625 #define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT            (0U)
12626 #define CAAM_DMA_X_AWTC_LC_AWLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK)
12627 /*! @} */
12628 
12629 /*! @name DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register */
12630 /*! @{ */
12631 
12632 #define CAAM_DMA_X_AWTC_SC_AWSC_MASK             (0xFFFFFU)
12633 #define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT            (0U)
12634 #define CAAM_DMA_X_AWTC_SC_AWSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK)
12635 /*! @} */
12636 
12637 /*! @name DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register */
12638 /*! @{ */
12639 
12640 #define CAAM_DMA_X_AWTC_LAT_SAWL_MASK            (0xFFFFFFFFU)
12641 #define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT           (0U)
12642 #define CAAM_DMA_X_AWTC_LAT_SAWL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK)
12643 /*! @} */
12644 
12645 /*! @name RTMCTL - RNG TRNG Miscellaneous Control Register */
12646 /*! @{ */
12647 
12648 #define CAAM_RTMCTL_SAMP_MODE_MASK               (0x3U)
12649 #define CAAM_RTMCTL_SAMP_MODE_SHIFT              (0U)
12650 /*! SAMP_MODE
12651  *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
12652  *  0b01..use raw data into both Entropy shifter and Statistical Checker
12653  *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
12654  *  0b11..undefined/reserved.
12655  */
12656 #define CAAM_RTMCTL_SAMP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK)
12657 
12658 #define CAAM_RTMCTL_OSC_DIV_MASK                 (0xCU)
12659 #define CAAM_RTMCTL_OSC_DIV_SHIFT                (2U)
12660 /*! OSC_DIV
12661  *  0b00..use ring oscillator with no divide
12662  *  0b01..use ring oscillator divided-by-2
12663  *  0b10..use ring oscillator divided-by-4
12664  *  0b11..use ring oscillator divided-by-8
12665  */
12666 #define CAAM_RTMCTL_OSC_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK)
12667 
12668 #define CAAM_RTMCTL_CLK_OUT_EN_MASK              (0x10U)
12669 #define CAAM_RTMCTL_CLK_OUT_EN_SHIFT             (4U)
12670 #define CAAM_RTMCTL_CLK_OUT_EN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK)
12671 
12672 #define CAAM_RTMCTL_TRNG_ACC_MASK                (0x20U)
12673 #define CAAM_RTMCTL_TRNG_ACC_SHIFT               (5U)
12674 #define CAAM_RTMCTL_TRNG_ACC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK)
12675 
12676 #define CAAM_RTMCTL_RST_DEF_MASK                 (0x40U)
12677 #define CAAM_RTMCTL_RST_DEF_SHIFT                (6U)
12678 #define CAAM_RTMCTL_RST_DEF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK)
12679 
12680 #define CAAM_RTMCTL_FORCE_SYSCLK_MASK            (0x80U)
12681 #define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT           (7U)
12682 #define CAAM_RTMCTL_FORCE_SYSCLK(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK)
12683 
12684 #define CAAM_RTMCTL_FCT_FAIL_MASK                (0x100U)
12685 #define CAAM_RTMCTL_FCT_FAIL_SHIFT               (8U)
12686 #define CAAM_RTMCTL_FCT_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK)
12687 
12688 #define CAAM_RTMCTL_FCT_VAL_MASK                 (0x200U)
12689 #define CAAM_RTMCTL_FCT_VAL_SHIFT                (9U)
12690 #define CAAM_RTMCTL_FCT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK)
12691 
12692 #define CAAM_RTMCTL_ENT_VAL_MASK                 (0x400U)
12693 #define CAAM_RTMCTL_ENT_VAL_SHIFT                (10U)
12694 #define CAAM_RTMCTL_ENT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK)
12695 
12696 #define CAAM_RTMCTL_TST_OUT_MASK                 (0x800U)
12697 #define CAAM_RTMCTL_TST_OUT_SHIFT                (11U)
12698 #define CAAM_RTMCTL_TST_OUT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK)
12699 
12700 #define CAAM_RTMCTL_ERR_MASK                     (0x1000U)
12701 #define CAAM_RTMCTL_ERR_SHIFT                    (12U)
12702 #define CAAM_RTMCTL_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK)
12703 
12704 #define CAAM_RTMCTL_TSTOP_OK_MASK                (0x2000U)
12705 #define CAAM_RTMCTL_TSTOP_OK_SHIFT               (13U)
12706 #define CAAM_RTMCTL_TSTOP_OK(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK)
12707 
12708 #define CAAM_RTMCTL_PRGM_MASK                    (0x10000U)
12709 #define CAAM_RTMCTL_PRGM_SHIFT                   (16U)
12710 #define CAAM_RTMCTL_PRGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK)
12711 /*! @} */
12712 
12713 /*! @name RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register */
12714 /*! @{ */
12715 
12716 #define CAAM_RTSCMISC_LRUN_MAX_MASK              (0xFFU)
12717 #define CAAM_RTSCMISC_LRUN_MAX_SHIFT             (0U)
12718 #define CAAM_RTSCMISC_LRUN_MAX(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK)
12719 
12720 #define CAAM_RTSCMISC_RTY_CNT_MASK               (0xF0000U)
12721 #define CAAM_RTSCMISC_RTY_CNT_SHIFT              (16U)
12722 #define CAAM_RTSCMISC_RTY_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK)
12723 /*! @} */
12724 
12725 /*! @name RTPKRRNG - RNG TRNG Poker Range Register */
12726 /*! @{ */
12727 
12728 #define CAAM_RTPKRRNG_PKR_RNG_MASK               (0xFFFFU)
12729 #define CAAM_RTPKRRNG_PKR_RNG_SHIFT              (0U)
12730 #define CAAM_RTPKRRNG_PKR_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK)
12731 /*! @} */
12732 
12733 /*! @name RTPKRMAX - RNG TRNG Poker Maximum Limit Register */
12734 /*! @{ */
12735 
12736 #define CAAM_RTPKRMAX_PKR_MAX_MASK               (0xFFFFFFU)
12737 #define CAAM_RTPKRMAX_PKR_MAX_SHIFT              (0U)
12738 #define CAAM_RTPKRMAX_PKR_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK)
12739 /*! @} */
12740 
12741 /*! @name RTPKRSQ - RNG TRNG Poker Square Calculation Result Register */
12742 /*! @{ */
12743 
12744 #define CAAM_RTPKRSQ_PKR_SQ_MASK                 (0xFFFFFFU)
12745 #define CAAM_RTPKRSQ_PKR_SQ_SHIFT                (0U)
12746 #define CAAM_RTPKRSQ_PKR_SQ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK)
12747 /*! @} */
12748 
12749 /*! @name RTSDCTL - RNG TRNG Seed Control Register */
12750 /*! @{ */
12751 
12752 #define CAAM_RTSDCTL_SAMP_SIZE_MASK              (0xFFFFU)
12753 #define CAAM_RTSDCTL_SAMP_SIZE_SHIFT             (0U)
12754 #define CAAM_RTSDCTL_SAMP_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK)
12755 
12756 #define CAAM_RTSDCTL_ENT_DLY_MASK                (0xFFFF0000U)
12757 #define CAAM_RTSDCTL_ENT_DLY_SHIFT               (16U)
12758 #define CAAM_RTSDCTL_ENT_DLY(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK)
12759 /*! @} */
12760 
12761 /*! @name RTSBLIM - RNG TRNG Sparse Bit Limit Register */
12762 /*! @{ */
12763 
12764 #define CAAM_RTSBLIM_SB_LIM_MASK                 (0x3FFU)
12765 #define CAAM_RTSBLIM_SB_LIM_SHIFT                (0U)
12766 #define CAAM_RTSBLIM_SB_LIM(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK)
12767 /*! @} */
12768 
12769 /*! @name RTTOTSAM - RNG TRNG Total Samples Register */
12770 /*! @{ */
12771 
12772 #define CAAM_RTTOTSAM_TOT_SAM_MASK               (0xFFFFFU)
12773 #define CAAM_RTTOTSAM_TOT_SAM_SHIFT              (0U)
12774 #define CAAM_RTTOTSAM_TOT_SAM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK)
12775 /*! @} */
12776 
12777 /*! @name RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register */
12778 /*! @{ */
12779 
12780 #define CAAM_RTFRQMIN_FRQ_MIN_MASK               (0x3FFFFFU)
12781 #define CAAM_RTFRQMIN_FRQ_MIN_SHIFT              (0U)
12782 #define CAAM_RTFRQMIN_FRQ_MIN(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK)
12783 /*! @} */
12784 
12785 /*! @name RTFRQCNT - RNG TRNG Frequency Count Register */
12786 /*! @{ */
12787 
12788 #define CAAM_RTFRQCNT_FRQ_CNT_MASK               (0x3FFFFFU)
12789 #define CAAM_RTFRQCNT_FRQ_CNT_SHIFT              (0U)
12790 #define CAAM_RTFRQCNT_FRQ_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK)
12791 /*! @} */
12792 
12793 /*! @name RTSCMC - RNG TRNG Statistical Check Monobit Count Register */
12794 /*! @{ */
12795 
12796 #define CAAM_RTSCMC_MONO_CNT_MASK                (0xFFFFU)
12797 #define CAAM_RTSCMC_MONO_CNT_SHIFT               (0U)
12798 #define CAAM_RTSCMC_MONO_CNT(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK)
12799 /*! @} */
12800 
12801 /*! @name RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register */
12802 /*! @{ */
12803 
12804 #define CAAM_RTSCR1C_R1_0_COUNT_MASK             (0x7FFFU)
12805 #define CAAM_RTSCR1C_R1_0_COUNT_SHIFT            (0U)
12806 #define CAAM_RTSCR1C_R1_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK)
12807 
12808 #define CAAM_RTSCR1C_R1_1_COUNT_MASK             (0x7FFF0000U)
12809 #define CAAM_RTSCR1C_R1_1_COUNT_SHIFT            (16U)
12810 #define CAAM_RTSCR1C_R1_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK)
12811 /*! @} */
12812 
12813 /*! @name RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register */
12814 /*! @{ */
12815 
12816 #define CAAM_RTSCR2C_R2_0_COUNT_MASK             (0x3FFFU)
12817 #define CAAM_RTSCR2C_R2_0_COUNT_SHIFT            (0U)
12818 #define CAAM_RTSCR2C_R2_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK)
12819 
12820 #define CAAM_RTSCR2C_R2_1_COUNT_MASK             (0x3FFF0000U)
12821 #define CAAM_RTSCR2C_R2_1_COUNT_SHIFT            (16U)
12822 #define CAAM_RTSCR2C_R2_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK)
12823 /*! @} */
12824 
12825 /*! @name RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register */
12826 /*! @{ */
12827 
12828 #define CAAM_RTSCR3C_R3_0_COUNT_MASK             (0x1FFFU)
12829 #define CAAM_RTSCR3C_R3_0_COUNT_SHIFT            (0U)
12830 #define CAAM_RTSCR3C_R3_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK)
12831 
12832 #define CAAM_RTSCR3C_R3_1_COUNT_MASK             (0x1FFF0000U)
12833 #define CAAM_RTSCR3C_R3_1_COUNT_SHIFT            (16U)
12834 #define CAAM_RTSCR3C_R3_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK)
12835 /*! @} */
12836 
12837 /*! @name RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register */
12838 /*! @{ */
12839 
12840 #define CAAM_RTSCR4C_R4_0_COUNT_MASK             (0xFFFU)
12841 #define CAAM_RTSCR4C_R4_0_COUNT_SHIFT            (0U)
12842 #define CAAM_RTSCR4C_R4_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK)
12843 
12844 #define CAAM_RTSCR4C_R4_1_COUNT_MASK             (0xFFF0000U)
12845 #define CAAM_RTSCR4C_R4_1_COUNT_SHIFT            (16U)
12846 #define CAAM_RTSCR4C_R4_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK)
12847 /*! @} */
12848 
12849 /*! @name RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register */
12850 /*! @{ */
12851 
12852 #define CAAM_RTSCR5C_R5_0_COUNT_MASK             (0x7FFU)
12853 #define CAAM_RTSCR5C_R5_0_COUNT_SHIFT            (0U)
12854 #define CAAM_RTSCR5C_R5_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK)
12855 
12856 #define CAAM_RTSCR5C_R5_1_COUNT_MASK             (0x7FF0000U)
12857 #define CAAM_RTSCR5C_R5_1_COUNT_SHIFT            (16U)
12858 #define CAAM_RTSCR5C_R5_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK)
12859 /*! @} */
12860 
12861 /*! @name RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register */
12862 /*! @{ */
12863 
12864 #define CAAM_RTSCR6PC_R6P_0_COUNT_MASK           (0x7FFU)
12865 #define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT          (0U)
12866 #define CAAM_RTSCR6PC_R6P_0_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK)
12867 
12868 #define CAAM_RTSCR6PC_R6P_1_COUNT_MASK           (0x7FF0000U)
12869 #define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT          (16U)
12870 #define CAAM_RTSCR6PC_R6P_1_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK)
12871 /*! @} */
12872 
12873 /*! @name RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register */
12874 /*! @{ */
12875 
12876 #define CAAM_RTFRQMAX_FRQ_MAX_MASK               (0x3FFFFFU)
12877 #define CAAM_RTFRQMAX_FRQ_MAX_SHIFT              (0U)
12878 #define CAAM_RTFRQMAX_FRQ_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK)
12879 /*! @} */
12880 
12881 /*! @name RTSCML - RNG TRNG Statistical Check Monobit Limit Register */
12882 /*! @{ */
12883 
12884 #define CAAM_RTSCML_MONO_MAX_MASK                (0xFFFFU)
12885 #define CAAM_RTSCML_MONO_MAX_SHIFT               (0U)
12886 #define CAAM_RTSCML_MONO_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK)
12887 
12888 #define CAAM_RTSCML_MONO_RNG_MASK                (0xFFFF0000U)
12889 #define CAAM_RTSCML_MONO_RNG_SHIFT               (16U)
12890 #define CAAM_RTSCML_MONO_RNG(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK)
12891 /*! @} */
12892 
12893 /*! @name RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register */
12894 /*! @{ */
12895 
12896 #define CAAM_RTSCR1L_RUN1_MAX_MASK               (0x7FFFU)
12897 #define CAAM_RTSCR1L_RUN1_MAX_SHIFT              (0U)
12898 #define CAAM_RTSCR1L_RUN1_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK)
12899 
12900 #define CAAM_RTSCR1L_RUN1_RNG_MASK               (0x7FFF0000U)
12901 #define CAAM_RTSCR1L_RUN1_RNG_SHIFT              (16U)
12902 #define CAAM_RTSCR1L_RUN1_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK)
12903 /*! @} */
12904 
12905 /*! @name RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register */
12906 /*! @{ */
12907 
12908 #define CAAM_RTSCR2L_RUN2_MAX_MASK               (0x3FFFU)
12909 #define CAAM_RTSCR2L_RUN2_MAX_SHIFT              (0U)
12910 #define CAAM_RTSCR2L_RUN2_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK)
12911 
12912 #define CAAM_RTSCR2L_RUN2_RNG_MASK               (0x3FFF0000U)
12913 #define CAAM_RTSCR2L_RUN2_RNG_SHIFT              (16U)
12914 #define CAAM_RTSCR2L_RUN2_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK)
12915 /*! @} */
12916 
12917 /*! @name RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register */
12918 /*! @{ */
12919 
12920 #define CAAM_RTSCR3L_RUN3_MAX_MASK               (0x1FFFU)
12921 #define CAAM_RTSCR3L_RUN3_MAX_SHIFT              (0U)
12922 #define CAAM_RTSCR3L_RUN3_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK)
12923 
12924 #define CAAM_RTSCR3L_RUN3_RNG_MASK               (0x1FFF0000U)
12925 #define CAAM_RTSCR3L_RUN3_RNG_SHIFT              (16U)
12926 #define CAAM_RTSCR3L_RUN3_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK)
12927 /*! @} */
12928 
12929 /*! @name RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register */
12930 /*! @{ */
12931 
12932 #define CAAM_RTSCR4L_RUN4_MAX_MASK               (0xFFFU)
12933 #define CAAM_RTSCR4L_RUN4_MAX_SHIFT              (0U)
12934 #define CAAM_RTSCR4L_RUN4_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK)
12935 
12936 #define CAAM_RTSCR4L_RUN4_RNG_MASK               (0xFFF0000U)
12937 #define CAAM_RTSCR4L_RUN4_RNG_SHIFT              (16U)
12938 #define CAAM_RTSCR4L_RUN4_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK)
12939 /*! @} */
12940 
12941 /*! @name RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register */
12942 /*! @{ */
12943 
12944 #define CAAM_RTSCR5L_RUN5_MAX_MASK               (0x7FFU)
12945 #define CAAM_RTSCR5L_RUN5_MAX_SHIFT              (0U)
12946 #define CAAM_RTSCR5L_RUN5_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK)
12947 
12948 #define CAAM_RTSCR5L_RUN5_RNG_MASK               (0x7FF0000U)
12949 #define CAAM_RTSCR5L_RUN5_RNG_SHIFT              (16U)
12950 #define CAAM_RTSCR5L_RUN5_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK)
12951 /*! @} */
12952 
12953 /*! @name RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register */
12954 /*! @{ */
12955 
12956 #define CAAM_RTSCR6PL_RUN6P_MAX_MASK             (0x7FFU)
12957 #define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT            (0U)
12958 #define CAAM_RTSCR6PL_RUN6P_MAX(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK)
12959 
12960 #define CAAM_RTSCR6PL_RUN6P_RNG_MASK             (0x7FF0000U)
12961 #define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT            (16U)
12962 #define CAAM_RTSCR6PL_RUN6P_RNG(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK)
12963 /*! @} */
12964 
12965 /*! @name RTSTATUS - RNG TRNG Status Register */
12966 /*! @{ */
12967 
12968 #define CAAM_RTSTATUS_F1BR0TF_MASK               (0x1U)
12969 #define CAAM_RTSTATUS_F1BR0TF_SHIFT              (0U)
12970 #define CAAM_RTSTATUS_F1BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK)
12971 
12972 #define CAAM_RTSTATUS_F1BR1TF_MASK               (0x2U)
12973 #define CAAM_RTSTATUS_F1BR1TF_SHIFT              (1U)
12974 #define CAAM_RTSTATUS_F1BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK)
12975 
12976 #define CAAM_RTSTATUS_F2BR0TF_MASK               (0x4U)
12977 #define CAAM_RTSTATUS_F2BR0TF_SHIFT              (2U)
12978 #define CAAM_RTSTATUS_F2BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK)
12979 
12980 #define CAAM_RTSTATUS_F2BR1TF_MASK               (0x8U)
12981 #define CAAM_RTSTATUS_F2BR1TF_SHIFT              (3U)
12982 #define CAAM_RTSTATUS_F2BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK)
12983 
12984 #define CAAM_RTSTATUS_F3BR01TF_MASK              (0x10U)
12985 #define CAAM_RTSTATUS_F3BR01TF_SHIFT             (4U)
12986 #define CAAM_RTSTATUS_F3BR01TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK)
12987 
12988 #define CAAM_RTSTATUS_F3BR1TF_MASK               (0x20U)
12989 #define CAAM_RTSTATUS_F3BR1TF_SHIFT              (5U)
12990 #define CAAM_RTSTATUS_F3BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK)
12991 
12992 #define CAAM_RTSTATUS_F4BR0TF_MASK               (0x40U)
12993 #define CAAM_RTSTATUS_F4BR0TF_SHIFT              (6U)
12994 #define CAAM_RTSTATUS_F4BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK)
12995 
12996 #define CAAM_RTSTATUS_F4BR1TF_MASK               (0x80U)
12997 #define CAAM_RTSTATUS_F4BR1TF_SHIFT              (7U)
12998 #define CAAM_RTSTATUS_F4BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK)
12999 
13000 #define CAAM_RTSTATUS_F5BR0TF_MASK               (0x100U)
13001 #define CAAM_RTSTATUS_F5BR0TF_SHIFT              (8U)
13002 #define CAAM_RTSTATUS_F5BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK)
13003 
13004 #define CAAM_RTSTATUS_F5BR1TF_MASK               (0x200U)
13005 #define CAAM_RTSTATUS_F5BR1TF_SHIFT              (9U)
13006 #define CAAM_RTSTATUS_F5BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK)
13007 
13008 #define CAAM_RTSTATUS_F6PBR0TF_MASK              (0x400U)
13009 #define CAAM_RTSTATUS_F6PBR0TF_SHIFT             (10U)
13010 #define CAAM_RTSTATUS_F6PBR0TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK)
13011 
13012 #define CAAM_RTSTATUS_F6PBR1TF_MASK              (0x800U)
13013 #define CAAM_RTSTATUS_F6PBR1TF_SHIFT             (11U)
13014 #define CAAM_RTSTATUS_F6PBR1TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK)
13015 
13016 #define CAAM_RTSTATUS_FSBTF_MASK                 (0x1000U)
13017 #define CAAM_RTSTATUS_FSBTF_SHIFT                (12U)
13018 #define CAAM_RTSTATUS_FSBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK)
13019 
13020 #define CAAM_RTSTATUS_FLRTF_MASK                 (0x2000U)
13021 #define CAAM_RTSTATUS_FLRTF_SHIFT                (13U)
13022 #define CAAM_RTSTATUS_FLRTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK)
13023 
13024 #define CAAM_RTSTATUS_FPTF_MASK                  (0x4000U)
13025 #define CAAM_RTSTATUS_FPTF_SHIFT                 (14U)
13026 #define CAAM_RTSTATUS_FPTF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK)
13027 
13028 #define CAAM_RTSTATUS_FMBTF_MASK                 (0x8000U)
13029 #define CAAM_RTSTATUS_FMBTF_SHIFT                (15U)
13030 #define CAAM_RTSTATUS_FMBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK)
13031 
13032 #define CAAM_RTSTATUS_RETRY_COUNT_MASK           (0xF0000U)
13033 #define CAAM_RTSTATUS_RETRY_COUNT_SHIFT          (16U)
13034 #define CAAM_RTSTATUS_RETRY_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK)
13035 /*! @} */
13036 
13037 /*! @name RTENT - RNG TRNG Entropy Read Register */
13038 /*! @{ */
13039 
13040 #define CAAM_RTENT_ENT_MASK                      (0xFFFFFFFFU)
13041 #define CAAM_RTENT_ENT_SHIFT                     (0U)
13042 #define CAAM_RTENT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK)
13043 /*! @} */
13044 
13045 /* The count of CAAM_RTENT */
13046 #define CAAM_RTENT_COUNT                         (16U)
13047 
13048 /*! @name RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register */
13049 /*! @{ */
13050 
13051 #define CAAM_RTPKRCNT10_PKR_0_CNT_MASK           (0xFFFFU)
13052 #define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT          (0U)
13053 #define CAAM_RTPKRCNT10_PKR_0_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK)
13054 
13055 #define CAAM_RTPKRCNT10_PKR_1_CNT_MASK           (0xFFFF0000U)
13056 #define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT          (16U)
13057 #define CAAM_RTPKRCNT10_PKR_1_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK)
13058 /*! @} */
13059 
13060 /*! @name RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register */
13061 /*! @{ */
13062 
13063 #define CAAM_RTPKRCNT32_PKR_2_CNT_MASK           (0xFFFFU)
13064 #define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT          (0U)
13065 #define CAAM_RTPKRCNT32_PKR_2_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK)
13066 
13067 #define CAAM_RTPKRCNT32_PKR_3_CNT_MASK           (0xFFFF0000U)
13068 #define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT          (16U)
13069 #define CAAM_RTPKRCNT32_PKR_3_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK)
13070 /*! @} */
13071 
13072 /*! @name RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register */
13073 /*! @{ */
13074 
13075 #define CAAM_RTPKRCNT54_PKR_4_CNT_MASK           (0xFFFFU)
13076 #define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT          (0U)
13077 #define CAAM_RTPKRCNT54_PKR_4_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK)
13078 
13079 #define CAAM_RTPKRCNT54_PKR_5_CNT_MASK           (0xFFFF0000U)
13080 #define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT          (16U)
13081 #define CAAM_RTPKRCNT54_PKR_5_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK)
13082 /*! @} */
13083 
13084 /*! @name RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register */
13085 /*! @{ */
13086 
13087 #define CAAM_RTPKRCNT76_PKR_6_CNT_MASK           (0xFFFFU)
13088 #define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT          (0U)
13089 #define CAAM_RTPKRCNT76_PKR_6_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK)
13090 
13091 #define CAAM_RTPKRCNT76_PKR_7_CNT_MASK           (0xFFFF0000U)
13092 #define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT          (16U)
13093 #define CAAM_RTPKRCNT76_PKR_7_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK)
13094 /*! @} */
13095 
13096 /*! @name RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register */
13097 /*! @{ */
13098 
13099 #define CAAM_RTPKRCNT98_PKR_8_CNT_MASK           (0xFFFFU)
13100 #define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT          (0U)
13101 #define CAAM_RTPKRCNT98_PKR_8_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK)
13102 
13103 #define CAAM_RTPKRCNT98_PKR_9_CNT_MASK           (0xFFFF0000U)
13104 #define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT          (16U)
13105 #define CAAM_RTPKRCNT98_PKR_9_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK)
13106 /*! @} */
13107 
13108 /*! @name RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register */
13109 /*! @{ */
13110 
13111 #define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK           (0xFFFFU)
13112 #define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT          (0U)
13113 #define CAAM_RTPKRCNTBA_PKR_A_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK)
13114 
13115 #define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK           (0xFFFF0000U)
13116 #define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT          (16U)
13117 #define CAAM_RTPKRCNTBA_PKR_B_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK)
13118 /*! @} */
13119 
13120 /*! @name RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register */
13121 /*! @{ */
13122 
13123 #define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK           (0xFFFFU)
13124 #define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT          (0U)
13125 #define CAAM_RTPKRCNTDC_PKR_C_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK)
13126 
13127 #define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK           (0xFFFF0000U)
13128 #define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT          (16U)
13129 #define CAAM_RTPKRCNTDC_PKR_D_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK)
13130 /*! @} */
13131 
13132 /*! @name RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register */
13133 /*! @{ */
13134 
13135 #define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK           (0xFFFFU)
13136 #define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT          (0U)
13137 #define CAAM_RTPKRCNTFE_PKR_E_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK)
13138 
13139 #define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK           (0xFFFF0000U)
13140 #define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT          (16U)
13141 #define CAAM_RTPKRCNTFE_PKR_F_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK)
13142 /*! @} */
13143 
13144 /*! @name RDSTA - RNG DRNG Status Register */
13145 /*! @{ */
13146 
13147 #define CAAM_RDSTA_IF0_MASK                      (0x1U)
13148 #define CAAM_RDSTA_IF0_SHIFT                     (0U)
13149 #define CAAM_RDSTA_IF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK)
13150 
13151 #define CAAM_RDSTA_IF1_MASK                      (0x2U)
13152 #define CAAM_RDSTA_IF1_SHIFT                     (1U)
13153 #define CAAM_RDSTA_IF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK)
13154 
13155 #define CAAM_RDSTA_PR0_MASK                      (0x10U)
13156 #define CAAM_RDSTA_PR0_SHIFT                     (4U)
13157 #define CAAM_RDSTA_PR0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK)
13158 
13159 #define CAAM_RDSTA_PR1_MASK                      (0x20U)
13160 #define CAAM_RDSTA_PR1_SHIFT                     (5U)
13161 #define CAAM_RDSTA_PR1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK)
13162 
13163 #define CAAM_RDSTA_TF0_MASK                      (0x100U)
13164 #define CAAM_RDSTA_TF0_SHIFT                     (8U)
13165 #define CAAM_RDSTA_TF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK)
13166 
13167 #define CAAM_RDSTA_TF1_MASK                      (0x200U)
13168 #define CAAM_RDSTA_TF1_SHIFT                     (9U)
13169 #define CAAM_RDSTA_TF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK)
13170 
13171 #define CAAM_RDSTA_ERRCODE_MASK                  (0xF0000U)
13172 #define CAAM_RDSTA_ERRCODE_SHIFT                 (16U)
13173 #define CAAM_RDSTA_ERRCODE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK)
13174 
13175 #define CAAM_RDSTA_CE_MASK                       (0x100000U)
13176 #define CAAM_RDSTA_CE_SHIFT                      (20U)
13177 #define CAAM_RDSTA_CE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK)
13178 
13179 #define CAAM_RDSTA_SKVN_MASK                     (0x40000000U)
13180 #define CAAM_RDSTA_SKVN_SHIFT                    (30U)
13181 #define CAAM_RDSTA_SKVN(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK)
13182 
13183 #define CAAM_RDSTA_SKVT_MASK                     (0x80000000U)
13184 #define CAAM_RDSTA_SKVT_SHIFT                    (31U)
13185 #define CAAM_RDSTA_SKVT(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK)
13186 /*! @} */
13187 
13188 /*! @name RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register */
13189 /*! @{ */
13190 
13191 #define CAAM_RDINT0_RESINT0_MASK                 (0xFFFFFFFFU)
13192 #define CAAM_RDINT0_RESINT0_SHIFT                (0U)
13193 #define CAAM_RDINT0_RESINT0(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK)
13194 /*! @} */
13195 
13196 /*! @name RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register */
13197 /*! @{ */
13198 
13199 #define CAAM_RDINT1_RESINT1_MASK                 (0xFFFFFFFFU)
13200 #define CAAM_RDINT1_RESINT1_SHIFT                (0U)
13201 #define CAAM_RDINT1_RESINT1(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK)
13202 /*! @} */
13203 
13204 /*! @name RDHCNTL - RNG DRNG Hash Control Register */
13205 /*! @{ */
13206 
13207 #define CAAM_RDHCNTL_HD_MASK                     (0x1U)
13208 #define CAAM_RDHCNTL_HD_SHIFT                    (0U)
13209 #define CAAM_RDHCNTL_HD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK)
13210 
13211 #define CAAM_RDHCNTL_HB_MASK                     (0x2U)
13212 #define CAAM_RDHCNTL_HB_SHIFT                    (1U)
13213 #define CAAM_RDHCNTL_HB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK)
13214 
13215 #define CAAM_RDHCNTL_HI_MASK                     (0x4U)
13216 #define CAAM_RDHCNTL_HI_SHIFT                    (2U)
13217 #define CAAM_RDHCNTL_HI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK)
13218 
13219 #define CAAM_RDHCNTL_HTM_MASK                    (0x8U)
13220 #define CAAM_RDHCNTL_HTM_SHIFT                   (3U)
13221 #define CAAM_RDHCNTL_HTM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK)
13222 
13223 #define CAAM_RDHCNTL_HTC_MASK                    (0x10U)
13224 #define CAAM_RDHCNTL_HTC_SHIFT                   (4U)
13225 #define CAAM_RDHCNTL_HTC(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK)
13226 /*! @} */
13227 
13228 /*! @name RDHDIG - RNG DRNG Hash Digest Register */
13229 /*! @{ */
13230 
13231 #define CAAM_RDHDIG_HASHMD_MASK                  (0xFFFFFFFFU)
13232 #define CAAM_RDHDIG_HASHMD_SHIFT                 (0U)
13233 #define CAAM_RDHDIG_HASHMD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK)
13234 /*! @} */
13235 
13236 /*! @name RDHBUF - RNG DRNG Hash Buffer Register */
13237 /*! @{ */
13238 
13239 #define CAAM_RDHBUF_HASHBUF_MASK                 (0xFFFFFFFFU)
13240 #define CAAM_RDHBUF_HASHBUF_SHIFT                (0U)
13241 #define CAAM_RDHBUF_HASHBUF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK)
13242 /*! @} */
13243 
13244 /*! @name PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register */
13245 /*! @{ */
13246 
13247 #define CAAM_PX_SDID_PG0_SDID_MASK               (0xFFFFU)
13248 #define CAAM_PX_SDID_PG0_SDID_SHIFT              (0U)
13249 #define CAAM_PX_SDID_PG0_SDID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK)
13250 /*! @} */
13251 
13252 /* The count of CAAM_PX_SDID_PG0 */
13253 #define CAAM_PX_SDID_PG0_COUNT                   (16U)
13254 
13255 /*! @name PX_SMAPR_PG0 - Secure Memory Access Permissions register */
13256 /*! @{ */
13257 
13258 #define CAAM_PX_SMAPR_PG0_G1_READ_MASK           (0x1U)
13259 #define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT          (0U)
13260 /*! G1_READ
13261  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
13262  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
13263  *       Trusted Descriptor and G1_TDO=1).
13264  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13265  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
13266  */
13267 #define CAAM_PX_SMAPR_PG0_G1_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK)
13268 
13269 #define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK          (0x2U)
13270 #define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT         (1U)
13271 /*! G1_WRITE
13272  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13273  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
13274  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
13275  *       not a Trusted Descriptor or if G1_TDO=0).
13276  */
13277 #define CAAM_PX_SMAPR_PG0_G1_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK)
13278 
13279 #define CAAM_PX_SMAPR_PG0_G1_TDO_MASK            (0x4U)
13280 #define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT           (2U)
13281 /*! G1_TDO
13282  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13283  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13284  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
13285  *       G1_WRITE and G1_READ settings.
13286  */
13287 #define CAAM_PX_SMAPR_PG0_G1_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK)
13288 
13289 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK         (0x8U)
13290 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT        (3U)
13291 /*! G1_SMBLOB
13292  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
13293  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
13294  */
13295 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK)
13296 
13297 #define CAAM_PX_SMAPR_PG0_G2_READ_MASK           (0x10U)
13298 #define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT          (4U)
13299 /*! G2_READ
13300  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
13301  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
13302  *       Trusted Descriptor and G2_TDO=1).
13303  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13304  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
13305  */
13306 #define CAAM_PX_SMAPR_PG0_G2_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK)
13307 
13308 #define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK          (0x20U)
13309 #define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT         (5U)
13310 /*! G2_WRITE
13311  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13312  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
13313  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
13314  *       not a Trusted Descriptor or if G2_TDO=0).
13315  */
13316 #define CAAM_PX_SMAPR_PG0_G2_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK)
13317 
13318 #define CAAM_PX_SMAPR_PG0_G2_TDO_MASK            (0x40U)
13319 #define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT           (6U)
13320 /*! G2_TDO
13321  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13322  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13323  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
13324  *       G2_WRITE and G2_READ settings.
13325  */
13326 #define CAAM_PX_SMAPR_PG0_G2_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK)
13327 
13328 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK         (0x80U)
13329 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT        (7U)
13330 /*! G2_SMBLOB
13331  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
13332  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
13333  */
13334 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK)
13335 
13336 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK          (0x1000U)
13337 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT         (12U)
13338 /*! SMAG_LCK
13339  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
13340  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
13341  *       until the partition is de-allocated or a POR occurs.
13342  */
13343 #define CAAM_PX_SMAPR_PG0_SMAG_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK)
13344 
13345 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK          (0x2000U)
13346 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT         (13U)
13347 /*! SMAP_LCK
13348  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
13349  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
13350  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
13351  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
13352  */
13353 #define CAAM_PX_SMAPR_PG0_SMAP_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK)
13354 
13355 #define CAAM_PX_SMAPR_PG0_PSP_MASK               (0x4000U)
13356 #define CAAM_PX_SMAPR_PG0_PSP_SHIFT              (14U)
13357 /*! PSP
13358  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
13359  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
13360  */
13361 #define CAAM_PX_SMAPR_PG0_PSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK)
13362 
13363 #define CAAM_PX_SMAPR_PG0_CSP_MASK               (0x8000U)
13364 #define CAAM_PX_SMAPR_PG0_CSP_SHIFT              (15U)
13365 /*! CSP
13366  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
13367  *       released or a security alarm occurs.
13368  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
13369  *       partition is released or a security alarm occurs.
13370  */
13371 #define CAAM_PX_SMAPR_PG0_CSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK)
13372 
13373 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK    (0xFFFF0000U)
13374 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT   (16U)
13375 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK)
13376 /*! @} */
13377 
13378 /* The count of CAAM_PX_SMAPR_PG0 */
13379 #define CAAM_PX_SMAPR_PG0_COUNT                  (16U)
13380 
13381 /*! @name PX_SMAG2_PG0 - Secure Memory Access Group Registers */
13382 /*! @{ */
13383 
13384 #define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK           (0x1U)
13385 #define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT          (0U)
13386 #define CAAM_PX_SMAG2_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK)
13387 
13388 #define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK           (0x2U)
13389 #define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT          (1U)
13390 #define CAAM_PX_SMAG2_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK)
13391 
13392 #define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK           (0x4U)
13393 #define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT          (2U)
13394 #define CAAM_PX_SMAG2_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK)
13395 
13396 #define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK           (0x8U)
13397 #define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT          (3U)
13398 #define CAAM_PX_SMAG2_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK)
13399 
13400 #define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK           (0x10U)
13401 #define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT          (4U)
13402 #define CAAM_PX_SMAG2_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK)
13403 
13404 #define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK           (0x20U)
13405 #define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT          (5U)
13406 #define CAAM_PX_SMAG2_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK)
13407 
13408 #define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK           (0x40U)
13409 #define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT          (6U)
13410 #define CAAM_PX_SMAG2_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK)
13411 
13412 #define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK           (0x80U)
13413 #define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT          (7U)
13414 #define CAAM_PX_SMAG2_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK)
13415 
13416 #define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK           (0x100U)
13417 #define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT          (8U)
13418 #define CAAM_PX_SMAG2_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK)
13419 
13420 #define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK           (0x200U)
13421 #define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT          (9U)
13422 #define CAAM_PX_SMAG2_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK)
13423 
13424 #define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK           (0x400U)
13425 #define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT          (10U)
13426 #define CAAM_PX_SMAG2_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK)
13427 
13428 #define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK           (0x800U)
13429 #define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT          (11U)
13430 #define CAAM_PX_SMAG2_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK)
13431 
13432 #define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK           (0x1000U)
13433 #define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT          (12U)
13434 #define CAAM_PX_SMAG2_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK)
13435 
13436 #define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK           (0x2000U)
13437 #define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT          (13U)
13438 #define CAAM_PX_SMAG2_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK)
13439 
13440 #define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK           (0x4000U)
13441 #define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT          (14U)
13442 #define CAAM_PX_SMAG2_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK)
13443 
13444 #define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK           (0x8000U)
13445 #define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT          (15U)
13446 #define CAAM_PX_SMAG2_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK)
13447 
13448 #define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK           (0x10000U)
13449 #define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT          (16U)
13450 #define CAAM_PX_SMAG2_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK)
13451 
13452 #define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK           (0x20000U)
13453 #define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT          (17U)
13454 #define CAAM_PX_SMAG2_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK)
13455 
13456 #define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK           (0x40000U)
13457 #define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT          (18U)
13458 #define CAAM_PX_SMAG2_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK)
13459 
13460 #define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK           (0x80000U)
13461 #define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT          (19U)
13462 #define CAAM_PX_SMAG2_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK)
13463 
13464 #define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK           (0x100000U)
13465 #define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT          (20U)
13466 #define CAAM_PX_SMAG2_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK)
13467 
13468 #define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK           (0x200000U)
13469 #define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT          (21U)
13470 #define CAAM_PX_SMAG2_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK)
13471 
13472 #define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK           (0x400000U)
13473 #define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT          (22U)
13474 #define CAAM_PX_SMAG2_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK)
13475 
13476 #define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK           (0x800000U)
13477 #define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT          (23U)
13478 #define CAAM_PX_SMAG2_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK)
13479 
13480 #define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK           (0x1000000U)
13481 #define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT          (24U)
13482 #define CAAM_PX_SMAG2_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK)
13483 
13484 #define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK           (0x2000000U)
13485 #define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT          (25U)
13486 #define CAAM_PX_SMAG2_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK)
13487 
13488 #define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK           (0x4000000U)
13489 #define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT          (26U)
13490 #define CAAM_PX_SMAG2_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK)
13491 
13492 #define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK           (0x8000000U)
13493 #define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT          (27U)
13494 #define CAAM_PX_SMAG2_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK)
13495 
13496 #define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK           (0x10000000U)
13497 #define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT          (28U)
13498 #define CAAM_PX_SMAG2_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK)
13499 
13500 #define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK           (0x20000000U)
13501 #define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT          (29U)
13502 #define CAAM_PX_SMAG2_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK)
13503 
13504 #define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK           (0x40000000U)
13505 #define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT          (30U)
13506 #define CAAM_PX_SMAG2_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK)
13507 
13508 #define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK           (0x80000000U)
13509 #define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT          (31U)
13510 #define CAAM_PX_SMAG2_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK)
13511 /*! @} */
13512 
13513 /* The count of CAAM_PX_SMAG2_PG0 */
13514 #define CAAM_PX_SMAG2_PG0_COUNT                  (16U)
13515 
13516 /*! @name PX_SMAG1_PG0 - Secure Memory Access Group Registers */
13517 /*! @{ */
13518 
13519 #define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK           (0x1U)
13520 #define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT          (0U)
13521 #define CAAM_PX_SMAG1_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK)
13522 
13523 #define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK           (0x2U)
13524 #define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT          (1U)
13525 #define CAAM_PX_SMAG1_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK)
13526 
13527 #define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK           (0x4U)
13528 #define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT          (2U)
13529 #define CAAM_PX_SMAG1_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK)
13530 
13531 #define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK           (0x8U)
13532 #define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT          (3U)
13533 #define CAAM_PX_SMAG1_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK)
13534 
13535 #define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK           (0x10U)
13536 #define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT          (4U)
13537 #define CAAM_PX_SMAG1_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK)
13538 
13539 #define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK           (0x20U)
13540 #define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT          (5U)
13541 #define CAAM_PX_SMAG1_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK)
13542 
13543 #define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK           (0x40U)
13544 #define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT          (6U)
13545 #define CAAM_PX_SMAG1_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK)
13546 
13547 #define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK           (0x80U)
13548 #define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT          (7U)
13549 #define CAAM_PX_SMAG1_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK)
13550 
13551 #define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK           (0x100U)
13552 #define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT          (8U)
13553 #define CAAM_PX_SMAG1_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK)
13554 
13555 #define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK           (0x200U)
13556 #define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT          (9U)
13557 #define CAAM_PX_SMAG1_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK)
13558 
13559 #define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK           (0x400U)
13560 #define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT          (10U)
13561 #define CAAM_PX_SMAG1_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK)
13562 
13563 #define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK           (0x800U)
13564 #define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT          (11U)
13565 #define CAAM_PX_SMAG1_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK)
13566 
13567 #define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK           (0x1000U)
13568 #define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT          (12U)
13569 #define CAAM_PX_SMAG1_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK)
13570 
13571 #define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK           (0x2000U)
13572 #define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT          (13U)
13573 #define CAAM_PX_SMAG1_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK)
13574 
13575 #define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK           (0x4000U)
13576 #define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT          (14U)
13577 #define CAAM_PX_SMAG1_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK)
13578 
13579 #define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK           (0x8000U)
13580 #define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT          (15U)
13581 #define CAAM_PX_SMAG1_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK)
13582 
13583 #define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK           (0x10000U)
13584 #define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT          (16U)
13585 #define CAAM_PX_SMAG1_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK)
13586 
13587 #define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK           (0x20000U)
13588 #define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT          (17U)
13589 #define CAAM_PX_SMAG1_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK)
13590 
13591 #define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK           (0x40000U)
13592 #define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT          (18U)
13593 #define CAAM_PX_SMAG1_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK)
13594 
13595 #define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK           (0x80000U)
13596 #define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT          (19U)
13597 #define CAAM_PX_SMAG1_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK)
13598 
13599 #define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK           (0x100000U)
13600 #define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT          (20U)
13601 #define CAAM_PX_SMAG1_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK)
13602 
13603 #define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK           (0x200000U)
13604 #define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT          (21U)
13605 #define CAAM_PX_SMAG1_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK)
13606 
13607 #define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK           (0x400000U)
13608 #define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT          (22U)
13609 #define CAAM_PX_SMAG1_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK)
13610 
13611 #define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK           (0x800000U)
13612 #define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT          (23U)
13613 #define CAAM_PX_SMAG1_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK)
13614 
13615 #define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK           (0x1000000U)
13616 #define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT          (24U)
13617 #define CAAM_PX_SMAG1_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK)
13618 
13619 #define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK           (0x2000000U)
13620 #define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT          (25U)
13621 #define CAAM_PX_SMAG1_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK)
13622 
13623 #define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK           (0x4000000U)
13624 #define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT          (26U)
13625 #define CAAM_PX_SMAG1_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK)
13626 
13627 #define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK           (0x8000000U)
13628 #define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT          (27U)
13629 #define CAAM_PX_SMAG1_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK)
13630 
13631 #define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK           (0x10000000U)
13632 #define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT          (28U)
13633 #define CAAM_PX_SMAG1_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK)
13634 
13635 #define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK           (0x20000000U)
13636 #define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT          (29U)
13637 #define CAAM_PX_SMAG1_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK)
13638 
13639 #define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK           (0x40000000U)
13640 #define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT          (30U)
13641 #define CAAM_PX_SMAG1_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK)
13642 
13643 #define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK           (0x80000000U)
13644 #define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT          (31U)
13645 #define CAAM_PX_SMAG1_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK)
13646 /*! @} */
13647 
13648 /* The count of CAAM_PX_SMAG1_PG0 */
13649 #define CAAM_PX_SMAG1_PG0_COUNT                  (16U)
13650 
13651 /*! @name REIS - Recoverable Error Interrupt Status */
13652 /*! @{ */
13653 
13654 #define CAAM_REIS_CWDE_MASK                      (0x1U)
13655 #define CAAM_REIS_CWDE_SHIFT                     (0U)
13656 #define CAAM_REIS_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK)
13657 
13658 #define CAAM_REIS_RBAE_MASK                      (0x10000U)
13659 #define CAAM_REIS_RBAE_SHIFT                     (16U)
13660 #define CAAM_REIS_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK)
13661 
13662 #define CAAM_REIS_JBAE0_MASK                     (0x1000000U)
13663 #define CAAM_REIS_JBAE0_SHIFT                    (24U)
13664 #define CAAM_REIS_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK)
13665 
13666 #define CAAM_REIS_JBAE1_MASK                     (0x2000000U)
13667 #define CAAM_REIS_JBAE1_SHIFT                    (25U)
13668 #define CAAM_REIS_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK)
13669 
13670 #define CAAM_REIS_JBAE2_MASK                     (0x4000000U)
13671 #define CAAM_REIS_JBAE2_SHIFT                    (26U)
13672 #define CAAM_REIS_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK)
13673 
13674 #define CAAM_REIS_JBAE3_MASK                     (0x8000000U)
13675 #define CAAM_REIS_JBAE3_SHIFT                    (27U)
13676 #define CAAM_REIS_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK)
13677 /*! @} */
13678 
13679 /*! @name REIE - Recoverable Error Interrupt Enable */
13680 /*! @{ */
13681 
13682 #define CAAM_REIE_CWDE_MASK                      (0x1U)
13683 #define CAAM_REIE_CWDE_SHIFT                     (0U)
13684 #define CAAM_REIE_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK)
13685 
13686 #define CAAM_REIE_RBAE_MASK                      (0x10000U)
13687 #define CAAM_REIE_RBAE_SHIFT                     (16U)
13688 #define CAAM_REIE_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK)
13689 
13690 #define CAAM_REIE_JBAE0_MASK                     (0x1000000U)
13691 #define CAAM_REIE_JBAE0_SHIFT                    (24U)
13692 #define CAAM_REIE_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK)
13693 
13694 #define CAAM_REIE_JBAE1_MASK                     (0x2000000U)
13695 #define CAAM_REIE_JBAE1_SHIFT                    (25U)
13696 #define CAAM_REIE_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK)
13697 
13698 #define CAAM_REIE_JBAE2_MASK                     (0x4000000U)
13699 #define CAAM_REIE_JBAE2_SHIFT                    (26U)
13700 #define CAAM_REIE_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK)
13701 
13702 #define CAAM_REIE_JBAE3_MASK                     (0x8000000U)
13703 #define CAAM_REIE_JBAE3_SHIFT                    (27U)
13704 #define CAAM_REIE_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK)
13705 /*! @} */
13706 
13707 /*! @name REIF - Recoverable Error Interrupt Force */
13708 /*! @{ */
13709 
13710 #define CAAM_REIF_CWDE_MASK                      (0x1U)
13711 #define CAAM_REIF_CWDE_SHIFT                     (0U)
13712 #define CAAM_REIF_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK)
13713 
13714 #define CAAM_REIF_RBAE_MASK                      (0x10000U)
13715 #define CAAM_REIF_RBAE_SHIFT                     (16U)
13716 #define CAAM_REIF_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK)
13717 
13718 #define CAAM_REIF_JBAE0_MASK                     (0x1000000U)
13719 #define CAAM_REIF_JBAE0_SHIFT                    (24U)
13720 #define CAAM_REIF_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK)
13721 
13722 #define CAAM_REIF_JBAE1_MASK                     (0x2000000U)
13723 #define CAAM_REIF_JBAE1_SHIFT                    (25U)
13724 #define CAAM_REIF_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK)
13725 
13726 #define CAAM_REIF_JBAE2_MASK                     (0x4000000U)
13727 #define CAAM_REIF_JBAE2_SHIFT                    (26U)
13728 #define CAAM_REIF_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK)
13729 
13730 #define CAAM_REIF_JBAE3_MASK                     (0x8000000U)
13731 #define CAAM_REIF_JBAE3_SHIFT                    (27U)
13732 #define CAAM_REIF_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK)
13733 /*! @} */
13734 
13735 /*! @name REIH - Recoverable Error Interrupt Halt */
13736 /*! @{ */
13737 
13738 #define CAAM_REIH_CWDE_MASK                      (0x1U)
13739 #define CAAM_REIH_CWDE_SHIFT                     (0U)
13740 /*! CWDE
13741  *  0b0..Don't halt CAAM if CAAM watchdog expired.
13742  *  0b1..Halt CAAM if CAAM watchdog expired..
13743  */
13744 #define CAAM_REIH_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK)
13745 
13746 #define CAAM_REIH_RBAE_MASK                      (0x10000U)
13747 #define CAAM_REIH_RBAE_SHIFT                     (16U)
13748 /*! RBAE
13749  *  0b0..Don't halt CAAM if RTIC-initiated job execution caused bus access error.
13750  *  0b1..Halt CAAM if RTIC-initiated job execution caused bus access error.
13751  */
13752 #define CAAM_REIH_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK)
13753 
13754 #define CAAM_REIH_JBAE0_MASK                     (0x1000000U)
13755 #define CAAM_REIH_JBAE0_SHIFT                    (24U)
13756 /*! JBAE0
13757  *  0b0..Don't halt CAAM if JR0-initiated job execution caused bus access error.
13758  *  0b1..Halt CAAM if JR0-initiated job execution caused bus access error.
13759  */
13760 #define CAAM_REIH_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK)
13761 
13762 #define CAAM_REIH_JBAE1_MASK                     (0x2000000U)
13763 #define CAAM_REIH_JBAE1_SHIFT                    (25U)
13764 /*! JBAE1
13765  *  0b0..Don't halt CAAM if JR1-initiated job execution caused bus access error.
13766  *  0b1..Halt CAAM if JR1-initiated job execution caused bus access error.
13767  */
13768 #define CAAM_REIH_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK)
13769 
13770 #define CAAM_REIH_JBAE2_MASK                     (0x4000000U)
13771 #define CAAM_REIH_JBAE2_SHIFT                    (26U)
13772 /*! JBAE2
13773  *  0b0..Don't halt CAAM if JR2-initiated job execution caused bus access error.
13774  *  0b1..Halt CAAM if JR2-initiated job execution caused bus access error.
13775  */
13776 #define CAAM_REIH_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK)
13777 
13778 #define CAAM_REIH_JBAE3_MASK                     (0x8000000U)
13779 #define CAAM_REIH_JBAE3_SHIFT                    (27U)
13780 /*! JBAE3
13781  *  0b0..Don't halt CAAM if JR3-initiated job execution caused bus access error.
13782  *  0b1..Halt CAAM if JR3-initiated job execution caused bus access error.
13783  */
13784 #define CAAM_REIH_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK)
13785 /*! @} */
13786 
13787 /*! @name SMWPJRR - Secure Memory Write Protect Job Ring Register */
13788 /*! @{ */
13789 
13790 #define CAAM_SMWPJRR_SMR_WP_JRa_MASK             (0x1U)
13791 #define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT            (0U)
13792 #define CAAM_SMWPJRR_SMR_WP_JRa(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK)
13793 /*! @} */
13794 
13795 /* The count of CAAM_SMWPJRR */
13796 #define CAAM_SMWPJRR_COUNT                       (4U)
13797 
13798 /*! @name SMCR_PG0 - Secure Memory Command Register */
13799 /*! @{ */
13800 
13801 #define CAAM_SMCR_PG0_CMD_MASK                   (0xFU)
13802 #define CAAM_SMCR_PG0_CMD_SHIFT                  (0U)
13803 #define CAAM_SMCR_PG0_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK)
13804 
13805 #define CAAM_SMCR_PG0_PRTN_MASK                  (0xF00U)
13806 #define CAAM_SMCR_PG0_PRTN_SHIFT                 (8U)
13807 #define CAAM_SMCR_PG0_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK)
13808 
13809 #define CAAM_SMCR_PG0_PAGE_MASK                  (0xFFFF0000U)
13810 #define CAAM_SMCR_PG0_PAGE_SHIFT                 (16U)
13811 #define CAAM_SMCR_PG0_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK)
13812 /*! @} */
13813 
13814 /*! @name SMCSR_PG0 - Secure Memory Command Status Register */
13815 /*! @{ */
13816 
13817 #define CAAM_SMCSR_PG0_PRTN_MASK                 (0xFU)
13818 #define CAAM_SMCSR_PG0_PRTN_SHIFT                (0U)
13819 #define CAAM_SMCSR_PG0_PRTN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK)
13820 
13821 #define CAAM_SMCSR_PG0_PO_MASK                   (0xC0U)
13822 #define CAAM_SMCSR_PG0_PO_SHIFT                  (6U)
13823 /*! PO
13824  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
13825  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
13826  *  0b01..Page does not exist in this version or is not initialized yet.
13827  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
13828  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
13829  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
13830  *        upon de-allocation.
13831  */
13832 #define CAAM_SMCSR_PG0_PO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK)
13833 
13834 #define CAAM_SMCSR_PG0_AERR_MASK                 (0x3000U)
13835 #define CAAM_SMCSR_PG0_AERR_SHIFT                (12U)
13836 #define CAAM_SMCSR_PG0_AERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK)
13837 
13838 #define CAAM_SMCSR_PG0_CERR_MASK                 (0xC000U)
13839 #define CAAM_SMCSR_PG0_CERR_SHIFT                (14U)
13840 /*! CERR
13841  *  0b00..No Error.
13842  *  0b01..Command has not yet completed.
13843  *  0b10..A security failure occurred.
13844  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
13845  *        command completed. The additional command was ignored.
13846  */
13847 #define CAAM_SMCSR_PG0_CERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK)
13848 
13849 #define CAAM_SMCSR_PG0_PAGE_MASK                 (0xFFF0000U)
13850 #define CAAM_SMCSR_PG0_PAGE_SHIFT                (16U)
13851 #define CAAM_SMCSR_PG0_PAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK)
13852 /*! @} */
13853 
13854 /*! @name CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half */
13855 /*! @{ */
13856 
13857 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK        (0xFFU)
13858 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT       (0U)
13859 #define CAAM_CAAMVID_MS_TRAD_MIN_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK)
13860 
13861 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK        (0xFF00U)
13862 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT       (8U)
13863 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK)
13864 
13865 #define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK          (0xFFFF0000U)
13866 #define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT         (16U)
13867 #define CAAM_CAAMVID_MS_TRAD_IP_ID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK)
13868 /*! @} */
13869 
13870 /*! @name CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half */
13871 /*! @{ */
13872 
13873 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK     (0xFFU)
13874 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT    (0U)
13875 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK)
13876 
13877 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK        (0xFF00U)
13878 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT       (8U)
13879 #define CAAM_CAAMVID_LS_TRAD_ECO_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK)
13880 
13881 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK       (0xFF0000U)
13882 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT      (16U)
13883 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK)
13884 
13885 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK    (0xFF000000U)
13886 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT   (24U)
13887 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK)
13888 /*! @} */
13889 
13890 /*! @name HT_JD_ADDR - Holding Tank 0 Job Descriptor Address */
13891 /*! @{ */
13892 
13893 #define CAAM_HT_JD_ADDR_JD_ADDR_MASK             (0xFFFFFFFFFU)
13894 #define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT            (0U)
13895 #define CAAM_HT_JD_ADDR_JD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK)
13896 /*! @} */
13897 
13898 /* The count of CAAM_HT_JD_ADDR */
13899 #define CAAM_HT_JD_ADDR_COUNT                    (1U)
13900 
13901 /*! @name HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address */
13902 /*! @{ */
13903 
13904 #define CAAM_HT_SD_ADDR_SD_ADDR_MASK             (0xFFFFFFFFFU)
13905 #define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT            (0U)
13906 #define CAAM_HT_SD_ADDR_SD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK)
13907 /*! @} */
13908 
13909 /* The count of CAAM_HT_SD_ADDR */
13910 #define CAAM_HT_SD_ADDR_COUNT                    (1U)
13911 
13912 /*! @name HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half */
13913 /*! @{ */
13914 
13915 #define CAAM_HT_JQ_CTRL_MS_ID_MASK               (0x7U)
13916 #define CAAM_HT_JQ_CTRL_MS_ID_SHIFT              (0U)
13917 #define CAAM_HT_JQ_CTRL_MS_ID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK)
13918 
13919 #define CAAM_HT_JQ_CTRL_MS_SRC_MASK              (0x700U)
13920 #define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT             (8U)
13921 /*! SRC
13922  *  0b000..Job Ring 0
13923  *  0b001..Job Ring 1
13924  *  0b010..Job Ring 2
13925  *  0b011..Job Ring 3
13926  *  0b100..RTIC
13927  *  0b101..Reserved
13928  *  0b110..Reserved
13929  *  0b111..Reserved
13930  */
13931 #define CAAM_HT_JQ_CTRL_MS_SRC(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK)
13932 
13933 #define CAAM_HT_JQ_CTRL_MS_JDDS_MASK             (0x4000U)
13934 #define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT            (14U)
13935 /*! JDDS
13936  *  0b1..SEQ DID
13937  *  0b0..Non-SEQ DID
13938  */
13939 #define CAAM_HT_JQ_CTRL_MS_JDDS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK)
13940 
13941 #define CAAM_HT_JQ_CTRL_MS_AMTD_MASK             (0x8000U)
13942 #define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT            (15U)
13943 #define CAAM_HT_JQ_CTRL_MS_AMTD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK)
13944 
13945 #define CAAM_HT_JQ_CTRL_MS_SOB_MASK              (0x10000U)
13946 #define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT             (16U)
13947 #define CAAM_HT_JQ_CTRL_MS_SOB(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK)
13948 
13949 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK         (0x60000U)
13950 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT        (17U)
13951 /*! HT_ERROR
13952  *  0b00..No error
13953  *  0b01..Job Descriptor or Shared Descriptor length error
13954  *  0b10..AXI_error while reading a Job Ring Shared Descriptor or the remainder of a Job Ring Job Descriptor
13955  *  0b11..reserved
13956  */
13957 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK)
13958 
13959 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK       (0x80000U)
13960 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT      (19U)
13961 /*! DWORD_SWAP
13962  *  0b0..DWords are in the order most-significant word, least-significant word.
13963  *  0b1..DWords are in the order least-significant word, most-significant word.
13964  */
13965 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK)
13966 
13967 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK         (0x7C00000U)
13968 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT        (22U)
13969 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK)
13970 
13971 #define CAAM_HT_JQ_CTRL_MS_ILE_MASK              (0x8000000U)
13972 #define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT             (27U)
13973 /*! ILE
13974  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
13975  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
13976  */
13977 #define CAAM_HT_JQ_CTRL_MS_ILE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK)
13978 
13979 #define CAAM_HT_JQ_CTRL_MS_FOUR_MASK             (0x10000000U)
13980 #define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT            (28U)
13981 #define CAAM_HT_JQ_CTRL_MS_FOUR(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK)
13982 
13983 #define CAAM_HT_JQ_CTRL_MS_WHL_MASK              (0x20000000U)
13984 #define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT             (29U)
13985 #define CAAM_HT_JQ_CTRL_MS_WHL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK)
13986 /*! @} */
13987 
13988 /* The count of CAAM_HT_JQ_CTRL_MS */
13989 #define CAAM_HT_JQ_CTRL_MS_COUNT                 (1U)
13990 
13991 /*! @name HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half */
13992 /*! @{ */
13993 
13994 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK         (0xFU)
13995 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT        (0U)
13996 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK)
13997 
13998 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK          (0x10U)
13999 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT         (4U)
14000 /*! PRIM_TZ
14001  *  0b0..TrustZone NonSecureWorld
14002  *  0b1..TrustZone SecureWorld
14003  */
14004 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK)
14005 
14006 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK        (0xFFE0U)
14007 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT       (5U)
14008 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK)
14009 
14010 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK          (0xF0000U)
14011 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT         (16U)
14012 #define CAAM_HT_JQ_CTRL_LS_OUT_DID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK)
14013 
14014 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK         (0xFFE00000U)
14015 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT        (21U)
14016 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK)
14017 /*! @} */
14018 
14019 /* The count of CAAM_HT_JQ_CTRL_LS */
14020 #define CAAM_HT_JQ_CTRL_LS_COUNT                 (1U)
14021 
14022 /*! @name HT_STATUS - Holding Tank Status */
14023 /*! @{ */
14024 
14025 #define CAAM_HT_STATUS_PEND_0_MASK               (0x1U)
14026 #define CAAM_HT_STATUS_PEND_0_SHIFT              (0U)
14027 #define CAAM_HT_STATUS_PEND_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK)
14028 
14029 #define CAAM_HT_STATUS_IN_USE_MASK               (0x40000000U)
14030 #define CAAM_HT_STATUS_IN_USE_SHIFT              (30U)
14031 #define CAAM_HT_STATUS_IN_USE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK)
14032 
14033 #define CAAM_HT_STATUS_BC_MASK                   (0x80000000U)
14034 #define CAAM_HT_STATUS_BC_SHIFT                  (31U)
14035 #define CAAM_HT_STATUS_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK)
14036 /*! @} */
14037 
14038 /* The count of CAAM_HT_STATUS */
14039 #define CAAM_HT_STATUS_COUNT                     (1U)
14040 
14041 /*! @name JQ_DEBUG_SEL - Job Queue Debug Select Register */
14042 /*! @{ */
14043 
14044 #define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK            (0x1U)
14045 #define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT           (0U)
14046 #define CAAM_JQ_DEBUG_SEL_HT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK)
14047 
14048 #define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK            (0x70000U)
14049 #define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT           (16U)
14050 #define CAAM_JQ_DEBUG_SEL_JOB_ID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK)
14051 /*! @} */
14052 
14053 /*! @name JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half */
14054 /*! @{ */
14055 
14056 #define CAAM_JRJIDU_LS_JID00_MASK                (0x1U)
14057 #define CAAM_JRJIDU_LS_JID00_SHIFT               (0U)
14058 #define CAAM_JRJIDU_LS_JID00(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK)
14059 
14060 #define CAAM_JRJIDU_LS_JID01_MASK                (0x2U)
14061 #define CAAM_JRJIDU_LS_JID01_SHIFT               (1U)
14062 #define CAAM_JRJIDU_LS_JID01(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK)
14063 
14064 #define CAAM_JRJIDU_LS_JID02_MASK                (0x4U)
14065 #define CAAM_JRJIDU_LS_JID02_SHIFT               (2U)
14066 #define CAAM_JRJIDU_LS_JID02(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK)
14067 
14068 #define CAAM_JRJIDU_LS_JID03_MASK                (0x8U)
14069 #define CAAM_JRJIDU_LS_JID03_SHIFT               (3U)
14070 #define CAAM_JRJIDU_LS_JID03(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK)
14071 /*! @} */
14072 
14073 /*! @name JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC */
14074 /*! @{ */
14075 
14076 #define CAAM_JRJDJIFBC_BC_MASK                   (0x80000000U)
14077 #define CAAM_JRJDJIFBC_BC_SHIFT                  (31U)
14078 #define CAAM_JRJDJIFBC_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK)
14079 /*! @} */
14080 
14081 /*! @name JRJDJIF - Job Ring Job-Done Job ID FIFO */
14082 /*! @{ */
14083 
14084 #define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK           (0x7U)
14085 #define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT          (0U)
14086 #define CAAM_JRJDJIF_JOB_ID_ENTRY(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK)
14087 /*! @} */
14088 
14089 /*! @name JRJDS1 - Job Ring Job-Done Source 1 */
14090 /*! @{ */
14091 
14092 #define CAAM_JRJDS1_SRC_MASK                     (0x3U)
14093 #define CAAM_JRJDS1_SRC_SHIFT                    (0U)
14094 #define CAAM_JRJDS1_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK)
14095 
14096 #define CAAM_JRJDS1_VALID_MASK                   (0x80000000U)
14097 #define CAAM_JRJDS1_VALID_SHIFT                  (31U)
14098 #define CAAM_JRJDS1_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK)
14099 /*! @} */
14100 
14101 /*! @name JRJDDA - Job Ring Job-Done Descriptor Address 0 Register */
14102 /*! @{ */
14103 
14104 #define CAAM_JRJDDA_JD_ADDR_MASK                 (0xFFFFFFFFFU)
14105 #define CAAM_JRJDDA_JD_ADDR_SHIFT                (0U)
14106 #define CAAM_JRJDDA_JD_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK)
14107 /*! @} */
14108 
14109 /* The count of CAAM_JRJDDA */
14110 #define CAAM_JRJDDA_COUNT                        (1U)
14111 
14112 /*! @name CRNR_MS - CHA Revision Number Register, most-significant half */
14113 /*! @{ */
14114 
14115 #define CAAM_CRNR_MS_CRCRN_MASK                  (0xFU)
14116 #define CAAM_CRNR_MS_CRCRN_SHIFT                 (0U)
14117 #define CAAM_CRNR_MS_CRCRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK)
14118 
14119 #define CAAM_CRNR_MS_SNW9RN_MASK                 (0xF0U)
14120 #define CAAM_CRNR_MS_SNW9RN_SHIFT                (4U)
14121 #define CAAM_CRNR_MS_SNW9RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK)
14122 
14123 #define CAAM_CRNR_MS_ZERN_MASK                   (0xF00U)
14124 #define CAAM_CRNR_MS_ZERN_SHIFT                  (8U)
14125 #define CAAM_CRNR_MS_ZERN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK)
14126 
14127 #define CAAM_CRNR_MS_ZARN_MASK                   (0xF000U)
14128 #define CAAM_CRNR_MS_ZARN_SHIFT                  (12U)
14129 #define CAAM_CRNR_MS_ZARN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK)
14130 
14131 #define CAAM_CRNR_MS_DECORN_MASK                 (0xF000000U)
14132 #define CAAM_CRNR_MS_DECORN_SHIFT                (24U)
14133 #define CAAM_CRNR_MS_DECORN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK)
14134 
14135 #define CAAM_CRNR_MS_JRRN_MASK                   (0xF0000000U)
14136 #define CAAM_CRNR_MS_JRRN_SHIFT                  (28U)
14137 #define CAAM_CRNR_MS_JRRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK)
14138 /*! @} */
14139 
14140 /*! @name CRNR_LS - CHA Revision Number Register, least-significant half */
14141 /*! @{ */
14142 
14143 #define CAAM_CRNR_LS_AESRN_MASK                  (0xFU)
14144 #define CAAM_CRNR_LS_AESRN_SHIFT                 (0U)
14145 #define CAAM_CRNR_LS_AESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK)
14146 
14147 #define CAAM_CRNR_LS_DESRN_MASK                  (0xF0U)
14148 #define CAAM_CRNR_LS_DESRN_SHIFT                 (4U)
14149 #define CAAM_CRNR_LS_DESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK)
14150 
14151 #define CAAM_CRNR_LS_MDRN_MASK                   (0xF000U)
14152 #define CAAM_CRNR_LS_MDRN_SHIFT                  (12U)
14153 #define CAAM_CRNR_LS_MDRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK)
14154 
14155 #define CAAM_CRNR_LS_RNGRN_MASK                  (0xF0000U)
14156 #define CAAM_CRNR_LS_RNGRN_SHIFT                 (16U)
14157 #define CAAM_CRNR_LS_RNGRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK)
14158 
14159 #define CAAM_CRNR_LS_SNW8RN_MASK                 (0xF00000U)
14160 #define CAAM_CRNR_LS_SNW8RN_SHIFT                (20U)
14161 #define CAAM_CRNR_LS_SNW8RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK)
14162 
14163 #define CAAM_CRNR_LS_KASRN_MASK                  (0xF000000U)
14164 #define CAAM_CRNR_LS_KASRN_SHIFT                 (24U)
14165 #define CAAM_CRNR_LS_KASRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK)
14166 
14167 #define CAAM_CRNR_LS_PKRN_MASK                   (0xF0000000U)
14168 #define CAAM_CRNR_LS_PKRN_SHIFT                  (28U)
14169 /*! PKRN
14170  *  0b0000..PKHA-SDv1
14171  *  0b0001..PKHA-SDv2
14172  *  0b0010..PKHA-SDv3
14173  *  0b0011..PKHA-SDv4
14174  */
14175 #define CAAM_CRNR_LS_PKRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK)
14176 /*! @} */
14177 
14178 /*! @name CTPR_MS - Compile Time Parameters Register, most-significant half */
14179 /*! @{ */
14180 
14181 #define CAAM_CTPR_MS_VIRT_EN_INCL_MASK           (0x1U)
14182 #define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT          (0U)
14183 #define CAAM_CTPR_MS_VIRT_EN_INCL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK)
14184 
14185 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK      (0x2U)
14186 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT     (1U)
14187 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK)
14188 
14189 #define CAAM_CTPR_MS_REG_PG_SIZE_MASK            (0x10U)
14190 #define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT           (4U)
14191 #define CAAM_CTPR_MS_REG_PG_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK)
14192 
14193 #define CAAM_CTPR_MS_RNG_I_MASK                  (0x700U)
14194 #define CAAM_CTPR_MS_RNG_I_SHIFT                 (8U)
14195 #define CAAM_CTPR_MS_RNG_I(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK)
14196 
14197 #define CAAM_CTPR_MS_AI_INCL_MASK                (0x800U)
14198 #define CAAM_CTPR_MS_AI_INCL_SHIFT               (11U)
14199 #define CAAM_CTPR_MS_AI_INCL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK)
14200 
14201 #define CAAM_CTPR_MS_DPAA2_MASK                  (0x2000U)
14202 #define CAAM_CTPR_MS_DPAA2_SHIFT                 (13U)
14203 #define CAAM_CTPR_MS_DPAA2(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK)
14204 
14205 #define CAAM_CTPR_MS_IP_CLK_MASK                 (0x4000U)
14206 #define CAAM_CTPR_MS_IP_CLK_SHIFT                (14U)
14207 #define CAAM_CTPR_MS_IP_CLK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK)
14208 
14209 #define CAAM_CTPR_MS_MCFG_BURST_MASK             (0x10000U)
14210 #define CAAM_CTPR_MS_MCFG_BURST_SHIFT            (16U)
14211 #define CAAM_CTPR_MS_MCFG_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK)
14212 
14213 #define CAAM_CTPR_MS_MCFG_PS_MASK                (0x20000U)
14214 #define CAAM_CTPR_MS_MCFG_PS_SHIFT               (17U)
14215 #define CAAM_CTPR_MS_MCFG_PS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK)
14216 
14217 #define CAAM_CTPR_MS_SG8_MASK                    (0x40000U)
14218 #define CAAM_CTPR_MS_SG8_SHIFT                   (18U)
14219 #define CAAM_CTPR_MS_SG8(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK)
14220 
14221 #define CAAM_CTPR_MS_PM_EVT_BUS_MASK             (0x80000U)
14222 #define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT            (19U)
14223 #define CAAM_CTPR_MS_PM_EVT_BUS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK)
14224 
14225 #define CAAM_CTPR_MS_DECO_WD_MASK                (0x100000U)
14226 #define CAAM_CTPR_MS_DECO_WD_SHIFT               (20U)
14227 #define CAAM_CTPR_MS_DECO_WD(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK)
14228 
14229 #define CAAM_CTPR_MS_PC_MASK                     (0x200000U)
14230 #define CAAM_CTPR_MS_PC_SHIFT                    (21U)
14231 #define CAAM_CTPR_MS_PC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK)
14232 
14233 #define CAAM_CTPR_MS_C1C2_MASK                   (0x800000U)
14234 #define CAAM_CTPR_MS_C1C2_SHIFT                  (23U)
14235 #define CAAM_CTPR_MS_C1C2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK)
14236 
14237 #define CAAM_CTPR_MS_ACC_CTL_MASK                (0x1000000U)
14238 #define CAAM_CTPR_MS_ACC_CTL_SHIFT               (24U)
14239 #define CAAM_CTPR_MS_ACC_CTL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK)
14240 
14241 #define CAAM_CTPR_MS_QI_MASK                     (0x2000000U)
14242 #define CAAM_CTPR_MS_QI_SHIFT                    (25U)
14243 #define CAAM_CTPR_MS_QI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK)
14244 
14245 #define CAAM_CTPR_MS_AXI_PRI_MASK                (0x4000000U)
14246 #define CAAM_CTPR_MS_AXI_PRI_SHIFT               (26U)
14247 #define CAAM_CTPR_MS_AXI_PRI(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK)
14248 
14249 #define CAAM_CTPR_MS_AXI_LIODN_MASK              (0x8000000U)
14250 #define CAAM_CTPR_MS_AXI_LIODN_SHIFT             (27U)
14251 #define CAAM_CTPR_MS_AXI_LIODN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK)
14252 
14253 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK         (0xF0000000U)
14254 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT        (28U)
14255 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK)
14256 /*! @} */
14257 
14258 /*! @name CTPR_LS - Compile Time Parameters Register, least-significant half */
14259 /*! @{ */
14260 
14261 #define CAAM_CTPR_LS_KG_DS_MASK                  (0x1U)
14262 #define CAAM_CTPR_LS_KG_DS_SHIFT                 (0U)
14263 /*! KG_DS
14264  *  0b0..CAAM does not implement specialized support for Public Key Generation and Digital Signatures.
14265  *  0b1..CAAM implements specialized support for Public Key Generation and Digital Signatures.
14266  */
14267 #define CAAM_CTPR_LS_KG_DS(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK)
14268 
14269 #define CAAM_CTPR_LS_BLOB_MASK                   (0x2U)
14270 #define CAAM_CTPR_LS_BLOB_SHIFT                  (1U)
14271 /*! BLOB
14272  *  0b0..CAAM does not implement specialized support for encapsulating and decapsulating cryptographic blobs.
14273  *  0b1..CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs.
14274  */
14275 #define CAAM_CTPR_LS_BLOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK)
14276 
14277 #define CAAM_CTPR_LS_WIFI_MASK                   (0x4U)
14278 #define CAAM_CTPR_LS_WIFI_SHIFT                  (2U)
14279 /*! WIFI
14280  *  0b0..CAAM does not implement specialized support for the WIFI protocol.
14281  *  0b1..CAAM implements specialized support for the WIFI protocol.
14282  */
14283 #define CAAM_CTPR_LS_WIFI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK)
14284 
14285 #define CAAM_CTPR_LS_WIMAX_MASK                  (0x8U)
14286 #define CAAM_CTPR_LS_WIMAX_SHIFT                 (3U)
14287 /*! WIMAX
14288  *  0b0..CAAM does not implement specialized support for the WIMAX protocol.
14289  *  0b1..CAAM implements specialized support for the WIMAX protocol.
14290  */
14291 #define CAAM_CTPR_LS_WIMAX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK)
14292 
14293 #define CAAM_CTPR_LS_SRTP_MASK                   (0x10U)
14294 #define CAAM_CTPR_LS_SRTP_SHIFT                  (4U)
14295 /*! SRTP
14296  *  0b0..CAAM does not implement specialized support for the SRTP protocol.
14297  *  0b1..CAAM implements specialized support for the SRTP protocol.
14298  */
14299 #define CAAM_CTPR_LS_SRTP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK)
14300 
14301 #define CAAM_CTPR_LS_IPSEC_MASK                  (0x20U)
14302 #define CAAM_CTPR_LS_IPSEC_SHIFT                 (5U)
14303 /*! IPSEC
14304  *  0b0..CAAM does not implement specialized support for the IPSEC protocol.
14305  *  0b1..CAAM implements specialized support for the IPSEC protocol.
14306  */
14307 #define CAAM_CTPR_LS_IPSEC(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK)
14308 
14309 #define CAAM_CTPR_LS_IKE_MASK                    (0x40U)
14310 #define CAAM_CTPR_LS_IKE_SHIFT                   (6U)
14311 /*! IKE
14312  *  0b0..CAAM does not implement specialized support for the IKE protocol.
14313  *  0b1..CAAM implements specialized support for the IKE protocol.
14314  */
14315 #define CAAM_CTPR_LS_IKE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK)
14316 
14317 #define CAAM_CTPR_LS_SSL_TLS_MASK                (0x80U)
14318 #define CAAM_CTPR_LS_SSL_TLS_SHIFT               (7U)
14319 /*! SSL_TLS
14320  *  0b0..CAAM does not implement specialized support for the SSL and TLS protocols.
14321  *  0b1..CAAM implements specialized support for the SSL and TLS protocols.
14322  */
14323 #define CAAM_CTPR_LS_SSL_TLS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK)
14324 
14325 #define CAAM_CTPR_LS_TLS_PRF_MASK                (0x100U)
14326 #define CAAM_CTPR_LS_TLS_PRF_SHIFT               (8U)
14327 /*! TLS_PRF
14328  *  0b0..CAAM does not implement specialized support for the TLS protocol pseudo-random function.
14329  *  0b1..CAAM implements specialized support for the TLS protocol pseudo-random function.
14330  */
14331 #define CAAM_CTPR_LS_TLS_PRF(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK)
14332 
14333 #define CAAM_CTPR_LS_MACSEC_MASK                 (0x200U)
14334 #define CAAM_CTPR_LS_MACSEC_SHIFT                (9U)
14335 /*! MACSEC
14336  *  0b0..CAAM does not implement specialized support for the MACSEC protocol.
14337  *  0b1..CAAM implements specialized support for the MACSEC protocol.
14338  */
14339 #define CAAM_CTPR_LS_MACSEC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK)
14340 
14341 #define CAAM_CTPR_LS_RSA_MASK                    (0x400U)
14342 #define CAAM_CTPR_LS_RSA_SHIFT                   (10U)
14343 /*! RSA
14344  *  0b0..CAAM does not implement specialized support for RSA encrypt and decrypt operations.
14345  *  0b1..CAAM implements specialized support for RSA encrypt and decrypt operations.
14346  */
14347 #define CAAM_CTPR_LS_RSA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK)
14348 
14349 #define CAAM_CTPR_LS_P3G_LTE_MASK                (0x800U)
14350 #define CAAM_CTPR_LS_P3G_LTE_SHIFT               (11U)
14351 /*! P3G_LTE
14352  *  0b0..CAAM does not implement specialized support for 3G and LTE protocols.
14353  *  0b1..CAAM implements specialized support for 3G and LTE protocols.
14354  */
14355 #define CAAM_CTPR_LS_P3G_LTE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK)
14356 
14357 #define CAAM_CTPR_LS_DBL_CRC_MASK                (0x1000U)
14358 #define CAAM_CTPR_LS_DBL_CRC_SHIFT               (12U)
14359 /*! DBL_CRC
14360  *  0b0..CAAM does not implement specialized support for Double CRC.
14361  *  0b1..CAAM implements specialized support for Double CRC.
14362  */
14363 #define CAAM_CTPR_LS_DBL_CRC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK)
14364 
14365 #define CAAM_CTPR_LS_MAN_PROT_MASK               (0x2000U)
14366 #define CAAM_CTPR_LS_MAN_PROT_SHIFT              (13U)
14367 /*! MAN_PROT
14368  *  0b0..CAAM does not implement Manufacturing Protection functions.
14369  *  0b1..CAAM implements Manufacturing Protection functions.
14370  */
14371 #define CAAM_CTPR_LS_MAN_PROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK)
14372 
14373 #define CAAM_CTPR_LS_DKP_MASK                    (0x4000U)
14374 #define CAAM_CTPR_LS_DKP_SHIFT                   (14U)
14375 /*! DKP
14376  *  0b0..CAAM does not implement the Derived Key Protocol.
14377  *  0b1..CAAM implements the Derived Key Protocol.
14378  */
14379 #define CAAM_CTPR_LS_DKP(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK)
14380 /*! @} */
14381 
14382 /*! @name SMSTA - Secure Memory Status Register */
14383 /*! @{ */
14384 
14385 #define CAAM_SMSTA_STATE_MASK                    (0xFU)
14386 #define CAAM_SMSTA_STATE_SHIFT                   (0U)
14387 /*! STATE
14388  *  0b0000..Reset State
14389  *  0b0001..Initialize State
14390  *  0b0010..Normal State
14391  *  0b0011..Fail State
14392  */
14393 #define CAAM_SMSTA_STATE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK)
14394 
14395 #define CAAM_SMSTA_ACCERR_MASK                   (0xF0U)
14396 #define CAAM_SMSTA_ACCERR_SHIFT                  (4U)
14397 /*! ACCERR
14398  *  0b0000..No error occurred
14399  *  0b0001..A bus transaction attempted to access a page in Secure Memory, but the page was not allocated to any partition.
14400  *  0b0010..A bus transaction attempted to access a partition, but the transaction's TrustZone World, DID was not
14401  *          granted access to the partition in the partition's SMAG2/1JR registers.
14402  *  0b0011..A bus transaction attempted to read, but reads from this partition are not allowed.
14403  *  0b0100..A bus transaction attempted to write, but writes to this partition are not allowed.
14404  *  0b0110..A bus transaction attempted a non-key read, but the only reads permitted from this partition are key reads.
14405  *  0b1001..Secure Memory Blob import or export was attempted, but Secure Memory Blob access is not allowed for this partition.
14406  *  0b1010..A Descriptor attempted a Secure Memory Blob import or export, but not all of the pages referenced were from the same partition.
14407  *  0b1011..A memory access was directed to Secure Memory, but the specified address is not implemented in Secure
14408  *          Memory. The address was either outside the address range occupied by Secure Memory, or was within an
14409  *          unimplemented portion of the 4kbyte address block occupied by a 1Kbyte or 2Kbyte Secure Memory page.
14410  *  0b1100..A bus transaction was attempted, but the burst would have crossed a page boundary.
14411  *  0b1101..An attempt was made to access a page while it was still being initialized.
14412  */
14413 #define CAAM_SMSTA_ACCERR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK)
14414 
14415 #define CAAM_SMSTA_DID_MASK                      (0xF00U)
14416 #define CAAM_SMSTA_DID_SHIFT                     (8U)
14417 #define CAAM_SMSTA_DID(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK)
14418 
14419 #define CAAM_SMSTA_NS_MASK                       (0x1000U)
14420 #define CAAM_SMSTA_NS_SHIFT                      (12U)
14421 #define CAAM_SMSTA_NS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK)
14422 
14423 #define CAAM_SMSTA_SMR_WP_MASK                   (0x8000U)
14424 #define CAAM_SMSTA_SMR_WP_SHIFT                  (15U)
14425 #define CAAM_SMSTA_SMR_WP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK)
14426 
14427 #define CAAM_SMSTA_PAGE_MASK                     (0x7FF0000U)
14428 #define CAAM_SMSTA_PAGE_SHIFT                    (16U)
14429 #define CAAM_SMSTA_PAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK)
14430 
14431 #define CAAM_SMSTA_PART_MASK                     (0xF0000000U)
14432 #define CAAM_SMSTA_PART_SHIFT                    (28U)
14433 #define CAAM_SMSTA_PART(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK)
14434 /*! @} */
14435 
14436 /*! @name SMPO - Secure Memory Partition Owners Register */
14437 /*! @{ */
14438 
14439 #define CAAM_SMPO_PO0_MASK                       (0x3U)
14440 #define CAAM_SMPO_PO0_SHIFT                      (0U)
14441 /*! PO0
14442  *  0b00..Available; Unowned. A Job Ring owner may claim partition 0 by writing to the appropriate SMAPJR register
14443  *        address alias. Note that the entire register will return all 0s if read by a entity that does not own
14444  *        the Job Ring associated with the SMPO address alias that was read.
14445  *  0b01..Partition 0 does not exist in this version
14446  *  0b10..Another entity owns partition 0. Partition 0 is unavailable to the reader. If the reader attempts to
14447  *        de-allocate partition 0 or write to the SMAPJR register or SMAGJR register for partition 0 or allocate a
14448  *        page to or de-allocate a page from partition 0 the command will be ignored. (Note that if a CSP partition is
14449  *        de-allocated, all entities (including the owner that de-allocated the partition) will see a 0b10 value
14450  *        for that partition until all its pages have been zeroized.)
14451  *  0b11..The entity that read the SMPO register owns partition 0. Ownership is claimed when the access
14452  *        permissions register (SMAPJR) of an available partition is first written.
14453  */
14454 #define CAAM_SMPO_PO0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK)
14455 
14456 #define CAAM_SMPO_PO1_MASK                       (0xCU)
14457 #define CAAM_SMPO_PO1_SHIFT                      (2U)
14458 #define CAAM_SMPO_PO1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK)
14459 
14460 #define CAAM_SMPO_PO2_MASK                       (0x30U)
14461 #define CAAM_SMPO_PO2_SHIFT                      (4U)
14462 #define CAAM_SMPO_PO2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK)
14463 
14464 #define CAAM_SMPO_PO3_MASK                       (0xC0U)
14465 #define CAAM_SMPO_PO3_SHIFT                      (6U)
14466 #define CAAM_SMPO_PO3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK)
14467 
14468 #define CAAM_SMPO_PO4_MASK                       (0x300U)
14469 #define CAAM_SMPO_PO4_SHIFT                      (8U)
14470 #define CAAM_SMPO_PO4(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK)
14471 
14472 #define CAAM_SMPO_PO5_MASK                       (0xC00U)
14473 #define CAAM_SMPO_PO5_SHIFT                      (10U)
14474 #define CAAM_SMPO_PO5(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK)
14475 
14476 #define CAAM_SMPO_PO6_MASK                       (0x3000U)
14477 #define CAAM_SMPO_PO6_SHIFT                      (12U)
14478 #define CAAM_SMPO_PO6(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK)
14479 
14480 #define CAAM_SMPO_PO7_MASK                       (0xC000U)
14481 #define CAAM_SMPO_PO7_SHIFT                      (14U)
14482 #define CAAM_SMPO_PO7(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK)
14483 
14484 #define CAAM_SMPO_PO8_MASK                       (0x30000U)
14485 #define CAAM_SMPO_PO8_SHIFT                      (16U)
14486 #define CAAM_SMPO_PO8(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK)
14487 
14488 #define CAAM_SMPO_PO9_MASK                       (0xC0000U)
14489 #define CAAM_SMPO_PO9_SHIFT                      (18U)
14490 #define CAAM_SMPO_PO9(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK)
14491 
14492 #define CAAM_SMPO_PO10_MASK                      (0x300000U)
14493 #define CAAM_SMPO_PO10_SHIFT                     (20U)
14494 #define CAAM_SMPO_PO10(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK)
14495 
14496 #define CAAM_SMPO_PO11_MASK                      (0xC00000U)
14497 #define CAAM_SMPO_PO11_SHIFT                     (22U)
14498 #define CAAM_SMPO_PO11(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK)
14499 
14500 #define CAAM_SMPO_PO12_MASK                      (0x3000000U)
14501 #define CAAM_SMPO_PO12_SHIFT                     (24U)
14502 #define CAAM_SMPO_PO12(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK)
14503 
14504 #define CAAM_SMPO_PO13_MASK                      (0xC000000U)
14505 #define CAAM_SMPO_PO13_SHIFT                     (26U)
14506 #define CAAM_SMPO_PO13(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK)
14507 
14508 #define CAAM_SMPO_PO14_MASK                      (0x30000000U)
14509 #define CAAM_SMPO_PO14_SHIFT                     (28U)
14510 #define CAAM_SMPO_PO14(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK)
14511 
14512 #define CAAM_SMPO_PO15_MASK                      (0xC0000000U)
14513 #define CAAM_SMPO_PO15_SHIFT                     (30U)
14514 #define CAAM_SMPO_PO15(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK)
14515 /*! @} */
14516 
14517 /*! @name FAR - Fault Address Register */
14518 /*! @{ */
14519 
14520 #define CAAM_FAR_FAR_MASK                        (0xFFFFFFFFFU)
14521 #define CAAM_FAR_FAR_SHIFT                       (0U)
14522 #define CAAM_FAR_FAR(x)                          (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK)
14523 /*! @} */
14524 
14525 /*! @name FADID - Fault Address DID Register */
14526 /*! @{ */
14527 
14528 #define CAAM_FADID_FDID_MASK                     (0xFU)
14529 #define CAAM_FADID_FDID_SHIFT                    (0U)
14530 #define CAAM_FADID_FDID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK)
14531 
14532 #define CAAM_FADID_FNS_MASK                      (0x10U)
14533 #define CAAM_FADID_FNS_SHIFT                     (4U)
14534 #define CAAM_FADID_FNS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK)
14535 
14536 #define CAAM_FADID_FICID_MASK                    (0xFFE0U)
14537 #define CAAM_FADID_FICID_SHIFT                   (5U)
14538 #define CAAM_FADID_FICID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK)
14539 /*! @} */
14540 
14541 /*! @name FADR - Fault Address Detail Register */
14542 /*! @{ */
14543 
14544 #define CAAM_FADR_FSZ_MASK                       (0x7FU)
14545 #define CAAM_FADR_FSZ_SHIFT                      (0U)
14546 #define CAAM_FADR_FSZ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK)
14547 
14548 #define CAAM_FADR_TYP_MASK                       (0x80U)
14549 #define CAAM_FADR_TYP_SHIFT                      (7U)
14550 /*! TYP
14551  *  0b0..Read.
14552  *  0b1..Write.
14553  */
14554 #define CAAM_FADR_TYP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK)
14555 
14556 #define CAAM_FADR_BLKID_MASK                     (0xF00U)
14557 #define CAAM_FADR_BLKID_SHIFT                    (8U)
14558 /*! BLKID
14559  *  0b0100..job queue controller Burst Buffer
14560  *  0b0101..One of the Job Rings (see JSRC field)
14561  *  0b1000..DECO0
14562  */
14563 #define CAAM_FADR_BLKID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK)
14564 
14565 #define CAAM_FADR_JSRC_MASK                      (0x7000U)
14566 #define CAAM_FADR_JSRC_SHIFT                     (12U)
14567 /*! JSRC
14568  *  0b000..Job Ring 0
14569  *  0b001..Job Ring 1
14570  *  0b010..Job Ring 2
14571  *  0b011..Job Ring 3
14572  *  0b100..RTIC
14573  *  0b101..reserved
14574  *  0b110..reserved
14575  *  0b111..reserved
14576  */
14577 #define CAAM_FADR_JSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK)
14578 
14579 #define CAAM_FADR_DTYP_MASK                      (0x8000U)
14580 #define CAAM_FADR_DTYP_SHIFT                     (15U)
14581 /*! DTYP
14582  *  0b0..message data
14583  *  0b1..control data
14584  */
14585 #define CAAM_FADR_DTYP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK)
14586 
14587 #define CAAM_FADR_FSZ_EXT_MASK                   (0x70000U)
14588 #define CAAM_FADR_FSZ_EXT_SHIFT                  (16U)
14589 #define CAAM_FADR_FSZ_EXT(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK)
14590 
14591 #define CAAM_FADR_FKMOD_MASK                     (0x1000000U)
14592 #define CAAM_FADR_FKMOD_SHIFT                    (24U)
14593 /*! FKMOD
14594  *  0b0..CAAM DMA was not attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14595  *  0b1..CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14596  */
14597 #define CAAM_FADR_FKMOD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK)
14598 
14599 #define CAAM_FADR_FKEY_MASK                      (0x2000000U)
14600 #define CAAM_FADR_FKEY_SHIFT                     (25U)
14601 /*! FKEY
14602  *  0b0..CAAM DMA was not attempting to perform a key read from Secure Memory at the time of the DMA error.
14603  *  0b1..CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error.
14604  */
14605 #define CAAM_FADR_FKEY(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK)
14606 
14607 #define CAAM_FADR_FTDSC_MASK                     (0x4000000U)
14608 #define CAAM_FADR_FTDSC_SHIFT                    (26U)
14609 /*! FTDSC
14610  *  0b0..CAAM DMA was not executing a Trusted Descriptor at the time of the DMA error.
14611  *  0b1..CAAM DMA was executing a Trusted Descriptor at the time of the DMA error.
14612  */
14613 #define CAAM_FADR_FTDSC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK)
14614 
14615 #define CAAM_FADR_FBNDG_MASK                     (0x8000000U)
14616 #define CAAM_FADR_FBNDG_SHIFT                    (27U)
14617 /*! FBNDG
14618  *  0b0..CAAM DMA was not reading access permissions from a Secure Memory partition at the time of the DMA error.
14619  *  0b1..CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error.
14620  */
14621 #define CAAM_FADR_FBNDG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK)
14622 
14623 #define CAAM_FADR_FNS_MASK                       (0x10000000U)
14624 #define CAAM_FADR_FNS_SHIFT                      (28U)
14625 /*! FNS
14626  *  0b0..CAAM DMA was asserting ns=0 at the time of the DMA error.
14627  *  0b1..CAAM DMA was asserting ns=1 at the time of the DMA error.
14628  */
14629 #define CAAM_FADR_FNS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK)
14630 
14631 #define CAAM_FADR_FERR_MASK                      (0xC0000000U)
14632 #define CAAM_FADR_FERR_SHIFT                     (30U)
14633 /*! FERR
14634  *  0b00..OKAY - Normal Access
14635  *  0b01..Reserved
14636  *  0b10..SLVERR - Slave Error
14637  *  0b11..DECERR - Decode Error
14638  */
14639 #define CAAM_FADR_FERR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK)
14640 /*! @} */
14641 
14642 /*! @name CSTA - CAAM Status Register */
14643 /*! @{ */
14644 
14645 #define CAAM_CSTA_BSY_MASK                       (0x1U)
14646 #define CAAM_CSTA_BSY_SHIFT                      (0U)
14647 #define CAAM_CSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK)
14648 
14649 #define CAAM_CSTA_IDLE_MASK                      (0x2U)
14650 #define CAAM_CSTA_IDLE_SHIFT                     (1U)
14651 #define CAAM_CSTA_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK)
14652 
14653 #define CAAM_CSTA_TRNG_IDLE_MASK                 (0x4U)
14654 #define CAAM_CSTA_TRNG_IDLE_SHIFT                (2U)
14655 #define CAAM_CSTA_TRNG_IDLE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK)
14656 
14657 #define CAAM_CSTA_MOO_MASK                       (0x300U)
14658 #define CAAM_CSTA_MOO_SHIFT                      (8U)
14659 /*! MOO
14660  *  0b00..Non-Secure
14661  *  0b01..Secure
14662  *  0b10..Trusted
14663  *  0b11..Fail
14664  */
14665 #define CAAM_CSTA_MOO(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK)
14666 
14667 #define CAAM_CSTA_PLEND_MASK                     (0x400U)
14668 #define CAAM_CSTA_PLEND_SHIFT                    (10U)
14669 /*! PLEND
14670  *  0b0..Platform default is Little Endian
14671  *  0b1..Platform default is Big Endian
14672  */
14673 #define CAAM_CSTA_PLEND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK)
14674 /*! @} */
14675 
14676 /*! @name SMVID_MS - Secure Memory Version ID Register, most-significant half */
14677 /*! @{ */
14678 
14679 #define CAAM_SMVID_MS_NPAG_MASK                  (0x3FFU)
14680 #define CAAM_SMVID_MS_NPAG_SHIFT                 (0U)
14681 #define CAAM_SMVID_MS_NPAG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK)
14682 
14683 #define CAAM_SMVID_MS_NPRT_MASK                  (0xF000U)
14684 #define CAAM_SMVID_MS_NPRT_SHIFT                 (12U)
14685 #define CAAM_SMVID_MS_NPRT(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK)
14686 
14687 #define CAAM_SMVID_MS_MAX_NPAG_MASK              (0x3FF0000U)
14688 #define CAAM_SMVID_MS_MAX_NPAG_SHIFT             (16U)
14689 #define CAAM_SMVID_MS_MAX_NPAG(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK)
14690 /*! @} */
14691 
14692 /*! @name SMVID_LS - Secure Memory Version ID Register, least-significant half */
14693 /*! @{ */
14694 
14695 #define CAAM_SMVID_LS_SMNV_MASK                  (0xFFU)
14696 #define CAAM_SMVID_LS_SMNV_SHIFT                 (0U)
14697 #define CAAM_SMVID_LS_SMNV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK)
14698 
14699 #define CAAM_SMVID_LS_SMJV_MASK                  (0xFF00U)
14700 #define CAAM_SMVID_LS_SMJV_SHIFT                 (8U)
14701 #define CAAM_SMVID_LS_SMJV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK)
14702 
14703 #define CAAM_SMVID_LS_PSIZ_MASK                  (0x70000U)
14704 #define CAAM_SMVID_LS_PSIZ_SHIFT                 (16U)
14705 #define CAAM_SMVID_LS_PSIZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK)
14706 /*! @} */
14707 
14708 /*! @name RVID - RTIC Version ID Register */
14709 /*! @{ */
14710 
14711 #define CAAM_RVID_RMNV_MASK                      (0xFFU)
14712 #define CAAM_RVID_RMNV_SHIFT                     (0U)
14713 #define CAAM_RVID_RMNV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK)
14714 
14715 #define CAAM_RVID_RMJV_MASK                      (0xFF00U)
14716 #define CAAM_RVID_RMJV_SHIFT                     (8U)
14717 #define CAAM_RVID_RMJV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK)
14718 
14719 #define CAAM_RVID_SHA_256_MASK                   (0x20000U)
14720 #define CAAM_RVID_SHA_256_SHIFT                  (17U)
14721 /*! SHA_256
14722  *  0b0..RTIC cannot use the SHA-256 hashing algorithm.
14723  *  0b1..RTIC can use the SHA-256 hashing algorithm.
14724  */
14725 #define CAAM_RVID_SHA_256(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK)
14726 
14727 #define CAAM_RVID_SHA_512_MASK                   (0x80000U)
14728 #define CAAM_RVID_SHA_512_SHIFT                  (19U)
14729 /*! SHA_512
14730  *  0b0..RTIC cannot use the SHA-512 hashing algorithm.
14731  *  0b1..RTIC can use the SHA-512 hashing algorithm.
14732  */
14733 #define CAAM_RVID_SHA_512(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK)
14734 
14735 #define CAAM_RVID_MA_MASK                        (0x1000000U)
14736 #define CAAM_RVID_MA_SHIFT                       (24U)
14737 #define CAAM_RVID_MA(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK)
14738 
14739 #define CAAM_RVID_MB_MASK                        (0x2000000U)
14740 #define CAAM_RVID_MB_SHIFT                       (25U)
14741 #define CAAM_RVID_MB(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK)
14742 
14743 #define CAAM_RVID_MC_MASK                        (0x4000000U)
14744 #define CAAM_RVID_MC_SHIFT                       (26U)
14745 #define CAAM_RVID_MC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK)
14746 
14747 #define CAAM_RVID_MD_MASK                        (0x8000000U)
14748 #define CAAM_RVID_MD_SHIFT                       (27U)
14749 #define CAAM_RVID_MD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK)
14750 /*! @} */
14751 
14752 /*! @name CCBVID - CHA Cluster Block Version ID Register */
14753 /*! @{ */
14754 
14755 #define CAAM_CCBVID_AMNV_MASK                    (0xFFU)
14756 #define CAAM_CCBVID_AMNV_SHIFT                   (0U)
14757 #define CAAM_CCBVID_AMNV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK)
14758 
14759 #define CAAM_CCBVID_AMJV_MASK                    (0xFF00U)
14760 #define CAAM_CCBVID_AMJV_SHIFT                   (8U)
14761 #define CAAM_CCBVID_AMJV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK)
14762 
14763 #define CAAM_CCBVID_CAAM_ERA_MASK                (0xFF000000U)
14764 #define CAAM_CCBVID_CAAM_ERA_SHIFT               (24U)
14765 #define CAAM_CCBVID_CAAM_ERA(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK)
14766 /*! @} */
14767 
14768 /*! @name CHAVID_MS - CHA Version ID Register, most-significant half */
14769 /*! @{ */
14770 
14771 #define CAAM_CHAVID_MS_CRCVID_MASK               (0xFU)
14772 #define CAAM_CHAVID_MS_CRCVID_SHIFT              (0U)
14773 #define CAAM_CHAVID_MS_CRCVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK)
14774 
14775 #define CAAM_CHAVID_MS_SNW9VID_MASK              (0xF0U)
14776 #define CAAM_CHAVID_MS_SNW9VID_SHIFT             (4U)
14777 #define CAAM_CHAVID_MS_SNW9VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK)
14778 
14779 #define CAAM_CHAVID_MS_ZEVID_MASK                (0xF00U)
14780 #define CAAM_CHAVID_MS_ZEVID_SHIFT               (8U)
14781 #define CAAM_CHAVID_MS_ZEVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK)
14782 
14783 #define CAAM_CHAVID_MS_ZAVID_MASK                (0xF000U)
14784 #define CAAM_CHAVID_MS_ZAVID_SHIFT               (12U)
14785 #define CAAM_CHAVID_MS_ZAVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK)
14786 
14787 #define CAAM_CHAVID_MS_DECOVID_MASK              (0xF000000U)
14788 #define CAAM_CHAVID_MS_DECOVID_SHIFT             (24U)
14789 #define CAAM_CHAVID_MS_DECOVID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK)
14790 
14791 #define CAAM_CHAVID_MS_JRVID_MASK                (0xF0000000U)
14792 #define CAAM_CHAVID_MS_JRVID_SHIFT               (28U)
14793 #define CAAM_CHAVID_MS_JRVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK)
14794 /*! @} */
14795 
14796 /*! @name CHAVID_LS - CHA Version ID Register, least-significant half */
14797 /*! @{ */
14798 
14799 #define CAAM_CHAVID_LS_AESVID_MASK               (0xFU)
14800 #define CAAM_CHAVID_LS_AESVID_SHIFT              (0U)
14801 /*! AESVID
14802  *  0b0100..High-performance AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, CBCXCBC, CTRXCBC, XTS, and GCM modes
14803  *  0b0011..Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes
14804  */
14805 #define CAAM_CHAVID_LS_AESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK)
14806 
14807 #define CAAM_CHAVID_LS_DESVID_MASK               (0xF0U)
14808 #define CAAM_CHAVID_LS_DESVID_SHIFT              (4U)
14809 #define CAAM_CHAVID_LS_DESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK)
14810 
14811 #define CAAM_CHAVID_LS_MDVID_MASK                (0xF000U)
14812 #define CAAM_CHAVID_LS_MDVID_SHIFT               (12U)
14813 /*! MDVID
14814  *  0b0000..Low-power MDHA, with SHA-1, SHA-256, SHA 224, MD5 and HMAC
14815  *  0b0001..Low-power MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5 and HMAC
14816  *  0b0010..Medium-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14817  *  0b0011..High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14818  */
14819 #define CAAM_CHAVID_LS_MDVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK)
14820 
14821 #define CAAM_CHAVID_LS_RNGVID_MASK               (0xF0000U)
14822 #define CAAM_CHAVID_LS_RNGVID_SHIFT              (16U)
14823 /*! RNGVID
14824  *  0b0010..RNGB
14825  *  0b0100..RNG4
14826  */
14827 #define CAAM_CHAVID_LS_RNGVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK)
14828 
14829 #define CAAM_CHAVID_LS_SNW8VID_MASK              (0xF00000U)
14830 #define CAAM_CHAVID_LS_SNW8VID_SHIFT             (20U)
14831 #define CAAM_CHAVID_LS_SNW8VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
14832 
14833 #define CAAM_CHAVID_LS_KASVID_MASK               (0xF000000U)
14834 #define CAAM_CHAVID_LS_KASVID_SHIFT              (24U)
14835 #define CAAM_CHAVID_LS_KASVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK)
14836 
14837 #define CAAM_CHAVID_LS_PKVID_MASK                (0xF0000000U)
14838 #define CAAM_CHAVID_LS_PKVID_SHIFT               (28U)
14839 /*! PKVID
14840  *  0b0000..PKHA-XT (32-bit); minimum modulus five bytes
14841  *  0b0001..PKHA-SD (32-bit)
14842  *  0b0010..PKHA-SD (64-bit)
14843  *  0b0011..PKHA-SD (128-bit)
14844  */
14845 #define CAAM_CHAVID_LS_PKVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK)
14846 /*! @} */
14847 
14848 /*! @name CHANUM_MS - CHA Number Register, most-significant half */
14849 /*! @{ */
14850 
14851 #define CAAM_CHANUM_MS_CRCNUM_MASK               (0xFU)
14852 #define CAAM_CHANUM_MS_CRCNUM_SHIFT              (0U)
14853 #define CAAM_CHANUM_MS_CRCNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK)
14854 
14855 #define CAAM_CHANUM_MS_SNW9NUM_MASK              (0xF0U)
14856 #define CAAM_CHANUM_MS_SNW9NUM_SHIFT             (4U)
14857 #define CAAM_CHANUM_MS_SNW9NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK)
14858 
14859 #define CAAM_CHANUM_MS_ZENUM_MASK                (0xF00U)
14860 #define CAAM_CHANUM_MS_ZENUM_SHIFT               (8U)
14861 #define CAAM_CHANUM_MS_ZENUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK)
14862 
14863 #define CAAM_CHANUM_MS_ZANUM_MASK                (0xF000U)
14864 #define CAAM_CHANUM_MS_ZANUM_SHIFT               (12U)
14865 #define CAAM_CHANUM_MS_ZANUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK)
14866 
14867 #define CAAM_CHANUM_MS_DECONUM_MASK              (0xF000000U)
14868 #define CAAM_CHANUM_MS_DECONUM_SHIFT             (24U)
14869 #define CAAM_CHANUM_MS_DECONUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK)
14870 
14871 #define CAAM_CHANUM_MS_JRNUM_MASK                (0xF0000000U)
14872 #define CAAM_CHANUM_MS_JRNUM_SHIFT               (28U)
14873 #define CAAM_CHANUM_MS_JRNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK)
14874 /*! @} */
14875 
14876 /*! @name CHANUM_LS - CHA Number Register, least-significant half */
14877 /*! @{ */
14878 
14879 #define CAAM_CHANUM_LS_AESNUM_MASK               (0xFU)
14880 #define CAAM_CHANUM_LS_AESNUM_SHIFT              (0U)
14881 #define CAAM_CHANUM_LS_AESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK)
14882 
14883 #define CAAM_CHANUM_LS_DESNUM_MASK               (0xF0U)
14884 #define CAAM_CHANUM_LS_DESNUM_SHIFT              (4U)
14885 #define CAAM_CHANUM_LS_DESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK)
14886 
14887 #define CAAM_CHANUM_LS_ARC4NUM_MASK              (0xF00U)
14888 #define CAAM_CHANUM_LS_ARC4NUM_SHIFT             (8U)
14889 #define CAAM_CHANUM_LS_ARC4NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK)
14890 
14891 #define CAAM_CHANUM_LS_MDNUM_MASK                (0xF000U)
14892 #define CAAM_CHANUM_LS_MDNUM_SHIFT               (12U)
14893 #define CAAM_CHANUM_LS_MDNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK)
14894 
14895 #define CAAM_CHANUM_LS_RNGNUM_MASK               (0xF0000U)
14896 #define CAAM_CHANUM_LS_RNGNUM_SHIFT              (16U)
14897 #define CAAM_CHANUM_LS_RNGNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK)
14898 
14899 #define CAAM_CHANUM_LS_SNW8NUM_MASK              (0xF00000U)
14900 #define CAAM_CHANUM_LS_SNW8NUM_SHIFT             (20U)
14901 #define CAAM_CHANUM_LS_SNW8NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK)
14902 
14903 #define CAAM_CHANUM_LS_KASNUM_MASK               (0xF000000U)
14904 #define CAAM_CHANUM_LS_KASNUM_SHIFT              (24U)
14905 #define CAAM_CHANUM_LS_KASNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK)
14906 
14907 #define CAAM_CHANUM_LS_PKNUM_MASK                (0xF0000000U)
14908 #define CAAM_CHANUM_LS_PKNUM_SHIFT               (28U)
14909 #define CAAM_CHANUM_LS_PKNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK)
14910 /*! @} */
14911 
14912 /*! @name IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 */
14913 /*! @{ */
14914 
14915 #define CAAM_IRBAR_JR_IRBA_MASK                  (0xFFFFFFFFFU)
14916 #define CAAM_IRBAR_JR_IRBA_SHIFT                 (0U)
14917 #define CAAM_IRBAR_JR_IRBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK)
14918 /*! @} */
14919 
14920 /* The count of CAAM_IRBAR_JR */
14921 #define CAAM_IRBAR_JR_COUNT                      (4U)
14922 
14923 /*! @name IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 */
14924 /*! @{ */
14925 
14926 #define CAAM_IRSR_JR_IRS_MASK                    (0x3FFU)
14927 #define CAAM_IRSR_JR_IRS_SHIFT                   (0U)
14928 #define CAAM_IRSR_JR_IRS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK)
14929 /*! @} */
14930 
14931 /* The count of CAAM_IRSR_JR */
14932 #define CAAM_IRSR_JR_COUNT                       (4U)
14933 
14934 /*! @name IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 */
14935 /*! @{ */
14936 
14937 #define CAAM_IRSAR_JR_IRSA_MASK                  (0x3FFU)
14938 #define CAAM_IRSAR_JR_IRSA_SHIFT                 (0U)
14939 #define CAAM_IRSAR_JR_IRSA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK)
14940 /*! @} */
14941 
14942 /* The count of CAAM_IRSAR_JR */
14943 #define CAAM_IRSAR_JR_COUNT                      (4U)
14944 
14945 /*! @name IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 */
14946 /*! @{ */
14947 
14948 #define CAAM_IRJAR_JR_IRJA_MASK                  (0x3FFU)
14949 #define CAAM_IRJAR_JR_IRJA_SHIFT                 (0U)
14950 #define CAAM_IRJAR_JR_IRJA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK)
14951 /*! @} */
14952 
14953 /* The count of CAAM_IRJAR_JR */
14954 #define CAAM_IRJAR_JR_COUNT                      (4U)
14955 
14956 /*! @name ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 */
14957 /*! @{ */
14958 
14959 #define CAAM_ORBAR_JR_ORBA_MASK                  (0xFFFFFFFFFU)
14960 #define CAAM_ORBAR_JR_ORBA_SHIFT                 (0U)
14961 #define CAAM_ORBAR_JR_ORBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK)
14962 /*! @} */
14963 
14964 /* The count of CAAM_ORBAR_JR */
14965 #define CAAM_ORBAR_JR_COUNT                      (4U)
14966 
14967 /*! @name ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 */
14968 /*! @{ */
14969 
14970 #define CAAM_ORSR_JR_ORS_MASK                    (0x3FFU)
14971 #define CAAM_ORSR_JR_ORS_SHIFT                   (0U)
14972 #define CAAM_ORSR_JR_ORS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK)
14973 /*! @} */
14974 
14975 /* The count of CAAM_ORSR_JR */
14976 #define CAAM_ORSR_JR_COUNT                       (4U)
14977 
14978 /*! @name ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 */
14979 /*! @{ */
14980 
14981 #define CAAM_ORJRR_JR_ORJR_MASK                  (0x3FFU)
14982 #define CAAM_ORJRR_JR_ORJR_SHIFT                 (0U)
14983 #define CAAM_ORJRR_JR_ORJR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK)
14984 /*! @} */
14985 
14986 /* The count of CAAM_ORJRR_JR */
14987 #define CAAM_ORJRR_JR_COUNT                      (4U)
14988 
14989 /*! @name ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 */
14990 /*! @{ */
14991 
14992 #define CAAM_ORSFR_JR_ORSF_MASK                  (0x3FFU)
14993 #define CAAM_ORSFR_JR_ORSF_SHIFT                 (0U)
14994 #define CAAM_ORSFR_JR_ORSF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK)
14995 /*! @} */
14996 
14997 /* The count of CAAM_ORSFR_JR */
14998 #define CAAM_ORSFR_JR_COUNT                      (4U)
14999 
15000 /*! @name JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 */
15001 /*! @{ */
15002 
15003 #define CAAM_JRSTAR_JR_SSED_MASK                 (0xFFFFFFFU)
15004 #define CAAM_JRSTAR_JR_SSED_SHIFT                (0U)
15005 #define CAAM_JRSTAR_JR_SSED(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK)
15006 
15007 #define CAAM_JRSTAR_JR_SSRC_MASK                 (0xF0000000U)
15008 #define CAAM_JRSTAR_JR_SSRC_SHIFT                (28U)
15009 /*! SSRC
15010  *  0b0000..No Status Source (No Error or Status Reported)
15011  *  0b0001..Reserved
15012  *  0b0010..CCB Status Source (CCB Error Reported)
15013  *  0b0011..Jump Halt User Status Source (User-Provided Status Reported)
15014  *  0b0100..DECO Status Source (DECO Error Reported)
15015  *  0b0101..Reserved
15016  *  0b0110..Job Ring Status Source (Job Ring Error Reported)
15017  *  0b0111..Jump Halt Condition Codes (Condition Code Status Reported)
15018  */
15019 #define CAAM_JRSTAR_JR_SSRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK)
15020 /*! @} */
15021 
15022 /* The count of CAAM_JRSTAR_JR */
15023 #define CAAM_JRSTAR_JR_COUNT                     (4U)
15024 
15025 /*! @name JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 */
15026 /*! @{ */
15027 
15028 #define CAAM_JRINTR_JR_JRI_MASK                  (0x1U)
15029 #define CAAM_JRINTR_JR_JRI_SHIFT                 (0U)
15030 #define CAAM_JRINTR_JR_JRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK)
15031 
15032 #define CAAM_JRINTR_JR_JRE_MASK                  (0x2U)
15033 #define CAAM_JRINTR_JR_JRE_SHIFT                 (1U)
15034 #define CAAM_JRINTR_JR_JRE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK)
15035 
15036 #define CAAM_JRINTR_JR_HALT_MASK                 (0xCU)
15037 #define CAAM_JRINTR_JR_HALT_SHIFT                (2U)
15038 #define CAAM_JRINTR_JR_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK)
15039 
15040 #define CAAM_JRINTR_JR_ENTER_FAIL_MASK           (0x10U)
15041 #define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT          (4U)
15042 #define CAAM_JRINTR_JR_ENTER_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK)
15043 
15044 #define CAAM_JRINTR_JR_EXIT_FAIL_MASK            (0x20U)
15045 #define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT           (5U)
15046 #define CAAM_JRINTR_JR_EXIT_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK)
15047 
15048 #define CAAM_JRINTR_JR_ERR_TYPE_MASK             (0x1F00U)
15049 #define CAAM_JRINTR_JR_ERR_TYPE_SHIFT            (8U)
15050 /*! ERR_TYPE
15051  *  0b00001..Error writing status to Output Ring
15052  *  0b00011..Bad input ring base address (not on a 4-byte boundary).
15053  *  0b00100..Bad output ring base address (not on a 4-byte boundary).
15054  *  0b00101..Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when
15055  *           there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely
15056  *           result in not being able to get all jobs out into the output ring for processing by software. Resetting
15057  *           the job ring will almost certainly be necessary.
15058  *  0b00110..Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when
15059  *           there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in
15060  *           the holding tanks or DECOs), or when the Job Ring is halted.
15061  *  0b00111..Job Ring reset released before Job Ring is halted.
15062  *  0b01000..Removed too many jobs (ORJRR larger than ORSFR).
15063  *  0b01001..Added too many jobs (IRJAR larger than IRSAR).
15064  *  0b01010..Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless
15065  *           masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register.
15066  *  0b01011..Writing IRSA > IRS
15067  *  0b01100..Writing ORWI > ORS in bytes
15068  *  0b01101..Writing IRRI > IRS in bytes
15069  *  0b01110..Writing IRSA when ring is active
15070  *  0b01111..Writing IRRI when ring is active
15071  *  0b10000..Writing ORSF when ring is active
15072  *  0b10001..Writing ORWI when ring is active
15073  */
15074 #define CAAM_JRINTR_JR_ERR_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK)
15075 
15076 #define CAAM_JRINTR_JR_ERR_ORWI_MASK             (0x3FFF0000U)
15077 #define CAAM_JRINTR_JR_ERR_ORWI_SHIFT            (16U)
15078 #define CAAM_JRINTR_JR_ERR_ORWI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK)
15079 /*! @} */
15080 
15081 /* The count of CAAM_JRINTR_JR */
15082 #define CAAM_JRINTR_JR_COUNT                     (4U)
15083 
15084 /*! @name JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half */
15085 /*! @{ */
15086 
15087 #define CAAM_JRCFGR_JR_MS_MBSI_MASK              (0x1U)
15088 #define CAAM_JRCFGR_JR_MS_MBSI_SHIFT             (0U)
15089 #define CAAM_JRCFGR_JR_MS_MBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK)
15090 
15091 #define CAAM_JRCFGR_JR_MS_MHWSI_MASK             (0x2U)
15092 #define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT            (1U)
15093 #define CAAM_JRCFGR_JR_MS_MHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK)
15094 
15095 #define CAAM_JRCFGR_JR_MS_MWSI_MASK              (0x4U)
15096 #define CAAM_JRCFGR_JR_MS_MWSI_SHIFT             (2U)
15097 #define CAAM_JRCFGR_JR_MS_MWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK)
15098 
15099 #define CAAM_JRCFGR_JR_MS_CBSI_MASK              (0x10U)
15100 #define CAAM_JRCFGR_JR_MS_CBSI_SHIFT             (4U)
15101 #define CAAM_JRCFGR_JR_MS_CBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK)
15102 
15103 #define CAAM_JRCFGR_JR_MS_CHWSI_MASK             (0x20U)
15104 #define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT            (5U)
15105 #define CAAM_JRCFGR_JR_MS_CHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK)
15106 
15107 #define CAAM_JRCFGR_JR_MS_CWSI_MASK              (0x40U)
15108 #define CAAM_JRCFGR_JR_MS_CWSI_SHIFT             (6U)
15109 #define CAAM_JRCFGR_JR_MS_CWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK)
15110 
15111 #define CAAM_JRCFGR_JR_MS_MBSO_MASK              (0x100U)
15112 #define CAAM_JRCFGR_JR_MS_MBSO_SHIFT             (8U)
15113 #define CAAM_JRCFGR_JR_MS_MBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK)
15114 
15115 #define CAAM_JRCFGR_JR_MS_MHWSO_MASK             (0x200U)
15116 #define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT            (9U)
15117 #define CAAM_JRCFGR_JR_MS_MHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK)
15118 
15119 #define CAAM_JRCFGR_JR_MS_MWSO_MASK              (0x400U)
15120 #define CAAM_JRCFGR_JR_MS_MWSO_SHIFT             (10U)
15121 #define CAAM_JRCFGR_JR_MS_MWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK)
15122 
15123 #define CAAM_JRCFGR_JR_MS_CBSO_MASK              (0x1000U)
15124 #define CAAM_JRCFGR_JR_MS_CBSO_SHIFT             (12U)
15125 #define CAAM_JRCFGR_JR_MS_CBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK)
15126 
15127 #define CAAM_JRCFGR_JR_MS_CHWSO_MASK             (0x2000U)
15128 #define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT            (13U)
15129 #define CAAM_JRCFGR_JR_MS_CHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK)
15130 
15131 #define CAAM_JRCFGR_JR_MS_CWSO_MASK              (0x4000U)
15132 #define CAAM_JRCFGR_JR_MS_CWSO_SHIFT             (14U)
15133 #define CAAM_JRCFGR_JR_MS_CWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK)
15134 
15135 #define CAAM_JRCFGR_JR_MS_DMBS_MASK              (0x10000U)
15136 #define CAAM_JRCFGR_JR_MS_DMBS_SHIFT             (16U)
15137 #define CAAM_JRCFGR_JR_MS_DMBS(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK)
15138 
15139 #define CAAM_JRCFGR_JR_MS_PEO_MASK               (0x20000U)
15140 #define CAAM_JRCFGR_JR_MS_PEO_SHIFT              (17U)
15141 #define CAAM_JRCFGR_JR_MS_PEO(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK)
15142 
15143 #define CAAM_JRCFGR_JR_MS_DWSO_MASK              (0x40000U)
15144 #define CAAM_JRCFGR_JR_MS_DWSO_SHIFT             (18U)
15145 #define CAAM_JRCFGR_JR_MS_DWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK)
15146 
15147 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK         (0x20000000U)
15148 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT        (29U)
15149 #define CAAM_JRCFGR_JR_MS_FAIL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK)
15150 
15151 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK      (0x40000000U)
15152 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT     (30U)
15153 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK)
15154 /*! @} */
15155 
15156 /* The count of CAAM_JRCFGR_JR_MS */
15157 #define CAAM_JRCFGR_JR_MS_COUNT                  (4U)
15158 
15159 /*! @name JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half */
15160 /*! @{ */
15161 
15162 #define CAAM_JRCFGR_JR_LS_IMSK_MASK              (0x1U)
15163 #define CAAM_JRCFGR_JR_LS_IMSK_SHIFT             (0U)
15164 /*! IMSK
15165  *  0b0..Interrupt enabled.
15166  *  0b1..Interrupt masked.
15167  */
15168 #define CAAM_JRCFGR_JR_LS_IMSK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK)
15169 
15170 #define CAAM_JRCFGR_JR_LS_ICEN_MASK              (0x2U)
15171 #define CAAM_JRCFGR_JR_LS_ICEN_SHIFT             (1U)
15172 /*! ICEN
15173  *  0b0..Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is
15174  *       written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears
15175  *       the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will
15176  *       clear but reassert on the next clock cycle.
15177  *  0b1..Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the
15178  *       threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software
15179  *       removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met
15180  *       (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle.
15181  */
15182 #define CAAM_JRCFGR_JR_LS_ICEN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK)
15183 
15184 #define CAAM_JRCFGR_JR_LS_ICDCT_MASK             (0xFF00U)
15185 #define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT            (8U)
15186 #define CAAM_JRCFGR_JR_LS_ICDCT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK)
15187 
15188 #define CAAM_JRCFGR_JR_LS_ICTT_MASK              (0xFFFF0000U)
15189 #define CAAM_JRCFGR_JR_LS_ICTT_SHIFT             (16U)
15190 #define CAAM_JRCFGR_JR_LS_ICTT(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK)
15191 /*! @} */
15192 
15193 /* The count of CAAM_JRCFGR_JR_LS */
15194 #define CAAM_JRCFGR_JR_LS_COUNT                  (4U)
15195 
15196 /*! @name IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 */
15197 /*! @{ */
15198 
15199 #define CAAM_IRRIR_JR_IRRI_MASK                  (0x1FFFU)
15200 #define CAAM_IRRIR_JR_IRRI_SHIFT                 (0U)
15201 #define CAAM_IRRIR_JR_IRRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK)
15202 /*! @} */
15203 
15204 /* The count of CAAM_IRRIR_JR */
15205 #define CAAM_IRRIR_JR_COUNT                      (4U)
15206 
15207 /*! @name ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 */
15208 /*! @{ */
15209 
15210 #define CAAM_ORWIR_JR_ORWI_MASK                  (0x3FFFU)
15211 #define CAAM_ORWIR_JR_ORWI_SHIFT                 (0U)
15212 #define CAAM_ORWIR_JR_ORWI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK)
15213 /*! @} */
15214 
15215 /* The count of CAAM_ORWIR_JR */
15216 #define CAAM_ORWIR_JR_COUNT                      (4U)
15217 
15218 /*! @name JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 */
15219 /*! @{ */
15220 
15221 #define CAAM_JRCR_JR_RESET_MASK                  (0x1U)
15222 #define CAAM_JRCR_JR_RESET_SHIFT                 (0U)
15223 #define CAAM_JRCR_JR_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK)
15224 
15225 #define CAAM_JRCR_JR_PARK_MASK                   (0x2U)
15226 #define CAAM_JRCR_JR_PARK_SHIFT                  (1U)
15227 #define CAAM_JRCR_JR_PARK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK)
15228 /*! @} */
15229 
15230 /* The count of CAAM_JRCR_JR */
15231 #define CAAM_JRCR_JR_COUNT                       (4U)
15232 
15233 /*! @name JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register */
15234 /*! @{ */
15235 
15236 #define CAAM_JRAAV_V0_MASK                       (0x1U)
15237 #define CAAM_JRAAV_V0_SHIFT                      (0U)
15238 #define CAAM_JRAAV_V0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK)
15239 
15240 #define CAAM_JRAAV_V1_MASK                       (0x2U)
15241 #define CAAM_JRAAV_V1_SHIFT                      (1U)
15242 #define CAAM_JRAAV_V1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK)
15243 
15244 #define CAAM_JRAAV_V2_MASK                       (0x4U)
15245 #define CAAM_JRAAV_V2_SHIFT                      (2U)
15246 #define CAAM_JRAAV_V2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK)
15247 
15248 #define CAAM_JRAAV_V3_MASK                       (0x8U)
15249 #define CAAM_JRAAV_V3_SHIFT                      (3U)
15250 #define CAAM_JRAAV_V3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK)
15251 
15252 #define CAAM_JRAAV_BC_MASK                       (0x80000000U)
15253 #define CAAM_JRAAV_BC_SHIFT                      (31U)
15254 #define CAAM_JRAAV_BC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK)
15255 /*! @} */
15256 
15257 /* The count of CAAM_JRAAV */
15258 #define CAAM_JRAAV_COUNT                         (4U)
15259 
15260 /*! @name JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register */
15261 /*! @{ */
15262 
15263 #define CAAM_JRAAA_JD_ADDR_MASK                  (0xFFFFFFFFFU)
15264 #define CAAM_JRAAA_JD_ADDR_SHIFT                 (0U)
15265 #define CAAM_JRAAA_JD_ADDR(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK)
15266 /*! @} */
15267 
15268 /* The count of CAAM_JRAAA */
15269 #define CAAM_JRAAA_COUNT                         (4U)
15270 
15271 /* The count of CAAM_JRAAA */
15272 #define CAAM_JRAAA_COUNT2                        (4U)
15273 
15274 /*! @name PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register */
15275 /*! @{ */
15276 
15277 #define CAAM_PX_SDID_JR_SDID_MASK                (0xFFFFU)
15278 #define CAAM_PX_SDID_JR_SDID_SHIFT               (0U)
15279 #define CAAM_PX_SDID_JR_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK)
15280 /*! @} */
15281 
15282 /* The count of CAAM_PX_SDID_JR */
15283 #define CAAM_PX_SDID_JR_COUNT                    (4U)
15284 
15285 /* The count of CAAM_PX_SDID_JR */
15286 #define CAAM_PX_SDID_JR_COUNT2                   (16U)
15287 
15288 /*! @name PX_SMAPR_JR - Secure Memory Access Permissions register */
15289 /*! @{ */
15290 
15291 #define CAAM_PX_SMAPR_JR_G1_READ_MASK            (0x1U)
15292 #define CAAM_PX_SMAPR_JR_G1_READ_SHIFT           (0U)
15293 /*! G1_READ
15294  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
15295  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
15296  *       Trusted Descriptor and G1_TDO=1).
15297  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15298  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
15299  */
15300 #define CAAM_PX_SMAPR_JR_G1_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK)
15301 
15302 #define CAAM_PX_SMAPR_JR_G1_WRITE_MASK           (0x2U)
15303 #define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT          (1U)
15304 /*! G1_WRITE
15305  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15306  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
15307  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
15308  *       not a Trusted Descriptor or if G1_TDO=0).
15309  */
15310 #define CAAM_PX_SMAPR_JR_G1_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK)
15311 
15312 #define CAAM_PX_SMAPR_JR_G1_TDO_MASK             (0x4U)
15313 #define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT            (2U)
15314 /*! G1_TDO
15315  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15316  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15317  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
15318  *       G1_WRITE and G1_READ settings.
15319  */
15320 #define CAAM_PX_SMAPR_JR_G1_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK)
15321 
15322 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK          (0x8U)
15323 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT         (3U)
15324 /*! G1_SMBLOB
15325  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
15326  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
15327  */
15328 #define CAAM_PX_SMAPR_JR_G1_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK)
15329 
15330 #define CAAM_PX_SMAPR_JR_G2_READ_MASK            (0x10U)
15331 #define CAAM_PX_SMAPR_JR_G2_READ_SHIFT           (4U)
15332 /*! G2_READ
15333  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
15334  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
15335  *       Trusted Descriptor and G2_TDO=1).
15336  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15337  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
15338  */
15339 #define CAAM_PX_SMAPR_JR_G2_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK)
15340 
15341 #define CAAM_PX_SMAPR_JR_G2_WRITE_MASK           (0x20U)
15342 #define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT          (5U)
15343 /*! G2_WRITE
15344  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15345  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
15346  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
15347  *       not a Trusted Descriptor or if G2_TDO=0).
15348  */
15349 #define CAAM_PX_SMAPR_JR_G2_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK)
15350 
15351 #define CAAM_PX_SMAPR_JR_G2_TDO_MASK             (0x40U)
15352 #define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT            (6U)
15353 /*! G2_TDO
15354  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15355  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15356  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
15357  *       G2_WRITE and G2_READ settings.
15358  */
15359 #define CAAM_PX_SMAPR_JR_G2_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK)
15360 
15361 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK          (0x80U)
15362 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT         (7U)
15363 /*! G2_SMBLOB
15364  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
15365  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
15366  */
15367 #define CAAM_PX_SMAPR_JR_G2_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK)
15368 
15369 #define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK           (0x1000U)
15370 #define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT          (12U)
15371 /*! SMAG_LCK
15372  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
15373  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
15374  *       until the partition is de-allocated or a POR occurs.
15375  */
15376 #define CAAM_PX_SMAPR_JR_SMAG_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK)
15377 
15378 #define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK           (0x2000U)
15379 #define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT          (13U)
15380 /*! SMAP_LCK
15381  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
15382  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
15383  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
15384  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
15385  */
15386 #define CAAM_PX_SMAPR_JR_SMAP_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK)
15387 
15388 #define CAAM_PX_SMAPR_JR_PSP_MASK                (0x4000U)
15389 #define CAAM_PX_SMAPR_JR_PSP_SHIFT               (14U)
15390 /*! PSP
15391  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
15392  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
15393  */
15394 #define CAAM_PX_SMAPR_JR_PSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK)
15395 
15396 #define CAAM_PX_SMAPR_JR_CSP_MASK                (0x8000U)
15397 #define CAAM_PX_SMAPR_JR_CSP_SHIFT               (15U)
15398 /*! CSP
15399  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
15400  *       released or a security alarm occurs.
15401  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
15402  *       partition is released or a security alarm occurs.
15403  */
15404 #define CAAM_PX_SMAPR_JR_CSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK)
15405 
15406 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK     (0xFFFF0000U)
15407 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT    (16U)
15408 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK)
15409 /*! @} */
15410 
15411 /* The count of CAAM_PX_SMAPR_JR */
15412 #define CAAM_PX_SMAPR_JR_COUNT                   (4U)
15413 
15414 /* The count of CAAM_PX_SMAPR_JR */
15415 #define CAAM_PX_SMAPR_JR_COUNT2                  (16U)
15416 
15417 /*! @name PX_SMAG2_JR - Secure Memory Access Group Registers */
15418 /*! @{ */
15419 
15420 #define CAAM_PX_SMAG2_JR_Gx_ID00_MASK            (0x1U)
15421 #define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT           (0U)
15422 #define CAAM_PX_SMAG2_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK)
15423 
15424 #define CAAM_PX_SMAG2_JR_Gx_ID01_MASK            (0x2U)
15425 #define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT           (1U)
15426 #define CAAM_PX_SMAG2_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK)
15427 
15428 #define CAAM_PX_SMAG2_JR_Gx_ID02_MASK            (0x4U)
15429 #define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT           (2U)
15430 #define CAAM_PX_SMAG2_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK)
15431 
15432 #define CAAM_PX_SMAG2_JR_Gx_ID03_MASK            (0x8U)
15433 #define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT           (3U)
15434 #define CAAM_PX_SMAG2_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK)
15435 
15436 #define CAAM_PX_SMAG2_JR_Gx_ID04_MASK            (0x10U)
15437 #define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT           (4U)
15438 #define CAAM_PX_SMAG2_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK)
15439 
15440 #define CAAM_PX_SMAG2_JR_Gx_ID05_MASK            (0x20U)
15441 #define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT           (5U)
15442 #define CAAM_PX_SMAG2_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK)
15443 
15444 #define CAAM_PX_SMAG2_JR_Gx_ID06_MASK            (0x40U)
15445 #define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT           (6U)
15446 #define CAAM_PX_SMAG2_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK)
15447 
15448 #define CAAM_PX_SMAG2_JR_Gx_ID07_MASK            (0x80U)
15449 #define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT           (7U)
15450 #define CAAM_PX_SMAG2_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK)
15451 
15452 #define CAAM_PX_SMAG2_JR_Gx_ID08_MASK            (0x100U)
15453 #define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT           (8U)
15454 #define CAAM_PX_SMAG2_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK)
15455 
15456 #define CAAM_PX_SMAG2_JR_Gx_ID09_MASK            (0x200U)
15457 #define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT           (9U)
15458 #define CAAM_PX_SMAG2_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK)
15459 
15460 #define CAAM_PX_SMAG2_JR_Gx_ID10_MASK            (0x400U)
15461 #define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT           (10U)
15462 #define CAAM_PX_SMAG2_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK)
15463 
15464 #define CAAM_PX_SMAG2_JR_Gx_ID11_MASK            (0x800U)
15465 #define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT           (11U)
15466 #define CAAM_PX_SMAG2_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK)
15467 
15468 #define CAAM_PX_SMAG2_JR_Gx_ID12_MASK            (0x1000U)
15469 #define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT           (12U)
15470 #define CAAM_PX_SMAG2_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK)
15471 
15472 #define CAAM_PX_SMAG2_JR_Gx_ID13_MASK            (0x2000U)
15473 #define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT           (13U)
15474 #define CAAM_PX_SMAG2_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK)
15475 
15476 #define CAAM_PX_SMAG2_JR_Gx_ID14_MASK            (0x4000U)
15477 #define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT           (14U)
15478 #define CAAM_PX_SMAG2_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK)
15479 
15480 #define CAAM_PX_SMAG2_JR_Gx_ID15_MASK            (0x8000U)
15481 #define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT           (15U)
15482 #define CAAM_PX_SMAG2_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK)
15483 
15484 #define CAAM_PX_SMAG2_JR_Gx_ID16_MASK            (0x10000U)
15485 #define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT           (16U)
15486 #define CAAM_PX_SMAG2_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK)
15487 
15488 #define CAAM_PX_SMAG2_JR_Gx_ID17_MASK            (0x20000U)
15489 #define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT           (17U)
15490 #define CAAM_PX_SMAG2_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK)
15491 
15492 #define CAAM_PX_SMAG2_JR_Gx_ID18_MASK            (0x40000U)
15493 #define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT           (18U)
15494 #define CAAM_PX_SMAG2_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK)
15495 
15496 #define CAAM_PX_SMAG2_JR_Gx_ID19_MASK            (0x80000U)
15497 #define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT           (19U)
15498 #define CAAM_PX_SMAG2_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK)
15499 
15500 #define CAAM_PX_SMAG2_JR_Gx_ID20_MASK            (0x100000U)
15501 #define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT           (20U)
15502 #define CAAM_PX_SMAG2_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK)
15503 
15504 #define CAAM_PX_SMAG2_JR_Gx_ID21_MASK            (0x200000U)
15505 #define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT           (21U)
15506 #define CAAM_PX_SMAG2_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK)
15507 
15508 #define CAAM_PX_SMAG2_JR_Gx_ID22_MASK            (0x400000U)
15509 #define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT           (22U)
15510 #define CAAM_PX_SMAG2_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK)
15511 
15512 #define CAAM_PX_SMAG2_JR_Gx_ID23_MASK            (0x800000U)
15513 #define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT           (23U)
15514 #define CAAM_PX_SMAG2_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK)
15515 
15516 #define CAAM_PX_SMAG2_JR_Gx_ID24_MASK            (0x1000000U)
15517 #define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT           (24U)
15518 #define CAAM_PX_SMAG2_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK)
15519 
15520 #define CAAM_PX_SMAG2_JR_Gx_ID25_MASK            (0x2000000U)
15521 #define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT           (25U)
15522 #define CAAM_PX_SMAG2_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK)
15523 
15524 #define CAAM_PX_SMAG2_JR_Gx_ID26_MASK            (0x4000000U)
15525 #define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT           (26U)
15526 #define CAAM_PX_SMAG2_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK)
15527 
15528 #define CAAM_PX_SMAG2_JR_Gx_ID27_MASK            (0x8000000U)
15529 #define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT           (27U)
15530 #define CAAM_PX_SMAG2_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK)
15531 
15532 #define CAAM_PX_SMAG2_JR_Gx_ID28_MASK            (0x10000000U)
15533 #define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT           (28U)
15534 #define CAAM_PX_SMAG2_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK)
15535 
15536 #define CAAM_PX_SMAG2_JR_Gx_ID29_MASK            (0x20000000U)
15537 #define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT           (29U)
15538 #define CAAM_PX_SMAG2_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK)
15539 
15540 #define CAAM_PX_SMAG2_JR_Gx_ID30_MASK            (0x40000000U)
15541 #define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT           (30U)
15542 #define CAAM_PX_SMAG2_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK)
15543 
15544 #define CAAM_PX_SMAG2_JR_Gx_ID31_MASK            (0x80000000U)
15545 #define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT           (31U)
15546 #define CAAM_PX_SMAG2_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK)
15547 /*! @} */
15548 
15549 /* The count of CAAM_PX_SMAG2_JR */
15550 #define CAAM_PX_SMAG2_JR_COUNT                   (4U)
15551 
15552 /* The count of CAAM_PX_SMAG2_JR */
15553 #define CAAM_PX_SMAG2_JR_COUNT2                  (16U)
15554 
15555 /*! @name PX_SMAG1_JR - Secure Memory Access Group Registers */
15556 /*! @{ */
15557 
15558 #define CAAM_PX_SMAG1_JR_Gx_ID00_MASK            (0x1U)
15559 #define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT           (0U)
15560 #define CAAM_PX_SMAG1_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK)
15561 
15562 #define CAAM_PX_SMAG1_JR_Gx_ID01_MASK            (0x2U)
15563 #define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT           (1U)
15564 #define CAAM_PX_SMAG1_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK)
15565 
15566 #define CAAM_PX_SMAG1_JR_Gx_ID02_MASK            (0x4U)
15567 #define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT           (2U)
15568 #define CAAM_PX_SMAG1_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK)
15569 
15570 #define CAAM_PX_SMAG1_JR_Gx_ID03_MASK            (0x8U)
15571 #define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT           (3U)
15572 #define CAAM_PX_SMAG1_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK)
15573 
15574 #define CAAM_PX_SMAG1_JR_Gx_ID04_MASK            (0x10U)
15575 #define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT           (4U)
15576 #define CAAM_PX_SMAG1_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK)
15577 
15578 #define CAAM_PX_SMAG1_JR_Gx_ID05_MASK            (0x20U)
15579 #define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT           (5U)
15580 #define CAAM_PX_SMAG1_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK)
15581 
15582 #define CAAM_PX_SMAG1_JR_Gx_ID06_MASK            (0x40U)
15583 #define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT           (6U)
15584 #define CAAM_PX_SMAG1_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK)
15585 
15586 #define CAAM_PX_SMAG1_JR_Gx_ID07_MASK            (0x80U)
15587 #define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT           (7U)
15588 #define CAAM_PX_SMAG1_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK)
15589 
15590 #define CAAM_PX_SMAG1_JR_Gx_ID08_MASK            (0x100U)
15591 #define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT           (8U)
15592 #define CAAM_PX_SMAG1_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK)
15593 
15594 #define CAAM_PX_SMAG1_JR_Gx_ID09_MASK            (0x200U)
15595 #define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT           (9U)
15596 #define CAAM_PX_SMAG1_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK)
15597 
15598 #define CAAM_PX_SMAG1_JR_Gx_ID10_MASK            (0x400U)
15599 #define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT           (10U)
15600 #define CAAM_PX_SMAG1_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK)
15601 
15602 #define CAAM_PX_SMAG1_JR_Gx_ID11_MASK            (0x800U)
15603 #define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT           (11U)
15604 #define CAAM_PX_SMAG1_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK)
15605 
15606 #define CAAM_PX_SMAG1_JR_Gx_ID12_MASK            (0x1000U)
15607 #define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT           (12U)
15608 #define CAAM_PX_SMAG1_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK)
15609 
15610 #define CAAM_PX_SMAG1_JR_Gx_ID13_MASK            (0x2000U)
15611 #define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT           (13U)
15612 #define CAAM_PX_SMAG1_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK)
15613 
15614 #define CAAM_PX_SMAG1_JR_Gx_ID14_MASK            (0x4000U)
15615 #define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT           (14U)
15616 #define CAAM_PX_SMAG1_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK)
15617 
15618 #define CAAM_PX_SMAG1_JR_Gx_ID15_MASK            (0x8000U)
15619 #define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT           (15U)
15620 #define CAAM_PX_SMAG1_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK)
15621 
15622 #define CAAM_PX_SMAG1_JR_Gx_ID16_MASK            (0x10000U)
15623 #define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT           (16U)
15624 #define CAAM_PX_SMAG1_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK)
15625 
15626 #define CAAM_PX_SMAG1_JR_Gx_ID17_MASK            (0x20000U)
15627 #define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT           (17U)
15628 #define CAAM_PX_SMAG1_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK)
15629 
15630 #define CAAM_PX_SMAG1_JR_Gx_ID18_MASK            (0x40000U)
15631 #define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT           (18U)
15632 #define CAAM_PX_SMAG1_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK)
15633 
15634 #define CAAM_PX_SMAG1_JR_Gx_ID19_MASK            (0x80000U)
15635 #define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT           (19U)
15636 #define CAAM_PX_SMAG1_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK)
15637 
15638 #define CAAM_PX_SMAG1_JR_Gx_ID20_MASK            (0x100000U)
15639 #define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT           (20U)
15640 #define CAAM_PX_SMAG1_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK)
15641 
15642 #define CAAM_PX_SMAG1_JR_Gx_ID21_MASK            (0x200000U)
15643 #define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT           (21U)
15644 #define CAAM_PX_SMAG1_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK)
15645 
15646 #define CAAM_PX_SMAG1_JR_Gx_ID22_MASK            (0x400000U)
15647 #define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT           (22U)
15648 #define CAAM_PX_SMAG1_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK)
15649 
15650 #define CAAM_PX_SMAG1_JR_Gx_ID23_MASK            (0x800000U)
15651 #define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT           (23U)
15652 #define CAAM_PX_SMAG1_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK)
15653 
15654 #define CAAM_PX_SMAG1_JR_Gx_ID24_MASK            (0x1000000U)
15655 #define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT           (24U)
15656 #define CAAM_PX_SMAG1_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK)
15657 
15658 #define CAAM_PX_SMAG1_JR_Gx_ID25_MASK            (0x2000000U)
15659 #define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT           (25U)
15660 #define CAAM_PX_SMAG1_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK)
15661 
15662 #define CAAM_PX_SMAG1_JR_Gx_ID26_MASK            (0x4000000U)
15663 #define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT           (26U)
15664 #define CAAM_PX_SMAG1_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK)
15665 
15666 #define CAAM_PX_SMAG1_JR_Gx_ID27_MASK            (0x8000000U)
15667 #define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT           (27U)
15668 #define CAAM_PX_SMAG1_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK)
15669 
15670 #define CAAM_PX_SMAG1_JR_Gx_ID28_MASK            (0x10000000U)
15671 #define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT           (28U)
15672 #define CAAM_PX_SMAG1_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK)
15673 
15674 #define CAAM_PX_SMAG1_JR_Gx_ID29_MASK            (0x20000000U)
15675 #define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT           (29U)
15676 #define CAAM_PX_SMAG1_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK)
15677 
15678 #define CAAM_PX_SMAG1_JR_Gx_ID30_MASK            (0x40000000U)
15679 #define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT           (30U)
15680 #define CAAM_PX_SMAG1_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK)
15681 
15682 #define CAAM_PX_SMAG1_JR_Gx_ID31_MASK            (0x80000000U)
15683 #define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT           (31U)
15684 #define CAAM_PX_SMAG1_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK)
15685 /*! @} */
15686 
15687 /* The count of CAAM_PX_SMAG1_JR */
15688 #define CAAM_PX_SMAG1_JR_COUNT                   (4U)
15689 
15690 /* The count of CAAM_PX_SMAG1_JR */
15691 #define CAAM_PX_SMAG1_JR_COUNT2                  (16U)
15692 
15693 /*! @name SMCR_JR - Secure Memory Command Register */
15694 /*! @{ */
15695 
15696 #define CAAM_SMCR_JR_CMD_MASK                    (0xFU)
15697 #define CAAM_SMCR_JR_CMD_SHIFT                   (0U)
15698 #define CAAM_SMCR_JR_CMD(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK)
15699 
15700 #define CAAM_SMCR_JR_PRTN_MASK                   (0xF00U)
15701 #define CAAM_SMCR_JR_PRTN_SHIFT                  (8U)
15702 #define CAAM_SMCR_JR_PRTN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK)
15703 
15704 #define CAAM_SMCR_JR_PAGE_MASK                   (0xFFFF0000U)
15705 #define CAAM_SMCR_JR_PAGE_SHIFT                  (16U)
15706 #define CAAM_SMCR_JR_PAGE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK)
15707 /*! @} */
15708 
15709 /* The count of CAAM_SMCR_JR */
15710 #define CAAM_SMCR_JR_COUNT                       (4U)
15711 
15712 /*! @name SMCSR_JR - Secure Memory Command Status Register */
15713 /*! @{ */
15714 
15715 #define CAAM_SMCSR_JR_PRTN_MASK                  (0xFU)
15716 #define CAAM_SMCSR_JR_PRTN_SHIFT                 (0U)
15717 #define CAAM_SMCSR_JR_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK)
15718 
15719 #define CAAM_SMCSR_JR_PO_MASK                    (0xC0U)
15720 #define CAAM_SMCSR_JR_PO_SHIFT                   (6U)
15721 /*! PO
15722  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
15723  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
15724  *  0b01..Page does not exist in this version or is not initialized yet.
15725  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
15726  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
15727  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
15728  *        upon de-allocation.
15729  */
15730 #define CAAM_SMCSR_JR_PO(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK)
15731 
15732 #define CAAM_SMCSR_JR_AERR_MASK                  (0x3000U)
15733 #define CAAM_SMCSR_JR_AERR_SHIFT                 (12U)
15734 #define CAAM_SMCSR_JR_AERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK)
15735 
15736 #define CAAM_SMCSR_JR_CERR_MASK                  (0xC000U)
15737 #define CAAM_SMCSR_JR_CERR_SHIFT                 (14U)
15738 /*! CERR
15739  *  0b00..No Error.
15740  *  0b01..Command has not yet completed.
15741  *  0b10..A security failure occurred.
15742  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
15743  *        command completed. The additional command was ignored.
15744  */
15745 #define CAAM_SMCSR_JR_CERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK)
15746 
15747 #define CAAM_SMCSR_JR_PAGE_MASK                  (0xFFF0000U)
15748 #define CAAM_SMCSR_JR_PAGE_SHIFT                 (16U)
15749 #define CAAM_SMCSR_JR_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK)
15750 /*! @} */
15751 
15752 /* The count of CAAM_SMCSR_JR */
15753 #define CAAM_SMCSR_JR_COUNT                      (4U)
15754 
15755 /*! @name REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 */
15756 /*! @{ */
15757 
15758 #define CAAM_REIR0JR_TYPE_MASK                   (0x3000000U)
15759 #define CAAM_REIR0JR_TYPE_SHIFT                  (24U)
15760 #define CAAM_REIR0JR_TYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK)
15761 
15762 #define CAAM_REIR0JR_MISS_MASK                   (0x80000000U)
15763 #define CAAM_REIR0JR_MISS_SHIFT                  (31U)
15764 #define CAAM_REIR0JR_MISS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK)
15765 /*! @} */
15766 
15767 /* The count of CAAM_REIR0JR */
15768 #define CAAM_REIR0JR_COUNT                       (4U)
15769 
15770 /*! @name REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 */
15771 /*! @{ */
15772 
15773 #define CAAM_REIR2JR_ADDR_MASK                   (0xFFFFFFFFFU)
15774 #define CAAM_REIR2JR_ADDR_SHIFT                  (0U)
15775 #define CAAM_REIR2JR_ADDR(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK)
15776 /*! @} */
15777 
15778 /* The count of CAAM_REIR2JR */
15779 #define CAAM_REIR2JR_COUNT                       (4U)
15780 
15781 /*! @name REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 */
15782 /*! @{ */
15783 
15784 #define CAAM_REIR4JR_ICID_MASK                   (0x7FFU)
15785 #define CAAM_REIR4JR_ICID_SHIFT                  (0U)
15786 #define CAAM_REIR4JR_ICID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK)
15787 
15788 #define CAAM_REIR4JR_DID_MASK                    (0x7800U)
15789 #define CAAM_REIR4JR_DID_SHIFT                   (11U)
15790 #define CAAM_REIR4JR_DID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK)
15791 
15792 #define CAAM_REIR4JR_AXCACHE_MASK                (0xF0000U)
15793 #define CAAM_REIR4JR_AXCACHE_SHIFT               (16U)
15794 #define CAAM_REIR4JR_AXCACHE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK)
15795 
15796 #define CAAM_REIR4JR_AXPROT_MASK                 (0x700000U)
15797 #define CAAM_REIR4JR_AXPROT_SHIFT                (20U)
15798 #define CAAM_REIR4JR_AXPROT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK)
15799 
15800 #define CAAM_REIR4JR_RWB_MASK                    (0x800000U)
15801 #define CAAM_REIR4JR_RWB_SHIFT                   (23U)
15802 #define CAAM_REIR4JR_RWB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK)
15803 
15804 #define CAAM_REIR4JR_ERR_MASK                    (0x30000000U)
15805 #define CAAM_REIR4JR_ERR_SHIFT                   (28U)
15806 #define CAAM_REIR4JR_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK)
15807 
15808 #define CAAM_REIR4JR_MIX_MASK                    (0xC0000000U)
15809 #define CAAM_REIR4JR_MIX_SHIFT                   (30U)
15810 #define CAAM_REIR4JR_MIX(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK)
15811 /*! @} */
15812 
15813 /* The count of CAAM_REIR4JR */
15814 #define CAAM_REIR4JR_COUNT                       (4U)
15815 
15816 /*! @name REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 */
15817 /*! @{ */
15818 
15819 #define CAAM_REIR5JR_BID_MASK                    (0xF0000U)
15820 #define CAAM_REIR5JR_BID_SHIFT                   (16U)
15821 #define CAAM_REIR5JR_BID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK)
15822 
15823 #define CAAM_REIR5JR_BNDG_MASK                   (0x2000000U)
15824 #define CAAM_REIR5JR_BNDG_SHIFT                  (25U)
15825 #define CAAM_REIR5JR_BNDG(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK)
15826 
15827 #define CAAM_REIR5JR_TDSC_MASK                   (0x4000000U)
15828 #define CAAM_REIR5JR_TDSC_SHIFT                  (26U)
15829 #define CAAM_REIR5JR_TDSC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK)
15830 
15831 #define CAAM_REIR5JR_KMOD_MASK                   (0x8000000U)
15832 #define CAAM_REIR5JR_KMOD_SHIFT                  (27U)
15833 #define CAAM_REIR5JR_KMOD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK)
15834 
15835 #define CAAM_REIR5JR_KEY_MASK                    (0x10000000U)
15836 #define CAAM_REIR5JR_KEY_SHIFT                   (28U)
15837 #define CAAM_REIR5JR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK)
15838 
15839 #define CAAM_REIR5JR_SMA_MASK                    (0x20000000U)
15840 #define CAAM_REIR5JR_SMA_SHIFT                   (29U)
15841 #define CAAM_REIR5JR_SMA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK)
15842 /*! @} */
15843 
15844 /* The count of CAAM_REIR5JR */
15845 #define CAAM_REIR5JR_COUNT                       (4U)
15846 
15847 /*! @name RSTA - RTIC Status Register */
15848 /*! @{ */
15849 
15850 #define CAAM_RSTA_BSY_MASK                       (0x1U)
15851 #define CAAM_RSTA_BSY_SHIFT                      (0U)
15852 /*! BSY
15853  *  0b0..RTIC Idle.
15854  *  0b1..RTIC Busy.
15855  */
15856 #define CAAM_RSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK)
15857 
15858 #define CAAM_RSTA_HD_MASK                        (0x2U)
15859 #define CAAM_RSTA_HD_SHIFT                       (1U)
15860 /*! HD
15861  *  0b0..Boot authentication disabled
15862  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15863  */
15864 #define CAAM_RSTA_HD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK)
15865 
15866 #define CAAM_RSTA_SV_MASK                        (0x4U)
15867 #define CAAM_RSTA_SV_SHIFT                       (2U)
15868 /*! SV
15869  *  0b0..Memory block contents authenticated.
15870  *  0b1..Memory block hash doesn't match reference value.
15871  */
15872 #define CAAM_RSTA_SV(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK)
15873 
15874 #define CAAM_RSTA_HE_MASK                        (0x8U)
15875 #define CAAM_RSTA_HE_SHIFT                       (3U)
15876 /*! HE
15877  *  0b0..Memory block contents authenticated.
15878  *  0b1..Memory block hash doesn't match reference value.
15879  */
15880 #define CAAM_RSTA_HE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK)
15881 
15882 #define CAAM_RSTA_MIS_MASK                       (0xF0U)
15883 #define CAAM_RSTA_MIS_SHIFT                      (4U)
15884 /*! MIS
15885  *  0b0000..Memory Block X is valid or state unknown
15886  *  0b0001..Memory Block X has been corrupted
15887  */
15888 #define CAAM_RSTA_MIS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK)
15889 
15890 #define CAAM_RSTA_AE_MASK                        (0xF00U)
15891 #define CAAM_RSTA_AE_SHIFT                       (8U)
15892 /*! AE
15893  *  0b0000..All reads by RTIC were valid.
15894  *  0b0001..An illegal address was accessed by the RTIC
15895  */
15896 #define CAAM_RSTA_AE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK)
15897 
15898 #define CAAM_RSTA_WE_MASK                        (0x10000U)
15899 #define CAAM_RSTA_WE_SHIFT                       (16U)
15900 /*! WE
15901  *  0b0..No RTIC Watchdog timer error has occurred.
15902  *  0b1..RTIC Watchdog timer has expired prior to completing a round of hashing.
15903  */
15904 #define CAAM_RSTA_WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK)
15905 
15906 #define CAAM_RSTA_ABH_MASK                       (0x20000U)
15907 #define CAAM_RSTA_ABH_SHIFT                      (17U)
15908 #define CAAM_RSTA_ABH(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK)
15909 
15910 #define CAAM_RSTA_HOD_MASK                       (0x40000U)
15911 #define CAAM_RSTA_HOD_SHIFT                      (18U)
15912 #define CAAM_RSTA_HOD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK)
15913 
15914 #define CAAM_RSTA_RTD_MASK                       (0x80000U)
15915 #define CAAM_RSTA_RTD_SHIFT                      (19U)
15916 #define CAAM_RSTA_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK)
15917 
15918 #define CAAM_RSTA_CS_MASK                        (0x6000000U)
15919 #define CAAM_RSTA_CS_SHIFT                       (25U)
15920 /*! CS
15921  *  0b00..Idle State
15922  *  0b01..Single Hash State
15923  *  0b10..Run-time State
15924  *  0b11..Error State
15925  */
15926 #define CAAM_RSTA_CS(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK)
15927 /*! @} */
15928 
15929 /*! @name RCMD - RTIC Command Register */
15930 /*! @{ */
15931 
15932 #define CAAM_RCMD_CINT_MASK                      (0x1U)
15933 #define CAAM_RCMD_CINT_SHIFT                     (0U)
15934 /*! CINT
15935  *  0b0..Do not clear interrupt
15936  *  0b1..Clear interrupt. This bit cannot be modified during run-time checking mode
15937  */
15938 #define CAAM_RCMD_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK)
15939 
15940 #define CAAM_RCMD_HO_MASK                        (0x2U)
15941 #define CAAM_RCMD_HO_SHIFT                       (1U)
15942 /*! HO
15943  *  0b0..Boot authentication disabled
15944  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15945  */
15946 #define CAAM_RCMD_HO(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK)
15947 
15948 #define CAAM_RCMD_RTC_MASK                       (0x4U)
15949 #define CAAM_RCMD_RTC_SHIFT                      (2U)
15950 /*! RTC
15951  *  0b0..Run-time checking disabled
15952  *  0b1..Verify run-time memory blocks continually
15953  */
15954 #define CAAM_RCMD_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK)
15955 
15956 #define CAAM_RCMD_RTD_MASK                       (0x8U)
15957 #define CAAM_RCMD_RTD_SHIFT                      (3U)
15958 /*! RTD
15959  *  0b0..Allow Run Time Mode
15960  *  0b1..Prevent Run Time Mode
15961  */
15962 #define CAAM_RCMD_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK)
15963 /*! @} */
15964 
15965 /*! @name RCTL - RTIC Control Register */
15966 /*! @{ */
15967 
15968 #define CAAM_RCTL_IE_MASK                        (0x1U)
15969 #define CAAM_RCTL_IE_SHIFT                       (0U)
15970 /*! IE
15971  *  0b0..Interrupts disabled
15972  *  0b1..Interrupts enabled
15973  */
15974 #define CAAM_RCTL_IE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK)
15975 
15976 #define CAAM_RCTL_RREQS_MASK                     (0xEU)
15977 #define CAAM_RCTL_RREQS_SHIFT                    (1U)
15978 #define CAAM_RCTL_RREQS(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK)
15979 
15980 #define CAAM_RCTL_HOME_MASK                      (0xF0U)
15981 #define CAAM_RCTL_HOME_SHIFT                     (4U)
15982 #define CAAM_RCTL_HOME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK)
15983 
15984 #define CAAM_RCTL_RTME_MASK                      (0xF00U)
15985 #define CAAM_RCTL_RTME_SHIFT                     (8U)
15986 #define CAAM_RCTL_RTME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK)
15987 
15988 #define CAAM_RCTL_RTMU_MASK                      (0xF000U)
15989 #define CAAM_RCTL_RTMU_SHIFT                     (12U)
15990 #define CAAM_RCTL_RTMU(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK)
15991 
15992 #define CAAM_RCTL_RALG_MASK                      (0xF0000U)
15993 #define CAAM_RCTL_RALG_SHIFT                     (16U)
15994 #define CAAM_RCTL_RALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK)
15995 
15996 #define CAAM_RCTL_RIDLE_MASK                     (0x100000U)
15997 #define CAAM_RCTL_RIDLE_SHIFT                    (20U)
15998 #define CAAM_RCTL_RIDLE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK)
15999 /*! @} */
16000 
16001 /*! @name RTHR - RTIC Throttle Register */
16002 /*! @{ */
16003 
16004 #define CAAM_RTHR_RTHR_MASK                      (0xFFFFU)
16005 #define CAAM_RTHR_RTHR_SHIFT                     (0U)
16006 #define CAAM_RTHR_RTHR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK)
16007 /*! @} */
16008 
16009 /*! @name RWDOG - RTIC Watchdog Timer */
16010 /*! @{ */
16011 
16012 #define CAAM_RWDOG_RWDOG_MASK                    (0xFFFFFFFFU)
16013 #define CAAM_RWDOG_RWDOG_SHIFT                   (0U)
16014 #define CAAM_RWDOG_RWDOG(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK)
16015 /*! @} */
16016 
16017 /*! @name REND - RTIC Endian Register */
16018 /*! @{ */
16019 
16020 #define CAAM_REND_REPO_MASK                      (0xFU)
16021 #define CAAM_REND_REPO_SHIFT                     (0U)
16022 /*! REPO
16023  *  0bxxx1..Byte Swap Memory Block A
16024  *  0bxx1x..Byte Swap Memory Block B
16025  *  0bx1xx..Byte Swap Memory Block C
16026  *  0b1xxx..Byte Swap Memory Block D
16027  */
16028 #define CAAM_REND_REPO(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK)
16029 
16030 #define CAAM_REND_RBS_MASK                       (0xF0U)
16031 #define CAAM_REND_RBS_SHIFT                      (4U)
16032 /*! RBS
16033  *  0bxxx1..Byte Swap Memory Block A
16034  *  0bxx1x..Byte Swap Memory Block B
16035  *  0bx1xx..Byte Swap Memory Block C
16036  *  0b1xxx..Byte Swap Memory Block D
16037  */
16038 #define CAAM_REND_RBS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK)
16039 
16040 #define CAAM_REND_RHWS_MASK                      (0xF00U)
16041 #define CAAM_REND_RHWS_SHIFT                     (8U)
16042 /*! RHWS
16043  *  0bxxx1..Half-Word Swap Memory Block A
16044  *  0bxx1x..Half-Word Swap Memory Block B
16045  *  0bx1xx..Half-Word Swap Memory Block C
16046  *  0b1xxx..Half-Word Swap Memory Block D
16047  */
16048 #define CAAM_REND_RHWS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK)
16049 
16050 #define CAAM_REND_RWS_MASK                       (0xF000U)
16051 #define CAAM_REND_RWS_SHIFT                      (12U)
16052 /*! RWS
16053  *  0bxxx1..Word Swap Memory Block A
16054  *  0bxx1x..Word Swap Memory Block B
16055  *  0bx1xx..Word Swap Memory Block C
16056  *  0b1xxx..Word Swap Memory Block D
16057  */
16058 #define CAAM_REND_RWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK)
16059 /*! @} */
16060 
16061 /*! @name RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register */
16062 /*! @{ */
16063 
16064 #define CAAM_RMA_MEMBLKADDR_MASK                 (0xFFFFFFFFFU)
16065 #define CAAM_RMA_MEMBLKADDR_SHIFT                (0U)
16066 #define CAAM_RMA_MEMBLKADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK)
16067 /*! @} */
16068 
16069 /* The count of CAAM_RMA */
16070 #define CAAM_RMA_COUNT                           (4U)
16071 
16072 /* The count of CAAM_RMA */
16073 #define CAAM_RMA_COUNT2                          (2U)
16074 
16075 /*! @name RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register */
16076 /*! @{ */
16077 
16078 #define CAAM_RML_MEMBLKLEN_MASK                  (0xFFFFFFFFU)
16079 #define CAAM_RML_MEMBLKLEN_SHIFT                 (0U)
16080 #define CAAM_RML_MEMBLKLEN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK)
16081 /*! @} */
16082 
16083 /* The count of CAAM_RML */
16084 #define CAAM_RML_COUNT                           (4U)
16085 
16086 /* The count of CAAM_RML */
16087 #define CAAM_RML_COUNT2                          (2U)
16088 
16089 /*! @name RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 */
16090 /*! @{ */
16091 
16092 #define CAAM_RMD_RTIC_Hash_Result_MASK           (0xFFFFFFFFU)
16093 #define CAAM_RMD_RTIC_Hash_Result_SHIFT          (0U)
16094 #define CAAM_RMD_RTIC_Hash_Result(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK)
16095 /*! @} */
16096 
16097 /* The count of CAAM_RMD */
16098 #define CAAM_RMD_COUNT                           (4U)
16099 
16100 /* The count of CAAM_RMD */
16101 #define CAAM_RMD_COUNT2                          (2U)
16102 
16103 /* The count of CAAM_RMD */
16104 #define CAAM_RMD_COUNT3                          (32U)
16105 
16106 /*! @name REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC */
16107 /*! @{ */
16108 
16109 #define CAAM_REIR0RTIC_TYPE_MASK                 (0x3000000U)
16110 #define CAAM_REIR0RTIC_TYPE_SHIFT                (24U)
16111 #define CAAM_REIR0RTIC_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK)
16112 
16113 #define CAAM_REIR0RTIC_MISS_MASK                 (0x80000000U)
16114 #define CAAM_REIR0RTIC_MISS_SHIFT                (31U)
16115 #define CAAM_REIR0RTIC_MISS(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK)
16116 /*! @} */
16117 
16118 /*! @name REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC */
16119 /*! @{ */
16120 
16121 #define CAAM_REIR2RTIC_ADDR_MASK                 (0xFFFFFFFFFFFFFFFFU)
16122 #define CAAM_REIR2RTIC_ADDR_SHIFT                (0U)
16123 #define CAAM_REIR2RTIC_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK)
16124 /*! @} */
16125 
16126 /*! @name REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC */
16127 /*! @{ */
16128 
16129 #define CAAM_REIR4RTIC_ICID_MASK                 (0x7FFU)
16130 #define CAAM_REIR4RTIC_ICID_SHIFT                (0U)
16131 #define CAAM_REIR4RTIC_ICID(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK)
16132 
16133 #define CAAM_REIR4RTIC_DID_MASK                  (0x7800U)
16134 #define CAAM_REIR4RTIC_DID_SHIFT                 (11U)
16135 #define CAAM_REIR4RTIC_DID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK)
16136 
16137 #define CAAM_REIR4RTIC_AXCACHE_MASK              (0xF0000U)
16138 #define CAAM_REIR4RTIC_AXCACHE_SHIFT             (16U)
16139 #define CAAM_REIR4RTIC_AXCACHE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK)
16140 
16141 #define CAAM_REIR4RTIC_AXPROT_MASK               (0x700000U)
16142 #define CAAM_REIR4RTIC_AXPROT_SHIFT              (20U)
16143 #define CAAM_REIR4RTIC_AXPROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK)
16144 
16145 #define CAAM_REIR4RTIC_RWB_MASK                  (0x800000U)
16146 #define CAAM_REIR4RTIC_RWB_SHIFT                 (23U)
16147 #define CAAM_REIR4RTIC_RWB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK)
16148 
16149 #define CAAM_REIR4RTIC_ERR_MASK                  (0x30000000U)
16150 #define CAAM_REIR4RTIC_ERR_SHIFT                 (28U)
16151 #define CAAM_REIR4RTIC_ERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK)
16152 
16153 #define CAAM_REIR4RTIC_MIX_MASK                  (0xC0000000U)
16154 #define CAAM_REIR4RTIC_MIX_SHIFT                 (30U)
16155 #define CAAM_REIR4RTIC_MIX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK)
16156 /*! @} */
16157 
16158 /*! @name REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC */
16159 /*! @{ */
16160 
16161 #define CAAM_REIR5RTIC_BID_MASK                  (0xF0000U)
16162 #define CAAM_REIR5RTIC_BID_SHIFT                 (16U)
16163 #define CAAM_REIR5RTIC_BID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK)
16164 
16165 #define CAAM_REIR5RTIC_SAFE_MASK                 (0x1000000U)
16166 #define CAAM_REIR5RTIC_SAFE_SHIFT                (24U)
16167 #define CAAM_REIR5RTIC_SAFE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK)
16168 
16169 #define CAAM_REIR5RTIC_SMA_MASK                  (0x2000000U)
16170 #define CAAM_REIR5RTIC_SMA_SHIFT                 (25U)
16171 #define CAAM_REIR5RTIC_SMA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK)
16172 /*! @} */
16173 
16174 /*! @name CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms */
16175 /*! @{ */
16176 
16177 #define CAAM_CC1MR_ENC_MASK                      (0x1U)
16178 #define CAAM_CC1MR_ENC_SHIFT                     (0U)
16179 /*! ENC
16180  *  0b0..Decrypt.
16181  *  0b1..Encrypt.
16182  */
16183 #define CAAM_CC1MR_ENC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK)
16184 
16185 #define CAAM_CC1MR_ICV_TEST_MASK                 (0x2U)
16186 #define CAAM_CC1MR_ICV_TEST_SHIFT                (1U)
16187 #define CAAM_CC1MR_ICV_TEST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK)
16188 
16189 #define CAAM_CC1MR_AS_MASK                       (0xCU)
16190 #define CAAM_CC1MR_AS_SHIFT                      (2U)
16191 /*! AS
16192  *  0b00..Update
16193  *  0b01..Initialize
16194  *  0b10..Finalize
16195  *  0b11..Initialize/Finalize
16196  */
16197 #define CAAM_CC1MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK)
16198 
16199 #define CAAM_CC1MR_AAI_MASK                      (0x1FF0U)
16200 #define CAAM_CC1MR_AAI_SHIFT                     (4U)
16201 #define CAAM_CC1MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK)
16202 
16203 #define CAAM_CC1MR_ALG_MASK                      (0xFF0000U)
16204 #define CAAM_CC1MR_ALG_SHIFT                     (16U)
16205 /*! ALG
16206  *  0b00010000..AES
16207  *  0b00100000..DES
16208  *  0b00100001..3DES
16209  *  0b01010000..RNG
16210  */
16211 #define CAAM_CC1MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK)
16212 /*! @} */
16213 
16214 /* The count of CAAM_CC1MR */
16215 #define CAAM_CC1MR_COUNT                         (1U)
16216 
16217 /*! @name CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms */
16218 /*! @{ */
16219 
16220 #define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK          (0xFFFU)
16221 #define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT         (0U)
16222 #define CAAM_CC1MR_PK_PKHA_MODE_LS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK)
16223 
16224 #define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK          (0xF0000U)
16225 #define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT         (16U)
16226 #define CAAM_CC1MR_PK_PKHA_MODE_MS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK)
16227 /*! @} */
16228 
16229 /* The count of CAAM_CC1MR_PK */
16230 #define CAAM_CC1MR_PK_COUNT                      (1U)
16231 
16232 /*! @name CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 */
16233 /*! @{ */
16234 
16235 #define CAAM_CC1MR_RNG_TST_MASK                  (0x1U)
16236 #define CAAM_CC1MR_RNG_TST_SHIFT                 (0U)
16237 #define CAAM_CC1MR_RNG_TST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK)
16238 
16239 #define CAAM_CC1MR_RNG_PR_MASK                   (0x2U)
16240 #define CAAM_CC1MR_RNG_PR_SHIFT                  (1U)
16241 #define CAAM_CC1MR_RNG_PR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK)
16242 
16243 #define CAAM_CC1MR_RNG_AS_MASK                   (0xCU)
16244 #define CAAM_CC1MR_RNG_AS_SHIFT                  (2U)
16245 #define CAAM_CC1MR_RNG_AS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK)
16246 
16247 #define CAAM_CC1MR_RNG_SH_MASK                   (0x30U)
16248 #define CAAM_CC1MR_RNG_SH_SHIFT                  (4U)
16249 /*! SH
16250  *  0b00..State Handle 0
16251  *  0b01..State Handle 1
16252  *  0b10..Reserved
16253  *  0b11..Reserved
16254  */
16255 #define CAAM_CC1MR_RNG_SH(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK)
16256 
16257 #define CAAM_CC1MR_RNG_NZB_MASK                  (0x100U)
16258 #define CAAM_CC1MR_RNG_NZB_SHIFT                 (8U)
16259 /*! NZB
16260  *  0b0..Generate random data with all-zero bytes permitted.
16261  *  0b1..Generate random data without any all-zero bytes.
16262  */
16263 #define CAAM_CC1MR_RNG_NZB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK)
16264 
16265 #define CAAM_CC1MR_RNG_OBP_MASK                  (0x200U)
16266 #define CAAM_CC1MR_RNG_OBP_SHIFT                 (9U)
16267 /*! OBP
16268  *  0b0..No odd byte parity.
16269  *  0b1..Generate random data with odd byte parity.
16270  */
16271 #define CAAM_CC1MR_RNG_OBP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK)
16272 
16273 #define CAAM_CC1MR_RNG_PS_MASK                   (0x400U)
16274 #define CAAM_CC1MR_RNG_PS_SHIFT                  (10U)
16275 /*! PS
16276  *  0b0..No personalization string is included.
16277  *  0b1..A personalization string is included.
16278  */
16279 #define CAAM_CC1MR_RNG_PS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK)
16280 
16281 #define CAAM_CC1MR_RNG_AI_MASK                   (0x800U)
16282 #define CAAM_CC1MR_RNG_AI_SHIFT                  (11U)
16283 /*! AI
16284  *  0b0..No additional entropy input has been provided.
16285  *  0b1..Additional entropy input has been provided.
16286  */
16287 #define CAAM_CC1MR_RNG_AI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK)
16288 
16289 #define CAAM_CC1MR_RNG_SK_MASK                   (0x1000U)
16290 #define CAAM_CC1MR_RNG_SK_SHIFT                  (12U)
16291 /*! SK
16292  *  0b0..The destination for the RNG data is specified by the FIFO STORE command.
16293  *  0b1..The RNG data will go to the JDKEKR, TDKEKR and DSKR.
16294  */
16295 #define CAAM_CC1MR_RNG_SK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK)
16296 
16297 #define CAAM_CC1MR_RNG_ALG_MASK                  (0xFF0000U)
16298 #define CAAM_CC1MR_RNG_ALG_SHIFT                 (16U)
16299 /*! ALG
16300  *  0b01010000..RNG
16301  */
16302 #define CAAM_CC1MR_RNG_ALG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK)
16303 /*! @} */
16304 
16305 /* The count of CAAM_CC1MR_RNG */
16306 #define CAAM_CC1MR_RNG_COUNT                     (1U)
16307 
16308 /*! @name CC1KSR - CCB 0 Class 1 Key Size Register */
16309 /*! @{ */
16310 
16311 #define CAAM_CC1KSR_C1KS_MASK                    (0x7FU)
16312 #define CAAM_CC1KSR_C1KS_SHIFT                   (0U)
16313 #define CAAM_CC1KSR_C1KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK)
16314 /*! @} */
16315 
16316 /* The count of CAAM_CC1KSR */
16317 #define CAAM_CC1KSR_COUNT                        (1U)
16318 
16319 /*! @name CC1DSR - CCB 0 Class 1 Data Size Register */
16320 /*! @{ */
16321 
16322 #define CAAM_CC1DSR_C1DS_MASK                    (0xFFFFFFFFU)
16323 #define CAAM_CC1DSR_C1DS_SHIFT                   (0U)
16324 #define CAAM_CC1DSR_C1DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK)
16325 
16326 #define CAAM_CC1DSR_C1CY_MASK                    (0x100000000U)
16327 #define CAAM_CC1DSR_C1CY_SHIFT                   (32U)
16328 /*! C1CY
16329  *  0b0..No carry out of the C1 Data Size Reg.
16330  *  0b1..There was a carry out of the C1 Data Size Reg.
16331  */
16332 #define CAAM_CC1DSR_C1CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK)
16333 
16334 #define CAAM_CC1DSR_NUMBITS_MASK                 (0xE000000000000000U)
16335 #define CAAM_CC1DSR_NUMBITS_SHIFT                (61U)
16336 #define CAAM_CC1DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK)
16337 /*! @} */
16338 
16339 /* The count of CAAM_CC1DSR */
16340 #define CAAM_CC1DSR_COUNT                        (1U)
16341 
16342 /*! @name CC1ICVSR - CCB 0 Class 1 ICV Size Register */
16343 /*! @{ */
16344 
16345 #define CAAM_CC1ICVSR_C1ICVS_MASK                (0x1FU)
16346 #define CAAM_CC1ICVSR_C1ICVS_SHIFT               (0U)
16347 #define CAAM_CC1ICVSR_C1ICVS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK)
16348 /*! @} */
16349 
16350 /* The count of CAAM_CC1ICVSR */
16351 #define CAAM_CC1ICVSR_COUNT                      (1U)
16352 
16353 /*! @name CCCTRL - CCB 0 CHA Control Register */
16354 /*! @{ */
16355 
16356 #define CAAM_CCCTRL_CCB_MASK                     (0x1U)
16357 #define CAAM_CCCTRL_CCB_SHIFT                    (0U)
16358 /*! CCB
16359  *  0b0..Do Not Reset
16360  *  0b1..Reset CCB
16361  */
16362 #define CAAM_CCCTRL_CCB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK)
16363 
16364 #define CAAM_CCCTRL_AES_MASK                     (0x2U)
16365 #define CAAM_CCCTRL_AES_SHIFT                    (1U)
16366 /*! AES
16367  *  0b0..Do Not Reset
16368  *  0b1..Reset AES Accelerator
16369  */
16370 #define CAAM_CCCTRL_AES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK)
16371 
16372 #define CAAM_CCCTRL_DES_MASK                     (0x4U)
16373 #define CAAM_CCCTRL_DES_SHIFT                    (2U)
16374 /*! DES
16375  *  0b0..Do Not Reset
16376  *  0b1..Reset DES Accelerator
16377  */
16378 #define CAAM_CCCTRL_DES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK)
16379 
16380 #define CAAM_CCCTRL_PK_MASK                      (0x40U)
16381 #define CAAM_CCCTRL_PK_SHIFT                     (6U)
16382 /*! PK
16383  *  0b0..Do Not Reset
16384  *  0b1..Reset Public Key Hardware Accelerator
16385  */
16386 #define CAAM_CCCTRL_PK(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK)
16387 
16388 #define CAAM_CCCTRL_MD_MASK                      (0x80U)
16389 #define CAAM_CCCTRL_MD_SHIFT                     (7U)
16390 /*! MD
16391  *  0b0..Do Not Reset
16392  *  0b1..Reset Message Digest Hardware Accelerator
16393  */
16394 #define CAAM_CCCTRL_MD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK)
16395 
16396 #define CAAM_CCCTRL_CRC_MASK                     (0x100U)
16397 #define CAAM_CCCTRL_CRC_SHIFT                    (8U)
16398 /*! CRC
16399  *  0b0..Do Not Reset
16400  *  0b1..Reset CRC Accelerator
16401  */
16402 #define CAAM_CCCTRL_CRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK)
16403 
16404 #define CAAM_CCCTRL_RNG_MASK                     (0x200U)
16405 #define CAAM_CCCTRL_RNG_SHIFT                    (9U)
16406 /*! RNG
16407  *  0b0..Do Not Reset
16408  *  0b1..Reset Random Number Generator Block.
16409  */
16410 #define CAAM_CCCTRL_RNG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK)
16411 
16412 #define CAAM_CCCTRL_UA0_MASK                     (0x10000U)
16413 #define CAAM_CCCTRL_UA0_SHIFT                    (16U)
16414 /*! UA0
16415  *  0b0..Don't unload the PKHA A0 Memory.
16416  *  0b1..Unload the PKHA A0 Memory into OFIFO.
16417  */
16418 #define CAAM_CCCTRL_UA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK)
16419 
16420 #define CAAM_CCCTRL_UA1_MASK                     (0x20000U)
16421 #define CAAM_CCCTRL_UA1_SHIFT                    (17U)
16422 /*! UA1
16423  *  0b0..Don't unload the PKHA A1 Memory.
16424  *  0b1..Unload the PKHA A1 Memory into OFIFO.
16425  */
16426 #define CAAM_CCCTRL_UA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK)
16427 
16428 #define CAAM_CCCTRL_UA2_MASK                     (0x40000U)
16429 #define CAAM_CCCTRL_UA2_SHIFT                    (18U)
16430 /*! UA2
16431  *  0b0..Don't unload the PKHA A2 Memory.
16432  *  0b1..Unload the PKHA A2 Memory into OFIFO.
16433  */
16434 #define CAAM_CCCTRL_UA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK)
16435 
16436 #define CAAM_CCCTRL_UA3_MASK                     (0x80000U)
16437 #define CAAM_CCCTRL_UA3_SHIFT                    (19U)
16438 /*! UA3
16439  *  0b0..Don't unload the PKHA A3 Memory.
16440  *  0b1..Unload the PKHA A3 Memory into OFIFO.
16441  */
16442 #define CAAM_CCCTRL_UA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK)
16443 
16444 #define CAAM_CCCTRL_UB0_MASK                     (0x100000U)
16445 #define CAAM_CCCTRL_UB0_SHIFT                    (20U)
16446 /*! UB0
16447  *  0b0..Don't unload the PKHA B0 Memory.
16448  *  0b1..Unload the PKHA B0 Memory into OFIFO.
16449  */
16450 #define CAAM_CCCTRL_UB0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK)
16451 
16452 #define CAAM_CCCTRL_UB1_MASK                     (0x200000U)
16453 #define CAAM_CCCTRL_UB1_SHIFT                    (21U)
16454 /*! UB1
16455  *  0b0..Don't unload the PKHA B1 Memory.
16456  *  0b1..Unload the PKHA B1 Memory into OFIFO.
16457  */
16458 #define CAAM_CCCTRL_UB1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK)
16459 
16460 #define CAAM_CCCTRL_UB2_MASK                     (0x400000U)
16461 #define CAAM_CCCTRL_UB2_SHIFT                    (22U)
16462 /*! UB2
16463  *  0b0..Don't unload the PKHA B2 Memory.
16464  *  0b1..Unload the PKHA B2 Memory into OFIFO.
16465  */
16466 #define CAAM_CCCTRL_UB2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK)
16467 
16468 #define CAAM_CCCTRL_UB3_MASK                     (0x800000U)
16469 #define CAAM_CCCTRL_UB3_SHIFT                    (23U)
16470 /*! UB3
16471  *  0b0..Don't unload the PKHA B3 Memory.
16472  *  0b1..Unload the PKHA B3 Memory into OFIFO.
16473  */
16474 #define CAAM_CCCTRL_UB3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK)
16475 
16476 #define CAAM_CCCTRL_UN_MASK                      (0x1000000U)
16477 #define CAAM_CCCTRL_UN_SHIFT                     (24U)
16478 /*! UN
16479  *  0b0..Don't unload the PKHA N Memory.
16480  *  0b1..Unload the PKHA N Memory into OFIFO.
16481  */
16482 #define CAAM_CCCTRL_UN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK)
16483 
16484 #define CAAM_CCCTRL_UA_MASK                      (0x4000000U)
16485 #define CAAM_CCCTRL_UA_SHIFT                     (26U)
16486 /*! UA
16487  *  0b0..Don't unload the PKHA A Memory.
16488  *  0b1..Unload the PKHA A Memory into OFIFO.
16489  */
16490 #define CAAM_CCCTRL_UA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK)
16491 
16492 #define CAAM_CCCTRL_UB_MASK                      (0x8000000U)
16493 #define CAAM_CCCTRL_UB_SHIFT                     (27U)
16494 /*! UB
16495  *  0b0..Don't unload the PKHA B Memory.
16496  *  0b1..Unload the PKHA B Memory into OFIFO.
16497  */
16498 #define CAAM_CCCTRL_UB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK)
16499 /*! @} */
16500 
16501 /* The count of CAAM_CCCTRL */
16502 #define CAAM_CCCTRL_COUNT                        (1U)
16503 
16504 /*! @name CICTL - CCB 0 Interrupt Control Register */
16505 /*! @{ */
16506 
16507 #define CAAM_CICTL_ADI_MASK                      (0x2U)
16508 #define CAAM_CICTL_ADI_SHIFT                     (1U)
16509 #define CAAM_CICTL_ADI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK)
16510 
16511 #define CAAM_CICTL_DDI_MASK                      (0x4U)
16512 #define CAAM_CICTL_DDI_SHIFT                     (2U)
16513 #define CAAM_CICTL_DDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK)
16514 
16515 #define CAAM_CICTL_PDI_MASK                      (0x40U)
16516 #define CAAM_CICTL_PDI_SHIFT                     (6U)
16517 #define CAAM_CICTL_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK)
16518 
16519 #define CAAM_CICTL_MDI_MASK                      (0x80U)
16520 #define CAAM_CICTL_MDI_SHIFT                     (7U)
16521 #define CAAM_CICTL_MDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK)
16522 
16523 #define CAAM_CICTL_CDI_MASK                      (0x100U)
16524 #define CAAM_CICTL_CDI_SHIFT                     (8U)
16525 #define CAAM_CICTL_CDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK)
16526 
16527 #define CAAM_CICTL_RNDI_MASK                     (0x200U)
16528 #define CAAM_CICTL_RNDI_SHIFT                    (9U)
16529 #define CAAM_CICTL_RNDI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK)
16530 
16531 #define CAAM_CICTL_AEI_MASK                      (0x20000U)
16532 #define CAAM_CICTL_AEI_SHIFT                     (17U)
16533 /*! AEI
16534  *  0b0..No AESA error detected
16535  *  0b1..AESA error detected
16536  */
16537 #define CAAM_CICTL_AEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK)
16538 
16539 #define CAAM_CICTL_DEI_MASK                      (0x40000U)
16540 #define CAAM_CICTL_DEI_SHIFT                     (18U)
16541 /*! DEI
16542  *  0b0..No DESA error detected
16543  *  0b1..DESA error detected
16544  */
16545 #define CAAM_CICTL_DEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK)
16546 
16547 #define CAAM_CICTL_PEI_MASK                      (0x400000U)
16548 #define CAAM_CICTL_PEI_SHIFT                     (22U)
16549 /*! PEI
16550  *  0b0..No PKHA error detected
16551  *  0b1..PKHA error detected
16552  */
16553 #define CAAM_CICTL_PEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK)
16554 
16555 #define CAAM_CICTL_MEI_MASK                      (0x800000U)
16556 #define CAAM_CICTL_MEI_SHIFT                     (23U)
16557 /*! MEI
16558  *  0b0..No MDHA error detected
16559  *  0b1..MDHA error detected
16560  */
16561 #define CAAM_CICTL_MEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK)
16562 
16563 #define CAAM_CICTL_CEI_MASK                      (0x1000000U)
16564 #define CAAM_CICTL_CEI_SHIFT                     (24U)
16565 /*! CEI
16566  *  0b0..No CRCA error detected
16567  *  0b1..CRCA error detected
16568  */
16569 #define CAAM_CICTL_CEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK)
16570 
16571 #define CAAM_CICTL_RNEI_MASK                     (0x2000000U)
16572 #define CAAM_CICTL_RNEI_SHIFT                    (25U)
16573 /*! RNEI
16574  *  0b0..No RNG error detected
16575  *  0b1..RNG error detected
16576  */
16577 #define CAAM_CICTL_RNEI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK)
16578 /*! @} */
16579 
16580 /* The count of CAAM_CICTL */
16581 #define CAAM_CICTL_COUNT                         (1U)
16582 
16583 /*! @name CCWR - CCB 0 Clear Written Register */
16584 /*! @{ */
16585 
16586 #define CAAM_CCWR_C1M_MASK                       (0x1U)
16587 #define CAAM_CCWR_C1M_SHIFT                      (0U)
16588 /*! C1M
16589  *  0b0..Don't clear the Class 1 Mode Register.
16590  *  0b1..Clear the Class 1 Mode Register.
16591  */
16592 #define CAAM_CCWR_C1M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK)
16593 
16594 #define CAAM_CCWR_C1DS_MASK                      (0x4U)
16595 #define CAAM_CCWR_C1DS_SHIFT                     (2U)
16596 /*! C1DS
16597  *  0b0..Don't clear the Class 1 Data Size Register.
16598  *  0b1..Clear the Class 1 Data Size Register.
16599  */
16600 #define CAAM_CCWR_C1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK)
16601 
16602 #define CAAM_CCWR_C1ICV_MASK                     (0x8U)
16603 #define CAAM_CCWR_C1ICV_SHIFT                    (3U)
16604 /*! C1ICV
16605  *  0b0..Don't clear the Class 1 ICV Size Register.
16606  *  0b1..Clear the Class 1 ICV Size Register.
16607  */
16608 #define CAAM_CCWR_C1ICV(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK)
16609 
16610 #define CAAM_CCWR_C1C_MASK                       (0x20U)
16611 #define CAAM_CCWR_C1C_SHIFT                      (5U)
16612 /*! C1C
16613  *  0b0..Don't clear the Class 1 Context Register.
16614  *  0b1..Clear the Class 1 Context Register.
16615  */
16616 #define CAAM_CCWR_C1C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK)
16617 
16618 #define CAAM_CCWR_C1K_MASK                       (0x40U)
16619 #define CAAM_CCWR_C1K_SHIFT                      (6U)
16620 /*! C1K
16621  *  0b0..Don't clear the Class 1 Key Register.
16622  *  0b1..Clear the Class 1 Key Register.
16623  */
16624 #define CAAM_CCWR_C1K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK)
16625 
16626 #define CAAM_CCWR_CPKA_MASK                      (0x1000U)
16627 #define CAAM_CCWR_CPKA_SHIFT                     (12U)
16628 /*! CPKA
16629  *  0b0..Don't clear the PKHA A Size Register.
16630  *  0b1..Clear the PKHA A Size Register.
16631  */
16632 #define CAAM_CCWR_CPKA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK)
16633 
16634 #define CAAM_CCWR_CPKB_MASK                      (0x2000U)
16635 #define CAAM_CCWR_CPKB_SHIFT                     (13U)
16636 /*! CPKB
16637  *  0b0..Don't clear the PKHA B Size Register.
16638  *  0b1..Clear the PKHA B Size Register.
16639  */
16640 #define CAAM_CCWR_CPKB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK)
16641 
16642 #define CAAM_CCWR_CPKN_MASK                      (0x4000U)
16643 #define CAAM_CCWR_CPKN_SHIFT                     (14U)
16644 /*! CPKN
16645  *  0b0..Don't clear the PKHA N Size Register.
16646  *  0b1..Clear the PKHA N Size Register.
16647  */
16648 #define CAAM_CCWR_CPKN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK)
16649 
16650 #define CAAM_CCWR_CPKE_MASK                      (0x8000U)
16651 #define CAAM_CCWR_CPKE_SHIFT                     (15U)
16652 /*! CPKE
16653  *  0b0..Don't clear the PKHA E Size Register..
16654  *  0b1..Clear the PKHA E Size Register.
16655  */
16656 #define CAAM_CCWR_CPKE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK)
16657 
16658 #define CAAM_CCWR_C2M_MASK                       (0x10000U)
16659 #define CAAM_CCWR_C2M_SHIFT                      (16U)
16660 /*! C2M
16661  *  0b0..Don't clear the Class 2 Mode Register.
16662  *  0b1..Clear the Class 2 Mode Register.
16663  */
16664 #define CAAM_CCWR_C2M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK)
16665 
16666 #define CAAM_CCWR_C2DS_MASK                      (0x40000U)
16667 #define CAAM_CCWR_C2DS_SHIFT                     (18U)
16668 /*! C2DS
16669  *  0b0..Don't clear the Class 2 Data Size Register.
16670  *  0b1..Clear the Class 2 Data Size Register.
16671  */
16672 #define CAAM_CCWR_C2DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK)
16673 
16674 #define CAAM_CCWR_C2C_MASK                       (0x200000U)
16675 #define CAAM_CCWR_C2C_SHIFT                      (21U)
16676 /*! C2C
16677  *  0b0..Don't clear the Class 2 Context Register.
16678  *  0b1..Clear the Class 2 Context Register.
16679  */
16680 #define CAAM_CCWR_C2C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK)
16681 
16682 #define CAAM_CCWR_C2K_MASK                       (0x400000U)
16683 #define CAAM_CCWR_C2K_SHIFT                      (22U)
16684 /*! C2K
16685  *  0b0..Don't clear the Class 2 Key Register.
16686  *  0b1..Clear the Class 2 Key Register.
16687  */
16688 #define CAAM_CCWR_C2K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK)
16689 
16690 #define CAAM_CCWR_CDS_MASK                       (0x2000000U)
16691 #define CAAM_CCWR_CDS_SHIFT                      (25U)
16692 /*! CDS
16693  *  0b0..Don't clear the shared descriptor signal.
16694  *  0b1..Clear the shared descriptor signal.
16695  */
16696 #define CAAM_CCWR_CDS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK)
16697 
16698 #define CAAM_CCWR_C2D_MASK                       (0x4000000U)
16699 #define CAAM_CCWR_C2D_SHIFT                      (26U)
16700 /*! C2D
16701  *  0b0..Don't clear the Class 2 done interrrupt.
16702  *  0b1..Clear the Class 2 done interrrupt.
16703  */
16704 #define CAAM_CCWR_C2D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK)
16705 
16706 #define CAAM_CCWR_C1D_MASK                       (0x8000000U)
16707 #define CAAM_CCWR_C1D_SHIFT                      (27U)
16708 /*! C1D
16709  *  0b0..Don't clear the Class 1 done interrrupt.
16710  *  0b1..Clear the Class 1 done interrrupt.
16711  */
16712 #define CAAM_CCWR_C1D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK)
16713 
16714 #define CAAM_CCWR_C2RST_MASK                     (0x10000000U)
16715 #define CAAM_CCWR_C2RST_SHIFT                    (28U)
16716 /*! C2RST
16717  *  0b0..Don't reset the Class 2 CHA.
16718  *  0b1..Reset the Class 2 CHA.
16719  */
16720 #define CAAM_CCWR_C2RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK)
16721 
16722 #define CAAM_CCWR_C1RST_MASK                     (0x20000000U)
16723 #define CAAM_CCWR_C1RST_SHIFT                    (29U)
16724 /*! C1RST
16725  *  0b0..Don't reset the Class 1 CHA.
16726  *  0b1..Reset the Class 1 CHA.
16727  */
16728 #define CAAM_CCWR_C1RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK)
16729 
16730 #define CAAM_CCWR_COF_MASK                       (0x40000000U)
16731 #define CAAM_CCWR_COF_SHIFT                      (30U)
16732 /*! COF
16733  *  0b0..Don't clear the OFIFO.
16734  *  0b1..Clear the OFIFO.
16735  */
16736 #define CAAM_CCWR_COF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK)
16737 
16738 #define CAAM_CCWR_CIF_MASK                       (0x80000000U)
16739 #define CAAM_CCWR_CIF_SHIFT                      (31U)
16740 /*! CIF
16741  *  0b0..Don't clear the IFIFO.
16742  *  0b1..Clear the IFIFO.
16743  */
16744 #define CAAM_CCWR_CIF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK)
16745 /*! @} */
16746 
16747 /* The count of CAAM_CCWR */
16748 #define CAAM_CCWR_COUNT                          (1U)
16749 
16750 /*! @name CCSTA_MS - CCB 0 Status and Error Register, most-significant half */
16751 /*! @{ */
16752 
16753 #define CAAM_CCSTA_MS_ERRID1_MASK                (0xFU)
16754 #define CAAM_CCSTA_MS_ERRID1_SHIFT               (0U)
16755 /*! ERRID1
16756  *  0b0001..Mode Error
16757  *  0b0010..Data Size Error, including PKHA N Memory Size Error
16758  *  0b0011..Key Size Error, including PKHA E Memory Size Error
16759  *  0b0100..PKHA A Memory Size Error
16760  *  0b0101..PKHA B Memory Size Error
16761  *  0b0110..Data Arrived out of Sequence Error
16762  *  0b0111..PKHA Divide by Zero Error
16763  *  0b1000..PKHA Modulus Even Error
16764  *  0b1001..DES Key Parity Error
16765  *  0b1010..ICV Check Failed
16766  *  0b1011..Internal Hardware Failure
16767  *  0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and
16768  *          AAD provided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
16769  *  0b1101..Class 1 CHA is not reset
16770  *  0b1110..Invalid CHA combination was selected
16771  *  0b1111..Invalid CHA Selected
16772  */
16773 #define CAAM_CCSTA_MS_ERRID1(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK)
16774 
16775 #define CAAM_CCSTA_MS_CL1_MASK                   (0xF000U)
16776 #define CAAM_CCSTA_MS_CL1_SHIFT                  (12U)
16777 /*! CL1
16778  *  0b0001..AES
16779  *  0b0010..DES
16780  *  0b0101..RNG
16781  *  0b1000..Public Key
16782  */
16783 #define CAAM_CCSTA_MS_CL1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK)
16784 
16785 #define CAAM_CCSTA_MS_ERRID2_MASK                (0xF0000U)
16786 #define CAAM_CCSTA_MS_ERRID2_SHIFT               (16U)
16787 /*! ERRID2
16788  *  0b0001..Mode Error
16789  *  0b0010..Data Size Error
16790  *  0b0011..Key Size Error
16791  *  0b0110..Data Arrived out of Sequence Error
16792  *  0b1010..ICV Check Failed
16793  *  0b1011..Internal Hardware Failure
16794  *  0b1110..Invalid CHA combination was selected.
16795  *  0b1111..Invalid CHA Selected
16796  */
16797 #define CAAM_CCSTA_MS_ERRID2(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK)
16798 
16799 #define CAAM_CCSTA_MS_CL2_MASK                   (0xF0000000U)
16800 #define CAAM_CCSTA_MS_CL2_SHIFT                  (28U)
16801 /*! CL2
16802  *  0b0100..MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and SHA-512/224, SHA-512/256
16803  *  0b1001..CRC
16804  */
16805 #define CAAM_CCSTA_MS_CL2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK)
16806 /*! @} */
16807 
16808 /* The count of CAAM_CCSTA_MS */
16809 #define CAAM_CCSTA_MS_COUNT                      (1U)
16810 
16811 /*! @name CCSTA_LS - CCB 0 Status and Error Register, least-significant half */
16812 /*! @{ */
16813 
16814 #define CAAM_CCSTA_LS_AB_MASK                    (0x2U)
16815 #define CAAM_CCSTA_LS_AB_SHIFT                   (1U)
16816 /*! AB
16817  *  0b0..AESA Idle
16818  *  0b1..AESA Busy
16819  */
16820 #define CAAM_CCSTA_LS_AB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK)
16821 
16822 #define CAAM_CCSTA_LS_DB_MASK                    (0x4U)
16823 #define CAAM_CCSTA_LS_DB_SHIFT                   (2U)
16824 /*! DB
16825  *  0b0..DESA Idle
16826  *  0b1..DESA Busy
16827  */
16828 #define CAAM_CCSTA_LS_DB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK)
16829 
16830 #define CAAM_CCSTA_LS_PB_MASK                    (0x40U)
16831 #define CAAM_CCSTA_LS_PB_SHIFT                   (6U)
16832 /*! PB
16833  *  0b0..PKHA Idle
16834  *  0b1..PKHA Busy
16835  */
16836 #define CAAM_CCSTA_LS_PB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK)
16837 
16838 #define CAAM_CCSTA_LS_MB_MASK                    (0x80U)
16839 #define CAAM_CCSTA_LS_MB_SHIFT                   (7U)
16840 /*! MB
16841  *  0b0..MDHA Idle
16842  *  0b1..MDHA Busy
16843  */
16844 #define CAAM_CCSTA_LS_MB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK)
16845 
16846 #define CAAM_CCSTA_LS_CB_MASK                    (0x100U)
16847 #define CAAM_CCSTA_LS_CB_SHIFT                   (8U)
16848 /*! CB
16849  *  0b0..CRCA Idle
16850  *  0b1..CRCA Busy
16851  */
16852 #define CAAM_CCSTA_LS_CB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK)
16853 
16854 #define CAAM_CCSTA_LS_RNB_MASK                   (0x200U)
16855 #define CAAM_CCSTA_LS_RNB_SHIFT                  (9U)
16856 /*! RNB
16857  *  0b0..RNG Idle
16858  *  0b1..RNG Busy
16859  */
16860 #define CAAM_CCSTA_LS_RNB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK)
16861 
16862 #define CAAM_CCSTA_LS_PDI_MASK                   (0x10000U)
16863 #define CAAM_CCSTA_LS_PDI_SHIFT                  (16U)
16864 /*! PDI
16865  *  0b0..Not Done
16866  *  0b1..Done Interrupt
16867  */
16868 #define CAAM_CCSTA_LS_PDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK)
16869 
16870 #define CAAM_CCSTA_LS_SDI_MASK                   (0x20000U)
16871 #define CAAM_CCSTA_LS_SDI_SHIFT                  (17U)
16872 /*! SDI
16873  *  0b0..Not Done
16874  *  0b1..Done Interrupt
16875  */
16876 #define CAAM_CCSTA_LS_SDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK)
16877 
16878 #define CAAM_CCSTA_LS_PEI_MASK                   (0x100000U)
16879 #define CAAM_CCSTA_LS_PEI_SHIFT                  (20U)
16880 /*! PEI
16881  *  0b0..No Error
16882  *  0b1..Error Interrupt
16883  */
16884 #define CAAM_CCSTA_LS_PEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK)
16885 
16886 #define CAAM_CCSTA_LS_SEI_MASK                   (0x200000U)
16887 #define CAAM_CCSTA_LS_SEI_SHIFT                  (21U)
16888 /*! SEI
16889  *  0b0..No Error
16890  *  0b1..Error Interrupt
16891  */
16892 #define CAAM_CCSTA_LS_SEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK)
16893 
16894 #define CAAM_CCSTA_LS_PRM_MASK                   (0x10000000U)
16895 #define CAAM_CCSTA_LS_PRM_SHIFT                  (28U)
16896 /*! PRM
16897  *  0b0..The given number is NOT prime.
16898  *  0b1..The given number is probably prime.
16899  */
16900 #define CAAM_CCSTA_LS_PRM(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK)
16901 
16902 #define CAAM_CCSTA_LS_GCD_MASK                   (0x20000000U)
16903 #define CAAM_CCSTA_LS_GCD_SHIFT                  (29U)
16904 /*! GCD
16905  *  0b0..The greatest common divisor of two numbers is NOT one.
16906  *  0b1..The greatest common divisor of two numbers is one.
16907  */
16908 #define CAAM_CCSTA_LS_GCD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK)
16909 
16910 #define CAAM_CCSTA_LS_PIZ_MASK                   (0x40000000U)
16911 #define CAAM_CCSTA_LS_PIZ_SHIFT                  (30U)
16912 /*! PIZ
16913  *  0b0..The result of a Public Key operation is not zero.
16914  *  0b1..The result of a Public Key operation is zero.
16915  */
16916 #define CAAM_CCSTA_LS_PIZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK)
16917 /*! @} */
16918 
16919 /* The count of CAAM_CCSTA_LS */
16920 #define CAAM_CCSTA_LS_COUNT                      (1U)
16921 
16922 /*! @name CC1AADSZR - CCB 0 Class 1 AAD Size Register */
16923 /*! @{ */
16924 
16925 #define CAAM_CC1AADSZR_AASZ_MASK                 (0xFU)
16926 #define CAAM_CC1AADSZR_AASZ_SHIFT                (0U)
16927 #define CAAM_CC1AADSZR_AASZ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK)
16928 /*! @} */
16929 
16930 /* The count of CAAM_CC1AADSZR */
16931 #define CAAM_CC1AADSZR_COUNT                     (1U)
16932 
16933 /*! @name CC1IVSZR - CCB 0 Class 1 IV Size Register */
16934 /*! @{ */
16935 
16936 #define CAAM_CC1IVSZR_IVSZ_MASK                  (0xFU)
16937 #define CAAM_CC1IVSZR_IVSZ_SHIFT                 (0U)
16938 #define CAAM_CC1IVSZR_IVSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK)
16939 /*! @} */
16940 
16941 /* The count of CAAM_CC1IVSZR */
16942 #define CAAM_CC1IVSZR_COUNT                      (1U)
16943 
16944 /*! @name CPKASZR - PKHA A Size Register */
16945 /*! @{ */
16946 
16947 #define CAAM_CPKASZR_PKASZ_MASK                  (0x3FFU)
16948 #define CAAM_CPKASZR_PKASZ_SHIFT                 (0U)
16949 #define CAAM_CPKASZR_PKASZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK)
16950 /*! @} */
16951 
16952 /* The count of CAAM_CPKASZR */
16953 #define CAAM_CPKASZR_COUNT                       (1U)
16954 
16955 /*! @name CPKBSZR - PKHA B Size Register */
16956 /*! @{ */
16957 
16958 #define CAAM_CPKBSZR_PKBSZ_MASK                  (0x3FFU)
16959 #define CAAM_CPKBSZR_PKBSZ_SHIFT                 (0U)
16960 #define CAAM_CPKBSZR_PKBSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK)
16961 /*! @} */
16962 
16963 /* The count of CAAM_CPKBSZR */
16964 #define CAAM_CPKBSZR_COUNT                       (1U)
16965 
16966 /*! @name CPKNSZR - PKHA N Size Register */
16967 /*! @{ */
16968 
16969 #define CAAM_CPKNSZR_PKNSZ_MASK                  (0x3FFU)
16970 #define CAAM_CPKNSZR_PKNSZ_SHIFT                 (0U)
16971 #define CAAM_CPKNSZR_PKNSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK)
16972 /*! @} */
16973 
16974 /* The count of CAAM_CPKNSZR */
16975 #define CAAM_CPKNSZR_COUNT                       (1U)
16976 
16977 /*! @name CPKESZR - PKHA E Size Register */
16978 /*! @{ */
16979 
16980 #define CAAM_CPKESZR_PKESZ_MASK                  (0x3FFU)
16981 #define CAAM_CPKESZR_PKESZ_SHIFT                 (0U)
16982 #define CAAM_CPKESZR_PKESZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK)
16983 /*! @} */
16984 
16985 /* The count of CAAM_CPKESZR */
16986 #define CAAM_CPKESZR_COUNT                       (1U)
16987 
16988 /*! @name CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 */
16989 /*! @{ */
16990 
16991 #define CAAM_CC1CTXR_C1CTX_MASK                  (0xFFFFFFFFU)
16992 #define CAAM_CC1CTXR_C1CTX_SHIFT                 (0U)
16993 #define CAAM_CC1CTXR_C1CTX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK)
16994 /*! @} */
16995 
16996 /* The count of CAAM_CC1CTXR */
16997 #define CAAM_CC1CTXR_COUNT                       (1U)
16998 
16999 /* The count of CAAM_CC1CTXR */
17000 #define CAAM_CC1CTXR_COUNT2                      (16U)
17001 
17002 /*! @name CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 */
17003 /*! @{ */
17004 
17005 #define CAAM_CC1KR_C1KEY_MASK                    (0xFFFFFFFFU)
17006 #define CAAM_CC1KR_C1KEY_SHIFT                   (0U)
17007 #define CAAM_CC1KR_C1KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK)
17008 /*! @} */
17009 
17010 /* The count of CAAM_CC1KR */
17011 #define CAAM_CC1KR_COUNT                         (1U)
17012 
17013 /* The count of CAAM_CC1KR */
17014 #define CAAM_CC1KR_COUNT2                        (8U)
17015 
17016 /*! @name CC2MR - CCB 0 Class 2 Mode Register */
17017 /*! @{ */
17018 
17019 #define CAAM_CC2MR_AP_MASK                       (0x1U)
17020 #define CAAM_CC2MR_AP_SHIFT                      (0U)
17021 /*! AP
17022  *  0b0..Authenticate
17023  *  0b1..Protect
17024  */
17025 #define CAAM_CC2MR_AP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK)
17026 
17027 #define CAAM_CC2MR_ICV_MASK                      (0x2U)
17028 #define CAAM_CC2MR_ICV_SHIFT                     (1U)
17029 /*! ICV
17030  *  0b0..Don't compare the calculated ICV against a received ICV.
17031  *  0b1..Compare the calculated ICV against a received ICV.
17032  */
17033 #define CAAM_CC2MR_ICV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK)
17034 
17035 #define CAAM_CC2MR_AS_MASK                       (0xCU)
17036 #define CAAM_CC2MR_AS_SHIFT                      (2U)
17037 /*! AS
17038  *  0b00..Update.
17039  *  0b01..Initialize.
17040  *  0b10..Finalize.
17041  *  0b11..Initialize/Finalize.
17042  */
17043 #define CAAM_CC2MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK)
17044 
17045 #define CAAM_CC2MR_AAI_MASK                      (0x1FF0U)
17046 #define CAAM_CC2MR_AAI_SHIFT                     (4U)
17047 #define CAAM_CC2MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK)
17048 
17049 #define CAAM_CC2MR_ALG_MASK                      (0xFF0000U)
17050 #define CAAM_CC2MR_ALG_SHIFT                     (16U)
17051 /*! ALG
17052  *  0b01000000..MD5
17053  *  0b01000001..SHA-1
17054  *  0b01000010..SHA-224
17055  *  0b01000011..SHA-256
17056  *  0b01000100..SHA-384
17057  *  0b01000101..SHA-512
17058  *  0b01000110..SHA-512/224
17059  *  0b01000111..SHA-512/256
17060  *  0b10010000..CRC
17061  */
17062 #define CAAM_CC2MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK)
17063 /*! @} */
17064 
17065 /* The count of CAAM_CC2MR */
17066 #define CAAM_CC2MR_COUNT                         (1U)
17067 
17068 /*! @name CC2KSR - CCB 0 Class 2 Key Size Register */
17069 /*! @{ */
17070 
17071 #define CAAM_CC2KSR_C2KS_MASK                    (0xFFU)
17072 #define CAAM_CC2KSR_C2KS_SHIFT                   (0U)
17073 #define CAAM_CC2KSR_C2KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK)
17074 /*! @} */
17075 
17076 /* The count of CAAM_CC2KSR */
17077 #define CAAM_CC2KSR_COUNT                        (1U)
17078 
17079 /*! @name CC2DSR - CCB 0 Class 2 Data Size Register */
17080 /*! @{ */
17081 
17082 #define CAAM_CC2DSR_C2DS_MASK                    (0xFFFFFFFFU)
17083 #define CAAM_CC2DSR_C2DS_SHIFT                   (0U)
17084 #define CAAM_CC2DSR_C2DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK)
17085 
17086 #define CAAM_CC2DSR_C2CY_MASK                    (0x100000000U)
17087 #define CAAM_CC2DSR_C2CY_SHIFT                   (32U)
17088 /*! C2CY
17089  *  0b0..A write to the Class 2 Data Size Register did not cause a carry.
17090  *  0b1..A write to the Class 2 Data Size Register caused a carry.
17091  */
17092 #define CAAM_CC2DSR_C2CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK)
17093 
17094 #define CAAM_CC2DSR_NUMBITS_MASK                 (0xE000000000000000U)
17095 #define CAAM_CC2DSR_NUMBITS_SHIFT                (61U)
17096 #define CAAM_CC2DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK)
17097 /*! @} */
17098 
17099 /* The count of CAAM_CC2DSR */
17100 #define CAAM_CC2DSR_COUNT                        (1U)
17101 
17102 /*! @name CC2ICVSZR - CCB 0 Class 2 ICV Size Register */
17103 /*! @{ */
17104 
17105 #define CAAM_CC2ICVSZR_ICVSZ_MASK                (0xFU)
17106 #define CAAM_CC2ICVSZR_ICVSZ_SHIFT               (0U)
17107 #define CAAM_CC2ICVSZR_ICVSZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK)
17108 /*! @} */
17109 
17110 /* The count of CAAM_CC2ICVSZR */
17111 #define CAAM_CC2ICVSZR_COUNT                     (1U)
17112 
17113 /*! @name CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 */
17114 /*! @{ */
17115 
17116 #define CAAM_CC2CTXR_C2CTXR_MASK                 (0xFFFFFFFFU)
17117 #define CAAM_CC2CTXR_C2CTXR_SHIFT                (0U)
17118 #define CAAM_CC2CTXR_C2CTXR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK)
17119 /*! @} */
17120 
17121 /* The count of CAAM_CC2CTXR */
17122 #define CAAM_CC2CTXR_COUNT                       (1U)
17123 
17124 /* The count of CAAM_CC2CTXR */
17125 #define CAAM_CC2CTXR_COUNT2                      (18U)
17126 
17127 /*! @name CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 */
17128 /*! @{ */
17129 
17130 #define CAAM_CC2KEYR_C2KEY_MASK                  (0xFFFFFFFFU)
17131 #define CAAM_CC2KEYR_C2KEY_SHIFT                 (0U)
17132 #define CAAM_CC2KEYR_C2KEY(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK)
17133 /*! @} */
17134 
17135 /* The count of CAAM_CC2KEYR */
17136 #define CAAM_CC2KEYR_COUNT                       (1U)
17137 
17138 /* The count of CAAM_CC2KEYR */
17139 #define CAAM_CC2KEYR_COUNT2                      (32U)
17140 
17141 /*! @name CFIFOSTA - CCB 0 FIFO Status Register */
17142 /*! @{ */
17143 
17144 #define CAAM_CFIFOSTA_DECOOQHEAD_MASK            (0xFFU)
17145 #define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT           (0U)
17146 #define CAAM_CFIFOSTA_DECOOQHEAD(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK)
17147 
17148 #define CAAM_CFIFOSTA_DMAOQHEAD_MASK             (0xFF00U)
17149 #define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT            (8U)
17150 #define CAAM_CFIFOSTA_DMAOQHEAD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK)
17151 
17152 #define CAAM_CFIFOSTA_C2IQHEAD_MASK              (0xFF0000U)
17153 #define CAAM_CFIFOSTA_C2IQHEAD_SHIFT             (16U)
17154 #define CAAM_CFIFOSTA_C2IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK)
17155 
17156 #define CAAM_CFIFOSTA_C1IQHEAD_MASK              (0xFF000000U)
17157 #define CAAM_CFIFOSTA_C1IQHEAD_SHIFT             (24U)
17158 #define CAAM_CFIFOSTA_C1IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK)
17159 /*! @} */
17160 
17161 /* The count of CAAM_CFIFOSTA */
17162 #define CAAM_CFIFOSTA_COUNT                      (1U)
17163 
17164 /*! @name CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b */
17165 /*! @{ */
17166 
17167 #define CAAM_CNFIFO_DL_MASK                      (0xFFFU)
17168 #define CAAM_CNFIFO_DL_SHIFT                     (0U)
17169 #define CAAM_CNFIFO_DL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK)
17170 
17171 #define CAAM_CNFIFO_AST_MASK                     (0x4000U)
17172 #define CAAM_CNFIFO_AST_SHIFT                    (14U)
17173 #define CAAM_CNFIFO_AST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK)
17174 
17175 #define CAAM_CNFIFO_OC_MASK                      (0x8000U)
17176 #define CAAM_CNFIFO_OC_SHIFT                     (15U)
17177 /*! OC
17178  *  0b0..Allow the final word to be popped from the Output Data FIFO.
17179  *  0b1..Don't pop the final word from the Output Data FIFO.
17180  */
17181 #define CAAM_CNFIFO_OC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK)
17182 
17183 #define CAAM_CNFIFO_PTYPE_MASK                   (0x70000U)
17184 #define CAAM_CNFIFO_PTYPE_SHIFT                  (16U)
17185 #define CAAM_CNFIFO_PTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK)
17186 
17187 #define CAAM_CNFIFO_BND_MASK                     (0x80000U)
17188 #define CAAM_CNFIFO_BND_SHIFT                    (19U)
17189 /*! BND
17190  *  0b0..Don't pad.
17191  *  0b1..Pad to the next 16-byte boundary.
17192  */
17193 #define CAAM_CNFIFO_BND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK)
17194 
17195 #define CAAM_CNFIFO_DTYPE_MASK                   (0xF00000U)
17196 #define CAAM_CNFIFO_DTYPE_SHIFT                  (20U)
17197 #define CAAM_CNFIFO_DTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK)
17198 
17199 #define CAAM_CNFIFO_STYPE_MASK                   (0x3000000U)
17200 #define CAAM_CNFIFO_STYPE_SHIFT                  (24U)
17201 #define CAAM_CNFIFO_STYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK)
17202 
17203 #define CAAM_CNFIFO_FC1_MASK                     (0x4000000U)
17204 #define CAAM_CNFIFO_FC1_SHIFT                    (26U)
17205 /*! FC1
17206  *  0b0..Don't flush Class 1 data.
17207  *  0b1..Flush Class 1 data.
17208  */
17209 #define CAAM_CNFIFO_FC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK)
17210 
17211 #define CAAM_CNFIFO_FC2_MASK                     (0x8000000U)
17212 #define CAAM_CNFIFO_FC2_SHIFT                    (27U)
17213 /*! FC2
17214  *  0b0..Don't flush Class 2 data.
17215  *  0b1..Flush Class 2 data.
17216  */
17217 #define CAAM_CNFIFO_FC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK)
17218 
17219 #define CAAM_CNFIFO_LC1_MASK                     (0x10000000U)
17220 #define CAAM_CNFIFO_LC1_SHIFT                    (28U)
17221 /*! LC1
17222  *  0b0..This is not the last Class 1 data.
17223  *  0b1..This is the last Class 1 data.
17224  */
17225 #define CAAM_CNFIFO_LC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK)
17226 
17227 #define CAAM_CNFIFO_LC2_MASK                     (0x20000000U)
17228 #define CAAM_CNFIFO_LC2_SHIFT                    (29U)
17229 /*! LC2
17230  *  0b0..This is not the last Class 2 data.
17231  *  0b1..This is the last Class 2 data.
17232  */
17233 #define CAAM_CNFIFO_LC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK)
17234 
17235 #define CAAM_CNFIFO_DEST_MASK                    (0xC0000000U)
17236 #define CAAM_CNFIFO_DEST_SHIFT                   (30U)
17237 /*! DEST
17238  *  0b00..DECO Alignment Block. If DTYPE == Eh, data sent to the DECO Alignment Block is dropped. This is used to
17239  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17240  *        the DECO Alignment Block destination.
17241  *  0b01..Class 1.
17242  *  0b10..Class 2.
17243  *  0b11..Both Class 1 and Class 2.
17244  */
17245 #define CAAM_CNFIFO_DEST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK)
17246 /*! @} */
17247 
17248 /* The count of CAAM_CNFIFO */
17249 #define CAAM_CNFIFO_COUNT                        (1U)
17250 
17251 /*! @name CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b */
17252 /*! @{ */
17253 
17254 #define CAAM_CNFIFO_2_PL_MASK                    (0x7FU)
17255 #define CAAM_CNFIFO_2_PL_SHIFT                   (0U)
17256 #define CAAM_CNFIFO_2_PL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK)
17257 
17258 #define CAAM_CNFIFO_2_PS_MASK                    (0x400U)
17259 #define CAAM_CNFIFO_2_PS_SHIFT                   (10U)
17260 /*! PS
17261  *  0b0..C2 CHA snoops pad data from padding block.
17262  *  0b1..C2 CHA snoops pad data from OFIFO.
17263  */
17264 #define CAAM_CNFIFO_2_PS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK)
17265 
17266 #define CAAM_CNFIFO_2_BM_MASK                    (0x800U)
17267 #define CAAM_CNFIFO_2_BM_SHIFT                   (11U)
17268 /*! BM
17269  *  0b0..When padding, pad to power-of-2 boundary.
17270  *  0b1..When padding, pad to power-of-2 boundary minus 1 byte.
17271  */
17272 #define CAAM_CNFIFO_2_BM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK)
17273 
17274 #define CAAM_CNFIFO_2_PR_MASK                    (0x8000U)
17275 #define CAAM_CNFIFO_2_PR_SHIFT                   (15U)
17276 /*! PR
17277  *  0b0..No prediction resistance.
17278  *  0b1..Prediction resistance.
17279  */
17280 #define CAAM_CNFIFO_2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK)
17281 
17282 #define CAAM_CNFIFO_2_PTYPE_MASK                 (0x70000U)
17283 #define CAAM_CNFIFO_2_PTYPE_SHIFT                (16U)
17284 /*! PTYPE
17285  *  0b000..All Zero.
17286  *  0b001..Random with nonzero bytes.
17287  *  0b010..Incremented (starting with 01h), followed by a byte containing the value N-1, i.e., if N==1, a single byte is output with value 0h.
17288  *  0b011..Random.
17289  *  0b100..All Zero with last byte containing the number of 0 bytes, i.e., if N==1, a single byte is output with value 0h.
17290  *  0b101..Random with nonzero bytes with last byte 0.
17291  *  0b110..N bytes of padding all containing the value N-1.
17292  *  0b111..Random with nonzero bytes, with the last byte containing the value N-1.
17293  */
17294 #define CAAM_CNFIFO_2_PTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK)
17295 
17296 #define CAAM_CNFIFO_2_BND_MASK                   (0x80000U)
17297 #define CAAM_CNFIFO_2_BND_SHIFT                  (19U)
17298 /*! BND
17299  *  0b0..Don't add boundary padding.
17300  *  0b1..Add boundary padding.
17301  */
17302 #define CAAM_CNFIFO_2_BND(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK)
17303 
17304 #define CAAM_CNFIFO_2_DTYPE_MASK                 (0xF00000U)
17305 #define CAAM_CNFIFO_2_DTYPE_SHIFT                (20U)
17306 #define CAAM_CNFIFO_2_DTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK)
17307 
17308 #define CAAM_CNFIFO_2_STYPE_MASK                 (0x3000000U)
17309 #define CAAM_CNFIFO_2_STYPE_SHIFT                (24U)
17310 #define CAAM_CNFIFO_2_STYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK)
17311 
17312 #define CAAM_CNFIFO_2_FC1_MASK                   (0x4000000U)
17313 #define CAAM_CNFIFO_2_FC1_SHIFT                  (26U)
17314 /*! FC1
17315  *  0b0..Don't flush the Class 1 data.
17316  *  0b1..Flush the Class 1 data.
17317  */
17318 #define CAAM_CNFIFO_2_FC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK)
17319 
17320 #define CAAM_CNFIFO_2_FC2_MASK                   (0x8000000U)
17321 #define CAAM_CNFIFO_2_FC2_SHIFT                  (27U)
17322 /*! FC2
17323  *  0b0..Don't flush the Class 2 data.
17324  *  0b1..Flush the Class 2 data.
17325  */
17326 #define CAAM_CNFIFO_2_FC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK)
17327 
17328 #define CAAM_CNFIFO_2_LC1_MASK                   (0x10000000U)
17329 #define CAAM_CNFIFO_2_LC1_SHIFT                  (28U)
17330 /*! LC1
17331  *  0b0..This is not the last Class 1 data.
17332  *  0b1..This is the last Class 1 data.
17333  */
17334 #define CAAM_CNFIFO_2_LC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK)
17335 
17336 #define CAAM_CNFIFO_2_LC2_MASK                   (0x20000000U)
17337 #define CAAM_CNFIFO_2_LC2_SHIFT                  (29U)
17338 /*! LC2
17339  *  0b0..This is not the last Class 2 data.
17340  *  0b1..This is the last Class 2 data.
17341  */
17342 #define CAAM_CNFIFO_2_LC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK)
17343 
17344 #define CAAM_CNFIFO_2_DEST_MASK                  (0xC0000000U)
17345 #define CAAM_CNFIFO_2_DEST_SHIFT                 (30U)
17346 /*! DEST
17347  *  0b00..DECO Alignment Block. If DTYPE is Eh, data sent to the DECO Alignment Block is dropped. This is used to
17348  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17349  *        the DECO Alignment Block destination.
17350  *  0b01..Class 1.
17351  *  0b10..Class 2.
17352  *  0b11..Both Class 1 and Class 2.
17353  */
17354 #define CAAM_CNFIFO_2_DEST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK)
17355 /*! @} */
17356 
17357 /* The count of CAAM_CNFIFO_2 */
17358 #define CAAM_CNFIFO_2_COUNT                      (1U)
17359 
17360 /*! @name CIFIFO - CCB 0 Input Data FIFO */
17361 /*! @{ */
17362 
17363 #define CAAM_CIFIFO_IFIFO_MASK                   (0xFFFFFFFFU)
17364 #define CAAM_CIFIFO_IFIFO_SHIFT                  (0U)
17365 #define CAAM_CIFIFO_IFIFO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK)
17366 /*! @} */
17367 
17368 /* The count of CAAM_CIFIFO */
17369 #define CAAM_CIFIFO_COUNT                        (1U)
17370 
17371 /*! @name COFIFO - CCB 0 Output Data FIFO */
17372 /*! @{ */
17373 
17374 #define CAAM_COFIFO_OFIFO_MASK                   (0xFFFFFFFFFFFFFFFFU)
17375 #define CAAM_COFIFO_OFIFO_SHIFT                  (0U)
17376 #define CAAM_COFIFO_OFIFO(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK)
17377 /*! @} */
17378 
17379 /* The count of CAAM_COFIFO */
17380 #define CAAM_COFIFO_COUNT                        (1U)
17381 
17382 /*! @name DJQCR_MS - DECO0 Job Queue Control Register, most-significant half */
17383 /*! @{ */
17384 
17385 #define CAAM_DJQCR_MS_ID_MASK                    (0x7U)
17386 #define CAAM_DJQCR_MS_ID_SHIFT                   (0U)
17387 #define CAAM_DJQCR_MS_ID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK)
17388 
17389 #define CAAM_DJQCR_MS_SRC_MASK                   (0x700U)
17390 #define CAAM_DJQCR_MS_SRC_SHIFT                  (8U)
17391 /*! SRC
17392  *  0b000..Job Ring 0
17393  *  0b001..Job Ring 1
17394  *  0b010..Job Ring 2
17395  *  0b011..Job Ring 3
17396  *  0b100..RTIC
17397  *  0b101..Reserved
17398  *  0b110..Reserved
17399  *  0b111..Reserved
17400  */
17401 #define CAAM_DJQCR_MS_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK)
17402 
17403 #define CAAM_DJQCR_MS_AMTD_MASK                  (0x8000U)
17404 #define CAAM_DJQCR_MS_AMTD_SHIFT                 (15U)
17405 /*! AMTD
17406  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17407  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17408  */
17409 #define CAAM_DJQCR_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK)
17410 
17411 #define CAAM_DJQCR_MS_SOB_MASK                   (0x10000U)
17412 #define CAAM_DJQCR_MS_SOB_SHIFT                  (16U)
17413 /*! SOB
17414  *  0b0..Shared Descriptor has NOT been loaded.
17415  *  0b1..Shared Descriptor HAS been loaded.
17416  */
17417 #define CAAM_DJQCR_MS_SOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK)
17418 
17419 #define CAAM_DJQCR_MS_DWS_MASK                   (0x80000U)
17420 #define CAAM_DJQCR_MS_DWS_SHIFT                  (19U)
17421 /*! DWS
17422  *  0b0..Double Word Swap is NOT set.
17423  *  0b1..Double Word Swap is set.
17424  */
17425 #define CAAM_DJQCR_MS_DWS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK)
17426 
17427 #define CAAM_DJQCR_MS_SHR_FROM_MASK              (0x7000000U)
17428 #define CAAM_DJQCR_MS_SHR_FROM_SHIFT             (24U)
17429 #define CAAM_DJQCR_MS_SHR_FROM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK)
17430 
17431 #define CAAM_DJQCR_MS_ILE_MASK                   (0x8000000U)
17432 #define CAAM_DJQCR_MS_ILE_SHIFT                  (27U)
17433 /*! ILE
17434  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17435  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17436  */
17437 #define CAAM_DJQCR_MS_ILE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK)
17438 
17439 #define CAAM_DJQCR_MS_FOUR_MASK                  (0x10000000U)
17440 #define CAAM_DJQCR_MS_FOUR_SHIFT                 (28U)
17441 /*! FOUR
17442  *  0b0..DECO has not been given at least four words of the descriptor.
17443  *  0b1..DECO has been given at least four words of the descriptor.
17444  */
17445 #define CAAM_DJQCR_MS_FOUR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK)
17446 
17447 #define CAAM_DJQCR_MS_WHL_MASK                   (0x20000000U)
17448 #define CAAM_DJQCR_MS_WHL_SHIFT                  (29U)
17449 /*! WHL
17450  *  0b0..DECO has not been given the whole descriptor.
17451  *  0b1..DECO has been given the whole descriptor.
17452  */
17453 #define CAAM_DJQCR_MS_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK)
17454 
17455 #define CAAM_DJQCR_MS_SING_MASK                  (0x40000000U)
17456 #define CAAM_DJQCR_MS_SING_SHIFT                 (30U)
17457 /*! SING
17458  *  0b0..Do not tell DECO to execute the descriptor in single-step mode.
17459  *  0b1..Tell DECO to execute the descriptor in single-step mode.
17460  */
17461 #define CAAM_DJQCR_MS_SING(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK)
17462 
17463 #define CAAM_DJQCR_MS_STEP_MASK                  (0x80000000U)
17464 #define CAAM_DJQCR_MS_STEP_SHIFT                 (31U)
17465 /*! STEP
17466  *  0b0..DECO has not been told to execute the next command in the descriptor.
17467  *  0b1..DECO has been told to execute the next command in the descriptor.
17468  */
17469 #define CAAM_DJQCR_MS_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK)
17470 /*! @} */
17471 
17472 /* The count of CAAM_DJQCR_MS */
17473 #define CAAM_DJQCR_MS_COUNT                      (1U)
17474 
17475 /*! @name DJQCR_LS - DECO0 Job Queue Control Register, least-significant half */
17476 /*! @{ */
17477 
17478 #define CAAM_DJQCR_LS_CMD_MASK                   (0xFFFFFFFFU)
17479 #define CAAM_DJQCR_LS_CMD_SHIFT                  (0U)
17480 #define CAAM_DJQCR_LS_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK)
17481 /*! @} */
17482 
17483 /* The count of CAAM_DJQCR_LS */
17484 #define CAAM_DJQCR_LS_COUNT                      (1U)
17485 
17486 /*! @name DDAR - DECO0 Descriptor Address Register */
17487 /*! @{ */
17488 
17489 #define CAAM_DDAR_DPTR_MASK                      (0xFFFFFFFFFU)
17490 #define CAAM_DDAR_DPTR_SHIFT                     (0U)
17491 #define CAAM_DDAR_DPTR(x)                        (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK)
17492 /*! @} */
17493 
17494 /* The count of CAAM_DDAR */
17495 #define CAAM_DDAR_COUNT                          (1U)
17496 
17497 /*! @name DOPSTA_MS - DECO0 Operation Status Register, most-significant half */
17498 /*! @{ */
17499 
17500 #define CAAM_DOPSTA_MS_STATUS_MASK               (0xFFU)
17501 #define CAAM_DOPSTA_MS_STATUS_SHIFT              (0U)
17502 #define CAAM_DOPSTA_MS_STATUS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK)
17503 
17504 #define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK        (0x7F00U)
17505 #define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT       (8U)
17506 #define CAAM_DOPSTA_MS_COMMAND_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK)
17507 
17508 #define CAAM_DOPSTA_MS_NLJ_MASK                  (0x8000000U)
17509 #define CAAM_DOPSTA_MS_NLJ_SHIFT                 (27U)
17510 /*! NLJ
17511  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17512  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17513  */
17514 #define CAAM_DOPSTA_MS_NLJ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK)
17515 
17516 #define CAAM_DOPSTA_MS_STATUS_TYPE_MASK          (0xF0000000U)
17517 #define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT         (28U)
17518 /*! STATUS_TYPE
17519  *  0b0000..no error
17520  *  0b0001..DMA error
17521  *  0b0010..CCB error
17522  *  0b0011..Jump Halt User Status
17523  *  0b0100..DECO error
17524  *  0b0101, 0b0110..Reserved
17525  *  0b0111..Jump Halt Condition Code
17526  */
17527 #define CAAM_DOPSTA_MS_STATUS_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK)
17528 /*! @} */
17529 
17530 /* The count of CAAM_DOPSTA_MS */
17531 #define CAAM_DOPSTA_MS_COUNT                     (1U)
17532 
17533 /*! @name DOPSTA_LS - DECO0 Operation Status Register, least-significant half */
17534 /*! @{ */
17535 
17536 #define CAAM_DOPSTA_LS_OUT_CT_MASK               (0xFFFFFFFFU)
17537 #define CAAM_DOPSTA_LS_OUT_CT_SHIFT              (0U)
17538 #define CAAM_DOPSTA_LS_OUT_CT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK)
17539 /*! @} */
17540 
17541 /* The count of CAAM_DOPSTA_LS */
17542 #define CAAM_DOPSTA_LS_COUNT                     (1U)
17543 
17544 /*! @name DPDIDSR - DECO0 Primary DID Status Register */
17545 /*! @{ */
17546 
17547 #define CAAM_DPDIDSR_PRIM_DID_MASK               (0xFU)
17548 #define CAAM_DPDIDSR_PRIM_DID_SHIFT              (0U)
17549 #define CAAM_DPDIDSR_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK)
17550 
17551 #define CAAM_DPDIDSR_PRIM_ICID_MASK              (0x3FF80000U)
17552 #define CAAM_DPDIDSR_PRIM_ICID_SHIFT             (19U)
17553 #define CAAM_DPDIDSR_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK)
17554 /*! @} */
17555 
17556 /* The count of CAAM_DPDIDSR */
17557 #define CAAM_DPDIDSR_COUNT                       (1U)
17558 
17559 /*! @name DODIDSR - DECO0 Output DID Status Register */
17560 /*! @{ */
17561 
17562 #define CAAM_DODIDSR_OUT_DID_MASK                (0xFU)
17563 #define CAAM_DODIDSR_OUT_DID_SHIFT               (0U)
17564 #define CAAM_DODIDSR_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK)
17565 
17566 #define CAAM_DODIDSR_OUT_ICID_MASK               (0x3FF80000U)
17567 #define CAAM_DODIDSR_OUT_ICID_SHIFT              (19U)
17568 #define CAAM_DODIDSR_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK)
17569 /*! @} */
17570 
17571 /* The count of CAAM_DODIDSR */
17572 #define CAAM_DODIDSR_COUNT                       (1U)
17573 
17574 /*! @name DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS */
17575 /*! @{ */
17576 
17577 #define CAAM_DMTH_MS_MATH_MS_MASK                (0xFFFFFFFFU)
17578 #define CAAM_DMTH_MS_MATH_MS_SHIFT               (0U)
17579 #define CAAM_DMTH_MS_MATH_MS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK)
17580 /*! @} */
17581 
17582 /* The count of CAAM_DMTH_MS */
17583 #define CAAM_DMTH_MS_COUNT                       (1U)
17584 
17585 /* The count of CAAM_DMTH_MS */
17586 #define CAAM_DMTH_MS_COUNT2                      (4U)
17587 
17588 /*! @name DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS */
17589 /*! @{ */
17590 
17591 #define CAAM_DMTH_LS_MATH_LS_MASK                (0xFFFFFFFFU)
17592 #define CAAM_DMTH_LS_MATH_LS_SHIFT               (0U)
17593 #define CAAM_DMTH_LS_MATH_LS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK)
17594 /*! @} */
17595 
17596 /* The count of CAAM_DMTH_LS */
17597 #define CAAM_DMTH_LS_COUNT                       (1U)
17598 
17599 /* The count of CAAM_DMTH_LS */
17600 #define CAAM_DMTH_LS_COUNT2                      (4U)
17601 
17602 /*! @name DGTR_0 - DECO0 Gather Table Register 0 Word 0 */
17603 /*! @{ */
17604 
17605 #define CAAM_DGTR_0_ADDRESS_POINTER_MASK         (0xFU)
17606 #define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT        (0U)
17607 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
17608  */
17609 #define CAAM_DGTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK)
17610 /*! @} */
17611 
17612 /* The count of CAAM_DGTR_0 */
17613 #define CAAM_DGTR_0_COUNT                        (1U)
17614 
17615 /* The count of CAAM_DGTR_0 */
17616 #define CAAM_DGTR_0_COUNT2                       (1U)
17617 
17618 /*! @name DGTR_1 - DECO0 Gather Table Register 0 Word 1 */
17619 /*! @{ */
17620 
17621 #define CAAM_DGTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17622 #define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT        (0U)
17623 #define CAAM_DGTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK)
17624 /*! @} */
17625 
17626 /* The count of CAAM_DGTR_1 */
17627 #define CAAM_DGTR_1_COUNT                        (1U)
17628 
17629 /* The count of CAAM_DGTR_1 */
17630 #define CAAM_DGTR_1_COUNT2                       (1U)
17631 
17632 /*! @name DGTR_2 - DECO0 Gather Table Register 0 Word 2 */
17633 /*! @{ */
17634 
17635 #define CAAM_DGTR_2_Length_MASK                  (0x3FFFFFFFU)
17636 #define CAAM_DGTR_2_Length_SHIFT                 (0U)
17637 #define CAAM_DGTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK)
17638 
17639 #define CAAM_DGTR_2_F_MASK                       (0x40000000U)
17640 #define CAAM_DGTR_2_F_SHIFT                      (30U)
17641 /*! F
17642  *  0b0..This is not the last entry of the SGT.
17643  *  0b1..This is the last entry of the SGT.
17644  */
17645 #define CAAM_DGTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK)
17646 
17647 #define CAAM_DGTR_2_E_MASK                       (0x80000000U)
17648 #define CAAM_DGTR_2_E_SHIFT                      (31U)
17649 /*! E
17650  *  0b0..Address Pointer points to a memory buffer.
17651  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17652  */
17653 #define CAAM_DGTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK)
17654 /*! @} */
17655 
17656 /* The count of CAAM_DGTR_2 */
17657 #define CAAM_DGTR_2_COUNT                        (1U)
17658 
17659 /* The count of CAAM_DGTR_2 */
17660 #define CAAM_DGTR_2_COUNT2                       (1U)
17661 
17662 /*! @name DGTR_3 - DECO0 Gather Table Register 0 Word 3 */
17663 /*! @{ */
17664 
17665 #define CAAM_DGTR_3_Offset_MASK                  (0x1FFFU)
17666 #define CAAM_DGTR_3_Offset_SHIFT                 (0U)
17667 #define CAAM_DGTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK)
17668 /*! @} */
17669 
17670 /* The count of CAAM_DGTR_3 */
17671 #define CAAM_DGTR_3_COUNT                        (1U)
17672 
17673 /* The count of CAAM_DGTR_3 */
17674 #define CAAM_DGTR_3_COUNT2                       (1U)
17675 
17676 /*! @name DSTR_0 - DECO0 Scatter Table Register 0 Word 0 */
17677 /*! @{ */
17678 
17679 #define CAAM_DSTR_0_ADDRESS_POINTER_MASK         (0xFU)
17680 #define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT        (0U)
17681 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
17682  */
17683 #define CAAM_DSTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK)
17684 /*! @} */
17685 
17686 /* The count of CAAM_DSTR_0 */
17687 #define CAAM_DSTR_0_COUNT                        (1U)
17688 
17689 /* The count of CAAM_DSTR_0 */
17690 #define CAAM_DSTR_0_COUNT2                       (1U)
17691 
17692 /*! @name DSTR_1 - DECO0 Scatter Table Register 0 Word 1 */
17693 /*! @{ */
17694 
17695 #define CAAM_DSTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17696 #define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT        (0U)
17697 #define CAAM_DSTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK)
17698 /*! @} */
17699 
17700 /* The count of CAAM_DSTR_1 */
17701 #define CAAM_DSTR_1_COUNT                        (1U)
17702 
17703 /* The count of CAAM_DSTR_1 */
17704 #define CAAM_DSTR_1_COUNT2                       (1U)
17705 
17706 /*! @name DSTR_2 - DECO0 Scatter Table Register 0 Word 2 */
17707 /*! @{ */
17708 
17709 #define CAAM_DSTR_2_Length_MASK                  (0x3FFFFFFFU)
17710 #define CAAM_DSTR_2_Length_SHIFT                 (0U)
17711 #define CAAM_DSTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK)
17712 
17713 #define CAAM_DSTR_2_F_MASK                       (0x40000000U)
17714 #define CAAM_DSTR_2_F_SHIFT                      (30U)
17715 /*! F
17716  *  0b0..This is not the last entry of the SGT.
17717  *  0b1..This is the last entry of the SGT.
17718  */
17719 #define CAAM_DSTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK)
17720 
17721 #define CAAM_DSTR_2_E_MASK                       (0x80000000U)
17722 #define CAAM_DSTR_2_E_SHIFT                      (31U)
17723 /*! E
17724  *  0b0..Address Pointer points to a memory buffer.
17725  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17726  */
17727 #define CAAM_DSTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK)
17728 /*! @} */
17729 
17730 /* The count of CAAM_DSTR_2 */
17731 #define CAAM_DSTR_2_COUNT                        (1U)
17732 
17733 /* The count of CAAM_DSTR_2 */
17734 #define CAAM_DSTR_2_COUNT2                       (1U)
17735 
17736 /*! @name DSTR_3 - DECO0 Scatter Table Register 0 Word 3 */
17737 /*! @{ */
17738 
17739 #define CAAM_DSTR_3_Offset_MASK                  (0x1FFFU)
17740 #define CAAM_DSTR_3_Offset_SHIFT                 (0U)
17741 #define CAAM_DSTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK)
17742 /*! @} */
17743 
17744 /* The count of CAAM_DSTR_3 */
17745 #define CAAM_DSTR_3_COUNT                        (1U)
17746 
17747 /* The count of CAAM_DSTR_3 */
17748 #define CAAM_DSTR_3_COUNT2                       (1U)
17749 
17750 /*! @name DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 */
17751 /*! @{ */
17752 
17753 #define CAAM_DDESB_DESBW_MASK                    (0xFFFFFFFFU)
17754 #define CAAM_DDESB_DESBW_SHIFT                   (0U)
17755 #define CAAM_DDESB_DESBW(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK)
17756 /*! @} */
17757 
17758 /* The count of CAAM_DDESB */
17759 #define CAAM_DDESB_COUNT                         (1U)
17760 
17761 /* The count of CAAM_DDESB */
17762 #define CAAM_DDESB_COUNT2                        (64U)
17763 
17764 /*! @name DDJR - DECO0 Debug Job Register */
17765 /*! @{ */
17766 
17767 #define CAAM_DDJR_ID_MASK                        (0x7U)
17768 #define CAAM_DDJR_ID_SHIFT                       (0U)
17769 #define CAAM_DDJR_ID(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK)
17770 
17771 #define CAAM_DDJR_SRC_MASK                       (0x700U)
17772 #define CAAM_DDJR_SRC_SHIFT                      (8U)
17773 /*! SRC
17774  *  0b000..Job Ring 0
17775  *  0b001..Job Ring 1
17776  *  0b010..Job Ring 2
17777  *  0b011..Job Ring 3
17778  *  0b100..RTIC
17779  *  0b101, 0b110, 0b111..Reserved
17780  */
17781 #define CAAM_DDJR_SRC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK)
17782 
17783 #define CAAM_DDJR_JDDS_MASK                      (0x4000U)
17784 #define CAAM_DDJR_JDDS_SHIFT                     (14U)
17785 /*! JDDS
17786  *  0b1..SEQ DID
17787  *  0b0..Non-SEQ DID
17788  */
17789 #define CAAM_DDJR_JDDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK)
17790 
17791 #define CAAM_DDJR_AMTD_MASK                      (0x8000U)
17792 #define CAAM_DDJR_AMTD_SHIFT                     (15U)
17793 /*! AMTD
17794  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17795  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17796  */
17797 #define CAAM_DDJR_AMTD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK)
17798 
17799 #define CAAM_DDJR_GSD_MASK                       (0x10000U)
17800 #define CAAM_DDJR_GSD_SHIFT                      (16U)
17801 /*! GSD
17802  *  0b0..Shared Descriptor was NOT obtained from another DECO.
17803  *  0b1..Shared Descriptor was obtained from another DECO.
17804  */
17805 #define CAAM_DDJR_GSD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK)
17806 
17807 #define CAAM_DDJR_DWS_MASK                       (0x80000U)
17808 #define CAAM_DDJR_DWS_SHIFT                      (19U)
17809 /*! DWS
17810  *  0b0..Double Word Swap is NOT set.
17811  *  0b1..Double Word Swap is set.
17812  */
17813 #define CAAM_DDJR_DWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK)
17814 
17815 #define CAAM_DDJR_SHR_FROM_MASK                  (0x7000000U)
17816 #define CAAM_DDJR_SHR_FROM_SHIFT                 (24U)
17817 #define CAAM_DDJR_SHR_FROM(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK)
17818 
17819 #define CAAM_DDJR_ILE_MASK                       (0x8000000U)
17820 #define CAAM_DDJR_ILE_SHIFT                      (27U)
17821 /*! ILE
17822  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17823  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17824  */
17825 #define CAAM_DDJR_ILE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK)
17826 
17827 #define CAAM_DDJR_FOUR_MASK                      (0x10000000U)
17828 #define CAAM_DDJR_FOUR_SHIFT                     (28U)
17829 /*! FOUR
17830  *  0b0..DECO has not been given at least four words of the descriptor.
17831  *  0b1..DECO has been given at least four words of the descriptor.
17832  */
17833 #define CAAM_DDJR_FOUR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK)
17834 
17835 #define CAAM_DDJR_WHL_MASK                       (0x20000000U)
17836 #define CAAM_DDJR_WHL_SHIFT                      (29U)
17837 /*! WHL
17838  *  0b0..DECO has not been given the whole descriptor.
17839  *  0b1..DECO has been given the whole descriptor.
17840  */
17841 #define CAAM_DDJR_WHL(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK)
17842 
17843 #define CAAM_DDJR_SING_MASK                      (0x40000000U)
17844 #define CAAM_DDJR_SING_SHIFT                     (30U)
17845 /*! SING
17846  *  0b0..DECO has not been told to execute the descriptor in single-step mode.
17847  *  0b1..DECO has been told to execute the descriptor in single-step mode.
17848  */
17849 #define CAAM_DDJR_SING(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK)
17850 
17851 #define CAAM_DDJR_STEP_MASK                      (0x80000000U)
17852 #define CAAM_DDJR_STEP_SHIFT                     (31U)
17853 /*! STEP
17854  *  0b0..DECO has not been told to execute the next command in the descriptor.
17855  *  0b1..DECO has been told to execute the next command in the descriptor.
17856  */
17857 #define CAAM_DDJR_STEP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK)
17858 /*! @} */
17859 
17860 /* The count of CAAM_DDJR */
17861 #define CAAM_DDJR_COUNT                          (1U)
17862 
17863 /*! @name DDDR - DECO0 Debug DECO Register */
17864 /*! @{ */
17865 
17866 #define CAAM_DDDR_CT_MASK                        (0x1U)
17867 #define CAAM_DDDR_CT_SHIFT                       (0U)
17868 /*! CT
17869  *  0b0..This DECO is NOTcurrently generating the signature of a Trusted Descriptor.
17870  *  0b1..This DECO is currently generating the signature of a Trusted Descriptor.
17871  */
17872 #define CAAM_DDDR_CT(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK)
17873 
17874 #define CAAM_DDDR_BRB_MASK                       (0x2U)
17875 #define CAAM_DDDR_BRB_SHIFT                      (1U)
17876 /*! BRB
17877  *  0b0..The READ machine in the Burster is not busy.
17878  *  0b1..The READ machine in the Burster is busy.
17879  */
17880 #define CAAM_DDDR_BRB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK)
17881 
17882 #define CAAM_DDDR_BWB_MASK                       (0x4U)
17883 #define CAAM_DDDR_BWB_SHIFT                      (2U)
17884 /*! BWB
17885  *  0b0..The WRITE machine in the Burster is not busy.
17886  *  0b1..The WRITE machine in the Burster is busy.
17887  */
17888 #define CAAM_DDDR_BWB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK)
17889 
17890 #define CAAM_DDDR_NC_MASK                        (0x8U)
17891 #define CAAM_DDDR_NC_SHIFT                       (3U)
17892 /*! NC
17893  *  0b0..This DECO is currently executing a command.
17894  *  0b1..This DECO is not currently executing a command.
17895  */
17896 #define CAAM_DDDR_NC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK)
17897 
17898 #define CAAM_DDDR_CSA_MASK                       (0x10U)
17899 #define CAAM_DDDR_CSA_SHIFT                      (4U)
17900 #define CAAM_DDDR_CSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK)
17901 
17902 #define CAAM_DDDR_CMD_STAGE_MASK                 (0xE0U)
17903 #define CAAM_DDDR_CMD_STAGE_SHIFT                (5U)
17904 #define CAAM_DDDR_CMD_STAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK)
17905 
17906 #define CAAM_DDDR_CMD_INDEX_MASK                 (0x3F00U)
17907 #define CAAM_DDDR_CMD_INDEX_SHIFT                (8U)
17908 #define CAAM_DDDR_CMD_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK)
17909 
17910 #define CAAM_DDDR_NLJ_MASK                       (0x4000U)
17911 #define CAAM_DDDR_NLJ_SHIFT                      (14U)
17912 /*! NLJ
17913  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17914  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17915  */
17916 #define CAAM_DDDR_NLJ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK)
17917 
17918 #define CAAM_DDDR_PTCL_RUN_MASK                  (0x8000U)
17919 #define CAAM_DDDR_PTCL_RUN_SHIFT                 (15U)
17920 /*! PTCL_RUN
17921  *  0b0..No protocol is running in this DECO.
17922  *  0b1..A protocol is running in this DECO.
17923  */
17924 #define CAAM_DDDR_PTCL_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK)
17925 
17926 #define CAAM_DDDR_PDB_STALL_MASK                 (0x30000U)
17927 #define CAAM_DDDR_PDB_STALL_SHIFT                (16U)
17928 #define CAAM_DDDR_PDB_STALL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK)
17929 
17930 #define CAAM_DDDR_PDB_WB_ST_MASK                 (0xC0000U)
17931 #define CAAM_DDDR_PDB_WB_ST_SHIFT                (18U)
17932 #define CAAM_DDDR_PDB_WB_ST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK)
17933 
17934 #define CAAM_DDDR_DECO_STATE_MASK                (0xF00000U)
17935 #define CAAM_DDDR_DECO_STATE_SHIFT               (20U)
17936 #define CAAM_DDDR_DECO_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK)
17937 
17938 #define CAAM_DDDR_NSEQLSEL_MASK                  (0x3000000U)
17939 #define CAAM_DDDR_NSEQLSEL_SHIFT                 (24U)
17940 /*! NSEQLSEL
17941  *  0b01..SEQ DID
17942  *  0b10..Non-SEQ DID
17943  *  0b11..Trusted DID
17944  */
17945 #define CAAM_DDDR_NSEQLSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK)
17946 
17947 #define CAAM_DDDR_SEQLSEL_MASK                   (0xC000000U)
17948 #define CAAM_DDDR_SEQLSEL_SHIFT                  (26U)
17949 /*! SEQLSEL
17950  *  0b01..SEQ DID
17951  *  0b10..Non-SEQ DID
17952  *  0b11..Trusted DID
17953  */
17954 #define CAAM_DDDR_SEQLSEL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK)
17955 
17956 #define CAAM_DDDR_TRCT_MASK                      (0x30000000U)
17957 #define CAAM_DDDR_TRCT_SHIFT                     (28U)
17958 #define CAAM_DDDR_TRCT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK)
17959 
17960 #define CAAM_DDDR_SD_MASK                        (0x40000000U)
17961 #define CAAM_DDDR_SD_SHIFT                       (30U)
17962 /*! SD
17963  *  0b0..This DECO has not received a shared descriptor from another DECO.
17964  *  0b1..This DECO has received a shared descriptor from another DECO.
17965  */
17966 #define CAAM_DDDR_SD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK)
17967 
17968 #define CAAM_DDDR_VALID_MASK                     (0x80000000U)
17969 #define CAAM_DDDR_VALID_SHIFT                    (31U)
17970 /*! VALID
17971  *  0b0..No descriptor is currently running in this DECO.
17972  *  0b1..There is currently a descriptor running in this DECO.
17973  */
17974 #define CAAM_DDDR_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK)
17975 /*! @} */
17976 
17977 /* The count of CAAM_DDDR */
17978 #define CAAM_DDDR_COUNT                          (1U)
17979 
17980 /*! @name DDJP - DECO0 Debug Job Pointer */
17981 /*! @{ */
17982 
17983 #define CAAM_DDJP_JDPTR_MASK                     (0xFFFFFFFFFU)
17984 #define CAAM_DDJP_JDPTR_SHIFT                    (0U)
17985 #define CAAM_DDJP_JDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK)
17986 /*! @} */
17987 
17988 /* The count of CAAM_DDJP */
17989 #define CAAM_DDJP_COUNT                          (1U)
17990 
17991 /*! @name DSDP - DECO0 Debug Shared Pointer */
17992 /*! @{ */
17993 
17994 #define CAAM_DSDP_SDPTR_MASK                     (0xFFFFFFFFFU)
17995 #define CAAM_DSDP_SDPTR_SHIFT                    (0U)
17996 #define CAAM_DSDP_SDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK)
17997 /*! @} */
17998 
17999 /* The count of CAAM_DSDP */
18000 #define CAAM_DSDP_COUNT                          (1U)
18001 
18002 /*! @name DDDR_MS - DECO0 Debug DID, most-significant half */
18003 /*! @{ */
18004 
18005 #define CAAM_DDDR_MS_PRIM_DID_MASK               (0xFU)
18006 #define CAAM_DDDR_MS_PRIM_DID_SHIFT              (0U)
18007 #define CAAM_DDDR_MS_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK)
18008 
18009 #define CAAM_DDDR_MS_PRIM_TZ_MASK                (0x10U)
18010 #define CAAM_DDDR_MS_PRIM_TZ_SHIFT               (4U)
18011 /*! PRIM_TZ
18012  *  0b0..TrustZone NonSecureWorld
18013  *  0b1..TrustZone SecureWorld
18014  */
18015 #define CAAM_DDDR_MS_PRIM_TZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK)
18016 
18017 #define CAAM_DDDR_MS_PRIM_ICID_MASK              (0xFFE0U)
18018 #define CAAM_DDDR_MS_PRIM_ICID_SHIFT             (5U)
18019 #define CAAM_DDDR_MS_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK)
18020 
18021 #define CAAM_DDDR_MS_OUT_DID_MASK                (0xF0000U)
18022 #define CAAM_DDDR_MS_OUT_DID_SHIFT               (16U)
18023 #define CAAM_DDDR_MS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK)
18024 
18025 #define CAAM_DDDR_MS_OUT_ICID_MASK               (0xFFE00000U)
18026 #define CAAM_DDDR_MS_OUT_ICID_SHIFT              (21U)
18027 #define CAAM_DDDR_MS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK)
18028 /*! @} */
18029 
18030 /* The count of CAAM_DDDR_MS */
18031 #define CAAM_DDDR_MS_COUNT                       (1U)
18032 
18033 /*! @name DDDR_LS - DECO0 Debug DID, least-significant half */
18034 /*! @{ */
18035 
18036 #define CAAM_DDDR_LS_OUT_DID_MASK                (0xFU)
18037 #define CAAM_DDDR_LS_OUT_DID_SHIFT               (0U)
18038 #define CAAM_DDDR_LS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK)
18039 
18040 #define CAAM_DDDR_LS_OUT_ICID_MASK               (0x3FF80000U)
18041 #define CAAM_DDDR_LS_OUT_ICID_SHIFT              (19U)
18042 #define CAAM_DDDR_LS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK)
18043 /*! @} */
18044 
18045 /* The count of CAAM_DDDR_LS */
18046 #define CAAM_DDDR_LS_COUNT                       (1U)
18047 
18048 /*! @name SOL - Sequence Output Length Register */
18049 /*! @{ */
18050 
18051 #define CAAM_SOL_SOL_MASK                        (0xFFFFFFFFU)
18052 #define CAAM_SOL_SOL_SHIFT                       (0U)
18053 #define CAAM_SOL_SOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK)
18054 /*! @} */
18055 
18056 /* The count of CAAM_SOL */
18057 #define CAAM_SOL_COUNT                           (1U)
18058 
18059 /*! @name VSOL - Variable Sequence Output Length Register */
18060 /*! @{ */
18061 
18062 #define CAAM_VSOL_VSOL_MASK                      (0xFFFFFFFFU)
18063 #define CAAM_VSOL_VSOL_SHIFT                     (0U)
18064 #define CAAM_VSOL_VSOL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK)
18065 /*! @} */
18066 
18067 /* The count of CAAM_VSOL */
18068 #define CAAM_VSOL_COUNT                          (1U)
18069 
18070 /*! @name SIL - Sequence Input Length Register */
18071 /*! @{ */
18072 
18073 #define CAAM_SIL_SIL_MASK                        (0xFFFFFFFFU)
18074 #define CAAM_SIL_SIL_SHIFT                       (0U)
18075 #define CAAM_SIL_SIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK)
18076 /*! @} */
18077 
18078 /* The count of CAAM_SIL */
18079 #define CAAM_SIL_COUNT                           (1U)
18080 
18081 /*! @name VSIL - Variable Sequence Input Length Register */
18082 /*! @{ */
18083 
18084 #define CAAM_VSIL_VSIL_MASK                      (0xFFFFFFFFU)
18085 #define CAAM_VSIL_VSIL_SHIFT                     (0U)
18086 #define CAAM_VSIL_VSIL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK)
18087 /*! @} */
18088 
18089 /* The count of CAAM_VSIL */
18090 #define CAAM_VSIL_COUNT                          (1U)
18091 
18092 /*! @name DPOVRD - Protocol Override Register */
18093 /*! @{ */
18094 
18095 #define CAAM_DPOVRD_DPOVRD_MASK                  (0xFFFFFFFFU)
18096 #define CAAM_DPOVRD_DPOVRD_SHIFT                 (0U)
18097 #define CAAM_DPOVRD_DPOVRD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK)
18098 /*! @} */
18099 
18100 /* The count of CAAM_DPOVRD */
18101 #define CAAM_DPOVRD_COUNT                        (1U)
18102 
18103 /*! @name UVSOL - Variable Sequence Output Length Register; Upper 32 bits */
18104 /*! @{ */
18105 
18106 #define CAAM_UVSOL_UVSOL_MASK                    (0xFFFFFFFFU)
18107 #define CAAM_UVSOL_UVSOL_SHIFT                   (0U)
18108 #define CAAM_UVSOL_UVSOL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK)
18109 /*! @} */
18110 
18111 /* The count of CAAM_UVSOL */
18112 #define CAAM_UVSOL_COUNT                         (1U)
18113 
18114 /*! @name UVSIL - Variable Sequence Input Length Register; Upper 32 bits */
18115 /*! @{ */
18116 
18117 #define CAAM_UVSIL_UVSIL_MASK                    (0xFFFFFFFFU)
18118 #define CAAM_UVSIL_UVSIL_SHIFT                   (0U)
18119 #define CAAM_UVSIL_UVSIL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK)
18120 /*! @} */
18121 
18122 /* The count of CAAM_UVSIL */
18123 #define CAAM_UVSIL_COUNT                         (1U)
18124 
18125 
18126 /*!
18127  * @}
18128  */ /* end of group CAAM_Register_Masks */
18129 
18130 
18131 /* CAAM - Peripheral instance base addresses */
18132 /** Peripheral CAAM base address */
18133 #define CAAM_BASE                                (0x40440000u)
18134 /** Peripheral CAAM base pointer */
18135 #define CAAM                                     ((CAAM_Type *)CAAM_BASE)
18136 /** Array initializer of CAAM peripheral base addresses */
18137 #define CAAM_BASE_ADDRS                          { CAAM_BASE }
18138 /** Array initializer of CAAM peripheral base pointers */
18139 #define CAAM_BASE_PTRS                           { CAAM }
18140 
18141 /*!
18142  * @}
18143  */ /* end of group CAAM_Peripheral_Access_Layer */
18144 
18145 
18146 /* ----------------------------------------------------------------------------
18147    -- CAN Peripheral Access Layer
18148    ---------------------------------------------------------------------------- */
18149 
18150 /*!
18151  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
18152  * @{
18153  */
18154 
18155 /** CAN - Register Layout Typedef */
18156 typedef struct {
18157   __IO uint32_t MCR;                               /**< Module Configuration register, offset: 0x0 */
18158   __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
18159   __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
18160        uint8_t RESERVED_0[4];
18161   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask register, offset: 0x10 */
18162   __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
18163   __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
18164   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
18165   __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
18166   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
18167   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
18168   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
18169   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
18170   __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
18171   __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
18172        uint8_t RESERVED_1[8];
18173   __I  uint32_t CRCR;                              /**< CRC register, offset: 0x44 */
18174   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
18175   __I  uint32_t RXFIR;                             /**< Rx FIFO Information register, offset: 0x4C */
18176   __IO uint32_t CBT;                               /**< CAN Bit Timing register, offset: 0x50 */
18177        uint8_t RESERVED_2[44];
18178   union {                                          /* offset: 0x80 */
18179     struct {                                         /* offset: 0x80, array step: 0x10 */
18180       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
18181       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
18182       __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
18183     } MB_8B[64];
18184     struct {                                         /* offset: 0x80, array step: 0x18 */
18185       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */
18186       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */
18187       __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
18188     } MB_16B[42];
18189     struct {                                         /* offset: 0x80, array step: 0x28 */
18190       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */
18191       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */
18192       __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
18193     } MB_32B[24];
18194     struct {                                         /* offset: 0x80, array step: 0x48 */
18195       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */
18196       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */
18197       __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
18198     } MB_64B[14];
18199     struct {                                         /* offset: 0x80, array step: 0x10 */
18200       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
18201       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
18202       __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
18203       __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
18204     } MB[64];
18205   };
18206        uint8_t RESERVED_3[1024];
18207   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
18208        uint8_t RESERVED_4[352];
18209   __IO uint32_t MECR;                              /**< Memory Error Control register, offset: 0xAE0 */
18210   __IO uint32_t ERRIAR;                            /**< Error Injection Address register, offset: 0xAE4 */
18211   __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern register, offset: 0xAE8 */
18212   __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern register, offset: 0xAEC */
18213   __I  uint32_t RERRAR;                            /**< Error Report Address register, offset: 0xAF0 */
18214   __I  uint32_t RERRDR;                            /**< Error Report Data register, offset: 0xAF4 */
18215   __I  uint32_t RERRSYNR;                          /**< Error Report Syndrome register, offset: 0xAF8 */
18216   __IO uint32_t ERRSR;                             /**< Error Status register, offset: 0xAFC */
18217        uint8_t RESERVED_5[256];
18218   __IO uint32_t FDCTRL;                            /**< CAN FD Control register, offset: 0xC00 */
18219   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing register, offset: 0xC04 */
18220   __I  uint32_t FDCRC;                             /**< CAN FD CRC register, offset: 0xC08 */
18221 } CAN_Type;
18222 
18223 /* ----------------------------------------------------------------------------
18224    -- CAN Register Masks
18225    ---------------------------------------------------------------------------- */
18226 
18227 /*!
18228  * @addtogroup CAN_Register_Masks CAN Register Masks
18229  * @{
18230  */
18231 
18232 /*! @name MCR - Module Configuration register */
18233 /*! @{ */
18234 
18235 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
18236 #define CAN_MCR_MAXMB_SHIFT                      (0U)
18237 /*! MAXMB - Number Of The Last Message Buffer
18238  */
18239 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
18240 
18241 #define CAN_MCR_IDAM_MASK                        (0x300U)
18242 #define CAN_MCR_IDAM_SHIFT                       (8U)
18243 /*! IDAM - ID Acceptance Mode
18244  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
18245  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
18246  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
18247  *  0b11..Format D: All frames rejected.
18248  */
18249 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
18250 
18251 #define CAN_MCR_FDEN_MASK                        (0x800U)
18252 #define CAN_MCR_FDEN_SHIFT                       (11U)
18253 /*! FDEN - CAN FD operation enable
18254  *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
18255  *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
18256  */
18257 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
18258 
18259 #define CAN_MCR_AEN_MASK                         (0x1000U)
18260 #define CAN_MCR_AEN_SHIFT                        (12U)
18261 /*! AEN - Abort Enable
18262  *  0b0..Abort disabled.
18263  *  0b1..Abort enabled.
18264  */
18265 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
18266 
18267 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
18268 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
18269 /*! LPRIOEN - Local Priority Enable
18270  *  0b0..Local Priority disabled.
18271  *  0b1..Local Priority enabled.
18272  */
18273 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
18274 
18275 #define CAN_MCR_DMA_MASK                         (0x8000U)
18276 #define CAN_MCR_DMA_SHIFT                        (15U)
18277 /*! DMA - DMA Enable
18278  *  0b0..DMA feature for RX FIFO disabled.
18279  *  0b1..DMA feature for RX FIFO enabled.
18280  */
18281 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
18282 
18283 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
18284 #define CAN_MCR_IRMQ_SHIFT                       (16U)
18285 /*! IRMQ - Individual Rx Masking And Queue Enable
18286  *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
18287  *       applications, the reading of C/S word locks the MB even if it is EMPTY.
18288  *  0b1..Individual Rx masking and queue feature are enabled.
18289  */
18290 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
18291 
18292 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
18293 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
18294 /*! SRXDIS - Self Reception Disable
18295  *  0b0..Self-reception enabled.
18296  *  0b1..Self-reception disabled.
18297  */
18298 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
18299 
18300 #define CAN_MCR_DOZE_MASK                        (0x40000U)
18301 #define CAN_MCR_DOZE_SHIFT                       (18U)
18302 /*! DOZE - Doze Mode Enable
18303  *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
18304  *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
18305  */
18306 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
18307 
18308 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
18309 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
18310 /*! WAKSRC - Wake Up Source
18311  *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
18312  *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
18313  */
18314 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
18315 
18316 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
18317 #define CAN_MCR_LPMACK_SHIFT                     (20U)
18318 /*! LPMACK - Low-Power Mode Acknowledge
18319  *  0b0..FlexCAN is not in a low-power mode.
18320  *  0b1..FlexCAN is in a low-power mode.
18321  */
18322 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
18323 
18324 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
18325 #define CAN_MCR_WRNEN_SHIFT                      (21U)
18326 /*! WRNEN - Warning Interrupt Enable
18327  *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
18328  *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
18329  */
18330 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
18331 
18332 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
18333 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
18334 /*! SLFWAK - Self Wake Up
18335  *  0b0..FlexCAN Self Wake Up feature is disabled.
18336  *  0b1..FlexCAN Self Wake Up feature is enabled.
18337  */
18338 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
18339 
18340 #define CAN_MCR_SUPV_MASK                        (0x800000U)
18341 #define CAN_MCR_SUPV_SHIFT                       (23U)
18342 /*! SUPV - Supervisor Mode
18343  *  0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.
18344  *  0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
18345  *       behaves as though the access was done to an unimplemented register location.
18346  */
18347 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
18348 
18349 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
18350 #define CAN_MCR_FRZACK_SHIFT                     (24U)
18351 /*! FRZACK - Freeze Mode Acknowledge
18352  *  0b0..FlexCAN not in Freeze mode, prescaler running.
18353  *  0b1..FlexCAN in Freeze mode, prescaler stopped.
18354  */
18355 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
18356 
18357 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
18358 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
18359 /*! SOFTRST - Soft Reset
18360  *  0b0..No reset request.
18361  *  0b1..Resets the registers affected by soft reset.
18362  */
18363 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
18364 
18365 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
18366 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
18367 /*! WAKMSK - Wake Up Interrupt Mask
18368  *  0b0..Wake Up interrupt is disabled.
18369  *  0b1..Wake Up interrupt is enabled.
18370  */
18371 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
18372 
18373 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
18374 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
18375 /*! NOTRDY - FlexCAN Not Ready
18376  *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
18377  *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
18378  */
18379 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
18380 
18381 #define CAN_MCR_HALT_MASK                        (0x10000000U)
18382 #define CAN_MCR_HALT_SHIFT                       (28U)
18383 /*! HALT - Halt FlexCAN
18384  *  0b0..No Freeze mode request.
18385  *  0b1..Enters Freeze mode if the FRZ bit is asserted.
18386  */
18387 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
18388 
18389 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
18390 #define CAN_MCR_RFEN_SHIFT                       (29U)
18391 /*! RFEN - Rx FIFO Enable
18392  *  0b0..Rx FIFO not enabled.
18393  *  0b1..Rx FIFO enabled.
18394  */
18395 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
18396 
18397 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
18398 #define CAN_MCR_FRZ_SHIFT                        (30U)
18399 /*! FRZ - Freeze Enable
18400  *  0b0..Not enabled to enter Freeze mode.
18401  *  0b1..Enabled to enter Freeze mode.
18402  */
18403 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
18404 
18405 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
18406 #define CAN_MCR_MDIS_SHIFT                       (31U)
18407 /*! MDIS - Module Disable
18408  *  0b0..Enable the FlexCAN module.
18409  *  0b1..Disable the FlexCAN module.
18410  */
18411 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
18412 /*! @} */
18413 
18414 /*! @name CTRL1 - Control 1 register */
18415 /*! @{ */
18416 
18417 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
18418 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
18419 /*! PROPSEG - Propagation Segment
18420  */
18421 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
18422 
18423 #define CAN_CTRL1_LOM_MASK                       (0x8U)
18424 #define CAN_CTRL1_LOM_SHIFT                      (3U)
18425 /*! LOM - Listen-Only Mode
18426  *  0b0..Listen-Only mode is deactivated.
18427  *  0b1..FlexCAN module operates in Listen-Only mode.
18428  */
18429 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
18430 
18431 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
18432 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
18433 /*! LBUF - Lowest Buffer Transmitted First
18434  *  0b0..Buffer with highest priority is transmitted first.
18435  *  0b1..Lowest number buffer is transmitted first.
18436  */
18437 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
18438 
18439 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
18440 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
18441 /*! TSYN - Timer Sync
18442  *  0b0..Timer sync feature disabled
18443  *  0b1..Timer sync feature enabled
18444  */
18445 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
18446 
18447 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
18448 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
18449 /*! BOFFREC - Bus Off Recovery
18450  *  0b0..Automatic recovering from Bus Off state enabled.
18451  *  0b1..Automatic recovering from Bus Off state disabled.
18452  */
18453 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
18454 
18455 #define CAN_CTRL1_SMP_MASK                       (0x80U)
18456 #define CAN_CTRL1_SMP_SHIFT                      (7U)
18457 /*! SMP - CAN Bit Sampling
18458  *  0b0..Just one sample is used to determine the bit value.
18459  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
18460  *       preceding samples; a majority rule is used.
18461  */
18462 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
18463 
18464 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
18465 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
18466 /*! RWRNMSK - Rx Warning Interrupt Mask
18467  *  0b0..Rx Warning interrupt disabled.
18468  *  0b1..Rx Warning interrupt enabled.
18469  */
18470 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
18471 
18472 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
18473 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
18474 /*! TWRNMSK - Tx Warning Interrupt Mask
18475  *  0b0..Tx Warning interrupt disabled.
18476  *  0b1..Tx Warning interrupt enabled.
18477  */
18478 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
18479 
18480 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
18481 #define CAN_CTRL1_LPB_SHIFT                      (12U)
18482 /*! LPB - Loop Back Mode
18483  *  0b0..Loop Back disabled.
18484  *  0b1..Loop Back enabled.
18485  */
18486 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
18487 
18488 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
18489 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
18490 /*! CLKSRC - CAN Engine Clock Source
18491  *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
18492  *  0b1..The CAN engine clock source is the peripheral clock.
18493  */
18494 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
18495 
18496 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
18497 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
18498 /*! ERRMSK - Error Interrupt Mask
18499  *  0b0..Error interrupt disabled.
18500  *  0b1..Error interrupt enabled.
18501  */
18502 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
18503 
18504 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
18505 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
18506 /*! BOFFMSK - Bus Off Interrupt Mask
18507  *  0b0..Bus Off interrupt disabled.
18508  *  0b1..Bus Off interrupt enabled.
18509  */
18510 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
18511 
18512 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
18513 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
18514 /*! PSEG2 - Phase Segment 2
18515  */
18516 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
18517 
18518 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
18519 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
18520 /*! PSEG1 - Phase Segment 1
18521  */
18522 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
18523 
18524 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
18525 #define CAN_CTRL1_RJW_SHIFT                      (22U)
18526 /*! RJW - Resync Jump Width
18527  */
18528 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
18529 
18530 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
18531 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
18532 /*! PRESDIV - Prescaler Division Factor
18533  */
18534 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
18535 /*! @} */
18536 
18537 /*! @name TIMER - Free Running Timer */
18538 /*! @{ */
18539 
18540 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
18541 #define CAN_TIMER_TIMER_SHIFT                    (0U)
18542 /*! TIMER - Timer Value
18543  */
18544 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
18545 /*! @} */
18546 
18547 /*! @name RXMGMASK - Rx Mailboxes Global Mask register */
18548 /*! @{ */
18549 
18550 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
18551 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
18552 /*! MG - Rx Mailboxes Global Mask Bits
18553  */
18554 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
18555 /*! @} */
18556 
18557 /*! @name RX14MASK - Rx 14 Mask register */
18558 /*! @{ */
18559 
18560 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
18561 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
18562 /*! RX14M - Rx Buffer 14 Mask Bits
18563  */
18564 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
18565 /*! @} */
18566 
18567 /*! @name RX15MASK - Rx 15 Mask register */
18568 /*! @{ */
18569 
18570 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
18571 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
18572 /*! RX15M - Rx Buffer 15 Mask Bits
18573  */
18574 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
18575 /*! @} */
18576 
18577 /*! @name ECR - Error Counter */
18578 /*! @{ */
18579 
18580 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
18581 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
18582 /*! TXERRCNT - Transmit Error Counter
18583  */
18584 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
18585 
18586 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
18587 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
18588 /*! RXERRCNT - Receive Error Counter
18589  */
18590 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
18591 
18592 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
18593 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
18594 /*! TXERRCNT_FAST - Transmit Error Counter for fast bits
18595  */
18596 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
18597 
18598 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
18599 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
18600 /*! RXERRCNT_FAST - Receive Error Counter for fast bits
18601  */
18602 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
18603 /*! @} */
18604 
18605 /*! @name ESR1 - Error and Status 1 register */
18606 /*! @{ */
18607 
18608 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
18609 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
18610 /*! WAKINT - Wake-Up Interrupt
18611  *  0b0..No such occurrence.
18612  *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
18613  */
18614 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
18615 
18616 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
18617 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
18618 /*! ERRINT - Error Interrupt
18619  *  0b0..No such occurrence.
18620  *  0b1..Indicates setting of any error bit in the Error and Status register.
18621  */
18622 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
18623 
18624 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
18625 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
18626 /*! BOFFINT - Bus Off Interrupt
18627  *  0b0..No such occurrence.
18628  *  0b1..FlexCAN module entered Bus Off state.
18629  */
18630 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
18631 
18632 #define CAN_ESR1_RX_MASK                         (0x8U)
18633 #define CAN_ESR1_RX_SHIFT                        (3U)
18634 /*! RX - FlexCAN In Reception
18635  *  0b0..FlexCAN is not receiving a message.
18636  *  0b1..FlexCAN is receiving a message.
18637  */
18638 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
18639 
18640 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
18641 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
18642 /*! FLTCONF - Fault Confinement State
18643  *  0b00..Error Active
18644  *  0b01..Error Passive
18645  *  0b1x..Bus Off
18646  */
18647 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
18648 
18649 #define CAN_ESR1_TX_MASK                         (0x40U)
18650 #define CAN_ESR1_TX_SHIFT                        (6U)
18651 /*! TX - FlexCAN In Transmission
18652  *  0b0..FlexCAN is not transmitting a message.
18653  *  0b1..FlexCAN is transmitting a message.
18654  */
18655 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
18656 
18657 #define CAN_ESR1_IDLE_MASK                       (0x80U)
18658 #define CAN_ESR1_IDLE_SHIFT                      (7U)
18659 /*! IDLE - IDLE
18660  *  0b0..No such occurrence.
18661  *  0b1..CAN bus is now IDLE.
18662  */
18663 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
18664 
18665 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
18666 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
18667 /*! RXWRN - Rx Error Warning
18668  *  0b0..No such occurrence.
18669  *  0b1..RXERRCNT is greater than or equal to 96.
18670  */
18671 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
18672 
18673 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
18674 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
18675 /*! TXWRN - TX Error Warning
18676  *  0b0..No such occurrence.
18677  *  0b1..TXERRCNT is greater than or equal to 96.
18678  */
18679 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
18680 
18681 #define CAN_ESR1_STFERR_MASK                     (0x400U)
18682 #define CAN_ESR1_STFERR_SHIFT                    (10U)
18683 /*! STFERR - Stuffing Error
18684  *  0b0..No such occurrence.
18685  *  0b1..A stuffing error occurred since last read of this register.
18686  */
18687 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
18688 
18689 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
18690 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
18691 /*! FRMERR - Form Error
18692  *  0b0..No such occurrence.
18693  *  0b1..A Form Error occurred since last read of this register.
18694  */
18695 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
18696 
18697 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
18698 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
18699 /*! CRCERR - Cyclic Redundancy Check Error
18700  *  0b0..No such occurrence.
18701  *  0b1..A CRC error occurred since last read of this register.
18702  */
18703 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
18704 
18705 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
18706 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
18707 /*! ACKERR - Acknowledge Error
18708  *  0b0..No such occurrence.
18709  *  0b1..An ACK error occurred since last read of this register.
18710  */
18711 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
18712 
18713 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
18714 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
18715 /*! BIT0ERR - Bit0 Error
18716  *  0b0..No such occurrence.
18717  *  0b1..At least one bit sent as dominant is received as recessive.
18718  */
18719 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
18720 
18721 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
18722 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
18723 /*! BIT1ERR - Bit1 Error
18724  *  0b0..No such occurrence.
18725  *  0b1..At least one bit sent as recessive is received as dominant.
18726  */
18727 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
18728 
18729 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
18730 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
18731 /*! RWRNINT - Rx Warning Interrupt Flag
18732  *  0b0..No such occurrence.
18733  *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
18734  */
18735 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
18736 
18737 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
18738 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
18739 /*! TWRNINT - Tx Warning Interrupt Flag
18740  *  0b0..No such occurrence.
18741  *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
18742  */
18743 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
18744 
18745 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
18746 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
18747 /*! SYNCH - CAN Synchronization Status
18748  *  0b0..FlexCAN is not synchronized to the CAN bus.
18749  *  0b1..FlexCAN is synchronized to the CAN bus.
18750  */
18751 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
18752 
18753 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
18754 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
18755 /*! BOFFDONEINT - Bus Off Done Interrupt
18756  *  0b0..No such occurrence.
18757  *  0b1..FlexCAN module has completed Bus Off process.
18758  */
18759 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
18760 
18761 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
18762 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
18763 /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
18764  *  0b0..No such occurrence.
18765  *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
18766  */
18767 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
18768 
18769 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
18770 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
18771 /*! ERROVR - Error Overrun
18772  *  0b0..Overrun has not occurred.
18773  *  0b1..Overrun has occurred.
18774  */
18775 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
18776 
18777 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
18778 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
18779 /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
18780  *  0b0..No such occurrence.
18781  *  0b1..A stuffing error occurred since last read of this register.
18782  */
18783 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
18784 
18785 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
18786 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
18787 /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
18788  *  0b0..No such occurrence.
18789  *  0b1..A form error occurred since last read of this register.
18790  */
18791 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
18792 
18793 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
18794 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
18795 /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
18796  *  0b0..No such occurrence.
18797  *  0b1..A CRC error occurred since last read of this register.
18798  */
18799 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
18800 
18801 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
18802 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
18803 /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
18804  *  0b0..No such occurrence.
18805  *  0b1..At least one bit sent as dominant is received as recessive.
18806  */
18807 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
18808 
18809 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
18810 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
18811 /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
18812  *  0b0..No such occurrence.
18813  *  0b1..At least one bit sent as recessive is received as dominant.
18814  */
18815 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
18816 /*! @} */
18817 
18818 /*! @name IMASK2 - Interrupt Masks 2 register */
18819 /*! @{ */
18820 
18821 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
18822 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
18823 /*! BUF63TO32M - Buffer MBi Mask
18824  */
18825 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
18826 /*! @} */
18827 
18828 /*! @name IMASK1 - Interrupt Masks 1 register */
18829 /*! @{ */
18830 
18831 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
18832 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
18833 /*! BUF31TO0M - Buffer MBi Mask
18834  */
18835 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
18836 /*! @} */
18837 
18838 /*! @name IFLAG2 - Interrupt Flags 2 register */
18839 /*! @{ */
18840 
18841 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
18842 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
18843 /*! BUF63TO32I - Buffer MBi Interrupt
18844  */
18845 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
18846 /*! @} */
18847 
18848 /*! @name IFLAG1 - Interrupt Flags 1 register */
18849 /*! @{ */
18850 
18851 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
18852 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
18853 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
18854  *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
18855  *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
18856  */
18857 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
18858 
18859 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
18860 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
18861 /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
18862  */
18863 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
18864 
18865 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
18866 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
18867 /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
18868  *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
18869  *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
18870  *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
18871  */
18872 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
18873 
18874 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
18875 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
18876 /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
18877  *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
18878  *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
18879  */
18880 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
18881 
18882 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
18883 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
18884 /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
18885  *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
18886  *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
18887  */
18888 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
18889 
18890 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
18891 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
18892 /*! BUF31TO8I - Buffer MBi Interrupt
18893  */
18894 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
18895 /*! @} */
18896 
18897 /*! @name CTRL2 - Control 2 register */
18898 /*! @{ */
18899 
18900 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
18901 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
18902 /*! EDFLTDIS - Edge Filter Disable
18903  *  0b0..Edge filter is enabled
18904  *  0b1..Edge filter is disabled
18905  */
18906 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
18907 
18908 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
18909 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
18910 /*! ISOCANFDEN - ISO CAN FD Enable
18911  *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
18912  *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
18913  */
18914 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
18915 
18916 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
18917 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
18918 /*! PREXCEN - Protocol Exception Enable
18919  *  0b0..Protocol exception is disabled.
18920  *  0b1..Protocol exception is enabled.
18921  */
18922 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
18923 
18924 #define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
18925 #define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
18926 /*! TIMER_SRC - Timer Source
18927  *  0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
18928  *  0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
18929  *       to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
18930  *       details about the external time tick.
18931  */
18932 #define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
18933 
18934 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
18935 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
18936 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
18937  *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
18938  *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
18939  *       the incoming frame. Mask bits do apply.
18940  */
18941 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
18942 
18943 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
18944 #define CAN_CTRL2_RRS_SHIFT                      (17U)
18945 /*! RRS - Remote Request Storing
18946  *  0b0..Remote response frame is generated.
18947  *  0b1..Remote request frame is stored.
18948  */
18949 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
18950 
18951 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
18952 #define CAN_CTRL2_MRP_SHIFT                      (18U)
18953 /*! MRP - Mailboxes Reception Priority
18954  *  0b0..Matching starts from Rx FIFO and continues on mailboxes.
18955  *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
18956  */
18957 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
18958 
18959 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
18960 #define CAN_CTRL2_TASD_SHIFT                     (19U)
18961 /*! TASD - Tx Arbitration Start Delay
18962  */
18963 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
18964 
18965 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
18966 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
18967 /*! RFFN - Number Of Rx FIFO Filters
18968  */
18969 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
18970 
18971 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
18972 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
18973 /*! WRMFRZ - Write-Access To Memory In Freeze Mode
18974  *  0b0..Maintain the write access restrictions.
18975  *  0b1..Enable unrestricted write access to FlexCAN memory.
18976  */
18977 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
18978 
18979 #define CAN_CTRL2_ECRWRE_MASK                    (0x20000000U)
18980 #define CAN_CTRL2_ECRWRE_SHIFT                   (29U)
18981 /*! ECRWRE - Error-correction Configuration Register Write Enable
18982  *  0b0..Disable update.
18983  *  0b1..Enable update.
18984  */
18985 #define CAN_CTRL2_ECRWRE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
18986 
18987 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
18988 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
18989 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
18990  *  0b0..Bus off done interrupt disabled.
18991  *  0b1..Bus off done interrupt enabled.
18992  */
18993 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
18994 
18995 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
18996 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
18997 /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
18998  *  0b0..ERRINT_FAST error interrupt disabled.
18999  *  0b1..ERRINT_FAST error interrupt enabled.
19000  */
19001 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
19002 /*! @} */
19003 
19004 /*! @name ESR2 - Error and Status 2 register */
19005 /*! @{ */
19006 
19007 #define CAN_ESR2_IMB_MASK                        (0x2000U)
19008 #define CAN_ESR2_IMB_SHIFT                       (13U)
19009 /*! IMB - Inactive Mailbox
19010  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
19011  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
19012  */
19013 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
19014 
19015 #define CAN_ESR2_VPS_MASK                        (0x4000U)
19016 #define CAN_ESR2_VPS_SHIFT                       (14U)
19017 /*! VPS - Valid Priority Status
19018  *  0b0..Contents of IMB and LPTM are invalid.
19019  *  0b1..Contents of IMB and LPTM are valid.
19020  */
19021 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
19022 
19023 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
19024 #define CAN_ESR2_LPTM_SHIFT                      (16U)
19025 /*! LPTM - Lowest Priority Tx Mailbox
19026  */
19027 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
19028 /*! @} */
19029 
19030 /*! @name CRCR - CRC register */
19031 /*! @{ */
19032 
19033 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
19034 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
19035 /*! TXCRC - Transmitted CRC value
19036  */
19037 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
19038 
19039 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
19040 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
19041 /*! MBCRC - CRC Mailbox
19042  */
19043 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
19044 /*! @} */
19045 
19046 /*! @name RXFGMASK - Rx FIFO Global Mask register */
19047 /*! @{ */
19048 
19049 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
19050 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
19051 /*! FGM - Rx FIFO Global Mask Bits
19052  */
19053 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
19054 /*! @} */
19055 
19056 /*! @name RXFIR - Rx FIFO Information register */
19057 /*! @{ */
19058 
19059 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
19060 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
19061 /*! IDHIT - Identifier Acceptance Filter Hit Indicator
19062  */
19063 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
19064 /*! @} */
19065 
19066 /*! @name CBT - CAN Bit Timing register */
19067 /*! @{ */
19068 
19069 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
19070 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
19071 /*! EPSEG2 - Extended Phase Segment 2
19072  */
19073 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
19074 
19075 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
19076 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
19077 /*! EPSEG1 - Extended Phase Segment 1
19078  */
19079 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
19080 
19081 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
19082 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
19083 /*! EPROPSEG - Extended Propagation Segment
19084  */
19085 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
19086 
19087 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
19088 #define CAN_CBT_ERJW_SHIFT                       (16U)
19089 /*! ERJW - Extended Resync Jump Width
19090  */
19091 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
19092 
19093 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
19094 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
19095 /*! EPRESDIV - Extended Prescaler Division Factor
19096  */
19097 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
19098 
19099 #define CAN_CBT_BTF_MASK                         (0x80000000U)
19100 #define CAN_CBT_BTF_SHIFT                        (31U)
19101 /*! BTF - Bit Timing Format Enable
19102  *  0b0..Extended bit time definitions disabled.
19103  *  0b1..Extended bit time definitions enabled.
19104  */
19105 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
19106 /*! @} */
19107 
19108 /* The count of CAN_CS */
19109 #define CAN_CS_COUNT_MB8B                        (64U)
19110 
19111 /* The count of CAN_ID */
19112 #define CAN_ID_COUNT_MB8B                        (64U)
19113 
19114 /* The count of CAN_WORD */
19115 #define CAN_WORD_COUNT_MB8B                      (64U)
19116 
19117 /* The count of CAN_WORD */
19118 #define CAN_WORD_COUNT_MB8B2                     (2U)
19119 
19120 /* The count of CAN_CS */
19121 #define CAN_CS_COUNT_MB16B                       (42U)
19122 
19123 /* The count of CAN_ID */
19124 #define CAN_ID_COUNT_MB16B                       (42U)
19125 
19126 /* The count of CAN_WORD */
19127 #define CAN_WORD_COUNT_MB16B                     (42U)
19128 
19129 /* The count of CAN_WORD */
19130 #define CAN_WORD_COUNT_MB16B2                    (4U)
19131 
19132 /* The count of CAN_CS */
19133 #define CAN_CS_COUNT_MB32B                       (24U)
19134 
19135 /* The count of CAN_ID */
19136 #define CAN_ID_COUNT_MB32B                       (24U)
19137 
19138 /* The count of CAN_WORD */
19139 #define CAN_WORD_COUNT_MB32B                     (24U)
19140 
19141 /* The count of CAN_WORD */
19142 #define CAN_WORD_COUNT_MB32B2                    (8U)
19143 
19144 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */
19145 /*! @{ */
19146 
19147 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
19148 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
19149 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
19150  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
19151  *    appears on the CAN bus.
19152  */
19153 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
19154 
19155 #define CAN_CS_DLC_MASK                          (0xF0000U)
19156 #define CAN_CS_DLC_SHIFT                         (16U)
19157 /*! DLC - Length of the data to be stored/transmitted.
19158  */
19159 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
19160 
19161 #define CAN_CS_RTR_MASK                          (0x100000U)
19162 #define CAN_CS_RTR_SHIFT                         (20U)
19163 /*! RTR - Remote Transmission Request. One/zero for remote/data frame.
19164  */
19165 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
19166 
19167 #define CAN_CS_IDE_MASK                          (0x200000U)
19168 #define CAN_CS_IDE_SHIFT                         (21U)
19169 /*! IDE - ID Extended. One/zero for extended/standard format frame.
19170  */
19171 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
19172 
19173 #define CAN_CS_SRR_MASK                          (0x400000U)
19174 #define CAN_CS_SRR_SHIFT                         (22U)
19175 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
19176  */
19177 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
19178 
19179 #define CAN_CS_CODE_MASK                         (0xF000000U)
19180 #define CAN_CS_CODE_SHIFT                        (24U)
19181 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
19182  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
19183  */
19184 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
19185 
19186 #define CAN_CS_ESI_MASK                          (0x20000000U)
19187 #define CAN_CS_ESI_SHIFT                         (29U)
19188 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
19189  */
19190 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19191 
19192 #define CAN_CS_BRS_MASK                          (0x40000000U)
19193 #define CAN_CS_BRS_SHIFT                         (30U)
19194 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
19195  */
19196 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19197 
19198 #define CAN_CS_EDL_MASK                          (0x80000000U)
19199 #define CAN_CS_EDL_SHIFT                         (31U)
19200 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
19201  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
19202  */
19203 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19204 /*! @} */
19205 
19206 /* The count of CAN_CS */
19207 #define CAN_CS_COUNT_MB64B                       (14U)
19208 
19209 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */
19210 /*! @{ */
19211 
19212 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
19213 #define CAN_ID_EXT_SHIFT                         (0U)
19214 /*! EXT - Contains extended (LOW word) identifier of message buffer.
19215  */
19216 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19217 
19218 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
19219 #define CAN_ID_STD_SHIFT                         (18U)
19220 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
19221  */
19222 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19223 
19224 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
19225 #define CAN_ID_PRIO_SHIFT                        (29U)
19226 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
19227  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
19228  *    ID to define the transmission priority.
19229  */
19230 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19231 /*! @} */
19232 
19233 /* The count of CAN_ID */
19234 #define CAN_ID_COUNT_MB64B                       (14U)
19235 
19236 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */
19237 /*! @{ */
19238 
19239 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
19240 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
19241 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
19242  */
19243 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19244 
19245 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
19246 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
19247 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
19248  */
19249 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19250 
19251 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
19252 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
19253 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
19254  */
19255 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19256 
19257 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
19258 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
19259 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
19260  */
19261 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19262 
19263 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
19264 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
19265 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
19266  */
19267 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19268 
19269 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
19270 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
19271 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
19272  */
19273 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19274 
19275 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
19276 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
19277 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
19278  */
19279 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19280 
19281 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
19282 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
19283 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
19284  */
19285 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19286 
19287 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
19288 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
19289 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
19290  */
19291 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19292 
19293 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
19294 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
19295 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
19296  */
19297 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19298 
19299 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
19300 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
19301 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
19302  */
19303 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19304 
19305 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
19306 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
19307 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
19308  */
19309 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19310 
19311 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
19312 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
19313 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
19314  */
19315 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19316 
19317 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
19318 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
19319 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
19320  */
19321 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19322 
19323 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
19324 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
19325 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
19326  */
19327 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19328 
19329 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
19330 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
19331 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
19332  */
19333 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19334 
19335 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
19336 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
19337 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
19338  */
19339 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19340 
19341 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
19342 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
19343 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
19344  */
19345 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19346 
19347 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
19348 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
19349 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
19350  */
19351 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19352 
19353 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
19354 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
19355 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
19356  */
19357 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19358 
19359 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
19360 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
19361 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
19362  */
19363 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19364 
19365 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
19366 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
19367 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
19368  */
19369 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19370 
19371 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
19372 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
19373 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
19374  */
19375 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19376 
19377 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
19378 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
19379 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
19380  */
19381 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19382 
19383 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
19384 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
19385 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
19386  */
19387 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19388 
19389 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
19390 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
19391 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
19392  */
19393 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19394 
19395 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
19396 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
19397 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
19398  */
19399 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19400 
19401 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
19402 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
19403 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
19404  */
19405 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19406 
19407 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
19408 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
19409 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
19410  */
19411 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19412 
19413 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
19414 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
19415 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
19416  */
19417 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19418 
19419 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
19420 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
19421 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
19422  */
19423 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19424 
19425 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
19426 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
19427 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
19428  */
19429 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19430 
19431 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
19432 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
19433 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
19434  */
19435 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19436 
19437 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
19438 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
19439 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
19440  */
19441 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19442 
19443 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
19444 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
19445 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
19446  */
19447 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19448 
19449 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
19450 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
19451 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
19452  */
19453 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19454 
19455 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
19456 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
19457 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
19458  */
19459 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19460 
19461 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
19462 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
19463 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
19464  */
19465 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19466 
19467 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
19468 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
19469 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
19470  */
19471 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19472 
19473 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
19474 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
19475 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
19476  */
19477 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19478 
19479 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
19480 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
19481 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
19482  */
19483 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19484 
19485 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
19486 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
19487 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
19488  */
19489 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19490 
19491 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
19492 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
19493 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
19494  */
19495 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19496 
19497 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
19498 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
19499 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
19500  */
19501 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19502 
19503 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
19504 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
19505 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
19506  */
19507 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19508 
19509 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
19510 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
19511 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
19512  */
19513 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19514 
19515 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
19516 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
19517 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
19518  */
19519 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19520 
19521 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
19522 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
19523 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
19524  */
19525 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19526 
19527 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
19528 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
19529 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
19530  */
19531 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19532 
19533 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
19534 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
19535 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
19536  */
19537 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19538 
19539 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
19540 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
19541 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
19542  */
19543 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19544 
19545 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
19546 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
19547 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
19548  */
19549 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19550 
19551 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
19552 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
19553 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
19554  */
19555 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19556 
19557 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
19558 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
19559 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
19560  */
19561 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19562 
19563 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
19564 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
19565 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
19566  */
19567 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19568 
19569 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
19570 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
19571 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
19572  */
19573 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19574 
19575 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
19576 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
19577 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
19578  */
19579 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19580 
19581 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
19582 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
19583 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
19584  */
19585 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19586 
19587 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
19588 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
19589 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
19590  */
19591 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19592 
19593 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
19594 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
19595 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
19596  */
19597 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19598 
19599 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
19600 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
19601 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
19602  */
19603 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19604 
19605 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
19606 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
19607 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
19608  */
19609 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19610 
19611 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
19612 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
19613 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
19614  */
19615 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19616 
19617 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
19618 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
19619 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
19620  */
19621 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19622 /*! @} */
19623 
19624 /* The count of CAN_WORD */
19625 #define CAN_WORD_COUNT_MB64B                     (14U)
19626 
19627 /* The count of CAN_WORD */
19628 #define CAN_WORD_COUNT_MB64B2                    (16U)
19629 
19630 /* The count of CAN_CS */
19631 #define CAN_CS_COUNT                             (64U)
19632 
19633 /* The count of CAN_ID */
19634 #define CAN_ID_COUNT                             (64U)
19635 
19636 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
19637 /*! @{ */
19638 
19639 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
19640 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
19641 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
19642  */
19643 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
19644 
19645 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
19646 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
19647 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
19648  */
19649 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
19650 
19651 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
19652 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
19653 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
19654  */
19655 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
19656 
19657 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
19658 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
19659 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
19660  */
19661 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
19662 /*! @} */
19663 
19664 /* The count of CAN_WORD0 */
19665 #define CAN_WORD0_COUNT                          (64U)
19666 
19667 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
19668 /*! @{ */
19669 
19670 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
19671 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
19672 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
19673  */
19674 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
19675 
19676 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
19677 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
19678 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
19679  */
19680 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
19681 
19682 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
19683 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
19684 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
19685  */
19686 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
19687 
19688 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
19689 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
19690 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
19691  */
19692 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
19693 /*! @} */
19694 
19695 /* The count of CAN_WORD1 */
19696 #define CAN_WORD1_COUNT                          (64U)
19697 
19698 /*! @name RXIMR - Rx Individual Mask registers */
19699 /*! @{ */
19700 
19701 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
19702 #define CAN_RXIMR_MI_SHIFT                       (0U)
19703 /*! MI - Individual Mask Bits
19704  */
19705 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
19706 /*! @} */
19707 
19708 /* The count of CAN_RXIMR */
19709 #define CAN_RXIMR_COUNT                          (64U)
19710 
19711 /*! @name MECR - Memory Error Control register */
19712 /*! @{ */
19713 
19714 #define CAN_MECR_NCEFAFRZ_MASK                   (0x80U)
19715 #define CAN_MECR_NCEFAFRZ_SHIFT                  (7U)
19716 /*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
19717  *  0b0..Keep normal operation.
19718  *  0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
19719  */
19720 #define CAN_MECR_NCEFAFRZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
19721 
19722 #define CAN_MECR_ECCDIS_MASK                     (0x100U)
19723 #define CAN_MECR_ECCDIS_SHIFT                    (8U)
19724 /*! ECCDIS - Error Correction Disable
19725  *  0b0..Enable memory error correction.
19726  *  0b1..Disable memory error correction.
19727  */
19728 #define CAN_MECR_ECCDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
19729 
19730 #define CAN_MECR_RERRDIS_MASK                    (0x200U)
19731 #define CAN_MECR_RERRDIS_SHIFT                   (9U)
19732 /*! RERRDIS - Error Report Disable
19733  *  0b0..Enable updates of the error report registers.
19734  *  0b1..Disable updates of the error report registers.
19735  */
19736 #define CAN_MECR_RERRDIS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
19737 
19738 #define CAN_MECR_EXTERRIE_MASK                   (0x2000U)
19739 #define CAN_MECR_EXTERRIE_SHIFT                  (13U)
19740 /*! EXTERRIE - Extended Error Injection Enable
19741  *  0b0..Error injection is applied only to the 32-bit word.
19742  *  0b1..Error injection is applied to the 64-bit word.
19743  */
19744 #define CAN_MECR_EXTERRIE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
19745 
19746 #define CAN_MECR_FAERRIE_MASK                    (0x4000U)
19747 #define CAN_MECR_FAERRIE_SHIFT                   (14U)
19748 /*! FAERRIE - FlexCAN Access Error Injection Enable
19749  *  0b0..Injection is disabled.
19750  *  0b1..Injection is enabled.
19751  */
19752 #define CAN_MECR_FAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
19753 
19754 #define CAN_MECR_HAERRIE_MASK                    (0x8000U)
19755 #define CAN_MECR_HAERRIE_SHIFT                   (15U)
19756 /*! HAERRIE - Host Access Error Injection Enable
19757  *  0b0..Injection is disabled.
19758  *  0b1..Injection is enabled.
19759  */
19760 #define CAN_MECR_HAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
19761 
19762 #define CAN_MECR_CEI_MSK_MASK                    (0x10000U)
19763 #define CAN_MECR_CEI_MSK_SHIFT                   (16U)
19764 /*! CEI_MSK - Correctable Errors Interrupt Mask
19765  *  0b0..Interrupt is disabled.
19766  *  0b1..Interrupt is enabled.
19767  */
19768 #define CAN_MECR_CEI_MSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
19769 
19770 #define CAN_MECR_FANCEI_MSK_MASK                 (0x40000U)
19771 #define CAN_MECR_FANCEI_MSK_SHIFT                (18U)
19772 /*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
19773  *  0b0..Interrupt is disabled.
19774  *  0b1..Interrupt is enabled.
19775  */
19776 #define CAN_MECR_FANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
19777 
19778 #define CAN_MECR_HANCEI_MSK_MASK                 (0x80000U)
19779 #define CAN_MECR_HANCEI_MSK_SHIFT                (19U)
19780 /*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
19781  *  0b0..Interrupt is disabled.
19782  *  0b1..Interrupt is enabled.
19783  */
19784 #define CAN_MECR_HANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
19785 
19786 #define CAN_MECR_ECRWRDIS_MASK                   (0x80000000U)
19787 #define CAN_MECR_ECRWRDIS_SHIFT                  (31U)
19788 /*! ECRWRDIS - Error Configuration Register Write Disable
19789  *  0b0..Write is enabled.
19790  *  0b1..Write is disabled.
19791  */
19792 #define CAN_MECR_ECRWRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
19793 /*! @} */
19794 
19795 /*! @name ERRIAR - Error Injection Address register */
19796 /*! @{ */
19797 
19798 #define CAN_ERRIAR_INJADDR_L_MASK                (0x3U)
19799 #define CAN_ERRIAR_INJADDR_L_SHIFT               (0U)
19800 /*! INJADDR_L - Error Injection Address Low
19801  */
19802 #define CAN_ERRIAR_INJADDR_L(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
19803 
19804 #define CAN_ERRIAR_INJADDR_H_MASK                (0x3FFCU)
19805 #define CAN_ERRIAR_INJADDR_H_SHIFT               (2U)
19806 /*! INJADDR_H - Error Injection Address High
19807  */
19808 #define CAN_ERRIAR_INJADDR_H(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
19809 /*! @} */
19810 
19811 /*! @name ERRIDPR - Error Injection Data Pattern register */
19812 /*! @{ */
19813 
19814 #define CAN_ERRIDPR_DFLIP_MASK                   (0xFFFFFFFFU)
19815 #define CAN_ERRIDPR_DFLIP_SHIFT                  (0U)
19816 /*! DFLIP - Data flip pattern
19817  */
19818 #define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
19819 /*! @} */
19820 
19821 /*! @name ERRIPPR - Error Injection Parity Pattern register */
19822 /*! @{ */
19823 
19824 #define CAN_ERRIPPR_PFLIP0_MASK                  (0x1FU)
19825 #define CAN_ERRIPPR_PFLIP0_SHIFT                 (0U)
19826 /*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)
19827  */
19828 #define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
19829 
19830 #define CAN_ERRIPPR_PFLIP1_MASK                  (0x1F00U)
19831 #define CAN_ERRIPPR_PFLIP1_SHIFT                 (8U)
19832 /*! PFLIP1 - Parity Flip Pattern For Byte 1
19833  */
19834 #define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
19835 
19836 #define CAN_ERRIPPR_PFLIP2_MASK                  (0x1F0000U)
19837 #define CAN_ERRIPPR_PFLIP2_SHIFT                 (16U)
19838 /*! PFLIP2 - Parity Flip Pattern For Byte 2
19839  */
19840 #define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
19841 
19842 #define CAN_ERRIPPR_PFLIP3_MASK                  (0x1F000000U)
19843 #define CAN_ERRIPPR_PFLIP3_SHIFT                 (24U)
19844 /*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)
19845  */
19846 #define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
19847 /*! @} */
19848 
19849 /*! @name RERRAR - Error Report Address register */
19850 /*! @{ */
19851 
19852 #define CAN_RERRAR_ERRADDR_MASK                  (0x3FFFU)
19853 #define CAN_RERRAR_ERRADDR_SHIFT                 (0U)
19854 /*! ERRADDR - Address Where Error Detected
19855  */
19856 #define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
19857 
19858 #define CAN_RERRAR_SAID_MASK                     (0x70000U)
19859 #define CAN_RERRAR_SAID_SHIFT                    (16U)
19860 /*! SAID - SAID
19861  */
19862 #define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
19863 
19864 #define CAN_RERRAR_NCE_MASK                      (0x1000000U)
19865 #define CAN_RERRAR_NCE_SHIFT                     (24U)
19866 /*! NCE - Non-Correctable Error
19867  *  0b0..Reporting a correctable error
19868  *  0b1..Reporting a non-correctable error
19869  */
19870 #define CAN_RERRAR_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
19871 /*! @} */
19872 
19873 /*! @name RERRDR - Error Report Data register */
19874 /*! @{ */
19875 
19876 #define CAN_RERRDR_RDATA_MASK                    (0xFFFFFFFFU)
19877 #define CAN_RERRDR_RDATA_SHIFT                   (0U)
19878 /*! RDATA - Raw data word read from memory with error
19879  */
19880 #define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
19881 /*! @} */
19882 
19883 /*! @name RERRSYNR - Error Report Syndrome register */
19884 /*! @{ */
19885 
19886 #define CAN_RERRSYNR_SYND0_MASK                  (0x1FU)
19887 #define CAN_RERRSYNR_SYND0_SHIFT                 (0U)
19888 /*! SYND0 - Error Syndrome For Byte 0 (least significant)
19889  */
19890 #define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
19891 
19892 #define CAN_RERRSYNR_BE0_MASK                    (0x80U)
19893 #define CAN_RERRSYNR_BE0_SHIFT                   (7U)
19894 /*! BE0 - Byte Enabled For Byte 0 (least significant)
19895  *  0b0..The byte was not read.
19896  *  0b1..The byte was read.
19897  */
19898 #define CAN_RERRSYNR_BE0(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
19899 
19900 #define CAN_RERRSYNR_SYND1_MASK                  (0x1F00U)
19901 #define CAN_RERRSYNR_SYND1_SHIFT                 (8U)
19902 /*! SYND1 - Error Syndrome for Byte 1
19903  */
19904 #define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
19905 
19906 #define CAN_RERRSYNR_BE1_MASK                    (0x8000U)
19907 #define CAN_RERRSYNR_BE1_SHIFT                   (15U)
19908 /*! BE1 - Byte Enabled For Byte 1
19909  *  0b0..The byte was not read.
19910  *  0b1..The byte was read.
19911  */
19912 #define CAN_RERRSYNR_BE1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
19913 
19914 #define CAN_RERRSYNR_SYND2_MASK                  (0x1F0000U)
19915 #define CAN_RERRSYNR_SYND2_SHIFT                 (16U)
19916 /*! SYND2 - Error Syndrome For Byte 2
19917  */
19918 #define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
19919 
19920 #define CAN_RERRSYNR_BE2_MASK                    (0x800000U)
19921 #define CAN_RERRSYNR_BE2_SHIFT                   (23U)
19922 /*! BE2 - Byte Enabled For Byte 2
19923  *  0b0..The byte was not read.
19924  *  0b1..The byte was read.
19925  */
19926 #define CAN_RERRSYNR_BE2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
19927 
19928 #define CAN_RERRSYNR_SYND3_MASK                  (0x1F000000U)
19929 #define CAN_RERRSYNR_SYND3_SHIFT                 (24U)
19930 /*! SYND3 - Error Syndrome For Byte 3 (most significant)
19931  */
19932 #define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
19933 
19934 #define CAN_RERRSYNR_BE3_MASK                    (0x80000000U)
19935 #define CAN_RERRSYNR_BE3_SHIFT                   (31U)
19936 /*! BE3 - Byte Enabled For Byte 3 (most significant)
19937  *  0b0..The byte was not read.
19938  *  0b1..The byte was read.
19939  */
19940 #define CAN_RERRSYNR_BE3(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
19941 /*! @} */
19942 
19943 /*! @name ERRSR - Error Status register */
19944 /*! @{ */
19945 
19946 #define CAN_ERRSR_CEIOF_MASK                     (0x1U)
19947 #define CAN_ERRSR_CEIOF_SHIFT                    (0U)
19948 /*! CEIOF - Correctable Error Interrupt Overrun Flag
19949  *  0b0..No overrun on correctable errors
19950  *  0b1..Overrun on correctable errors
19951  */
19952 #define CAN_ERRSR_CEIOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
19953 
19954 #define CAN_ERRSR_FANCEIOF_MASK                  (0x4U)
19955 #define CAN_ERRSR_FANCEIOF_SHIFT                 (2U)
19956 /*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
19957  *  0b0..No overrun on non-correctable errors in FlexCAN access
19958  *  0b1..Overrun on non-correctable errors in FlexCAN access
19959  */
19960 #define CAN_ERRSR_FANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
19961 
19962 #define CAN_ERRSR_HANCEIOF_MASK                  (0x8U)
19963 #define CAN_ERRSR_HANCEIOF_SHIFT                 (3U)
19964 /*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
19965  *  0b0..No overrun on non-correctable errors in host access
19966  *  0b1..Overrun on non-correctable errors in host access
19967  */
19968 #define CAN_ERRSR_HANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
19969 
19970 #define CAN_ERRSR_CEIF_MASK                      (0x10000U)
19971 #define CAN_ERRSR_CEIF_SHIFT                     (16U)
19972 /*! CEIF - Correctable Error Interrupt Flag
19973  *  0b0..No correctable errors were detected so far.
19974  *  0b1..A correctable error was detected.
19975  */
19976 #define CAN_ERRSR_CEIF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
19977 
19978 #define CAN_ERRSR_FANCEIF_MASK                   (0x40000U)
19979 #define CAN_ERRSR_FANCEIF_SHIFT                  (18U)
19980 /*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
19981  *  0b0..No non-correctable errors were detected in FlexCAN accesses so far.
19982  *  0b1..A non-correctable error was detected in a FlexCAN access.
19983  */
19984 #define CAN_ERRSR_FANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
19985 
19986 #define CAN_ERRSR_HANCEIF_MASK                   (0x80000U)
19987 #define CAN_ERRSR_HANCEIF_SHIFT                  (19U)
19988 /*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
19989  *  0b0..No non-correctable errors were detected in host accesses so far.
19990  *  0b1..A non-correctable error was detected in a host access.
19991  */
19992 #define CAN_ERRSR_HANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
19993 /*! @} */
19994 
19995 /*! @name FDCTRL - CAN FD Control register */
19996 /*! @{ */
19997 
19998 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
19999 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
20000 /*! TDCVAL - Transceiver Delay Compensation Value
20001  */
20002 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
20003 
20004 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
20005 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
20006 /*! TDCOFF - Transceiver Delay Compensation Offset
20007  */
20008 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
20009 
20010 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
20011 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
20012 /*! TDCFAIL - Transceiver Delay Compensation Fail
20013  *  0b0..Measured loop delay is in range.
20014  *  0b1..Measured loop delay is out of range.
20015  */
20016 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
20017 
20018 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
20019 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
20020 /*! TDCEN - Transceiver Delay Compensation Enable
20021  *  0b0..TDC is disabled
20022  *  0b1..TDC is enabled
20023  */
20024 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
20025 
20026 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
20027 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
20028 /*! MBDSR0 - Message Buffer Data Size for Region 0
20029  *  0b00..Selects 8 bytes per message buffer.
20030  *  0b01..Selects 16 bytes per message buffer.
20031  *  0b10..Selects 32 bytes per message buffer.
20032  *  0b11..Selects 64 bytes per message buffer.
20033  */
20034 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
20035 
20036 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
20037 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
20038 /*! MBDSR1 - Message Buffer Data Size for Region 1
20039  *  0b00..Selects 8 bytes per message buffer.
20040  *  0b01..Selects 16 bytes per message buffer.
20041  *  0b10..Selects 32 bytes per message buffer.
20042  *  0b11..Selects 64 bytes per message buffer.
20043  */
20044 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
20045 
20046 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
20047 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
20048 /*! FDRATE - Bit Rate Switch Enable
20049  *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
20050  *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
20051  */
20052 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
20053 /*! @} */
20054 
20055 /*! @name FDCBT - CAN FD Bit Timing register */
20056 /*! @{ */
20057 
20058 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
20059 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
20060 /*! FPSEG2 - Fast Phase Segment 2
20061  */
20062 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
20063 
20064 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
20065 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
20066 /*! FPSEG1 - Fast Phase Segment 1
20067  */
20068 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
20069 
20070 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
20071 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
20072 /*! FPROPSEG - Fast Propagation Segment
20073  */
20074 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
20075 
20076 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
20077 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
20078 /*! FRJW - Fast Resync Jump Width
20079  */
20080 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
20081 
20082 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
20083 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
20084 /*! FPRESDIV - Fast Prescaler Division Factor
20085  */
20086 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
20087 /*! @} */
20088 
20089 /*! @name FDCRC - CAN FD CRC register */
20090 /*! @{ */
20091 
20092 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
20093 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
20094 /*! FD_TXCRC - Extended Transmitted CRC value
20095  */
20096 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
20097 
20098 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
20099 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
20100 /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
20101  */
20102 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
20103 /*! @} */
20104 
20105 
20106 /*!
20107  * @}
20108  */ /* end of group CAN_Register_Masks */
20109 
20110 
20111 /* CAN - Peripheral instance base addresses */
20112 /** Peripheral CAN1 base address */
20113 #define CAN1_BASE                                (0x400C4000u)
20114 /** Peripheral CAN1 base pointer */
20115 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
20116 /** Peripheral CAN2 base address */
20117 #define CAN2_BASE                                (0x400C8000u)
20118 /** Peripheral CAN2 base pointer */
20119 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
20120 /** Peripheral CAN3 base address */
20121 #define CAN3_BASE                                (0x40C3C000u)
20122 /** Peripheral CAN3 base pointer */
20123 #define CAN3                                     ((CAN_Type *)CAN3_BASE)
20124 /** Array initializer of CAN peripheral base addresses */
20125 #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
20126 /** Array initializer of CAN peripheral base pointers */
20127 #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
20128 /** Interrupt vectors for the CAN peripheral type */
20129 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20130 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20131 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20132 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20133 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20134 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20135 
20136 /*!
20137  * @}
20138  */ /* end of group CAN_Peripheral_Access_Layer */
20139 
20140 
20141 /* ----------------------------------------------------------------------------
20142    -- CAN_WRAPPER Peripheral Access Layer
20143    ---------------------------------------------------------------------------- */
20144 
20145 /*!
20146  * @addtogroup CAN_WRAPPER_Peripheral_Access_Layer CAN_WRAPPER Peripheral Access Layer
20147  * @{
20148  */
20149 
20150 /** CAN_WRAPPER - Register Layout Typedef */
20151 typedef struct {
20152        uint8_t RESERVED_0[2528];
20153   __IO uint32_t GFWR;                              /**< Glitch Filter Width Register, offset: 0x9E0 */
20154 } CAN_WRAPPER_Type;
20155 
20156 /* ----------------------------------------------------------------------------
20157    -- CAN_WRAPPER Register Masks
20158    ---------------------------------------------------------------------------- */
20159 
20160 /*!
20161  * @addtogroup CAN_WRAPPER_Register_Masks CAN_WRAPPER Register Masks
20162  * @{
20163  */
20164 
20165 /*! @name GFWR - Glitch Filter Width Register */
20166 /*! @{ */
20167 
20168 #define CAN_WRAPPER_GFWR_GFWR_MASK               (0xFFU)
20169 #define CAN_WRAPPER_GFWR_GFWR_SHIFT              (0U)
20170 /*! GFWR - Glitch Filter Width
20171  */
20172 #define CAN_WRAPPER_GFWR_GFWR(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK)
20173 /*! @} */
20174 
20175 
20176 /*!
20177  * @}
20178  */ /* end of group CAN_WRAPPER_Register_Masks */
20179 
20180 
20181 /* CAN_WRAPPER - Peripheral instance base addresses */
20182 /** Peripheral CAN1_WRAPPER base address */
20183 #define CAN1_WRAPPER_BASE                        (0x400C4000u)
20184 /** Peripheral CAN1_WRAPPER base pointer */
20185 #define CAN1_WRAPPER                             ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
20186 /** Peripheral CAN2_WRAPPER base address */
20187 #define CAN2_WRAPPER_BASE                        (0x400C8000u)
20188 /** Peripheral CAN2_WRAPPER base pointer */
20189 #define CAN2_WRAPPER                             ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
20190 /** Peripheral CAN3_WRAPPER base address */
20191 #define CAN3_WRAPPER_BASE                        (0x40C3C000u)
20192 /** Peripheral CAN3_WRAPPER base pointer */
20193 #define CAN3_WRAPPER                             ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
20194 /** Array initializer of CAN_WRAPPER peripheral base addresses */
20195 #define CAN_WRAPPER_BASE_ADDRS                   { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
20196 /** Array initializer of CAN_WRAPPER peripheral base pointers */
20197 #define CAN_WRAPPER_BASE_PTRS                    { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
20198 
20199 /*!
20200  * @}
20201  */ /* end of group CAN_WRAPPER_Peripheral_Access_Layer */
20202 
20203 
20204 /* ----------------------------------------------------------------------------
20205    -- CCM Peripheral Access Layer
20206    ---------------------------------------------------------------------------- */
20207 
20208 /*!
20209  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
20210  * @{
20211  */
20212 
20213 /** CCM - Register Layout Typedef */
20214 typedef struct {
20215   struct {                                         /* offset: 0x0, array step: 0x80 */
20216     __IO uint32_t CONTROL;                           /**< Clock root control, array offset: 0x0, array step: 0x80 */
20217     __IO uint32_t CONTROL_SET;                       /**< Clock root control, array offset: 0x4, array step: 0x80 */
20218     __IO uint32_t CONTROL_CLR;                       /**< Clock root control, array offset: 0x8, array step: 0x80 */
20219     __IO uint32_t CONTROL_TOG;                       /**< Clock root control, array offset: 0xC, array step: 0x80 */
20220          uint8_t RESERVED_0[16];
20221     __I  uint32_t STATUS0;                           /**< Clock root working status, array offset: 0x20, array step: 0x80 */
20222     __I  uint32_t STATUS1;                           /**< Clock root low power status, array offset: 0x24, array step: 0x80 */
20223          uint8_t RESERVED_1[4];
20224     __I  uint32_t CONFIG;                            /**< Clock root configuration, array offset: 0x2C, array step: 0x80 */
20225     __IO uint32_t AUTHEN;                            /**< Clock root access control, array offset: 0x30, array step: 0x80 */
20226     __IO uint32_t AUTHEN_SET;                        /**< Clock root access control, array offset: 0x34, array step: 0x80 */
20227     __IO uint32_t AUTHEN_CLR;                        /**< Clock root access control, array offset: 0x38, array step: 0x80 */
20228     __IO uint32_t AUTHEN_TOG;                        /**< Clock root access control, array offset: 0x3C, array step: 0x80 */
20229     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4 */
20230   } CLOCK_ROOT[79];
20231        uint8_t RESERVED_0[6272];
20232   struct {                                         /* offset: 0x4000, array step: 0x80 */
20233     __IO uint32_t CONTROL;                           /**< Clock group control, array offset: 0x4000, array step: 0x80 */
20234     __IO uint32_t CONTROL_SET;                       /**< Clock group control, array offset: 0x4004, array step: 0x80 */
20235     __IO uint32_t CONTROL_CLR;                       /**< Clock group control, array offset: 0x4008, array step: 0x80 */
20236     __IO uint32_t CONTROL_TOG;                       /**< Clock group control, array offset: 0x400C, array step: 0x80 */
20237          uint8_t RESERVED_0[16];
20238     __IO uint32_t STATUS0;                           /**< Clock group working status, array offset: 0x4020, array step: 0x80 */
20239     __I  uint32_t STATUS1;                           /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */
20240          uint8_t RESERVED_1[4];
20241     __I  uint32_t CONFIG;                            /**< Clock group configuration, array offset: 0x402C, array step: 0x80 */
20242     __IO uint32_t AUTHEN;                            /**< Clock group access control, array offset: 0x4030, array step: 0x80 */
20243     __IO uint32_t AUTHEN_SET;                        /**< Clock group access control, array offset: 0x4034, array step: 0x80 */
20244     __IO uint32_t AUTHEN_CLR;                        /**< Clock group access control, array offset: 0x4038, array step: 0x80 */
20245     __IO uint32_t AUTHEN_TOG;                        /**< Clock group access control, array offset: 0x403C, array step: 0x80 */
20246     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4 */
20247   } CLOCK_GROUP[2];
20248        uint8_t RESERVED_1[1792];
20249   struct {                                         /* offset: 0x4800, array step: 0x20 */
20250     __IO uint32_t GPR_SHARED;                        /**< General Purpose Register, array offset: 0x4800, array step: 0x20 */
20251     __IO uint32_t SET;                               /**< General Purpose Register, array offset: 0x4804, array step: 0x20 */
20252     __IO uint32_t CLR;                               /**< General Purpose Register, array offset: 0x4808, array step: 0x20 */
20253     __IO uint32_t TOG;                               /**< General Purpose Register, array offset: 0x480C, array step: 0x20 */
20254     __IO uint32_t AUTHEN;                            /**< GPR access control, array offset: 0x4810, array step: 0x20 */
20255     __IO uint32_t AUTHEN_SET;                        /**< GPR access control, array offset: 0x4814, array step: 0x20 */
20256     __IO uint32_t AUTHEN_CLR;                        /**< GPR access control, array offset: 0x4818, array step: 0x20 */
20257     __IO uint32_t AUTHEN_TOG;                        /**< GPR access control, array offset: 0x481C, array step: 0x20 */
20258   } GPR_SHARED[8];
20259        uint8_t RESERVED_2[800];
20260   __IO uint32_t GPR_PRIVATE1;                      /**< General Purpose Register, offset: 0x4C20 */
20261   __IO uint32_t GPR_PRIVATE1_SET;                  /**< General Purpose Register, offset: 0x4C24 */
20262   __IO uint32_t GPR_PRIVATE1_CLR;                  /**< General Purpose Register, offset: 0x4C28 */
20263   __IO uint32_t GPR_PRIVATE1_TOG;                  /**< General Purpose Register, offset: 0x4C2C */
20264   __IO uint32_t GPR_PRIVATE1_AUTHEN;               /**< GPR access control, offset: 0x4C30 */
20265   __IO uint32_t GPR_PRIVATE1_AUTHEN_SET;           /**< GPR access control, offset: 0x4C34 */
20266   __IO uint32_t GPR_PRIVATE1_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C38 */
20267   __IO uint32_t GPR_PRIVATE1_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C3C */
20268   __IO uint32_t GPR_PRIVATE2;                      /**< General Purpose Register, offset: 0x4C40 */
20269   __IO uint32_t GPR_PRIVATE2_SET;                  /**< General Purpose Register, offset: 0x4C44 */
20270   __IO uint32_t GPR_PRIVATE2_CLR;                  /**< General Purpose Register, offset: 0x4C48 */
20271   __IO uint32_t GPR_PRIVATE2_TOG;                  /**< General Purpose Register, offset: 0x4C4C */
20272   __IO uint32_t GPR_PRIVATE2_AUTHEN;               /**< GPR access control, offset: 0x4C50 */
20273   __IO uint32_t GPR_PRIVATE2_AUTHEN_SET;           /**< GPR access control, offset: 0x4C54 */
20274   __IO uint32_t GPR_PRIVATE2_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C58 */
20275   __IO uint32_t GPR_PRIVATE2_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C5C */
20276   __IO uint32_t GPR_PRIVATE3;                      /**< General Purpose Register, offset: 0x4C60 */
20277   __IO uint32_t GPR_PRIVATE3_SET;                  /**< General Purpose Register, offset: 0x4C64 */
20278   __IO uint32_t GPR_PRIVATE3_CLR;                  /**< General Purpose Register, offset: 0x4C68 */
20279   __IO uint32_t GPR_PRIVATE3_TOG;                  /**< General Purpose Register, offset: 0x4C6C */
20280   __IO uint32_t GPR_PRIVATE3_AUTHEN;               /**< GPR access control, offset: 0x4C70 */
20281   __IO uint32_t GPR_PRIVATE3_AUTHEN_SET;           /**< GPR access control, offset: 0x4C74 */
20282   __IO uint32_t GPR_PRIVATE3_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C78 */
20283   __IO uint32_t GPR_PRIVATE3_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C7C */
20284   __IO uint32_t GPR_PRIVATE4;                      /**< General Purpose Register, offset: 0x4C80 */
20285   __IO uint32_t GPR_PRIVATE4_SET;                  /**< General Purpose Register, offset: 0x4C84 */
20286   __IO uint32_t GPR_PRIVATE4_CLR;                  /**< General Purpose Register, offset: 0x4C88 */
20287   __IO uint32_t GPR_PRIVATE4_TOG;                  /**< General Purpose Register, offset: 0x4C8C */
20288   __IO uint32_t GPR_PRIVATE4_AUTHEN;               /**< GPR access control, offset: 0x4C90 */
20289   __IO uint32_t GPR_PRIVATE4_AUTHEN_SET;           /**< GPR access control, offset: 0x4C94 */
20290   __IO uint32_t GPR_PRIVATE4_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C98 */
20291   __IO uint32_t GPR_PRIVATE4_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C9C */
20292   __IO uint32_t GPR_PRIVATE5;                      /**< General Purpose Register, offset: 0x4CA0 */
20293   __IO uint32_t GPR_PRIVATE5_SET;                  /**< General Purpose Register, offset: 0x4CA4 */
20294   __IO uint32_t GPR_PRIVATE5_CLR;                  /**< General Purpose Register, offset: 0x4CA8 */
20295   __IO uint32_t GPR_PRIVATE5_TOG;                  /**< General Purpose Register, offset: 0x4CAC */
20296   __IO uint32_t GPR_PRIVATE5_AUTHEN;               /**< GPR access control, offset: 0x4CB0 */
20297   __IO uint32_t GPR_PRIVATE5_AUTHEN_SET;           /**< GPR access control, offset: 0x4CB4 */
20298   __IO uint32_t GPR_PRIVATE5_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CB8 */
20299   __IO uint32_t GPR_PRIVATE5_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CBC */
20300   __IO uint32_t GPR_PRIVATE6;                      /**< General Purpose Register, offset: 0x4CC0 */
20301   __IO uint32_t GPR_PRIVATE6_SET;                  /**< General Purpose Register, offset: 0x4CC4 */
20302   __IO uint32_t GPR_PRIVATE6_CLR;                  /**< General Purpose Register, offset: 0x4CC8 */
20303   __IO uint32_t GPR_PRIVATE6_TOG;                  /**< General Purpose Register, offset: 0x4CCC */
20304   __IO uint32_t GPR_PRIVATE6_AUTHEN;               /**< GPR access control, offset: 0x4CD0 */
20305   __IO uint32_t GPR_PRIVATE6_AUTHEN_SET;           /**< GPR access control, offset: 0x4CD4 */
20306   __IO uint32_t GPR_PRIVATE6_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CD8 */
20307   __IO uint32_t GPR_PRIVATE6_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CDC */
20308   __IO uint32_t GPR_PRIVATE7;                      /**< General Purpose Register, offset: 0x4CE0 */
20309   __IO uint32_t GPR_PRIVATE7_SET;                  /**< General Purpose Register, offset: 0x4CE4 */
20310   __IO uint32_t GPR_PRIVATE7_CLR;                  /**< General Purpose Register, offset: 0x4CE8 */
20311   __IO uint32_t GPR_PRIVATE7_TOG;                  /**< General Purpose Register, offset: 0x4CEC */
20312   __IO uint32_t GPR_PRIVATE7_AUTHEN;               /**< GPR access control, offset: 0x4CF0 */
20313   __IO uint32_t GPR_PRIVATE7_AUTHEN_SET;           /**< GPR access control, offset: 0x4CF4 */
20314   __IO uint32_t GPR_PRIVATE7_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CF8 */
20315   __IO uint32_t GPR_PRIVATE7_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CFC */
20316        uint8_t RESERVED_3[768];
20317   struct {                                         /* offset: 0x5000, array step: 0x20 */
20318     __IO uint32_t DIRECT;                            /**< Clock source direct control, array offset: 0x5000, array step: 0x20 */
20319     __IO uint32_t DOMAINr;                           /**< Clock source domain control, array offset: 0x5004, array step: 0x20 */
20320     __IO uint32_t SETPOINT;                          /**< Clock source Setpoint setting, array offset: 0x5008, array step: 0x20 */
20321          uint8_t RESERVED_0[4];
20322     __I  uint32_t STATUS0;                           /**< Clock source working status, array offset: 0x5010, array step: 0x20 */
20323     __I  uint32_t STATUS1;                           /**< Clock source low power status, array offset: 0x5014, array step: 0x20 */
20324     __I  uint32_t CONFIG;                            /**< Clock source configuration, array offset: 0x5018, array step: 0x20 */
20325     __IO uint32_t AUTHEN;                            /**< Clock source access control, array offset: 0x501C, array step: 0x20 */
20326   } OSCPLL[29];
20327        uint8_t RESERVED_4[3168];
20328   struct {                                         /* offset: 0x6000, array step: 0x20 */
20329     __IO uint32_t DIRECT;                            /**< LPCG direct control, array offset: 0x6000, array step: 0x20 */
20330     __IO uint32_t DOMAINr;                           /**< LPCG domain control, array offset: 0x6004, array step: 0x20 */
20331     __IO uint32_t SETPOINT;                          /**< LPCG Setpoint setting, array offset: 0x6008, array step: 0x20 */
20332          uint8_t RESERVED_0[4];
20333     __I  uint32_t STATUS0;                           /**< LPCG working status, array offset: 0x6010, array step: 0x20 */
20334     __I  uint32_t STATUS1;                           /**< LPCG low power status, array offset: 0x6014, array step: 0x20 */
20335     __I  uint32_t CONFIG;                            /**< LPCG configuration, array offset: 0x6018, array step: 0x20 */
20336     __IO uint32_t AUTHEN;                            /**< LPCG access control, array offset: 0x601C, array step: 0x20 */
20337   } LPCG[138];
20338 } CCM_Type;
20339 
20340 /* ----------------------------------------------------------------------------
20341    -- CCM Register Masks
20342    ---------------------------------------------------------------------------- */
20343 
20344 /*!
20345  * @addtogroup CCM_Register_Masks CCM Register Masks
20346  * @{
20347  */
20348 
20349 /*! @name CLOCK_ROOT_CONTROL - Clock root control */
20350 /*! @{ */
20351 
20352 #define CCM_CLOCK_ROOT_CONTROL_DIV_MASK          (0xFFU)
20353 #define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT         (0U)
20354 /*! DIV - Clock divider
20355  */
20356 #define CCM_CLOCK_ROOT_CONTROL_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
20357 
20358 #define CCM_CLOCK_ROOT_CONTROL_MUX_MASK          (0x700U)
20359 #define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT         (8U)
20360 /*! MUX - Clock multiplexer
20361  */
20362 #define CCM_CLOCK_ROOT_CONTROL_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
20363 
20364 #define CCM_CLOCK_ROOT_CONTROL_OFF_MASK          (0x1000000U)
20365 #define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT         (24U)
20366 /*! OFF - OFF
20367  *  0b0..Turn on clock
20368  *  0b1..Turn off clock
20369  */
20370 #define CCM_CLOCK_ROOT_CONTROL_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
20371 /*! @} */
20372 
20373 /* The count of CCM_CLOCK_ROOT_CONTROL */
20374 #define CCM_CLOCK_ROOT_CONTROL_COUNT             (79U)
20375 
20376 /*! @name CLOCK_ROOT_CONTROL_SET - Clock root control */
20377 /*! @{ */
20378 
20379 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK      (0xFFU)
20380 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT     (0U)
20381 /*! DIV - Clock divider
20382  */
20383 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
20384 
20385 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK      (0x700U)
20386 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT     (8U)
20387 /*! MUX - Clock multiplexer
20388  */
20389 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
20390 
20391 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK      (0x1000000U)
20392 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT     (24U)
20393 /*! OFF - OFF
20394  */
20395 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
20396 /*! @} */
20397 
20398 /* The count of CCM_CLOCK_ROOT_CONTROL_SET */
20399 #define CCM_CLOCK_ROOT_CONTROL_SET_COUNT         (79U)
20400 
20401 /*! @name CLOCK_ROOT_CONTROL_CLR - Clock root control */
20402 /*! @{ */
20403 
20404 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK      (0xFFU)
20405 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT     (0U)
20406 /*! DIV - Clock divider
20407  */
20408 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
20409 
20410 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK      (0x700U)
20411 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT     (8U)
20412 /*! MUX - Clock multiplexer
20413  */
20414 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
20415 
20416 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK      (0x1000000U)
20417 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT     (24U)
20418 /*! OFF - OFF
20419  */
20420 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
20421 /*! @} */
20422 
20423 /* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
20424 #define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT         (79U)
20425 
20426 /*! @name CLOCK_ROOT_CONTROL_TOG - Clock root control */
20427 /*! @{ */
20428 
20429 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK      (0xFFU)
20430 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT     (0U)
20431 /*! DIV - Clock divider
20432  */
20433 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
20434 
20435 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK      (0x700U)
20436 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT     (8U)
20437 /*! MUX - Clock multiplexer
20438  */
20439 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
20440 
20441 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK      (0x1000000U)
20442 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT     (24U)
20443 /*! OFF - OFF
20444  */
20445 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
20446 /*! @} */
20447 
20448 /* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
20449 #define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT         (79U)
20450 
20451 /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */
20452 /*! @{ */
20453 
20454 #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK          (0xFFU)
20455 #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT         (0U)
20456 /*! DIV - Current clock root DIV setting
20457  */
20458 #define CCM_CLOCK_ROOT_STATUS0_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
20459 
20460 #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK          (0x700U)
20461 #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT         (8U)
20462 /*! MUX - Current clock root MUX setting
20463  */
20464 #define CCM_CLOCK_ROOT_STATUS0_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
20465 
20466 #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK          (0x1000000U)
20467 #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT         (24U)
20468 /*! OFF - Current clock root OFF setting
20469  *  0b0..Clock is running
20470  *  0b1..Clock is disabled/off
20471  */
20472 #define CCM_CLOCK_ROOT_STATUS0_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
20473 
20474 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK    (0x8000000U)
20475 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT   (27U)
20476 /*! POWERDOWN - Current clock root POWERDOWN setting
20477  *  0b1..Clock root is Powered Down
20478  *  0b0..Clock root is running
20479  */
20480 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK)
20481 
20482 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
20483 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT  (28U)
20484 /*! SLICE_BUSY - Internal updating in generation logic
20485  *  0b1..Clock generation logic is applying the new setting
20486  *  0b0..Clock generation logic is not busy
20487  */
20488 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
20489 
20490 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
20491 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
20492 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
20493  *  0b1..Synchronization in process
20494  *  0b0..Synchronization not in process
20495  */
20496 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
20497 
20498 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
20499 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U)
20500 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
20501  *  0b1..Synchronization in process
20502  *  0b0..Synchronization not in process
20503  */
20504 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK)
20505 
20506 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK     (0x80000000U)
20507 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT    (31U)
20508 /*! CHANGING - Internal updating in clock root
20509  *  0b1..Clock generation logic is updating currently
20510  *  0b0..Clock Status is not updating currently
20511  */
20512 #define CCM_CLOCK_ROOT_STATUS0_CHANGING(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
20513 /*! @} */
20514 
20515 /* The count of CCM_CLOCK_ROOT_STATUS0 */
20516 #define CCM_CLOCK_ROOT_STATUS0_COUNT             (79U)
20517 
20518 /*! @name CLOCK_ROOT_STATUS1 - Clock root low power status */
20519 /*! @{ */
20520 
20521 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
20522 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U)
20523 /*! TARGET_SETPOINT - Target Setpoint
20524  */
20525 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK)
20526 
20527 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
20528 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
20529 /*! CURRENT_SETPOINT - Current Setpoint
20530  */
20531 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK)
20532 
20533 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
20534 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U)
20535 /*! DOWN_REQUEST - Clock frequency decrease request
20536  *  0b1..Frequency decrease requested
20537  *  0b0..Frequency decrease not requested
20538  */
20539 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK)
20540 
20541 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK    (0x2000000U)
20542 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT   (25U)
20543 /*! DOWN_DONE - Clock frequency decrease finish
20544  *  0b1..Frequency decrease completed
20545  *  0b0..Frequency decrease not completed
20546  */
20547 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK)
20548 
20549 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK   (0x4000000U)
20550 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT  (26U)
20551 /*! UP_REQUEST - Clock frequency increase request
20552  *  0b1..Frequency increase requested
20553  *  0b0..Frequency increase not requested
20554  */
20555 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK)
20556 
20557 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK      (0x8000000U)
20558 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT     (27U)
20559 /*! UP_DONE - Clock frequency increase finish
20560  *  0b1..Frequency increase completed
20561  *  0b0..Frequency increase not completed
20562  */
20563 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK)
20564 /*! @} */
20565 
20566 /* The count of CCM_CLOCK_ROOT_STATUS1 */
20567 #define CCM_CLOCK_ROOT_STATUS1_COUNT             (79U)
20568 
20569 /*! @name CLOCK_ROOT_CONFIG - Clock root configuration */
20570 /*! @{ */
20571 
20572 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
20573 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
20574 /*! SETPOINT_PRESENT - Setpoint present
20575  *  0b1..Setpoint is implemented.
20576  *  0b0..Setpoint is not implemented.
20577  */
20578 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK)
20579 /*! @} */
20580 
20581 /* The count of CCM_CLOCK_ROOT_CONFIG */
20582 #define CCM_CLOCK_ROOT_CONFIG_COUNT              (79U)
20583 
20584 /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */
20585 /*! @{ */
20586 
20587 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK       (0x1U)
20588 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT      (0U)
20589 /*! TZ_USER - User access
20590  *  0b1..Clock can be changed in user mode
20591  *  0b0..Clock cannot be changed in user mode
20592  */
20593 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
20594 
20595 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK         (0x2U)
20596 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT        (1U)
20597 /*! TZ_NS - Non-secure access
20598  *  0b0..Cannot be changed in Non-secure mode
20599  *  0b1..Can be changed in Non-secure mode
20600  */
20601 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
20602 
20603 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK       (0x10U)
20604 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT      (4U)
20605 /*! LOCK_TZ - Lock truszone setting
20606  *  0b0..Trustzone setting is not locked
20607  *  0b1..Trustzone setting is locked
20608  */
20609 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
20610 
20611 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK    (0xF00U)
20612 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT   (8U)
20613 /*! WHITE_LIST - Whitelist
20614  *  0b0000..This domain is NOT allowed to change clock
20615  *  0b0001..This domain is allowed to change clock
20616  */
20617 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
20618 
20619 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK     (0x1000U)
20620 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT    (12U)
20621 /*! LOCK_LIST - Lock Whitelist
20622  *  0b0..Whitelist is not locked
20623  *  0b1..Whitelist is locked
20624  */
20625 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
20626 
20627 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
20628 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
20629 /*! DOMAIN_MODE - Low power and access control by domain
20630  *  0b1..Clock works in Domain Mode
20631  *  0b0..Clock does NOT work in Domain Mode
20632  */
20633 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK)
20634 
20635 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
20636 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U)
20637 /*! SETPOINT_MODE - Low power and access control by Setpoint
20638  *  0b1..Clock works in Setpoint Mode
20639  *  0b0..Clock does NOT work in Setpoint Mode
20640  */
20641 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK)
20642 
20643 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK     (0x100000U)
20644 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT    (20U)
20645 /*! LOCK_MODE - Lock low power and access mode
20646  *  0b0..MODE is not locked
20647  *  0b1..MODE is locked
20648  */
20649 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK)
20650 /*! @} */
20651 
20652 /* The count of CCM_CLOCK_ROOT_AUTHEN */
20653 #define CCM_CLOCK_ROOT_AUTHEN_COUNT              (79U)
20654 
20655 /*! @name CLOCK_ROOT_AUTHEN_SET - Clock root access control */
20656 /*! @{ */
20657 
20658 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK   (0x1U)
20659 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT  (0U)
20660 /*! TZ_USER - User access
20661  */
20662 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK)
20663 
20664 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK     (0x2U)
20665 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT    (1U)
20666 /*! TZ_NS - Non-secure access
20667  */
20668 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK)
20669 
20670 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
20671 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
20672 /*! LOCK_TZ - Lock truszone setting
20673  */
20674 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK)
20675 
20676 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
20677 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
20678 /*! WHITE_LIST - Whitelist
20679  */
20680 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK)
20681 
20682 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
20683 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
20684 /*! LOCK_LIST - Lock Whitelist
20685  */
20686 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK)
20687 
20688 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
20689 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
20690 /*! DOMAIN_MODE - Low power and access control by domain
20691  */
20692 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK)
20693 
20694 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
20695 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
20696 /*! SETPOINT_MODE - Low power and access control by Setpoint
20697  */
20698 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK)
20699 
20700 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
20701 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
20702 /*! LOCK_MODE - Lock low power and access mode
20703  */
20704 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK)
20705 /*! @} */
20706 
20707 /* The count of CCM_CLOCK_ROOT_AUTHEN_SET */
20708 #define CCM_CLOCK_ROOT_AUTHEN_SET_COUNT          (79U)
20709 
20710 /*! @name CLOCK_ROOT_AUTHEN_CLR - Clock root access control */
20711 /*! @{ */
20712 
20713 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
20714 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
20715 /*! TZ_USER - User access
20716  */
20717 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK)
20718 
20719 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
20720 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
20721 /*! TZ_NS - Non-secure access
20722  */
20723 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK)
20724 
20725 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
20726 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
20727 /*! LOCK_TZ - Lock truszone setting
20728  */
20729 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK)
20730 
20731 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
20732 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
20733 /*! WHITE_LIST - Whitelist
20734  */
20735 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK)
20736 
20737 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
20738 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
20739 /*! LOCK_LIST - Lock Whitelist
20740  */
20741 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK)
20742 
20743 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
20744 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
20745 /*! DOMAIN_MODE - Low power and access control by domain
20746  */
20747 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK)
20748 
20749 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
20750 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
20751 /*! SETPOINT_MODE - Low power and access control by Setpoint
20752  */
20753 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK)
20754 
20755 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
20756 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
20757 /*! LOCK_MODE - Lock low power and access mode
20758  */
20759 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK)
20760 /*! @} */
20761 
20762 /* The count of CCM_CLOCK_ROOT_AUTHEN_CLR */
20763 #define CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT          (79U)
20764 
20765 /*! @name CLOCK_ROOT_AUTHEN_TOG - Clock root access control */
20766 /*! @{ */
20767 
20768 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
20769 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
20770 /*! TZ_USER - User access
20771  */
20772 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK)
20773 
20774 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
20775 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
20776 /*! TZ_NS - Non-secure access
20777  */
20778 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK)
20779 
20780 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
20781 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
20782 /*! LOCK_TZ - Lock truszone setting
20783  */
20784 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK)
20785 
20786 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
20787 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
20788 /*! WHITE_LIST - Whitelist
20789  */
20790 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK)
20791 
20792 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
20793 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
20794 /*! LOCK_LIST - Lock Whitelist
20795  */
20796 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK)
20797 
20798 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
20799 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
20800 /*! DOMAIN_MODE - Low power and access control by domain
20801  */
20802 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK)
20803 
20804 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
20805 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
20806 /*! SETPOINT_MODE - Low power and access control by Setpoint
20807  */
20808 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK)
20809 
20810 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
20811 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
20812 /*! LOCK_MODE - Lock low power and access mode
20813  */
20814 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK)
20815 /*! @} */
20816 
20817 /* The count of CCM_CLOCK_ROOT_AUTHEN_TOG */
20818 #define CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT          (79U)
20819 
20820 /*! @name CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting */
20821 /*! @{ */
20822 
20823 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU)
20824 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U)
20825 /*! DIV - Clock divider
20826  */
20827 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK)
20828 
20829 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U)
20830 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U)
20831 /*! MUX - Clock multiplexer
20832  */
20833 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK)
20834 
20835 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
20836 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U)
20837 /*! OFF - OFF
20838  *  0b1..OFF
20839  *  0b0..ON
20840  */
20841 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK)
20842 
20843 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
20844 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
20845 /*! GRADE - Grade
20846  */
20847 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK)
20848 /*! @} */
20849 
20850 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
20851 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U)
20852 
20853 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
20854 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U)
20855 
20856 /*! @name CLOCK_GROUP_CONTROL - Clock group control */
20857 /*! @{ */
20858 
20859 #define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK        (0xFU)
20860 #define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT       (0U)
20861 /*! DIV0 - Clock divider0
20862  */
20863 #define CCM_CLOCK_GROUP_CONTROL_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK)
20864 
20865 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK      (0xFF0000U)
20866 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT     (16U)
20867 /*! RSTDIV - Clock group global restart count
20868  */
20869 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK)
20870 
20871 #define CCM_CLOCK_GROUP_CONTROL_OFF_MASK         (0x1000000U)
20872 #define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT        (24U)
20873 /*! OFF - OFF
20874  *  0b0..Clock is running
20875  *  0b1..Turn off clock
20876  */
20877 #define CCM_CLOCK_GROUP_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK)
20878 /*! @} */
20879 
20880 /* The count of CCM_CLOCK_GROUP_CONTROL */
20881 #define CCM_CLOCK_GROUP_CONTROL_COUNT            (2U)
20882 
20883 /*! @name CLOCK_GROUP_CONTROL_SET - Clock group control */
20884 /*! @{ */
20885 
20886 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK    (0xFU)
20887 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT   (0U)
20888 /*! DIV0 - Clock divider0
20889  */
20890 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK)
20891 
20892 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK  (0xFF0000U)
20893 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U)
20894 /*! RSTDIV - Clock group global restart count
20895  */
20896 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK)
20897 
20898 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK     (0x1000000U)
20899 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT    (24U)
20900 /*! OFF - OFF
20901  */
20902 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK)
20903 /*! @} */
20904 
20905 /* The count of CCM_CLOCK_GROUP_CONTROL_SET */
20906 #define CCM_CLOCK_GROUP_CONTROL_SET_COUNT        (2U)
20907 
20908 /*! @name CLOCK_GROUP_CONTROL_CLR - Clock group control */
20909 /*! @{ */
20910 
20911 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK    (0xFU)
20912 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT   (0U)
20913 /*! DIV0 - Clock divider0
20914  */
20915 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK)
20916 
20917 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK  (0xFF0000U)
20918 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U)
20919 /*! RSTDIV - Clock group global restart count
20920  */
20921 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK)
20922 
20923 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK     (0x1000000U)
20924 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT    (24U)
20925 /*! OFF - OFF
20926  */
20927 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK)
20928 /*! @} */
20929 
20930 /* The count of CCM_CLOCK_GROUP_CONTROL_CLR */
20931 #define CCM_CLOCK_GROUP_CONTROL_CLR_COUNT        (2U)
20932 
20933 /*! @name CLOCK_GROUP_CONTROL_TOG - Clock group control */
20934 /*! @{ */
20935 
20936 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK    (0xFU)
20937 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT   (0U)
20938 /*! DIV0 - Clock divider0
20939  */
20940 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK)
20941 
20942 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK  (0xFF0000U)
20943 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U)
20944 /*! RSTDIV - Clock group global restart count
20945  */
20946 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK)
20947 
20948 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK     (0x1000000U)
20949 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT    (24U)
20950 /*! OFF - OFF
20951  */
20952 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK)
20953 /*! @} */
20954 
20955 /* The count of CCM_CLOCK_GROUP_CONTROL_TOG */
20956 #define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT        (2U)
20957 
20958 /*! @name CLOCK_GROUP_STATUS0 - Clock group working status */
20959 /*! @{ */
20960 
20961 #define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK        (0xFU)
20962 #define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT       (0U)
20963 /*! DIV0 - Clock divider
20964  */
20965 #define CCM_CLOCK_GROUP_STATUS0_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK)
20966 
20967 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK      (0xFF0000U)
20968 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT     (16U)
20969 /*! RSTDIV - Clock divider
20970  */
20971 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK)
20972 
20973 #define CCM_CLOCK_GROUP_STATUS0_OFF_MASK         (0x1000000U)
20974 #define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT        (24U)
20975 /*! OFF - OFF
20976  *  0b0..Clock is running.
20977  *  0b1..Turn off clock.
20978  */
20979 #define CCM_CLOCK_GROUP_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK)
20980 
20981 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK   (0x8000000U)
20982 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT  (27U)
20983 /*! POWERDOWN - Current clock root POWERDOWN setting
20984  *  0b1..Clock root is Powered Down
20985  *  0b0..Clock root is running
20986  */
20987 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK)
20988 
20989 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK  (0x10000000U)
20990 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U)
20991 /*! SLICE_BUSY - Internal updating in generation logic
20992  *  0b1..Clock generation logic is applying the new setting
20993  *  0b0..Clock generation logic is not busy
20994  */
20995 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK)
20996 
20997 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
20998 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U)
20999 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
21000  *  0b1..Synchronization in process
21001  *  0b0..Synchronization not in process
21002  */
21003 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK)
21004 
21005 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
21006 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U)
21007 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
21008  *  0b1..Synchronization in process
21009  *  0b0..Synchronization not in process
21010  */
21011 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK)
21012 
21013 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK    (0x80000000U)
21014 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT   (31U)
21015 /*! CHANGING - Internal updating in clock group
21016  *  0b1..Clock root logic is updating currently
21017  *  0b0..Clock root is not updating currently
21018  */
21019 #define CCM_CLOCK_GROUP_STATUS0_CHANGING(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK)
21020 /*! @} */
21021 
21022 /* The count of CCM_CLOCK_GROUP_STATUS0 */
21023 #define CCM_CLOCK_GROUP_STATUS0_COUNT            (2U)
21024 
21025 /*! @name CLOCK_GROUP_STATUS1 - Clock group low power/extend status */
21026 /*! @{ */
21027 
21028 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
21029 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U)
21030 /*! TARGET_SETPOINT - Next Setpoint to change to
21031  */
21032 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK)
21033 
21034 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
21035 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
21036 /*! CURRENT_SETPOINT - Current Setpoint
21037  */
21038 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK)
21039 
21040 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
21041 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U)
21042 /*! DOWN_REQUEST - Clock frequency decrease request
21043  *  0b1..Handshake signal with GPC status indicating frequency decrease is requested
21044  *  0b0..No handshake signal is not requested
21045  */
21046 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK)
21047 
21048 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK   (0x2000000U)
21049 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT  (25U)
21050 /*! DOWN_DONE - Clock frequency decrease complete
21051  *  0b1..Handshake signal with GPC status indicating frequency decrease is complete
21052  *  0b0..Handshake signal with GPC status indicating frequency decrease is not complete
21053  */
21054 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK)
21055 
21056 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK  (0x4000000U)
21057 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U)
21058 /*! UP_REQUEST - Clock frequency increase request
21059  *  0b1..Handshake signal with GPC status indicating frequency increase is requested
21060  *  0b0..No handshake signal is not requested
21061  */
21062 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK)
21063 
21064 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK     (0x8000000U)
21065 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT    (27U)
21066 /*! UP_DONE - Clock frequency increase complete
21067  *  0b1..Handshake signal with GPC status indicating frequency increase is complete
21068  *  0b0..Handshake signal with GPC status indicating frequency increase is not complete
21069  */
21070 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK)
21071 /*! @} */
21072 
21073 /* The count of CCM_CLOCK_GROUP_STATUS1 */
21074 #define CCM_CLOCK_GROUP_STATUS1_COUNT            (2U)
21075 
21076 /*! @name CLOCK_GROUP_CONFIG - Clock group configuration */
21077 /*! @{ */
21078 
21079 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
21080 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
21081 /*! SETPOINT_PRESENT - Setpoint present
21082  *  0b1..Setpoint is implemented.
21083  *  0b0..Setpoint is not implemented.
21084  */
21085 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK)
21086 /*! @} */
21087 
21088 /* The count of CCM_CLOCK_GROUP_CONFIG */
21089 #define CCM_CLOCK_GROUP_CONFIG_COUNT             (2U)
21090 
21091 /*! @name CLOCK_GROUP_AUTHEN - Clock group access control */
21092 /*! @{ */
21093 
21094 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK      (0x1U)
21095 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT     (0U)
21096 /*! TZ_USER - User access
21097  *  0b1..Clock can be changed in user mode.
21098  *  0b0..Clock cannot be changed in user mode.
21099  */
21100 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK)
21101 
21102 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK        (0x2U)
21103 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT       (1U)
21104 /*! TZ_NS - Non-secure access
21105  *  0b0..Cannot be changed in Non-secure mode.
21106  *  0b1..Can be changed in Non-secure mode.
21107  */
21108 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK)
21109 
21110 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK      (0x10U)
21111 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT     (4U)
21112 /*! LOCK_TZ - Lock truszone setting
21113  *  0b0..Trustzone setting is not locked.
21114  *  0b1..Trustzone setting is locked.
21115  */
21116 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK)
21117 
21118 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK   (0xF00U)
21119 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT  (8U)
21120 /*! WHITE_LIST - Whitelist
21121  */
21122 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK)
21123 
21124 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK    (0x1000U)
21125 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT   (12U)
21126 /*! LOCK_LIST - Lock Whitelist
21127  *  0b0..Whitelist is not locked.
21128  *  0b1..Whitelist is locked.
21129  */
21130 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK)
21131 
21132 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
21133 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21134 /*! DOMAIN_MODE - Low power and access control by domain
21135  *  0b1..Clock works in Domain Mode.
21136  *  0b0..Clock does not work in Domain Mode.
21137  */
21138 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK)
21139 
21140 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
21141 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U)
21142 /*! SETPOINT_MODE - Low power and access control by Setpoint
21143  */
21144 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK)
21145 
21146 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK    (0x100000U)
21147 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT   (20U)
21148 /*! LOCK_MODE - Lock low power and access mode
21149  *  0b0..MODE is not locked.
21150  *  0b1..MODE is locked.
21151  */
21152 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK)
21153 /*! @} */
21154 
21155 /* The count of CCM_CLOCK_GROUP_AUTHEN */
21156 #define CCM_CLOCK_GROUP_AUTHEN_COUNT             (2U)
21157 
21158 /*! @name CLOCK_GROUP_AUTHEN_SET - Clock group access control */
21159 /*! @{ */
21160 
21161 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK  (0x1U)
21162 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U)
21163 /*! TZ_USER - User access
21164  */
21165 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK)
21166 
21167 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK    (0x2U)
21168 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT   (1U)
21169 /*! TZ_NS - Non-secure access
21170  */
21171 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK)
21172 
21173 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
21174 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21175 /*! LOCK_TZ - Lock truszone setting
21176  */
21177 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK)
21178 
21179 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21180 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21181 /*! WHITE_LIST - Whitelist
21182  */
21183 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK)
21184 
21185 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21186 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21187 /*! LOCK_LIST - Lock Whitelist
21188  */
21189 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK)
21190 
21191 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21192 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21193 /*! DOMAIN_MODE - Low power and access control by domain
21194  */
21195 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK)
21196 
21197 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
21198 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
21199 /*! SETPOINT_MODE - Low power and access control by Setpoint
21200  */
21201 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK)
21202 
21203 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21204 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21205 /*! LOCK_MODE - Lock low power and access mode
21206  */
21207 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK)
21208 /*! @} */
21209 
21210 /* The count of CCM_CLOCK_GROUP_AUTHEN_SET */
21211 #define CCM_CLOCK_GROUP_AUTHEN_SET_COUNT         (2U)
21212 
21213 /*! @name CLOCK_GROUP_AUTHEN_CLR - Clock group access control */
21214 /*! @{ */
21215 
21216 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
21217 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21218 /*! TZ_USER - User access
21219  */
21220 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK)
21221 
21222 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
21223 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
21224 /*! TZ_NS - Non-secure access
21225  */
21226 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK)
21227 
21228 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
21229 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21230 /*! LOCK_TZ - Lock truszone setting
21231  */
21232 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK)
21233 
21234 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21235 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21236 /*! WHITE_LIST - Whitelist
21237  */
21238 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK)
21239 
21240 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21241 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21242 /*! LOCK_LIST - Lock Whitelist
21243  */
21244 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK)
21245 
21246 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21247 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21248 /*! DOMAIN_MODE - Low power and access control by domain
21249  */
21250 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK)
21251 
21252 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21253 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21254 /*! SETPOINT_MODE - Low power and access control by Setpoint
21255  */
21256 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK)
21257 
21258 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21259 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21260 /*! LOCK_MODE - Lock low power and access mode
21261  */
21262 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK)
21263 /*! @} */
21264 
21265 /* The count of CCM_CLOCK_GROUP_AUTHEN_CLR */
21266 #define CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT         (2U)
21267 
21268 /*! @name CLOCK_GROUP_AUTHEN_TOG - Clock group access control */
21269 /*! @{ */
21270 
21271 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
21272 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21273 /*! TZ_USER - User access
21274  */
21275 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK)
21276 
21277 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
21278 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
21279 /*! TZ_NS - Non-secure access
21280  */
21281 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK)
21282 
21283 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
21284 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21285 /*! LOCK_TZ - Lock truszone setting
21286  */
21287 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK)
21288 
21289 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21290 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21291 /*! WHITE_LIST - Whitelist
21292  */
21293 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK)
21294 
21295 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21296 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21297 /*! LOCK_LIST - Lock Whitelist
21298  */
21299 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK)
21300 
21301 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21302 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21303 /*! DOMAIN_MODE - Low power and access control by domain
21304  */
21305 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK)
21306 
21307 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21308 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21309 /*! SETPOINT_MODE - Low power and access control by Setpoint
21310  */
21311 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK)
21312 
21313 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21314 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21315 /*! LOCK_MODE - Lock low power and access mode
21316  */
21317 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK)
21318 /*! @} */
21319 
21320 /* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */
21321 #define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT         (2U)
21322 
21323 /*! @name CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting */
21324 /*! @{ */
21325 
21326 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU)
21327 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U)
21328 /*! DIV0 - Clock divider
21329  *  0b0000..Direct output.
21330  *  0b0001..Divide by 2.
21331  *  0b0010..Divide by 3.
21332  *  0b0011..Divide by 4.
21333  *  0b1111..Divide by 16.
21334  */
21335 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK)
21336 
21337 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U)
21338 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U)
21339 /*! RSTDIV - Clock group global restart count
21340  */
21341 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK)
21342 
21343 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21344 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21345 /*! OFF - OFF
21346  *  0b0..Clock is running.
21347  *  0b1..Turn off clock.
21348  */
21349 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK)
21350 
21351 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21352 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21353 /*! GRADE - Grade
21354  */
21355 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK)
21356 /*! @} */
21357 
21358 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21359 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U)
21360 
21361 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21362 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U)
21363 
21364 /*! @name GPR_SHARED - General Purpose Register */
21365 /*! @{ */
21366 
21367 #define CCM_GPR_SHARED_GPR_MASK                  (0xFFFFFFFFU)
21368 #define CCM_GPR_SHARED_GPR_SHIFT                 (0U)
21369 /*! GPR - GP register
21370  */
21371 #define CCM_GPR_SHARED_GPR(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK)
21372 /*! @} */
21373 
21374 /* The count of CCM_GPR_SHARED */
21375 #define CCM_GPR_SHARED_COUNT                     (8U)
21376 
21377 /*! @name GPR_SHARED_SET - General Purpose Register */
21378 /*! @{ */
21379 
21380 #define CCM_GPR_SHARED_SET_GPR_MASK              (0xFFFFFFFFU)
21381 #define CCM_GPR_SHARED_SET_GPR_SHIFT             (0U)
21382 /*! GPR - GP register
21383  */
21384 #define CCM_GPR_SHARED_SET_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK)
21385 /*! @} */
21386 
21387 /* The count of CCM_GPR_SHARED_SET */
21388 #define CCM_GPR_SHARED_SET_COUNT                 (8U)
21389 
21390 /*! @name GPR_SHARED_CLR - General Purpose Register */
21391 /*! @{ */
21392 
21393 #define CCM_GPR_SHARED_CLR_GPR_MASK              (0xFFFFFFFFU)
21394 #define CCM_GPR_SHARED_CLR_GPR_SHIFT             (0U)
21395 /*! GPR - GP register
21396  */
21397 #define CCM_GPR_SHARED_CLR_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK)
21398 /*! @} */
21399 
21400 /* The count of CCM_GPR_SHARED_CLR */
21401 #define CCM_GPR_SHARED_CLR_COUNT                 (8U)
21402 
21403 /*! @name GPR_SHARED_TOG - General Purpose Register */
21404 /*! @{ */
21405 
21406 #define CCM_GPR_SHARED_TOG_GPR_MASK              (0xFFFFFFFFU)
21407 #define CCM_GPR_SHARED_TOG_GPR_SHIFT             (0U)
21408 /*! GPR - GP register
21409  */
21410 #define CCM_GPR_SHARED_TOG_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK)
21411 /*! @} */
21412 
21413 /* The count of CCM_GPR_SHARED_TOG */
21414 #define CCM_GPR_SHARED_TOG_COUNT                 (8U)
21415 
21416 /*! @name GPR_SHARED_AUTHEN - GPR access control */
21417 /*! @{ */
21418 
21419 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK       (0x1U)
21420 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT      (0U)
21421 /*! TZ_USER - User access
21422  *  0b1..Clock can be changed in user mode.
21423  *  0b0..Clock cannot be changed in user mode.
21424  */
21425 #define CCM_GPR_SHARED_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK)
21426 
21427 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK         (0x2U)
21428 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT        (1U)
21429 /*! TZ_NS - Non-secure access
21430  *  0b0..Cannot be changed in Non-secure mode.
21431  *  0b1..Can be changed in Non-secure mode.
21432  */
21433 #define CCM_GPR_SHARED_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK)
21434 
21435 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK       (0x10U)
21436 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT      (4U)
21437 /*! LOCK_TZ - Lock truszone setting
21438  *  0b0..Trustzone setting is not locked.
21439  *  0b1..Trustzone setting is locked.
21440  */
21441 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK)
21442 
21443 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK    (0xF00U)
21444 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT   (8U)
21445 /*! WHITE_LIST - Whitelist
21446  *  0b0000..This domain is NOT allowed to change clock.
21447  *  0b0001..This domain is allowed to change clock.
21448  */
21449 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK)
21450 
21451 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK     (0x1000U)
21452 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT    (12U)
21453 /*! LOCK_LIST - Lock Whitelist
21454  *  0b0..Whitelist is not locked.
21455  *  0b1..Whitelist is locked.
21456  */
21457 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK)
21458 
21459 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
21460 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
21461 /*! DOMAIN_MODE - Low power and access control by domain
21462  *  0b1..Clock works in Domain Mode.
21463  *  0b0..Clock does NOT work in Domain Mode.
21464  */
21465 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK)
21466 
21467 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK     (0x100000U)
21468 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT    (20U)
21469 /*! LOCK_MODE - Lock low power and access mode
21470  *  0b0..MODE is not locked.
21471  *  0b1..MODE is locked.
21472  */
21473 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK)
21474 /*! @} */
21475 
21476 /* The count of CCM_GPR_SHARED_AUTHEN */
21477 #define CCM_GPR_SHARED_AUTHEN_COUNT              (8U)
21478 
21479 /*! @name GPR_SHARED_AUTHEN_SET - GPR access control */
21480 /*! @{ */
21481 
21482 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK   (0x1U)
21483 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT  (0U)
21484 /*! TZ_USER - User access
21485  */
21486 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK)
21487 
21488 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK     (0x2U)
21489 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT    (1U)
21490 /*! TZ_NS - Non-secure access
21491  */
21492 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK)
21493 
21494 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
21495 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
21496 /*! LOCK_TZ - Lock truszone setting
21497  */
21498 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK)
21499 
21500 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21501 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21502 /*! WHITE_LIST - Whitelist
21503  */
21504 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK)
21505 
21506 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21507 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21508 /*! LOCK_LIST - Lock Whitelist
21509  */
21510 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK)
21511 
21512 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21513 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21514 /*! DOMAIN_MODE - Low power and access control by domain
21515  */
21516 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK)
21517 
21518 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21519 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21520 /*! LOCK_MODE - Lock low power and access mode
21521  */
21522 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK)
21523 /*! @} */
21524 
21525 /* The count of CCM_GPR_SHARED_AUTHEN_SET */
21526 #define CCM_GPR_SHARED_AUTHEN_SET_COUNT          (8U)
21527 
21528 /*! @name GPR_SHARED_AUTHEN_CLR - GPR access control */
21529 /*! @{ */
21530 
21531 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
21532 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
21533 /*! TZ_USER - User access
21534  */
21535 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK)
21536 
21537 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
21538 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
21539 /*! TZ_NS - Non-secure access
21540  */
21541 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK)
21542 
21543 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
21544 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
21545 /*! LOCK_TZ - Lock truszone setting
21546  */
21547 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK)
21548 
21549 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21550 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21551 /*! WHITE_LIST - Whitelist
21552  */
21553 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK)
21554 
21555 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21556 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21557 /*! LOCK_LIST - Lock Whitelist
21558  */
21559 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK)
21560 
21561 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21562 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21563 /*! DOMAIN_MODE - Low power and access control by domain
21564  */
21565 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK)
21566 
21567 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21568 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21569 /*! LOCK_MODE - Lock low power and access mode
21570  */
21571 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK)
21572 /*! @} */
21573 
21574 /* The count of CCM_GPR_SHARED_AUTHEN_CLR */
21575 #define CCM_GPR_SHARED_AUTHEN_CLR_COUNT          (8U)
21576 
21577 /*! @name GPR_SHARED_AUTHEN_TOG - GPR access control */
21578 /*! @{ */
21579 
21580 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
21581 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
21582 /*! TZ_USER - User access
21583  */
21584 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK)
21585 
21586 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
21587 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
21588 /*! TZ_NS - Non-secure access
21589  */
21590 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK)
21591 
21592 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
21593 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
21594 /*! LOCK_TZ - Lock truszone setting
21595  */
21596 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK)
21597 
21598 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21599 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21600 /*! WHITE_LIST - Whitelist
21601  */
21602 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK)
21603 
21604 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21605 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21606 /*! LOCK_LIST - Lock Whitelist
21607  */
21608 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK)
21609 
21610 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21611 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21612 /*! DOMAIN_MODE - Low power and access control by domain
21613  */
21614 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK)
21615 
21616 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21617 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21618 /*! LOCK_MODE - Lock low power and access mode
21619  */
21620 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK)
21621 /*! @} */
21622 
21623 /* The count of CCM_GPR_SHARED_AUTHEN_TOG */
21624 #define CCM_GPR_SHARED_AUTHEN_TOG_COUNT          (8U)
21625 
21626 /*! @name GPR_PRIVATE1 - General Purpose Register */
21627 /*! @{ */
21628 
21629 #define CCM_GPR_PRIVATE1_GPR_MASK                (0xFFFFFFFFU)
21630 #define CCM_GPR_PRIVATE1_GPR_SHIFT               (0U)
21631 /*! GPR - GP register
21632  */
21633 #define CCM_GPR_PRIVATE1_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK)
21634 /*! @} */
21635 
21636 /*! @name GPR_PRIVATE1_SET - General Purpose Register */
21637 /*! @{ */
21638 
21639 #define CCM_GPR_PRIVATE1_SET_GPR_MASK            (0xFFFFFFFFU)
21640 #define CCM_GPR_PRIVATE1_SET_GPR_SHIFT           (0U)
21641 /*! GPR - GP register
21642  */
21643 #define CCM_GPR_PRIVATE1_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK)
21644 /*! @} */
21645 
21646 /*! @name GPR_PRIVATE1_CLR - General Purpose Register */
21647 /*! @{ */
21648 
21649 #define CCM_GPR_PRIVATE1_CLR_GPR_MASK            (0xFFFFFFFFU)
21650 #define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT           (0U)
21651 /*! GPR - GP register
21652  */
21653 #define CCM_GPR_PRIVATE1_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK)
21654 /*! @} */
21655 
21656 /*! @name GPR_PRIVATE1_TOG - General Purpose Register */
21657 /*! @{ */
21658 
21659 #define CCM_GPR_PRIVATE1_TOG_GPR_MASK            (0xFFFFFFFFU)
21660 #define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT           (0U)
21661 /*! GPR - GP register
21662  */
21663 #define CCM_GPR_PRIVATE1_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK)
21664 /*! @} */
21665 
21666 /*! @name GPR_PRIVATE1_AUTHEN - GPR access control */
21667 /*! @{ */
21668 
21669 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK     (0x1U)
21670 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT    (0U)
21671 /*! TZ_USER - User access
21672  *  0b1..Clock can be changed in user mode.
21673  *  0b0..Clock cannot be changed in user mode.
21674  */
21675 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK)
21676 
21677 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK       (0x2U)
21678 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT      (1U)
21679 /*! TZ_NS - Non-secure access
21680  *  0b0..Cannot be changed in Non-secure mode.
21681  *  0b1..Can be changed in Non-secure mode.
21682  */
21683 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK)
21684 
21685 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK     (0x10U)
21686 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT    (4U)
21687 /*! LOCK_TZ - Lock truszone setting
21688  *  0b0..Trustzone setting is not locked.
21689  *  0b1..Trustzone setting is locked.
21690  */
21691 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK)
21692 
21693 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK  (0xF00U)
21694 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U)
21695 /*! WHITE_LIST - Whitelist
21696  *  0b0000..This domain is NOT allowed to change clock.
21697  *  0b0001..This domain is allowed to change clock.
21698  */
21699 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK)
21700 
21701 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK   (0x1000U)
21702 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT  (12U)
21703 /*! LOCK_LIST - Lock Whitelist
21704  *  0b0..Whitelist is not locked.
21705  *  0b1..Whitelist is locked.
21706  */
21707 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK)
21708 
21709 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21710 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21711 /*! DOMAIN_MODE - Low power and access control by Domain
21712  *  0b1..Clock works in Domain Mode.
21713  *  0b0..Clock does NOT work in Domain Mode.
21714  */
21715 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK)
21716 
21717 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK   (0x100000U)
21718 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT  (20U)
21719 /*! LOCK_MODE - Lock low power and access mode
21720  *  0b0..MODE is not locked.
21721  *  0b1..MODE is locked.
21722  */
21723 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK)
21724 /*! @} */
21725 
21726 /*! @name GPR_PRIVATE1_AUTHEN_SET - GPR access control */
21727 /*! @{ */
21728 
21729 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U)
21730 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U)
21731 /*! TZ_USER - User access
21732  */
21733 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK)
21734 
21735 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK   (0x2U)
21736 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT  (1U)
21737 /*! TZ_NS - Non-secure access
21738  */
21739 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK)
21740 
21741 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21742 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21743 /*! LOCK_TZ - Lock truszone setting
21744  */
21745 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK)
21746 
21747 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21748 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21749 /*! WHITE_LIST - Whitelist
21750  */
21751 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK)
21752 
21753 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21754 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21755 /*! LOCK_LIST - Lock Whitelist
21756  */
21757 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK)
21758 
21759 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21760 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21761 /*! DOMAIN_MODE - Low power and access control by Domain
21762  */
21763 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK)
21764 
21765 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21766 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21767 /*! LOCK_MODE - Lock low power and access mode
21768  */
21769 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK)
21770 /*! @} */
21771 
21772 /*! @name GPR_PRIVATE1_AUTHEN_CLR - GPR access control */
21773 /*! @{ */
21774 
21775 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U)
21776 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21777 /*! TZ_USER - User access
21778  */
21779 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK)
21780 
21781 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
21782 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
21783 /*! TZ_NS - Non-secure access
21784  */
21785 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK)
21786 
21787 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
21788 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21789 /*! LOCK_TZ - Lock truszone setting
21790  */
21791 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK)
21792 
21793 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21794 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21795 /*! WHITE_LIST - Whitelist
21796  */
21797 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK)
21798 
21799 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21800 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21801 /*! LOCK_LIST - Lock Whitelist
21802  */
21803 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK)
21804 
21805 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21806 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21807 /*! DOMAIN_MODE - Low power and access control by Domain
21808  */
21809 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK)
21810 
21811 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21812 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21813 /*! LOCK_MODE - Lock low power and access mode
21814  */
21815 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK)
21816 /*! @} */
21817 
21818 /*! @name GPR_PRIVATE1_AUTHEN_TOG - GPR access control */
21819 /*! @{ */
21820 
21821 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U)
21822 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21823 /*! TZ_USER - User access
21824  */
21825 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK)
21826 
21827 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
21828 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
21829 /*! TZ_NS - Non-secure access
21830  */
21831 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK)
21832 
21833 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
21834 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21835 /*! LOCK_TZ - Lock truszone setting
21836  */
21837 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK)
21838 
21839 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21840 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21841 /*! WHITE_LIST - Whitelist
21842  */
21843 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK)
21844 
21845 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21846 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21847 /*! LOCK_LIST - Lock Whitelist
21848  */
21849 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK)
21850 
21851 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21852 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21853 /*! DOMAIN_MODE - Low power and access control by Domain
21854  */
21855 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK)
21856 
21857 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21858 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21859 /*! LOCK_MODE - Lock low power and access mode
21860  */
21861 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK)
21862 /*! @} */
21863 
21864 /*! @name GPR_PRIVATE2 - General Purpose Register */
21865 /*! @{ */
21866 
21867 #define CCM_GPR_PRIVATE2_GPR_MASK                (0xFFFFFFFFU)
21868 #define CCM_GPR_PRIVATE2_GPR_SHIFT               (0U)
21869 /*! GPR - GP register
21870  */
21871 #define CCM_GPR_PRIVATE2_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK)
21872 /*! @} */
21873 
21874 /*! @name GPR_PRIVATE2_SET - General Purpose Register */
21875 /*! @{ */
21876 
21877 #define CCM_GPR_PRIVATE2_SET_GPR_MASK            (0xFFFFFFFFU)
21878 #define CCM_GPR_PRIVATE2_SET_GPR_SHIFT           (0U)
21879 /*! GPR - GP register
21880  */
21881 #define CCM_GPR_PRIVATE2_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK)
21882 /*! @} */
21883 
21884 /*! @name GPR_PRIVATE2_CLR - General Purpose Register */
21885 /*! @{ */
21886 
21887 #define CCM_GPR_PRIVATE2_CLR_GPR_MASK            (0xFFFFFFFFU)
21888 #define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT           (0U)
21889 /*! GPR - GP register
21890  */
21891 #define CCM_GPR_PRIVATE2_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK)
21892 /*! @} */
21893 
21894 /*! @name GPR_PRIVATE2_TOG - General Purpose Register */
21895 /*! @{ */
21896 
21897 #define CCM_GPR_PRIVATE2_TOG_GPR_MASK            (0xFFFFFFFFU)
21898 #define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT           (0U)
21899 /*! GPR - GP register
21900  */
21901 #define CCM_GPR_PRIVATE2_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK)
21902 /*! @} */
21903 
21904 /*! @name GPR_PRIVATE2_AUTHEN - GPR access control */
21905 /*! @{ */
21906 
21907 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK     (0x1U)
21908 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT    (0U)
21909 /*! TZ_USER - User access
21910  *  0b1..Clock can be changed in user mode.
21911  *  0b0..Clock cannot be changed in user mode.
21912  */
21913 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK)
21914 
21915 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK       (0x2U)
21916 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT      (1U)
21917 /*! TZ_NS - Non-secure access
21918  *  0b0..Cannot be changed in Non-secure mode.
21919  *  0b1..Can be changed in Non-secure mode.
21920  */
21921 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK)
21922 
21923 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK     (0x10U)
21924 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT    (4U)
21925 /*! LOCK_TZ - Lock truszone setting
21926  *  0b0..Trustzone setting is not locked.
21927  *  0b1..Trustzone setting is locked.
21928  */
21929 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK)
21930 
21931 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK  (0xF00U)
21932 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U)
21933 /*! WHITE_LIST - Whitelist
21934  *  0b0000..This domain is NOT allowed to change clock.
21935  *  0b0001..This domain is allowed to change clock.
21936  */
21937 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK)
21938 
21939 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK   (0x1000U)
21940 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT  (12U)
21941 /*! LOCK_LIST - Lock Whitelist
21942  *  0b0..Whitelist is not locked.
21943  *  0b1..Whitelist is locked.
21944  */
21945 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK)
21946 
21947 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21948 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21949 /*! DOMAIN_MODE - Low power and access control by Domain
21950  *  0b1..Clock works in Domain Mode.
21951  *  0b0..Clock does NOT work in Domain Mode.
21952  */
21953 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK)
21954 
21955 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK   (0x100000U)
21956 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT  (20U)
21957 /*! LOCK_MODE - Lock low power and access mode
21958  *  0b0..MODE is not locked.
21959  *  0b1..MODE is locked.
21960  */
21961 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK)
21962 /*! @} */
21963 
21964 /*! @name GPR_PRIVATE2_AUTHEN_SET - GPR access control */
21965 /*! @{ */
21966 
21967 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U)
21968 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U)
21969 /*! TZ_USER - User access
21970  */
21971 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK)
21972 
21973 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK   (0x2U)
21974 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT  (1U)
21975 /*! TZ_NS - Non-secure access
21976  */
21977 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK)
21978 
21979 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21980 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21981 /*! LOCK_TZ - Lock truszone setting
21982  */
21983 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK)
21984 
21985 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21986 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21987 /*! WHITE_LIST - Whitelist
21988  */
21989 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK)
21990 
21991 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21992 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21993 /*! LOCK_LIST - Lock Whitelist
21994  */
21995 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK)
21996 
21997 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21998 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21999 /*! DOMAIN_MODE - Low power and access control by Domain
22000  */
22001 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK)
22002 
22003 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22004 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22005 /*! LOCK_MODE - Lock low power and access mode
22006  */
22007 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK)
22008 /*! @} */
22009 
22010 /*! @name GPR_PRIVATE2_AUTHEN_CLR - GPR access control */
22011 /*! @{ */
22012 
22013 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22014 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22015 /*! TZ_USER - User access
22016  */
22017 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK)
22018 
22019 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22020 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22021 /*! TZ_NS - Non-secure access
22022  */
22023 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK)
22024 
22025 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22026 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22027 /*! LOCK_TZ - Lock truszone setting
22028  */
22029 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK)
22030 
22031 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22032 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22033 /*! WHITE_LIST - Whitelist
22034  */
22035 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK)
22036 
22037 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22038 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22039 /*! LOCK_LIST - Lock Whitelist
22040  */
22041 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK)
22042 
22043 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22044 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22045 /*! DOMAIN_MODE - Low power and access control by Domain
22046  */
22047 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK)
22048 
22049 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22050 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22051 /*! LOCK_MODE - Lock low power and access mode
22052  */
22053 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK)
22054 /*! @} */
22055 
22056 /*! @name GPR_PRIVATE2_AUTHEN_TOG - GPR access control */
22057 /*! @{ */
22058 
22059 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22060 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22061 /*! TZ_USER - User access
22062  */
22063 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK)
22064 
22065 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22066 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22067 /*! TZ_NS - Non-secure access
22068  */
22069 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK)
22070 
22071 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22072 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22073 /*! LOCK_TZ - Lock truszone setting
22074  */
22075 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK)
22076 
22077 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22078 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22079 /*! WHITE_LIST - Whitelist
22080  */
22081 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK)
22082 
22083 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22084 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22085 /*! LOCK_LIST - Lock Whitelist
22086  */
22087 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK)
22088 
22089 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22090 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22091 /*! DOMAIN_MODE - Low power and access control by Domain
22092  */
22093 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK)
22094 
22095 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22096 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22097 /*! LOCK_MODE - Lock low power and access mode
22098  */
22099 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK)
22100 /*! @} */
22101 
22102 /*! @name GPR_PRIVATE3 - General Purpose Register */
22103 /*! @{ */
22104 
22105 #define CCM_GPR_PRIVATE3_GPR_MASK                (0xFFFFFFFFU)
22106 #define CCM_GPR_PRIVATE3_GPR_SHIFT               (0U)
22107 /*! GPR - GP register
22108  */
22109 #define CCM_GPR_PRIVATE3_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK)
22110 /*! @} */
22111 
22112 /*! @name GPR_PRIVATE3_SET - General Purpose Register */
22113 /*! @{ */
22114 
22115 #define CCM_GPR_PRIVATE3_SET_GPR_MASK            (0xFFFFFFFFU)
22116 #define CCM_GPR_PRIVATE3_SET_GPR_SHIFT           (0U)
22117 /*! GPR - GP register
22118  */
22119 #define CCM_GPR_PRIVATE3_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK)
22120 /*! @} */
22121 
22122 /*! @name GPR_PRIVATE3_CLR - General Purpose Register */
22123 /*! @{ */
22124 
22125 #define CCM_GPR_PRIVATE3_CLR_GPR_MASK            (0xFFFFFFFFU)
22126 #define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT           (0U)
22127 /*! GPR - GP register
22128  */
22129 #define CCM_GPR_PRIVATE3_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK)
22130 /*! @} */
22131 
22132 /*! @name GPR_PRIVATE3_TOG - General Purpose Register */
22133 /*! @{ */
22134 
22135 #define CCM_GPR_PRIVATE3_TOG_GPR_MASK            (0xFFFFFFFFU)
22136 #define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT           (0U)
22137 /*! GPR - GP register
22138  */
22139 #define CCM_GPR_PRIVATE3_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK)
22140 /*! @} */
22141 
22142 /*! @name GPR_PRIVATE3_AUTHEN - GPR access control */
22143 /*! @{ */
22144 
22145 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK     (0x1U)
22146 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT    (0U)
22147 /*! TZ_USER - User access
22148  *  0b1..Clock can be changed in user mode.
22149  *  0b0..Clock cannot be changed in user mode.
22150  */
22151 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK)
22152 
22153 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK       (0x2U)
22154 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT      (1U)
22155 /*! TZ_NS - Non-secure access
22156  *  0b0..Cannot be changed in Non-secure mode.
22157  *  0b1..Can be changed in Non-secure mode.
22158  */
22159 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK)
22160 
22161 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK     (0x10U)
22162 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT    (4U)
22163 /*! LOCK_TZ - Lock truszone setting
22164  *  0b0..Trustzone setting is not locked.
22165  *  0b1..Trustzone setting is locked.
22166  */
22167 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK)
22168 
22169 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22170 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U)
22171 /*! WHITE_LIST - Whitelist
22172  *  0b0000..This domain is NOT allowed to change clock.
22173  *  0b0001..This domain is allowed to change clock.
22174  */
22175 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK)
22176 
22177 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22178 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT  (12U)
22179 /*! LOCK_LIST - Lock Whitelist
22180  *  0b0..Whitelist is not locked.
22181  *  0b1..Whitelist is locked.
22182  */
22183 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK)
22184 
22185 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22186 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22187 /*! DOMAIN_MODE - Low power and access control by Domain
22188  *  0b1..Clock works in Domain Mode.
22189  *  0b0..Clock does NOT work in Domain Mode.
22190  */
22191 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK)
22192 
22193 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22194 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT  (20U)
22195 /*! LOCK_MODE - Lock low power and access mode
22196  *  0b0..MODE is not locked.
22197  *  0b1..MODE is locked.
22198  */
22199 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK)
22200 /*! @} */
22201 
22202 /*! @name GPR_PRIVATE3_AUTHEN_SET - GPR access control */
22203 /*! @{ */
22204 
22205 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U)
22206 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U)
22207 /*! TZ_USER - User access
22208  */
22209 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK)
22210 
22211 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22212 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22213 /*! TZ_NS - Non-secure access
22214  */
22215 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK)
22216 
22217 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22218 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22219 /*! LOCK_TZ - Lock truszone setting
22220  */
22221 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK)
22222 
22223 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22224 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22225 /*! WHITE_LIST - Whitelist
22226  */
22227 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK)
22228 
22229 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22230 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22231 /*! LOCK_LIST - Lock Whitelist
22232  */
22233 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK)
22234 
22235 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22236 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22237 /*! DOMAIN_MODE - Low power and access control by Domain
22238  */
22239 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK)
22240 
22241 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22242 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22243 /*! LOCK_MODE - Lock low power and access mode
22244  */
22245 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK)
22246 /*! @} */
22247 
22248 /*! @name GPR_PRIVATE3_AUTHEN_CLR - GPR access control */
22249 /*! @{ */
22250 
22251 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22252 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22253 /*! TZ_USER - User access
22254  */
22255 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK)
22256 
22257 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22258 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22259 /*! TZ_NS - Non-secure access
22260  */
22261 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK)
22262 
22263 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22264 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22265 /*! LOCK_TZ - Lock truszone setting
22266  */
22267 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK)
22268 
22269 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22270 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22271 /*! WHITE_LIST - Whitelist
22272  */
22273 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK)
22274 
22275 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22276 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22277 /*! LOCK_LIST - Lock Whitelist
22278  */
22279 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK)
22280 
22281 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22282 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22283 /*! DOMAIN_MODE - Low power and access control by Domain
22284  */
22285 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK)
22286 
22287 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22288 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22289 /*! LOCK_MODE - Lock low power and access mode
22290  */
22291 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK)
22292 /*! @} */
22293 
22294 /*! @name GPR_PRIVATE3_AUTHEN_TOG - GPR access control */
22295 /*! @{ */
22296 
22297 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22298 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22299 /*! TZ_USER - User access
22300  */
22301 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK)
22302 
22303 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22304 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22305 /*! TZ_NS - Non-secure access
22306  */
22307 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK)
22308 
22309 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22310 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22311 /*! LOCK_TZ - Lock truszone setting
22312  */
22313 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK)
22314 
22315 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22316 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22317 /*! WHITE_LIST - Whitelist
22318  */
22319 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK)
22320 
22321 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22322 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22323 /*! LOCK_LIST - Lock Whitelist
22324  */
22325 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK)
22326 
22327 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22328 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22329 /*! DOMAIN_MODE - Low power and access control by Domain
22330  */
22331 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK)
22332 
22333 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22334 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22335 /*! LOCK_MODE - Lock low power and access mode
22336  */
22337 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK)
22338 /*! @} */
22339 
22340 /*! @name GPR_PRIVATE4 - General Purpose Register */
22341 /*! @{ */
22342 
22343 #define CCM_GPR_PRIVATE4_GPR_MASK                (0xFFFFFFFFU)
22344 #define CCM_GPR_PRIVATE4_GPR_SHIFT               (0U)
22345 /*! GPR - GP register
22346  */
22347 #define CCM_GPR_PRIVATE4_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK)
22348 /*! @} */
22349 
22350 /*! @name GPR_PRIVATE4_SET - General Purpose Register */
22351 /*! @{ */
22352 
22353 #define CCM_GPR_PRIVATE4_SET_GPR_MASK            (0xFFFFFFFFU)
22354 #define CCM_GPR_PRIVATE4_SET_GPR_SHIFT           (0U)
22355 /*! GPR - GP register
22356  */
22357 #define CCM_GPR_PRIVATE4_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK)
22358 /*! @} */
22359 
22360 /*! @name GPR_PRIVATE4_CLR - General Purpose Register */
22361 /*! @{ */
22362 
22363 #define CCM_GPR_PRIVATE4_CLR_GPR_MASK            (0xFFFFFFFFU)
22364 #define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT           (0U)
22365 /*! GPR - GP register
22366  */
22367 #define CCM_GPR_PRIVATE4_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK)
22368 /*! @} */
22369 
22370 /*! @name GPR_PRIVATE4_TOG - General Purpose Register */
22371 /*! @{ */
22372 
22373 #define CCM_GPR_PRIVATE4_TOG_GPR_MASK            (0xFFFFFFFFU)
22374 #define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT           (0U)
22375 /*! GPR - GP register
22376  */
22377 #define CCM_GPR_PRIVATE4_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK)
22378 /*! @} */
22379 
22380 /*! @name GPR_PRIVATE4_AUTHEN - GPR access control */
22381 /*! @{ */
22382 
22383 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK     (0x1U)
22384 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT    (0U)
22385 /*! TZ_USER - User access
22386  *  0b1..Clock can be changed in user mode.
22387  *  0b0..Clock cannot be changed in user mode.
22388  */
22389 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK)
22390 
22391 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK       (0x2U)
22392 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT      (1U)
22393 /*! TZ_NS - Non-secure access
22394  *  0b0..Cannot be changed in Non-secure mode.
22395  *  0b1..Can be changed in Non-secure mode.
22396  */
22397 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK)
22398 
22399 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK     (0x10U)
22400 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT    (4U)
22401 /*! LOCK_TZ - Lock truszone setting
22402  *  0b0..Trustzone setting is not locked.
22403  *  0b1..Trustzone setting is locked.
22404  */
22405 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK)
22406 
22407 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22408 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U)
22409 /*! WHITE_LIST - Whitelist
22410  *  0b0000..This domain is NOT allowed to change clock.
22411  *  0b0001..This domain is allowed to change clock.
22412  */
22413 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK)
22414 
22415 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22416 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT  (12U)
22417 /*! LOCK_LIST - Lock Whitelist
22418  *  0b0..Whitelist is not locked.
22419  *  0b1..Whitelist is locked.
22420  */
22421 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK)
22422 
22423 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22424 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22425 /*! DOMAIN_MODE - Low power and access control by Domain
22426  *  0b1..Clock works in Domain Mode.
22427  *  0b0..Clock does NOT work in Domain Mode.
22428  */
22429 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK)
22430 
22431 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22432 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT  (20U)
22433 /*! LOCK_MODE - Lock low power and access mode
22434  *  0b0..MODE is not locked.
22435  *  0b1..MODE is locked.
22436  */
22437 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK)
22438 /*! @} */
22439 
22440 /*! @name GPR_PRIVATE4_AUTHEN_SET - GPR access control */
22441 /*! @{ */
22442 
22443 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U)
22444 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U)
22445 /*! TZ_USER - User access
22446  */
22447 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK)
22448 
22449 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22450 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22451 /*! TZ_NS - Non-secure access
22452  */
22453 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK)
22454 
22455 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22456 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22457 /*! LOCK_TZ - Lock truszone setting
22458  */
22459 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK)
22460 
22461 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22462 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22463 /*! WHITE_LIST - Whitelist
22464  */
22465 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK)
22466 
22467 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22468 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22469 /*! LOCK_LIST - Lock Whitelist
22470  */
22471 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK)
22472 
22473 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22474 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22475 /*! DOMAIN_MODE - Low power and access control by Domain
22476  */
22477 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK)
22478 
22479 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22480 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22481 /*! LOCK_MODE - Lock low power and access mode
22482  */
22483 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK)
22484 /*! @} */
22485 
22486 /*! @name GPR_PRIVATE4_AUTHEN_CLR - GPR access control */
22487 /*! @{ */
22488 
22489 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22490 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22491 /*! TZ_USER - User access
22492  */
22493 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK)
22494 
22495 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22496 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22497 /*! TZ_NS - Non-secure access
22498  */
22499 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK)
22500 
22501 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22502 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22503 /*! LOCK_TZ - Lock truszone setting
22504  */
22505 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK)
22506 
22507 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22508 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22509 /*! WHITE_LIST - Whitelist
22510  */
22511 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK)
22512 
22513 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22514 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22515 /*! LOCK_LIST - Lock Whitelist
22516  */
22517 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK)
22518 
22519 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22520 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22521 /*! DOMAIN_MODE - Low power and access control by Domain
22522  */
22523 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK)
22524 
22525 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22526 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22527 /*! LOCK_MODE - Lock low power and access mode
22528  */
22529 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK)
22530 /*! @} */
22531 
22532 /*! @name GPR_PRIVATE4_AUTHEN_TOG - GPR access control */
22533 /*! @{ */
22534 
22535 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22536 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22537 /*! TZ_USER - User access
22538  */
22539 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK)
22540 
22541 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22542 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22543 /*! TZ_NS - Non-secure access
22544  */
22545 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK)
22546 
22547 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22548 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22549 /*! LOCK_TZ - Lock truszone setting
22550  */
22551 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK)
22552 
22553 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22554 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22555 /*! WHITE_LIST - Whitelist
22556  */
22557 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK)
22558 
22559 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22560 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22561 /*! LOCK_LIST - Lock Whitelist
22562  */
22563 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK)
22564 
22565 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22566 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22567 /*! DOMAIN_MODE - Low power and access control by Domain
22568  */
22569 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK)
22570 
22571 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22572 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22573 /*! LOCK_MODE - Lock low power and access mode
22574  */
22575 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK)
22576 /*! @} */
22577 
22578 /*! @name GPR_PRIVATE5 - General Purpose Register */
22579 /*! @{ */
22580 
22581 #define CCM_GPR_PRIVATE5_GPR_MASK                (0xFFFFFFFFU)
22582 #define CCM_GPR_PRIVATE5_GPR_SHIFT               (0U)
22583 /*! GPR - GP register
22584  */
22585 #define CCM_GPR_PRIVATE5_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK)
22586 /*! @} */
22587 
22588 /*! @name GPR_PRIVATE5_SET - General Purpose Register */
22589 /*! @{ */
22590 
22591 #define CCM_GPR_PRIVATE5_SET_GPR_MASK            (0xFFFFFFFFU)
22592 #define CCM_GPR_PRIVATE5_SET_GPR_SHIFT           (0U)
22593 /*! GPR - GP register
22594  */
22595 #define CCM_GPR_PRIVATE5_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK)
22596 /*! @} */
22597 
22598 /*! @name GPR_PRIVATE5_CLR - General Purpose Register */
22599 /*! @{ */
22600 
22601 #define CCM_GPR_PRIVATE5_CLR_GPR_MASK            (0xFFFFFFFFU)
22602 #define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT           (0U)
22603 /*! GPR - GP register
22604  */
22605 #define CCM_GPR_PRIVATE5_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK)
22606 /*! @} */
22607 
22608 /*! @name GPR_PRIVATE5_TOG - General Purpose Register */
22609 /*! @{ */
22610 
22611 #define CCM_GPR_PRIVATE5_TOG_GPR_MASK            (0xFFFFFFFFU)
22612 #define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT           (0U)
22613 /*! GPR - GP register
22614  */
22615 #define CCM_GPR_PRIVATE5_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK)
22616 /*! @} */
22617 
22618 /*! @name GPR_PRIVATE5_AUTHEN - GPR access control */
22619 /*! @{ */
22620 
22621 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK     (0x1U)
22622 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT    (0U)
22623 /*! TZ_USER - User access
22624  *  0b1..Clock can be changed in user mode.
22625  *  0b0..Clock cannot be changed in user mode.
22626  */
22627 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK)
22628 
22629 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK       (0x2U)
22630 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT      (1U)
22631 /*! TZ_NS - Non-secure access
22632  *  0b0..Cannot be changed in Non-secure mode.
22633  *  0b1..Can be changed in Non-secure mode.
22634  */
22635 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK)
22636 
22637 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK     (0x10U)
22638 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT    (4U)
22639 /*! LOCK_TZ - Lock truszone setting
22640  *  0b0..Trustzone setting is not locked.
22641  *  0b1..Trustzone setting is locked.
22642  */
22643 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK)
22644 
22645 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22646 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U)
22647 /*! WHITE_LIST - Whitelist
22648  *  0b0000..This domain is NOT allowed to change clock.
22649  *  0b0001..This domain is allowed to change clock.
22650  */
22651 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK)
22652 
22653 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22654 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT  (12U)
22655 /*! LOCK_LIST - Lock Whitelist
22656  *  0b0..Whitelist is not locked.
22657  *  0b1..Whitelist is locked.
22658  */
22659 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK)
22660 
22661 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22662 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22663 /*! DOMAIN_MODE - Low power and access control by Domain
22664  *  0b1..Clock works in Domain Mode.
22665  *  0b0..Clock does NOT work in Domain Mode.
22666  */
22667 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK)
22668 
22669 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22670 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT  (20U)
22671 /*! LOCK_MODE - Lock low power and access mode
22672  *  0b0..MODE is not locked.
22673  *  0b1..MODE is locked.
22674  */
22675 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK)
22676 /*! @} */
22677 
22678 /*! @name GPR_PRIVATE5_AUTHEN_SET - GPR access control */
22679 /*! @{ */
22680 
22681 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U)
22682 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U)
22683 /*! TZ_USER - User access
22684  */
22685 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK)
22686 
22687 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22688 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22689 /*! TZ_NS - Non-secure access
22690  */
22691 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK)
22692 
22693 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22694 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22695 /*! LOCK_TZ - Lock truszone setting
22696  */
22697 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK)
22698 
22699 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22700 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22701 /*! WHITE_LIST - Whitelist
22702  */
22703 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK)
22704 
22705 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22706 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22707 /*! LOCK_LIST - Lock Whitelist
22708  */
22709 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK)
22710 
22711 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22712 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22713 /*! DOMAIN_MODE - Low power and access control by Domain
22714  */
22715 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK)
22716 
22717 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22718 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22719 /*! LOCK_MODE - Lock low power and access mode
22720  */
22721 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK)
22722 /*! @} */
22723 
22724 /*! @name GPR_PRIVATE5_AUTHEN_CLR - GPR access control */
22725 /*! @{ */
22726 
22727 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22728 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22729 /*! TZ_USER - User access
22730  */
22731 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK)
22732 
22733 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22734 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22735 /*! TZ_NS - Non-secure access
22736  */
22737 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK)
22738 
22739 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22740 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22741 /*! LOCK_TZ - Lock truszone setting
22742  */
22743 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK)
22744 
22745 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22746 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22747 /*! WHITE_LIST - Whitelist
22748  */
22749 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK)
22750 
22751 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22752 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22753 /*! LOCK_LIST - Lock Whitelist
22754  */
22755 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK)
22756 
22757 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22758 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22759 /*! DOMAIN_MODE - Low power and access control by Domain
22760  */
22761 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK)
22762 
22763 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22764 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22765 /*! LOCK_MODE - Lock low power and access mode
22766  */
22767 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK)
22768 /*! @} */
22769 
22770 /*! @name GPR_PRIVATE5_AUTHEN_TOG - GPR access control */
22771 /*! @{ */
22772 
22773 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22774 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22775 /*! TZ_USER - User access
22776  */
22777 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK)
22778 
22779 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22780 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22781 /*! TZ_NS - Non-secure access
22782  */
22783 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK)
22784 
22785 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22786 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22787 /*! LOCK_TZ - Lock truszone setting
22788  */
22789 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK)
22790 
22791 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22792 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22793 /*! WHITE_LIST - Whitelist
22794  */
22795 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK)
22796 
22797 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22798 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22799 /*! LOCK_LIST - Lock Whitelist
22800  */
22801 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK)
22802 
22803 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22804 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22805 /*! DOMAIN_MODE - Low power and access control by Domain
22806  */
22807 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK)
22808 
22809 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22810 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22811 /*! LOCK_MODE - Lock low power and access mode
22812  */
22813 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK)
22814 /*! @} */
22815 
22816 /*! @name GPR_PRIVATE6 - General Purpose Register */
22817 /*! @{ */
22818 
22819 #define CCM_GPR_PRIVATE6_GPR_MASK                (0xFFFFFFFFU)
22820 #define CCM_GPR_PRIVATE6_GPR_SHIFT               (0U)
22821 /*! GPR - GP register
22822  */
22823 #define CCM_GPR_PRIVATE6_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK)
22824 /*! @} */
22825 
22826 /*! @name GPR_PRIVATE6_SET - General Purpose Register */
22827 /*! @{ */
22828 
22829 #define CCM_GPR_PRIVATE6_SET_GPR_MASK            (0xFFFFFFFFU)
22830 #define CCM_GPR_PRIVATE6_SET_GPR_SHIFT           (0U)
22831 /*! GPR - GP register
22832  */
22833 #define CCM_GPR_PRIVATE6_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK)
22834 /*! @} */
22835 
22836 /*! @name GPR_PRIVATE6_CLR - General Purpose Register */
22837 /*! @{ */
22838 
22839 #define CCM_GPR_PRIVATE6_CLR_GPR_MASK            (0xFFFFFFFFU)
22840 #define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT           (0U)
22841 /*! GPR - GP register
22842  */
22843 #define CCM_GPR_PRIVATE6_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK)
22844 /*! @} */
22845 
22846 /*! @name GPR_PRIVATE6_TOG - General Purpose Register */
22847 /*! @{ */
22848 
22849 #define CCM_GPR_PRIVATE6_TOG_GPR_MASK            (0xFFFFFFFFU)
22850 #define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT           (0U)
22851 /*! GPR - GP register
22852  */
22853 #define CCM_GPR_PRIVATE6_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK)
22854 /*! @} */
22855 
22856 /*! @name GPR_PRIVATE6_AUTHEN - GPR access control */
22857 /*! @{ */
22858 
22859 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK     (0x1U)
22860 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT    (0U)
22861 /*! TZ_USER - User access
22862  *  0b1..Clock can be changed in user mode.
22863  *  0b0..Clock cannot be changed in user mode.
22864  */
22865 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK)
22866 
22867 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK       (0x2U)
22868 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT      (1U)
22869 /*! TZ_NS - Non-secure access
22870  *  0b0..Cannot be changed in Non-secure mode.
22871  *  0b1..Can be changed in Non-secure mode.
22872  */
22873 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK)
22874 
22875 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK     (0x10U)
22876 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT    (4U)
22877 /*! LOCK_TZ - Lock truszone setting
22878  *  0b0..Trustzone setting is not locked.
22879  *  0b1..Trustzone setting is locked.
22880  */
22881 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK)
22882 
22883 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22884 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U)
22885 /*! WHITE_LIST - Whitelist
22886  *  0b0000..This domain is NOT allowed to change clock.
22887  *  0b0001..This domain is allowed to change clock.
22888  */
22889 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK)
22890 
22891 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22892 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT  (12U)
22893 /*! LOCK_LIST - Lock Whitelist
22894  *  0b0..Whitelist is not locked.
22895  *  0b1..Whitelist is locked.
22896  */
22897 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK)
22898 
22899 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22900 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22901 /*! DOMAIN_MODE - Low power and access control by Domain
22902  *  0b1..Clock works in Domain Mode.
22903  *  0b0..Clock does NOT work in Domain Mode.
22904  */
22905 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK)
22906 
22907 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22908 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT  (20U)
22909 /*! LOCK_MODE - Lock low power and access mode
22910  *  0b0..MODE is not locked.
22911  *  0b1..MODE is locked.
22912  */
22913 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK)
22914 /*! @} */
22915 
22916 /*! @name GPR_PRIVATE6_AUTHEN_SET - GPR access control */
22917 /*! @{ */
22918 
22919 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U)
22920 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U)
22921 /*! TZ_USER - User access
22922  */
22923 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK)
22924 
22925 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22926 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22927 /*! TZ_NS - Non-secure access
22928  */
22929 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK)
22930 
22931 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22932 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22933 /*! LOCK_TZ - Lock truszone setting
22934  */
22935 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK)
22936 
22937 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22938 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22939 /*! WHITE_LIST - Whitelist
22940  */
22941 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK)
22942 
22943 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22944 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22945 /*! LOCK_LIST - Lock Whitelist
22946  */
22947 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK)
22948 
22949 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22950 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22951 /*! DOMAIN_MODE - Low power and access control by Domain
22952  */
22953 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK)
22954 
22955 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22956 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22957 /*! LOCK_MODE - Lock low power and access mode
22958  */
22959 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK)
22960 /*! @} */
22961 
22962 /*! @name GPR_PRIVATE6_AUTHEN_CLR - GPR access control */
22963 /*! @{ */
22964 
22965 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22966 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22967 /*! TZ_USER - User access
22968  */
22969 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK)
22970 
22971 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22972 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22973 /*! TZ_NS - Non-secure access
22974  */
22975 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK)
22976 
22977 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22978 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22979 /*! LOCK_TZ - Lock truszone setting
22980  */
22981 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK)
22982 
22983 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22984 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22985 /*! WHITE_LIST - Whitelist
22986  */
22987 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK)
22988 
22989 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22990 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22991 /*! LOCK_LIST - Lock Whitelist
22992  */
22993 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK)
22994 
22995 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22996 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22997 /*! DOMAIN_MODE - Low power and access control by Domain
22998  */
22999 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK)
23000 
23001 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23002 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23003 /*! LOCK_MODE - Lock low power and access mode
23004  */
23005 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK)
23006 /*! @} */
23007 
23008 /*! @name GPR_PRIVATE6_AUTHEN_TOG - GPR access control */
23009 /*! @{ */
23010 
23011 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23012 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23013 /*! TZ_USER - User access
23014  */
23015 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK)
23016 
23017 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23018 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23019 /*! TZ_NS - Non-secure access
23020  */
23021 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK)
23022 
23023 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23024 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23025 /*! LOCK_TZ - Lock truszone setting
23026  */
23027 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK)
23028 
23029 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23030 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23031 /*! WHITE_LIST - Whitelist
23032  */
23033 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK)
23034 
23035 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23036 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23037 /*! LOCK_LIST - Lock Whitelist
23038  */
23039 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK)
23040 
23041 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23042 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23043 /*! DOMAIN_MODE - Low power and access control by Domain
23044  */
23045 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK)
23046 
23047 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23048 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23049 /*! LOCK_MODE - Lock low power and access mode
23050  */
23051 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK)
23052 /*! @} */
23053 
23054 /*! @name GPR_PRIVATE7 - General Purpose Register */
23055 /*! @{ */
23056 
23057 #define CCM_GPR_PRIVATE7_GPR_MASK                (0xFFFFFFFFU)
23058 #define CCM_GPR_PRIVATE7_GPR_SHIFT               (0U)
23059 /*! GPR - GP register
23060  */
23061 #define CCM_GPR_PRIVATE7_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK)
23062 /*! @} */
23063 
23064 /*! @name GPR_PRIVATE7_SET - General Purpose Register */
23065 /*! @{ */
23066 
23067 #define CCM_GPR_PRIVATE7_SET_GPR_MASK            (0xFFFFFFFFU)
23068 #define CCM_GPR_PRIVATE7_SET_GPR_SHIFT           (0U)
23069 /*! GPR - GP register
23070  */
23071 #define CCM_GPR_PRIVATE7_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK)
23072 /*! @} */
23073 
23074 /*! @name GPR_PRIVATE7_CLR - General Purpose Register */
23075 /*! @{ */
23076 
23077 #define CCM_GPR_PRIVATE7_CLR_GPR_MASK            (0xFFFFFFFFU)
23078 #define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT           (0U)
23079 /*! GPR - GP register
23080  */
23081 #define CCM_GPR_PRIVATE7_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK)
23082 /*! @} */
23083 
23084 /*! @name GPR_PRIVATE7_TOG - General Purpose Register */
23085 /*! @{ */
23086 
23087 #define CCM_GPR_PRIVATE7_TOG_GPR_MASK            (0xFFFFFFFFU)
23088 #define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT           (0U)
23089 /*! GPR - GP register
23090  */
23091 #define CCM_GPR_PRIVATE7_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK)
23092 /*! @} */
23093 
23094 /*! @name GPR_PRIVATE7_AUTHEN - GPR access control */
23095 /*! @{ */
23096 
23097 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK     (0x1U)
23098 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT    (0U)
23099 /*! TZ_USER - User access
23100  *  0b1..Clock can be changed in user mode.
23101  *  0b0..Clock cannot be changed in user mode.
23102  */
23103 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK)
23104 
23105 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK       (0x2U)
23106 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT      (1U)
23107 /*! TZ_NS - Non-secure access
23108  *  0b0..Cannot be changed in Non-secure mode.
23109  *  0b1..Can be changed in Non-secure mode.
23110  */
23111 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK)
23112 
23113 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK     (0x10U)
23114 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT    (4U)
23115 /*! LOCK_TZ - Lock truszone setting
23116  *  0b0..Trustzone setting is not locked.
23117  *  0b1..Trustzone setting is locked.
23118  */
23119 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK)
23120 
23121 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK  (0xF00U)
23122 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U)
23123 /*! WHITE_LIST - Whitelist
23124  *  0b0000..This domain is NOT allowed to change clock.
23125  *  0b0001..This domain is allowed to change clock.
23126  */
23127 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK)
23128 
23129 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK   (0x1000U)
23130 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT  (12U)
23131 /*! LOCK_LIST - Lock Whitelist
23132  *  0b0..Whitelist is not locked.
23133  *  0b1..Whitelist is locked.
23134  */
23135 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK)
23136 
23137 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23138 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23139 /*! DOMAIN_MODE - Low power and access control by Domain
23140  *  0b1..Clock works in Domain Mode.
23141  *  0b0..Clock does NOT work in Domain Mode.
23142  */
23143 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK)
23144 
23145 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23146 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT  (20U)
23147 /*! LOCK_MODE - Lock low power and access mode
23148  *  0b0..MODE is not locked.
23149  *  0b1..MODE is locked.
23150  */
23151 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK)
23152 /*! @} */
23153 
23154 /*! @name GPR_PRIVATE7_AUTHEN_SET - GPR access control */
23155 /*! @{ */
23156 
23157 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U)
23158 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U)
23159 /*! TZ_USER - User access
23160  */
23161 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK)
23162 
23163 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23164 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23165 /*! TZ_NS - Non-secure access
23166  */
23167 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK)
23168 
23169 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23170 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23171 /*! LOCK_TZ - Lock truszone setting
23172  */
23173 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK)
23174 
23175 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23176 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23177 /*! WHITE_LIST - Whitelist
23178  */
23179 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK)
23180 
23181 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23182 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23183 /*! LOCK_LIST - Lock Whitelist
23184  */
23185 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK)
23186 
23187 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23188 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23189 /*! DOMAIN_MODE - Low power and access control by Domain
23190  */
23191 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK)
23192 
23193 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23194 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23195 /*! LOCK_MODE - Lock low power and access mode
23196  */
23197 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK)
23198 /*! @} */
23199 
23200 /*! @name GPR_PRIVATE7_AUTHEN_CLR - GPR access control */
23201 /*! @{ */
23202 
23203 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23204 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23205 /*! TZ_USER - User access
23206  */
23207 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK)
23208 
23209 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23210 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23211 /*! TZ_NS - Non-secure access
23212  */
23213 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK)
23214 
23215 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23216 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23217 /*! LOCK_TZ - Lock truszone setting
23218  */
23219 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK)
23220 
23221 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23222 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23223 /*! WHITE_LIST - Whitelist
23224  */
23225 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK)
23226 
23227 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23228 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23229 /*! LOCK_LIST - Lock Whitelist
23230  */
23231 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK)
23232 
23233 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23234 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23235 /*! DOMAIN_MODE - Low power and access control by Domain
23236  */
23237 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK)
23238 
23239 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23240 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23241 /*! LOCK_MODE - Lock low power and access mode
23242  */
23243 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK)
23244 /*! @} */
23245 
23246 /*! @name GPR_PRIVATE7_AUTHEN_TOG - GPR access control */
23247 /*! @{ */
23248 
23249 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23250 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23251 /*! TZ_USER - User access
23252  */
23253 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK)
23254 
23255 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23256 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23257 /*! TZ_NS - Non-secure access
23258  */
23259 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK)
23260 
23261 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23262 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23263 /*! LOCK_TZ - Lock truszone setting
23264  */
23265 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK)
23266 
23267 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23268 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23269 /*! WHITE_LIST - Whitelist
23270  */
23271 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK)
23272 
23273 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23274 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23275 /*! LOCK_LIST - Lock Whitelist
23276  */
23277 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK)
23278 
23279 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23280 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23281 /*! DOMAIN_MODE - Low power and access control by Domain
23282  */
23283 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK)
23284 
23285 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23286 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23287 /*! LOCK_MODE - Lock low power and access mode
23288  */
23289 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK)
23290 /*! @} */
23291 
23292 /*! @name OSCPLL_DIRECT - Clock source direct control */
23293 /*! @{ */
23294 
23295 #define CCM_OSCPLL_DIRECT_ON_MASK                (0x1U)
23296 #define CCM_OSCPLL_DIRECT_ON_SHIFT               (0U)
23297 /*! ON - turn on clock source
23298  *  0b0..OSCPLL is OFF
23299  *  0b1..OSCPLL is ON
23300  */
23301 #define CCM_OSCPLL_DIRECT_ON(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
23302 /*! @} */
23303 
23304 /* The count of CCM_OSCPLL_DIRECT */
23305 #define CCM_OSCPLL_DIRECT_COUNT                  (29U)
23306 
23307 /*! @name OSCPLL_DOMAIN - Clock source domain control */
23308 /*! @{ */
23309 
23310 #define CCM_OSCPLL_DOMAIN_LEVEL_MASK             (0x7U)
23311 #define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT            (0U)
23312 /*! LEVEL - Current dependence level
23313  *  0b000..This clock source is not needed in any mode, and can be turned off
23314  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23315  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23316  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23317  *  0b100..This clock source is always on in any mode (including SUSPEND)
23318  *  0b101, 0b110, 0b111..Reserved
23319  */
23320 #define CCM_OSCPLL_DOMAIN_LEVEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK)
23321 
23322 #define CCM_OSCPLL_DOMAIN_LEVEL0_MASK            (0x70000U)
23323 #define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT           (16U)
23324 /*! LEVEL0 - Dependence level
23325  *  0b000..This clock source is not needed in any mode, and can be turned off
23326  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23327  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23328  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23329  *  0b100..This clock source is always on in any mode (including SUSPEND)
23330  *  0b101, 0b110, 0b111..Reserved
23331  */
23332 #define CCM_OSCPLL_DOMAIN_LEVEL0(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK)
23333 
23334 #define CCM_OSCPLL_DOMAIN_LEVEL1_MASK            (0x700000U)
23335 #define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT           (20U)
23336 /*! LEVEL1 - Depend level
23337  *  0b000..This clock source is not needed in any mode, and can be turned off
23338  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23339  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23340  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23341  *  0b100..This clock source is always on in any mode (including SUSPEND)
23342  *  0b101, 0b110, 0b111..Reserved
23343  */
23344 #define CCM_OSCPLL_DOMAIN_LEVEL1(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK)
23345 
23346 #define CCM_OSCPLL_DOMAIN_LEVEL2_MASK            (0x7000000U)
23347 #define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT           (24U)
23348 /*! LEVEL2 - Depend level
23349  *  0b000..This clock source is not needed in any mode, and can be turned off
23350  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23351  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23352  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23353  *  0b100..This clock source is always on in any mode (including SUSPEND)
23354  *  0b101, 0b110, 0b111..Reserved
23355  */
23356 #define CCM_OSCPLL_DOMAIN_LEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK)
23357 
23358 #define CCM_OSCPLL_DOMAIN_LEVEL3_MASK            (0x70000000U)
23359 #define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT           (28U)
23360 /*! LEVEL3 - Depend level
23361  *  0b000..This clock source is not needed in any mode, and can be turned off
23362  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23363  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23364  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23365  *  0b100..This clock source is always on in any mode (including SUSPEND)
23366  *  0b101, 0b110, 0b111..Reserved
23367  */
23368 #define CCM_OSCPLL_DOMAIN_LEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK)
23369 /*! @} */
23370 
23371 /* The count of CCM_OSCPLL_DOMAIN */
23372 #define CCM_OSCPLL_DOMAIN_COUNT                  (29U)
23373 
23374 /*! @name OSCPLL_SETPOINT - Clock source Setpoint setting */
23375 /*! @{ */
23376 
23377 #define CCM_OSCPLL_SETPOINT_SETPOINT_MASK        (0xFFFFU)
23378 #define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT       (0U)
23379 /*! SETPOINT - Setpoint
23380  */
23381 #define CCM_OSCPLL_SETPOINT_SETPOINT(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK)
23382 
23383 #define CCM_OSCPLL_SETPOINT_STANDBY_MASK         (0xFFFF0000U)
23384 #define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT        (16U)
23385 /*! STANDBY - Standby
23386  */
23387 #define CCM_OSCPLL_SETPOINT_STANDBY(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK)
23388 /*! @} */
23389 
23390 /* The count of CCM_OSCPLL_SETPOINT */
23391 #define CCM_OSCPLL_SETPOINT_COUNT                (29U)
23392 
23393 /*! @name OSCPLL_STATUS0 - Clock source working status */
23394 /*! @{ */
23395 
23396 #define CCM_OSCPLL_STATUS0_ON_MASK               (0x1U)
23397 #define CCM_OSCPLL_STATUS0_ON_SHIFT              (0U)
23398 /*! ON - Clock source current state
23399  *  0b0..Clock source is OFF
23400  *  0b1..Clock source is ON
23401  */
23402 #define CCM_OSCPLL_STATUS0_ON(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
23403 
23404 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK     (0x10U)
23405 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT    (4U)
23406 /*! STATUS_EARLY - Clock source active
23407  *  0b1..Clock source is active
23408  *  0b0..Clock source is not active
23409  */
23410 #define CCM_OSCPLL_STATUS0_STATUS_EARLY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
23411 
23412 #define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK      (0x20U)
23413 #define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT     (5U)
23414 /*! STATUS_LATE - Clock source ready
23415  *  0b1..Clock source is ready to use
23416  *  0b0..Clock source is not ready to use
23417  */
23418 #define CCM_OSCPLL_STATUS0_STATUS_LATE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
23419 
23420 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK    (0xF00U)
23421 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT   (8U)
23422 /*! ACTIVE_DOMAIN - Domains that own this clock source
23423  *  0b0000..Clock not owned by any domain
23424  *  0b0001..Clock owned by Domain0
23425  *  0b0010..Clock owned by Domain1
23426  *  0b0011..Clock owned by Domain0 and Domain1
23427  *  0b0100..Clock owned by Domain2
23428  *  0b0101..Clock owned by Domain0 and Domain2
23429  *  0b0110..Clock owned by Domain1 and Domain2
23430  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
23431  *  0b1000..Clock owned by Domain3
23432  *  0b1001..Clock owned by Domain0 and Domain3
23433  *  0b1010..Clock owned by Domain1 and Domain3
23434  *  0b1011..Clock owned by Domain2 and Domain3
23435  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
23436  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
23437  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
23438  *  0b1111..Clock owned by all domains
23439  */
23440 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK)
23441 
23442 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK    (0xF000U)
23443 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT   (12U)
23444 /*! DOMAIN_ENABLE - Enable status from each domain
23445  *  0b0000..No domain request
23446  *  0b0001..Request from Domain0
23447  *  0b0010..Request from Domain1
23448  *  0b0011..Request from Domain0 and Domain1
23449  *  0b0100..Request from Domain2
23450  *  0b0101..Request from Domain0 and Domain2
23451  *  0b0110..Request from Domain1 and Domain2
23452  *  0b0111..Request from Domain0, Domain1 and Domain 2
23453  *  0b1000..Request from Domain3
23454  *  0b1001..Request from Domain0 and Domain3
23455  *  0b1010..Request from Domain1 and Domain3
23456  *  0b1011..Request from Domain2 and Domain3
23457  *  0b1100..Request from Domain0, Domain 1, and Domain3
23458  *  0b1101..Request from Domain0, Domain 2, and Domain3
23459  *  0b1110..Request from Domain1, Domain 2, and Domain3
23460  *  0b1111..Request from all domains
23461  */
23462 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK)
23463 
23464 #define CCM_OSCPLL_STATUS0_IN_USE_MASK           (0x10000000U)
23465 #define CCM_OSCPLL_STATUS0_IN_USE_SHIFT          (28U)
23466 /*! IN_USE - In use
23467  *  0b1..Clock source is being used by clock roots
23468  *  0b0..Clock source is not being used by clock roots
23469  */
23470 #define CCM_OSCPLL_STATUS0_IN_USE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
23471 /*! @} */
23472 
23473 /* The count of CCM_OSCPLL_STATUS0 */
23474 #define CCM_OSCPLL_STATUS0_COUNT                 (29U)
23475 
23476 /*! @name OSCPLL_STATUS1 - Clock source low power status */
23477 /*! @{ */
23478 
23479 #define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK        (0x3U)
23480 #define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT       (0U)
23481 /*! CPU0_MODE - Domain0 Low Power Mode
23482  *  0b00..Run
23483  *  0b01..Wait
23484  *  0b10..Stop
23485  *  0b11..Suspend
23486  */
23487 #define CCM_OSCPLL_STATUS1_CPU0_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK)
23488 
23489 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
23490 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
23491 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
23492  *  0b1..Request from domain to enter Low Power Mode
23493  *  0b0..No request
23494  */
23495 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK)
23496 
23497 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK   (0x8U)
23498 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT  (3U)
23499 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
23500  *  0b1..Clock is gated-off
23501  *  0b0..Clock is not gated
23502  */
23503 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK)
23504 
23505 #define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK        (0x30U)
23506 #define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT       (4U)
23507 /*! CPU1_MODE - Domain1 Low Power Mode
23508  *  0b00..Run
23509  *  0b01..Wait
23510  *  0b10..Stop
23511  *  0b11..Suspend
23512  */
23513 #define CCM_OSCPLL_STATUS1_CPU1_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK)
23514 
23515 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
23516 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
23517 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
23518  *  0b1..Request from domain to enter Low Power Mode
23519  *  0b0..No request
23520  */
23521 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK)
23522 
23523 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK   (0x80U)
23524 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT  (7U)
23525 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
23526  *  0b1..Clock is gated-off
23527  *  0b0..Clock is not gated
23528  */
23529 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK)
23530 
23531 #define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK        (0x300U)
23532 #define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT       (8U)
23533 /*! CPU2_MODE - Domain2 Low Power Mode
23534  *  0b00..Run
23535  *  0b01..Wait
23536  *  0b10..Stop
23537  *  0b11..Suspend
23538  */
23539 #define CCM_OSCPLL_STATUS1_CPU2_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK)
23540 
23541 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
23542 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
23543 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
23544  *  0b1..Request from domain to enter Low Power Mode
23545  *  0b0..No request
23546  */
23547 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK)
23548 
23549 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK   (0x800U)
23550 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT  (11U)
23551 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
23552  *  0b1..Clock is gated-off
23553  *  0b0..Clock is not gated
23554  */
23555 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK)
23556 
23557 #define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK        (0x3000U)
23558 #define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT       (12U)
23559 /*! CPU3_MODE - Domain3 Low Power Mode
23560  *  0b00..Run
23561  *  0b01..Wait
23562  *  0b10..Stop
23563  *  0b11..Suspend
23564  */
23565 #define CCM_OSCPLL_STATUS1_CPU3_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK)
23566 
23567 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
23568 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
23569 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
23570  *  0b1..Request from domain to enter Low Power Mode
23571  *  0b0..No request
23572  */
23573 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK)
23574 
23575 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK   (0x8000U)
23576 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT  (15U)
23577 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
23578  *  0b1..Clock is gated-off
23579  *  0b0..Clock is not gated
23580  */
23581 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK)
23582 
23583 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK  (0xF0000U)
23584 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U)
23585 /*! TARGET_SETPOINT - Next Setpoint to change to
23586  */
23587 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK)
23588 
23589 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
23590 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
23591 /*! CURRENT_SETPOINT - Current Setpoint
23592  */
23593 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK)
23594 
23595 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
23596 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
23597 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
23598  *  0b1..Clock gate requested to be turned off
23599  *  0b0..No request
23600  */
23601 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK)
23602 
23603 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
23604 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
23605 /*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC Setpoint
23606  *  0b1..Clock source is turned off
23607  *  0b0..Clock source is not turned off
23608  */
23609 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK)
23610 
23611 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
23612 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
23613 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
23614  *  0b1..Clock gate requested to be turned on
23615  *  0b0..No request
23616  */
23617 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK)
23618 
23619 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
23620 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
23621 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
23622  *  0b1..Request to turn on clock gate
23623  *  0b0..No request
23624  */
23625 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK)
23626 
23627 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U)
23628 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U)
23629 /*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby
23630  *  0b1..Clock gate requested to be turned off
23631  *  0b0..No request
23632  */
23633 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK)
23634 
23635 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK  (0x20000000U)
23636 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U)
23637 /*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby
23638  *  0b1..Clock source is turned off
23639  *  0b0..Clock source is not turned off
23640  */
23641 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK)
23642 
23643 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U)
23644 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U)
23645 /*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby
23646  *  0b1..Request to turn on Clock gate is complete
23647  *  0b0..Request to turn on Clock gate is not complete
23648  */
23649 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK)
23650 
23651 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U)
23652 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U)
23653 /*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby
23654  *  0b1..Clock gate requested to be turned on
23655  *  0b0..No request
23656  */
23657 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK)
23658 /*! @} */
23659 
23660 /* The count of CCM_OSCPLL_STATUS1 */
23661 #define CCM_OSCPLL_STATUS1_COUNT                 (29U)
23662 
23663 /*! @name OSCPLL_CONFIG - Clock source configuration */
23664 /*! @{ */
23665 
23666 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK  (0x2U)
23667 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U)
23668 /*! AUTOMODE_PRESENT - Automode Present
23669  *  0b1..Present
23670  *  0b0..Not present
23671  */
23672 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK)
23673 
23674 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK  (0x10U)
23675 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
23676 /*! SETPOINT_PRESENT - Setpoint present
23677  *  0b1..Setpoint is implemented.
23678  *  0b0..Setpoint is not implemented.
23679  */
23680 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK)
23681 /*! @} */
23682 
23683 /* The count of CCM_OSCPLL_CONFIG */
23684 #define CCM_OSCPLL_CONFIG_COUNT                  (29U)
23685 
23686 /*! @name OSCPLL_AUTHEN - Clock source access control */
23687 /*! @{ */
23688 
23689 #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK           (0x1U)
23690 #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT          (0U)
23691 /*! TZ_USER - User access
23692  *  0b1..Clock can be changed in user mode.
23693  *  0b0..Clock cannot be changed in user mode.
23694  */
23695 #define CCM_OSCPLL_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
23696 
23697 #define CCM_OSCPLL_AUTHEN_TZ_NS_MASK             (0x2U)
23698 #define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT            (1U)
23699 /*! TZ_NS - Non-secure access
23700  *  0b0..Cannot be changed in Non-secure mode.
23701  *  0b1..Can be changed in Non-secure mode.
23702  */
23703 #define CCM_OSCPLL_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
23704 
23705 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK           (0x10U)
23706 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT          (4U)
23707 /*! LOCK_TZ - lock truszone setting
23708  *  0b0..Trustzone setting is not locked.
23709  *  0b1..Trustzone setting is locked.
23710  */
23711 #define CCM_OSCPLL_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
23712 
23713 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK        (0xF00U)
23714 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT       (8U)
23715 /*! WHITE_LIST - Whitelist
23716  */
23717 #define CCM_OSCPLL_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
23718 
23719 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK         (0x1000U)
23720 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT        (12U)
23721 /*! LOCK_LIST - Lock Whitelist
23722  *  0b0..Whitelist is not locked.
23723  *  0b1..Whitelist is locked.
23724  */
23725 #define CCM_OSCPLL_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
23726 
23727 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK       (0x10000U)
23728 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT      (16U)
23729 /*! DOMAIN_MODE - Low power and access control by domain
23730  *  0b1..Clock works in Domain Mode.
23731  *  0b0..Clock does not work in Domain Mode.
23732  */
23733 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK)
23734 
23735 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK     (0x20000U)
23736 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT    (17U)
23737 /*! SETPOINT_MODE - LPCG works in Setpoint controlled Mode.
23738  */
23739 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK)
23740 
23741 #define CCM_OSCPLL_AUTHEN_CPULPM_MASK            (0x40000U)
23742 #define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT           (18U)
23743 /*! CPULPM - CPU Low Power Mode
23744  *  0b1..PLL functions in Low Power Mode
23745  *  0b0..PLL does not function in Low power Mode
23746  */
23747 #define CCM_OSCPLL_AUTHEN_CPULPM(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK)
23748 
23749 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK         (0x100000U)
23750 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT        (20U)
23751 /*! LOCK_MODE - Lock low power and access mode
23752  *  0b0..MODE is not locked.
23753  *  0b1..MODE is locked.
23754  */
23755 #define CCM_OSCPLL_AUTHEN_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK)
23756 /*! @} */
23757 
23758 /* The count of CCM_OSCPLL_AUTHEN */
23759 #define CCM_OSCPLL_AUTHEN_COUNT                  (29U)
23760 
23761 /*! @name LPCG_DIRECT - LPCG direct control */
23762 /*! @{ */
23763 
23764 #define CCM_LPCG_DIRECT_ON_MASK                  (0x1U)
23765 #define CCM_LPCG_DIRECT_ON_SHIFT                 (0U)
23766 /*! ON - LPCG on
23767  *  0b0..LPCG is OFF.
23768  *  0b1..LPCG is ON.
23769  */
23770 #define CCM_LPCG_DIRECT_ON(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
23771 /*! @} */
23772 
23773 /* The count of CCM_LPCG_DIRECT */
23774 #define CCM_LPCG_DIRECT_COUNT                    (138U)
23775 
23776 /*! @name LPCG_DOMAIN - LPCG domain control */
23777 /*! @{ */
23778 
23779 #define CCM_LPCG_DOMAIN_LEVEL_MASK               (0x7U)
23780 #define CCM_LPCG_DOMAIN_LEVEL_SHIFT              (0U)
23781 /*! LEVEL - Current dependence level
23782  *  0b000..This clock source is not needed in any mode, and can be turned off
23783  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23784  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23785  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23786  *  0b100..This clock source is always on in any mode (including SUSPEND)
23787  *  0b101, 0b110, 0b111..Reserved
23788  */
23789 #define CCM_LPCG_DOMAIN_LEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK)
23790 
23791 #define CCM_LPCG_DOMAIN_LEVEL0_MASK              (0x70000U)
23792 #define CCM_LPCG_DOMAIN_LEVEL0_SHIFT             (16U)
23793 /*! LEVEL0 - Depend level
23794  *  0b000..This clock source is not needed in any mode, and can be turned off
23795  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23796  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23797  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23798  *  0b100..This clock source is always on in any mode (including SUSPEND)
23799  *  0b101, 0b110, 0b111..Reserved
23800  */
23801 #define CCM_LPCG_DOMAIN_LEVEL0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK)
23802 
23803 #define CCM_LPCG_DOMAIN_LEVEL1_MASK              (0x700000U)
23804 #define CCM_LPCG_DOMAIN_LEVEL1_SHIFT             (20U)
23805 /*! LEVEL1 - Depend level
23806  *  0b000..This clock source is not needed in any mode, and can be turned off
23807  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23808  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23809  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23810  *  0b100..This clock source is always on in any mode (including SUSPEND)
23811  *  0b101, 0b110, 0b111..Reserved
23812  */
23813 #define CCM_LPCG_DOMAIN_LEVEL1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK)
23814 
23815 #define CCM_LPCG_DOMAIN_LEVEL2_MASK              (0x7000000U)
23816 #define CCM_LPCG_DOMAIN_LEVEL2_SHIFT             (24U)
23817 /*! LEVEL2 - Depend level
23818  *  0b000..This clock source is not needed in any mode, and can be turned off
23819  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23820  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23821  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23822  *  0b100..This clock source is always on in any mode (including SUSPEND)
23823  *  0b101, 0b110, 0b111..Reserved
23824  */
23825 #define CCM_LPCG_DOMAIN_LEVEL2(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK)
23826 
23827 #define CCM_LPCG_DOMAIN_LEVEL3_MASK              (0x70000000U)
23828 #define CCM_LPCG_DOMAIN_LEVEL3_SHIFT             (28U)
23829 /*! LEVEL3 - Depend level
23830  *  0b000..This clock source is not needed in any mode, and can be turned off
23831  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23832  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23833  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23834  *  0b100..This clock source is always on in any mode (including SUSPEND)
23835  *  0b101, 0b110, 0b111..Reserved
23836  */
23837 #define CCM_LPCG_DOMAIN_LEVEL3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK)
23838 /*! @} */
23839 
23840 /* The count of CCM_LPCG_DOMAIN */
23841 #define CCM_LPCG_DOMAIN_COUNT                    (138U)
23842 
23843 /*! @name LPCG_SETPOINT - LPCG Setpoint setting */
23844 /*! @{ */
23845 
23846 #define CCM_LPCG_SETPOINT_SETPOINT_MASK          (0xFFFFU)
23847 #define CCM_LPCG_SETPOINT_SETPOINT_SHIFT         (0U)
23848 /*! SETPOINT - Setpoints
23849  */
23850 #define CCM_LPCG_SETPOINT_SETPOINT(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK)
23851 
23852 #define CCM_LPCG_SETPOINT_STANDBY_MASK           (0xFFFF0000U)
23853 #define CCM_LPCG_SETPOINT_STANDBY_SHIFT          (16U)
23854 /*! STANDBY - Standby
23855  */
23856 #define CCM_LPCG_SETPOINT_STANDBY(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK)
23857 /*! @} */
23858 
23859 /* The count of CCM_LPCG_SETPOINT */
23860 #define CCM_LPCG_SETPOINT_COUNT                  (138U)
23861 
23862 /*! @name LPCG_STATUS0 - LPCG working status */
23863 /*! @{ */
23864 
23865 #define CCM_LPCG_STATUS0_ON_MASK                 (0x1U)
23866 #define CCM_LPCG_STATUS0_ON_SHIFT                (0U)
23867 /*! ON - LPCG current state
23868  *  0b0..LPCG is OFF.
23869  *  0b1..LPCG is ON.
23870  */
23871 #define CCM_LPCG_STATUS0_ON(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
23872 
23873 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK      (0xF00U)
23874 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT     (8U)
23875 /*! ACTIVE_DOMAIN - Domains that own this clock gate
23876  *  0b0000..Clock not owned by any domain
23877  *  0b0001..Clock owned by Domain0
23878  *  0b0010..Clock owned by Domain1
23879  *  0b0011..Clock owned by Domain0 and Domain1
23880  *  0b0100..Clock owned by Domain2
23881  *  0b0101..Clock owned by Domain0 and Domain2
23882  *  0b0110..Clock owned by Domain1 and Domain2
23883  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
23884  *  0b1000..Clock owned by Domain3
23885  *  0b1001..Clock owned by Domain0 and Domain3
23886  *  0b1010..Clock owned by Domain1 and Domain3
23887  *  0b1011..Clock owned by Domain2 and Domain3
23888  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
23889  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
23890  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
23891  *  0b1111..Clock owned by all domains
23892  */
23893 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK)
23894 
23895 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK      (0xF000U)
23896 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT     (12U)
23897 /*! DOMAIN_ENABLE - Enable status from each domain
23898  *  0b0000..No domain request
23899  *  0b0001..Request from Domain0
23900  *  0b0010..Request from Domain1
23901  *  0b0011..Request from Domain0 and Domain1
23902  *  0b0100..Request from Domain2
23903  *  0b0101..Request from Domain0 and Domain2
23904  *  0b0110..Request from Domain1 and Domain2
23905  *  0b0111..Request from Domain0, Domain1 and Domain 2
23906  *  0b1000..Request from Domain3
23907  *  0b1001..Request from Domain0 and Domain3
23908  *  0b1010..Request from Domain1 and Domain3
23909  *  0b1011..Request from Domain2 and Domain3
23910  *  0b1100..Request from Domain0, Domain 1, and Domain3
23911  *  0b1101..Request from Domain0, Domain 2, and Domain3
23912  *  0b1110..Request from Domain1, Domain 2, and Domain3
23913  *  0b1111..Request from all domains
23914  */
23915 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK)
23916 /*! @} */
23917 
23918 /* The count of CCM_LPCG_STATUS0 */
23919 #define CCM_LPCG_STATUS0_COUNT                   (138U)
23920 
23921 /*! @name LPCG_STATUS1 - LPCG low power status */
23922 /*! @{ */
23923 
23924 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK          (0x3U)
23925 #define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT         (0U)
23926 /*! CPU0_MODE - Domain0 Low Power Mode
23927  *  0b00..Run
23928  *  0b01..Wait
23929  *  0b10..Stop
23930  *  0b11..Suspend
23931  */
23932 #define CCM_LPCG_STATUS1_CPU0_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
23933 
23934 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK  (0x4U)
23935 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
23936 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
23937  *  0b1..Request from domain to enter Low Power Mode
23938  *  0b0..No request
23939  */
23940 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK)
23941 
23942 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK     (0x8U)
23943 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT    (3U)
23944 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
23945  *  0b1..Clock is gated-off
23946  *  0b0..Clock is not gated
23947  */
23948 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK)
23949 
23950 #define CCM_LPCG_STATUS1_CPU1_MODE_MASK          (0x30U)
23951 #define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT         (4U)
23952 /*! CPU1_MODE - Domain1 Low Power Mode
23953  *  0b00..Run
23954  *  0b01..Wait
23955  *  0b10..Stop
23956  *  0b11..Suspend
23957  */
23958 #define CCM_LPCG_STATUS1_CPU1_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK)
23959 
23960 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK  (0x40U)
23961 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
23962 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
23963  *  0b1..Request from domain to enter Low Power Mode
23964  *  0b0..No request
23965  */
23966 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK)
23967 
23968 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK     (0x80U)
23969 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT    (7U)
23970 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
23971  *  0b1..Clock is gated-off
23972  *  0b0..Clock is not gated
23973  */
23974 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK)
23975 
23976 #define CCM_LPCG_STATUS1_CPU2_MODE_MASK          (0x300U)
23977 #define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT         (8U)
23978 /*! CPU2_MODE - Domain2 Low Power Mode
23979  *  0b00..Run
23980  *  0b01..Wait
23981  *  0b10..Stop
23982  *  0b11..Suspend
23983  */
23984 #define CCM_LPCG_STATUS1_CPU2_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK)
23985 
23986 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK  (0x400U)
23987 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
23988 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
23989  *  0b1..Request from domain to enter Low Power Mode
23990  *  0b0..No request
23991  */
23992 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK)
23993 
23994 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK     (0x800U)
23995 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT    (11U)
23996 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
23997  *  0b1..Clock is gated-off
23998  *  0b0..Clock is not gated
23999  */
24000 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK)
24001 
24002 #define CCM_LPCG_STATUS1_CPU3_MODE_MASK          (0x3000U)
24003 #define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT         (12U)
24004 /*! CPU3_MODE - Domain3 Low Power Mode
24005  *  0b00..Run
24006  *  0b01..Wait
24007  *  0b10..Stop
24008  *  0b11..Suspend
24009  */
24010 #define CCM_LPCG_STATUS1_CPU3_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK)
24011 
24012 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK  (0x4000U)
24013 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
24014 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
24015  *  0b1..Request from domain to enter Low Power Mode
24016  *  0b0..No request
24017  */
24018 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK)
24019 
24020 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK     (0x8000U)
24021 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT    (15U)
24022 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
24023  *  0b1..Clock is gated-off
24024  *  0b0..Clock is not gated
24025  */
24026 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK)
24027 
24028 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK    (0xF0000U)
24029 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
24030 /*! TARGET_SETPOINT - Next Setpoint to change to
24031  */
24032 #define CCM_LPCG_STATUS1_TARGET_SETPOINT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK)
24033 
24034 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
24035 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT  (20U)
24036 /*! CURRENT_SETPOINT - Current Setpoint
24037  */
24038 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK)
24039 
24040 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
24041 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
24042 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
24043  *  0b1..Clock gate requested to be turned off
24044  *  0b0..No request
24045  */
24046 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK)
24047 
24048 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK  (0x2000000U)
24049 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
24050 /*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC Setpoint
24051  *  0b1..Clock gate is turned off
24052  *  0b0..Clock gate is not turned off
24053  */
24054 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK)
24055 
24056 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
24057 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
24058 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
24059  *  0b1..Clock gate requested to be turned on
24060  *  0b0..No request
24061  */
24062 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK)
24063 
24064 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK   (0x8000000U)
24065 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT  (27U)
24066 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
24067  *  0b1..Clock gate is turned on
24068  *  0b0..Clock gate is not turned on
24069  */
24070 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK)
24071 /*! @} */
24072 
24073 /* The count of CCM_LPCG_STATUS1 */
24074 #define CCM_LPCG_STATUS1_COUNT                   (138U)
24075 
24076 /*! @name LPCG_CONFIG - LPCG configuration */
24077 /*! @{ */
24078 
24079 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK    (0x10U)
24080 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
24081 /*! SETPOINT_PRESENT - Setpoint present
24082  *  0b1..Setpoint is implemented.
24083  *  0b0..Setpoint is not implemented.
24084  */
24085 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK)
24086 /*! @} */
24087 
24088 /* The count of CCM_LPCG_CONFIG */
24089 #define CCM_LPCG_CONFIG_COUNT                    (138U)
24090 
24091 /*! @name LPCG_AUTHEN - LPCG access control */
24092 /*! @{ */
24093 
24094 #define CCM_LPCG_AUTHEN_TZ_USER_MASK             (0x1U)
24095 #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT            (0U)
24096 /*! TZ_USER - User access
24097  *  0b1..LPCG can be changed in user mode.
24098  *  0b0..LPCG cannot be changed in user mode.
24099  */
24100 #define CCM_LPCG_AUTHEN_TZ_USER(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
24101 
24102 #define CCM_LPCG_AUTHEN_TZ_NS_MASK               (0x2U)
24103 #define CCM_LPCG_AUTHEN_TZ_NS_SHIFT              (1U)
24104 /*! TZ_NS - Non-secure access
24105  *  0b0..Cannot be changed in Non-secure mode.
24106  *  0b1..Can be changed in Non-secure mode.
24107  */
24108 #define CCM_LPCG_AUTHEN_TZ_NS(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
24109 
24110 #define CCM_LPCG_AUTHEN_LOCK_TZ_MASK             (0x10U)
24111 #define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT            (4U)
24112 /*! LOCK_TZ - lock truszone setting
24113  *  0b0..Trustzone setting is not locked.
24114  *  0b1..Trustzone setting is locked.
24115  */
24116 #define CCM_LPCG_AUTHEN_LOCK_TZ(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
24117 
24118 #define CCM_LPCG_AUTHEN_WHITE_LIST_MASK          (0xF00U)
24119 #define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT         (8U)
24120 /*! WHITE_LIST - Whitelist
24121  */
24122 #define CCM_LPCG_AUTHEN_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
24123 
24124 #define CCM_LPCG_AUTHEN_LOCK_LIST_MASK           (0x1000U)
24125 #define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT          (12U)
24126 /*! LOCK_LIST - Lock Whitelist
24127  *  0b0..Whitelist is not locked.
24128  *  0b1..Whitelist is locked.
24129  */
24130 #define CCM_LPCG_AUTHEN_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
24131 
24132 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK         (0x10000U)
24133 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT        (16U)
24134 /*! DOMAIN_MODE - Low power and access control by domain
24135  *  0b1..Clock works in Domain Mode
24136  *  0b0..Clock does not work in Domain Mode
24137  */
24138 #define CCM_LPCG_AUTHEN_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK)
24139 
24140 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK       (0x20000U)
24141 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT      (17U)
24142 /*! SETPOINT_MODE - Low power and access control by Setpoint
24143  *  0b1..LPCG is functioning in Setpoint controlled Mode
24144  *  0b0..LPCG is not functioning in Setpoint controlled Mode
24145  */
24146 #define CCM_LPCG_AUTHEN_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK)
24147 
24148 #define CCM_LPCG_AUTHEN_CPULPM_MASK              (0x40000U)
24149 #define CCM_LPCG_AUTHEN_CPULPM_SHIFT             (18U)
24150 /*! CPULPM - CPU Low Power Mode
24151  *  0b1..LPCG is functioning in Low Power Mode
24152  *  0b0..LPCG is not functioning in Low power Mode
24153  */
24154 #define CCM_LPCG_AUTHEN_CPULPM(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK)
24155 
24156 #define CCM_LPCG_AUTHEN_LOCK_MODE_MASK           (0x100000U)
24157 #define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT          (20U)
24158 /*! LOCK_MODE - Lock low power and access mode
24159  *  0b0..MODE is not locked.
24160  *  0b1..MODE is locked.
24161  */
24162 #define CCM_LPCG_AUTHEN_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK)
24163 /*! @} */
24164 
24165 /* The count of CCM_LPCG_AUTHEN */
24166 #define CCM_LPCG_AUTHEN_COUNT                    (138U)
24167 
24168 
24169 /*!
24170  * @}
24171  */ /* end of group CCM_Register_Masks */
24172 
24173 
24174 /* CCM - Peripheral instance base addresses */
24175 /** Peripheral CCM base address */
24176 #define CCM_BASE                                 (0x40CC0000u)
24177 /** Peripheral CCM base pointer */
24178 #define CCM                                      ((CCM_Type *)CCM_BASE)
24179 /** Array initializer of CCM peripheral base addresses */
24180 #define CCM_BASE_ADDRS                           { CCM_BASE }
24181 /** Array initializer of CCM peripheral base pointers */
24182 #define CCM_BASE_PTRS                            { CCM }
24183 
24184 /*!
24185  * @}
24186  */ /* end of group CCM_Peripheral_Access_Layer */
24187 
24188 
24189 /* ----------------------------------------------------------------------------
24190    -- CCM_OBS Peripheral Access Layer
24191    ---------------------------------------------------------------------------- */
24192 
24193 /*!
24194  * @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer
24195  * @{
24196  */
24197 
24198 /** CCM_OBS - Register Layout Typedef */
24199 typedef struct {
24200   struct {                                         /* offset: 0x0, array step: 0x80 */
24201     __IO uint32_t CONTROL;                           /**< Observe control, array offset: 0x0, array step: 0x80 */
24202     __IO uint32_t CONTROL_SET;                       /**< Observe control, array offset: 0x4, array step: 0x80 */
24203     __IO uint32_t CONTROL_CLR;                       /**< Observe control, array offset: 0x8, array step: 0x80 */
24204     __IO uint32_t CONTROL_TOG;                       /**< Observe control, array offset: 0xC, array step: 0x80 */
24205          uint8_t RESERVED_0[16];
24206     __I  uint32_t STATUS0;                           /**< Observe status, array offset: 0x20, array step: 0x80 */
24207          uint8_t RESERVED_1[12];
24208     __IO uint32_t AUTHEN;                            /**< Observe access control, array offset: 0x30, array step: 0x80 */
24209     __IO uint32_t AUTHEN_SET;                        /**< Observe access control, array offset: 0x34, array step: 0x80 */
24210     __IO uint32_t AUTHEN_CLR;                        /**< Observe access control, array offset: 0x38, array step: 0x80 */
24211     __IO uint32_t AUTHEN_TOG;                        /**< Observe access control, array offset: 0x3C, array step: 0x80 */
24212     __I  uint32_t FREQUENCY_CURRENT;                 /**< Current frequency detected, array offset: 0x40, array step: 0x80 */
24213     __I  uint32_t FREQUENCY_MIN;                     /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */
24214     __I  uint32_t FREQUENCY_MAX;                     /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */
24215          uint8_t RESERVED_2[52];
24216   } OBSERVE[6];
24217 } CCM_OBS_Type;
24218 
24219 /* ----------------------------------------------------------------------------
24220    -- CCM_OBS Register Masks
24221    ---------------------------------------------------------------------------- */
24222 
24223 /*!
24224  * @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks
24225  * @{
24226  */
24227 
24228 /*! @name OBSERVE_CONTROL - Observe control */
24229 /*! @{ */
24230 
24231 #define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK      (0x1FFU)
24232 #define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT     (0U)
24233 /*! SELECT - Observe signal selector
24234  */
24235 #define CCM_OBS_OBSERVE_CONTROL_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK)
24236 
24237 #define CCM_OBS_OBSERVE_CONTROL_RAW_MASK         (0x1000U)
24238 #define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT        (12U)
24239 /*! RAW - Observe raw signal
24240  *  0b0..Select divided signal.
24241  *  0b1..Select raw signal.
24242  */
24243 #define CCM_OBS_OBSERVE_CONTROL_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK)
24244 
24245 #define CCM_OBS_OBSERVE_CONTROL_INV_MASK         (0x2000U)
24246 #define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT        (13U)
24247 /*! INV - Invert
24248  *  0b0..Clock phase remain same.
24249  *  0b1..Invert clock phase before measurement or send to IO.
24250  */
24251 #define CCM_OBS_OBSERVE_CONTROL_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK)
24252 
24253 #define CCM_OBS_OBSERVE_CONTROL_RESET_MASK       (0x8000U)
24254 #define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT      (15U)
24255 /*! RESET - Reset observe divider
24256  *  0b0..No reset
24257  *  0b1..Reset observe divider
24258  */
24259 #define CCM_OBS_OBSERVE_CONTROL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK)
24260 
24261 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK      (0xFF0000U)
24262 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT     (16U)
24263 /*! DIVIDE - Divider for observe signal
24264  */
24265 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK)
24266 
24267 #define CCM_OBS_OBSERVE_CONTROL_OFF_MASK         (0x1000000U)
24268 #define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT        (24U)
24269 /*! OFF - Turn off
24270  *  0b0..observe slice is on
24271  *  0b1..observe slice is off
24272  */
24273 #define CCM_OBS_OBSERVE_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK)
24274 /*! @} */
24275 
24276 /* The count of CCM_OBS_OBSERVE_CONTROL */
24277 #define CCM_OBS_OBSERVE_CONTROL_COUNT            (6U)
24278 
24279 /*! @name OBSERVE_CONTROL_SET - Observe control */
24280 /*! @{ */
24281 
24282 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK  (0x1FFU)
24283 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U)
24284 /*! SELECT - Observe signal selector
24285  */
24286 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK)
24287 
24288 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK     (0x1000U)
24289 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT    (12U)
24290 /*! RAW - Observe raw signal
24291  */
24292 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK)
24293 
24294 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK     (0x2000U)
24295 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT    (13U)
24296 /*! INV - Invert
24297  */
24298 #define CCM_OBS_OBSERVE_CONTROL_SET_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK)
24299 
24300 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK   (0x8000U)
24301 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT  (15U)
24302 /*! RESET - Reset observe divider
24303  */
24304 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK)
24305 
24306 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK  (0xFF0000U)
24307 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U)
24308 /*! DIVIDE - Divider for observe signal
24309  */
24310 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK)
24311 
24312 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK     (0x1000000U)
24313 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT    (24U)
24314 /*! OFF - Turn off
24315  */
24316 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK)
24317 /*! @} */
24318 
24319 /* The count of CCM_OBS_OBSERVE_CONTROL_SET */
24320 #define CCM_OBS_OBSERVE_CONTROL_SET_COUNT        (6U)
24321 
24322 /*! @name OBSERVE_CONTROL_CLR - Observe control */
24323 /*! @{ */
24324 
24325 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK  (0x1FFU)
24326 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U)
24327 /*! SELECT - Observe signal selector
24328  */
24329 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK)
24330 
24331 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK     (0x1000U)
24332 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT    (12U)
24333 /*! RAW - Observe raw signal
24334  */
24335 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK)
24336 
24337 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK     (0x2000U)
24338 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT    (13U)
24339 /*! INV - Invert
24340  */
24341 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK)
24342 
24343 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK   (0x8000U)
24344 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT  (15U)
24345 /*! RESET - Reset observe divider
24346  */
24347 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK)
24348 
24349 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK  (0xFF0000U)
24350 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U)
24351 /*! DIVIDE - Divider for observe signal
24352  */
24353 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
24354 
24355 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK     (0x1000000U)
24356 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT    (24U)
24357 /*! OFF - Turn off
24358  */
24359 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK)
24360 /*! @} */
24361 
24362 /* The count of CCM_OBS_OBSERVE_CONTROL_CLR */
24363 #define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT        (6U)
24364 
24365 /*! @name OBSERVE_CONTROL_TOG - Observe control */
24366 /*! @{ */
24367 
24368 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK  (0x1FFU)
24369 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U)
24370 /*! SELECT - Observe signal selector
24371  */
24372 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK)
24373 
24374 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK     (0x1000U)
24375 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT    (12U)
24376 /*! RAW - Observe raw signal
24377  */
24378 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK)
24379 
24380 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK     (0x2000U)
24381 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT    (13U)
24382 /*! INV - Invert
24383  */
24384 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK)
24385 
24386 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK   (0x8000U)
24387 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT  (15U)
24388 /*! RESET - Reset observe divider
24389  */
24390 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK)
24391 
24392 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK  (0xFF0000U)
24393 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U)
24394 /*! DIVIDE - Divider for observe signal
24395  */
24396 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
24397 
24398 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK     (0x1000000U)
24399 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT    (24U)
24400 /*! OFF - Turn off
24401  */
24402 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK)
24403 /*! @} */
24404 
24405 /* The count of CCM_OBS_OBSERVE_CONTROL_TOG */
24406 #define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT        (6U)
24407 
24408 /*! @name OBSERVE_STATUS0 - Observe status */
24409 /*! @{ */
24410 
24411 #define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK      (0x1FFU)
24412 #define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT     (0U)
24413 /*! SELECT - Select value
24414  */
24415 #define CCM_OBS_OBSERVE_STATUS0_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK)
24416 
24417 #define CCM_OBS_OBSERVE_STATUS0_RAW_MASK         (0x1000U)
24418 #define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT        (12U)
24419 /*! RAW - Observe raw signal
24420  *  0b0..Divided signal is selected
24421  *  0b1..Raw signal is selected
24422  */
24423 #define CCM_OBS_OBSERVE_STATUS0_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK)
24424 
24425 #define CCM_OBS_OBSERVE_STATUS0_INV_MASK         (0x2000U)
24426 #define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT        (13U)
24427 /*! INV - Polarity of the observe target
24428  *  0b1..Polarity of the observe target is inverted
24429  *  0b0..Polarity is not inverted
24430  */
24431 #define CCM_OBS_OBSERVE_STATUS0_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK)
24432 
24433 #define CCM_OBS_OBSERVE_STATUS0_RESET_MASK       (0x8000U)
24434 #define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT      (15U)
24435 /*! RESET - Reset state
24436  *  0b1..Observe divider is in reset state
24437  *  0b0..Observe divider is not in reset state
24438  */
24439 #define CCM_OBS_OBSERVE_STATUS0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK)
24440 
24441 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK      (0xFF0000U)
24442 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT     (16U)
24443 /*! DIVIDE - Divide value status. The clock will be divided by DIVIDE + 1.
24444  */
24445 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK)
24446 
24447 #define CCM_OBS_OBSERVE_STATUS0_OFF_MASK         (0x1000000U)
24448 #define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT        (24U)
24449 /*! OFF - Turn off slice
24450  *  0b0..observe slice is on
24451  *  0b1..observe slice is off
24452  */
24453 #define CCM_OBS_OBSERVE_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK)
24454 /*! @} */
24455 
24456 /* The count of CCM_OBS_OBSERVE_STATUS0 */
24457 #define CCM_OBS_OBSERVE_STATUS0_COUNT            (6U)
24458 
24459 /*! @name OBSERVE_AUTHEN - Observe access control */
24460 /*! @{ */
24461 
24462 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK      (0x1U)
24463 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT     (0U)
24464 /*! TZ_USER - User access
24465  *  0b1..Clock can be changed in user mode.
24466  *  0b0..Clock cannot be changed in user mode.
24467  */
24468 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK)
24469 
24470 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK        (0x2U)
24471 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT       (1U)
24472 /*! TZ_NS - Non-secure access
24473  *  0b0..Cannot be changed in Non-secure mode.
24474  *  0b1..Can be changed in Non-secure mode.
24475  */
24476 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK)
24477 
24478 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK      (0x10U)
24479 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT     (4U)
24480 /*! LOCK_TZ - Lock truszone setting
24481  *  0b0..Trustzone setting is not locked.
24482  *  0b1..Trustzone setting is locked.
24483  */
24484 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK)
24485 
24486 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK   (0xF00U)
24487 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT  (8U)
24488 /*! WHITE_LIST - White list
24489  *  0b1111..All domain can change.
24490  *  0b0010..Domain 1 can change.
24491  *  0b0011..Domain 0 and domain 1 can change.
24492  *  0b0000..No domain can change.
24493  *  0b0100..Domain 2 can change.
24494  *  0b0001..Domain 0 can change.
24495  */
24496 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK)
24497 
24498 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK    (0x1000U)
24499 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT   (12U)
24500 /*! LOCK_LIST - Lock white list
24501  *  0b0..White list is not locked.
24502  *  0b1..White list is locked.
24503  */
24504 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK)
24505 
24506 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
24507 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U)
24508 /*! DOMAIN_MODE - Low power and access control by domain
24509  *  0b1..Clock works in domain mode.
24510  *  0b0..Clock does not work in domain mode.
24511  */
24512 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK)
24513 
24514 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK    (0x100000U)
24515 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT   (20U)
24516 /*! LOCK_MODE - Lock low power and access mode
24517  *  0b0..MODE is not locked.
24518  *  0b1..MODE is locked.
24519  */
24520 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK)
24521 /*! @} */
24522 
24523 /* The count of CCM_OBS_OBSERVE_AUTHEN */
24524 #define CCM_OBS_OBSERVE_AUTHEN_COUNT             (6U)
24525 
24526 /*! @name OBSERVE_AUTHEN_SET - Observe access control */
24527 /*! @{ */
24528 
24529 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK  (0x1U)
24530 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U)
24531 /*! TZ_USER - User access
24532  */
24533 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
24534 
24535 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK    (0x2U)
24536 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT   (1U)
24537 /*! TZ_NS - Non-secure access
24538  */
24539 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
24540 
24541 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
24542 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
24543 /*! LOCK_TZ - Lock truszone setting
24544  */
24545 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
24546 
24547 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
24548 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
24549 /*! WHITE_LIST - White list
24550  */
24551 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
24552 
24553 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
24554 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
24555 /*! LOCK_LIST - Lock white list
24556  */
24557 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
24558 
24559 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
24560 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
24561 /*! DOMAIN_MODE - Low power and access control by domain
24562  */
24563 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK)
24564 
24565 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
24566 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
24567 /*! LOCK_MODE - Lock low power and access mode
24568  */
24569 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK)
24570 /*! @} */
24571 
24572 /* The count of CCM_OBS_OBSERVE_AUTHEN_SET */
24573 #define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT         (6U)
24574 
24575 /*! @name OBSERVE_AUTHEN_CLR - Observe access control */
24576 /*! @{ */
24577 
24578 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
24579 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U)
24580 /*! TZ_USER - User access
24581  */
24582 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
24583 
24584 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
24585 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
24586 /*! TZ_NS - Non-secure access
24587  */
24588 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
24589 
24590 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
24591 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
24592 /*! LOCK_TZ - Lock truszone setting
24593  */
24594 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
24595 
24596 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
24597 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
24598 /*! WHITE_LIST - White list
24599  */
24600 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
24601 
24602 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
24603 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
24604 /*! LOCK_LIST - Lock white list
24605  */
24606 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
24607 
24608 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
24609 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
24610 /*! DOMAIN_MODE - Low power and access control by domain
24611  */
24612 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK)
24613 
24614 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
24615 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
24616 /*! LOCK_MODE - Lock low power and access mode
24617  */
24618 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK)
24619 /*! @} */
24620 
24621 /* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */
24622 #define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT         (6U)
24623 
24624 /*! @name OBSERVE_AUTHEN_TOG - Observe access control */
24625 /*! @{ */
24626 
24627 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
24628 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U)
24629 /*! TZ_USER - User access
24630  */
24631 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
24632 
24633 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
24634 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
24635 /*! TZ_NS - Non-secure access
24636  */
24637 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
24638 
24639 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
24640 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
24641 /*! LOCK_TZ - Lock truszone setting
24642  */
24643 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
24644 
24645 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
24646 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
24647 /*! WHITE_LIST - White list
24648  */
24649 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
24650 
24651 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
24652 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
24653 /*! LOCK_LIST - Lock white list
24654  */
24655 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
24656 
24657 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
24658 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
24659 /*! DOMAIN_MODE - Low power and access control by domain
24660  */
24661 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK)
24662 
24663 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
24664 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
24665 /*! LOCK_MODE - Lock low power and access mode
24666  */
24667 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK)
24668 /*! @} */
24669 
24670 /* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */
24671 #define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT         (6U)
24672 
24673 /*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */
24674 /*! @{ */
24675 
24676 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
24677 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
24678 /*! FREQUENCY - Frequency
24679  */
24680 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
24681 /*! @} */
24682 
24683 /* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */
24684 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT  (6U)
24685 
24686 /*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */
24687 /*! @{ */
24688 
24689 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
24690 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
24691 /*! FREQUENCY - Frequency
24692  */
24693 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
24694 /*! @} */
24695 
24696 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */
24697 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT      (6U)
24698 
24699 /*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */
24700 /*! @{ */
24701 
24702 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
24703 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
24704 /*! FREQUENCY - Frequency
24705  */
24706 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
24707 /*! @} */
24708 
24709 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */
24710 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT      (6U)
24711 
24712 
24713 /*!
24714  * @}
24715  */ /* end of group CCM_OBS_Register_Masks */
24716 
24717 
24718 /* CCM_OBS - Peripheral instance base addresses */
24719 /** Peripheral CCM_OBS base address */
24720 #define CCM_OBS_BASE                             (0x40150000u)
24721 /** Peripheral CCM_OBS base pointer */
24722 #define CCM_OBS                                  ((CCM_OBS_Type *)CCM_OBS_BASE)
24723 /** Array initializer of CCM_OBS peripheral base addresses */
24724 #define CCM_OBS_BASE_ADDRS                       { CCM_OBS_BASE }
24725 /** Array initializer of CCM_OBS peripheral base pointers */
24726 #define CCM_OBS_BASE_PTRS                        { CCM_OBS }
24727 
24728 /*!
24729  * @}
24730  */ /* end of group CCM_OBS_Peripheral_Access_Layer */
24731 
24732 
24733 /* ----------------------------------------------------------------------------
24734    -- CDOG Peripheral Access Layer
24735    ---------------------------------------------------------------------------- */
24736 
24737 /*!
24738  * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
24739  * @{
24740  */
24741 
24742 /** CDOG - Register Layout Typedef */
24743 typedef struct {
24744   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
24745   __IO uint32_t RELOAD;                            /**< Instruction Timer reload, offset: 0x4 */
24746   __IO uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer, offset: 0x8 */
24747   __O  uint32_t SECURE_COUNTER;                    /**< Secure Counter, offset: 0xC */
24748   __I  uint32_t STATUS;                            /**< Status 1, offset: 0x10 */
24749   __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x14 */
24750   __IO uint32_t FLAGS;                             /**< Flags, offset: 0x18 */
24751   __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage, offset: 0x1C */
24752   __O  uint32_t START;                             /**< START Command, offset: 0x20 */
24753   __O  uint32_t STOP;                              /**< STOP Command, offset: 0x24 */
24754   __O  uint32_t RESTART;                           /**< RESTART Command, offset: 0x28 */
24755   __O  uint32_t ADD;                               /**< ADD Command, offset: 0x2C */
24756   __O  uint32_t ADD1;                              /**< ADD1 Command, offset: 0x30 */
24757   __O  uint32_t ADD16;                             /**< ADD16 Command, offset: 0x34 */
24758   __O  uint32_t ADD256;                            /**< ADD256 Command, offset: 0x38 */
24759   __O  uint32_t SUB;                               /**< SUB Command, offset: 0x3C */
24760   __O  uint32_t SUB1;                              /**< SUB1 Command, offset: 0x40 */
24761   __O  uint32_t SUB16;                             /**< SUB16 Command, offset: 0x44 */
24762   __O  uint32_t SUB256;                            /**< SUB256 Command, offset: 0x48 */
24763 } CDOG_Type;
24764 
24765 /* ----------------------------------------------------------------------------
24766    -- CDOG Register Masks
24767    ---------------------------------------------------------------------------- */
24768 
24769 /*!
24770  * @addtogroup CDOG_Register_Masks CDOG Register Masks
24771  * @{
24772  */
24773 
24774 /*! @name CONTROL - Control */
24775 /*! @{ */
24776 
24777 #define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
24778 #define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
24779 /*! LOCK_CTRL - Lock control
24780  *  0b01..Locked
24781  *  0b10..Unlocked
24782  */
24783 #define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
24784 
24785 #define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
24786 #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
24787 /*! TIMEOUT_CTRL - TIMEOUT fault control
24788  *  0b100..Disable both reset and interrupt
24789  *  0b001..Enable reset
24790  *  0b010..Enable interrupt
24791  */
24792 #define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
24793 
24794 #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
24795 #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
24796 /*! MISCOMPARE_CTRL - MISCOMPARE fault control
24797  *  0b100..Disable both reset and interrupt
24798  *  0b001..Enable reset
24799  *  0b010..Enable interrupt
24800  */
24801 #define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
24802 
24803 #define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
24804 #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
24805 /*! SEQUENCE_CTRL - SEQUENCE fault control
24806  *  0b001..Enable reset
24807  *  0b010..Enable interrupt
24808  *  0b100..Disable both reset and interrupt
24809  */
24810 #define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
24811 
24812 #define CDOG_CONTROL_CONTROL_CTRL_MASK           (0x3800U)
24813 #define CDOG_CONTROL_CONTROL_CTRL_SHIFT          (11U)
24814 /*! CONTROL_CTRL - CONTROL fault control
24815  *  0b001..Enable reset
24816  *  0b100..Disable reset
24817  */
24818 #define CDOG_CONTROL_CONTROL_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
24819 
24820 #define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
24821 #define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
24822 /*! STATE_CTRL - STATE fault control
24823  *  0b001..Enable reset
24824  *  0b010..Enable interrupt
24825  *  0b100..Disable both reset and interrupt
24826  */
24827 #define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
24828 
24829 #define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
24830 #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
24831 /*! ADDRESS_CTRL - ADDRESS fault control
24832  *  0b001..Enable reset
24833  *  0b010..Enable interrupt
24834  *  0b100..Disable both reset and interrupt
24835  */
24836 #define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
24837 
24838 #define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
24839 #define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
24840 /*! IRQ_PAUSE - IRQ pause control
24841  *  0b01..Keep the timer running
24842  *  0b10..Stop the timer
24843  */
24844 #define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
24845 
24846 #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
24847 #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
24848 /*! DEBUG_HALT_CTRL - DEBUG_HALT control
24849  *  0b01..Keep the timer running
24850  *  0b10..Stop the timer
24851  */
24852 #define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
24853 /*! @} */
24854 
24855 /*! @name RELOAD - Instruction Timer reload */
24856 /*! @{ */
24857 
24858 #define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
24859 #define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
24860 /*! RLOAD - Instruction Timer reload value
24861  */
24862 #define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
24863 /*! @} */
24864 
24865 /*! @name INSTRUCTION_TIMER - Instruction Timer */
24866 /*! @{ */
24867 
24868 #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
24869 #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
24870 /*! INSTIM - Current value of the Instruction Timer
24871  */
24872 #define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
24873 /*! @} */
24874 
24875 /*! @name SECURE_COUNTER - Secure Counter */
24876 /*! @{ */
24877 
24878 #define CDOG_SECURE_COUNTER_SECCNT_MASK          (0xFFFFFFFFU)
24879 #define CDOG_SECURE_COUNTER_SECCNT_SHIFT         (0U)
24880 /*! SECCNT - Secure Counter
24881  */
24882 #define CDOG_SECURE_COUNTER_SECCNT(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
24883 /*! @} */
24884 
24885 /*! @name STATUS - Status 1 */
24886 /*! @{ */
24887 
24888 #define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
24889 #define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
24890 /*! NUMTOF - Number of TIMEOUT faults since the last POR
24891  */
24892 #define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
24893 
24894 #define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
24895 #define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
24896 /*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR
24897  */
24898 #define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
24899 
24900 #define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
24901 #define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
24902 /*! NUMILSEQF - Number of SEQUENCE faults since the last POR
24903  */
24904 #define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
24905 
24906 #define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
24907 #define CDOG_STATUS_CURST_SHIFT                  (28U)
24908 /*! CURST - Current State
24909  */
24910 #define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
24911 /*! @} */
24912 
24913 /*! @name STATUS2 - Status 2 */
24914 /*! @{ */
24915 
24916 #define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
24917 #define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
24918 /*! NUMCNTF - Number of CONTROL faults since the last POR
24919  */
24920 #define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
24921 
24922 #define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
24923 #define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
24924 /*! NUMILLSTF - Number of STATE faults since the last POR
24925  */
24926 #define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
24927 
24928 #define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
24929 #define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
24930 /*! NUMILLA - Number of ADDRESS faults since the last POR
24931  */
24932 #define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
24933 /*! @} */
24934 
24935 /*! @name FLAGS - Flags */
24936 /*! @{ */
24937 
24938 #define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
24939 #define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
24940 /*! TO_FLAG - TIMEOUT fault flag
24941  *  0b0..A TIMEOUT fault has not occurred
24942  *  0b1..A TIMEOUT fault has occurred
24943  */
24944 #define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
24945 
24946 #define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
24947 #define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
24948 /*! MISCOM_FLAG - MISCOMPARE fault flag
24949  *  0b0..A MISCOMPARE fault has not occurred
24950  *  0b1..A MISCOMPARE fault has occurred
24951  */
24952 #define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
24953 
24954 #define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
24955 #define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
24956 /*! SEQ_FLAG - SEQUENCE fault flag
24957  *  0b0..A SEQUENCE fault has not occurred
24958  *  0b1..A SEQUENCE fault has occurred
24959  */
24960 #define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
24961 
24962 #define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
24963 #define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
24964 /*! CNT_FLAG - CONTROL fault flag
24965  *  0b0..A CONTROL fault has not occurred
24966  *  0b1..A CONTROL fault has occurred
24967  */
24968 #define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
24969 
24970 #define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
24971 #define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
24972 /*! STATE_FLAG - STATE fault flag
24973  *  0b0..A STATE fault has not occurred
24974  *  0b1..A STATE fault has occurred
24975  */
24976 #define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
24977 
24978 #define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
24979 #define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
24980 /*! ADDR_FLAG - ADDRESS fault flag
24981  *  0b0..An ADDRESS fault has not occurred
24982  *  0b1..An ADDRESS fault has occurred
24983  */
24984 #define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
24985 
24986 #define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
24987 #define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
24988 /*! POR_FLAG - Power-on reset flag
24989  *  0b0..A Power-on reset event has not occurred
24990  *  0b1..A Power-on reset event has occurred
24991  */
24992 #define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
24993 /*! @} */
24994 
24995 /*! @name PERSISTENT - Persistent Data Storage */
24996 /*! @{ */
24997 
24998 #define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
24999 #define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
25000 /*! PERSIS - Persistent Storage
25001  */
25002 #define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
25003 /*! @} */
25004 
25005 /*! @name START - START Command */
25006 /*! @{ */
25007 
25008 #define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
25009 #define CDOG_START_STRT_SHIFT                    (0U)
25010 /*! STRT - Start command
25011  */
25012 #define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
25013 /*! @} */
25014 
25015 /*! @name STOP - STOP Command */
25016 /*! @{ */
25017 
25018 #define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
25019 #define CDOG_STOP_STP_SHIFT                      (0U)
25020 /*! STP - Stop command
25021  */
25022 #define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
25023 /*! @} */
25024 
25025 /*! @name RESTART - RESTART Command */
25026 /*! @{ */
25027 
25028 #define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
25029 #define CDOG_RESTART_RSTRT_SHIFT                 (0U)
25030 /*! RSTRT - Restart command
25031  */
25032 #define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
25033 /*! @} */
25034 
25035 /*! @name ADD - ADD Command */
25036 /*! @{ */
25037 
25038 #define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
25039 #define CDOG_ADD_AD_SHIFT                        (0U)
25040 /*! AD - ADD Write Value
25041  */
25042 #define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
25043 /*! @} */
25044 
25045 /*! @name ADD1 - ADD1 Command */
25046 /*! @{ */
25047 
25048 #define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
25049 #define CDOG_ADD1_AD1_SHIFT                      (0U)
25050 /*! AD1 - ADD 1
25051  */
25052 #define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
25053 /*! @} */
25054 
25055 /*! @name ADD16 - ADD16 Command */
25056 /*! @{ */
25057 
25058 #define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
25059 #define CDOG_ADD16_AD16_SHIFT                    (0U)
25060 /*! AD16 - ADD 16
25061  */
25062 #define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
25063 /*! @} */
25064 
25065 /*! @name ADD256 - ADD256 Command */
25066 /*! @{ */
25067 
25068 #define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
25069 #define CDOG_ADD256_AD256_SHIFT                  (0U)
25070 /*! AD256 - ADD 256
25071  */
25072 #define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
25073 /*! @} */
25074 
25075 /*! @name SUB - SUB Command */
25076 /*! @{ */
25077 
25078 #define CDOG_SUB_S0B_MASK                        (0xFFFFFFFFU)
25079 #define CDOG_SUB_S0B_SHIFT                       (0U)
25080 /*! S0B - Subtract Write Value
25081  */
25082 #define CDOG_SUB_S0B(x)                          (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
25083 /*! @} */
25084 
25085 /*! @name SUB1 - SUB1 Command */
25086 /*! @{ */
25087 
25088 #define CDOG_SUB1_S1B_MASK                       (0xFFFFFFFFU)
25089 #define CDOG_SUB1_S1B_SHIFT                      (0U)
25090 /*! S1B - Subtract 1
25091  */
25092 #define CDOG_SUB1_S1B(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
25093 /*! @} */
25094 
25095 /*! @name SUB16 - SUB16 Command */
25096 /*! @{ */
25097 
25098 #define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
25099 #define CDOG_SUB16_SB16_SHIFT                    (0U)
25100 /*! SB16 - Subtract 16
25101  */
25102 #define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
25103 /*! @} */
25104 
25105 /*! @name SUB256 - SUB256 Command */
25106 /*! @{ */
25107 
25108 #define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
25109 #define CDOG_SUB256_SB256_SHIFT                  (0U)
25110 /*! SB256 - Subtract 256
25111  */
25112 #define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
25113 /*! @} */
25114 
25115 
25116 /*!
25117  * @}
25118  */ /* end of group CDOG_Register_Masks */
25119 
25120 
25121 /* CDOG - Peripheral instance base addresses */
25122 /** Peripheral CDOG base address */
25123 #define CDOG_BASE                                (0x41900000u)
25124 /** Peripheral CDOG base pointer */
25125 #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
25126 /** Array initializer of CDOG peripheral base addresses */
25127 #define CDOG_BASE_ADDRS                          { CDOG_BASE }
25128 /** Array initializer of CDOG peripheral base pointers */
25129 #define CDOG_BASE_PTRS                           { CDOG }
25130 
25131 /*!
25132  * @}
25133  */ /* end of group CDOG_Peripheral_Access_Layer */
25134 
25135 
25136 /* ----------------------------------------------------------------------------
25137    -- CMP Peripheral Access Layer
25138    ---------------------------------------------------------------------------- */
25139 
25140 /*!
25141  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
25142  * @{
25143  */
25144 
25145 /** CMP - Register Layout Typedef */
25146 typedef struct {
25147   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
25148   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
25149   __IO uint32_t C0;                                /**< CMP Control Register 0, offset: 0x8 */
25150   __IO uint32_t C1;                                /**< CMP Control Register 1, offset: 0xC */
25151   __IO uint32_t C2;                                /**< CMP Control Register 2, offset: 0x10 */
25152   __IO uint32_t C3;                                /**< CMP Control Register 3, offset: 0x14 */
25153 } CMP_Type;
25154 
25155 /* ----------------------------------------------------------------------------
25156    -- CMP Register Masks
25157    ---------------------------------------------------------------------------- */
25158 
25159 /*!
25160  * @addtogroup CMP_Register_Masks CMP Register Masks
25161  * @{
25162  */
25163 
25164 /*! @name VERID - Version ID Register */
25165 /*! @{ */
25166 
25167 #define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
25168 #define CMP_VERID_FEATURE_SHIFT                  (0U)
25169 /*! FEATURE - Feature Specification Number. This read only filed returns the feature set number.
25170  */
25171 #define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
25172 
25173 #define CMP_VERID_MINOR_MASK                     (0xFF0000U)
25174 #define CMP_VERID_MINOR_SHIFT                    (16U)
25175 /*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.
25176  */
25177 #define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
25178 
25179 #define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
25180 #define CMP_VERID_MAJOR_SHIFT                    (24U)
25181 /*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification.
25182  */
25183 #define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
25184 /*! @} */
25185 
25186 /*! @name PARAM - Parameter Register */
25187 /*! @{ */
25188 
25189 #define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
25190 #define CMP_PARAM_PARAM_SHIFT                    (0U)
25191 /*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.
25192  */
25193 #define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
25194 /*! @} */
25195 
25196 /*! @name C0 - CMP Control Register 0 */
25197 /*! @{ */
25198 
25199 #define CMP_C0_HYSTCTR_MASK                      (0x3U)
25200 #define CMP_C0_HYSTCTR_SHIFT                     (0U)
25201 /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
25202  *  0b00..The hard block output has level 0 hysteresis internally.
25203  *  0b01..The hard block output has level 1 hysteresis internally.
25204  *  0b10..The hard block output has level 2 hysteresis internally.
25205  *  0b11..The hard block output has level 3 hysteresis internally.
25206  */
25207 #define CMP_C0_HYSTCTR(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
25208 
25209 #define CMP_C0_FILTER_CNT_MASK                   (0x70U)
25210 #define CMP_C0_FILTER_CNT_SHIFT                  (4U)
25211 /*! FILTER_CNT - Filter Sample Count
25212  *  0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
25213  *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
25214  *  0b010..2 consecutive samples must agree.
25215  *  0b011..3 consecutive samples must agree.
25216  *  0b100..4 consecutive samples must agree.
25217  *  0b101..5 consecutive samples must agree.
25218  *  0b110..6 consecutive samples must agree.
25219  *  0b111..7 consecutive samples must agree.
25220  */
25221 #define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
25222 
25223 #define CMP_C0_EN_MASK                           (0x100U)
25224 #define CMP_C0_EN_SHIFT                          (8U)
25225 /*! EN - Comparator Module Enable
25226  *  0b0..Analog Comparator is disabled.
25227  *  0b1..Analog Comparator is enabled.
25228  */
25229 #define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
25230 
25231 #define CMP_C0_OPE_MASK                          (0x200U)
25232 #define CMP_C0_OPE_SHIFT                         (9U)
25233 /*! OPE - Comparator Output Pin Enable
25234  *  0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
25235  *  0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
25236  */
25237 #define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
25238 
25239 #define CMP_C0_COS_MASK                          (0x400U)
25240 #define CMP_C0_COS_SHIFT                         (10U)
25241 /*! COS - Comparator Output Select
25242  *  0b0..Set CMPO to equal COUT (filtered comparator output).
25243  *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
25244  */
25245 #define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
25246 
25247 #define CMP_C0_INVT_MASK                         (0x800U)
25248 #define CMP_C0_INVT_SHIFT                        (11U)
25249 /*! INVT - Comparator invert
25250  *  0b0..Does not invert the comparator output.
25251  *  0b1..Inverts the comparator output.
25252  */
25253 #define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
25254 
25255 #define CMP_C0_PMODE_MASK                        (0x1000U)
25256 #define CMP_C0_PMODE_SHIFT                       (12U)
25257 /*! PMODE - Power Mode Select
25258  *  0b0..Low Speed (LS) comparison mode is selected.
25259  *  0b1..High Speed (HS) comparison mode is selected.
25260  */
25261 #define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
25262 
25263 #define CMP_C0_WE_MASK                           (0x4000U)
25264 #define CMP_C0_WE_SHIFT                          (14U)
25265 /*! WE - Windowing Enable
25266  *  0b0..Windowing mode is not selected.
25267  *  0b1..Windowing mode is selected.
25268  */
25269 #define CMP_C0_WE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
25270 
25271 #define CMP_C0_SE_MASK                           (0x8000U)
25272 #define CMP_C0_SE_SHIFT                          (15U)
25273 /*! SE - Sample Enable
25274  *  0b0..Sampling mode is not selected.
25275  *  0b1..Sampling mode is selected.
25276  */
25277 #define CMP_C0_SE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
25278 
25279 #define CMP_C0_FPR_MASK                          (0xFF0000U)
25280 #define CMP_C0_FPR_SHIFT                         (16U)
25281 /*! FPR - Filter Sample Period
25282  */
25283 #define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
25284 
25285 #define CMP_C0_COUT_MASK                         (0x1000000U)
25286 #define CMP_C0_COUT_SHIFT                        (24U)
25287 /*! COUT - Analog Comparator Output
25288  */
25289 #define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
25290 
25291 #define CMP_C0_CFF_MASK                          (0x2000000U)
25292 #define CMP_C0_CFF_SHIFT                         (25U)
25293 /*! CFF - Analog Comparator Flag Falling
25294  *  0b0..A falling edge has not been detected on COUT.
25295  *  0b1..A falling edge on COUT has occurred.
25296  */
25297 #define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
25298 
25299 #define CMP_C0_CFR_MASK                          (0x4000000U)
25300 #define CMP_C0_CFR_SHIFT                         (26U)
25301 /*! CFR - Analog Comparator Flag Rising
25302  *  0b0..A rising edge has not been detected on COUT.
25303  *  0b1..A rising edge on COUT has occurred.
25304  */
25305 #define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
25306 
25307 #define CMP_C0_IEF_MASK                          (0x8000000U)
25308 #define CMP_C0_IEF_SHIFT                         (27U)
25309 /*! IEF - Comparator Interrupt Enable Falling
25310  *  0b0..Interrupt is disabled.
25311  *  0b1..Interrupt is enabled.
25312  */
25313 #define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
25314 
25315 #define CMP_C0_IER_MASK                          (0x10000000U)
25316 #define CMP_C0_IER_SHIFT                         (28U)
25317 /*! IER - Comparator Interrupt Enable Rising
25318  *  0b0..Interrupt is disabled.
25319  *  0b1..Interrupt is enabled.
25320  */
25321 #define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
25322 
25323 #define CMP_C0_DMAEN_MASK                        (0x40000000U)
25324 #define CMP_C0_DMAEN_SHIFT                       (30U)
25325 /*! DMAEN - DMA Enable
25326  *  0b0..DMA is disabled.
25327  *  0b1..DMA is enabled.
25328  */
25329 #define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
25330 
25331 #define CMP_C0_LINKEN_MASK                       (0x80000000U)
25332 #define CMP_C0_LINKEN_SHIFT                      (31U)
25333 /*! LINKEN - CMP to DAC link enable.
25334  *  0b0..CMP to DAC link is disabled
25335  *  0b1..CMP to DAC link is enabled.
25336  */
25337 #define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
25338 /*! @} */
25339 
25340 /*! @name C1 - CMP Control Register 1 */
25341 /*! @{ */
25342 
25343 #define CMP_C1_VOSEL_MASK                        (0xFFU)
25344 #define CMP_C1_VOSEL_SHIFT                       (0U)
25345 /*! VOSEL - DAC Output Voltage Select
25346  */
25347 #define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
25348 
25349 #define CMP_C1_DMODE_MASK                        (0x100U)
25350 #define CMP_C1_DMODE_SHIFT                       (8U)
25351 /*! DMODE - DAC Mode Selection
25352  *  0b0..DAC is selected to work in low speed and low power mode.
25353  *  0b1..DAC is selected to work in high speed high power mode.
25354  */
25355 #define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
25356 
25357 #define CMP_C1_VRSEL_MASK                        (0x200U)
25358 #define CMP_C1_VRSEL_SHIFT                       (9U)
25359 /*! VRSEL - Supply Voltage Reference Source Select
25360  *  0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
25361  *  0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
25362  */
25363 #define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
25364 
25365 #define CMP_C1_DACEN_MASK                        (0x400U)
25366 #define CMP_C1_DACEN_SHIFT                       (10U)
25367 /*! DACEN - DAC Enable
25368  *  0b0..DAC is disabled.
25369  *  0b1..DAC is enabled.
25370  */
25371 #define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
25372 
25373 #define CMP_C1_CHN0_MASK                         (0x10000U)
25374 #define CMP_C1_CHN0_SHIFT                        (16U)
25375 /*! CHN0 - Channel 0 input enable
25376  */
25377 #define CMP_C1_CHN0(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
25378 
25379 #define CMP_C1_CHN1_MASK                         (0x20000U)
25380 #define CMP_C1_CHN1_SHIFT                        (17U)
25381 /*! CHN1 - Channel 1 input enable
25382  */
25383 #define CMP_C1_CHN1(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
25384 
25385 #define CMP_C1_CHN2_MASK                         (0x40000U)
25386 #define CMP_C1_CHN2_SHIFT                        (18U)
25387 /*! CHN2 - Channel 2 input enable
25388  */
25389 #define CMP_C1_CHN2(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
25390 
25391 #define CMP_C1_CHN3_MASK                         (0x80000U)
25392 #define CMP_C1_CHN3_SHIFT                        (19U)
25393 /*! CHN3 - Channel 3 input enable
25394  */
25395 #define CMP_C1_CHN3(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
25396 
25397 #define CMP_C1_CHN4_MASK                         (0x100000U)
25398 #define CMP_C1_CHN4_SHIFT                        (20U)
25399 /*! CHN4 - Channel 4 input enable
25400  */
25401 #define CMP_C1_CHN4(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
25402 
25403 #define CMP_C1_CHN5_MASK                         (0x200000U)
25404 #define CMP_C1_CHN5_SHIFT                        (21U)
25405 /*! CHN5 - Channel 5 input enable
25406  */
25407 #define CMP_C1_CHN5(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
25408 
25409 #define CMP_C1_MSEL_MASK                         (0x7000000U)
25410 #define CMP_C1_MSEL_SHIFT                        (24U)
25411 /*! MSEL - Minus Input MUX Control
25412  *  0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
25413  *  0b001..External Input 1 for Minus Channel -- Reference Input 0
25414  *  0b010..External Input 2 for Minus Channel -- Reference Input 1
25415  *  0b011..External Input 3 for Minus Channel -- Reference Input 2
25416  *  0b100..External Input 4 for Minus Channel -- Reference Input 3
25417  *  0b101..External Input 5 for Minus Channel -- Reference Input 4
25418  *  0b110..External Input 6 for Minus Channel -- Reference Input 5
25419  *  0b111..Internal 8b DAC output
25420  */
25421 #define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
25422 
25423 #define CMP_C1_PSEL_MASK                         (0x70000000U)
25424 #define CMP_C1_PSEL_SHIFT                        (28U)
25425 /*! PSEL - Plus Input MUX Control
25426  *  0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
25427  *  0b001..External Input 1 for Plus Channel -- Reference Input 0
25428  *  0b010..External Input 2 for Plus Channel -- Reference Input 1
25429  *  0b011..External Input 3 for Plus Channel -- Reference Input 2
25430  *  0b100..External Input 4 for Plus Channel -- Reference Input 3
25431  *  0b101..External Input 5 for Plus Channel -- Reference Input 4
25432  *  0b110..External Input 6 for Plus Channel -- Reference Input 5
25433  *  0b111..Internal 8b DAC output
25434  */
25435 #define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
25436 /*! @} */
25437 
25438 /*! @name C2 - CMP Control Register 2 */
25439 /*! @{ */
25440 
25441 #define CMP_C2_ACOn_MASK                         (0x3FU)
25442 #define CMP_C2_ACOn_SHIFT                        (0U)
25443 /*! ACOn - ACOn
25444  */
25445 #define CMP_C2_ACOn(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
25446 
25447 #define CMP_C2_INITMOD_MASK                      (0x3F00U)
25448 #define CMP_C2_INITMOD_SHIFT                     (8U)
25449 /*! INITMOD - Comparator and DAC initialization delay modulus.
25450  */
25451 #define CMP_C2_INITMOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
25452 
25453 #define CMP_C2_NSAM_MASK                         (0xC000U)
25454 #define CMP_C2_NSAM_SHIFT                        (14U)
25455 /*! NSAM - Number of sample clocks
25456  *  0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
25457  *  0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
25458  *  0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
25459  *  0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
25460  */
25461 #define CMP_C2_NSAM(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
25462 
25463 #define CMP_C2_CH0F_MASK                         (0x10000U)
25464 #define CMP_C2_CH0F_SHIFT                        (16U)
25465 /*! CH0F - CH0F
25466  */
25467 #define CMP_C2_CH0F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
25468 
25469 #define CMP_C2_CH1F_MASK                         (0x20000U)
25470 #define CMP_C2_CH1F_SHIFT                        (17U)
25471 /*! CH1F - CH1F
25472  */
25473 #define CMP_C2_CH1F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
25474 
25475 #define CMP_C2_CH2F_MASK                         (0x40000U)
25476 #define CMP_C2_CH2F_SHIFT                        (18U)
25477 /*! CH2F - CH2F
25478  */
25479 #define CMP_C2_CH2F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
25480 
25481 #define CMP_C2_CH3F_MASK                         (0x80000U)
25482 #define CMP_C2_CH3F_SHIFT                        (19U)
25483 /*! CH3F - CH3F
25484  */
25485 #define CMP_C2_CH3F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
25486 
25487 #define CMP_C2_CH4F_MASK                         (0x100000U)
25488 #define CMP_C2_CH4F_SHIFT                        (20U)
25489 /*! CH4F - CH4F
25490  */
25491 #define CMP_C2_CH4F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
25492 
25493 #define CMP_C2_CH5F_MASK                         (0x200000U)
25494 #define CMP_C2_CH5F_SHIFT                        (21U)
25495 /*! CH5F - CH5F
25496  */
25497 #define CMP_C2_CH5F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
25498 
25499 #define CMP_C2_FXMXCH_MASK                       (0xE000000U)
25500 #define CMP_C2_FXMXCH_SHIFT                      (25U)
25501 /*! FXMXCH - Fixed channel selection
25502  *  0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
25503  *  0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
25504  *  0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
25505  *  0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
25506  *  0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
25507  *  0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
25508  *  0b110..Reserved.
25509  *  0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
25510  */
25511 #define CMP_C2_FXMXCH(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
25512 
25513 #define CMP_C2_FXMP_MASK                         (0x20000000U)
25514 #define CMP_C2_FXMP_SHIFT                        (29U)
25515 /*! FXMP - Fixed MUX Port
25516  *  0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
25517  *  0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
25518  */
25519 #define CMP_C2_FXMP(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
25520 
25521 #define CMP_C2_RRIE_MASK                         (0x40000000U)
25522 #define CMP_C2_RRIE_SHIFT                        (30U)
25523 /*! RRIE - Round-Robin interrupt enable
25524  *  0b0..The round-robin interrupt is disabled.
25525  *  0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
25526  */
25527 #define CMP_C2_RRIE(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
25528 /*! @} */
25529 
25530 /*! @name C3 - CMP Control Register 3 */
25531 /*! @{ */
25532 
25533 #define CMP_C3_ACPH2TC_MASK                      (0x70U)
25534 #define CMP_C3_ACPH2TC_SHIFT                     (4U)
25535 /*! ACPH2TC - Analog Comparator Phase2 Timing Control.
25536  *  0b000..Phase2 active time in one sampling period equals to T
25537  *  0b001..Phase2 active time in one sampling period equals to 2*T
25538  *  0b010..Phase2 active time in one sampling period equals to 4*T
25539  *  0b011..Phase2 active time in one sampling period equals to 8*T
25540  *  0b100..Phase2 active time in one sampling period equals to 16*T
25541  *  0b101..Phase2 active time in one sampling period equals to 32*T
25542  *  0b110..Phase2 active time in one sampling period equals to 64*T
25543  *  0b111..Phase2 active time in one sampling period equals to 16*T
25544  */
25545 #define CMP_C3_ACPH2TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
25546 
25547 #define CMP_C3_ACPH1TC_MASK                      (0x700U)
25548 #define CMP_C3_ACPH1TC_SHIFT                     (8U)
25549 /*! ACPH1TC - Analog Comparator Phase1 Timing Control.
25550  *  0b000..Phase1 active time in one sampling period equals to T
25551  *  0b001..Phase1 active time in one sampling period equals to 2*T
25552  *  0b010..Phase1 active time in one sampling period equals to 4*T
25553  *  0b011..Phase1 active time in one sampling period equals to 8*T
25554  *  0b100..Phase1 active time in one sampling period equals to T
25555  *  0b101..Phase1 active time in one sampling period equals to T
25556  *  0b110..Phase1 active time in one sampling period equals to T
25557  *  0b111..Phase1 active time in one sampling period equals to 0
25558  */
25559 #define CMP_C3_ACPH1TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
25560 
25561 #define CMP_C3_ACSAT_MASK                        (0x7000U)
25562 #define CMP_C3_ACSAT_SHIFT                       (12U)
25563 /*! ACSAT - Analog Comparator Sampling Time control.
25564  *  0b000..The sampling time equals to T
25565  *  0b001..The sampling time equasl to 2*T
25566  *  0b010..The sampling time equasl to 4*T
25567  *  0b011..The sampling time equasl to 8*T
25568  *  0b100..The sampling time equasl to 16*T
25569  *  0b101..The sampling time equasl to 32*T
25570  *  0b110..The sampling time equasl to 64*T
25571  *  0b111..The sampling time equasl to 256*T
25572  */
25573 #define CMP_C3_ACSAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
25574 
25575 #define CMP_C3_DMCS_MASK                         (0x10000U)
25576 #define CMP_C3_DMCS_SHIFT                        (16U)
25577 /*! DMCS - Discrete Mode Clock Selection
25578  *  0b0..Slow clock is selected for the timing generation.
25579  *  0b1..Fast clock is selected for the timing generation.
25580  */
25581 #define CMP_C3_DMCS(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
25582 
25583 #define CMP_C3_RDIVE_MASK                        (0x100000U)
25584 #define CMP_C3_RDIVE_SHIFT                       (20U)
25585 /*! RDIVE - Resistor Divider Enable
25586  *  0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
25587  *  0b1..The resistor is enabled because the inputs are above 1.8v.
25588  */
25589 #define CMP_C3_RDIVE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
25590 
25591 #define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
25592 #define CMP_C3_NCHCTEN_SHIFT                     (24U)
25593 /*! NCHCTEN - Negative Channel Continuous Mode Enable.
25594  *  0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
25595  *  0b1..Negative channel is in Continuous Mode and no special timing is requried.
25596  */
25597 #define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
25598 
25599 #define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
25600 #define CMP_C3_PCHCTEN_SHIFT                     (28U)
25601 /*! PCHCTEN - Positive Channel Continuous Mode Enable.
25602  *  0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
25603  *  0b1..Positive channel is in Continuous Mode and no special timing is requried.
25604  */
25605 #define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
25606 /*! @} */
25607 
25608 
25609 /*!
25610  * @}
25611  */ /* end of group CMP_Register_Masks */
25612 
25613 
25614 /* CMP - Peripheral instance base addresses */
25615 /** Peripheral CMP1 base address */
25616 #define CMP1_BASE                                (0x401A4000u)
25617 /** Peripheral CMP1 base pointer */
25618 #define CMP1                                     ((CMP_Type *)CMP1_BASE)
25619 /** Peripheral CMP2 base address */
25620 #define CMP2_BASE                                (0x401A8000u)
25621 /** Peripheral CMP2 base pointer */
25622 #define CMP2                                     ((CMP_Type *)CMP2_BASE)
25623 /** Peripheral CMP3 base address */
25624 #define CMP3_BASE                                (0x401AC000u)
25625 /** Peripheral CMP3 base pointer */
25626 #define CMP3                                     ((CMP_Type *)CMP3_BASE)
25627 /** Peripheral CMP4 base address */
25628 #define CMP4_BASE                                (0x401B0000u)
25629 /** Peripheral CMP4 base pointer */
25630 #define CMP4                                     ((CMP_Type *)CMP4_BASE)
25631 /** Array initializer of CMP peripheral base addresses */
25632 #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
25633 /** Array initializer of CMP peripheral base pointers */
25634 #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
25635 /** Interrupt vectors for the CMP peripheral type */
25636 #define CMP_IRQS                                 { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
25637 
25638 /*!
25639  * @}
25640  */ /* end of group CMP_Peripheral_Access_Layer */
25641 
25642 
25643 /* ----------------------------------------------------------------------------
25644    -- CSI Peripheral Access Layer
25645    ---------------------------------------------------------------------------- */
25646 
25647 /*!
25648  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
25649  * @{
25650  */
25651 
25652 /** CSI - Register Layout Typedef */
25653 typedef struct {
25654   __IO uint32_t CR1;                               /**< CSI Control Register 1, offset: 0x0 */
25655   __IO uint32_t CR2;                               /**< CSI Control Register 2, offset: 0x4 */
25656   __IO uint32_t CR3;                               /**< CSI Control Register 3, offset: 0x8 */
25657   __I  uint32_t STATFIFO;                          /**< CSI Statistic FIFO Register, offset: 0xC */
25658   __I  uint32_t RFIFO;                             /**< CSI RX FIFO Register, offset: 0x10 */
25659   __IO uint32_t RXCNT;                             /**< CSI RX Count Register, offset: 0x14 */
25660   __IO uint32_t SR;                                /**< CSI Status Register, offset: 0x18 */
25661        uint8_t RESERVED_0[4];
25662   __IO uint32_t DMASA_STATFIFO;                    /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
25663   __IO uint32_t DMATS_STATFIFO;                    /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
25664   __IO uint32_t DMASA_FB1;                         /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
25665   __IO uint32_t DMASA_FB2;                         /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
25666   __IO uint32_t FBUF_PARA;                         /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
25667   __IO uint32_t IMAG_PARA;                         /**< CSI Image Parameter Register, offset: 0x34 */
25668        uint8_t RESERVED_1[16];
25669   __IO uint32_t CR18;                              /**< CSI Control Register 18, offset: 0x48 */
25670   __IO uint32_t CR19;                              /**< CSI Control Register 19, offset: 0x4C */
25671   __IO uint32_t CR20;                              /**< CSI Control Register 20, offset: 0x50 */
25672   __IO uint32_t CR[256];                           /**< CSI Control Register, array offset: 0x54, array step: 0x4 */
25673 } CSI_Type;
25674 
25675 /* ----------------------------------------------------------------------------
25676    -- CSI Register Masks
25677    ---------------------------------------------------------------------------- */
25678 
25679 /*!
25680  * @addtogroup CSI_Register_Masks CSI Register Masks
25681  * @{
25682  */
25683 
25684 /*! @name CR1 - CSI Control Register 1 */
25685 /*! @{ */
25686 
25687 #define CSI_CR1_PIXEL_BIT_MASK                   (0x1U)
25688 #define CSI_CR1_PIXEL_BIT_SHIFT                  (0U)
25689 /*! PIXEL_BIT
25690  *  0b0..8-bit data for each pixel
25691  *  0b1..10-bit data for each pixel
25692  */
25693 #define CSI_CR1_PIXEL_BIT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
25694 
25695 #define CSI_CR1_REDGE_MASK                       (0x2U)
25696 #define CSI_CR1_REDGE_SHIFT                      (1U)
25697 /*! REDGE
25698  *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
25699  *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
25700  */
25701 #define CSI_CR1_REDGE(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
25702 
25703 #define CSI_CR1_INV_PCLK_MASK                    (0x4U)
25704 #define CSI_CR1_INV_PCLK_SHIFT                   (2U)
25705 /*! INV_PCLK
25706  *  0b0..CSI_PIXCLK is directly applied to internal circuitry
25707  *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
25708  */
25709 #define CSI_CR1_INV_PCLK(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
25710 
25711 #define CSI_CR1_INV_DATA_MASK                    (0x8U)
25712 #define CSI_CR1_INV_DATA_SHIFT                   (3U)
25713 /*! INV_DATA
25714  *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
25715  *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
25716  */
25717 #define CSI_CR1_INV_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
25718 
25719 #define CSI_CR1_GCLK_MODE_MASK                   (0x10U)
25720 #define CSI_CR1_GCLK_MODE_SHIFT                  (4U)
25721 /*! GCLK_MODE
25722  *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
25723  *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
25724  */
25725 #define CSI_CR1_GCLK_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
25726 
25727 #define CSI_CR1_CLR_RXFIFO_MASK                  (0x20U)
25728 #define CSI_CR1_CLR_RXFIFO_SHIFT                 (5U)
25729 #define CSI_CR1_CLR_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
25730 
25731 #define CSI_CR1_CLR_STATFIFO_MASK                (0x40U)
25732 #define CSI_CR1_CLR_STATFIFO_SHIFT               (6U)
25733 #define CSI_CR1_CLR_STATFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
25734 
25735 #define CSI_CR1_PACK_DIR_MASK                    (0x80U)
25736 #define CSI_CR1_PACK_DIR_SHIFT                   (7U)
25737 /*! PACK_DIR
25738  *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
25739  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
25740  *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
25741  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
25742  */
25743 #define CSI_CR1_PACK_DIR(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
25744 
25745 #define CSI_CR1_FCC_MASK                         (0x100U)
25746 #define CSI_CR1_FCC_SHIFT                        (8U)
25747 /*! FCC
25748  *  0b0..Asynchronous FIFO clear is selected.
25749  *  0b1..Synchronous FIFO clear is selected.
25750  */
25751 #define CSI_CR1_FCC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
25752 
25753 #define CSI_CR1_CCIR_EN_MASK                     (0x400U)
25754 #define CSI_CR1_CCIR_EN_SHIFT                    (10U)
25755 /*! CCIR_EN
25756  *  0b0..Traditional interface is selected.
25757  *  0b1..BT.656 interface is selected.
25758  */
25759 #define CSI_CR1_CCIR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
25760 
25761 #define CSI_CR1_HSYNC_POL_MASK                   (0x800U)
25762 #define CSI_CR1_HSYNC_POL_SHIFT                  (11U)
25763 /*! HSYNC_POL
25764  *  0b0..HSYNC is active low
25765  *  0b1..HSYNC is active high
25766  */
25767 #define CSI_CR1_HSYNC_POL(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
25768 
25769 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK      (0x1000U)
25770 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT     (12U)
25771 /*! HISTOGRAM_CALC_DONE_IE
25772  *  0b0..Histogram done interrupt disable
25773  *  0b1..Histogram done interrupt enable
25774  */
25775 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK)
25776 
25777 #define CSI_CR1_SOF_INTEN_MASK                   (0x10000U)
25778 #define CSI_CR1_SOF_INTEN_SHIFT                  (16U)
25779 /*! SOF_INTEN
25780  *  0b0..SOF interrupt disable
25781  *  0b1..SOF interrupt enable
25782  */
25783 #define CSI_CR1_SOF_INTEN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
25784 
25785 #define CSI_CR1_SOF_POL_MASK                     (0x20000U)
25786 #define CSI_CR1_SOF_POL_SHIFT                    (17U)
25787 /*! SOF_POL
25788  *  0b0..SOF interrupt is generated on SOF falling edge
25789  *  0b1..SOF interrupt is generated on SOF rising edge
25790  */
25791 #define CSI_CR1_SOF_POL(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
25792 
25793 #define CSI_CR1_RXFF_INTEN_MASK                  (0x40000U)
25794 #define CSI_CR1_RXFF_INTEN_SHIFT                 (18U)
25795 /*! RXFF_INTEN
25796  *  0b0..RxFIFO full interrupt disable
25797  *  0b1..RxFIFO full interrupt enable
25798  */
25799 #define CSI_CR1_RXFF_INTEN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
25800 
25801 #define CSI_CR1_FB1_DMA_DONE_INTEN_MASK          (0x80000U)
25802 #define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT         (19U)
25803 /*! FB1_DMA_DONE_INTEN
25804  *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
25805  *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
25806  */
25807 #define CSI_CR1_FB1_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
25808 
25809 #define CSI_CR1_FB2_DMA_DONE_INTEN_MASK          (0x100000U)
25810 #define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT         (20U)
25811 /*! FB2_DMA_DONE_INTEN
25812  *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
25813  *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
25814  */
25815 #define CSI_CR1_FB2_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
25816 
25817 #define CSI_CR1_STATFF_INTEN_MASK                (0x200000U)
25818 #define CSI_CR1_STATFF_INTEN_SHIFT               (21U)
25819 /*! STATFF_INTEN
25820  *  0b0..STATFIFO full interrupt disable
25821  *  0b1..STATFIFO full interrupt enable
25822  */
25823 #define CSI_CR1_STATFF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
25824 
25825 #define CSI_CR1_SFF_DMA_DONE_INTEN_MASK          (0x400000U)
25826 #define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT         (22U)
25827 /*! SFF_DMA_DONE_INTEN
25828  *  0b0..STATFIFO DMA Transfer Done interrupt disable
25829  *  0b1..STATFIFO DMA Transfer Done interrupt enable
25830  */
25831 #define CSI_CR1_SFF_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
25832 
25833 #define CSI_CR1_RF_OR_INTEN_MASK                 (0x1000000U)
25834 #define CSI_CR1_RF_OR_INTEN_SHIFT                (24U)
25835 /*! RF_OR_INTEN
25836  *  0b0..RxFIFO overrun interrupt is disabled
25837  *  0b1..RxFIFO overrun interrupt is enabled
25838  */
25839 #define CSI_CR1_RF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
25840 
25841 #define CSI_CR1_SF_OR_INTEN_MASK                 (0x2000000U)
25842 #define CSI_CR1_SF_OR_INTEN_SHIFT                (25U)
25843 /*! SF_OR_INTEN
25844  *  0b0..STATFIFO overrun interrupt is disabled
25845  *  0b1..STATFIFO overrun interrupt is enabled
25846  */
25847 #define CSI_CR1_SF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
25848 
25849 #define CSI_CR1_COF_INT_EN_MASK                  (0x4000000U)
25850 #define CSI_CR1_COF_INT_EN_SHIFT                 (26U)
25851 /*! COF_INT_EN
25852  *  0b0..COF interrupt is disabled
25853  *  0b1..COF interrupt is enabled
25854  */
25855 #define CSI_CR1_COF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
25856 
25857 #define CSI_CR1_VIDEO_MODE_MASK                  (0x8000000U)
25858 #define CSI_CR1_VIDEO_MODE_SHIFT                 (27U)
25859 /*! VIDEO_MODE
25860  *  0b0..Progressive mode is selected
25861  *  0b1..Interlace mode is selected
25862  */
25863 #define CSI_CR1_VIDEO_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK)
25864 
25865 #define CSI_CR1_EOF_INT_EN_MASK                  (0x20000000U)
25866 #define CSI_CR1_EOF_INT_EN_SHIFT                 (29U)
25867 /*! EOF_INT_EN
25868  *  0b0..EOF interrupt is disabled.
25869  *  0b1..EOF interrupt is generated when RX count value is reached.
25870  */
25871 #define CSI_CR1_EOF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
25872 
25873 #define CSI_CR1_EXT_VSYNC_MASK                   (0x40000000U)
25874 #define CSI_CR1_EXT_VSYNC_SHIFT                  (30U)
25875 /*! EXT_VSYNC
25876  *  0b0..Internal VSYNC mode
25877  *  0b1..External VSYNC mode
25878  */
25879 #define CSI_CR1_EXT_VSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
25880 
25881 #define CSI_CR1_SWAP16_EN_MASK                   (0x80000000U)
25882 #define CSI_CR1_SWAP16_EN_SHIFT                  (31U)
25883 /*! SWAP16_EN
25884  *  0b0..Disable swapping
25885  *  0b1..Enable swapping
25886  */
25887 #define CSI_CR1_SWAP16_EN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
25888 /*! @} */
25889 
25890 /*! @name CR2 - CSI Control Register 2 */
25891 /*! @{ */
25892 
25893 #define CSI_CR2_HSC_MASK                         (0xFFU)
25894 #define CSI_CR2_HSC_SHIFT                        (0U)
25895 #define CSI_CR2_HSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
25896 
25897 #define CSI_CR2_VSC_MASK                         (0xFF00U)
25898 #define CSI_CR2_VSC_SHIFT                        (8U)
25899 #define CSI_CR2_VSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
25900 
25901 #define CSI_CR2_LVRM_MASK                        (0x70000U)
25902 #define CSI_CR2_LVRM_SHIFT                       (16U)
25903 /*! LVRM
25904  *  0b000..512 x 384
25905  *  0b001..448 x 336
25906  *  0b010..384 x 288
25907  *  0b011..384 x 256
25908  *  0b100..320 x 240
25909  *  0b101..288 x 216
25910  *  0b110..400 x 300
25911  */
25912 #define CSI_CR2_LVRM(x)                          (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
25913 
25914 #define CSI_CR2_BTS_MASK                         (0x180000U)
25915 #define CSI_CR2_BTS_SHIFT                        (19U)
25916 /*! BTS
25917  *  0b00..GR
25918  *  0b01..RG
25919  *  0b10..BG
25920  *  0b11..GB
25921  */
25922 #define CSI_CR2_BTS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
25923 
25924 #define CSI_CR2_SCE_MASK                         (0x800000U)
25925 #define CSI_CR2_SCE_SHIFT                        (23U)
25926 /*! SCE
25927  *  0b0..Skip count disable
25928  *  0b1..Skip count enable
25929  */
25930 #define CSI_CR2_SCE(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
25931 
25932 #define CSI_CR2_AFS_MASK                         (0x3000000U)
25933 #define CSI_CR2_AFS_SHIFT                        (24U)
25934 /*! AFS
25935  *  0b00..Abs Diff on consecutive green pixels
25936  *  0b01..Abs Diff on every third green pixels
25937  *  0b1x..Abs Diff on every four green pixels
25938  */
25939 #define CSI_CR2_AFS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
25940 
25941 #define CSI_CR2_DRM_MASK                         (0x4000000U)
25942 #define CSI_CR2_DRM_SHIFT                        (26U)
25943 /*! DRM
25944  *  0b0..Stats grid of 8 x 6
25945  *  0b1..Stats grid of 8 x 12
25946  */
25947 #define CSI_CR2_DRM(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
25948 
25949 #define CSI_CR2_DMA_BURST_TYPE_SFF_MASK          (0x30000000U)
25950 #define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT         (28U)
25951 /*! DMA_BURST_TYPE_SFF
25952  *  0bx0..INCR8
25953  *  0b01..INCR4
25954  *  0b11..INCR16
25955  */
25956 #define CSI_CR2_DMA_BURST_TYPE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
25957 
25958 #define CSI_CR2_DMA_BURST_TYPE_RFF_MASK          (0xC0000000U)
25959 #define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT         (30U)
25960 /*! DMA_BURST_TYPE_RFF
25961  *  0bx0..INCR8
25962  *  0b01..INCR4
25963  *  0b11..INCR16
25964  */
25965 #define CSI_CR2_DMA_BURST_TYPE_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
25966 /*! @} */
25967 
25968 /*! @name CR3 - CSI Control Register 3 */
25969 /*! @{ */
25970 
25971 #define CSI_CR3_ECC_AUTO_EN_MASK                 (0x1U)
25972 #define CSI_CR3_ECC_AUTO_EN_SHIFT                (0U)
25973 /*! ECC_AUTO_EN
25974  *  0b0..Auto Error correction is disabled.
25975  *  0b1..Auto Error correction is enabled.
25976  */
25977 #define CSI_CR3_ECC_AUTO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
25978 
25979 #define CSI_CR3_ECC_INT_EN_MASK                  (0x2U)
25980 #define CSI_CR3_ECC_INT_EN_SHIFT                 (1U)
25981 /*! ECC_INT_EN
25982  *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
25983  *  0b1..Interrupt is generated when error is detected.
25984  */
25985 #define CSI_CR3_ECC_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
25986 
25987 #define CSI_CR3_ZERO_PACK_EN_MASK                (0x4U)
25988 #define CSI_CR3_ZERO_PACK_EN_SHIFT               (2U)
25989 /*! ZERO_PACK_EN
25990  *  0b0..Zero packing disabled
25991  *  0b1..Zero packing enabled
25992  */
25993 #define CSI_CR3_ZERO_PACK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
25994 
25995 #define CSI_CR3_SENSOR_16BITS_MASK               (0x8U)
25996 #define CSI_CR3_SENSOR_16BITS_SHIFT              (3U)
25997 /*! SENSOR_16BITS
25998  *  0b0..Only one 8-bit sensor is connected.
25999  *  0b1..One 16-bit sensor is connected.
26000  */
26001 #define CSI_CR3_SENSOR_16BITS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
26002 
26003 #define CSI_CR3_RxFF_LEVEL_MASK                  (0x70U)
26004 #define CSI_CR3_RxFF_LEVEL_SHIFT                 (4U)
26005 /*! RxFF_LEVEL
26006  *  0b000..4 Double words
26007  *  0b001..8 Double words
26008  *  0b010..16 Double words
26009  *  0b011..24 Double words
26010  *  0b100..32 Double words
26011  *  0b101..48 Double words
26012  *  0b110..64 Double words
26013  *  0b111..96 Double words
26014  */
26015 #define CSI_CR3_RxFF_LEVEL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
26016 
26017 #define CSI_CR3_HRESP_ERR_EN_MASK                (0x80U)
26018 #define CSI_CR3_HRESP_ERR_EN_SHIFT               (7U)
26019 /*! HRESP_ERR_EN
26020  *  0b0..Disable hresponse error interrupt
26021  *  0b1..Enable hresponse error interrupt
26022  */
26023 #define CSI_CR3_HRESP_ERR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
26024 
26025 #define CSI_CR3_STATFF_LEVEL_MASK                (0x700U)
26026 #define CSI_CR3_STATFF_LEVEL_SHIFT               (8U)
26027 /*! STATFF_LEVEL
26028  *  0b000..4 Double words
26029  *  0b001..8 Double words
26030  *  0b010..12 Double words
26031  *  0b011..16 Double words
26032  *  0b100..24 Double words
26033  *  0b101..32 Double words
26034  *  0b110..48 Double words
26035  *  0b111..64 Double words
26036  */
26037 #define CSI_CR3_STATFF_LEVEL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
26038 
26039 #define CSI_CR3_DMA_REQ_EN_SFF_MASK              (0x800U)
26040 #define CSI_CR3_DMA_REQ_EN_SFF_SHIFT             (11U)
26041 /*! DMA_REQ_EN_SFF
26042  *  0b0..Disable the dma request
26043  *  0b1..Enable the dma request
26044  */
26045 #define CSI_CR3_DMA_REQ_EN_SFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
26046 
26047 #define CSI_CR3_DMA_REQ_EN_RFF_MASK              (0x1000U)
26048 #define CSI_CR3_DMA_REQ_EN_RFF_SHIFT             (12U)
26049 /*! DMA_REQ_EN_RFF
26050  *  0b0..Disable the dma request
26051  *  0b1..Enable the dma request
26052  */
26053 #define CSI_CR3_DMA_REQ_EN_RFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
26054 
26055 #define CSI_CR3_DMA_REFLASH_SFF_MASK             (0x2000U)
26056 #define CSI_CR3_DMA_REFLASH_SFF_SHIFT            (13U)
26057 /*! DMA_REFLASH_SFF
26058  *  0b0..No reflashing
26059  *  0b1..Reflash the embedded DMA controller
26060  */
26061 #define CSI_CR3_DMA_REFLASH_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
26062 
26063 #define CSI_CR3_DMA_REFLASH_RFF_MASK             (0x4000U)
26064 #define CSI_CR3_DMA_REFLASH_RFF_SHIFT            (14U)
26065 /*! DMA_REFLASH_RFF
26066  *  0b0..No reflashing
26067  *  0b1..Reflash the embedded DMA controller
26068  */
26069 #define CSI_CR3_DMA_REFLASH_RFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
26070 
26071 #define CSI_CR3_FRMCNT_RST_MASK                  (0x8000U)
26072 #define CSI_CR3_FRMCNT_RST_SHIFT                 (15U)
26073 /*! FRMCNT_RST
26074  *  0b0..Do not reset
26075  *  0b1..Reset frame counter immediately
26076  */
26077 #define CSI_CR3_FRMCNT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
26078 
26079 #define CSI_CR3_FRMCNT_MASK                      (0xFFFF0000U)
26080 #define CSI_CR3_FRMCNT_SHIFT                     (16U)
26081 #define CSI_CR3_FRMCNT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
26082 /*! @} */
26083 
26084 /*! @name STATFIFO - CSI Statistic FIFO Register */
26085 /*! @{ */
26086 
26087 #define CSI_STATFIFO_STAT_MASK                   (0xFFFFFFFFU)
26088 #define CSI_STATFIFO_STAT_SHIFT                  (0U)
26089 #define CSI_STATFIFO_STAT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
26090 /*! @} */
26091 
26092 /*! @name RFIFO - CSI RX FIFO Register */
26093 /*! @{ */
26094 
26095 #define CSI_RFIFO_IMAGE_MASK                     (0xFFFFFFFFU)
26096 #define CSI_RFIFO_IMAGE_SHIFT                    (0U)
26097 #define CSI_RFIFO_IMAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
26098 /*! @} */
26099 
26100 /*! @name RXCNT - CSI RX Count Register */
26101 /*! @{ */
26102 
26103 #define CSI_RXCNT_RXCNT_MASK                     (0x3FFFFFU)
26104 #define CSI_RXCNT_RXCNT_SHIFT                    (0U)
26105 #define CSI_RXCNT_RXCNT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
26106 /*! @} */
26107 
26108 /*! @name SR - CSI Status Register */
26109 /*! @{ */
26110 
26111 #define CSI_SR_DRDY_MASK                         (0x1U)
26112 #define CSI_SR_DRDY_SHIFT                        (0U)
26113 /*! DRDY
26114  *  0b0..No data (word) is ready
26115  *  0b1..At least 1 datum (word) is ready in RXFIFO.
26116  */
26117 #define CSI_SR_DRDY(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
26118 
26119 #define CSI_SR_ECC_INT_MASK                      (0x2U)
26120 #define CSI_SR_ECC_INT_SHIFT                     (1U)
26121 /*! ECC_INT
26122  *  0b0..No error detected
26123  *  0b1..Error is detected in BT.656 coding
26124  */
26125 #define CSI_SR_ECC_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
26126 
26127 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK      (0x4U)
26128 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT     (2U)
26129 /*! HISTOGRAM_CALC_DONE_INT
26130  *  0b0..Histogram calculation is not finished
26131  *  0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
26132  */
26133 #define CSI_SR_HISTOGRAM_CALC_DONE_INT(x)        (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK)
26134 
26135 #define CSI_SR_HRESP_ERR_INT_MASK                (0x80U)
26136 #define CSI_SR_HRESP_ERR_INT_SHIFT               (7U)
26137 /*! HRESP_ERR_INT
26138  *  0b0..No hresponse error.
26139  *  0b1..Hresponse error is detected.
26140  */
26141 #define CSI_SR_HRESP_ERR_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
26142 
26143 #define CSI_SR_COF_INT_MASK                      (0x2000U)
26144 #define CSI_SR_COF_INT_SHIFT                     (13U)
26145 /*! COF_INT
26146  *  0b0..Video field has no change.
26147  *  0b1..Change of video field is detected.
26148  */
26149 #define CSI_SR_COF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
26150 
26151 #define CSI_SR_F1_INT_MASK                       (0x4000U)
26152 #define CSI_SR_F1_INT_SHIFT                      (14U)
26153 /*! F1_INT
26154  *  0b0..Field 1 of video is not detected.
26155  *  0b1..Field 1 of video is about to start.
26156  */
26157 #define CSI_SR_F1_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
26158 
26159 #define CSI_SR_F2_INT_MASK                       (0x8000U)
26160 #define CSI_SR_F2_INT_SHIFT                      (15U)
26161 /*! F2_INT
26162  *  0b0..Field 2 of video is not detected
26163  *  0b1..Field 2 of video is about to start
26164  */
26165 #define CSI_SR_F2_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
26166 
26167 #define CSI_SR_SOF_INT_MASK                      (0x10000U)
26168 #define CSI_SR_SOF_INT_SHIFT                     (16U)
26169 /*! SOF_INT
26170  *  0b0..SOF is not detected.
26171  *  0b1..SOF is detected.
26172  */
26173 #define CSI_SR_SOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
26174 
26175 #define CSI_SR_EOF_INT_MASK                      (0x20000U)
26176 #define CSI_SR_EOF_INT_SHIFT                     (17U)
26177 /*! EOF_INT
26178  *  0b0..EOF is not detected.
26179  *  0b1..EOF is detected.
26180  */
26181 #define CSI_SR_EOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
26182 
26183 #define CSI_SR_RxFF_INT_MASK                     (0x40000U)
26184 #define CSI_SR_RxFF_INT_SHIFT                    (18U)
26185 /*! RxFF_INT
26186  *  0b0..RxFIFO is not full.
26187  *  0b1..RxFIFO is full.
26188  */
26189 #define CSI_SR_RxFF_INT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
26190 
26191 #define CSI_SR_DMA_TSF_DONE_FB1_MASK             (0x80000U)
26192 #define CSI_SR_DMA_TSF_DONE_FB1_SHIFT            (19U)
26193 /*! DMA_TSF_DONE_FB1
26194  *  0b0..DMA transfer is not completed.
26195  *  0b1..DMA transfer is completed.
26196  */
26197 #define CSI_SR_DMA_TSF_DONE_FB1(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
26198 
26199 #define CSI_SR_DMA_TSF_DONE_FB2_MASK             (0x100000U)
26200 #define CSI_SR_DMA_TSF_DONE_FB2_SHIFT            (20U)
26201 /*! DMA_TSF_DONE_FB2
26202  *  0b0..DMA transfer is not completed.
26203  *  0b1..DMA transfer is completed.
26204  */
26205 #define CSI_SR_DMA_TSF_DONE_FB2(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
26206 
26207 #define CSI_SR_STATFF_INT_MASK                   (0x200000U)
26208 #define CSI_SR_STATFF_INT_SHIFT                  (21U)
26209 /*! STATFF_INT
26210  *  0b0..STATFIFO is not full.
26211  *  0b1..STATFIFO is full.
26212  */
26213 #define CSI_SR_STATFF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
26214 
26215 #define CSI_SR_DMA_TSF_DONE_SFF_MASK             (0x400000U)
26216 #define CSI_SR_DMA_TSF_DONE_SFF_SHIFT            (22U)
26217 /*! DMA_TSF_DONE_SFF
26218  *  0b0..DMA transfer is not completed.
26219  *  0b1..DMA transfer is completed.
26220  */
26221 #define CSI_SR_DMA_TSF_DONE_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
26222 
26223 #define CSI_SR_RF_OR_INT_MASK                    (0x1000000U)
26224 #define CSI_SR_RF_OR_INT_SHIFT                   (24U)
26225 /*! RF_OR_INT
26226  *  0b0..RXFIFO has not overflowed.
26227  *  0b1..RXFIFO has overflowed.
26228  */
26229 #define CSI_SR_RF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
26230 
26231 #define CSI_SR_SF_OR_INT_MASK                    (0x2000000U)
26232 #define CSI_SR_SF_OR_INT_SHIFT                   (25U)
26233 /*! SF_OR_INT
26234  *  0b0..STATFIFO has not overflowed.
26235  *  0b1..STATFIFO has overflowed.
26236  */
26237 #define CSI_SR_SF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
26238 
26239 #define CSI_SR_DMA_FIELD1_DONE_MASK              (0x4000000U)
26240 #define CSI_SR_DMA_FIELD1_DONE_SHIFT             (26U)
26241 #define CSI_SR_DMA_FIELD1_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
26242 
26243 #define CSI_SR_DMA_FIELD0_DONE_MASK              (0x8000000U)
26244 #define CSI_SR_DMA_FIELD0_DONE_SHIFT             (27U)
26245 #define CSI_SR_DMA_FIELD0_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
26246 
26247 #define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK       (0x10000000U)
26248 #define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT      (28U)
26249 #define CSI_SR_BASEADDR_CHHANGE_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
26250 /*! @} */
26251 
26252 /*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
26253 /*! @{ */
26254 
26255 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
26256 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
26257 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
26258 /*! @} */
26259 
26260 /*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
26261 /*! @{ */
26262 
26263 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
26264 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
26265 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)   (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
26266 /*! @} */
26267 
26268 /*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
26269 /*! @{ */
26270 
26271 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK    (0xFFFFFFFCU)
26272 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT   (2U)
26273 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
26274 /*! @} */
26275 
26276 /*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
26277 /*! @{ */
26278 
26279 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK    (0xFFFFFFFCU)
26280 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT   (2U)
26281 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
26282 /*! @} */
26283 
26284 /*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */
26285 /*! @{ */
26286 
26287 #define CSI_FBUF_PARA_FBUF_STRIDE_MASK           (0xFFFFU)
26288 #define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT          (0U)
26289 #define CSI_FBUF_PARA_FBUF_STRIDE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
26290 
26291 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK    (0xFFFF0000U)
26292 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT   (16U)
26293 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)      (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
26294 /*! @} */
26295 
26296 /*! @name IMAG_PARA - CSI Image Parameter Register */
26297 /*! @{ */
26298 
26299 #define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK          (0xFFFFU)
26300 #define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT         (0U)
26301 #define CSI_IMAG_PARA_IMAGE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
26302 
26303 #define CSI_IMAG_PARA_IMAGE_WIDTH_MASK           (0xFFFF0000U)
26304 #define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT          (16U)
26305 #define CSI_IMAG_PARA_IMAGE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
26306 /*! @} */
26307 
26308 /*! @name CR18 - CSI Control Register 18 */
26309 /*! @{ */
26310 
26311 #define CSI_CR18_NTSC_EN_MASK                    (0x1U)
26312 #define CSI_CR18_NTSC_EN_SHIFT                   (0U)
26313 /*! NTSC_EN
26314  *  0b0..PAL
26315  *  0b1..NTSC
26316  */
26317 #define CSI_CR18_NTSC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK)
26318 
26319 #define CSI_CR18_TVDECODER_IN_EN_MASK            (0x2U)
26320 #define CSI_CR18_TVDECODER_IN_EN_SHIFT           (1U)
26321 #define CSI_CR18_TVDECODER_IN_EN(x)              (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK)
26322 
26323 #define CSI_CR18_DEINTERLACE_EN_MASK             (0x4U)
26324 #define CSI_CR18_DEINTERLACE_EN_SHIFT            (2U)
26325 /*! DEINTERLACE_EN
26326  *  0b0..Deinterlace disabled
26327  *  0b1..Deinterlace enabled
26328  */
26329 #define CSI_CR18_DEINTERLACE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
26330 
26331 #define CSI_CR18_PARALLEL24_EN_MASK              (0x8U)
26332 #define CSI_CR18_PARALLEL24_EN_SHIFT             (3U)
26333 /*! PARALLEL24_EN
26334  *  0b0..Input is disabled
26335  *  0b1..Input is enabled
26336  */
26337 #define CSI_CR18_PARALLEL24_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
26338 
26339 #define CSI_CR18_BASEADDR_SWITCH_EN_MASK         (0x10U)
26340 #define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT        (4U)
26341 #define CSI_CR18_BASEADDR_SWITCH_EN(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
26342 
26343 #define CSI_CR18_BASEADDR_SWITCH_SEL_MASK        (0x20U)
26344 #define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT       (5U)
26345 /*! BASEADDR_SWITCH_SEL
26346  *  0b0..Switching base address at the edge of the vsync
26347  *  0b1..Switching base address at the edge of the first data of each frame
26348  */
26349 #define CSI_CR18_BASEADDR_SWITCH_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
26350 
26351 #define CSI_CR18_FIELD0_DONE_IE_MASK             (0x40U)
26352 #define CSI_CR18_FIELD0_DONE_IE_SHIFT            (6U)
26353 /*! FIELD0_DONE_IE
26354  *  0b0..Interrupt disabled
26355  *  0b1..Interrupt enabled
26356  */
26357 #define CSI_CR18_FIELD0_DONE_IE(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
26358 
26359 #define CSI_CR18_DMA_FIELD1_DONE_IE_MASK         (0x80U)
26360 #define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT        (7U)
26361 /*! DMA_FIELD1_DONE_IE
26362  *  0b0..Interrupt disabled
26363  *  0b1..Interrupt enabled
26364  */
26365 #define CSI_CR18_DMA_FIELD1_DONE_IE(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
26366 
26367 #define CSI_CR18_LAST_DMA_REQ_SEL_MASK           (0x100U)
26368 #define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT          (8U)
26369 /*! LAST_DMA_REQ_SEL
26370  *  0b0..fifo_full_level
26371  *  0b1..hburst_length
26372  */
26373 #define CSI_CR18_LAST_DMA_REQ_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
26374 
26375 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK   (0x200U)
26376 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT  (9U)
26377 /*! BASEADDR_CHANGE_ERROR_IE
26378  *  0b0..Interrupt disabled
26379  *  0b1..Interrupt enabled
26380  */
26381 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)     (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
26382 
26383 #define CSI_CR18_RGB888A_FORMAT_SEL_MASK         (0x400U)
26384 #define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT        (10U)
26385 /*! RGB888A_FORMAT_SEL
26386  *  0b0..{8'h0, data[23:0]}
26387  *  0b1..{data[23:0], 8'h0}
26388  */
26389 #define CSI_CR18_RGB888A_FORMAT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
26390 
26391 #define CSI_CR18_AHB_HPROT_MASK                  (0xF000U)
26392 #define CSI_CR18_AHB_HPROT_SHIFT                 (12U)
26393 #define CSI_CR18_AHB_HPROT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
26394 
26395 #define CSI_CR18_MASK_OPTION_MASK                (0xC0000U)
26396 #define CSI_CR18_MASK_OPTION_SHIFT               (18U)
26397 /*! MASK_OPTION
26398  *  0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1.
26399  *  0b01..Writing to memory when CSI_ENABLE is 1.
26400  *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
26401  *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
26402  */
26403 #define CSI_CR18_MASK_OPTION(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
26404 
26405 #define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK          (0x100000U)
26406 #define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT         (20U)
26407 /*! MIPI_DOUBLE_CMPNT
26408  *  0b0..Single component per clock cycle (half pixel per clock cycle)
26409  *  0b1..Double component per clock cycle (a pixel per clock cycle)
26410  */
26411 #define CSI_CR18_MIPI_DOUBLE_CMPNT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK)
26412 
26413 #define CSI_CR18_MIPI_YU_SWAP_MASK               (0x200000U)
26414 #define CSI_CR18_MIPI_YU_SWAP_SHIFT              (21U)
26415 /*! MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode.
26416  */
26417 #define CSI_CR18_MIPI_YU_SWAP(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK)
26418 
26419 #define CSI_CR18_DATA_FROM_MIPI_MASK             (0x400000U)
26420 #define CSI_CR18_DATA_FROM_MIPI_SHIFT            (22U)
26421 /*! DATA_FROM_MIPI
26422  *  0b0..Data from parallel sensor
26423  *  0b1..Data from MIPI
26424  */
26425 #define CSI_CR18_DATA_FROM_MIPI(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK)
26426 
26427 #define CSI_CR18_LINE_STRIDE_EN_MASK             (0x1000000U)
26428 #define CSI_CR18_LINE_STRIDE_EN_SHIFT            (24U)
26429 #define CSI_CR18_LINE_STRIDE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK)
26430 
26431 #define CSI_CR18_MIPI_DATA_FORMAT_MASK           (0x7E000000U)
26432 #define CSI_CR18_MIPI_DATA_FORMAT_SHIFT          (25U)
26433 /*! MIPI_DATA_FORMAT - Image Data Format
26434  */
26435 #define CSI_CR18_MIPI_DATA_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK)
26436 
26437 #define CSI_CR18_CSI_ENABLE_MASK                 (0x80000000U)
26438 #define CSI_CR18_CSI_ENABLE_SHIFT                (31U)
26439 #define CSI_CR18_CSI_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
26440 /*! @} */
26441 
26442 /*! @name CR19 - CSI Control Register 19 */
26443 /*! @{ */
26444 
26445 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
26446 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
26447 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
26448 /*! @} */
26449 
26450 /*! @name CR20 - CSI Control Register 20 */
26451 /*! @{ */
26452 
26453 #define CSI_CR20_THRESHOLD_MASK                  (0xFFU)
26454 #define CSI_CR20_THRESHOLD_SHIFT                 (0U)
26455 #define CSI_CR20_THRESHOLD(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK)
26456 
26457 #define CSI_CR20_BINARY_EN_MASK                  (0x100U)
26458 #define CSI_CR20_BINARY_EN_SHIFT                 (8U)
26459 /*! BINARY_EN
26460  *  0b0..Output is Y8 format(8 bits each pixel)
26461  *  0b1..Output is Y1 format(1 bit each pixel)
26462  */
26463 #define CSI_CR20_BINARY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK)
26464 
26465 #define CSI_CR20_QR_DATA_FORMAT_MASK             (0xE00U)
26466 #define CSI_CR20_QR_DATA_FORMAT_SHIFT            (9U)
26467 /*! QR_DATA_FORMAT
26468  *  0b000..YU YV one cycle per 1 pixel input
26469  *  0b001..UY VY one cycle per1 pixel input
26470  *  0b010..Y U Y V two cycles per 1 pixel input
26471  *  0b011..U Y V Y two cycles per 1 pixel input
26472  *  0b100..YUV one cycle per 1 pixel input
26473  *  0b101..Y U V three cycles per 1 pixel input
26474  */
26475 #define CSI_CR20_QR_DATA_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK)
26476 
26477 #define CSI_CR20_BIG_END_MASK                    (0x1000U)
26478 #define CSI_CR20_BIG_END_SHIFT                   (12U)
26479 /*! BIG_END
26480  *  0b0..The newest (most recent) data will be assigned the lowest position when store to memory.
26481  *  0b1..The newest (most recent) data will be assigned the highest position when store to memory.
26482  */
26483 #define CSI_CR20_BIG_END(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK)
26484 
26485 #define CSI_CR20_10BIT_NEW_EN_MASK               (0x20000000U)
26486 #define CSI_CR20_10BIT_NEW_EN_SHIFT              (29U)
26487 /*! 10BIT_NEW_EN
26488  *  0b0..When input 8bits data, it will use the data[9:2]
26489  *  0b1..If input is 10bits data, it will use the data[7:0] (optional)
26490  */
26491 #define CSI_CR20_10BIT_NEW_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK)
26492 
26493 #define CSI_CR20_HISTOGRAM_EN_MASK               (0x40000000U)
26494 #define CSI_CR20_HISTOGRAM_EN_SHIFT              (30U)
26495 /*! HISTOGRAM_EN
26496  *  0b0..Histogram disable
26497  *  0b1..Histogram enable
26498  */
26499 #define CSI_CR20_HISTOGRAM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK)
26500 
26501 #define CSI_CR20_QRCODE_EN_MASK                  (0x80000000U)
26502 #define CSI_CR20_QRCODE_EN_SHIFT                 (31U)
26503 /*! QRCODE_EN
26504  *  0b0..Normal mode
26505  *  0b1..Gray scale mode
26506  */
26507 #define CSI_CR20_QRCODE_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK)
26508 /*! @} */
26509 
26510 /*! @name CR - CSI Control Register */
26511 /*! @{ */
26512 
26513 #define CSI_CR_PIXEL_COUNTERS_MASK               (0xFFFFFFU)
26514 #define CSI_CR_PIXEL_COUNTERS_SHIFT              (0U)
26515 #define CSI_CR_PIXEL_COUNTERS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK)
26516 /*! @} */
26517 
26518 /* The count of CSI_CR */
26519 #define CSI_CR_COUNT                             (256U)
26520 
26521 
26522 /*!
26523  * @}
26524  */ /* end of group CSI_Register_Masks */
26525 
26526 
26527 /* CSI - Peripheral instance base addresses */
26528 /** Peripheral CSI base address */
26529 #define CSI_BASE                                 (0x40800000u)
26530 /** Peripheral CSI base pointer */
26531 #define CSI                                      ((CSI_Type *)CSI_BASE)
26532 /** Array initializer of CSI peripheral base addresses */
26533 #define CSI_BASE_ADDRS                           { CSI_BASE }
26534 /** Array initializer of CSI peripheral base pointers */
26535 #define CSI_BASE_PTRS                            { CSI }
26536 /** Interrupt vectors for the CSI peripheral type */
26537 #define CSI_IRQS                                 { CSI_IRQn }
26538 /* Backward compatibility */
26539 #define CSI_CSICR1_PIXEL_BIT_MASK     CSI_CR1_PIXEL_BIT_MASK
26540 #define CSI_CSICR1_PIXEL_BIT_SHIFT     CSI_CR1_PIXEL_BIT_SHIFT
26541 #define CSI_CSICR1_PIXEL_BIT(x)     CSI_CR1_PIXEL_BIT(x)
26542 #define CSI_CSICR1_REDGE_MASK     CSI_CR1_REDGE_MASK
26543 #define CSI_CSICR1_REDGE_SHIFT     CSI_CR1_REDGE_SHIFT
26544 #define CSI_CSICR1_REDGE(x)     CSI_CR1_REDGE(x)
26545 #define CSI_CSICR1_INV_PCLK_MASK     CSI_CR1_INV_PCLK_MASK
26546 #define CSI_CSICR1_INV_PCLK_SHIFT     CSI_CR1_INV_PCLK_SHIFT
26547 #define CSI_CSICR1_INV_PCLK(x)     CSI_CR1_INV_PCLK(x)
26548 #define CSI_CSICR1_INV_DATA_MASK     CSI_CR1_INV_DATA_MASK
26549 #define CSI_CSICR1_INV_DATA_SHIFT     CSI_CR1_INV_DATA_SHIFT
26550 #define CSI_CSICR1_INV_DATA(x)     CSI_CR1_INV_DATA(x)
26551 #define CSI_CSICR1_GCLK_MODE_MASK     CSI_CR1_GCLK_MODE_MASK
26552 #define CSI_CSICR1_GCLK_MODE_SHIFT     CSI_CR1_GCLK_MODE_SHIFT
26553 #define CSI_CSICR1_GCLK_MODE(x)     CSI_CR1_GCLK_MODE(x)
26554 #define CSI_CSICR1_CLR_RXFIFO_MASK     CSI_CR1_CLR_RXFIFO_MASK
26555 #define CSI_CSICR1_CLR_RXFIFO_SHIFT     CSI_CR1_CLR_RXFIFO_SHIFT
26556 #define CSI_CSICR1_CLR_RXFIFO(x)     CSI_CR1_CLR_RXFIFO(x)
26557 #define CSI_CSICR1_CLR_STATFIFO_MASK     CSI_CR1_CLR_STATFIFO_MASK
26558 #define CSI_CSICR1_CLR_STATFIFO_SHIFT     CSI_CR1_CLR_STATFIFO_SHIFT
26559 #define CSI_CSICR1_CLR_STATFIFO(x)     CSI_CR1_CLR_STATFIFO(x)
26560 #define CSI_CSICR1_PACK_DIR_MASK     CSI_CR1_PACK_DIR_MASK
26561 #define CSI_CSICR1_PACK_DIR_SHIFT     CSI_CR1_PACK_DIR_SHIFT
26562 #define CSI_CSICR1_PACK_DIR(x)     CSI_CR1_PACK_DIR(x)
26563 #define CSI_CSICR1_FCC_MASK     CSI_CR1_FCC_MASK
26564 #define CSI_CSICR1_FCC_SHIFT     CSI_CR1_FCC_SHIFT
26565 #define CSI_CSICR1_FCC(x)     CSI_CR1_FCC(x)
26566 #define CSI_CSICR1_CCIR_EN_MASK     CSI_CR1_CCIR_EN_MASK
26567 #define CSI_CSICR1_CCIR_EN_SHIFT     CSI_CR1_CCIR_EN_SHIFT
26568 #define CSI_CSICR1_CCIR_EN(x)     CSI_CR1_CCIR_EN(x)
26569 #define CSI_CSICR1_HSYNC_POL_MASK     CSI_CR1_HSYNC_POL_MASK
26570 #define CSI_CSICR1_HSYNC_POL_SHIFT     CSI_CR1_HSYNC_POL_SHIFT
26571 #define CSI_CSICR1_HSYNC_POL(x)     CSI_CR1_HSYNC_POL(x)
26572 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK     CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
26573 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT     CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
26574 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x)     CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
26575 #define CSI_CSICR1_SOF_INTEN_MASK     CSI_CR1_SOF_INTEN_MASK
26576 #define CSI_CSICR1_SOF_INTEN_SHIFT     CSI_CR1_SOF_INTEN_SHIFT
26577 #define CSI_CSICR1_SOF_INTEN(x)     CSI_CR1_SOF_INTEN(x)
26578 #define CSI_CSICR1_SOF_POL_MASK     CSI_CR1_SOF_POL_MASK
26579 #define CSI_CSICR1_SOF_POL_SHIFT     CSI_CR1_SOF_POL_SHIFT
26580 #define CSI_CSICR1_SOF_POL(x)     CSI_CR1_SOF_POL(x)
26581 #define CSI_CSICR1_RXFF_INTEN_MASK     CSI_CR1_RXFF_INTEN_MASK
26582 #define CSI_CSICR1_RXFF_INTEN_SHIFT     CSI_CR1_RXFF_INTEN_SHIFT
26583 #define CSI_CSICR1_RXFF_INTEN(x)     CSI_CR1_RXFF_INTEN(x)
26584 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK     CSI_CR1_FB1_DMA_DONE_INTEN_MASK
26585 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
26586 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x)     CSI_CR1_FB1_DMA_DONE_INTEN(x)
26587 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK     CSI_CR1_FB2_DMA_DONE_INTEN_MASK
26588 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
26589 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x)     CSI_CR1_FB2_DMA_DONE_INTEN(x)
26590 #define CSI_CSICR1_STATFF_INTEN_MASK     CSI_CR1_STATFF_INTEN_MASK
26591 #define CSI_CSICR1_STATFF_INTEN_SHIFT     CSI_CR1_STATFF_INTEN_SHIFT
26592 #define CSI_CSICR1_STATFF_INTEN(x)     CSI_CR1_STATFF_INTEN(x)
26593 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK     CSI_CR1_SFF_DMA_DONE_INTEN_MASK
26594 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT     CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
26595 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x)     CSI_CR1_SFF_DMA_DONE_INTEN(x)
26596 #define CSI_CSICR1_RF_OR_INTEN_MASK     CSI_CR1_RF_OR_INTEN_MASK
26597 #define CSI_CSICR1_RF_OR_INTEN_SHIFT     CSI_CR1_RF_OR_INTEN_SHIFT
26598 #define CSI_CSICR1_RF_OR_INTEN(x)     CSI_CR1_RF_OR_INTEN(x)
26599 #define CSI_CSICR1_SF_OR_INTEN_MASK     CSI_CR1_SF_OR_INTEN_MASK
26600 #define CSI_CSICR1_SF_OR_INTEN_SHIFT     CSI_CR1_SF_OR_INTEN_SHIFT
26601 #define CSI_CSICR1_SF_OR_INTEN(x)     CSI_CR1_SF_OR_INTEN(x)
26602 #define CSI_CSICR1_COF_INT_EN_MASK     CSI_CR1_COF_INT_EN_MASK
26603 #define CSI_CSICR1_COF_INT_EN_SHIFT     CSI_CR1_COF_INT_EN_SHIFT
26604 #define CSI_CSICR1_COF_INT_EN(x)     CSI_CR1_COF_INT_EN(x)
26605 #define CSI_CSICR1_VIDEO_MODE_MASK     CSI_CR1_VIDEO_MODE_MASK
26606 #define CSI_CSICR1_VIDEO_MODE_SHIFT     CSI_CR1_VIDEO_MODE_SHIFT
26607 #define CSI_CSICR1_VIDEO_MODE(x)     CSI_CR1_VIDEO_MODE(x)
26608 #define CSI_CSICR1_EOF_INT_EN_MASK     CSI_CR1_EOF_INT_EN_MASK
26609 #define CSI_CSICR1_EOF_INT_EN_SHIFT     CSI_CR1_EOF_INT_EN_SHIFT
26610 #define CSI_CSICR1_EOF_INT_EN(x)     CSI_CR1_EOF_INT_EN(x)
26611 #define CSI_CSICR1_EXT_VSYNC_MASK     CSI_CR1_EXT_VSYNC_MASK
26612 #define CSI_CSICR1_EXT_VSYNC_SHIFT     CSI_CR1_EXT_VSYNC_SHIFT
26613 #define CSI_CSICR1_EXT_VSYNC(x)     CSI_CR1_EXT_VSYNC(x)
26614 #define CSI_CSICR1_SWAP16_EN_MASK     CSI_CR1_SWAP16_EN_MASK
26615 #define CSI_CSICR1_SWAP16_EN_SHIFT     CSI_CR1_SWAP16_EN_SHIFT
26616 #define CSI_CSICR1_SWAP16_EN(x)     CSI_CR1_SWAP16_EN(x)
26617 #define CSI_CSICR2_HSC_MASK     CSI_CR2_HSC_MASK
26618 #define CSI_CSICR2_HSC_SHIFT     CSI_CR2_HSC_SHIFT
26619 #define CSI_CSICR2_HSC(x)     CSI_CR2_HSC(x)
26620 #define CSI_CSICR2_VSC_MASK     CSI_CR2_VSC_MASK
26621 #define CSI_CSICR2_VSC_SHIFT     CSI_CR2_VSC_SHIFT
26622 #define CSI_CSICR2_VSC(x)     CSI_CR2_VSC(x)
26623 #define CSI_CSICR2_LVRM_MASK     CSI_CR2_LVRM_MASK
26624 #define CSI_CSICR2_LVRM_SHIFT     CSI_CR2_LVRM_SHIFT
26625 #define CSI_CSICR2_LVRM(x)     CSI_CR2_LVRM(x)
26626 #define CSI_CSICR2_BTS_MASK     CSI_CR2_BTS_MASK
26627 #define CSI_CSICR2_BTS_SHIFT     CSI_CR2_BTS_SHIFT
26628 #define CSI_CSICR2_BTS(x)     CSI_CR2_BTS(x)
26629 #define CSI_CSICR2_SCE_MASK     CSI_CR2_SCE_MASK
26630 #define CSI_CSICR2_SCE_SHIFT     CSI_CR2_SCE_SHIFT
26631 #define CSI_CSICR2_SCE(x)     CSI_CR2_SCE(x)
26632 #define CSI_CSICR2_AFS_MASK     CSI_CR2_AFS_MASK
26633 #define CSI_CSICR2_AFS_SHIFT     CSI_CR2_AFS_SHIFT
26634 #define CSI_CSICR2_AFS(x)     CSI_CR2_AFS(x)
26635 #define CSI_CSICR2_DRM_MASK     CSI_CR2_DRM_MASK
26636 #define CSI_CSICR2_DRM_SHIFT     CSI_CR2_DRM_SHIFT
26637 #define CSI_CSICR2_DRM(x)     CSI_CR2_DRM(x)
26638 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK     CSI_CR2_DMA_BURST_TYPE_SFF_MASK
26639 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
26640 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)     CSI_CR2_DMA_BURST_TYPE_SFF(x)
26641 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK     CSI_CR2_DMA_BURST_TYPE_RFF_MASK
26642 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
26643 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)     CSI_CR2_DMA_BURST_TYPE_RFF(x)
26644 #define CSI_CSICR3_ECC_AUTO_EN_MASK     CSI_CR3_ECC_AUTO_EN_MASK
26645 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT     CSI_CR3_ECC_AUTO_EN_SHIFT
26646 #define CSI_CSICR3_ECC_AUTO_EN(x)     CSI_CR3_ECC_AUTO_EN(x)
26647 #define CSI_CSICR3_ECC_INT_EN_MASK     CSI_CR3_ECC_INT_EN_MASK
26648 #define CSI_CSICR3_ECC_INT_EN_SHIFT     CSI_CR3_ECC_INT_EN_SHIFT
26649 #define CSI_CSICR3_ECC_INT_EN(x)     CSI_CR3_ECC_INT_EN(x)
26650 #define CSI_CSICR3_ZERO_PACK_EN_MASK     CSI_CR3_ZERO_PACK_EN_MASK
26651 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT     CSI_CR3_ZERO_PACK_EN_SHIFT
26652 #define CSI_CSICR3_ZERO_PACK_EN(x)     CSI_CR3_ZERO_PACK_EN(x)
26653 #define CSI_CSICR3_SENSOR_16BITS_MASK     CSI_CR3_SENSOR_16BITS_MASK
26654 #define CSI_CSICR3_SENSOR_16BITS_SHIFT     CSI_CR3_SENSOR_16BITS_SHIFT
26655 #define CSI_CSICR3_SENSOR_16BITS(x)     CSI_CR3_SENSOR_16BITS(x)
26656 #define CSI_CSICR3_RxFF_LEVEL_MASK     CSI_CR3_RxFF_LEVEL_MASK
26657 #define CSI_CSICR3_RxFF_LEVEL_SHIFT     CSI_CR3_RxFF_LEVEL_SHIFT
26658 #define CSI_CSICR3_RxFF_LEVEL(x)     CSI_CR3_RxFF_LEVEL(x)
26659 #define CSI_CSICR3_HRESP_ERR_EN_MASK     CSI_CR3_HRESP_ERR_EN_MASK
26660 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT     CSI_CR3_HRESP_ERR_EN_SHIFT
26661 #define CSI_CSICR3_HRESP_ERR_EN(x)     CSI_CR3_HRESP_ERR_EN(x)
26662 #define CSI_CSICR3_STATFF_LEVEL_MASK     CSI_CR3_STATFF_LEVEL_MASK
26663 #define CSI_CSICR3_STATFF_LEVEL_SHIFT     CSI_CR3_STATFF_LEVEL_SHIFT
26664 #define CSI_CSICR3_STATFF_LEVEL(x)     CSI_CR3_STATFF_LEVEL(x)
26665 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK     CSI_CR3_DMA_REQ_EN_SFF_MASK
26666 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT     CSI_CR3_DMA_REQ_EN_SFF_SHIFT
26667 #define CSI_CSICR3_DMA_REQ_EN_SFF(x)     CSI_CR3_DMA_REQ_EN_SFF(x)
26668 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK     CSI_CR3_DMA_REQ_EN_RFF_MASK
26669 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT     CSI_CR3_DMA_REQ_EN_RFF_SHIFT
26670 #define CSI_CSICR3_DMA_REQ_EN_RFF(x)     CSI_CR3_DMA_REQ_EN_RFF(x)
26671 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK     CSI_CR3_DMA_REFLASH_SFF_MASK
26672 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT     CSI_CR3_DMA_REFLASH_SFF_SHIFT
26673 #define CSI_CSICR3_DMA_REFLASH_SFF(x)     CSI_CR3_DMA_REFLASH_SFF(x)
26674 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK     CSI_CR3_DMA_REFLASH_RFF_MASK
26675 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT     CSI_CR3_DMA_REFLASH_RFF_SHIFT
26676 #define CSI_CSICR3_DMA_REFLASH_RFF(x)     CSI_CR3_DMA_REFLASH_RFF(x)
26677 #define CSI_CSICR3_FRMCNT_RST_MASK     CSI_CR3_FRMCNT_RST_MASK
26678 #define CSI_CSICR3_FRMCNT_RST_SHIFT     CSI_CR3_FRMCNT_RST_SHIFT
26679 #define CSI_CSICR3_FRMCNT_RST(x)     CSI_CR3_FRMCNT_RST(x)
26680 #define CSI_CSICR3_FRMCNT_MASK     CSI_CR3_FRMCNT_MASK
26681 #define CSI_CSICR3_FRMCNT_SHIFT     CSI_CR3_FRMCNT_SHIFT
26682 #define CSI_CSICR3_FRMCNT(x)     CSI_CR3_FRMCNT(x)
26683 #define CSI_CSISTATFIFO_STAT_MASK     CSI_STATFIFO_STAT_MASK
26684 #define CSI_CSISTATFIFO_STAT_SHIFT     CSI_STATFIFO_STAT_SHIFT
26685 #define CSI_CSISTATFIFO_STAT(x)     CSI_STATFIFO_STAT(x)
26686 #define CSI_CSIRFIFO_IMAGE_MASK     CSI_RFIFO_IMAGE_MASK
26687 #define CSI_CSIRFIFO_IMAGE_SHIFT     CSI_RFIFO_IMAGE_SHIFT
26688 #define CSI_CSIRFIFO_IMAGE(x)     CSI_RFIFO_IMAGE(x)
26689 #define CSI_CSIRXCNT_RXCNT_MASK     CSI_RXCNT_RXCNT_MASK
26690 #define CSI_CSIRXCNT_RXCNT_SHIFT     CSI_RXCNT_RXCNT_SHIFT
26691 #define CSI_CSIRXCNT_RXCNT(x)     CSI_RXCNT_RXCNT(x)
26692 #define CSI_CSISR_DRDY_MASK     CSI_SR_DRDY_MASK
26693 #define CSI_CSISR_DRDY_SHIFT     CSI_SR_DRDY_SHIFT
26694 #define CSI_CSISR_DRDY(x)     CSI_SR_DRDY(x)
26695 #define CSI_CSISR_ECC_INT_MASK     CSI_SR_ECC_INT_MASK
26696 #define CSI_CSISR_ECC_INT_SHIFT     CSI_SR_ECC_INT_SHIFT
26697 #define CSI_CSISR_ECC_INT(x)     CSI_SR_ECC_INT(x)
26698 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK     CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
26699 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT     CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
26700 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x)     CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
26701 #define CSI_CSISR_HRESP_ERR_INT_MASK     CSI_SR_HRESP_ERR_INT_MASK
26702 #define CSI_CSISR_HRESP_ERR_INT_SHIFT     CSI_SR_HRESP_ERR_INT_SHIFT
26703 #define CSI_CSISR_HRESP_ERR_INT(x)     CSI_SR_HRESP_ERR_INT(x)
26704 #define CSI_CSISR_COF_INT_MASK     CSI_SR_COF_INT_MASK
26705 #define CSI_CSISR_COF_INT_SHIFT     CSI_SR_COF_INT_SHIFT
26706 #define CSI_CSISR_COF_INT(x)     CSI_SR_COF_INT(x)
26707 #define CSI_CSISR_F1_INT_MASK     CSI_SR_F1_INT_MASK
26708 #define CSI_CSISR_F1_INT_SHIFT     CSI_SR_F1_INT_SHIFT
26709 #define CSI_CSISR_F1_INT(x)     CSI_SR_F1_INT(x)
26710 #define CSI_CSISR_F2_INT_MASK     CSI_SR_F2_INT_MASK
26711 #define CSI_CSISR_F2_INT_SHIFT     CSI_SR_F2_INT_SHIFT
26712 #define CSI_CSISR_F2_INT(x)     CSI_SR_F2_INT(x)
26713 #define CSI_CSISR_SOF_INT_MASK     CSI_SR_SOF_INT_MASK
26714 #define CSI_CSISR_SOF_INT_SHIFT     CSI_SR_SOF_INT_SHIFT
26715 #define CSI_CSISR_SOF_INT(x)     CSI_SR_SOF_INT(x)
26716 #define CSI_CSISR_EOF_INT_MASK     CSI_SR_EOF_INT_MASK
26717 #define CSI_CSISR_EOF_INT_SHIFT     CSI_SR_EOF_INT_SHIFT
26718 #define CSI_CSISR_EOF_INT(x)     CSI_SR_EOF_INT(x)
26719 #define CSI_CSISR_RxFF_INT_MASK     CSI_SR_RxFF_INT_MASK
26720 #define CSI_CSISR_RxFF_INT_SHIFT     CSI_SR_RxFF_INT_SHIFT
26721 #define CSI_CSISR_RxFF_INT(x)     CSI_SR_RxFF_INT(x)
26722 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK     CSI_SR_DMA_TSF_DONE_FB1_MASK
26723 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT     CSI_SR_DMA_TSF_DONE_FB1_SHIFT
26724 #define CSI_CSISR_DMA_TSF_DONE_FB1(x)     CSI_SR_DMA_TSF_DONE_FB1(x)
26725 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK     CSI_SR_DMA_TSF_DONE_FB2_MASK
26726 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT     CSI_SR_DMA_TSF_DONE_FB2_SHIFT
26727 #define CSI_CSISR_DMA_TSF_DONE_FB2(x)     CSI_SR_DMA_TSF_DONE_FB2(x)
26728 #define CSI_CSISR_STATFF_INT_MASK     CSI_SR_STATFF_INT_MASK
26729 #define CSI_CSISR_STATFF_INT_SHIFT     CSI_SR_STATFF_INT_SHIFT
26730 #define CSI_CSISR_STATFF_INT(x)     CSI_SR_STATFF_INT(x)
26731 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK     CSI_SR_DMA_TSF_DONE_SFF_MASK
26732 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT     CSI_SR_DMA_TSF_DONE_SFF_SHIFT
26733 #define CSI_CSISR_DMA_TSF_DONE_SFF(x)     CSI_SR_DMA_TSF_DONE_SFF(x)
26734 #define CSI_CSISR_RF_OR_INT_MASK     CSI_SR_RF_OR_INT_MASK
26735 #define CSI_CSISR_RF_OR_INT_SHIFT     CSI_SR_RF_OR_INT_SHIFT
26736 #define CSI_CSISR_RF_OR_INT(x)     CSI_SR_RF_OR_INT(x)
26737 #define CSI_CSISR_SF_OR_INT_MASK     CSI_SR_SF_OR_INT_MASK
26738 #define CSI_CSISR_SF_OR_INT_SHIFT     CSI_SR_SF_OR_INT_SHIFT
26739 #define CSI_CSISR_SF_OR_INT(x)     CSI_SR_SF_OR_INT(x)
26740 #define CSI_CSISR_DMA_FIELD1_DONE_MASK     CSI_SR_DMA_FIELD1_DONE_MASK
26741 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT     CSI_SR_DMA_FIELD1_DONE_SHIFT
26742 #define CSI_CSISR_DMA_FIELD1_DONE(x)     CSI_SR_DMA_FIELD1_DONE(x)
26743 #define CSI_CSISR_DMA_FIELD0_DONE_MASK     CSI_SR_DMA_FIELD0_DONE_MASK
26744 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT     CSI_SR_DMA_FIELD0_DONE_SHIFT
26745 #define CSI_CSISR_DMA_FIELD0_DONE(x)     CSI_SR_DMA_FIELD0_DONE(x)
26746 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK     CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
26747 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT     CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
26748 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x)     CSI_SR_BASEADDR_CHHANGE_ERROR(x)
26749 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
26750 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
26751 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x)     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
26752 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
26753 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
26754 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
26755 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK     CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
26756 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT     CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
26757 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)     CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
26758 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK     CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
26759 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT     CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
26760 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)     CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
26761 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK     CSI_FBUF_PARA_FBUF_STRIDE_MASK
26762 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT     CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
26763 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)     CSI_FBUF_PARA_FBUF_STRIDE(x)
26764 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK     CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
26765 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT     CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
26766 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)     CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
26767 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK     CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
26768 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT     CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
26769 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)     CSI_IMAG_PARA_IMAGE_HEIGHT(x)
26770 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK     CSI_IMAG_PARA_IMAGE_WIDTH_MASK
26771 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT     CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
26772 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)     CSI_IMAG_PARA_IMAGE_WIDTH(x)
26773 #define CSI_CSICR18_NTSC_EN_MASK     CSI_CR18_NTSC_EN_MASK
26774 #define CSI_CSICR18_NTSC_EN_SHIFT     CSI_CR18_NTSC_EN_SHIFT
26775 #define CSI_CSICR18_NTSC_EN(x)     CSI_CR18_NTSC_EN(x)
26776 #define CSI_CSICR18_TVDECODER_IN_EN_MASK     CSI_CR18_TVDECODER_IN_EN_MASK
26777 #define CSI_CSICR18_TVDECODER_IN_EN_SHIFT     CSI_CR18_TVDECODER_IN_EN_SHIFT
26778 #define CSI_CSICR18_TVDECODER_IN_EN(x)     CSI_CR18_TVDECODER_IN_EN(x)
26779 #define CSI_CSICR18_DEINTERLACE_EN_MASK     CSI_CR18_DEINTERLACE_EN_MASK
26780 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT     CSI_CR18_DEINTERLACE_EN_SHIFT
26781 #define CSI_CSICR18_DEINTERLACE_EN(x)     CSI_CR18_DEINTERLACE_EN(x)
26782 #define CSI_CSICR18_PARALLEL24_EN_MASK     CSI_CR18_PARALLEL24_EN_MASK
26783 #define CSI_CSICR18_PARALLEL24_EN_SHIFT     CSI_CR18_PARALLEL24_EN_SHIFT
26784 #define CSI_CSICR18_PARALLEL24_EN(x)     CSI_CR18_PARALLEL24_EN(x)
26785 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK     CSI_CR18_BASEADDR_SWITCH_EN_MASK
26786 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
26787 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x)     CSI_CR18_BASEADDR_SWITCH_EN(x)
26788 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     CSI_CR18_BASEADDR_SWITCH_SEL_MASK
26789 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT     CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
26790 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x)     CSI_CR18_BASEADDR_SWITCH_SEL(x)
26791 #define CSI_CSICR18_FIELD0_DONE_IE_MASK     CSI_CR18_FIELD0_DONE_IE_MASK
26792 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT     CSI_CR18_FIELD0_DONE_IE_SHIFT
26793 #define CSI_CSICR18_FIELD0_DONE_IE(x)     CSI_CR18_FIELD0_DONE_IE(x)
26794 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK     CSI_CR18_DMA_FIELD1_DONE_IE_MASK
26795 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
26796 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x)     CSI_CR18_DMA_FIELD1_DONE_IE(x)
26797 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK     CSI_CR18_LAST_DMA_REQ_SEL_MASK
26798 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT     CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
26799 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x)     CSI_CR18_LAST_DMA_REQ_SEL(x)
26800 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
26801 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
26802 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)     CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
26803 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK     CSI_CR18_RGB888A_FORMAT_SEL_MASK
26804 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
26805 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x)     CSI_CR18_RGB888A_FORMAT_SEL(x)
26806 #define CSI_CSICR18_AHB_HPROT_MASK     CSI_CR18_AHB_HPROT_MASK
26807 #define CSI_CSICR18_AHB_HPROT_SHIFT     CSI_CR18_AHB_HPROT_SHIFT
26808 #define CSI_CSICR18_AHB_HPROT(x)     CSI_CR18_AHB_HPROT(x)
26809 #define CSI_CSICR18_MASK_OPTION_MASK     CSI_CR18_MASK_OPTION_MASK
26810 #define CSI_CSICR18_MASK_OPTION_SHIFT     CSI_CR18_MASK_OPTION_SHIFT
26811 #define CSI_CSICR18_MASK_OPTION(x)     CSI_CR18_MASK_OPTION(x)
26812 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK     CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
26813 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT     CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
26814 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x)     CSI_CR18_MIPI_DOUBLE_CMPNT(x)
26815 #define CSI_CSICR18_MIPI_YU_SWAP_MASK     CSI_CR18_MIPI_YU_SWAP_MASK
26816 #define CSI_CSICR18_MIPI_YU_SWAP_SHIFT     CSI_CR18_MIPI_YU_SWAP_SHIFT
26817 #define CSI_CSICR18_MIPI_YU_SWAP(x)     CSI_CR18_MIPI_YU_SWAP(x)
26818 #define CSI_CSICR18_DATA_FROM_MIPI_MASK     CSI_CR18_DATA_FROM_MIPI_MASK
26819 #define CSI_CSICR18_DATA_FROM_MIPI_SHIFT     CSI_CR18_DATA_FROM_MIPI_SHIFT
26820 #define CSI_CSICR18_DATA_FROM_MIPI(x)     CSI_CR18_DATA_FROM_MIPI(x)
26821 #define CSI_CSICR18_LINE_STRIDE_EN_MASK     CSI_CR18_LINE_STRIDE_EN_MASK
26822 #define CSI_CSICR18_LINE_STRIDE_EN_SHIFT     CSI_CR18_LINE_STRIDE_EN_SHIFT
26823 #define CSI_CSICR18_LINE_STRIDE_EN(x)     CSI_CR18_LINE_STRIDE_EN(x)
26824 #define CSI_CSICR18_MIPI_DATA_FORMAT_MASK     CSI_CR18_MIPI_DATA_FORMAT_MASK
26825 #define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT     CSI_CR18_MIPI_DATA_FORMAT_SHIFT
26826 #define CSI_CSICR18_MIPI_DATA_FORMAT(x)     CSI_CR18_MIPI_DATA_FORMAT(x)
26827 #define CSI_CSICR18_CSI_ENABLE_MASK     CSI_CR18_CSI_ENABLE_MASK
26828 #define CSI_CSICR18_CSI_ENABLE_SHIFT     CSI_CR18_CSI_ENABLE_SHIFT
26829 #define CSI_CSICR18_CSI_ENABLE(x)     CSI_CR18_CSI_ENABLE(x)
26830 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
26831 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
26832 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
26833 #define CSI_CSICR20_THRESHOLD_MASK     CSI_CR20_THRESHOLD_MASK
26834 #define CSI_CSICR20_THRESHOLD_SHIFT     CSI_CR20_THRESHOLD_SHIFT
26835 #define CSI_CSICR20_THRESHOLD(x)     CSI_CR20_THRESHOLD(x)
26836 #define CSI_CSICR20_BINARY_EN_MASK     CSI_CR20_BINARY_EN_MASK
26837 #define CSI_CSICR20_BINARY_EN_SHIFT     CSI_CR20_BINARY_EN_SHIFT
26838 #define CSI_CSICR20_BINARY_EN(x)     CSI_CR20_BINARY_EN(x)
26839 #define CSI_CSICR20_QR_DATA_FORMAT_MASK     CSI_CR20_QR_DATA_FORMAT_MASK
26840 #define CSI_CSICR20_QR_DATA_FORMAT_SHIFT     CSI_CR20_QR_DATA_FORMAT_SHIFT
26841 #define CSI_CSICR20_QR_DATA_FORMAT(x)     CSI_CR20_QR_DATA_FORMAT(x)
26842 #define CSI_CSICR20_BIG_END_MASK     CSI_CR20_BIG_END_MASK
26843 #define CSI_CSICR20_BIG_END_SHIFT     CSI_CR20_BIG_END_SHIFT
26844 #define CSI_CSICR20_BIG_END(x)     CSI_CR20_BIG_END(x)
26845 #define CSI_CSICR20_10BIT_NEW_EN_MASK     CSI_CR20_10BIT_NEW_EN_MASK
26846 #define CSI_CSICR20_10BIT_NEW_EN_SHIFT     CSI_CR20_10BIT_NEW_EN_SHIFT
26847 #define CSI_CSICR20_10BIT_NEW_EN(x)     CSI_CR20_10BIT_NEW_EN(x)
26848 #define CSI_CSICR20_HISTOGRAM_EN_MASK     CSI_CR20_HISTOGRAM_EN_MASK
26849 #define CSI_CSICR20_HISTOGRAM_EN_SHIFT     CSI_CR20_HISTOGRAM_EN_SHIFT
26850 #define CSI_CSICR20_HISTOGRAM_EN(x)     CSI_CR20_HISTOGRAM_EN(x)
26851 #define CSI_CSICR20_QRCODE_EN_MASK     CSI_CR20_QRCODE_EN_MASK
26852 #define CSI_CSICR20_QRCODE_EN_SHIFT     CSI_CR20_QRCODE_EN_SHIFT
26853 #define CSI_CSICR20_QRCODE_EN(x)     CSI_CR20_QRCODE_EN(x)
26854 #define CSI_CSICR21_PIXEL_COUNTERS_MASK     CSI_CR21_PIXEL_COUNTERS_MASK
26855 #define CSI_CSICR21_PIXEL_COUNTERS_SHIFT     CSI_CR21_PIXEL_COUNTERS_SHIFT
26856 #define CSI_CSICR21_PIXEL_COUNTERS(x)     CSI_CR21_PIXEL_COUNTERS(x)
26857 #define CSI_CSICR22_PIXEL_COUNTERS_MASK     CSI_CR22_PIXEL_COUNTERS_MASK
26858 #define CSI_CSICR22_PIXEL_COUNTERS_SHIFT     CSI_CR22_PIXEL_COUNTERS_SHIFT
26859 #define CSI_CSICR22_PIXEL_COUNTERS(x)     CSI_CR22_PIXEL_COUNTERS(x)
26860 #define CSI_CSICR23_PIXEL_COUNTERS_MASK     CSI_CR23_PIXEL_COUNTERS_MASK
26861 #define CSI_CSICR23_PIXEL_COUNTERS_SHIFT     CSI_CR23_PIXEL_COUNTERS_SHIFT
26862 #define CSI_CSICR23_PIXEL_COUNTERS(x)     CSI_CR23_PIXEL_COUNTERS(x)
26863 #define CSI_CSICR24_PIXEL_COUNTERS_MASK     CSI_CR24_PIXEL_COUNTERS_MASK
26864 #define CSI_CSICR24_PIXEL_COUNTERS_SHIFT     CSI_CR24_PIXEL_COUNTERS_SHIFT
26865 #define CSI_CSICR24_PIXEL_COUNTERS(x)     CSI_CR24_PIXEL_COUNTERS(x)
26866 #define CSI_CSICR25_PIXEL_COUNTERS_MASK     CSI_CR25_PIXEL_COUNTERS_MASK
26867 #define CSI_CSICR25_PIXEL_COUNTERS_SHIFT     CSI_CR25_PIXEL_COUNTERS_SHIFT
26868 #define CSI_CSICR25_PIXEL_COUNTERS(x)     CSI_CR25_PIXEL_COUNTERS(x)
26869 #define CSI_CSICR26_PIXEL_COUNTERS_MASK     CSI_CR26_PIXEL_COUNTERS_MASK
26870 #define CSI_CSICR26_PIXEL_COUNTERS_SHIFT     CSI_CR26_PIXEL_COUNTERS_SHIFT
26871 #define CSI_CSICR26_PIXEL_COUNTERS(x)     CSI_CR26_PIXEL_COUNTERS(x)
26872 #define CSI_CSICR27_PIXEL_COUNTERS_MASK     CSI_CR27_PIXEL_COUNTERS_MASK
26873 #define CSI_CSICR27_PIXEL_COUNTERS_SHIFT     CSI_CR27_PIXEL_COUNTERS_SHIFT
26874 #define CSI_CSICR27_PIXEL_COUNTERS(x)     CSI_CR27_PIXEL_COUNTERS(x)
26875 #define CSI_CSICR28_PIXEL_COUNTERS_MASK     CSI_CR28_PIXEL_COUNTERS_MASK
26876 #define CSI_CSICR28_PIXEL_COUNTERS_SHIFT     CSI_CR28_PIXEL_COUNTERS_SHIFT
26877 #define CSI_CSICR28_PIXEL_COUNTERS(x)     CSI_CR28_PIXEL_COUNTERS(x)
26878 #define CSI_CSICR29_PIXEL_COUNTERS_MASK     CSI_CR29_PIXEL_COUNTERS_MASK
26879 #define CSI_CSICR29_PIXEL_COUNTERS_SHIFT     CSI_CR29_PIXEL_COUNTERS_SHIFT
26880 #define CSI_CSICR29_PIXEL_COUNTERS(x)     CSI_CR29_PIXEL_COUNTERS(x)
26881 #define CSI_CSICR30_PIXEL_COUNTERS_MASK     CSI_CR30_PIXEL_COUNTERS_MASK
26882 #define CSI_CSICR30_PIXEL_COUNTERS_SHIFT     CSI_CR30_PIXEL_COUNTERS_SHIFT
26883 #define CSI_CSICR30_PIXEL_COUNTERS(x)     CSI_CR30_PIXEL_COUNTERS(x)
26884 #define CSI_CSICR31_PIXEL_COUNTERS_MASK     CSI_CR31_PIXEL_COUNTERS_MASK
26885 #define CSI_CSICR31_PIXEL_COUNTERS_SHIFT     CSI_CR31_PIXEL_COUNTERS_SHIFT
26886 #define CSI_CSICR31_PIXEL_COUNTERS(x)     CSI_CR31_PIXEL_COUNTERS(x)
26887 #define CSI_CSICR32_PIXEL_COUNTERS_MASK     CSI_CR32_PIXEL_COUNTERS_MASK
26888 #define CSI_CSICR32_PIXEL_COUNTERS_SHIFT     CSI_CR32_PIXEL_COUNTERS_SHIFT
26889 #define CSI_CSICR32_PIXEL_COUNTERS(x)     CSI_CR32_PIXEL_COUNTERS(x)
26890 #define CSI_CSICR33_PIXEL_COUNTERS_MASK     CSI_CR33_PIXEL_COUNTERS_MASK
26891 #define CSI_CSICR33_PIXEL_COUNTERS_SHIFT     CSI_CR33_PIXEL_COUNTERS_SHIFT
26892 #define CSI_CSICR33_PIXEL_COUNTERS(x)     CSI_CR33_PIXEL_COUNTERS(x)
26893 #define CSI_CSICR34_PIXEL_COUNTERS_MASK     CSI_CR34_PIXEL_COUNTERS_MASK
26894 #define CSI_CSICR34_PIXEL_COUNTERS_SHIFT     CSI_CR34_PIXEL_COUNTERS_SHIFT
26895 #define CSI_CSICR34_PIXEL_COUNTERS(x)     CSI_CR34_PIXEL_COUNTERS(x)
26896 #define CSI_CSICR35_PIXEL_COUNTERS_MASK     CSI_CR35_PIXEL_COUNTERS_MASK
26897 #define CSI_CSICR35_PIXEL_COUNTERS_SHIFT     CSI_CR35_PIXEL_COUNTERS_SHIFT
26898 #define CSI_CSICR35_PIXEL_COUNTERS(x)     CSI_CR35_PIXEL_COUNTERS(x)
26899 #define CSI_CSICR36_PIXEL_COUNTERS_MASK     CSI_CR36_PIXEL_COUNTERS_MASK
26900 #define CSI_CSICR36_PIXEL_COUNTERS_SHIFT     CSI_CR36_PIXEL_COUNTERS_SHIFT
26901 #define CSI_CSICR36_PIXEL_COUNTERS(x)     CSI_CR36_PIXEL_COUNTERS(x)
26902 #define CSI_CSICR37_PIXEL_COUNTERS_MASK     CSI_CR37_PIXEL_COUNTERS_MASK
26903 #define CSI_CSICR37_PIXEL_COUNTERS_SHIFT     CSI_CR37_PIXEL_COUNTERS_SHIFT
26904 #define CSI_CSICR37_PIXEL_COUNTERS(x)     CSI_CR37_PIXEL_COUNTERS(x)
26905 #define CSI_CSICR38_PIXEL_COUNTERS_MASK     CSI_CR38_PIXEL_COUNTERS_MASK
26906 #define CSI_CSICR38_PIXEL_COUNTERS_SHIFT     CSI_CR38_PIXEL_COUNTERS_SHIFT
26907 #define CSI_CSICR38_PIXEL_COUNTERS(x)     CSI_CR38_PIXEL_COUNTERS(x)
26908 #define CSI_CSICR39_PIXEL_COUNTERS_MASK     CSI_CR39_PIXEL_COUNTERS_MASK
26909 #define CSI_CSICR39_PIXEL_COUNTERS_SHIFT     CSI_CR39_PIXEL_COUNTERS_SHIFT
26910 #define CSI_CSICR39_PIXEL_COUNTERS(x)     CSI_CR39_PIXEL_COUNTERS(x)
26911 #define CSI_CSICR40_PIXEL_COUNTERS_MASK     CSI_CR40_PIXEL_COUNTERS_MASK
26912 #define CSI_CSICR40_PIXEL_COUNTERS_SHIFT     CSI_CR40_PIXEL_COUNTERS_SHIFT
26913 #define CSI_CSICR40_PIXEL_COUNTERS(x)     CSI_CR40_PIXEL_COUNTERS(x)
26914 #define CSI_CSICR41_PIXEL_COUNTERS_MASK     CSI_CR41_PIXEL_COUNTERS_MASK
26915 #define CSI_CSICR41_PIXEL_COUNTERS_SHIFT     CSI_CR41_PIXEL_COUNTERS_SHIFT
26916 #define CSI_CSICR41_PIXEL_COUNTERS(x)     CSI_CR41_PIXEL_COUNTERS(x)
26917 #define CSI_CSICR42_PIXEL_COUNTERS_MASK     CSI_CR42_PIXEL_COUNTERS_MASK
26918 #define CSI_CSICR42_PIXEL_COUNTERS_SHIFT     CSI_CR42_PIXEL_COUNTERS_SHIFT
26919 #define CSI_CSICR42_PIXEL_COUNTERS(x)     CSI_CR42_PIXEL_COUNTERS(x)
26920 #define CSI_CSICR43_PIXEL_COUNTERS_MASK     CSI_CR43_PIXEL_COUNTERS_MASK
26921 #define CSI_CSICR43_PIXEL_COUNTERS_SHIFT     CSI_CR43_PIXEL_COUNTERS_SHIFT
26922 #define CSI_CSICR43_PIXEL_COUNTERS(x)     CSI_CR43_PIXEL_COUNTERS(x)
26923 #define CSI_CSICR44_PIXEL_COUNTERS_MASK     CSI_CR44_PIXEL_COUNTERS_MASK
26924 #define CSI_CSICR44_PIXEL_COUNTERS_SHIFT     CSI_CR44_PIXEL_COUNTERS_SHIFT
26925 #define CSI_CSICR44_PIXEL_COUNTERS(x)     CSI_CR44_PIXEL_COUNTERS(x)
26926 #define CSI_CSICR45_PIXEL_COUNTERS_MASK     CSI_CR45_PIXEL_COUNTERS_MASK
26927 #define CSI_CSICR45_PIXEL_COUNTERS_SHIFT     CSI_CR45_PIXEL_COUNTERS_SHIFT
26928 #define CSI_CSICR45_PIXEL_COUNTERS(x)     CSI_CR45_PIXEL_COUNTERS(x)
26929 #define CSI_CSICR46_PIXEL_COUNTERS_MASK     CSI_CR46_PIXEL_COUNTERS_MASK
26930 #define CSI_CSICR46_PIXEL_COUNTERS_SHIFT     CSI_CR46_PIXEL_COUNTERS_SHIFT
26931 #define CSI_CSICR46_PIXEL_COUNTERS(x)     CSI_CR46_PIXEL_COUNTERS(x)
26932 #define CSI_CSICR47_PIXEL_COUNTERS_MASK     CSI_CR47_PIXEL_COUNTERS_MASK
26933 #define CSI_CSICR47_PIXEL_COUNTERS_SHIFT     CSI_CR47_PIXEL_COUNTERS_SHIFT
26934 #define CSI_CSICR47_PIXEL_COUNTERS(x)     CSI_CR47_PIXEL_COUNTERS(x)
26935 #define CSI_CSICR48_PIXEL_COUNTERS_MASK     CSI_CR48_PIXEL_COUNTERS_MASK
26936 #define CSI_CSICR48_PIXEL_COUNTERS_SHIFT     CSI_CR48_PIXEL_COUNTERS_SHIFT
26937 #define CSI_CSICR48_PIXEL_COUNTERS(x)     CSI_CR48_PIXEL_COUNTERS(x)
26938 #define CSI_CSICR49_PIXEL_COUNTERS_MASK     CSI_CR49_PIXEL_COUNTERS_MASK
26939 #define CSI_CSICR49_PIXEL_COUNTERS_SHIFT     CSI_CR49_PIXEL_COUNTERS_SHIFT
26940 #define CSI_CSICR49_PIXEL_COUNTERS(x)     CSI_CR49_PIXEL_COUNTERS(x)
26941 #define CSI_CSICR50_PIXEL_COUNTERS_MASK     CSI_CR50_PIXEL_COUNTERS_MASK
26942 #define CSI_CSICR50_PIXEL_COUNTERS_SHIFT     CSI_CR50_PIXEL_COUNTERS_SHIFT
26943 #define CSI_CSICR50_PIXEL_COUNTERS(x)     CSI_CR50_PIXEL_COUNTERS(x)
26944 #define CSI_CSICR51_PIXEL_COUNTERS_MASK     CSI_CR51_PIXEL_COUNTERS_MASK
26945 #define CSI_CSICR51_PIXEL_COUNTERS_SHIFT     CSI_CR51_PIXEL_COUNTERS_SHIFT
26946 #define CSI_CSICR51_PIXEL_COUNTERS(x)     CSI_CR51_PIXEL_COUNTERS(x)
26947 #define CSI_CSICR52_PIXEL_COUNTERS_MASK     CSI_CR52_PIXEL_COUNTERS_MASK
26948 #define CSI_CSICR52_PIXEL_COUNTERS_SHIFT     CSI_CR52_PIXEL_COUNTERS_SHIFT
26949 #define CSI_CSICR52_PIXEL_COUNTERS(x)     CSI_CR52_PIXEL_COUNTERS(x)
26950 #define CSI_CSICR53_PIXEL_COUNTERS_MASK     CSI_CR53_PIXEL_COUNTERS_MASK
26951 #define CSI_CSICR53_PIXEL_COUNTERS_SHIFT     CSI_CR53_PIXEL_COUNTERS_SHIFT
26952 #define CSI_CSICR53_PIXEL_COUNTERS(x)     CSI_CR53_PIXEL_COUNTERS(x)
26953 #define CSI_CSICR54_PIXEL_COUNTERS_MASK     CSI_CR54_PIXEL_COUNTERS_MASK
26954 #define CSI_CSICR54_PIXEL_COUNTERS_SHIFT     CSI_CR54_PIXEL_COUNTERS_SHIFT
26955 #define CSI_CSICR54_PIXEL_COUNTERS(x)     CSI_CR54_PIXEL_COUNTERS(x)
26956 #define CSI_CSICR55_PIXEL_COUNTERS_MASK     CSI_CR55_PIXEL_COUNTERS_MASK
26957 #define CSI_CSICR55_PIXEL_COUNTERS_SHIFT     CSI_CR55_PIXEL_COUNTERS_SHIFT
26958 #define CSI_CSICR55_PIXEL_COUNTERS(x)     CSI_CR55_PIXEL_COUNTERS(x)
26959 #define CSI_CSICR56_PIXEL_COUNTERS_MASK     CSI_CR56_PIXEL_COUNTERS_MASK
26960 #define CSI_CSICR56_PIXEL_COUNTERS_SHIFT     CSI_CR56_PIXEL_COUNTERS_SHIFT
26961 #define CSI_CSICR56_PIXEL_COUNTERS(x)     CSI_CR56_PIXEL_COUNTERS(x)
26962 #define CSI_CSICR57_PIXEL_COUNTERS_MASK     CSI_CR57_PIXEL_COUNTERS_MASK
26963 #define CSI_CSICR57_PIXEL_COUNTERS_SHIFT     CSI_CR57_PIXEL_COUNTERS_SHIFT
26964 #define CSI_CSICR57_PIXEL_COUNTERS(x)     CSI_CR57_PIXEL_COUNTERS(x)
26965 #define CSI_CSICR58_PIXEL_COUNTERS_MASK     CSI_CR58_PIXEL_COUNTERS_MASK
26966 #define CSI_CSICR58_PIXEL_COUNTERS_SHIFT     CSI_CR58_PIXEL_COUNTERS_SHIFT
26967 #define CSI_CSICR58_PIXEL_COUNTERS(x)     CSI_CR58_PIXEL_COUNTERS(x)
26968 #define CSI_CSICR59_PIXEL_COUNTERS_MASK     CSI_CR59_PIXEL_COUNTERS_MASK
26969 #define CSI_CSICR59_PIXEL_COUNTERS_SHIFT     CSI_CR59_PIXEL_COUNTERS_SHIFT
26970 #define CSI_CSICR59_PIXEL_COUNTERS(x)     CSI_CR59_PIXEL_COUNTERS(x)
26971 #define CSI_CSICR60_PIXEL_COUNTERS_MASK     CSI_CR60_PIXEL_COUNTERS_MASK
26972 #define CSI_CSICR60_PIXEL_COUNTERS_SHIFT     CSI_CR60_PIXEL_COUNTERS_SHIFT
26973 #define CSI_CSICR60_PIXEL_COUNTERS(x)     CSI_CR60_PIXEL_COUNTERS(x)
26974 #define CSI_CSICR61_PIXEL_COUNTERS_MASK     CSI_CR61_PIXEL_COUNTERS_MASK
26975 #define CSI_CSICR61_PIXEL_COUNTERS_SHIFT     CSI_CR61_PIXEL_COUNTERS_SHIFT
26976 #define CSI_CSICR61_PIXEL_COUNTERS(x)     CSI_CR61_PIXEL_COUNTERS(x)
26977 #define CSI_CSICR62_PIXEL_COUNTERS_MASK     CSI_CR62_PIXEL_COUNTERS_MASK
26978 #define CSI_CSICR62_PIXEL_COUNTERS_SHIFT     CSI_CR62_PIXEL_COUNTERS_SHIFT
26979 #define CSI_CSICR62_PIXEL_COUNTERS(x)     CSI_CR62_PIXEL_COUNTERS(x)
26980 #define CSI_CSICR63_PIXEL_COUNTERS_MASK     CSI_CR63_PIXEL_COUNTERS_MASK
26981 #define CSI_CSICR63_PIXEL_COUNTERS_SHIFT     CSI_CR63_PIXEL_COUNTERS_SHIFT
26982 #define CSI_CSICR63_PIXEL_COUNTERS(x)     CSI_CR63_PIXEL_COUNTERS(x)
26983 #define CSI_CSICR64_PIXEL_COUNTERS_MASK     CSI_CR64_PIXEL_COUNTERS_MASK
26984 #define CSI_CSICR64_PIXEL_COUNTERS_SHIFT     CSI_CR64_PIXEL_COUNTERS_SHIFT
26985 #define CSI_CSICR64_PIXEL_COUNTERS(x)     CSI_CR64_PIXEL_COUNTERS(x)
26986 #define CSI_CSICR65_PIXEL_COUNTERS_MASK     CSI_CR65_PIXEL_COUNTERS_MASK
26987 #define CSI_CSICR65_PIXEL_COUNTERS_SHIFT     CSI_CR65_PIXEL_COUNTERS_SHIFT
26988 #define CSI_CSICR65_PIXEL_COUNTERS(x)     CSI_CR65_PIXEL_COUNTERS(x)
26989 #define CSI_CSICR66_PIXEL_COUNTERS_MASK     CSI_CR66_PIXEL_COUNTERS_MASK
26990 #define CSI_CSICR66_PIXEL_COUNTERS_SHIFT     CSI_CR66_PIXEL_COUNTERS_SHIFT
26991 #define CSI_CSICR66_PIXEL_COUNTERS(x)     CSI_CR66_PIXEL_COUNTERS(x)
26992 #define CSI_CSICR67_PIXEL_COUNTERS_MASK     CSI_CR67_PIXEL_COUNTERS_MASK
26993 #define CSI_CSICR67_PIXEL_COUNTERS_SHIFT     CSI_CR67_PIXEL_COUNTERS_SHIFT
26994 #define CSI_CSICR67_PIXEL_COUNTERS(x)     CSI_CR67_PIXEL_COUNTERS(x)
26995 #define CSI_CSICR68_PIXEL_COUNTERS_MASK     CSI_CR68_PIXEL_COUNTERS_MASK
26996 #define CSI_CSICR68_PIXEL_COUNTERS_SHIFT     CSI_CR68_PIXEL_COUNTERS_SHIFT
26997 #define CSI_CSICR68_PIXEL_COUNTERS(x)     CSI_CR68_PIXEL_COUNTERS(x)
26998 #define CSI_CSICR69_PIXEL_COUNTERS_MASK     CSI_CR69_PIXEL_COUNTERS_MASK
26999 #define CSI_CSICR69_PIXEL_COUNTERS_SHIFT     CSI_CR69_PIXEL_COUNTERS_SHIFT
27000 #define CSI_CSICR69_PIXEL_COUNTERS(x)     CSI_CR69_PIXEL_COUNTERS(x)
27001 #define CSI_CSICR70_PIXEL_COUNTERS_MASK     CSI_CR70_PIXEL_COUNTERS_MASK
27002 #define CSI_CSICR70_PIXEL_COUNTERS_SHIFT     CSI_CR70_PIXEL_COUNTERS_SHIFT
27003 #define CSI_CSICR70_PIXEL_COUNTERS(x)     CSI_CR70_PIXEL_COUNTERS(x)
27004 #define CSI_CSICR71_PIXEL_COUNTERS_MASK     CSI_CR71_PIXEL_COUNTERS_MASK
27005 #define CSI_CSICR71_PIXEL_COUNTERS_SHIFT     CSI_CR71_PIXEL_COUNTERS_SHIFT
27006 #define CSI_CSICR71_PIXEL_COUNTERS(x)     CSI_CR71_PIXEL_COUNTERS(x)
27007 #define CSI_CSICR72_PIXEL_COUNTERS_MASK     CSI_CR72_PIXEL_COUNTERS_MASK
27008 #define CSI_CSICR72_PIXEL_COUNTERS_SHIFT     CSI_CR72_PIXEL_COUNTERS_SHIFT
27009 #define CSI_CSICR72_PIXEL_COUNTERS(x)     CSI_CR72_PIXEL_COUNTERS(x)
27010 #define CSI_CSICR73_PIXEL_COUNTERS_MASK     CSI_CR73_PIXEL_COUNTERS_MASK
27011 #define CSI_CSICR73_PIXEL_COUNTERS_SHIFT     CSI_CR73_PIXEL_COUNTERS_SHIFT
27012 #define CSI_CSICR73_PIXEL_COUNTERS(x)     CSI_CR73_PIXEL_COUNTERS(x)
27013 #define CSI_CSICR74_PIXEL_COUNTERS_MASK     CSI_CR74_PIXEL_COUNTERS_MASK
27014 #define CSI_CSICR74_PIXEL_COUNTERS_SHIFT     CSI_CR74_PIXEL_COUNTERS_SHIFT
27015 #define CSI_CSICR74_PIXEL_COUNTERS(x)     CSI_CR74_PIXEL_COUNTERS(x)
27016 #define CSI_CSICR75_PIXEL_COUNTERS_MASK     CSI_CR75_PIXEL_COUNTERS_MASK
27017 #define CSI_CSICR75_PIXEL_COUNTERS_SHIFT     CSI_CR75_PIXEL_COUNTERS_SHIFT
27018 #define CSI_CSICR75_PIXEL_COUNTERS(x)     CSI_CR75_PIXEL_COUNTERS(x)
27019 #define CSI_CSICR76_PIXEL_COUNTERS_MASK     CSI_CR76_PIXEL_COUNTERS_MASK
27020 #define CSI_CSICR76_PIXEL_COUNTERS_SHIFT     CSI_CR76_PIXEL_COUNTERS_SHIFT
27021 #define CSI_CSICR76_PIXEL_COUNTERS(x)     CSI_CR76_PIXEL_COUNTERS(x)
27022 #define CSI_CSICR77_PIXEL_COUNTERS_MASK     CSI_CR77_PIXEL_COUNTERS_MASK
27023 #define CSI_CSICR77_PIXEL_COUNTERS_SHIFT     CSI_CR77_PIXEL_COUNTERS_SHIFT
27024 #define CSI_CSICR77_PIXEL_COUNTERS(x)     CSI_CR77_PIXEL_COUNTERS(x)
27025 #define CSI_CSICR78_PIXEL_COUNTERS_MASK     CSI_CR78_PIXEL_COUNTERS_MASK
27026 #define CSI_CSICR78_PIXEL_COUNTERS_SHIFT     CSI_CR78_PIXEL_COUNTERS_SHIFT
27027 #define CSI_CSICR78_PIXEL_COUNTERS(x)     CSI_CR78_PIXEL_COUNTERS(x)
27028 #define CSI_CSICR79_PIXEL_COUNTERS_MASK     CSI_CR79_PIXEL_COUNTERS_MASK
27029 #define CSI_CSICR79_PIXEL_COUNTERS_SHIFT     CSI_CR79_PIXEL_COUNTERS_SHIFT
27030 #define CSI_CSICR79_PIXEL_COUNTERS(x)     CSI_CR79_PIXEL_COUNTERS(x)
27031 #define CSI_CSICR80_PIXEL_COUNTERS_MASK     CSI_CR80_PIXEL_COUNTERS_MASK
27032 #define CSI_CSICR80_PIXEL_COUNTERS_SHIFT     CSI_CR80_PIXEL_COUNTERS_SHIFT
27033 #define CSI_CSICR80_PIXEL_COUNTERS(x)     CSI_CR80_PIXEL_COUNTERS(x)
27034 #define CSI_CSICR81_PIXEL_COUNTERS_MASK     CSI_CR81_PIXEL_COUNTERS_MASK
27035 #define CSI_CSICR81_PIXEL_COUNTERS_SHIFT     CSI_CR81_PIXEL_COUNTERS_SHIFT
27036 #define CSI_CSICR81_PIXEL_COUNTERS(x)     CSI_CR81_PIXEL_COUNTERS(x)
27037 #define CSI_CSICR82_PIXEL_COUNTERS_MASK     CSI_CR82_PIXEL_COUNTERS_MASK
27038 #define CSI_CSICR82_PIXEL_COUNTERS_SHIFT     CSI_CR82_PIXEL_COUNTERS_SHIFT
27039 #define CSI_CSICR82_PIXEL_COUNTERS(x)     CSI_CR82_PIXEL_COUNTERS(x)
27040 #define CSI_CSICR83_PIXEL_COUNTERS_MASK     CSI_CR83_PIXEL_COUNTERS_MASK
27041 #define CSI_CSICR83_PIXEL_COUNTERS_SHIFT     CSI_CR83_PIXEL_COUNTERS_SHIFT
27042 #define CSI_CSICR83_PIXEL_COUNTERS(x)     CSI_CR83_PIXEL_COUNTERS(x)
27043 #define CSI_CSICR84_PIXEL_COUNTERS_MASK     CSI_CR84_PIXEL_COUNTERS_MASK
27044 #define CSI_CSICR84_PIXEL_COUNTERS_SHIFT     CSI_CR84_PIXEL_COUNTERS_SHIFT
27045 #define CSI_CSICR84_PIXEL_COUNTERS(x)     CSI_CR84_PIXEL_COUNTERS(x)
27046 #define CSI_CSICR85_PIXEL_COUNTERS_MASK     CSI_CR85_PIXEL_COUNTERS_MASK
27047 #define CSI_CSICR85_PIXEL_COUNTERS_SHIFT     CSI_CR85_PIXEL_COUNTERS_SHIFT
27048 #define CSI_CSICR85_PIXEL_COUNTERS(x)     CSI_CR85_PIXEL_COUNTERS(x)
27049 #define CSI_CSICR86_PIXEL_COUNTERS_MASK     CSI_CR86_PIXEL_COUNTERS_MASK
27050 #define CSI_CSICR86_PIXEL_COUNTERS_SHIFT     CSI_CR86_PIXEL_COUNTERS_SHIFT
27051 #define CSI_CSICR86_PIXEL_COUNTERS(x)     CSI_CR86_PIXEL_COUNTERS(x)
27052 #define CSI_CSICR87_PIXEL_COUNTERS_MASK     CSI_CR87_PIXEL_COUNTERS_MASK
27053 #define CSI_CSICR87_PIXEL_COUNTERS_SHIFT     CSI_CR87_PIXEL_COUNTERS_SHIFT
27054 #define CSI_CSICR87_PIXEL_COUNTERS(x)     CSI_CR87_PIXEL_COUNTERS(x)
27055 #define CSI_CSICR88_PIXEL_COUNTERS_MASK     CSI_CR88_PIXEL_COUNTERS_MASK
27056 #define CSI_CSICR88_PIXEL_COUNTERS_SHIFT     CSI_CR88_PIXEL_COUNTERS_SHIFT
27057 #define CSI_CSICR88_PIXEL_COUNTERS(x)     CSI_CR88_PIXEL_COUNTERS(x)
27058 #define CSI_CSICR89_PIXEL_COUNTERS_MASK     CSI_CR89_PIXEL_COUNTERS_MASK
27059 #define CSI_CSICR89_PIXEL_COUNTERS_SHIFT     CSI_CR89_PIXEL_COUNTERS_SHIFT
27060 #define CSI_CSICR89_PIXEL_COUNTERS(x)     CSI_CR89_PIXEL_COUNTERS(x)
27061 #define CSI_CSICR90_PIXEL_COUNTERS_MASK     CSI_CR90_PIXEL_COUNTERS_MASK
27062 #define CSI_CSICR90_PIXEL_COUNTERS_SHIFT     CSI_CR90_PIXEL_COUNTERS_SHIFT
27063 #define CSI_CSICR90_PIXEL_COUNTERS(x)     CSI_CR90_PIXEL_COUNTERS(x)
27064 #define CSI_CSICR91_PIXEL_COUNTERS_MASK     CSI_CR91_PIXEL_COUNTERS_MASK
27065 #define CSI_CSICR91_PIXEL_COUNTERS_SHIFT     CSI_CR91_PIXEL_COUNTERS_SHIFT
27066 #define CSI_CSICR91_PIXEL_COUNTERS(x)     CSI_CR91_PIXEL_COUNTERS(x)
27067 #define CSI_CSICR92_PIXEL_COUNTERS_MASK     CSI_CR92_PIXEL_COUNTERS_MASK
27068 #define CSI_CSICR92_PIXEL_COUNTERS_SHIFT     CSI_CR92_PIXEL_COUNTERS_SHIFT
27069 #define CSI_CSICR92_PIXEL_COUNTERS(x)     CSI_CR92_PIXEL_COUNTERS(x)
27070 #define CSI_CSICR93_PIXEL_COUNTERS_MASK     CSI_CR93_PIXEL_COUNTERS_MASK
27071 #define CSI_CSICR93_PIXEL_COUNTERS_SHIFT     CSI_CR93_PIXEL_COUNTERS_SHIFT
27072 #define CSI_CSICR93_PIXEL_COUNTERS(x)     CSI_CR93_PIXEL_COUNTERS(x)
27073 #define CSI_CSICR94_PIXEL_COUNTERS_MASK     CSI_CR94_PIXEL_COUNTERS_MASK
27074 #define CSI_CSICR94_PIXEL_COUNTERS_SHIFT     CSI_CR94_PIXEL_COUNTERS_SHIFT
27075 #define CSI_CSICR94_PIXEL_COUNTERS(x)     CSI_CR94_PIXEL_COUNTERS(x)
27076 #define CSI_CSICR95_PIXEL_COUNTERS_MASK     CSI_CR95_PIXEL_COUNTERS_MASK
27077 #define CSI_CSICR95_PIXEL_COUNTERS_SHIFT     CSI_CR95_PIXEL_COUNTERS_SHIFT
27078 #define CSI_CSICR95_PIXEL_COUNTERS(x)     CSI_CR95_PIXEL_COUNTERS(x)
27079 #define CSI_CSICR96_PIXEL_COUNTERS_MASK     CSI_CR96_PIXEL_COUNTERS_MASK
27080 #define CSI_CSICR96_PIXEL_COUNTERS_SHIFT     CSI_CR96_PIXEL_COUNTERS_SHIFT
27081 #define CSI_CSICR96_PIXEL_COUNTERS(x)     CSI_CR96_PIXEL_COUNTERS(x)
27082 #define CSI_CSICR97_PIXEL_COUNTERS_MASK     CSI_CR97_PIXEL_COUNTERS_MASK
27083 #define CSI_CSICR97_PIXEL_COUNTERS_SHIFT     CSI_CR97_PIXEL_COUNTERS_SHIFT
27084 #define CSI_CSICR97_PIXEL_COUNTERS(x)     CSI_CR97_PIXEL_COUNTERS(x)
27085 #define CSI_CSICR98_PIXEL_COUNTERS_MASK     CSI_CR98_PIXEL_COUNTERS_MASK
27086 #define CSI_CSICR98_PIXEL_COUNTERS_SHIFT     CSI_CR98_PIXEL_COUNTERS_SHIFT
27087 #define CSI_CSICR98_PIXEL_COUNTERS(x)     CSI_CR98_PIXEL_COUNTERS(x)
27088 #define CSI_CSICR99_PIXEL_COUNTERS_MASK     CSI_CR99_PIXEL_COUNTERS_MASK
27089 #define CSI_CSICR99_PIXEL_COUNTERS_SHIFT     CSI_CR99_PIXEL_COUNTERS_SHIFT
27090 #define CSI_CSICR99_PIXEL_COUNTERS(x)     CSI_CR99_PIXEL_COUNTERS(x)
27091 #define CSI_CSICR100_PIXEL_COUNTERS_MASK     CSI_CR100_PIXEL_COUNTERS_MASK
27092 #define CSI_CSICR100_PIXEL_COUNTERS_SHIFT     CSI_CR100_PIXEL_COUNTERS_SHIFT
27093 #define CSI_CSICR100_PIXEL_COUNTERS(x)     CSI_CR100_PIXEL_COUNTERS(x)
27094 #define CSI_CSICR101_PIXEL_COUNTERS_MASK     CSI_CR101_PIXEL_COUNTERS_MASK
27095 #define CSI_CSICR101_PIXEL_COUNTERS_SHIFT     CSI_CR101_PIXEL_COUNTERS_SHIFT
27096 #define CSI_CSICR101_PIXEL_COUNTERS(x)     CSI_CR101_PIXEL_COUNTERS(x)
27097 #define CSI_CSICR102_PIXEL_COUNTERS_MASK     CSI_CR102_PIXEL_COUNTERS_MASK
27098 #define CSI_CSICR102_PIXEL_COUNTERS_SHIFT     CSI_CR102_PIXEL_COUNTERS_SHIFT
27099 #define CSI_CSICR102_PIXEL_COUNTERS(x)     CSI_CR102_PIXEL_COUNTERS(x)
27100 #define CSI_CSICR103_PIXEL_COUNTERS_MASK     CSI_CR103_PIXEL_COUNTERS_MASK
27101 #define CSI_CSICR103_PIXEL_COUNTERS_SHIFT     CSI_CR103_PIXEL_COUNTERS_SHIFT
27102 #define CSI_CSICR103_PIXEL_COUNTERS(x)     CSI_CR103_PIXEL_COUNTERS(x)
27103 #define CSI_CSICR104_PIXEL_COUNTERS_MASK     CSI_CR104_PIXEL_COUNTERS_MASK
27104 #define CSI_CSICR104_PIXEL_COUNTERS_SHIFT     CSI_CR104_PIXEL_COUNTERS_SHIFT
27105 #define CSI_CSICR104_PIXEL_COUNTERS(x)     CSI_CR104_PIXEL_COUNTERS(x)
27106 #define CSI_CSICR105_PIXEL_COUNTERS_MASK     CSI_CR105_PIXEL_COUNTERS_MASK
27107 #define CSI_CSICR105_PIXEL_COUNTERS_SHIFT     CSI_CR105_PIXEL_COUNTERS_SHIFT
27108 #define CSI_CSICR105_PIXEL_COUNTERS(x)     CSI_CR105_PIXEL_COUNTERS(x)
27109 #define CSI_CSICR106_PIXEL_COUNTERS_MASK     CSI_CR106_PIXEL_COUNTERS_MASK
27110 #define CSI_CSICR106_PIXEL_COUNTERS_SHIFT     CSI_CR106_PIXEL_COUNTERS_SHIFT
27111 #define CSI_CSICR106_PIXEL_COUNTERS(x)     CSI_CR106_PIXEL_COUNTERS(x)
27112 #define CSI_CSICR107_PIXEL_COUNTERS_MASK     CSI_CR107_PIXEL_COUNTERS_MASK
27113 #define CSI_CSICR107_PIXEL_COUNTERS_SHIFT     CSI_CR107_PIXEL_COUNTERS_SHIFT
27114 #define CSI_CSICR107_PIXEL_COUNTERS(x)     CSI_CR107_PIXEL_COUNTERS(x)
27115 #define CSI_CSICR108_PIXEL_COUNTERS_MASK     CSI_CR108_PIXEL_COUNTERS_MASK
27116 #define CSI_CSICR108_PIXEL_COUNTERS_SHIFT     CSI_CR108_PIXEL_COUNTERS_SHIFT
27117 #define CSI_CSICR108_PIXEL_COUNTERS(x)     CSI_CR108_PIXEL_COUNTERS(x)
27118 #define CSI_CSICR109_PIXEL_COUNTERS_MASK     CSI_CR109_PIXEL_COUNTERS_MASK
27119 #define CSI_CSICR109_PIXEL_COUNTERS_SHIFT     CSI_CR109_PIXEL_COUNTERS_SHIFT
27120 #define CSI_CSICR109_PIXEL_COUNTERS(x)     CSI_CR109_PIXEL_COUNTERS(x)
27121 #define CSI_CSICR110_PIXEL_COUNTERS_MASK     CSI_CR110_PIXEL_COUNTERS_MASK
27122 #define CSI_CSICR110_PIXEL_COUNTERS_SHIFT     CSI_CR110_PIXEL_COUNTERS_SHIFT
27123 #define CSI_CSICR110_PIXEL_COUNTERS(x)     CSI_CR110_PIXEL_COUNTERS(x)
27124 #define CSI_CSICR111_PIXEL_COUNTERS_MASK     CSI_CR111_PIXEL_COUNTERS_MASK
27125 #define CSI_CSICR111_PIXEL_COUNTERS_SHIFT     CSI_CR111_PIXEL_COUNTERS_SHIFT
27126 #define CSI_CSICR111_PIXEL_COUNTERS(x)     CSI_CR111_PIXEL_COUNTERS(x)
27127 #define CSI_CSICR112_PIXEL_COUNTERS_MASK     CSI_CR112_PIXEL_COUNTERS_MASK
27128 #define CSI_CSICR112_PIXEL_COUNTERS_SHIFT     CSI_CR112_PIXEL_COUNTERS_SHIFT
27129 #define CSI_CSICR112_PIXEL_COUNTERS(x)     CSI_CR112_PIXEL_COUNTERS(x)
27130 #define CSI_CSICR113_PIXEL_COUNTERS_MASK     CSI_CR113_PIXEL_COUNTERS_MASK
27131 #define CSI_CSICR113_PIXEL_COUNTERS_SHIFT     CSI_CR113_PIXEL_COUNTERS_SHIFT
27132 #define CSI_CSICR113_PIXEL_COUNTERS(x)     CSI_CR113_PIXEL_COUNTERS(x)
27133 #define CSI_CSICR114_PIXEL_COUNTERS_MASK     CSI_CR114_PIXEL_COUNTERS_MASK
27134 #define CSI_CSICR114_PIXEL_COUNTERS_SHIFT     CSI_CR114_PIXEL_COUNTERS_SHIFT
27135 #define CSI_CSICR114_PIXEL_COUNTERS(x)     CSI_CR114_PIXEL_COUNTERS(x)
27136 #define CSI_CSICR115_PIXEL_COUNTERS_MASK     CSI_CR115_PIXEL_COUNTERS_MASK
27137 #define CSI_CSICR115_PIXEL_COUNTERS_SHIFT     CSI_CR115_PIXEL_COUNTERS_SHIFT
27138 #define CSI_CSICR115_PIXEL_COUNTERS(x)     CSI_CR115_PIXEL_COUNTERS(x)
27139 #define CSI_CSICR116_PIXEL_COUNTERS_MASK     CSI_CR116_PIXEL_COUNTERS_MASK
27140 #define CSI_CSICR116_PIXEL_COUNTERS_SHIFT     CSI_CR116_PIXEL_COUNTERS_SHIFT
27141 #define CSI_CSICR116_PIXEL_COUNTERS(x)     CSI_CR116_PIXEL_COUNTERS(x)
27142 #define CSI_CSICR117_PIXEL_COUNTERS_MASK     CSI_CR117_PIXEL_COUNTERS_MASK
27143 #define CSI_CSICR117_PIXEL_COUNTERS_SHIFT     CSI_CR117_PIXEL_COUNTERS_SHIFT
27144 #define CSI_CSICR117_PIXEL_COUNTERS(x)     CSI_CR117_PIXEL_COUNTERS(x)
27145 #define CSI_CSICR118_PIXEL_COUNTERS_MASK     CSI_CR118_PIXEL_COUNTERS_MASK
27146 #define CSI_CSICR118_PIXEL_COUNTERS_SHIFT     CSI_CR118_PIXEL_COUNTERS_SHIFT
27147 #define CSI_CSICR118_PIXEL_COUNTERS(x)     CSI_CR118_PIXEL_COUNTERS(x)
27148 #define CSI_CSICR119_PIXEL_COUNTERS_MASK     CSI_CR119_PIXEL_COUNTERS_MASK
27149 #define CSI_CSICR119_PIXEL_COUNTERS_SHIFT     CSI_CR119_PIXEL_COUNTERS_SHIFT
27150 #define CSI_CSICR119_PIXEL_COUNTERS(x)     CSI_CR119_PIXEL_COUNTERS(x)
27151 #define CSI_CSICR120_PIXEL_COUNTERS_MASK     CSI_CR120_PIXEL_COUNTERS_MASK
27152 #define CSI_CSICR120_PIXEL_COUNTERS_SHIFT     CSI_CR120_PIXEL_COUNTERS_SHIFT
27153 #define CSI_CSICR120_PIXEL_COUNTERS(x)     CSI_CR120_PIXEL_COUNTERS(x)
27154 #define CSI_CSICR121_PIXEL_COUNTERS_MASK     CSI_CR121_PIXEL_COUNTERS_MASK
27155 #define CSI_CSICR121_PIXEL_COUNTERS_SHIFT     CSI_CR121_PIXEL_COUNTERS_SHIFT
27156 #define CSI_CSICR121_PIXEL_COUNTERS(x)     CSI_CR121_PIXEL_COUNTERS(x)
27157 #define CSI_CSICR122_PIXEL_COUNTERS_MASK     CSI_CR122_PIXEL_COUNTERS_MASK
27158 #define CSI_CSICR122_PIXEL_COUNTERS_SHIFT     CSI_CR122_PIXEL_COUNTERS_SHIFT
27159 #define CSI_CSICR122_PIXEL_COUNTERS(x)     CSI_CR122_PIXEL_COUNTERS(x)
27160 #define CSI_CSICR123_PIXEL_COUNTERS_MASK     CSI_CR123_PIXEL_COUNTERS_MASK
27161 #define CSI_CSICR123_PIXEL_COUNTERS_SHIFT     CSI_CR123_PIXEL_COUNTERS_SHIFT
27162 #define CSI_CSICR123_PIXEL_COUNTERS(x)     CSI_CR123_PIXEL_COUNTERS(x)
27163 #define CSI_CSICR124_PIXEL_COUNTERS_MASK     CSI_CR124_PIXEL_COUNTERS_MASK
27164 #define CSI_CSICR124_PIXEL_COUNTERS_SHIFT     CSI_CR124_PIXEL_COUNTERS_SHIFT
27165 #define CSI_CSICR124_PIXEL_COUNTERS(x)     CSI_CR124_PIXEL_COUNTERS(x)
27166 #define CSI_CSICR125_PIXEL_COUNTERS_MASK     CSI_CR125_PIXEL_COUNTERS_MASK
27167 #define CSI_CSICR125_PIXEL_COUNTERS_SHIFT     CSI_CR125_PIXEL_COUNTERS_SHIFT
27168 #define CSI_CSICR125_PIXEL_COUNTERS(x)     CSI_CR125_PIXEL_COUNTERS(x)
27169 #define CSI_CSICR126_PIXEL_COUNTERS_MASK     CSI_CR126_PIXEL_COUNTERS_MASK
27170 #define CSI_CSICR126_PIXEL_COUNTERS_SHIFT     CSI_CR126_PIXEL_COUNTERS_SHIFT
27171 #define CSI_CSICR126_PIXEL_COUNTERS(x)     CSI_CR126_PIXEL_COUNTERS(x)
27172 #define CSI_CSICR127_PIXEL_COUNTERS_MASK     CSI_CR127_PIXEL_COUNTERS_MASK
27173 #define CSI_CSICR127_PIXEL_COUNTERS_SHIFT     CSI_CR127_PIXEL_COUNTERS_SHIFT
27174 #define CSI_CSICR127_PIXEL_COUNTERS(x)     CSI_CR127_PIXEL_COUNTERS(x)
27175 #define CSI_CSICR128_PIXEL_COUNTERS_MASK     CSI_CR128_PIXEL_COUNTERS_MASK
27176 #define CSI_CSICR128_PIXEL_COUNTERS_SHIFT     CSI_CR128_PIXEL_COUNTERS_SHIFT
27177 #define CSI_CSICR128_PIXEL_COUNTERS(x)     CSI_CR128_PIXEL_COUNTERS(x)
27178 #define CSI_CSICR129_PIXEL_COUNTERS_MASK     CSI_CR129_PIXEL_COUNTERS_MASK
27179 #define CSI_CSICR129_PIXEL_COUNTERS_SHIFT     CSI_CR129_PIXEL_COUNTERS_SHIFT
27180 #define CSI_CSICR129_PIXEL_COUNTERS(x)     CSI_CR129_PIXEL_COUNTERS(x)
27181 #define CSI_CSICR130_PIXEL_COUNTERS_MASK     CSI_CR130_PIXEL_COUNTERS_MASK
27182 #define CSI_CSICR130_PIXEL_COUNTERS_SHIFT     CSI_CR130_PIXEL_COUNTERS_SHIFT
27183 #define CSI_CSICR130_PIXEL_COUNTERS(x)     CSI_CR130_PIXEL_COUNTERS(x)
27184 #define CSI_CSICR131_PIXEL_COUNTERS_MASK     CSI_CR131_PIXEL_COUNTERS_MASK
27185 #define CSI_CSICR131_PIXEL_COUNTERS_SHIFT     CSI_CR131_PIXEL_COUNTERS_SHIFT
27186 #define CSI_CSICR131_PIXEL_COUNTERS(x)     CSI_CR131_PIXEL_COUNTERS(x)
27187 #define CSI_CSICR132_PIXEL_COUNTERS_MASK     CSI_CR132_PIXEL_COUNTERS_MASK
27188 #define CSI_CSICR132_PIXEL_COUNTERS_SHIFT     CSI_CR132_PIXEL_COUNTERS_SHIFT
27189 #define CSI_CSICR132_PIXEL_COUNTERS(x)     CSI_CR132_PIXEL_COUNTERS(x)
27190 #define CSI_CSICR133_PIXEL_COUNTERS_MASK     CSI_CR133_PIXEL_COUNTERS_MASK
27191 #define CSI_CSICR133_PIXEL_COUNTERS_SHIFT     CSI_CR133_PIXEL_COUNTERS_SHIFT
27192 #define CSI_CSICR133_PIXEL_COUNTERS(x)     CSI_CR133_PIXEL_COUNTERS(x)
27193 #define CSI_CSICR134_PIXEL_COUNTERS_MASK     CSI_CR134_PIXEL_COUNTERS_MASK
27194 #define CSI_CSICR134_PIXEL_COUNTERS_SHIFT     CSI_CR134_PIXEL_COUNTERS_SHIFT
27195 #define CSI_CSICR134_PIXEL_COUNTERS(x)     CSI_CR134_PIXEL_COUNTERS(x)
27196 #define CSI_CSICR135_PIXEL_COUNTERS_MASK     CSI_CR135_PIXEL_COUNTERS_MASK
27197 #define CSI_CSICR135_PIXEL_COUNTERS_SHIFT     CSI_CR135_PIXEL_COUNTERS_SHIFT
27198 #define CSI_CSICR135_PIXEL_COUNTERS(x)     CSI_CR135_PIXEL_COUNTERS(x)
27199 #define CSI_CSICR136_PIXEL_COUNTERS_MASK     CSI_CR136_PIXEL_COUNTERS_MASK
27200 #define CSI_CSICR136_PIXEL_COUNTERS_SHIFT     CSI_CR136_PIXEL_COUNTERS_SHIFT
27201 #define CSI_CSICR136_PIXEL_COUNTERS(x)     CSI_CR136_PIXEL_COUNTERS(x)
27202 #define CSI_CSICR137_PIXEL_COUNTERS_MASK     CSI_CR137_PIXEL_COUNTERS_MASK
27203 #define CSI_CSICR137_PIXEL_COUNTERS_SHIFT     CSI_CR137_PIXEL_COUNTERS_SHIFT
27204 #define CSI_CSICR137_PIXEL_COUNTERS(x)     CSI_CR137_PIXEL_COUNTERS(x)
27205 #define CSI_CSICR138_PIXEL_COUNTERS_MASK     CSI_CR138_PIXEL_COUNTERS_MASK
27206 #define CSI_CSICR138_PIXEL_COUNTERS_SHIFT     CSI_CR138_PIXEL_COUNTERS_SHIFT
27207 #define CSI_CSICR138_PIXEL_COUNTERS(x)     CSI_CR138_PIXEL_COUNTERS(x)
27208 #define CSI_CSICR139_PIXEL_COUNTERS_MASK     CSI_CR139_PIXEL_COUNTERS_MASK
27209 #define CSI_CSICR139_PIXEL_COUNTERS_SHIFT     CSI_CR139_PIXEL_COUNTERS_SHIFT
27210 #define CSI_CSICR139_PIXEL_COUNTERS(x)     CSI_CR139_PIXEL_COUNTERS(x)
27211 #define CSI_CSICR140_PIXEL_COUNTERS_MASK     CSI_CR140_PIXEL_COUNTERS_MASK
27212 #define CSI_CSICR140_PIXEL_COUNTERS_SHIFT     CSI_CR140_PIXEL_COUNTERS_SHIFT
27213 #define CSI_CSICR140_PIXEL_COUNTERS(x)     CSI_CR140_PIXEL_COUNTERS(x)
27214 #define CSI_CSICR141_PIXEL_COUNTERS_MASK     CSI_CR141_PIXEL_COUNTERS_MASK
27215 #define CSI_CSICR141_PIXEL_COUNTERS_SHIFT     CSI_CR141_PIXEL_COUNTERS_SHIFT
27216 #define CSI_CSICR141_PIXEL_COUNTERS(x)     CSI_CR141_PIXEL_COUNTERS(x)
27217 #define CSI_CSICR142_PIXEL_COUNTERS_MASK     CSI_CR142_PIXEL_COUNTERS_MASK
27218 #define CSI_CSICR142_PIXEL_COUNTERS_SHIFT     CSI_CR142_PIXEL_COUNTERS_SHIFT
27219 #define CSI_CSICR142_PIXEL_COUNTERS(x)     CSI_CR142_PIXEL_COUNTERS(x)
27220 #define CSI_CSICR143_PIXEL_COUNTERS_MASK     CSI_CR143_PIXEL_COUNTERS_MASK
27221 #define CSI_CSICR143_PIXEL_COUNTERS_SHIFT     CSI_CR143_PIXEL_COUNTERS_SHIFT
27222 #define CSI_CSICR143_PIXEL_COUNTERS(x)     CSI_CR143_PIXEL_COUNTERS(x)
27223 #define CSI_CSICR144_PIXEL_COUNTERS_MASK     CSI_CR144_PIXEL_COUNTERS_MASK
27224 #define CSI_CSICR144_PIXEL_COUNTERS_SHIFT     CSI_CR144_PIXEL_COUNTERS_SHIFT
27225 #define CSI_CSICR144_PIXEL_COUNTERS(x)     CSI_CR144_PIXEL_COUNTERS(x)
27226 #define CSI_CSICR145_PIXEL_COUNTERS_MASK     CSI_CR145_PIXEL_COUNTERS_MASK
27227 #define CSI_CSICR145_PIXEL_COUNTERS_SHIFT     CSI_CR145_PIXEL_COUNTERS_SHIFT
27228 #define CSI_CSICR145_PIXEL_COUNTERS(x)     CSI_CR145_PIXEL_COUNTERS(x)
27229 #define CSI_CSICR146_PIXEL_COUNTERS_MASK     CSI_CR146_PIXEL_COUNTERS_MASK
27230 #define CSI_CSICR146_PIXEL_COUNTERS_SHIFT     CSI_CR146_PIXEL_COUNTERS_SHIFT
27231 #define CSI_CSICR146_PIXEL_COUNTERS(x)     CSI_CR146_PIXEL_COUNTERS(x)
27232 #define CSI_CSICR147_PIXEL_COUNTERS_MASK     CSI_CR147_PIXEL_COUNTERS_MASK
27233 #define CSI_CSICR147_PIXEL_COUNTERS_SHIFT     CSI_CR147_PIXEL_COUNTERS_SHIFT
27234 #define CSI_CSICR147_PIXEL_COUNTERS(x)     CSI_CR147_PIXEL_COUNTERS(x)
27235 #define CSI_CSICR148_PIXEL_COUNTERS_MASK     CSI_CR148_PIXEL_COUNTERS_MASK
27236 #define CSI_CSICR148_PIXEL_COUNTERS_SHIFT     CSI_CR148_PIXEL_COUNTERS_SHIFT
27237 #define CSI_CSICR148_PIXEL_COUNTERS(x)     CSI_CR148_PIXEL_COUNTERS(x)
27238 #define CSI_CSICR149_PIXEL_COUNTERS_MASK     CSI_CR149_PIXEL_COUNTERS_MASK
27239 #define CSI_CSICR149_PIXEL_COUNTERS_SHIFT     CSI_CR149_PIXEL_COUNTERS_SHIFT
27240 #define CSI_CSICR149_PIXEL_COUNTERS(x)     CSI_CR149_PIXEL_COUNTERS(x)
27241 #define CSI_CSICR150_PIXEL_COUNTERS_MASK     CSI_CR150_PIXEL_COUNTERS_MASK
27242 #define CSI_CSICR150_PIXEL_COUNTERS_SHIFT     CSI_CR150_PIXEL_COUNTERS_SHIFT
27243 #define CSI_CSICR150_PIXEL_COUNTERS(x)     CSI_CR150_PIXEL_COUNTERS(x)
27244 #define CSI_CSICR151_PIXEL_COUNTERS_MASK     CSI_CR151_PIXEL_COUNTERS_MASK
27245 #define CSI_CSICR151_PIXEL_COUNTERS_SHIFT     CSI_CR151_PIXEL_COUNTERS_SHIFT
27246 #define CSI_CSICR151_PIXEL_COUNTERS(x)     CSI_CR151_PIXEL_COUNTERS(x)
27247 #define CSI_CSICR152_PIXEL_COUNTERS_MASK     CSI_CR152_PIXEL_COUNTERS_MASK
27248 #define CSI_CSICR152_PIXEL_COUNTERS_SHIFT     CSI_CR152_PIXEL_COUNTERS_SHIFT
27249 #define CSI_CSICR152_PIXEL_COUNTERS(x)     CSI_CR152_PIXEL_COUNTERS(x)
27250 #define CSI_CSICR153_PIXEL_COUNTERS_MASK     CSI_CR153_PIXEL_COUNTERS_MASK
27251 #define CSI_CSICR153_PIXEL_COUNTERS_SHIFT     CSI_CR153_PIXEL_COUNTERS_SHIFT
27252 #define CSI_CSICR153_PIXEL_COUNTERS(x)     CSI_CR153_PIXEL_COUNTERS(x)
27253 #define CSI_CSICR154_PIXEL_COUNTERS_MASK     CSI_CR154_PIXEL_COUNTERS_MASK
27254 #define CSI_CSICR154_PIXEL_COUNTERS_SHIFT     CSI_CR154_PIXEL_COUNTERS_SHIFT
27255 #define CSI_CSICR154_PIXEL_COUNTERS(x)     CSI_CR154_PIXEL_COUNTERS(x)
27256 #define CSI_CSICR155_PIXEL_COUNTERS_MASK     CSI_CR155_PIXEL_COUNTERS_MASK
27257 #define CSI_CSICR155_PIXEL_COUNTERS_SHIFT     CSI_CR155_PIXEL_COUNTERS_SHIFT
27258 #define CSI_CSICR155_PIXEL_COUNTERS(x)     CSI_CR155_PIXEL_COUNTERS(x)
27259 #define CSI_CSICR156_PIXEL_COUNTERS_MASK     CSI_CR156_PIXEL_COUNTERS_MASK
27260 #define CSI_CSICR156_PIXEL_COUNTERS_SHIFT     CSI_CR156_PIXEL_COUNTERS_SHIFT
27261 #define CSI_CSICR156_PIXEL_COUNTERS(x)     CSI_CR156_PIXEL_COUNTERS(x)
27262 #define CSI_CSICR157_PIXEL_COUNTERS_MASK     CSI_CR157_PIXEL_COUNTERS_MASK
27263 #define CSI_CSICR157_PIXEL_COUNTERS_SHIFT     CSI_CR157_PIXEL_COUNTERS_SHIFT
27264 #define CSI_CSICR157_PIXEL_COUNTERS(x)     CSI_CR157_PIXEL_COUNTERS(x)
27265 #define CSI_CSICR158_PIXEL_COUNTERS_MASK     CSI_CR158_PIXEL_COUNTERS_MASK
27266 #define CSI_CSICR158_PIXEL_COUNTERS_SHIFT     CSI_CR158_PIXEL_COUNTERS_SHIFT
27267 #define CSI_CSICR158_PIXEL_COUNTERS(x)     CSI_CR158_PIXEL_COUNTERS(x)
27268 #define CSI_CSICR159_PIXEL_COUNTERS_MASK     CSI_CR159_PIXEL_COUNTERS_MASK
27269 #define CSI_CSICR159_PIXEL_COUNTERS_SHIFT     CSI_CR159_PIXEL_COUNTERS_SHIFT
27270 #define CSI_CSICR159_PIXEL_COUNTERS(x)     CSI_CR159_PIXEL_COUNTERS(x)
27271 #define CSI_CSICR160_PIXEL_COUNTERS_MASK     CSI_CR160_PIXEL_COUNTERS_MASK
27272 #define CSI_CSICR160_PIXEL_COUNTERS_SHIFT     CSI_CR160_PIXEL_COUNTERS_SHIFT
27273 #define CSI_CSICR160_PIXEL_COUNTERS(x)     CSI_CR160_PIXEL_COUNTERS(x)
27274 #define CSI_CSICR161_PIXEL_COUNTERS_MASK     CSI_CR161_PIXEL_COUNTERS_MASK
27275 #define CSI_CSICR161_PIXEL_COUNTERS_SHIFT     CSI_CR161_PIXEL_COUNTERS_SHIFT
27276 #define CSI_CSICR161_PIXEL_COUNTERS(x)     CSI_CR161_PIXEL_COUNTERS(x)
27277 #define CSI_CSICR162_PIXEL_COUNTERS_MASK     CSI_CR162_PIXEL_COUNTERS_MASK
27278 #define CSI_CSICR162_PIXEL_COUNTERS_SHIFT     CSI_CR162_PIXEL_COUNTERS_SHIFT
27279 #define CSI_CSICR162_PIXEL_COUNTERS(x)     CSI_CR162_PIXEL_COUNTERS(x)
27280 #define CSI_CSICR163_PIXEL_COUNTERS_MASK     CSI_CR163_PIXEL_COUNTERS_MASK
27281 #define CSI_CSICR163_PIXEL_COUNTERS_SHIFT     CSI_CR163_PIXEL_COUNTERS_SHIFT
27282 #define CSI_CSICR163_PIXEL_COUNTERS(x)     CSI_CR163_PIXEL_COUNTERS(x)
27283 #define CSI_CSICR164_PIXEL_COUNTERS_MASK     CSI_CR164_PIXEL_COUNTERS_MASK
27284 #define CSI_CSICR164_PIXEL_COUNTERS_SHIFT     CSI_CR164_PIXEL_COUNTERS_SHIFT
27285 #define CSI_CSICR164_PIXEL_COUNTERS(x)     CSI_CR164_PIXEL_COUNTERS(x)
27286 #define CSI_CSICR165_PIXEL_COUNTERS_MASK     CSI_CR165_PIXEL_COUNTERS_MASK
27287 #define CSI_CSICR165_PIXEL_COUNTERS_SHIFT     CSI_CR165_PIXEL_COUNTERS_SHIFT
27288 #define CSI_CSICR165_PIXEL_COUNTERS(x)     CSI_CR165_PIXEL_COUNTERS(x)
27289 #define CSI_CSICR166_PIXEL_COUNTERS_MASK     CSI_CR166_PIXEL_COUNTERS_MASK
27290 #define CSI_CSICR166_PIXEL_COUNTERS_SHIFT     CSI_CR166_PIXEL_COUNTERS_SHIFT
27291 #define CSI_CSICR166_PIXEL_COUNTERS(x)     CSI_CR166_PIXEL_COUNTERS(x)
27292 #define CSI_CSICR167_PIXEL_COUNTERS_MASK     CSI_CR167_PIXEL_COUNTERS_MASK
27293 #define CSI_CSICR167_PIXEL_COUNTERS_SHIFT     CSI_CR167_PIXEL_COUNTERS_SHIFT
27294 #define CSI_CSICR167_PIXEL_COUNTERS(x)     CSI_CR167_PIXEL_COUNTERS(x)
27295 #define CSI_CSICR168_PIXEL_COUNTERS_MASK     CSI_CR168_PIXEL_COUNTERS_MASK
27296 #define CSI_CSICR168_PIXEL_COUNTERS_SHIFT     CSI_CR168_PIXEL_COUNTERS_SHIFT
27297 #define CSI_CSICR168_PIXEL_COUNTERS(x)     CSI_CR168_PIXEL_COUNTERS(x)
27298 #define CSI_CSICR169_PIXEL_COUNTERS_MASK     CSI_CR169_PIXEL_COUNTERS_MASK
27299 #define CSI_CSICR169_PIXEL_COUNTERS_SHIFT     CSI_CR169_PIXEL_COUNTERS_SHIFT
27300 #define CSI_CSICR169_PIXEL_COUNTERS(x)     CSI_CR169_PIXEL_COUNTERS(x)
27301 #define CSI_CSICR170_PIXEL_COUNTERS_MASK     CSI_CR170_PIXEL_COUNTERS_MASK
27302 #define CSI_CSICR170_PIXEL_COUNTERS_SHIFT     CSI_CR170_PIXEL_COUNTERS_SHIFT
27303 #define CSI_CSICR170_PIXEL_COUNTERS(x)     CSI_CR170_PIXEL_COUNTERS(x)
27304 #define CSI_CSICR171_PIXEL_COUNTERS_MASK     CSI_CR171_PIXEL_COUNTERS_MASK
27305 #define CSI_CSICR171_PIXEL_COUNTERS_SHIFT     CSI_CR171_PIXEL_COUNTERS_SHIFT
27306 #define CSI_CSICR171_PIXEL_COUNTERS(x)     CSI_CR171_PIXEL_COUNTERS(x)
27307 #define CSI_CSICR172_PIXEL_COUNTERS_MASK     CSI_CR172_PIXEL_COUNTERS_MASK
27308 #define CSI_CSICR172_PIXEL_COUNTERS_SHIFT     CSI_CR172_PIXEL_COUNTERS_SHIFT
27309 #define CSI_CSICR172_PIXEL_COUNTERS(x)     CSI_CR172_PIXEL_COUNTERS(x)
27310 #define CSI_CSICR173_PIXEL_COUNTERS_MASK     CSI_CR173_PIXEL_COUNTERS_MASK
27311 #define CSI_CSICR173_PIXEL_COUNTERS_SHIFT     CSI_CR173_PIXEL_COUNTERS_SHIFT
27312 #define CSI_CSICR173_PIXEL_COUNTERS(x)     CSI_CR173_PIXEL_COUNTERS(x)
27313 #define CSI_CSICR174_PIXEL_COUNTERS_MASK     CSI_CR174_PIXEL_COUNTERS_MASK
27314 #define CSI_CSICR174_PIXEL_COUNTERS_SHIFT     CSI_CR174_PIXEL_COUNTERS_SHIFT
27315 #define CSI_CSICR174_PIXEL_COUNTERS(x)     CSI_CR174_PIXEL_COUNTERS(x)
27316 #define CSI_CSICR175_PIXEL_COUNTERS_MASK     CSI_CR175_PIXEL_COUNTERS_MASK
27317 #define CSI_CSICR175_PIXEL_COUNTERS_SHIFT     CSI_CR175_PIXEL_COUNTERS_SHIFT
27318 #define CSI_CSICR175_PIXEL_COUNTERS(x)     CSI_CR175_PIXEL_COUNTERS(x)
27319 #define CSI_CSICR176_PIXEL_COUNTERS_MASK     CSI_CR176_PIXEL_COUNTERS_MASK
27320 #define CSI_CSICR176_PIXEL_COUNTERS_SHIFT     CSI_CR176_PIXEL_COUNTERS_SHIFT
27321 #define CSI_CSICR176_PIXEL_COUNTERS(x)     CSI_CR176_PIXEL_COUNTERS(x)
27322 #define CSI_CSICR177_PIXEL_COUNTERS_MASK     CSI_CR177_PIXEL_COUNTERS_MASK
27323 #define CSI_CSICR177_PIXEL_COUNTERS_SHIFT     CSI_CR177_PIXEL_COUNTERS_SHIFT
27324 #define CSI_CSICR177_PIXEL_COUNTERS(x)     CSI_CR177_PIXEL_COUNTERS(x)
27325 #define CSI_CSICR178_PIXEL_COUNTERS_MASK     CSI_CR178_PIXEL_COUNTERS_MASK
27326 #define CSI_CSICR178_PIXEL_COUNTERS_SHIFT     CSI_CR178_PIXEL_COUNTERS_SHIFT
27327 #define CSI_CSICR178_PIXEL_COUNTERS(x)     CSI_CR178_PIXEL_COUNTERS(x)
27328 #define CSI_CSICR179_PIXEL_COUNTERS_MASK     CSI_CR179_PIXEL_COUNTERS_MASK
27329 #define CSI_CSICR179_PIXEL_COUNTERS_SHIFT     CSI_CR179_PIXEL_COUNTERS_SHIFT
27330 #define CSI_CSICR179_PIXEL_COUNTERS(x)     CSI_CR179_PIXEL_COUNTERS(x)
27331 #define CSI_CSICR180_PIXEL_COUNTERS_MASK     CSI_CR180_PIXEL_COUNTERS_MASK
27332 #define CSI_CSICR180_PIXEL_COUNTERS_SHIFT     CSI_CR180_PIXEL_COUNTERS_SHIFT
27333 #define CSI_CSICR180_PIXEL_COUNTERS(x)     CSI_CR180_PIXEL_COUNTERS(x)
27334 #define CSI_CSICR181_PIXEL_COUNTERS_MASK     CSI_CR181_PIXEL_COUNTERS_MASK
27335 #define CSI_CSICR181_PIXEL_COUNTERS_SHIFT     CSI_CR181_PIXEL_COUNTERS_SHIFT
27336 #define CSI_CSICR181_PIXEL_COUNTERS(x)     CSI_CR181_PIXEL_COUNTERS(x)
27337 #define CSI_CSICR182_PIXEL_COUNTERS_MASK     CSI_CR182_PIXEL_COUNTERS_MASK
27338 #define CSI_CSICR182_PIXEL_COUNTERS_SHIFT     CSI_CR182_PIXEL_COUNTERS_SHIFT
27339 #define CSI_CSICR182_PIXEL_COUNTERS(x)     CSI_CR182_PIXEL_COUNTERS(x)
27340 #define CSI_CSICR183_PIXEL_COUNTERS_MASK     CSI_CR183_PIXEL_COUNTERS_MASK
27341 #define CSI_CSICR183_PIXEL_COUNTERS_SHIFT     CSI_CR183_PIXEL_COUNTERS_SHIFT
27342 #define CSI_CSICR183_PIXEL_COUNTERS(x)     CSI_CR183_PIXEL_COUNTERS(x)
27343 #define CSI_CSICR184_PIXEL_COUNTERS_MASK     CSI_CR184_PIXEL_COUNTERS_MASK
27344 #define CSI_CSICR184_PIXEL_COUNTERS_SHIFT     CSI_CR184_PIXEL_COUNTERS_SHIFT
27345 #define CSI_CSICR184_PIXEL_COUNTERS(x)     CSI_CR184_PIXEL_COUNTERS(x)
27346 #define CSI_CSICR185_PIXEL_COUNTERS_MASK     CSI_CR185_PIXEL_COUNTERS_MASK
27347 #define CSI_CSICR185_PIXEL_COUNTERS_SHIFT     CSI_CR185_PIXEL_COUNTERS_SHIFT
27348 #define CSI_CSICR185_PIXEL_COUNTERS(x)     CSI_CR185_PIXEL_COUNTERS(x)
27349 #define CSI_CSICR186_PIXEL_COUNTERS_MASK     CSI_CR186_PIXEL_COUNTERS_MASK
27350 #define CSI_CSICR186_PIXEL_COUNTERS_SHIFT     CSI_CR186_PIXEL_COUNTERS_SHIFT
27351 #define CSI_CSICR186_PIXEL_COUNTERS(x)     CSI_CR186_PIXEL_COUNTERS(x)
27352 #define CSI_CSICR187_PIXEL_COUNTERS_MASK     CSI_CR187_PIXEL_COUNTERS_MASK
27353 #define CSI_CSICR187_PIXEL_COUNTERS_SHIFT     CSI_CR187_PIXEL_COUNTERS_SHIFT
27354 #define CSI_CSICR187_PIXEL_COUNTERS(x)     CSI_CR187_PIXEL_COUNTERS(x)
27355 #define CSI_CSICR188_PIXEL_COUNTERS_MASK     CSI_CR188_PIXEL_COUNTERS_MASK
27356 #define CSI_CSICR188_PIXEL_COUNTERS_SHIFT     CSI_CR188_PIXEL_COUNTERS_SHIFT
27357 #define CSI_CSICR188_PIXEL_COUNTERS(x)     CSI_CR188_PIXEL_COUNTERS(x)
27358 #define CSI_CSICR189_PIXEL_COUNTERS_MASK     CSI_CR189_PIXEL_COUNTERS_MASK
27359 #define CSI_CSICR189_PIXEL_COUNTERS_SHIFT     CSI_CR189_PIXEL_COUNTERS_SHIFT
27360 #define CSI_CSICR189_PIXEL_COUNTERS(x)     CSI_CR189_PIXEL_COUNTERS(x)
27361 #define CSI_CSICR190_PIXEL_COUNTERS_MASK     CSI_CR190_PIXEL_COUNTERS_MASK
27362 #define CSI_CSICR190_PIXEL_COUNTERS_SHIFT     CSI_CR190_PIXEL_COUNTERS_SHIFT
27363 #define CSI_CSICR190_PIXEL_COUNTERS(x)     CSI_CR190_PIXEL_COUNTERS(x)
27364 #define CSI_CSICR191_PIXEL_COUNTERS_MASK     CSI_CR191_PIXEL_COUNTERS_MASK
27365 #define CSI_CSICR191_PIXEL_COUNTERS_SHIFT     CSI_CR191_PIXEL_COUNTERS_SHIFT
27366 #define CSI_CSICR191_PIXEL_COUNTERS(x)     CSI_CR191_PIXEL_COUNTERS(x)
27367 #define CSI_CSICR192_PIXEL_COUNTERS_MASK     CSI_CR192_PIXEL_COUNTERS_MASK
27368 #define CSI_CSICR192_PIXEL_COUNTERS_SHIFT     CSI_CR192_PIXEL_COUNTERS_SHIFT
27369 #define CSI_CSICR192_PIXEL_COUNTERS(x)     CSI_CR192_PIXEL_COUNTERS(x)
27370 #define CSI_CSICR193_PIXEL_COUNTERS_MASK     CSI_CR193_PIXEL_COUNTERS_MASK
27371 #define CSI_CSICR193_PIXEL_COUNTERS_SHIFT     CSI_CR193_PIXEL_COUNTERS_SHIFT
27372 #define CSI_CSICR193_PIXEL_COUNTERS(x)     CSI_CR193_PIXEL_COUNTERS(x)
27373 #define CSI_CSICR194_PIXEL_COUNTERS_MASK     CSI_CR194_PIXEL_COUNTERS_MASK
27374 #define CSI_CSICR194_PIXEL_COUNTERS_SHIFT     CSI_CR194_PIXEL_COUNTERS_SHIFT
27375 #define CSI_CSICR194_PIXEL_COUNTERS(x)     CSI_CR194_PIXEL_COUNTERS(x)
27376 #define CSI_CSICR195_PIXEL_COUNTERS_MASK     CSI_CR195_PIXEL_COUNTERS_MASK
27377 #define CSI_CSICR195_PIXEL_COUNTERS_SHIFT     CSI_CR195_PIXEL_COUNTERS_SHIFT
27378 #define CSI_CSICR195_PIXEL_COUNTERS(x)     CSI_CR195_PIXEL_COUNTERS(x)
27379 #define CSI_CSICR196_PIXEL_COUNTERS_MASK     CSI_CR196_PIXEL_COUNTERS_MASK
27380 #define CSI_CSICR196_PIXEL_COUNTERS_SHIFT     CSI_CR196_PIXEL_COUNTERS_SHIFT
27381 #define CSI_CSICR196_PIXEL_COUNTERS(x)     CSI_CR196_PIXEL_COUNTERS(x)
27382 #define CSI_CSICR197_PIXEL_COUNTERS_MASK     CSI_CR197_PIXEL_COUNTERS_MASK
27383 #define CSI_CSICR197_PIXEL_COUNTERS_SHIFT     CSI_CR197_PIXEL_COUNTERS_SHIFT
27384 #define CSI_CSICR197_PIXEL_COUNTERS(x)     CSI_CR197_PIXEL_COUNTERS(x)
27385 #define CSI_CSICR198_PIXEL_COUNTERS_MASK     CSI_CR198_PIXEL_COUNTERS_MASK
27386 #define CSI_CSICR198_PIXEL_COUNTERS_SHIFT     CSI_CR198_PIXEL_COUNTERS_SHIFT
27387 #define CSI_CSICR198_PIXEL_COUNTERS(x)     CSI_CR198_PIXEL_COUNTERS(x)
27388 #define CSI_CSICR199_PIXEL_COUNTERS_MASK     CSI_CR199_PIXEL_COUNTERS_MASK
27389 #define CSI_CSICR199_PIXEL_COUNTERS_SHIFT     CSI_CR199_PIXEL_COUNTERS_SHIFT
27390 #define CSI_CSICR199_PIXEL_COUNTERS(x)     CSI_CR199_PIXEL_COUNTERS(x)
27391 #define CSI_CSICR200_PIXEL_COUNTERS_MASK     CSI_CR200_PIXEL_COUNTERS_MASK
27392 #define CSI_CSICR200_PIXEL_COUNTERS_SHIFT     CSI_CR200_PIXEL_COUNTERS_SHIFT
27393 #define CSI_CSICR200_PIXEL_COUNTERS(x)     CSI_CR200_PIXEL_COUNTERS(x)
27394 #define CSI_CSICR201_PIXEL_COUNTERS_MASK     CSI_CR201_PIXEL_COUNTERS_MASK
27395 #define CSI_CSICR201_PIXEL_COUNTERS_SHIFT     CSI_CR201_PIXEL_COUNTERS_SHIFT
27396 #define CSI_CSICR201_PIXEL_COUNTERS(x)     CSI_CR201_PIXEL_COUNTERS(x)
27397 #define CSI_CSICR202_PIXEL_COUNTERS_MASK     CSI_CR202_PIXEL_COUNTERS_MASK
27398 #define CSI_CSICR202_PIXEL_COUNTERS_SHIFT     CSI_CR202_PIXEL_COUNTERS_SHIFT
27399 #define CSI_CSICR202_PIXEL_COUNTERS(x)     CSI_CR202_PIXEL_COUNTERS(x)
27400 #define CSI_CSICR203_PIXEL_COUNTERS_MASK     CSI_CR203_PIXEL_COUNTERS_MASK
27401 #define CSI_CSICR203_PIXEL_COUNTERS_SHIFT     CSI_CR203_PIXEL_COUNTERS_SHIFT
27402 #define CSI_CSICR203_PIXEL_COUNTERS(x)     CSI_CR203_PIXEL_COUNTERS(x)
27403 #define CSI_CSICR204_PIXEL_COUNTERS_MASK     CSI_CR204_PIXEL_COUNTERS_MASK
27404 #define CSI_CSICR204_PIXEL_COUNTERS_SHIFT     CSI_CR204_PIXEL_COUNTERS_SHIFT
27405 #define CSI_CSICR204_PIXEL_COUNTERS(x)     CSI_CR204_PIXEL_COUNTERS(x)
27406 #define CSI_CSICR205_PIXEL_COUNTERS_MASK     CSI_CR205_PIXEL_COUNTERS_MASK
27407 #define CSI_CSICR205_PIXEL_COUNTERS_SHIFT     CSI_CR205_PIXEL_COUNTERS_SHIFT
27408 #define CSI_CSICR205_PIXEL_COUNTERS(x)     CSI_CR205_PIXEL_COUNTERS(x)
27409 #define CSI_CSICR206_PIXEL_COUNTERS_MASK     CSI_CR206_PIXEL_COUNTERS_MASK
27410 #define CSI_CSICR206_PIXEL_COUNTERS_SHIFT     CSI_CR206_PIXEL_COUNTERS_SHIFT
27411 #define CSI_CSICR206_PIXEL_COUNTERS(x)     CSI_CR206_PIXEL_COUNTERS(x)
27412 #define CSI_CSICR207_PIXEL_COUNTERS_MASK     CSI_CR207_PIXEL_COUNTERS_MASK
27413 #define CSI_CSICR207_PIXEL_COUNTERS_SHIFT     CSI_CR207_PIXEL_COUNTERS_SHIFT
27414 #define CSI_CSICR207_PIXEL_COUNTERS(x)     CSI_CR207_PIXEL_COUNTERS(x)
27415 #define CSI_CSICR208_PIXEL_COUNTERS_MASK     CSI_CR208_PIXEL_COUNTERS_MASK
27416 #define CSI_CSICR208_PIXEL_COUNTERS_SHIFT     CSI_CR208_PIXEL_COUNTERS_SHIFT
27417 #define CSI_CSICR208_PIXEL_COUNTERS(x)     CSI_CR208_PIXEL_COUNTERS(x)
27418 #define CSI_CSICR209_PIXEL_COUNTERS_MASK     CSI_CR209_PIXEL_COUNTERS_MASK
27419 #define CSI_CSICR209_PIXEL_COUNTERS_SHIFT     CSI_CR209_PIXEL_COUNTERS_SHIFT
27420 #define CSI_CSICR209_PIXEL_COUNTERS(x)     CSI_CR209_PIXEL_COUNTERS(x)
27421 #define CSI_CSICR210_PIXEL_COUNTERS_MASK     CSI_CR210_PIXEL_COUNTERS_MASK
27422 #define CSI_CSICR210_PIXEL_COUNTERS_SHIFT     CSI_CR210_PIXEL_COUNTERS_SHIFT
27423 #define CSI_CSICR210_PIXEL_COUNTERS(x)     CSI_CR210_PIXEL_COUNTERS(x)
27424 #define CSI_CSICR211_PIXEL_COUNTERS_MASK     CSI_CR211_PIXEL_COUNTERS_MASK
27425 #define CSI_CSICR211_PIXEL_COUNTERS_SHIFT     CSI_CR211_PIXEL_COUNTERS_SHIFT
27426 #define CSI_CSICR211_PIXEL_COUNTERS(x)     CSI_CR211_PIXEL_COUNTERS(x)
27427 #define CSI_CSICR212_PIXEL_COUNTERS_MASK     CSI_CR212_PIXEL_COUNTERS_MASK
27428 #define CSI_CSICR212_PIXEL_COUNTERS_SHIFT     CSI_CR212_PIXEL_COUNTERS_SHIFT
27429 #define CSI_CSICR212_PIXEL_COUNTERS(x)     CSI_CR212_PIXEL_COUNTERS(x)
27430 #define CSI_CSICR213_PIXEL_COUNTERS_MASK     CSI_CR213_PIXEL_COUNTERS_MASK
27431 #define CSI_CSICR213_PIXEL_COUNTERS_SHIFT     CSI_CR213_PIXEL_COUNTERS_SHIFT
27432 #define CSI_CSICR213_PIXEL_COUNTERS(x)     CSI_CR213_PIXEL_COUNTERS(x)
27433 #define CSI_CSICR214_PIXEL_COUNTERS_MASK     CSI_CR214_PIXEL_COUNTERS_MASK
27434 #define CSI_CSICR214_PIXEL_COUNTERS_SHIFT     CSI_CR214_PIXEL_COUNTERS_SHIFT
27435 #define CSI_CSICR214_PIXEL_COUNTERS(x)     CSI_CR214_PIXEL_COUNTERS(x)
27436 #define CSI_CSICR215_PIXEL_COUNTERS_MASK     CSI_CR215_PIXEL_COUNTERS_MASK
27437 #define CSI_CSICR215_PIXEL_COUNTERS_SHIFT     CSI_CR215_PIXEL_COUNTERS_SHIFT
27438 #define CSI_CSICR215_PIXEL_COUNTERS(x)     CSI_CR215_PIXEL_COUNTERS(x)
27439 #define CSI_CSICR216_PIXEL_COUNTERS_MASK     CSI_CR216_PIXEL_COUNTERS_MASK
27440 #define CSI_CSICR216_PIXEL_COUNTERS_SHIFT     CSI_CR216_PIXEL_COUNTERS_SHIFT
27441 #define CSI_CSICR216_PIXEL_COUNTERS(x)     CSI_CR216_PIXEL_COUNTERS(x)
27442 #define CSI_CSICR217_PIXEL_COUNTERS_MASK     CSI_CR217_PIXEL_COUNTERS_MASK
27443 #define CSI_CSICR217_PIXEL_COUNTERS_SHIFT     CSI_CR217_PIXEL_COUNTERS_SHIFT
27444 #define CSI_CSICR217_PIXEL_COUNTERS(x)     CSI_CR217_PIXEL_COUNTERS(x)
27445 #define CSI_CSICR218_PIXEL_COUNTERS_MASK     CSI_CR218_PIXEL_COUNTERS_MASK
27446 #define CSI_CSICR218_PIXEL_COUNTERS_SHIFT     CSI_CR218_PIXEL_COUNTERS_SHIFT
27447 #define CSI_CSICR218_PIXEL_COUNTERS(x)     CSI_CR218_PIXEL_COUNTERS(x)
27448 #define CSI_CSICR219_PIXEL_COUNTERS_MASK     CSI_CR219_PIXEL_COUNTERS_MASK
27449 #define CSI_CSICR219_PIXEL_COUNTERS_SHIFT     CSI_CR219_PIXEL_COUNTERS_SHIFT
27450 #define CSI_CSICR219_PIXEL_COUNTERS(x)     CSI_CR219_PIXEL_COUNTERS(x)
27451 #define CSI_CSICR220_PIXEL_COUNTERS_MASK     CSI_CR220_PIXEL_COUNTERS_MASK
27452 #define CSI_CSICR220_PIXEL_COUNTERS_SHIFT     CSI_CR220_PIXEL_COUNTERS_SHIFT
27453 #define CSI_CSICR220_PIXEL_COUNTERS(x)     CSI_CR220_PIXEL_COUNTERS(x)
27454 #define CSI_CSICR221_PIXEL_COUNTERS_MASK     CSI_CR221_PIXEL_COUNTERS_MASK
27455 #define CSI_CSICR221_PIXEL_COUNTERS_SHIFT     CSI_CR221_PIXEL_COUNTERS_SHIFT
27456 #define CSI_CSICR221_PIXEL_COUNTERS(x)     CSI_CR221_PIXEL_COUNTERS(x)
27457 #define CSI_CSICR222_PIXEL_COUNTERS_MASK     CSI_CR222_PIXEL_COUNTERS_MASK
27458 #define CSI_CSICR222_PIXEL_COUNTERS_SHIFT     CSI_CR222_PIXEL_COUNTERS_SHIFT
27459 #define CSI_CSICR222_PIXEL_COUNTERS(x)     CSI_CR222_PIXEL_COUNTERS(x)
27460 #define CSI_CSICR223_PIXEL_COUNTERS_MASK     CSI_CR223_PIXEL_COUNTERS_MASK
27461 #define CSI_CSICR223_PIXEL_COUNTERS_SHIFT     CSI_CR223_PIXEL_COUNTERS_SHIFT
27462 #define CSI_CSICR223_PIXEL_COUNTERS(x)     CSI_CR223_PIXEL_COUNTERS(x)
27463 #define CSI_CSICR224_PIXEL_COUNTERS_MASK     CSI_CR224_PIXEL_COUNTERS_MASK
27464 #define CSI_CSICR224_PIXEL_COUNTERS_SHIFT     CSI_CR224_PIXEL_COUNTERS_SHIFT
27465 #define CSI_CSICR224_PIXEL_COUNTERS(x)     CSI_CR224_PIXEL_COUNTERS(x)
27466 #define CSI_CSICR225_PIXEL_COUNTERS_MASK     CSI_CR225_PIXEL_COUNTERS_MASK
27467 #define CSI_CSICR225_PIXEL_COUNTERS_SHIFT     CSI_CR225_PIXEL_COUNTERS_SHIFT
27468 #define CSI_CSICR225_PIXEL_COUNTERS(x)     CSI_CR225_PIXEL_COUNTERS(x)
27469 #define CSI_CSICR226_PIXEL_COUNTERS_MASK     CSI_CR226_PIXEL_COUNTERS_MASK
27470 #define CSI_CSICR226_PIXEL_COUNTERS_SHIFT     CSI_CR226_PIXEL_COUNTERS_SHIFT
27471 #define CSI_CSICR226_PIXEL_COUNTERS(x)     CSI_CR226_PIXEL_COUNTERS(x)
27472 #define CSI_CSICR227_PIXEL_COUNTERS_MASK     CSI_CR227_PIXEL_COUNTERS_MASK
27473 #define CSI_CSICR227_PIXEL_COUNTERS_SHIFT     CSI_CR227_PIXEL_COUNTERS_SHIFT
27474 #define CSI_CSICR227_PIXEL_COUNTERS(x)     CSI_CR227_PIXEL_COUNTERS(x)
27475 #define CSI_CSICR228_PIXEL_COUNTERS_MASK     CSI_CR228_PIXEL_COUNTERS_MASK
27476 #define CSI_CSICR228_PIXEL_COUNTERS_SHIFT     CSI_CR228_PIXEL_COUNTERS_SHIFT
27477 #define CSI_CSICR228_PIXEL_COUNTERS(x)     CSI_CR228_PIXEL_COUNTERS(x)
27478 #define CSI_CSICR229_PIXEL_COUNTERS_MASK     CSI_CR229_PIXEL_COUNTERS_MASK
27479 #define CSI_CSICR229_PIXEL_COUNTERS_SHIFT     CSI_CR229_PIXEL_COUNTERS_SHIFT
27480 #define CSI_CSICR229_PIXEL_COUNTERS(x)     CSI_CR229_PIXEL_COUNTERS(x)
27481 #define CSI_CSICR230_PIXEL_COUNTERS_MASK     CSI_CR230_PIXEL_COUNTERS_MASK
27482 #define CSI_CSICR230_PIXEL_COUNTERS_SHIFT     CSI_CR230_PIXEL_COUNTERS_SHIFT
27483 #define CSI_CSICR230_PIXEL_COUNTERS(x)     CSI_CR230_PIXEL_COUNTERS(x)
27484 #define CSI_CSICR231_PIXEL_COUNTERS_MASK     CSI_CR231_PIXEL_COUNTERS_MASK
27485 #define CSI_CSICR231_PIXEL_COUNTERS_SHIFT     CSI_CR231_PIXEL_COUNTERS_SHIFT
27486 #define CSI_CSICR231_PIXEL_COUNTERS(x)     CSI_CR231_PIXEL_COUNTERS(x)
27487 #define CSI_CSICR232_PIXEL_COUNTERS_MASK     CSI_CR232_PIXEL_COUNTERS_MASK
27488 #define CSI_CSICR232_PIXEL_COUNTERS_SHIFT     CSI_CR232_PIXEL_COUNTERS_SHIFT
27489 #define CSI_CSICR232_PIXEL_COUNTERS(x)     CSI_CR232_PIXEL_COUNTERS(x)
27490 #define CSI_CSICR233_PIXEL_COUNTERS_MASK     CSI_CR233_PIXEL_COUNTERS_MASK
27491 #define CSI_CSICR233_PIXEL_COUNTERS_SHIFT     CSI_CR233_PIXEL_COUNTERS_SHIFT
27492 #define CSI_CSICR233_PIXEL_COUNTERS(x)     CSI_CR233_PIXEL_COUNTERS(x)
27493 #define CSI_CSICR234_PIXEL_COUNTERS_MASK     CSI_CR234_PIXEL_COUNTERS_MASK
27494 #define CSI_CSICR234_PIXEL_COUNTERS_SHIFT     CSI_CR234_PIXEL_COUNTERS_SHIFT
27495 #define CSI_CSICR234_PIXEL_COUNTERS(x)     CSI_CR234_PIXEL_COUNTERS(x)
27496 #define CSI_CSICR235_PIXEL_COUNTERS_MASK     CSI_CR235_PIXEL_COUNTERS_MASK
27497 #define CSI_CSICR235_PIXEL_COUNTERS_SHIFT     CSI_CR235_PIXEL_COUNTERS_SHIFT
27498 #define CSI_CSICR235_PIXEL_COUNTERS(x)     CSI_CR235_PIXEL_COUNTERS(x)
27499 #define CSI_CSICR236_PIXEL_COUNTERS_MASK     CSI_CR236_PIXEL_COUNTERS_MASK
27500 #define CSI_CSICR236_PIXEL_COUNTERS_SHIFT     CSI_CR236_PIXEL_COUNTERS_SHIFT
27501 #define CSI_CSICR236_PIXEL_COUNTERS(x)     CSI_CR236_PIXEL_COUNTERS(x)
27502 #define CSI_CSICR237_PIXEL_COUNTERS_MASK     CSI_CR237_PIXEL_COUNTERS_MASK
27503 #define CSI_CSICR237_PIXEL_COUNTERS_SHIFT     CSI_CR237_PIXEL_COUNTERS_SHIFT
27504 #define CSI_CSICR237_PIXEL_COUNTERS(x)     CSI_CR237_PIXEL_COUNTERS(x)
27505 #define CSI_CSICR238_PIXEL_COUNTERS_MASK     CSI_CR238_PIXEL_COUNTERS_MASK
27506 #define CSI_CSICR238_PIXEL_COUNTERS_SHIFT     CSI_CR238_PIXEL_COUNTERS_SHIFT
27507 #define CSI_CSICR238_PIXEL_COUNTERS(x)     CSI_CR238_PIXEL_COUNTERS(x)
27508 #define CSI_CSICR239_PIXEL_COUNTERS_MASK     CSI_CR239_PIXEL_COUNTERS_MASK
27509 #define CSI_CSICR239_PIXEL_COUNTERS_SHIFT     CSI_CR239_PIXEL_COUNTERS_SHIFT
27510 #define CSI_CSICR239_PIXEL_COUNTERS(x)     CSI_CR239_PIXEL_COUNTERS(x)
27511 #define CSI_CSICR240_PIXEL_COUNTERS_MASK     CSI_CR240_PIXEL_COUNTERS_MASK
27512 #define CSI_CSICR240_PIXEL_COUNTERS_SHIFT     CSI_CR240_PIXEL_COUNTERS_SHIFT
27513 #define CSI_CSICR240_PIXEL_COUNTERS(x)     CSI_CR240_PIXEL_COUNTERS(x)
27514 #define CSI_CSICR241_PIXEL_COUNTERS_MASK     CSI_CR241_PIXEL_COUNTERS_MASK
27515 #define CSI_CSICR241_PIXEL_COUNTERS_SHIFT     CSI_CR241_PIXEL_COUNTERS_SHIFT
27516 #define CSI_CSICR241_PIXEL_COUNTERS(x)     CSI_CR241_PIXEL_COUNTERS(x)
27517 #define CSI_CSICR242_PIXEL_COUNTERS_MASK     CSI_CR242_PIXEL_COUNTERS_MASK
27518 #define CSI_CSICR242_PIXEL_COUNTERS_SHIFT     CSI_CR242_PIXEL_COUNTERS_SHIFT
27519 #define CSI_CSICR242_PIXEL_COUNTERS(x)     CSI_CR242_PIXEL_COUNTERS(x)
27520 #define CSI_CSICR243_PIXEL_COUNTERS_MASK     CSI_CR243_PIXEL_COUNTERS_MASK
27521 #define CSI_CSICR243_PIXEL_COUNTERS_SHIFT     CSI_CR243_PIXEL_COUNTERS_SHIFT
27522 #define CSI_CSICR243_PIXEL_COUNTERS(x)     CSI_CR243_PIXEL_COUNTERS(x)
27523 #define CSI_CSICR244_PIXEL_COUNTERS_MASK     CSI_CR244_PIXEL_COUNTERS_MASK
27524 #define CSI_CSICR244_PIXEL_COUNTERS_SHIFT     CSI_CR244_PIXEL_COUNTERS_SHIFT
27525 #define CSI_CSICR244_PIXEL_COUNTERS(x)     CSI_CR244_PIXEL_COUNTERS(x)
27526 #define CSI_CSICR245_PIXEL_COUNTERS_MASK     CSI_CR245_PIXEL_COUNTERS_MASK
27527 #define CSI_CSICR245_PIXEL_COUNTERS_SHIFT     CSI_CR245_PIXEL_COUNTERS_SHIFT
27528 #define CSI_CSICR245_PIXEL_COUNTERS(x)     CSI_CR245_PIXEL_COUNTERS(x)
27529 #define CSI_CSICR246_PIXEL_COUNTERS_MASK     CSI_CR246_PIXEL_COUNTERS_MASK
27530 #define CSI_CSICR246_PIXEL_COUNTERS_SHIFT     CSI_CR246_PIXEL_COUNTERS_SHIFT
27531 #define CSI_CSICR246_PIXEL_COUNTERS(x)     CSI_CR246_PIXEL_COUNTERS(x)
27532 #define CSI_CSICR247_PIXEL_COUNTERS_MASK     CSI_CR247_PIXEL_COUNTERS_MASK
27533 #define CSI_CSICR247_PIXEL_COUNTERS_SHIFT     CSI_CR247_PIXEL_COUNTERS_SHIFT
27534 #define CSI_CSICR247_PIXEL_COUNTERS(x)     CSI_CR247_PIXEL_COUNTERS(x)
27535 #define CSI_CSICR248_PIXEL_COUNTERS_MASK     CSI_CR248_PIXEL_COUNTERS_MASK
27536 #define CSI_CSICR248_PIXEL_COUNTERS_SHIFT     CSI_CR248_PIXEL_COUNTERS_SHIFT
27537 #define CSI_CSICR248_PIXEL_COUNTERS(x)     CSI_CR248_PIXEL_COUNTERS(x)
27538 #define CSI_CSICR249_PIXEL_COUNTERS_MASK     CSI_CR249_PIXEL_COUNTERS_MASK
27539 #define CSI_CSICR249_PIXEL_COUNTERS_SHIFT     CSI_CR249_PIXEL_COUNTERS_SHIFT
27540 #define CSI_CSICR249_PIXEL_COUNTERS(x)     CSI_CR249_PIXEL_COUNTERS(x)
27541 #define CSI_CSICR250_PIXEL_COUNTERS_MASK     CSI_CR250_PIXEL_COUNTERS_MASK
27542 #define CSI_CSICR250_PIXEL_COUNTERS_SHIFT     CSI_CR250_PIXEL_COUNTERS_SHIFT
27543 #define CSI_CSICR250_PIXEL_COUNTERS(x)     CSI_CR250_PIXEL_COUNTERS(x)
27544 #define CSI_CSICR251_PIXEL_COUNTERS_MASK     CSI_CR251_PIXEL_COUNTERS_MASK
27545 #define CSI_CSICR251_PIXEL_COUNTERS_SHIFT     CSI_CR251_PIXEL_COUNTERS_SHIFT
27546 #define CSI_CSICR251_PIXEL_COUNTERS(x)     CSI_CR251_PIXEL_COUNTERS(x)
27547 #define CSI_CSICR252_PIXEL_COUNTERS_MASK     CSI_CR252_PIXEL_COUNTERS_MASK
27548 #define CSI_CSICR252_PIXEL_COUNTERS_SHIFT     CSI_CR252_PIXEL_COUNTERS_SHIFT
27549 #define CSI_CSICR252_PIXEL_COUNTERS(x)     CSI_CR252_PIXEL_COUNTERS(x)
27550 #define CSI_CSICR253_PIXEL_COUNTERS_MASK     CSI_CR253_PIXEL_COUNTERS_MASK
27551 #define CSI_CSICR253_PIXEL_COUNTERS_SHIFT     CSI_CR253_PIXEL_COUNTERS_SHIFT
27552 #define CSI_CSICR253_PIXEL_COUNTERS(x)     CSI_CR253_PIXEL_COUNTERS(x)
27553 #define CSI_CSICR254_PIXEL_COUNTERS_MASK     CSI_CR254_PIXEL_COUNTERS_MASK
27554 #define CSI_CSICR254_PIXEL_COUNTERS_SHIFT     CSI_CR254_PIXEL_COUNTERS_SHIFT
27555 #define CSI_CSICR254_PIXEL_COUNTERS(x)     CSI_CR254_PIXEL_COUNTERS(x)
27556 #define CSI_CSICR255_PIXEL_COUNTERS_MASK     CSI_CR255_PIXEL_COUNTERS_MASK
27557 #define CSI_CSICR255_PIXEL_COUNTERS_SHIFT     CSI_CR255_PIXEL_COUNTERS_SHIFT
27558 #define CSI_CSICR255_PIXEL_COUNTERS(x)     CSI_CR255_PIXEL_COUNTERS(x)
27559 #define CSI_CSICR256_PIXEL_COUNTERS_MASK     CSI_CR256_PIXEL_COUNTERS_MASK
27560 #define CSI_CSICR256_PIXEL_COUNTERS_SHIFT     CSI_CR256_PIXEL_COUNTERS_SHIFT
27561 #define CSI_CSICR256_PIXEL_COUNTERS(x)     CSI_CR256_PIXEL_COUNTERS(x)
27562 #define CSI_CSICR257_PIXEL_COUNTERS_MASK     CSI_CR257_PIXEL_COUNTERS_MASK
27563 #define CSI_CSICR257_PIXEL_COUNTERS_SHIFT     CSI_CR257_PIXEL_COUNTERS_SHIFT
27564 #define CSI_CSICR257_PIXEL_COUNTERS(x)     CSI_CR257_PIXEL_COUNTERS(x)
27565 #define CSI_CSICR258_PIXEL_COUNTERS_MASK     CSI_CR258_PIXEL_COUNTERS_MASK
27566 #define CSI_CSICR258_PIXEL_COUNTERS_SHIFT     CSI_CR258_PIXEL_COUNTERS_SHIFT
27567 #define CSI_CSICR258_PIXEL_COUNTERS(x)     CSI_CR258_PIXEL_COUNTERS(x)
27568 #define CSI_CSICR259_PIXEL_COUNTERS_MASK     CSI_CR259_PIXEL_COUNTERS_MASK
27569 #define CSI_CSICR259_PIXEL_COUNTERS_SHIFT     CSI_CR259_PIXEL_COUNTERS_SHIFT
27570 #define CSI_CSICR259_PIXEL_COUNTERS(x)     CSI_CR259_PIXEL_COUNTERS(x)
27571 #define CSI_CSICR260_PIXEL_COUNTERS_MASK     CSI_CR260_PIXEL_COUNTERS_MASK
27572 #define CSI_CSICR260_PIXEL_COUNTERS_SHIFT     CSI_CR260_PIXEL_COUNTERS_SHIFT
27573 #define CSI_CSICR260_PIXEL_COUNTERS(x)     CSI_CR260_PIXEL_COUNTERS(x)
27574 #define CSI_CSICR261_PIXEL_COUNTERS_MASK     CSI_CR261_PIXEL_COUNTERS_MASK
27575 #define CSI_CSICR261_PIXEL_COUNTERS_SHIFT     CSI_CR261_PIXEL_COUNTERS_SHIFT
27576 #define CSI_CSICR261_PIXEL_COUNTERS(x)     CSI_CR261_PIXEL_COUNTERS(x)
27577 #define CSI_CSICR262_PIXEL_COUNTERS_MASK     CSI_CR262_PIXEL_COUNTERS_MASK
27578 #define CSI_CSICR262_PIXEL_COUNTERS_SHIFT     CSI_CR262_PIXEL_COUNTERS_SHIFT
27579 #define CSI_CSICR262_PIXEL_COUNTERS(x)     CSI_CR262_PIXEL_COUNTERS(x)
27580 #define CSI_CSICR263_PIXEL_COUNTERS_MASK     CSI_CR263_PIXEL_COUNTERS_MASK
27581 #define CSI_CSICR263_PIXEL_COUNTERS_SHIFT     CSI_CR263_PIXEL_COUNTERS_SHIFT
27582 #define CSI_CSICR263_PIXEL_COUNTERS(x)     CSI_CR263_PIXEL_COUNTERS(x)
27583 #define CSI_CSICR264_PIXEL_COUNTERS_MASK     CSI_CR264_PIXEL_COUNTERS_MASK
27584 #define CSI_CSICR264_PIXEL_COUNTERS_SHIFT     CSI_CR264_PIXEL_COUNTERS_SHIFT
27585 #define CSI_CSICR264_PIXEL_COUNTERS(x)     CSI_CR264_PIXEL_COUNTERS(x)
27586 #define CSI_CSICR265_PIXEL_COUNTERS_MASK     CSI_CR265_PIXEL_COUNTERS_MASK
27587 #define CSI_CSICR265_PIXEL_COUNTERS_SHIFT     CSI_CR265_PIXEL_COUNTERS_SHIFT
27588 #define CSI_CSICR265_PIXEL_COUNTERS(x)     CSI_CR265_PIXEL_COUNTERS(x)
27589 #define CSI_CSICR266_PIXEL_COUNTERS_MASK     CSI_CR266_PIXEL_COUNTERS_MASK
27590 #define CSI_CSICR266_PIXEL_COUNTERS_SHIFT     CSI_CR266_PIXEL_COUNTERS_SHIFT
27591 #define CSI_CSICR266_PIXEL_COUNTERS(x)     CSI_CR266_PIXEL_COUNTERS(x)
27592 #define CSI_CSICR267_PIXEL_COUNTERS_MASK     CSI_CR267_PIXEL_COUNTERS_MASK
27593 #define CSI_CSICR267_PIXEL_COUNTERS_SHIFT     CSI_CR267_PIXEL_COUNTERS_SHIFT
27594 #define CSI_CSICR267_PIXEL_COUNTERS(x)     CSI_CR267_PIXEL_COUNTERS(x)
27595 #define CSI_CSICR268_PIXEL_COUNTERS_MASK     CSI_CR268_PIXEL_COUNTERS_MASK
27596 #define CSI_CSICR268_PIXEL_COUNTERS_SHIFT     CSI_CR268_PIXEL_COUNTERS_SHIFT
27597 #define CSI_CSICR268_PIXEL_COUNTERS(x)     CSI_CR268_PIXEL_COUNTERS(x)
27598 #define CSI_CSICR269_PIXEL_COUNTERS_MASK     CSI_CR269_PIXEL_COUNTERS_MASK
27599 #define CSI_CSICR269_PIXEL_COUNTERS_SHIFT     CSI_CR269_PIXEL_COUNTERS_SHIFT
27600 #define CSI_CSICR269_PIXEL_COUNTERS(x)     CSI_CR269_PIXEL_COUNTERS(x)
27601 #define CSI_CSICR270_PIXEL_COUNTERS_MASK     CSI_CR270_PIXEL_COUNTERS_MASK
27602 #define CSI_CSICR270_PIXEL_COUNTERS_SHIFT     CSI_CR270_PIXEL_COUNTERS_SHIFT
27603 #define CSI_CSICR270_PIXEL_COUNTERS(x)     CSI_CR270_PIXEL_COUNTERS(x)
27604 #define CSI_CSICR271_PIXEL_COUNTERS_MASK     CSI_CR271_PIXEL_COUNTERS_MASK
27605 #define CSI_CSICR271_PIXEL_COUNTERS_SHIFT     CSI_CR271_PIXEL_COUNTERS_SHIFT
27606 #define CSI_CSICR271_PIXEL_COUNTERS(x)     CSI_CR271_PIXEL_COUNTERS(x)
27607 #define CSI_CSICR272_PIXEL_COUNTERS_MASK     CSI_CR272_PIXEL_COUNTERS_MASK
27608 #define CSI_CSICR272_PIXEL_COUNTERS_SHIFT     CSI_CR272_PIXEL_COUNTERS_SHIFT
27609 #define CSI_CSICR272_PIXEL_COUNTERS(x)     CSI_CR272_PIXEL_COUNTERS(x)
27610 #define CSI_CSICR273_PIXEL_COUNTERS_MASK     CSI_CR273_PIXEL_COUNTERS_MASK
27611 #define CSI_CSICR273_PIXEL_COUNTERS_SHIFT     CSI_CR273_PIXEL_COUNTERS_SHIFT
27612 #define CSI_CSICR273_PIXEL_COUNTERS(x)     CSI_CR273_PIXEL_COUNTERS(x)
27613 #define CSI_CSICR274_PIXEL_COUNTERS_MASK     CSI_CR274_PIXEL_COUNTERS_MASK
27614 #define CSI_CSICR274_PIXEL_COUNTERS_SHIFT     CSI_CR274_PIXEL_COUNTERS_SHIFT
27615 #define CSI_CSICR274_PIXEL_COUNTERS(x)     CSI_CR274_PIXEL_COUNTERS(x)
27616 #define CSI_CSICR275_PIXEL_COUNTERS_MASK     CSI_CR275_PIXEL_COUNTERS_MASK
27617 #define CSI_CSICR275_PIXEL_COUNTERS_SHIFT     CSI_CR275_PIXEL_COUNTERS_SHIFT
27618 #define CSI_CSICR275_PIXEL_COUNTERS(x)     CSI_CR275_PIXEL_COUNTERS(x)
27619 #define CSI_CSICR276_PIXEL_COUNTERS_MASK     CSI_CR276_PIXEL_COUNTERS_MASK
27620 #define CSI_CSICR276_PIXEL_COUNTERS_SHIFT     CSI_CR276_PIXEL_COUNTERS_SHIFT
27621 #define CSI_CSICR276_PIXEL_COUNTERS(x)     CSI_CR276_PIXEL_COUNTERS(x)
27622 
27623 
27624 /*!
27625  * @}
27626  */ /* end of group CSI_Peripheral_Access_Layer */
27627 
27628 
27629 /* ----------------------------------------------------------------------------
27630    -- DAC Peripheral Access Layer
27631    ---------------------------------------------------------------------------- */
27632 
27633 /*!
27634  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
27635  * @{
27636  */
27637 
27638 /** DAC - Register Layout Typedef */
27639 typedef struct {
27640   __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
27641   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
27642   __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
27643   __IO uint32_t CR;                                /**< DAC Status and Control Register, offset: 0xC */
27644   __I  uint32_t PTR;                               /**< DAC FIFO Pointer Register, offset: 0x10 */
27645   __IO uint32_t CR2;                               /**< DAC Status and Control Register 2, offset: 0x14 */
27646 } DAC_Type;
27647 
27648 /* ----------------------------------------------------------------------------
27649    -- DAC Register Masks
27650    ---------------------------------------------------------------------------- */
27651 
27652 /*!
27653  * @addtogroup DAC_Register_Masks DAC Register Masks
27654  * @{
27655  */
27656 
27657 /*! @name VERID - Version Identifier Register */
27658 /*! @{ */
27659 
27660 #define DAC_VERID_FEATURE_MASK                   (0xFFFFU)
27661 #define DAC_VERID_FEATURE_SHIFT                  (0U)
27662 /*! FEATURE - Feature Identification Number
27663  *  0b0000000000000000..Standard feature set
27664  *  0b0000000000000001..C40 feature set
27665  *  0b0000000000000010..5V DAC feature set
27666  *  0b0000000000000100..ADC BIST feature set
27667  */
27668 #define DAC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
27669 
27670 #define DAC_VERID_MINOR_MASK                     (0xFF0000U)
27671 #define DAC_VERID_MINOR_SHIFT                    (16U)
27672 /*! MINOR - Minor version number
27673  */
27674 #define DAC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
27675 
27676 #define DAC_VERID_MAJOR_MASK                     (0xFF000000U)
27677 #define DAC_VERID_MAJOR_SHIFT                    (24U)
27678 /*! MAJOR - Major version number
27679  */
27680 #define DAC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
27681 /*! @} */
27682 
27683 /*! @name PARAM - Parameter Register */
27684 /*! @{ */
27685 
27686 #define DAC_PARAM_FIFOSZ_MASK                    (0x7U)
27687 #define DAC_PARAM_FIFOSZ_SHIFT                   (0U)
27688 /*! FIFOSZ - FIFO size
27689  *  0b000..FIFO depth is 2
27690  *  0b001..FIFO depth is 4
27691  *  0b010..FIFO depth is 8
27692  *  0b011..FIFO depth is 16
27693  *  0b100..FIFO depth is 32
27694  *  0b101..FIFO depth is 64
27695  *  0b110..FIFO depth is 128
27696  *  0b111..FIFO depth is 256
27697  */
27698 #define DAC_PARAM_FIFOSZ(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
27699 /*! @} */
27700 
27701 /*! @name DATA - DAC Data Register */
27702 /*! @{ */
27703 
27704 #define DAC_DATA_DATA0_MASK                      (0xFFFU)
27705 #define DAC_DATA_DATA0_SHIFT                     (0U)
27706 /*! DATA0 - FIFO DATA0
27707  */
27708 #define DAC_DATA_DATA0(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
27709 /*! @} */
27710 
27711 /*! @name CR - DAC Status and Control Register */
27712 /*! @{ */
27713 
27714 #define DAC_CR_FULLF_MASK                        (0x1U)
27715 #define DAC_CR_FULLF_SHIFT                       (0U)
27716 /*! FULLF - Full Flag
27717  *  0b0..FIFO is not full.
27718  *  0b1..FIFO is full.
27719  */
27720 #define DAC_CR_FULLF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
27721 
27722 #define DAC_CR_NEMPTF_MASK                       (0x2U)
27723 #define DAC_CR_NEMPTF_SHIFT                      (1U)
27724 /*! NEMPTF - Nearly Empty Flag
27725  *  0b0..More than one data is available in the FIFO.
27726  *  0b1..One data is available in the FIFO.
27727  */
27728 #define DAC_CR_NEMPTF(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
27729 
27730 #define DAC_CR_WMF_MASK                          (0x4U)
27731 #define DAC_CR_WMF_SHIFT                         (2U)
27732 /*! WMF - FIFO Watermark Status Flag
27733  *  0b0..The DAC buffer read pointer has not reached the watermark level.
27734  *  0b1..The DAC buffer read pointer has reached the watermark level.
27735  */
27736 #define DAC_CR_WMF(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
27737 
27738 #define DAC_CR_UDFF_MASK                         (0x8U)
27739 #define DAC_CR_UDFF_SHIFT                        (3U)
27740 /*! UDFF - Underflow Flag
27741  *  0b0..No underflow has occurred since the last time the flag was cleared.
27742  *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
27743  */
27744 #define DAC_CR_UDFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
27745 
27746 #define DAC_CR_OVFF_MASK                         (0x10U)
27747 #define DAC_CR_OVFF_SHIFT                        (4U)
27748 /*! OVFF - Overflow Flag
27749  *  0b0..No overflow has occurred since the last time the flag was cleared.
27750  *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
27751  */
27752 #define DAC_CR_OVFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
27753 
27754 #define DAC_CR_FULLIE_MASK                       (0x100U)
27755 #define DAC_CR_FULLIE_SHIFT                      (8U)
27756 /*! FULLIE - Full Interrupt Enable
27757  *  0b0..FIFO Full interrupt is disabled.
27758  *  0b1..FIFO Full interrupt is enabled.
27759  */
27760 #define DAC_CR_FULLIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
27761 
27762 #define DAC_CR_EMPTIE_MASK                       (0x200U)
27763 #define DAC_CR_EMPTIE_SHIFT                      (9U)
27764 /*! EMPTIE - Nearly Empty Interrupt Enable
27765  *  0b0..FIFO Nearly Empty interrupt is disabled.
27766  *  0b1..FIFO Nearly Empty interrupt is enabled.
27767  */
27768 #define DAC_CR_EMPTIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
27769 
27770 #define DAC_CR_WTMIE_MASK                        (0x400U)
27771 #define DAC_CR_WTMIE_SHIFT                       (10U)
27772 /*! WTMIE - Watermark Interrupt Enable
27773  *  0b0..Watermark interrupt is disabled.
27774  *  0b1..Watermark interrupt is enabled.
27775  */
27776 #define DAC_CR_WTMIE(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
27777 
27778 #define DAC_CR_SWTRG_MASK                        (0x1000U)
27779 #define DAC_CR_SWTRG_SHIFT                       (12U)
27780 /*! SWTRG - DAC Software Trigger
27781  *  0b0..The DAC soft trigger is not valid.
27782  *  0b1..The DAC soft trigger is valid.
27783  */
27784 #define DAC_CR_SWTRG(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
27785 
27786 #define DAC_CR_TRGSEL_MASK                       (0x2000U)
27787 #define DAC_CR_TRGSEL_SHIFT                      (13U)
27788 /*! TRGSEL - DAC Trigger Select
27789  *  0b0..The DAC hardware trigger is selected.
27790  *  0b1..The DAC software trigger is selected.
27791  */
27792 #define DAC_CR_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
27793 
27794 #define DAC_CR_DACRFS_MASK                       (0x4000U)
27795 #define DAC_CR_DACRFS_SHIFT                      (14U)
27796 /*! DACRFS - DAC Reference Select
27797  *  0b0..The DAC selects DACREF_1 as the reference voltage.
27798  *  0b1..The DAC selects DACREF_2 as the reference voltage.
27799  */
27800 #define DAC_CR_DACRFS(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
27801 
27802 #define DAC_CR_DACEN_MASK                        (0x8000U)
27803 #define DAC_CR_DACEN_SHIFT                       (15U)
27804 /*! DACEN - DAC Enable
27805  *  0b0..The DAC system is disabled.
27806  *  0b1..The DAC system is enabled.
27807  */
27808 #define DAC_CR_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
27809 
27810 #define DAC_CR_FIFOEN_MASK                       (0x10000U)
27811 #define DAC_CR_FIFOEN_SHIFT                      (16U)
27812 /*! FIFOEN - FIFO Enable
27813  *  0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
27814  *  0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
27815  */
27816 #define DAC_CR_FIFOEN(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
27817 
27818 #define DAC_CR_SWMD_MASK                         (0x20000U)
27819 #define DAC_CR_SWMD_SHIFT                        (17U)
27820 /*! SWMD - DAC FIFO Mode Select
27821  *  0b0..Normal mode
27822  *  0b1..Swing back mode
27823  */
27824 #define DAC_CR_SWMD(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
27825 
27826 #define DAC_CR_UVIE_MASK                         (0x40000U)
27827 #define DAC_CR_UVIE_SHIFT                        (18U)
27828 /*! UVIE - Underflow and overflow interrupt enable
27829  *  0b0..Underflow and overflow interrupt is disabled.
27830  *  0b1..Underflow and overflow interrupt is enabled.
27831  */
27832 #define DAC_CR_UVIE(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
27833 
27834 #define DAC_CR_FIFORST_MASK                      (0x200000U)
27835 #define DAC_CR_FIFORST_SHIFT                     (21U)
27836 /*! FIFORST - FIFO Reset
27837  *  0b0..No effect
27838  *  0b1..FIFO reset
27839  */
27840 #define DAC_CR_FIFORST(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
27841 
27842 #define DAC_CR_SWRST_MASK                        (0x400000U)
27843 #define DAC_CR_SWRST_SHIFT                       (22U)
27844 /*! SWRST - Software reset
27845  */
27846 #define DAC_CR_SWRST(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
27847 
27848 #define DAC_CR_DMAEN_MASK                        (0x800000U)
27849 #define DAC_CR_DMAEN_SHIFT                       (23U)
27850 /*! DMAEN - DMA Enable Select
27851  *  0b0..DMA is disabled.
27852  *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
27853  *       interrupts will not be presented on this module at the same time.
27854  */
27855 #define DAC_CR_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
27856 
27857 #define DAC_CR_WML_MASK                          (0xFF000000U)
27858 #define DAC_CR_WML_SHIFT                         (24U)
27859 /*! WML - Watermark Level Select
27860  */
27861 #define DAC_CR_WML(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
27862 /*! @} */
27863 
27864 /*! @name PTR - DAC FIFO Pointer Register */
27865 /*! @{ */
27866 
27867 #define DAC_PTR_DACWFP_MASK                      (0xFFU)
27868 #define DAC_PTR_DACWFP_SHIFT                     (0U)
27869 /*! DACWFP - DACWFP
27870  */
27871 #define DAC_PTR_DACWFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
27872 
27873 #define DAC_PTR_DACRFP_MASK                      (0xFF0000U)
27874 #define DAC_PTR_DACRFP_SHIFT                     (16U)
27875 /*! DACRFP - DACRFP
27876  */
27877 #define DAC_PTR_DACRFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
27878 /*! @} */
27879 
27880 /*! @name CR2 - DAC Status and Control Register 2 */
27881 /*! @{ */
27882 
27883 #define DAC_CR2_BFEN_MASK                        (0x1U)
27884 #define DAC_CR2_BFEN_SHIFT                       (0U)
27885 /*! BFEN - Buffer Enable
27886  *  0b0..Opamp is not used as buffer
27887  *  0b1..Opamp is used as buffer
27888  */
27889 #define DAC_CR2_BFEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
27890 
27891 #define DAC_CR2_OEN_MASK                         (0x2U)
27892 #define DAC_CR2_OEN_SHIFT                        (1U)
27893 /*! OEN - Optional Enable
27894  *  0b0..Output buffer is not bypassed
27895  *  0b1..Output buffer is bypassed
27896  */
27897 #define DAC_CR2_OEN(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
27898 
27899 #define DAC_CR2_BFMS_MASK                        (0x4U)
27900 #define DAC_CR2_BFMS_SHIFT                       (2U)
27901 /*! BFMS - Buffer Middle Speed Select
27902  *  0b0..Buffer middle speed not selected
27903  *  0b1..Buffer middle speed selected
27904  */
27905 #define DAC_CR2_BFMS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
27906 
27907 #define DAC_CR2_BFHS_MASK                        (0x8U)
27908 #define DAC_CR2_BFHS_SHIFT                       (3U)
27909 /*! BFHS - Buffer High Speed Select
27910  *  0b0..Buffer high speed not selected
27911  *  0b1..Buffer high speed selected
27912  */
27913 #define DAC_CR2_BFHS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
27914 
27915 #define DAC_CR2_IREF2_MASK                       (0x10U)
27916 #define DAC_CR2_IREF2_SHIFT                      (4U)
27917 /*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
27918  *  0b0..Internal PTAT Current Reference not selected
27919  *  0b1..Internal PTAT Current Reference selected
27920  */
27921 #define DAC_CR2_IREF2(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
27922 
27923 #define DAC_CR2_IREF1_MASK                       (0x20U)
27924 #define DAC_CR2_IREF1_SHIFT                      (5U)
27925 /*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
27926  *  0b0..Internal ZTC Current Reference not selected
27927  *  0b1..Internal ZTC Current Reference selected
27928  */
27929 #define DAC_CR2_IREF1(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
27930 
27931 #define DAC_CR2_IREF_MASK                        (0x40U)
27932 #define DAC_CR2_IREF_SHIFT                       (6U)
27933 /*! IREF - Internal Current Reference Select
27934  *  0b0..Internal Current Reference not selected
27935  *  0b1..Internal Current Reference selected
27936  */
27937 #define DAC_CR2_IREF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
27938 /*! @} */
27939 
27940 
27941 /*!
27942  * @}
27943  */ /* end of group DAC_Register_Masks */
27944 
27945 
27946 /* DAC - Peripheral instance base addresses */
27947 /** Peripheral DAC base address */
27948 #define DAC_BASE                                 (0x40064000u)
27949 /** Peripheral DAC base pointer */
27950 #define DAC                                      ((DAC_Type *)DAC_BASE)
27951 /** Array initializer of DAC peripheral base addresses */
27952 #define DAC_BASE_ADDRS                           { DAC_BASE }
27953 /** Array initializer of DAC peripheral base pointers */
27954 #define DAC_BASE_PTRS                            { DAC }
27955 /** Interrupt vectors for the DAC peripheral type */
27956 #define DAC_IRQS                                 { DAC_IRQn }
27957 
27958 /*!
27959  * @}
27960  */ /* end of group DAC_Peripheral_Access_Layer */
27961 
27962 
27963 /* ----------------------------------------------------------------------------
27964    -- DCDC Peripheral Access Layer
27965    ---------------------------------------------------------------------------- */
27966 
27967 /*!
27968  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
27969  * @{
27970  */
27971 
27972 /** DCDC - Register Layout Typedef */
27973 typedef struct {
27974   __IO uint32_t CTRL0;                             /**< DCDC Control Register 0, offset: 0x0 */
27975   __IO uint32_t CTRL1;                             /**< DCDC Control Register 1, offset: 0x4 */
27976   __IO uint32_t REG0;                              /**< DCDC Register 0, offset: 0x8 */
27977   __IO uint32_t REG1;                              /**< DCDC Register 1, offset: 0xC */
27978   __IO uint32_t REG2;                              /**< DCDC Register 2, offset: 0x10 */
27979   __IO uint32_t REG3;                              /**< DCDC Register 3, offset: 0x14 */
27980   __IO uint32_t REG4;                              /**< DCDC Register 4, offset: 0x18 */
27981   __IO uint32_t REG5;                              /**< DCDC Register 5, offset: 0x1C */
27982   __IO uint32_t REG6;                              /**< DCDC Register 6, offset: 0x20 */
27983   __IO uint32_t REG7;                              /**< DCDC Register 7, offset: 0x24 */
27984   __IO uint32_t REG7P;                             /**< DCDC Register 7 plus, offset: 0x28 */
27985   __IO uint32_t REG8;                              /**< DCDC Register 8, offset: 0x2C */
27986   __IO uint32_t REG9;                              /**< DCDC Register 9, offset: 0x30 */
27987   __IO uint32_t REG10;                             /**< DCDC Register 10, offset: 0x34 */
27988   __IO uint32_t REG11;                             /**< DCDC Register 11, offset: 0x38 */
27989   __IO uint32_t REG12;                             /**< DCDC Register 12, offset: 0x3C */
27990   __IO uint32_t REG13;                             /**< DCDC Register 13, offset: 0x40 */
27991   __IO uint32_t REG14;                             /**< DCDC Register 14, offset: 0x44 */
27992   __IO uint32_t REG15;                             /**< DCDC Register 15, offset: 0x48 */
27993   __IO uint32_t REG16;                             /**< DCDC Register 16, offset: 0x4C */
27994   __IO uint32_t REG17;                             /**< DCDC Register 17, offset: 0x50 */
27995   __IO uint32_t REG18;                             /**< DCDC Register 18, offset: 0x54 */
27996   __IO uint32_t REG19;                             /**< DCDC Register 19, offset: 0x58 */
27997   __IO uint32_t REG20;                             /**< DCDC Register 20, offset: 0x5C */
27998   __IO uint32_t REG21;                             /**< DCDC Register 21, offset: 0x60 */
27999   __IO uint32_t REG22;                             /**< DCDC Register 22, offset: 0x64 */
28000   __IO uint32_t REG23;                             /**< DCDC Register 23, offset: 0x68 */
28001   __IO uint32_t REG24;                             /**< DCDC Register 24, offset: 0x6C */
28002 } DCDC_Type;
28003 
28004 /* ----------------------------------------------------------------------------
28005    -- DCDC Register Masks
28006    ---------------------------------------------------------------------------- */
28007 
28008 /*!
28009  * @addtogroup DCDC_Register_Masks DCDC Register Masks
28010  * @{
28011  */
28012 
28013 /*! @name CTRL0 - DCDC Control Register 0 */
28014 /*! @{ */
28015 
28016 #define DCDC_CTRL0_ENABLE_MASK                   (0x1U)
28017 #define DCDC_CTRL0_ENABLE_SHIFT                  (0U)
28018 /*! ENABLE
28019  *  0b0..Disable (Bypass)
28020  *  0b1..Enable
28021  */
28022 #define DCDC_CTRL0_ENABLE(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
28023 
28024 #define DCDC_CTRL0_DIG_EN_MASK                   (0x2U)
28025 #define DCDC_CTRL0_DIG_EN_SHIFT                  (1U)
28026 /*! DIG_EN
28027  *  0b0..Reserved
28028  *  0b1..Enable
28029  */
28030 #define DCDC_CTRL0_DIG_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
28031 
28032 #define DCDC_CTRL0_STBY_EN_MASK                  (0x4U)
28033 #define DCDC_CTRL0_STBY_EN_SHIFT                 (2U)
28034 /*! STBY_EN
28035  *  0b1..Enter into standby mode
28036  */
28037 #define DCDC_CTRL0_STBY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
28038 
28039 #define DCDC_CTRL0_LP_MODE_EN_MASK               (0x8U)
28040 #define DCDC_CTRL0_LP_MODE_EN_SHIFT              (3U)
28041 /*! LP_MODE_EN
28042  *  0b1..Enter into low-power mode
28043  */
28044 #define DCDC_CTRL0_LP_MODE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
28045 
28046 #define DCDC_CTRL0_STBY_LP_MODE_EN_MASK          (0x10U)
28047 #define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT         (4U)
28048 /*! STBY_LP_MODE_EN
28049  *  0b0..Disable DCDC entry into low-power mode from a GPC standby request
28050  *  0b1..Enable DCDC to enter into low-power mode from a GPC standby request
28051  */
28052 #define DCDC_CTRL0_STBY_LP_MODE_EN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
28053 
28054 #define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK          (0x20U)
28055 #define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT         (5U)
28056 /*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout
28057  *  0b0..Wait DCDC_OK for ACK
28058  *  0b1..Enable internal count for DCDC_OK timeout
28059  */
28060 #define DCDC_CTRL0_ENABLE_DCDC_CNT(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
28061 
28062 #define DCDC_CTRL0_TRIM_HOLD_MASK                (0x40U)
28063 #define DCDC_CTRL0_TRIM_HOLD_SHIFT               (6U)
28064 /*! TRIM_HOLD - Hold trim input
28065  *  0b0..Sample trim input
28066  *  0b1..Hold trim input
28067  */
28068 #define DCDC_CTRL0_TRIM_HOLD(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
28069 
28070 #define DCDC_CTRL0_DEBUG_BITS_MASK               (0x7FF80000U)
28071 #define DCDC_CTRL0_DEBUG_BITS_SHIFT              (19U)
28072 /*! DEBUG_BITS - DEBUG_BITS[11:0]
28073  */
28074 #define DCDC_CTRL0_DEBUG_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
28075 
28076 #define DCDC_CTRL0_CONTROL_MODE_MASK             (0x80000000U)
28077 #define DCDC_CTRL0_CONTROL_MODE_SHIFT            (31U)
28078 /*! CONTROL_MODE - Control mode
28079  *  0b0..Software control mode
28080  *  0b1..Hardware control mode (controlled by GPC Setpoints)
28081  */
28082 #define DCDC_CTRL0_CONTROL_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
28083 /*! @} */
28084 
28085 /*! @name CTRL1 - DCDC Control Register 1 */
28086 /*! @{ */
28087 
28088 #define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK           (0x1FU)
28089 #define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT          (0U)
28090 /*! VDD1P8CTRL_TRG
28091  *  0b11111..2.275V
28092  *  0b01100..1.8V
28093  *  0b00000..1.5V
28094  */
28095 #define DCDC_CTRL1_VDD1P8CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
28096 
28097 #define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK           (0x1F00U)
28098 #define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT          (8U)
28099 /*! VDD1P0CTRL_TRG
28100  *  0b11111..1.375V
28101  *  0b10000..1.0V
28102  *  0b00000..0.6V
28103  */
28104 #define DCDC_CTRL1_VDD1P0CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
28105 
28106 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK      (0x1F0000U)
28107 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT     (16U)
28108 /*! VDD1P8CTRL_STBY_TRG
28109  *  0b11111..2.3V
28110  *  0b01011..1.8V
28111  *  0b00000..1.525V
28112  */
28113 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
28114 
28115 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK      (0x1F000000U)
28116 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT     (24U)
28117 /*! VDD1P0CTRL_STBY_TRG
28118  *  0b11111..1.4V
28119  *  0b01111..1.0V
28120  *  0b00000..0.625V
28121  */
28122 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)
28123 /*! @} */
28124 
28125 /*! @name REG0 - DCDC Register 0 */
28126 /*! @{ */
28127 
28128 #define DCDC_REG0_PWD_ZCD_MASK                   (0x1U)
28129 #define DCDC_REG0_PWD_ZCD_SHIFT                  (0U)
28130 /*! PWD_ZCD - Power Down Zero Cross Detection
28131  *  0b0..Zero cross detetion function powered up
28132  *  0b1..Zero cross detetion function powered down
28133  */
28134 #define DCDC_REG0_PWD_ZCD(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
28135 
28136 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
28137 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT  (1U)
28138 /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
28139  *  0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal
28140  *       ring oscillator to 24M xtal automatically
28141  *  0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
28142  */
28143 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
28144 
28145 #define DCDC_REG0_SEL_CLK_MASK                   (0x4U)
28146 #define DCDC_REG0_SEL_CLK_SHIFT                  (2U)
28147 /*! SEL_CLK - Select Clock
28148  *  0b0..DCDC uses internal ring oscillator
28149  *  0b1..DCDC uses 24M xtal
28150  */
28151 #define DCDC_REG0_SEL_CLK(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
28152 
28153 #define DCDC_REG0_PWD_OSC_INT_MASK               (0x8U)
28154 #define DCDC_REG0_PWD_OSC_INT_SHIFT              (3U)
28155 /*! PWD_OSC_INT - Power down internal ring oscillator
28156  *  0b0..Internal ring oscillator powered up
28157  *  0b1..Internal ring oscillator powered down
28158  */
28159 #define DCDC_REG0_PWD_OSC_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
28160 
28161 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK           (0x10U)
28162 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT          (4U)
28163 /*! PWD_CUR_SNS_CMP - Power down signal of the current detector
28164  *  0b0..Current Detector powered up
28165  *  0b1..Current Detector powered down
28166  */
28167 #define DCDC_REG0_PWD_CUR_SNS_CMP(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
28168 
28169 #define DCDC_REG0_CUR_SNS_THRSH_MASK             (0xE0U)
28170 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT            (5U)
28171 /*! CUR_SNS_THRSH - Current Sense (detector) Threshold
28172  */
28173 #define DCDC_REG0_CUR_SNS_THRSH(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
28174 
28175 #define DCDC_REG0_PWD_OVERCUR_DET_MASK           (0x100U)
28176 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT          (8U)
28177 /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
28178  *  0b0..Overcurrent detection comparator is enabled
28179  *  0b1..Overcurrent detection comparator is disabled
28180  */
28181 #define DCDC_REG0_PWD_OVERCUR_DET(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
28182 
28183 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK       (0x800U)
28184 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT      (11U)
28185 /*! PWD_CMP_DCDC_IN_DET
28186  *  0b0..Low voltage detection comparator is enabled
28187  *  0b1..Low voltage detection comparator is disabled
28188  */
28189 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
28190 
28191 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK       (0x10000U)
28192 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT      (16U)
28193 /*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8
28194  *  0b0..Overvoltage detection comparator for the VDD1P8 output is enabled
28195  *  0b1..Overvoltage detection comparator for the VDD1P8 output is disabled
28196  */
28197 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
28198 
28199 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK       (0x20000U)
28200 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT      (17U)
28201 /*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0
28202  *  0b0..Overvoltage detection comparator for the VDD1P0 output is enabled
28203  *  0b1..Overvoltage detection comparator for the VDD1P0 output is disabled
28204  */
28205 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
28206 
28207 #define DCDC_REG0_LP_HIGH_HYS_MASK               (0x200000U)
28208 #define DCDC_REG0_LP_HIGH_HYS_SHIFT              (21U)
28209 /*! LP_HIGH_HYS - Low Power High Hysteric Value
28210  *  0b0..Adjust hysteretic value in low power to 12.5mV
28211  *  0b1..Adjust hysteretic value in low power to 25mV
28212  */
28213 #define DCDC_REG0_LP_HIGH_HYS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
28214 
28215 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
28216 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
28217 /*! PWD_CMP_OFFSET - power down the out-of-range detection comparator
28218  *  0b0..Out-of-range comparator powered up
28219  *  0b1..Out-of-range comparator powered down
28220  */
28221 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
28222 
28223 #define DCDC_REG0_XTALOK_DISABLE_MASK            (0x8000000U)
28224 #define DCDC_REG0_XTALOK_DISABLE_SHIFT           (27U)
28225 /*! XTALOK_DISABLE - Disable xtalok detection circuit
28226  *  0b0..Enable xtalok detection circuit
28227  *  0b1..Disable xtalok detection circuit and always outputs OK signal "1"
28228  */
28229 #define DCDC_REG0_XTALOK_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
28230 
28231 #define DCDC_REG0_XTAL_24M_OK_MASK               (0x20000000U)
28232 #define DCDC_REG0_XTAL_24M_OK_SHIFT              (29U)
28233 /*! XTAL_24M_OK - 24M XTAL OK
28234  *  0b0..DCDC uses internal ring oscillator
28235  *  0b1..DCDC uses xtal 24M
28236  */
28237 #define DCDC_REG0_XTAL_24M_OK(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
28238 
28239 #define DCDC_REG0_STS_DC_OK_MASK                 (0x80000000U)
28240 #define DCDC_REG0_STS_DC_OK_SHIFT                (31U)
28241 /*! STS_DC_OK - DCDC Output OK
28242  *  0b0..DCDC is settling
28243  *  0b1..DCDC already settled
28244  */
28245 #define DCDC_REG0_STS_DC_OK(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
28246 /*! @} */
28247 
28248 /*! @name REG1 - DCDC Register 1 */
28249 /*! @{ */
28250 
28251 #define DCDC_REG1_DM_CTRL_MASK                   (0x8U)
28252 #define DCDC_REG1_DM_CTRL_SHIFT                  (3U)
28253 /*! DM_CTRL - DM Control
28254  *  0b0..No change to ripple when the discontinuous current is present in DCM.
28255  *  0b1..Improves ripple when the inductor current goes to zero in DCM.
28256  */
28257 #define DCDC_REG1_DM_CTRL(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
28258 
28259 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK         (0x10U)
28260 #define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT        (4U)
28261 /*! RLOAD_REG_EN_LPSR - Load Resistor Enable
28262  *  0b0..Disconnect load resistor
28263  *  0b1..Connect load resistor
28264  */
28265 #define DCDC_REG1_RLOAD_REG_EN_LPSR(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
28266 
28267 #define DCDC_REG1_VBG_TRIM_MASK                  (0x7C0U)
28268 #define DCDC_REG1_VBG_TRIM_SHIFT                 (6U)
28269 /*! VBG_TRIM - Trim Bandgap Voltage
28270  *  0b00000..0.452V
28271  *  0b10000..0.5V
28272  *  0b11111..0.545V
28273  */
28274 #define DCDC_REG1_VBG_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
28275 
28276 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK           (0x1800U)
28277 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT          (11U)
28278 /*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias
28279  *  0b00..50nA
28280  *  0b01..100nA
28281  *  0b10..200nA
28282  *  0b11..400nA
28283  */
28284 #define DCDC_REG1_LP_CMP_ISRC_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
28285 
28286 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK    (0x8000000U)
28287 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
28288 /*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection
28289  */
28290 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
28291 
28292 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK    (0x10000000U)
28293 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
28294 /*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection
28295  */
28296 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
28297 
28298 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK       (0x20000000U)
28299 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT      (29U)
28300 /*! LOOPCTRL_EN_CM_HYST
28301  *  0b0..Disable hysteresis in switching converter common mode analog comparators
28302  *  0b1..Enable hysteresis in switching converter common mode analog comparators
28303  */
28304 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
28305 
28306 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK       (0x40000000U)
28307 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT      (30U)
28308 /*! LOOPCTRL_EN_DF_HYST
28309  *  0b0..Disable hysteresis in switching converter differential mode analog comparators
28310  *  0b1..Enable hysteresis in switching converter differential mode analog comparators
28311  */
28312 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
28313 /*! @} */
28314 
28315 /*! @name REG2 - DCDC Register 2 */
28316 /*! @{ */
28317 
28318 #define DCDC_REG2_LOOPCTRL_DC_C_MASK             (0x3U)
28319 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT            (0U)
28320 #define DCDC_REG2_LOOPCTRL_DC_C(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
28321 
28322 #define DCDC_REG2_LOOPCTRL_DC_R_MASK             (0x3CU)
28323 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT            (2U)
28324 #define DCDC_REG2_LOOPCTRL_DC_R(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
28325 
28326 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK            (0x1C0U)
28327 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT           (6U)
28328 #define DCDC_REG2_LOOPCTRL_DC_FF(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
28329 
28330 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK       (0xE00U)
28331 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT      (9U)
28332 /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale
28333  */
28334 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
28335 
28336 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK    (0x1000U)
28337 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
28338 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
28339 
28340 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK        (0x2000U)
28341 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT       (13U)
28342 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
28343 
28344 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK     (0x8000U)
28345 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT    (15U)
28346 #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
28347 
28348 #define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK      (0x3FF0000U)
28349 #define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT     (16U)
28350 #define DCDC_REG2_BATTMONITOR_BATT_VAL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
28351 
28352 #define DCDC_REG2_DCM_SET_CTRL_MASK              (0x10000000U)
28353 #define DCDC_REG2_DCM_SET_CTRL_SHIFT             (28U)
28354 /*! DCM_SET_CTRL - DCM Set Control
28355  */
28356 #define DCDC_REG2_DCM_SET_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
28357 
28358 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK       (0x40000000U)
28359 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT      (30U)
28360 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
28361 /*! @} */
28362 
28363 /*! @name REG3 - DCDC Register 3 */
28364 /*! @{ */
28365 
28366 #define DCDC_REG3_IN_BROWNOUT_MASK               (0x4000U)
28367 #define DCDC_REG3_IN_BROWNOUT_SHIFT              (14U)
28368 /*! IN_BROWNOUT
28369  *  0b1..DCDC_IN is lower than 2.6V
28370  */
28371 #define DCDC_REG3_IN_BROWNOUT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
28372 
28373 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
28374 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT  (15U)
28375 /*! OVERVOLT_VDD1P8_DET_OUT
28376  *  0b1..VDD1P8 Overvoltage
28377  */
28378 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
28379 
28380 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
28381 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT  (16U)
28382 /*! OVERVOLT_VDD1P0_DET_OUT
28383  *  0b1..VDD1P0 Overvoltage
28384  */
28385 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
28386 
28387 #define DCDC_REG3_OVERCUR_DETECT_OUT_MASK        (0x20000U)
28388 #define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT       (17U)
28389 /*! OVERCUR_DETECT_OUT
28390  *  0b1..Overcurrent
28391  */
28392 #define DCDC_REG3_OVERCUR_DETECT_OUT(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
28393 
28394 #define DCDC_REG3_ENABLE_FF_MASK                 (0x40000U)
28395 #define DCDC_REG3_ENABLE_FF_SHIFT                (18U)
28396 /*! ENABLE_FF
28397  *  0b1..Enable feed-forward (FF) function that can speed up transient settling.
28398  */
28399 #define DCDC_REG3_ENABLE_FF(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
28400 
28401 #define DCDC_REG3_DISABLE_PULSE_SKIP_MASK        (0x80000U)
28402 #define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT       (19U)
28403 /*! DISABLE_PULSE_SKIP - Disable Pulse Skip
28404  *  0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN
28405  */
28406 #define DCDC_REG3_DISABLE_PULSE_SKIP(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
28407 
28408 #define DCDC_REG3_DISABLE_IDLE_SKIP_MASK         (0x100000U)
28409 #define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT        (20U)
28410 /*! DISABLE_IDLE_SKIP
28411  *  0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output
28412  *       voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled
28413  *       (PWD_CMP_OFFSET=0).
28414  */
28415 #define DCDC_REG3_DISABLE_IDLE_SKIP(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
28416 
28417 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK  (0x200000U)
28418 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U)
28419 /*! DOUBLE_IBIAS_CMP_LP_LPSR
28420  *  0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode
28421  */
28422 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
28423 
28424 #define DCDC_REG3_REG_FBK_SEL_MASK               (0xC00000U)
28425 #define DCDC_REG3_REG_FBK_SEL_SHIFT              (22U)
28426 #define DCDC_REG3_REG_FBK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
28427 
28428 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK         (0x1000000U)
28429 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT        (24U)
28430 /*! MINPWR_DC_HALFCLK
28431  *  0b0..DCDC clock remains at full frequency for continuous mode
28432  *  0b1..DCDC clock set to half frequency for continuous mode
28433  */
28434 #define DCDC_REG3_MINPWR_DC_HALFCLK(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
28435 
28436 #define DCDC_REG3_MINPWR_HALF_FETS_MASK          (0x4000000U)
28437 #define DCDC_REG3_MINPWR_HALF_FETS_SHIFT         (26U)
28438 #define DCDC_REG3_MINPWR_HALF_FETS(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
28439 
28440 #define DCDC_REG3_MISC_DELAY_TIMING_MASK         (0x8000000U)
28441 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT        (27U)
28442 /*! MISC_DELAY_TIMING - Miscellaneous Delay Timing
28443  */
28444 #define DCDC_REG3_MISC_DELAY_TIMING(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
28445 
28446 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
28447 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT  (29U)
28448 /*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0
28449  *  0b0..Enable stepping for VDD1P0
28450  *  0b1..Disable stepping for VDD1P0
28451  */
28452 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
28453 
28454 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
28455 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT  (30U)
28456 /*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8
28457  *  0b0..Enable stepping for VDD1P8
28458  *  0b1..Disable stepping for VDD1P8
28459  */
28460 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)
28461 /*! @} */
28462 
28463 /*! @name REG4 - DCDC Register 4 */
28464 /*! @{ */
28465 
28466 #define DCDC_REG4_ENABLE_SP_MASK                 (0xFFFFU)
28467 #define DCDC_REG4_ENABLE_SP_SHIFT                (0U)
28468 #define DCDC_REG4_ENABLE_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)
28469 /*! @} */
28470 
28471 /*! @name REG5 - DCDC Register 5 */
28472 /*! @{ */
28473 
28474 #define DCDC_REG5_DIG_EN_SP_MASK                 (0xFFFFU)
28475 #define DCDC_REG5_DIG_EN_SP_SHIFT                (0U)
28476 #define DCDC_REG5_DIG_EN_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)
28477 /*! @} */
28478 
28479 /*! @name REG6 - DCDC Register 6 */
28480 /*! @{ */
28481 
28482 #define DCDC_REG6_LP_MODE_SP_MASK                (0xFFFFU)
28483 #define DCDC_REG6_LP_MODE_SP_SHIFT               (0U)
28484 #define DCDC_REG6_LP_MODE_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)
28485 /*! @} */
28486 
28487 /*! @name REG7 - DCDC Register 7 */
28488 /*! @{ */
28489 
28490 #define DCDC_REG7_STBY_EN_SP_MASK                (0xFFFFU)
28491 #define DCDC_REG7_STBY_EN_SP_SHIFT               (0U)
28492 #define DCDC_REG7_STBY_EN_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)
28493 /*! @} */
28494 
28495 /*! @name REG7P - DCDC Register 7 plus */
28496 /*! @{ */
28497 
28498 #define DCDC_REG7P_STBY_LP_MODE_SP_MASK          (0xFFFFU)
28499 #define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT         (0U)
28500 #define DCDC_REG7P_STBY_LP_MODE_SP(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)
28501 /*! @} */
28502 
28503 /*! @name REG8 - DCDC Register 8 */
28504 /*! @{ */
28505 
28506 #define DCDC_REG8_ANA_TRG_SP0_MASK               (0xFFFFFFFFU)
28507 #define DCDC_REG8_ANA_TRG_SP0_SHIFT              (0U)
28508 #define DCDC_REG8_ANA_TRG_SP0(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)
28509 /*! @} */
28510 
28511 /*! @name REG9 - DCDC Register 9 */
28512 /*! @{ */
28513 
28514 #define DCDC_REG9_ANA_TRG_SP1_MASK               (0xFFFFFFFFU)
28515 #define DCDC_REG9_ANA_TRG_SP1_SHIFT              (0U)
28516 #define DCDC_REG9_ANA_TRG_SP1(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)
28517 /*! @} */
28518 
28519 /*! @name REG10 - DCDC Register 10 */
28520 /*! @{ */
28521 
28522 #define DCDC_REG10_ANA_TRG_SP2_MASK              (0xFFFFFFFFU)
28523 #define DCDC_REG10_ANA_TRG_SP2_SHIFT             (0U)
28524 #define DCDC_REG10_ANA_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)
28525 /*! @} */
28526 
28527 /*! @name REG11 - DCDC Register 11 */
28528 /*! @{ */
28529 
28530 #define DCDC_REG11_ANA_TRG_SP3_MASK              (0xFFFFFFFFU)
28531 #define DCDC_REG11_ANA_TRG_SP3_SHIFT             (0U)
28532 #define DCDC_REG11_ANA_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)
28533 /*! @} */
28534 
28535 /*! @name REG12 - DCDC Register 12 */
28536 /*! @{ */
28537 
28538 #define DCDC_REG12_DIG_TRG_SP0_MASK              (0xFFFFFFFFU)
28539 #define DCDC_REG12_DIG_TRG_SP0_SHIFT             (0U)
28540 #define DCDC_REG12_DIG_TRG_SP0(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)
28541 /*! @} */
28542 
28543 /*! @name REG13 - DCDC Register 13 */
28544 /*! @{ */
28545 
28546 #define DCDC_REG13_DIG_TRG_SP1_MASK              (0xFFFFFFFFU)
28547 #define DCDC_REG13_DIG_TRG_SP1_SHIFT             (0U)
28548 #define DCDC_REG13_DIG_TRG_SP1(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)
28549 /*! @} */
28550 
28551 /*! @name REG14 - DCDC Register 14 */
28552 /*! @{ */
28553 
28554 #define DCDC_REG14_DIG_TRG_SP2_MASK              (0xFFFFFFFFU)
28555 #define DCDC_REG14_DIG_TRG_SP2_SHIFT             (0U)
28556 #define DCDC_REG14_DIG_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)
28557 /*! @} */
28558 
28559 /*! @name REG15 - DCDC Register 15 */
28560 /*! @{ */
28561 
28562 #define DCDC_REG15_DIG_TRG_SP3_MASK              (0xFFFFFFFFU)
28563 #define DCDC_REG15_DIG_TRG_SP3_SHIFT             (0U)
28564 #define DCDC_REG15_DIG_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)
28565 /*! @} */
28566 
28567 /*! @name REG16 - DCDC Register 16 */
28568 /*! @{ */
28569 
28570 #define DCDC_REG16_ANA_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
28571 #define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT        (0U)
28572 #define DCDC_REG16_ANA_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)
28573 /*! @} */
28574 
28575 /*! @name REG17 - DCDC Register 17 */
28576 /*! @{ */
28577 
28578 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
28579 #define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT        (0U)
28580 #define DCDC_REG17_ANA_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28581 /*! @} */
28582 
28583 /*! @name REG18 - DCDC Register 18 */
28584 /*! @{ */
28585 
28586 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
28587 #define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT        (0U)
28588 #define DCDC_REG18_ANA_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28589 /*! @} */
28590 
28591 /*! @name REG19 - DCDC Register 19 */
28592 /*! @{ */
28593 
28594 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
28595 #define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT        (0U)
28596 #define DCDC_REG19_ANA_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
28597 /*! @} */
28598 
28599 /*! @name REG20 - DCDC Register 20 */
28600 /*! @{ */
28601 
28602 #define DCDC_REG20_DIG_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
28603 #define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT        (0U)
28604 #define DCDC_REG20_DIG_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)
28605 /*! @} */
28606 
28607 /*! @name REG21 - DCDC Register 21 */
28608 /*! @{ */
28609 
28610 #define DCDC_REG21_DIG_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
28611 #define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT        (0U)
28612 #define DCDC_REG21_DIG_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)
28613 /*! @} */
28614 
28615 /*! @name REG22 - DCDC Register 22 */
28616 /*! @{ */
28617 
28618 #define DCDC_REG22_DIG_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
28619 #define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT        (0U)
28620 #define DCDC_REG22_DIG_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)
28621 /*! @} */
28622 
28623 /*! @name REG23 - DCDC Register 23 */
28624 /*! @{ */
28625 
28626 #define DCDC_REG23_DIG_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
28627 #define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT        (0U)
28628 #define DCDC_REG23_DIG_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)
28629 /*! @} */
28630 
28631 /*! @name REG24 - DCDC Register 24 */
28632 /*! @{ */
28633 
28634 #define DCDC_REG24_OK_COUNT_MASK                 (0xFFFFFFFFU)
28635 #define DCDC_REG24_OK_COUNT_SHIFT                (0U)
28636 #define DCDC_REG24_OK_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
28637 /*! @} */
28638 
28639 
28640 /*!
28641  * @}
28642  */ /* end of group DCDC_Register_Masks */
28643 
28644 
28645 /* DCDC - Peripheral instance base addresses */
28646 /** Peripheral DCDC base address */
28647 #define DCDC_BASE                                (0x40CA8000u)
28648 /** Peripheral DCDC base pointer */
28649 #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
28650 /** Array initializer of DCDC peripheral base addresses */
28651 #define DCDC_BASE_ADDRS                          { DCDC_BASE }
28652 /** Array initializer of DCDC peripheral base pointers */
28653 #define DCDC_BASE_PTRS                           { DCDC }
28654 
28655 /*!
28656  * @}
28657  */ /* end of group DCDC_Peripheral_Access_Layer */
28658 
28659 
28660 /* ----------------------------------------------------------------------------
28661    -- DCIC Peripheral Access Layer
28662    ---------------------------------------------------------------------------- */
28663 
28664 /*!
28665  * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer
28666  * @{
28667  */
28668 
28669 /** DCIC - Register Layout Typedef */
28670 typedef struct {
28671   __IO uint32_t DCICC;                             /**< DCIC Control Register, offset: 0x0 */
28672   __IO uint32_t DCICIC;                            /**< DCIC Interrupt Control Register, offset: 0x4 */
28673   __IO uint32_t DCICS;                             /**< DCIC Status Register, offset: 0x8 */
28674        uint8_t RESERVED_0[4];
28675   struct {                                         /* offset: 0x10, array step: 0x10 */
28676     __IO uint32_t DCICRC;                            /**< DCIC ROI Config Register, array offset: 0x10, array step: 0x10 */
28677     __IO uint32_t DCICRS;                            /**< DCIC ROI Size Register, array offset: 0x14, array step: 0x10 */
28678     __IO uint32_t DCICRRS;                           /**< DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10 */
28679     __I  uint32_t DCICRCS;                           /**< DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10 */
28680   } REGION[16];
28681 } DCIC_Type;
28682 
28683 /* ----------------------------------------------------------------------------
28684    -- DCIC Register Masks
28685    ---------------------------------------------------------------------------- */
28686 
28687 /*!
28688  * @addtogroup DCIC_Register_Masks DCIC Register Masks
28689  * @{
28690  */
28691 
28692 /*! @name DCICC - DCIC Control Register */
28693 /*! @{ */
28694 
28695 #define DCIC_DCICC_IC_EN_MASK                    (0x1U)
28696 #define DCIC_DCICC_IC_EN_SHIFT                   (0U)
28697 /*! IC_EN
28698  *  0b0..Disabled
28699  *  0b1..Enabled
28700  */
28701 #define DCIC_DCICC_IC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK)
28702 
28703 #define DCIC_DCICC_DE_POL_MASK                   (0x10U)
28704 #define DCIC_DCICC_DE_POL_SHIFT                  (4U)
28705 /*! DE_POL
28706  *  0b0..Active High.
28707  *  0b1..Active Low.
28708  */
28709 #define DCIC_DCICC_DE_POL(x)                     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK)
28710 
28711 #define DCIC_DCICC_HSYNC_POL_MASK                (0x20U)
28712 #define DCIC_DCICC_HSYNC_POL_SHIFT               (5U)
28713 /*! HSYNC_POL
28714  *  0b0..Active High.
28715  *  0b1..Active Low.
28716  */
28717 #define DCIC_DCICC_HSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK)
28718 
28719 #define DCIC_DCICC_VSYNC_POL_MASK                (0x40U)
28720 #define DCIC_DCICC_VSYNC_POL_SHIFT               (6U)
28721 /*! VSYNC_POL
28722  *  0b0..Active High.
28723  *  0b1..Active Low.
28724  */
28725 #define DCIC_DCICC_VSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK)
28726 
28727 #define DCIC_DCICC_CLK_POL_MASK                  (0x80U)
28728 #define DCIC_DCICC_CLK_POL_SHIFT                 (7U)
28729 /*! CLK_POL
28730  *  0b0..Not inverted (default).
28731  *  0b1..Inverted.
28732  */
28733 #define DCIC_DCICC_CLK_POL(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK)
28734 /*! @} */
28735 
28736 /*! @name DCICIC - DCIC Interrupt Control Register */
28737 /*! @{ */
28738 
28739 #define DCIC_DCICIC_EI_MASK_MASK                 (0x1U)
28740 #define DCIC_DCICIC_EI_MASK_SHIFT                (0U)
28741 /*! EI_MASK
28742  *  0b0..Mask disabled - Interrupt assertion enabled
28743  *  0b1..Mask enabled - Interrupt assertion disabled
28744  */
28745 #define DCIC_DCICIC_EI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK)
28746 
28747 #define DCIC_DCICIC_FI_MASK_MASK                 (0x2U)
28748 #define DCIC_DCICIC_FI_MASK_SHIFT                (1U)
28749 /*! FI_MASK
28750  *  0b0..Mask disabled - Interrupt assertion enabled
28751  *  0b1..Mask enabled - Interrupt assertion disabled
28752  */
28753 #define DCIC_DCICIC_FI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK)
28754 
28755 #define DCIC_DCICIC_FREEZE_MASK_MASK             (0x8U)
28756 #define DCIC_DCICIC_FREEZE_MASK_SHIFT            (3U)
28757 /*! FREEZE_MASK
28758  *  0b0..Masks change allowed
28759  *  0b1..Masks are frozen
28760  */
28761 #define DCIC_DCICIC_FREEZE_MASK(x)               (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK)
28762 
28763 #define DCIC_DCICIC_EXT_SIG_EN_MASK              (0x10000U)
28764 #define DCIC_DCICIC_EXT_SIG_EN_SHIFT             (16U)
28765 /*! EXT_SIG_EN
28766  *  0b0..Disabled
28767  *  0b1..Enabled
28768  */
28769 #define DCIC_DCICIC_EXT_SIG_EN(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK)
28770 /*! @} */
28771 
28772 /*! @name DCICS - DCIC Status Register */
28773 /*! @{ */
28774 
28775 #define DCIC_DCICS_ROI_MATCH_STAT_MASK           (0xFFFFU)
28776 #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT          (0U)
28777 /*! ROI_MATCH_STAT
28778  *  0b0000000000000000..ROI calculated CRC matches expected signature
28779  *  0b0000000000000001..Mismatch at ROI calculated CRC
28780  */
28781 #define DCIC_DCICS_ROI_MATCH_STAT(x)             (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK)
28782 
28783 #define DCIC_DCICS_EI_STAT_MASK                  (0x10000U)
28784 #define DCIC_DCICS_EI_STAT_SHIFT                 (16U)
28785 /*! EI_STAT
28786  *  0b0..No pending Interrupt
28787  *  0b1..Pending Interrupt
28788  */
28789 #define DCIC_DCICS_EI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK)
28790 
28791 #define DCIC_DCICS_FI_STAT_MASK                  (0x20000U)
28792 #define DCIC_DCICS_FI_STAT_SHIFT                 (17U)
28793 /*! FI_STAT
28794  *  0b0..No pending Interrupt
28795  *  0b1..Pending Interrupt
28796  */
28797 #define DCIC_DCICS_FI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK)
28798 /*! @} */
28799 
28800 /*! @name DCICRC - DCIC ROI Config Register */
28801 /*! @{ */
28802 
28803 #define DCIC_DCICRC_START_OFFSET_X_MASK          (0x1FFFU)
28804 #define DCIC_DCICRC_START_OFFSET_X_SHIFT         (0U)
28805 #define DCIC_DCICRC_START_OFFSET_X(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK)
28806 
28807 #define DCIC_DCICRC_START_OFFSET_Y_MASK          (0xFFF0000U)
28808 #define DCIC_DCICRC_START_OFFSET_Y_SHIFT         (16U)
28809 #define DCIC_DCICRC_START_OFFSET_Y(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK)
28810 
28811 #define DCIC_DCICRC_ROI_FREEZE_MASK              (0x40000000U)
28812 #define DCIC_DCICRC_ROI_FREEZE_SHIFT             (30U)
28813 /*! ROI_FREEZE
28814  *  0b0..ROI configuration can be changed
28815  *  0b1..ROI configuration is frozen
28816  */
28817 #define DCIC_DCICRC_ROI_FREEZE(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK)
28818 
28819 #define DCIC_DCICRC_ROI_EN_MASK                  (0x80000000U)
28820 #define DCIC_DCICRC_ROI_EN_SHIFT                 (31U)
28821 /*! ROI_EN
28822  *  0b0..Disabled
28823  *  0b1..Enabled
28824  */
28825 #define DCIC_DCICRC_ROI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK)
28826 /*! @} */
28827 
28828 /* The count of DCIC_DCICRC */
28829 #define DCIC_DCICRC_COUNT                        (16U)
28830 
28831 /*! @name DCICRS - DCIC ROI Size Register */
28832 /*! @{ */
28833 
28834 #define DCIC_DCICRS_END_OFFSET_X_MASK            (0x1FFFU)
28835 #define DCIC_DCICRS_END_OFFSET_X_SHIFT           (0U)
28836 #define DCIC_DCICRS_END_OFFSET_X(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK)
28837 
28838 #define DCIC_DCICRS_END_OFFSET_Y_MASK            (0xFFF0000U)
28839 #define DCIC_DCICRS_END_OFFSET_Y_SHIFT           (16U)
28840 #define DCIC_DCICRS_END_OFFSET_Y(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK)
28841 /*! @} */
28842 
28843 /* The count of DCIC_DCICRS */
28844 #define DCIC_DCICRS_COUNT                        (16U)
28845 
28846 /*! @name DCICRRS - DCIC ROI Reference Signature Register */
28847 /*! @{ */
28848 
28849 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK    (0xFFFFFFFFU)
28850 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT   (0U)
28851 #define DCIC_DCICRRS_REFERENCE_SIGNATURE(x)      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
28852 /*! @} */
28853 
28854 /* The count of DCIC_DCICRRS */
28855 #define DCIC_DCICRRS_COUNT                       (16U)
28856 
28857 /*! @name DCICRCS - DCIC ROI Calculated Signature Register */
28858 /*! @{ */
28859 
28860 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK   (0xFFFFFFFFU)
28861 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT  (0U)
28862 #define DCIC_DCICRCS_CALCULATED_SIGNATURE(x)     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
28863 /*! @} */
28864 
28865 /* The count of DCIC_DCICRCS */
28866 #define DCIC_DCICRCS_COUNT                       (16U)
28867 
28868 
28869 /*!
28870  * @}
28871  */ /* end of group DCIC_Register_Masks */
28872 
28873 
28874 /* DCIC - Peripheral instance base addresses */
28875 /** Peripheral DCIC1 base address */
28876 #define DCIC1_BASE                               (0x40819000u)
28877 /** Peripheral DCIC1 base pointer */
28878 #define DCIC1                                    ((DCIC_Type *)DCIC1_BASE)
28879 /** Peripheral DCIC2 base address */
28880 #define DCIC2_BASE                               (0x4081A000u)
28881 /** Peripheral DCIC2 base pointer */
28882 #define DCIC2                                    ((DCIC_Type *)DCIC2_BASE)
28883 /** Array initializer of DCIC peripheral base addresses */
28884 #define DCIC_BASE_ADDRS                          { 0u, DCIC1_BASE, DCIC2_BASE }
28885 /** Array initializer of DCIC peripheral base pointers */
28886 #define DCIC_BASE_PTRS                           { (DCIC_Type *)0u, DCIC1, DCIC2 }
28887 
28888 /*!
28889  * @}
28890  */ /* end of group DCIC_Peripheral_Access_Layer */
28891 
28892 
28893 /* ----------------------------------------------------------------------------
28894    -- DMA Peripheral Access Layer
28895    ---------------------------------------------------------------------------- */
28896 
28897 /*!
28898  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
28899  * @{
28900  */
28901 
28902 /** DMA - Register Layout Typedef */
28903 typedef struct {
28904   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
28905   __I  uint32_t ES;                                /**< Error Status, offset: 0x4 */
28906        uint8_t RESERVED_0[4];
28907   __IO uint32_t ERQ;                               /**< Enable Request, offset: 0xC */
28908        uint8_t RESERVED_1[4];
28909   __IO uint32_t EEI;                               /**< Enable Error Interrupt, offset: 0x14 */
28910   __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt, offset: 0x18 */
28911   __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt, offset: 0x19 */
28912   __O  uint8_t CERQ;                               /**< Clear Enable Request, offset: 0x1A */
28913   __O  uint8_t SERQ;                               /**< Set Enable Request, offset: 0x1B */
28914   __O  uint8_t CDNE;                               /**< Clear DONE Status Bit, offset: 0x1C */
28915   __O  uint8_t SSRT;                               /**< Set START Bit, offset: 0x1D */
28916   __O  uint8_t CERR;                               /**< Clear Error, offset: 0x1E */
28917   __O  uint8_t CINT;                               /**< Clear Interrupt Request, offset: 0x1F */
28918        uint8_t RESERVED_2[4];
28919   __IO uint32_t INT;                               /**< Interrupt Request, offset: 0x24 */
28920        uint8_t RESERVED_3[4];
28921   __IO uint32_t ERR;                               /**< Error, offset: 0x2C */
28922        uint8_t RESERVED_4[4];
28923   __I  uint32_t HRS;                               /**< Hardware Request Status, offset: 0x34 */
28924        uint8_t RESERVED_5[12];
28925   __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop, offset: 0x44 */
28926        uint8_t RESERVED_6[184];
28927   __IO uint8_t DCHPRI3;                            /**< Channel Priority, offset: 0x100 */
28928   __IO uint8_t DCHPRI2;                            /**< Channel Priority, offset: 0x101 */
28929   __IO uint8_t DCHPRI1;                            /**< Channel Priority, offset: 0x102 */
28930   __IO uint8_t DCHPRI0;                            /**< Channel Priority, offset: 0x103 */
28931   __IO uint8_t DCHPRI7;                            /**< Channel Priority, offset: 0x104 */
28932   __IO uint8_t DCHPRI6;                            /**< Channel Priority, offset: 0x105 */
28933   __IO uint8_t DCHPRI5;                            /**< Channel Priority, offset: 0x106 */
28934   __IO uint8_t DCHPRI4;                            /**< Channel Priority, offset: 0x107 */
28935   __IO uint8_t DCHPRI11;                           /**< Channel Priority, offset: 0x108 */
28936   __IO uint8_t DCHPRI10;                           /**< Channel Priority, offset: 0x109 */
28937   __IO uint8_t DCHPRI9;                            /**< Channel Priority, offset: 0x10A */
28938   __IO uint8_t DCHPRI8;                            /**< Channel Priority, offset: 0x10B */
28939   __IO uint8_t DCHPRI15;                           /**< Channel Priority, offset: 0x10C */
28940   __IO uint8_t DCHPRI14;                           /**< Channel Priority, offset: 0x10D */
28941   __IO uint8_t DCHPRI13;                           /**< Channel Priority, offset: 0x10E */
28942   __IO uint8_t DCHPRI12;                           /**< Channel Priority, offset: 0x10F */
28943   __IO uint8_t DCHPRI19;                           /**< Channel Priority, offset: 0x110 */
28944   __IO uint8_t DCHPRI18;                           /**< Channel Priority, offset: 0x111 */
28945   __IO uint8_t DCHPRI17;                           /**< Channel Priority, offset: 0x112 */
28946   __IO uint8_t DCHPRI16;                           /**< Channel Priority, offset: 0x113 */
28947   __IO uint8_t DCHPRI23;                           /**< Channel Priority, offset: 0x114 */
28948   __IO uint8_t DCHPRI22;                           /**< Channel Priority, offset: 0x115 */
28949   __IO uint8_t DCHPRI21;                           /**< Channel Priority, offset: 0x116 */
28950   __IO uint8_t DCHPRI20;                           /**< Channel Priority, offset: 0x117 */
28951   __IO uint8_t DCHPRI27;                           /**< Channel Priority, offset: 0x118 */
28952   __IO uint8_t DCHPRI26;                           /**< Channel Priority, offset: 0x119 */
28953   __IO uint8_t DCHPRI25;                           /**< Channel Priority, offset: 0x11A */
28954   __IO uint8_t DCHPRI24;                           /**< Channel Priority, offset: 0x11B */
28955   __IO uint8_t DCHPRI31;                           /**< Channel Priority, offset: 0x11C */
28956   __IO uint8_t DCHPRI30;                           /**< Channel Priority, offset: 0x11D */
28957   __IO uint8_t DCHPRI29;                           /**< Channel Priority, offset: 0x11E */
28958   __IO uint8_t DCHPRI28;                           /**< Channel Priority, offset: 0x11F */
28959        uint8_t RESERVED_7[3808];
28960   struct {                                         /* offset: 0x1000, array step: 0x20 */
28961     __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
28962     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
28963     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
28964     union {                                          /* offset: 0x1008, array step: 0x20 */
28965       __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
28966       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
28967       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
28968     };
28969     __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
28970     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
28971     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
28972     union {                                          /* offset: 0x1016, array step: 0x20 */
28973       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
28974       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
28975     };
28976     __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
28977     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
28978     union {                                          /* offset: 0x101E, array step: 0x20 */
28979       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
28980       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
28981     };
28982   } TCD[32];
28983 } DMA_Type;
28984 
28985 /* ----------------------------------------------------------------------------
28986    -- DMA Register Masks
28987    ---------------------------------------------------------------------------- */
28988 
28989 /*!
28990  * @addtogroup DMA_Register_Masks DMA Register Masks
28991  * @{
28992  */
28993 
28994 /*! @name CR - Control */
28995 /*! @{ */
28996 
28997 #define DMA_CR_EDBG_MASK                         (0x2U)
28998 #define DMA_CR_EDBG_SHIFT                        (1U)
28999 /*! EDBG - Enable Debug
29000  *  0b0..When the chip is in Debug mode, the eDMA continues to operate.
29001  *  0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.
29002  */
29003 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
29004 
29005 #define DMA_CR_ERCA_MASK                         (0x4U)
29006 #define DMA_CR_ERCA_SHIFT                        (2U)
29007 /*! ERCA - Enable Round Robin Channel Arbitration
29008  *  0b0..Fixed priority arbitration within each group
29009  *  0b1..Round robin arbitration within each group
29010  */
29011 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
29012 
29013 #define DMA_CR_ERGA_MASK                         (0x8U)
29014 #define DMA_CR_ERGA_SHIFT                        (3U)
29015 /*! ERGA - Enable Round Robin Group Arbitration
29016  *  0b0..Fixed priority arbitration
29017  *  0b1..Round robin arbitration
29018  */
29019 #define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
29020 
29021 #define DMA_CR_HOE_MASK                          (0x10U)
29022 #define DMA_CR_HOE_SHIFT                         (4U)
29023 /*! HOE - Halt On Error
29024  *  0b0..Normal operation
29025  *  0b1..Error causes HALT field to be automatically set to 1
29026  */
29027 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
29028 
29029 #define DMA_CR_HALT_MASK                         (0x20U)
29030 #define DMA_CR_HALT_SHIFT                        (5U)
29031 /*! HALT - Halt eDMA Operations
29032  *  0b0..Normal operation
29033  *  0b1..eDMA operations halted
29034  */
29035 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
29036 
29037 #define DMA_CR_CLM_MASK                          (0x40U)
29038 #define DMA_CR_CLM_SHIFT                         (6U)
29039 /*! CLM - Continuous Link Mode
29040  *  0b0..Continuous link mode is off
29041  *  0b1..Continuous link mode is on
29042  */
29043 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
29044 
29045 #define DMA_CR_EMLM_MASK                         (0x80U)
29046 #define DMA_CR_EMLM_SHIFT                        (7U)
29047 /*! EMLM - Enable Minor Loop Mapping
29048  *  0b0..Disabled
29049  *  0b1..Enabled
29050  */
29051 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
29052 
29053 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
29054 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
29055 /*! GRP0PRI - Channel Group 0 Priority
29056  */
29057 #define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
29058 
29059 #define DMA_CR_GRP1PRI_MASK                      (0x400U)
29060 #define DMA_CR_GRP1PRI_SHIFT                     (10U)
29061 /*! GRP1PRI - Channel Group 1 Priority
29062  */
29063 #define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
29064 
29065 #define DMA_CR_ECX_MASK                          (0x10000U)
29066 #define DMA_CR_ECX_SHIFT                         (16U)
29067 /*! ECX - Error Cancel Transfer
29068  *  0b0..Normal operation
29069  *  0b1..Cancel the remaining data transfer
29070  */
29071 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
29072 
29073 #define DMA_CR_CX_MASK                           (0x20000U)
29074 #define DMA_CR_CX_SHIFT                          (17U)
29075 /*! CX - Cancel Transfer
29076  *  0b0..Normal operation
29077  *  0b1..Cancel the remaining data transfer
29078  */
29079 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
29080 
29081 #define DMA_CR_VERSION_MASK                      (0x7F000000U)
29082 #define DMA_CR_VERSION_SHIFT                     (24U)
29083 /*! VERSION - eDMA version number
29084  */
29085 #define DMA_CR_VERSION(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
29086 
29087 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
29088 #define DMA_CR_ACTIVE_SHIFT                      (31U)
29089 /*! ACTIVE - eDMA Active Status
29090  *  0b0..eDMA is idle
29091  *  0b1..eDMA is executing a channel
29092  */
29093 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
29094 /*! @} */
29095 
29096 /*! @name ES - Error Status */
29097 /*! @{ */
29098 
29099 #define DMA_ES_DBE_MASK                          (0x1U)
29100 #define DMA_ES_DBE_SHIFT                         (0U)
29101 /*! DBE - Destination Bus Error
29102  *  0b0..No destination bus error.
29103  *  0b1..The most-recently recorded error was a bus error on a destination write.
29104  */
29105 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
29106 
29107 #define DMA_ES_SBE_MASK                          (0x2U)
29108 #define DMA_ES_SBE_SHIFT                         (1U)
29109 /*! SBE - Source Bus Error
29110  *  0b0..No source bus error.
29111  *  0b1..The most-recently recorded error was a bus error on a source read.
29112  */
29113 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
29114 
29115 #define DMA_ES_SGE_MASK                          (0x4U)
29116 #define DMA_ES_SGE_SHIFT                         (2U)
29117 /*! SGE - Scatter/Gather Configuration Error
29118  *  0b0..No scatter/gather configuration error.
29119  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
29120  */
29121 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
29122 
29123 #define DMA_ES_NCE_MASK                          (0x8U)
29124 #define DMA_ES_NCE_SHIFT                         (3U)
29125 /*! NCE - NBYTES/CITER Configuration Error
29126  *  0b0..No NBYTES/CITER configuration error.
29127  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
29128  *       fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or
29129  *       TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
29130  */
29131 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
29132 
29133 #define DMA_ES_DOE_MASK                          (0x10U)
29134 #define DMA_ES_DOE_SHIFT                         (4U)
29135 /*! DOE - Destination Offset Error
29136  *  0b0..No destination offset configuration error.
29137  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
29138  */
29139 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
29140 
29141 #define DMA_ES_DAE_MASK                          (0x20U)
29142 #define DMA_ES_DAE_SHIFT                         (5U)
29143 /*! DAE - Destination Address Error
29144  *  0b0..No destination address configuration error.
29145  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
29146  *       is inconsistent with TCDn_ATTR[DSIZE].
29147  */
29148 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
29149 
29150 #define DMA_ES_SOE_MASK                          (0x40U)
29151 #define DMA_ES_SOE_SHIFT                         (6U)
29152 /*! SOE - Source Offset Error
29153  *  0b0..No source offset configuration error.
29154  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
29155  */
29156 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
29157 
29158 #define DMA_ES_SAE_MASK                          (0x80U)
29159 #define DMA_ES_SAE_SHIFT                         (7U)
29160 /*! SAE - Source Address Error
29161  *  0b0..No source address configuration error.
29162  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
29163  *       is inconsistent with TCDn_ATTR[SSIZE].
29164  */
29165 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
29166 
29167 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
29168 #define DMA_ES_ERRCHN_SHIFT                      (8U)
29169 /*! ERRCHN - Error Channel Number or Canceled Channel Number
29170  */
29171 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
29172 
29173 #define DMA_ES_CPE_MASK                          (0x4000U)
29174 #define DMA_ES_CPE_SHIFT                         (14U)
29175 /*! CPE - Channel Priority Error
29176  *  0b0..No channel priority error.
29177  *  0b1..The most-recently recorded error was a configuration error in the channel priorities within a group.
29178  *       Channel priorities within a group are not unique.
29179  */
29180 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
29181 
29182 #define DMA_ES_GPE_MASK                          (0x8000U)
29183 #define DMA_ES_GPE_SHIFT                         (15U)
29184 /*! GPE - Group Priority Error
29185  *  0b0..No group priority error.
29186  *  0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.
29187  */
29188 #define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
29189 
29190 #define DMA_ES_ECX_MASK                          (0x10000U)
29191 #define DMA_ES_ECX_SHIFT                         (16U)
29192 /*! ECX - Transfer Canceled
29193  *  0b0..No canceled transfers
29194  *  0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
29195  */
29196 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
29197 
29198 #define DMA_ES_VLD_MASK                          (0x80000000U)
29199 #define DMA_ES_VLD_SHIFT                         (31U)
29200 /*! VLD - Logical OR of all ERR status fields
29201  *  0b0..No ERR fields are 1
29202  *  0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
29203  */
29204 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
29205 /*! @} */
29206 
29207 /*! @name ERQ - Enable Request */
29208 /*! @{ */
29209 
29210 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
29211 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
29212 /*! ERQ0 - Enable DMA Request 0
29213  *  0b0..The DMA request signal for channel 0 is disabled
29214  *  0b1..The DMA request signal for channel 0 is enabled
29215  */
29216 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
29217 
29218 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
29219 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
29220 /*! ERQ1 - Enable DMA Request 1
29221  *  0b0..The DMA request signal for channel 1 is disabled
29222  *  0b1..The DMA request signal for channel 1 is enabled
29223  */
29224 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
29225 
29226 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
29227 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
29228 /*! ERQ2 - Enable DMA Request 2
29229  *  0b0..The DMA request signal for channel 2 is disabled
29230  *  0b1..The DMA request signal for channel 2 is enabled
29231  */
29232 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
29233 
29234 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
29235 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
29236 /*! ERQ3 - Enable DMA Request 3
29237  *  0b0..The DMA request signal for channel 3 is disabled
29238  *  0b1..The DMA request signal for channel 3 is enabled
29239  */
29240 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
29241 
29242 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
29243 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
29244 /*! ERQ4 - Enable DMA Request 4
29245  *  0b0..The DMA request signal for channel 4 is disabled
29246  *  0b1..The DMA request signal for channel 4 is enabled
29247  */
29248 #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
29249 
29250 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
29251 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
29252 /*! ERQ5 - Enable DMA Request 5
29253  *  0b0..The DMA request signal for channel 5 is disabled
29254  *  0b1..The DMA request signal for channel 5 is enabled
29255  */
29256 #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
29257 
29258 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
29259 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
29260 /*! ERQ6 - Enable DMA Request 6
29261  *  0b0..The DMA request signal for channel 6 is disabled
29262  *  0b1..The DMA request signal for channel 6 is enabled
29263  */
29264 #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
29265 
29266 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
29267 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
29268 /*! ERQ7 - Enable DMA Request 7
29269  *  0b0..The DMA request signal for channel 7 is disabled
29270  *  0b1..The DMA request signal for channel 7 is enabled
29271  */
29272 #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
29273 
29274 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
29275 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
29276 /*! ERQ8 - Enable DMA Request 8
29277  *  0b0..The DMA request signal for channel 8 is disabled
29278  *  0b1..The DMA request signal for channel 8 is enabled
29279  */
29280 #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
29281 
29282 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
29283 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
29284 /*! ERQ9 - Enable DMA Request 9
29285  *  0b0..The DMA request signal for channel 9 is disabled
29286  *  0b1..The DMA request signal for channel 9 is enabled
29287  */
29288 #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
29289 
29290 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
29291 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
29292 /*! ERQ10 - Enable DMA Request 10
29293  *  0b0..The DMA request signal for channel 10 is disabled
29294  *  0b1..The DMA request signal for channel 10 is enabled
29295  */
29296 #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
29297 
29298 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
29299 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
29300 /*! ERQ11 - Enable DMA Request 11
29301  *  0b0..The DMA request signal for channel 11 is disabled
29302  *  0b1..The DMA request signal for channel 11 is enabled
29303  */
29304 #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
29305 
29306 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
29307 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
29308 /*! ERQ12 - Enable DMA Request 12
29309  *  0b0..The DMA request signal for channel 12 is disabled
29310  *  0b1..The DMA request signal for channel 12 is enabled
29311  */
29312 #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
29313 
29314 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
29315 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
29316 /*! ERQ13 - Enable DMA Request 13
29317  *  0b0..The DMA request signal for channel 13 is disabled
29318  *  0b1..The DMA request signal for channel 13 is enabled
29319  */
29320 #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
29321 
29322 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
29323 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
29324 /*! ERQ14 - Enable DMA Request 14
29325  *  0b0..The DMA request signal for channel 14 is disabled
29326  *  0b1..The DMA request signal for channel 14 is enabled
29327  */
29328 #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
29329 
29330 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
29331 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
29332 /*! ERQ15 - Enable DMA Request 15
29333  *  0b0..The DMA request signal for channel 15 is disabled
29334  *  0b1..The DMA request signal for channel 15 is enabled
29335  */
29336 #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
29337 
29338 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
29339 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
29340 /*! ERQ16 - Enable DMA Request 16
29341  *  0b0..The DMA request signal for channel 16 is disabled
29342  *  0b1..The DMA request signal for channel 16 is enabled
29343  */
29344 #define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
29345 
29346 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
29347 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
29348 /*! ERQ17 - Enable DMA Request 17
29349  *  0b0..The DMA request signal for channel 17 is disabled
29350  *  0b1..The DMA request signal for channel 17 is enabled
29351  */
29352 #define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
29353 
29354 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
29355 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
29356 /*! ERQ18 - Enable DMA Request 18
29357  *  0b0..The DMA request signal for channel 18 is disabled
29358  *  0b1..The DMA request signal for channel 18 is enabled
29359  */
29360 #define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
29361 
29362 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
29363 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
29364 /*! ERQ19 - Enable DMA Request 19
29365  *  0b0..The DMA request signal for channel 19 is disabled
29366  *  0b1..The DMA request signal for channel 19 is enabled
29367  */
29368 #define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
29369 
29370 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
29371 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
29372 /*! ERQ20 - Enable DMA Request 20
29373  *  0b0..The DMA request signal for channel 20 is disabled
29374  *  0b1..The DMA request signal for channel 20 is enabled
29375  */
29376 #define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
29377 
29378 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
29379 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
29380 /*! ERQ21 - Enable DMA Request 21
29381  *  0b0..The DMA request signal for channel 21 is disabled
29382  *  0b1..The DMA request signal for channel 21 is enabled
29383  */
29384 #define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
29385 
29386 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
29387 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
29388 /*! ERQ22 - Enable DMA Request 22
29389  *  0b0..The DMA request signal for channel 22 is disabled
29390  *  0b1..The DMA request signal for channel 22 is enabled
29391  */
29392 #define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
29393 
29394 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
29395 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
29396 /*! ERQ23 - Enable DMA Request 23
29397  *  0b0..The DMA request signal for channel 23 is disabled
29398  *  0b1..The DMA request signal for channel 23 is enabled
29399  */
29400 #define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
29401 
29402 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
29403 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
29404 /*! ERQ24 - Enable DMA Request 24
29405  *  0b0..The DMA request signal for channel 24 is disabled
29406  *  0b1..The DMA request signal for channel 24 is enabled
29407  */
29408 #define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
29409 
29410 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
29411 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
29412 /*! ERQ25 - Enable DMA Request 25
29413  *  0b0..The DMA request signal for channel 25 is disabled
29414  *  0b1..The DMA request signal for channel 25 is enabled
29415  */
29416 #define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
29417 
29418 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
29419 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
29420 /*! ERQ26 - Enable DMA Request 26
29421  *  0b0..The DMA request signal for channel 26 is disabled
29422  *  0b1..The DMA request signal for channel 26 is enabled
29423  */
29424 #define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
29425 
29426 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
29427 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
29428 /*! ERQ27 - Enable DMA Request 27
29429  *  0b0..The DMA request signal for channel 27 is disabled
29430  *  0b1..The DMA request signal for channel 27 is enabled
29431  */
29432 #define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
29433 
29434 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
29435 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
29436 /*! ERQ28 - Enable DMA Request 28
29437  *  0b0..The DMA request signal for channel 28 is disabled
29438  *  0b1..The DMA request signal for channel 28 is enabled
29439  */
29440 #define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
29441 
29442 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
29443 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
29444 /*! ERQ29 - Enable DMA Request 29
29445  *  0b0..The DMA request signal for channel 29 is disabled
29446  *  0b1..The DMA request signal for channel 29 is enabled
29447  */
29448 #define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
29449 
29450 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
29451 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
29452 /*! ERQ30 - Enable DMA Request 30
29453  *  0b0..The DMA request signal for channel 30 is disabled
29454  *  0b1..The DMA request signal for channel 30 is enabled
29455  */
29456 #define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
29457 
29458 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
29459 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
29460 /*! ERQ31 - Enable DMA Request 31
29461  *  0b0..The DMA request signal for channel 31 is disabled
29462  *  0b1..The DMA request signal for channel 31 is enabled
29463  */
29464 #define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
29465 /*! @} */
29466 
29467 /*! @name EEI - Enable Error Interrupt */
29468 /*! @{ */
29469 
29470 #define DMA_EEI_EEI0_MASK                        (0x1U)
29471 #define DMA_EEI_EEI0_SHIFT                       (0U)
29472 /*! EEI0 - Enable Error Interrupt 0
29473  *  0b0..An error on channel 0 does not generate an error interrupt
29474  *  0b1..An error on channel 0 generates an error interrupt request
29475  */
29476 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
29477 
29478 #define DMA_EEI_EEI1_MASK                        (0x2U)
29479 #define DMA_EEI_EEI1_SHIFT                       (1U)
29480 /*! EEI1 - Enable Error Interrupt 1
29481  *  0b0..An error on channel 1 does not generate an error interrupt
29482  *  0b1..An error on channel 1 generates an error interrupt request
29483  */
29484 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
29485 
29486 #define DMA_EEI_EEI2_MASK                        (0x4U)
29487 #define DMA_EEI_EEI2_SHIFT                       (2U)
29488 /*! EEI2 - Enable Error Interrupt 2
29489  *  0b0..An error on channel 2 does not generate an error interrupt
29490  *  0b1..An error on channel 2 generates an error interrupt request
29491  */
29492 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
29493 
29494 #define DMA_EEI_EEI3_MASK                        (0x8U)
29495 #define DMA_EEI_EEI3_SHIFT                       (3U)
29496 /*! EEI3 - Enable Error Interrupt 3
29497  *  0b0..An error on channel 3 does not generate an error interrupt
29498  *  0b1..An error on channel 3 generates an error interrupt request
29499  */
29500 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
29501 
29502 #define DMA_EEI_EEI4_MASK                        (0x10U)
29503 #define DMA_EEI_EEI4_SHIFT                       (4U)
29504 /*! EEI4 - Enable Error Interrupt 4
29505  *  0b0..An error on channel 4 does not generate an error interrupt
29506  *  0b1..An error on channel 4 generates an error interrupt request
29507  */
29508 #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
29509 
29510 #define DMA_EEI_EEI5_MASK                        (0x20U)
29511 #define DMA_EEI_EEI5_SHIFT                       (5U)
29512 /*! EEI5 - Enable Error Interrupt 5
29513  *  0b0..An error on channel 5 does not generate an error interrupt
29514  *  0b1..An error on channel 5 generates an error interrupt request
29515  */
29516 #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
29517 
29518 #define DMA_EEI_EEI6_MASK                        (0x40U)
29519 #define DMA_EEI_EEI6_SHIFT                       (6U)
29520 /*! EEI6 - Enable Error Interrupt 6
29521  *  0b0..An error on channel 6 does not generate an error interrupt
29522  *  0b1..An error on channel 6 generates an error interrupt request
29523  */
29524 #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
29525 
29526 #define DMA_EEI_EEI7_MASK                        (0x80U)
29527 #define DMA_EEI_EEI7_SHIFT                       (7U)
29528 /*! EEI7 - Enable Error Interrupt 7
29529  *  0b0..An error on channel 7 does not generate an error interrupt
29530  *  0b1..An error on channel 7 generates an error interrupt request
29531  */
29532 #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
29533 
29534 #define DMA_EEI_EEI8_MASK                        (0x100U)
29535 #define DMA_EEI_EEI8_SHIFT                       (8U)
29536 /*! EEI8 - Enable Error Interrupt 8
29537  *  0b0..An error on channel 8 does not generate an error interrupt
29538  *  0b1..An error on channel 8 generates an error interrupt request
29539  */
29540 #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
29541 
29542 #define DMA_EEI_EEI9_MASK                        (0x200U)
29543 #define DMA_EEI_EEI9_SHIFT                       (9U)
29544 /*! EEI9 - Enable Error Interrupt 9
29545  *  0b0..An error on channel 9 does not generate an error interrupt
29546  *  0b1..An error on channel 9 generates an error interrupt request
29547  */
29548 #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
29549 
29550 #define DMA_EEI_EEI10_MASK                       (0x400U)
29551 #define DMA_EEI_EEI10_SHIFT                      (10U)
29552 /*! EEI10 - Enable Error Interrupt 10
29553  *  0b0..An error on channel 10 does not generate an error interrupt
29554  *  0b1..An error on channel 10 generates an error interrupt request
29555  */
29556 #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
29557 
29558 #define DMA_EEI_EEI11_MASK                       (0x800U)
29559 #define DMA_EEI_EEI11_SHIFT                      (11U)
29560 /*! EEI11 - Enable Error Interrupt 11
29561  *  0b0..An error on channel 11 does not generate an error interrupt
29562  *  0b1..An error on channel 11 generates an error interrupt request
29563  */
29564 #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
29565 
29566 #define DMA_EEI_EEI12_MASK                       (0x1000U)
29567 #define DMA_EEI_EEI12_SHIFT                      (12U)
29568 /*! EEI12 - Enable Error Interrupt 12
29569  *  0b0..An error on channel 12 does not generate an error interrupt
29570  *  0b1..An error on channel 12 generates an error interrupt request
29571  */
29572 #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
29573 
29574 #define DMA_EEI_EEI13_MASK                       (0x2000U)
29575 #define DMA_EEI_EEI13_SHIFT                      (13U)
29576 /*! EEI13 - Enable Error Interrupt 13
29577  *  0b0..An error on channel 13 does not generate an error interrupt
29578  *  0b1..An error on channel 13 generates an error interrupt request
29579  */
29580 #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
29581 
29582 #define DMA_EEI_EEI14_MASK                       (0x4000U)
29583 #define DMA_EEI_EEI14_SHIFT                      (14U)
29584 /*! EEI14 - Enable Error Interrupt 14
29585  *  0b0..An error on channel 14 does not generate an error interrupt
29586  *  0b1..An error on channel 14 generates an error interrupt request
29587  */
29588 #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
29589 
29590 #define DMA_EEI_EEI15_MASK                       (0x8000U)
29591 #define DMA_EEI_EEI15_SHIFT                      (15U)
29592 /*! EEI15 - Enable Error Interrupt 15
29593  *  0b0..An error on channel 15 does not generate an error interrupt
29594  *  0b1..An error on channel 15 generates an error interrupt request
29595  */
29596 #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
29597 
29598 #define DMA_EEI_EEI16_MASK                       (0x10000U)
29599 #define DMA_EEI_EEI16_SHIFT                      (16U)
29600 /*! EEI16 - Enable Error Interrupt 16
29601  *  0b0..An error on channel 16 does not generate an error interrupt
29602  *  0b1..An error on channel 16 generates an error interrupt request
29603  */
29604 #define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
29605 
29606 #define DMA_EEI_EEI17_MASK                       (0x20000U)
29607 #define DMA_EEI_EEI17_SHIFT                      (17U)
29608 /*! EEI17 - Enable Error Interrupt 17
29609  *  0b0..An error on channel 17 does not generate an error interrupt
29610  *  0b1..An error on channel 17 generates an error interrupt request
29611  */
29612 #define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
29613 
29614 #define DMA_EEI_EEI18_MASK                       (0x40000U)
29615 #define DMA_EEI_EEI18_SHIFT                      (18U)
29616 /*! EEI18 - Enable Error Interrupt 18
29617  *  0b0..An error on channel 18 does not generate an error interrupt
29618  *  0b1..An error on channel 18 generates an error interrupt request
29619  */
29620 #define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
29621 
29622 #define DMA_EEI_EEI19_MASK                       (0x80000U)
29623 #define DMA_EEI_EEI19_SHIFT                      (19U)
29624 /*! EEI19 - Enable Error Interrupt 19
29625  *  0b0..An error on channel 19 does not generate an error interrupt
29626  *  0b1..An error on channel 19 generates an error interrupt request
29627  */
29628 #define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
29629 
29630 #define DMA_EEI_EEI20_MASK                       (0x100000U)
29631 #define DMA_EEI_EEI20_SHIFT                      (20U)
29632 /*! EEI20 - Enable Error Interrupt 20
29633  *  0b0..An error on channel 20 does not generate an error interrupt
29634  *  0b1..An error on channel 20 generates an error interrupt request
29635  */
29636 #define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
29637 
29638 #define DMA_EEI_EEI21_MASK                       (0x200000U)
29639 #define DMA_EEI_EEI21_SHIFT                      (21U)
29640 /*! EEI21 - Enable Error Interrupt 21
29641  *  0b0..An error on channel 21 does not generate an error interrupt
29642  *  0b1..An error on channel 21 generates an error interrupt request
29643  */
29644 #define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
29645 
29646 #define DMA_EEI_EEI22_MASK                       (0x400000U)
29647 #define DMA_EEI_EEI22_SHIFT                      (22U)
29648 /*! EEI22 - Enable Error Interrupt 22
29649  *  0b0..An error on channel 22 does not generate an error interrupt
29650  *  0b1..An error on channel 22 generates an error interrupt request
29651  */
29652 #define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
29653 
29654 #define DMA_EEI_EEI23_MASK                       (0x800000U)
29655 #define DMA_EEI_EEI23_SHIFT                      (23U)
29656 /*! EEI23 - Enable Error Interrupt 23
29657  *  0b0..An error on channel 23 does not generate an error interrupt
29658  *  0b1..An error on channel 23 generates an error interrupt request
29659  */
29660 #define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
29661 
29662 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
29663 #define DMA_EEI_EEI24_SHIFT                      (24U)
29664 /*! EEI24 - Enable Error Interrupt 24
29665  *  0b0..An error on channel 24 does not generate an error interrupt
29666  *  0b1..An error on channel 24 generates an error interrupt request
29667  */
29668 #define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
29669 
29670 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
29671 #define DMA_EEI_EEI25_SHIFT                      (25U)
29672 /*! EEI25 - Enable Error Interrupt 25
29673  *  0b0..An error on channel 25 does not generate an error interrupt
29674  *  0b1..An error on channel 25 generates an error interrupt request
29675  */
29676 #define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
29677 
29678 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
29679 #define DMA_EEI_EEI26_SHIFT                      (26U)
29680 /*! EEI26 - Enable Error Interrupt 26
29681  *  0b0..An error on channel 26 does not generate an error interrupt
29682  *  0b1..An error on channel 26 generates an error interrupt request
29683  */
29684 #define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
29685 
29686 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
29687 #define DMA_EEI_EEI27_SHIFT                      (27U)
29688 /*! EEI27 - Enable Error Interrupt 27
29689  *  0b0..An error on channel 27 does not generate an error interrupt
29690  *  0b1..An error on channel 27 generates an error interrupt request
29691  */
29692 #define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
29693 
29694 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
29695 #define DMA_EEI_EEI28_SHIFT                      (28U)
29696 /*! EEI28 - Enable Error Interrupt 28
29697  *  0b0..An error on channel 28 does not generate an error interrupt
29698  *  0b1..An error on channel 28 generates an error interrupt request
29699  */
29700 #define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
29701 
29702 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
29703 #define DMA_EEI_EEI29_SHIFT                      (29U)
29704 /*! EEI29 - Enable Error Interrupt 29
29705  *  0b0..An error on channel 29 does not generate an error interrupt
29706  *  0b1..An error on channel 29 generates an error interrupt request
29707  */
29708 #define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
29709 
29710 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
29711 #define DMA_EEI_EEI30_SHIFT                      (30U)
29712 /*! EEI30 - Enable Error Interrupt 30
29713  *  0b0..An error on channel 30 does not generate an error interrupt
29714  *  0b1..An error on channel 30 generates an error interrupt request
29715  */
29716 #define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
29717 
29718 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
29719 #define DMA_EEI_EEI31_SHIFT                      (31U)
29720 /*! EEI31 - Enable Error Interrupt 31
29721  *  0b0..An error on channel 31 does not generate an error interrupt
29722  *  0b1..An error on channel 31 generates an error interrupt request
29723  */
29724 #define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
29725 /*! @} */
29726 
29727 /*! @name CEEI - Clear Enable Error Interrupt */
29728 /*! @{ */
29729 
29730 #define DMA_CEEI_CEEI_MASK                       (0x1FU)
29731 #define DMA_CEEI_CEEI_SHIFT                      (0U)
29732 /*! CEEI - Clear Enable Error Interrupt
29733  */
29734 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
29735 
29736 #define DMA_CEEI_CAEE_MASK                       (0x40U)
29737 #define DMA_CEEI_CAEE_SHIFT                      (6U)
29738 /*! CAEE - Clear All Enable Error Interrupts
29739  *  0b0..Write 0 only to the EEI field specified in the CEEI field
29740  *  0b1..Write 0 to all fields in EEI
29741  */
29742 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
29743 
29744 #define DMA_CEEI_NOP_MASK                        (0x80U)
29745 #define DMA_CEEI_NOP_SHIFT                       (7U)
29746 /*! NOP - No Op Enable
29747  *  0b0..Normal operation
29748  *  0b1..No operation, ignore the other fields in this register
29749  */
29750 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
29751 /*! @} */
29752 
29753 /*! @name SEEI - Set Enable Error Interrupt */
29754 /*! @{ */
29755 
29756 #define DMA_SEEI_SEEI_MASK                       (0x1FU)
29757 #define DMA_SEEI_SEEI_SHIFT                      (0U)
29758 /*! SEEI - Set Enable Error Interrupt
29759  */
29760 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
29761 
29762 #define DMA_SEEI_SAEE_MASK                       (0x40U)
29763 #define DMA_SEEI_SAEE_SHIFT                      (6U)
29764 /*! SAEE - Set All Enable Error Interrupts
29765  *  0b0..Write 1 only to the EEI field specified in the SEEI field
29766  *  0b1..Writes 1 to all fields in EEI
29767  */
29768 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
29769 
29770 #define DMA_SEEI_NOP_MASK                        (0x80U)
29771 #define DMA_SEEI_NOP_SHIFT                       (7U)
29772 /*! NOP - No Op Enable
29773  *  0b0..Normal operation
29774  *  0b1..No operation, ignore the other fields in this register
29775  */
29776 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
29777 /*! @} */
29778 
29779 /*! @name CERQ - Clear Enable Request */
29780 /*! @{ */
29781 
29782 #define DMA_CERQ_CERQ_MASK                       (0x1FU)
29783 #define DMA_CERQ_CERQ_SHIFT                      (0U)
29784 /*! CERQ - Clear Enable Request
29785  */
29786 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
29787 
29788 #define DMA_CERQ_CAER_MASK                       (0x40U)
29789 #define DMA_CERQ_CAER_SHIFT                      (6U)
29790 /*! CAER - Clear All Enable Requests
29791  *  0b0..Write 0 to only the ERQ field specified in the CERQ field
29792  *  0b1..Write 0 to all fields in ERQ
29793  */
29794 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
29795 
29796 #define DMA_CERQ_NOP_MASK                        (0x80U)
29797 #define DMA_CERQ_NOP_SHIFT                       (7U)
29798 /*! NOP - No Op Enable
29799  *  0b0..Normal operation
29800  *  0b1..No operation, ignore the other fields in this register
29801  */
29802 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
29803 /*! @} */
29804 
29805 /*! @name SERQ - Set Enable Request */
29806 /*! @{ */
29807 
29808 #define DMA_SERQ_SERQ_MASK                       (0x1FU)
29809 #define DMA_SERQ_SERQ_SHIFT                      (0U)
29810 /*! SERQ - Set Enable Request
29811  */
29812 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
29813 
29814 #define DMA_SERQ_SAER_MASK                       (0x40U)
29815 #define DMA_SERQ_SAER_SHIFT                      (6U)
29816 /*! SAER - Set All Enable Requests
29817  *  0b0..Write 1 to only the ERQ field specified in the SERQ field
29818  *  0b1..Write 1 to all fields in ERQ
29819  */
29820 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
29821 
29822 #define DMA_SERQ_NOP_MASK                        (0x80U)
29823 #define DMA_SERQ_NOP_SHIFT                       (7U)
29824 /*! NOP - No Op Enable
29825  *  0b0..Normal operation
29826  *  0b1..No operation, ignore the other fields in this register
29827  */
29828 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
29829 /*! @} */
29830 
29831 /*! @name CDNE - Clear DONE Status Bit */
29832 /*! @{ */
29833 
29834 #define DMA_CDNE_CDNE_MASK                       (0x1FU)
29835 #define DMA_CDNE_CDNE_SHIFT                      (0U)
29836 /*! CDNE - Clear DONE field
29837  */
29838 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
29839 
29840 #define DMA_CDNE_CADN_MASK                       (0x40U)
29841 #define DMA_CDNE_CADN_SHIFT                      (6U)
29842 /*! CADN - Clears All DONE fields
29843  *  0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
29844  *  0b1..Writes 0 to all bits in TCDn_CSR[DONE]
29845  */
29846 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
29847 
29848 #define DMA_CDNE_NOP_MASK                        (0x80U)
29849 #define DMA_CDNE_NOP_SHIFT                       (7U)
29850 /*! NOP - No Op Enable
29851  *  0b0..Normal operation
29852  *  0b1..No operation; all other fields in this register are ignored.
29853  */
29854 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
29855 /*! @} */
29856 
29857 /*! @name SSRT - Set START Bit */
29858 /*! @{ */
29859 
29860 #define DMA_SSRT_SSRT_MASK                       (0x1FU)
29861 #define DMA_SSRT_SSRT_SHIFT                      (0U)
29862 /*! SSRT - Set START field
29863  */
29864 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
29865 
29866 #define DMA_SSRT_SAST_MASK                       (0x40U)
29867 #define DMA_SSRT_SAST_SHIFT                      (6U)
29868 /*! SAST - Set All START fields (activates all channels)
29869  *  0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
29870  *  0b1..Write 1 to all bits in TCDn_CSR[START]
29871  */
29872 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
29873 
29874 #define DMA_SSRT_NOP_MASK                        (0x80U)
29875 #define DMA_SSRT_NOP_SHIFT                       (7U)
29876 /*! NOP - No Op Enable
29877  *  0b0..Normal operation
29878  *  0b1..No operation; all other fields in this register are ignored.
29879  */
29880 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
29881 /*! @} */
29882 
29883 /*! @name CERR - Clear Error */
29884 /*! @{ */
29885 
29886 #define DMA_CERR_CERR_MASK                       (0x1FU)
29887 #define DMA_CERR_CERR_SHIFT                      (0U)
29888 /*! CERR - Clear Error Indicator
29889  */
29890 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
29891 
29892 #define DMA_CERR_CAEI_MASK                       (0x40U)
29893 #define DMA_CERR_CAEI_SHIFT                      (6U)
29894 /*! CAEI - Clear All Error Indicators
29895  *  0b0..Write 0 to only the ERR field specified in the CERR field
29896  *  0b1..Write 0 to all fields in ERR
29897  */
29898 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
29899 
29900 #define DMA_CERR_NOP_MASK                        (0x80U)
29901 #define DMA_CERR_NOP_SHIFT                       (7U)
29902 /*! NOP - No Op Enable
29903  *  0b0..Normal operation
29904  *  0b1..No operation; all other fields in this register are ignored.
29905  */
29906 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
29907 /*! @} */
29908 
29909 /*! @name CINT - Clear Interrupt Request */
29910 /*! @{ */
29911 
29912 #define DMA_CINT_CINT_MASK                       (0x1FU)
29913 #define DMA_CINT_CINT_SHIFT                      (0U)
29914 /*! CINT - Clear Interrupt Request
29915  */
29916 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
29917 
29918 #define DMA_CINT_CAIR_MASK                       (0x40U)
29919 #define DMA_CINT_CAIR_SHIFT                      (6U)
29920 /*! CAIR - Clear All Interrupt Requests
29921  *  0b0..Clear only the INT field specified in the CINT field
29922  *  0b1..Clear all bits in INT
29923  */
29924 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
29925 
29926 #define DMA_CINT_NOP_MASK                        (0x80U)
29927 #define DMA_CINT_NOP_SHIFT                       (7U)
29928 /*! NOP - No Op Enable
29929  *  0b0..Normal operation
29930  *  0b1..No operation; all other fields in this register are ignored.
29931  */
29932 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
29933 /*! @} */
29934 
29935 /*! @name INT - Interrupt Request */
29936 /*! @{ */
29937 
29938 #define DMA_INT_INT0_MASK                        (0x1U)
29939 #define DMA_INT_INT0_SHIFT                       (0U)
29940 /*! INT0 - Interrupt Request 0
29941  *  0b0..The interrupt request for channel 0 is cleared
29942  *  0b1..The interrupt request for channel 0 is active
29943  */
29944 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
29945 
29946 #define DMA_INT_INT1_MASK                        (0x2U)
29947 #define DMA_INT_INT1_SHIFT                       (1U)
29948 /*! INT1 - Interrupt Request 1
29949  *  0b0..The interrupt request for channel 1 is cleared
29950  *  0b1..The interrupt request for channel 1 is active
29951  */
29952 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
29953 
29954 #define DMA_INT_INT2_MASK                        (0x4U)
29955 #define DMA_INT_INT2_SHIFT                       (2U)
29956 /*! INT2 - Interrupt Request 2
29957  *  0b0..The interrupt request for channel 2 is cleared
29958  *  0b1..The interrupt request for channel 2 is active
29959  */
29960 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
29961 
29962 #define DMA_INT_INT3_MASK                        (0x8U)
29963 #define DMA_INT_INT3_SHIFT                       (3U)
29964 /*! INT3 - Interrupt Request 3
29965  *  0b0..The interrupt request for channel 3 is cleared
29966  *  0b1..The interrupt request for channel 3 is active
29967  */
29968 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
29969 
29970 #define DMA_INT_INT4_MASK                        (0x10U)
29971 #define DMA_INT_INT4_SHIFT                       (4U)
29972 /*! INT4 - Interrupt Request 4
29973  *  0b0..The interrupt request for channel 4 is cleared
29974  *  0b1..The interrupt request for channel 4 is active
29975  */
29976 #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
29977 
29978 #define DMA_INT_INT5_MASK                        (0x20U)
29979 #define DMA_INT_INT5_SHIFT                       (5U)
29980 /*! INT5 - Interrupt Request 5
29981  *  0b0..The interrupt request for channel 5 is cleared
29982  *  0b1..The interrupt request for channel 5 is active
29983  */
29984 #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
29985 
29986 #define DMA_INT_INT6_MASK                        (0x40U)
29987 #define DMA_INT_INT6_SHIFT                       (6U)
29988 /*! INT6 - Interrupt Request 6
29989  *  0b0..The interrupt request for channel 6 is cleared
29990  *  0b1..The interrupt request for channel 6 is active
29991  */
29992 #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
29993 
29994 #define DMA_INT_INT7_MASK                        (0x80U)
29995 #define DMA_INT_INT7_SHIFT                       (7U)
29996 /*! INT7 - Interrupt Request 7
29997  *  0b0..The interrupt request for channel 7 is cleared
29998  *  0b1..The interrupt request for channel 7 is active
29999  */
30000 #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
30001 
30002 #define DMA_INT_INT8_MASK                        (0x100U)
30003 #define DMA_INT_INT8_SHIFT                       (8U)
30004 /*! INT8 - Interrupt Request 8
30005  *  0b0..The interrupt request for channel 8 is cleared
30006  *  0b1..The interrupt request for channel 8 is active
30007  */
30008 #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
30009 
30010 #define DMA_INT_INT9_MASK                        (0x200U)
30011 #define DMA_INT_INT9_SHIFT                       (9U)
30012 /*! INT9 - Interrupt Request 9
30013  *  0b0..The interrupt request for channel 9 is cleared
30014  *  0b1..The interrupt request for channel 9 is active
30015  */
30016 #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
30017 
30018 #define DMA_INT_INT10_MASK                       (0x400U)
30019 #define DMA_INT_INT10_SHIFT                      (10U)
30020 /*! INT10 - Interrupt Request 10
30021  *  0b0..The interrupt request for channel 10 is cleared
30022  *  0b1..The interrupt request for channel 10 is active
30023  */
30024 #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
30025 
30026 #define DMA_INT_INT11_MASK                       (0x800U)
30027 #define DMA_INT_INT11_SHIFT                      (11U)
30028 /*! INT11 - Interrupt Request 11
30029  *  0b0..The interrupt request for channel 11 is cleared
30030  *  0b1..The interrupt request for channel 11 is active
30031  */
30032 #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
30033 
30034 #define DMA_INT_INT12_MASK                       (0x1000U)
30035 #define DMA_INT_INT12_SHIFT                      (12U)
30036 /*! INT12 - Interrupt Request 12
30037  *  0b0..The interrupt request for channel 12 is cleared
30038  *  0b1..The interrupt request for channel 12 is active
30039  */
30040 #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
30041 
30042 #define DMA_INT_INT13_MASK                       (0x2000U)
30043 #define DMA_INT_INT13_SHIFT                      (13U)
30044 /*! INT13 - Interrupt Request 13
30045  *  0b0..The interrupt request for channel 13 is cleared
30046  *  0b1..The interrupt request for channel 13 is active
30047  */
30048 #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
30049 
30050 #define DMA_INT_INT14_MASK                       (0x4000U)
30051 #define DMA_INT_INT14_SHIFT                      (14U)
30052 /*! INT14 - Interrupt Request 14
30053  *  0b0..The interrupt request for channel 14 is cleared
30054  *  0b1..The interrupt request for channel 14 is active
30055  */
30056 #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
30057 
30058 #define DMA_INT_INT15_MASK                       (0x8000U)
30059 #define DMA_INT_INT15_SHIFT                      (15U)
30060 /*! INT15 - Interrupt Request 15
30061  *  0b0..The interrupt request for channel 15 is cleared
30062  *  0b1..The interrupt request for channel 15 is active
30063  */
30064 #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
30065 
30066 #define DMA_INT_INT16_MASK                       (0x10000U)
30067 #define DMA_INT_INT16_SHIFT                      (16U)
30068 /*! INT16 - Interrupt Request 16
30069  *  0b0..The interrupt request for channel 16 is cleared
30070  *  0b1..The interrupt request for channel 16 is active
30071  */
30072 #define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
30073 
30074 #define DMA_INT_INT17_MASK                       (0x20000U)
30075 #define DMA_INT_INT17_SHIFT                      (17U)
30076 /*! INT17 - Interrupt Request 17
30077  *  0b0..The interrupt request for channel 17 is cleared
30078  *  0b1..The interrupt request for channel 17 is active
30079  */
30080 #define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
30081 
30082 #define DMA_INT_INT18_MASK                       (0x40000U)
30083 #define DMA_INT_INT18_SHIFT                      (18U)
30084 /*! INT18 - Interrupt Request 18
30085  *  0b0..The interrupt request for channel 18 is cleared
30086  *  0b1..The interrupt request for channel 18 is active
30087  */
30088 #define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
30089 
30090 #define DMA_INT_INT19_MASK                       (0x80000U)
30091 #define DMA_INT_INT19_SHIFT                      (19U)
30092 /*! INT19 - Interrupt Request 19
30093  *  0b0..The interrupt request for channel 19 is cleared
30094  *  0b1..The interrupt request for channel 19 is active
30095  */
30096 #define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
30097 
30098 #define DMA_INT_INT20_MASK                       (0x100000U)
30099 #define DMA_INT_INT20_SHIFT                      (20U)
30100 /*! INT20 - Interrupt Request 20
30101  *  0b0..The interrupt request for channel 20 is cleared
30102  *  0b1..The interrupt request for channel 20 is active
30103  */
30104 #define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
30105 
30106 #define DMA_INT_INT21_MASK                       (0x200000U)
30107 #define DMA_INT_INT21_SHIFT                      (21U)
30108 /*! INT21 - Interrupt Request 21
30109  *  0b0..The interrupt request for channel 21 is cleared
30110  *  0b1..The interrupt request for channel 21 is active
30111  */
30112 #define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
30113 
30114 #define DMA_INT_INT22_MASK                       (0x400000U)
30115 #define DMA_INT_INT22_SHIFT                      (22U)
30116 /*! INT22 - Interrupt Request 22
30117  *  0b0..The interrupt request for channel 22 is cleared
30118  *  0b1..The interrupt request for channel 22 is active
30119  */
30120 #define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
30121 
30122 #define DMA_INT_INT23_MASK                       (0x800000U)
30123 #define DMA_INT_INT23_SHIFT                      (23U)
30124 /*! INT23 - Interrupt Request 23
30125  *  0b0..The interrupt request for channel 23 is cleared
30126  *  0b1..The interrupt request for channel 23 is active
30127  */
30128 #define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
30129 
30130 #define DMA_INT_INT24_MASK                       (0x1000000U)
30131 #define DMA_INT_INT24_SHIFT                      (24U)
30132 /*! INT24 - Interrupt Request 24
30133  *  0b0..The interrupt request for channel 24 is cleared
30134  *  0b1..The interrupt request for channel 24 is active
30135  */
30136 #define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
30137 
30138 #define DMA_INT_INT25_MASK                       (0x2000000U)
30139 #define DMA_INT_INT25_SHIFT                      (25U)
30140 /*! INT25 - Interrupt Request 25
30141  *  0b0..The interrupt request for channel 25 is cleared
30142  *  0b1..The interrupt request for channel 25 is active
30143  */
30144 #define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
30145 
30146 #define DMA_INT_INT26_MASK                       (0x4000000U)
30147 #define DMA_INT_INT26_SHIFT                      (26U)
30148 /*! INT26 - Interrupt Request 26
30149  *  0b0..The interrupt request for channel 26 is cleared
30150  *  0b1..The interrupt request for channel 26 is active
30151  */
30152 #define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
30153 
30154 #define DMA_INT_INT27_MASK                       (0x8000000U)
30155 #define DMA_INT_INT27_SHIFT                      (27U)
30156 /*! INT27 - Interrupt Request 27
30157  *  0b0..The interrupt request for channel 27 is cleared
30158  *  0b1..The interrupt request for channel 27 is active
30159  */
30160 #define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
30161 
30162 #define DMA_INT_INT28_MASK                       (0x10000000U)
30163 #define DMA_INT_INT28_SHIFT                      (28U)
30164 /*! INT28 - Interrupt Request 28
30165  *  0b0..The interrupt request for channel 28 is cleared
30166  *  0b1..The interrupt request for channel 28 is active
30167  */
30168 #define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
30169 
30170 #define DMA_INT_INT29_MASK                       (0x20000000U)
30171 #define DMA_INT_INT29_SHIFT                      (29U)
30172 /*! INT29 - Interrupt Request 29
30173  *  0b0..The interrupt request for channel 29 is cleared
30174  *  0b1..The interrupt request for channel 29 is active
30175  */
30176 #define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
30177 
30178 #define DMA_INT_INT30_MASK                       (0x40000000U)
30179 #define DMA_INT_INT30_SHIFT                      (30U)
30180 /*! INT30 - Interrupt Request 30
30181  *  0b0..The interrupt request for channel 30 is cleared
30182  *  0b1..The interrupt request for channel 30 is active
30183  */
30184 #define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
30185 
30186 #define DMA_INT_INT31_MASK                       (0x80000000U)
30187 #define DMA_INT_INT31_SHIFT                      (31U)
30188 /*! INT31 - Interrupt Request 31
30189  *  0b0..The interrupt request for channel 31 is cleared
30190  *  0b1..The interrupt request for channel 31 is active
30191  */
30192 #define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
30193 /*! @} */
30194 
30195 /*! @name ERR - Error */
30196 /*! @{ */
30197 
30198 #define DMA_ERR_ERR0_MASK                        (0x1U)
30199 #define DMA_ERR_ERR0_SHIFT                       (0U)
30200 /*! ERR0 - Error In Channel 0
30201  *  0b0..No error in this channel has occurred
30202  *  0b1..An error in this channel has occurred
30203  */
30204 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
30205 
30206 #define DMA_ERR_ERR1_MASK                        (0x2U)
30207 #define DMA_ERR_ERR1_SHIFT                       (1U)
30208 /*! ERR1 - Error In Channel 1
30209  *  0b0..No error in this channel has occurred
30210  *  0b1..An error in this channel has occurred
30211  */
30212 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
30213 
30214 #define DMA_ERR_ERR2_MASK                        (0x4U)
30215 #define DMA_ERR_ERR2_SHIFT                       (2U)
30216 /*! ERR2 - Error In Channel 2
30217  *  0b0..No error in this channel has occurred
30218  *  0b1..An error in this channel has occurred
30219  */
30220 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
30221 
30222 #define DMA_ERR_ERR3_MASK                        (0x8U)
30223 #define DMA_ERR_ERR3_SHIFT                       (3U)
30224 /*! ERR3 - Error In Channel 3
30225  *  0b0..No error in this channel has occurred
30226  *  0b1..An error in this channel has occurred
30227  */
30228 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
30229 
30230 #define DMA_ERR_ERR4_MASK                        (0x10U)
30231 #define DMA_ERR_ERR4_SHIFT                       (4U)
30232 /*! ERR4 - Error In Channel 4
30233  *  0b0..No error in this channel has occurred
30234  *  0b1..An error in this channel has occurred
30235  */
30236 #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
30237 
30238 #define DMA_ERR_ERR5_MASK                        (0x20U)
30239 #define DMA_ERR_ERR5_SHIFT                       (5U)
30240 /*! ERR5 - Error In Channel 5
30241  *  0b0..No error in this channel has occurred
30242  *  0b1..An error in this channel has occurred
30243  */
30244 #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
30245 
30246 #define DMA_ERR_ERR6_MASK                        (0x40U)
30247 #define DMA_ERR_ERR6_SHIFT                       (6U)
30248 /*! ERR6 - Error In Channel 6
30249  *  0b0..No error in this channel has occurred
30250  *  0b1..An error in this channel has occurred
30251  */
30252 #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
30253 
30254 #define DMA_ERR_ERR7_MASK                        (0x80U)
30255 #define DMA_ERR_ERR7_SHIFT                       (7U)
30256 /*! ERR7 - Error In Channel 7
30257  *  0b0..No error in this channel has occurred
30258  *  0b1..An error in this channel has occurred
30259  */
30260 #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
30261 
30262 #define DMA_ERR_ERR8_MASK                        (0x100U)
30263 #define DMA_ERR_ERR8_SHIFT                       (8U)
30264 /*! ERR8 - Error In Channel 8
30265  *  0b0..No error in this channel has occurred
30266  *  0b1..An error in this channel has occurred
30267  */
30268 #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
30269 
30270 #define DMA_ERR_ERR9_MASK                        (0x200U)
30271 #define DMA_ERR_ERR9_SHIFT                       (9U)
30272 /*! ERR9 - Error In Channel 9
30273  *  0b0..No error in this channel has occurred
30274  *  0b1..An error in this channel has occurred
30275  */
30276 #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
30277 
30278 #define DMA_ERR_ERR10_MASK                       (0x400U)
30279 #define DMA_ERR_ERR10_SHIFT                      (10U)
30280 /*! ERR10 - Error In Channel 10
30281  *  0b0..No error in this channel has occurred
30282  *  0b1..An error in this channel has occurred
30283  */
30284 #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
30285 
30286 #define DMA_ERR_ERR11_MASK                       (0x800U)
30287 #define DMA_ERR_ERR11_SHIFT                      (11U)
30288 /*! ERR11 - Error In Channel 11
30289  *  0b0..No error in this channel has occurred
30290  *  0b1..An error in this channel has occurred
30291  */
30292 #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
30293 
30294 #define DMA_ERR_ERR12_MASK                       (0x1000U)
30295 #define DMA_ERR_ERR12_SHIFT                      (12U)
30296 /*! ERR12 - Error In Channel 12
30297  *  0b0..No error in this channel has occurred
30298  *  0b1..An error in this channel has occurred
30299  */
30300 #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
30301 
30302 #define DMA_ERR_ERR13_MASK                       (0x2000U)
30303 #define DMA_ERR_ERR13_SHIFT                      (13U)
30304 /*! ERR13 - Error In Channel 13
30305  *  0b0..No error in this channel has occurred
30306  *  0b1..An error in this channel has occurred
30307  */
30308 #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
30309 
30310 #define DMA_ERR_ERR14_MASK                       (0x4000U)
30311 #define DMA_ERR_ERR14_SHIFT                      (14U)
30312 /*! ERR14 - Error In Channel 14
30313  *  0b0..No error in this channel has occurred
30314  *  0b1..An error in this channel has occurred
30315  */
30316 #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
30317 
30318 #define DMA_ERR_ERR15_MASK                       (0x8000U)
30319 #define DMA_ERR_ERR15_SHIFT                      (15U)
30320 /*! ERR15 - Error In Channel 15
30321  *  0b0..No error in this channel has occurred
30322  *  0b1..An error in this channel has occurred
30323  */
30324 #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
30325 
30326 #define DMA_ERR_ERR16_MASK                       (0x10000U)
30327 #define DMA_ERR_ERR16_SHIFT                      (16U)
30328 /*! ERR16 - Error In Channel 16
30329  *  0b0..No error in this channel has occurred
30330  *  0b1..An error in this channel has occurred
30331  */
30332 #define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
30333 
30334 #define DMA_ERR_ERR17_MASK                       (0x20000U)
30335 #define DMA_ERR_ERR17_SHIFT                      (17U)
30336 /*! ERR17 - Error In Channel 17
30337  *  0b0..No error in this channel has occurred
30338  *  0b1..An error in this channel has occurred
30339  */
30340 #define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
30341 
30342 #define DMA_ERR_ERR18_MASK                       (0x40000U)
30343 #define DMA_ERR_ERR18_SHIFT                      (18U)
30344 /*! ERR18 - Error In Channel 18
30345  *  0b0..No error in this channel has occurred
30346  *  0b1..An error in this channel has occurred
30347  */
30348 #define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
30349 
30350 #define DMA_ERR_ERR19_MASK                       (0x80000U)
30351 #define DMA_ERR_ERR19_SHIFT                      (19U)
30352 /*! ERR19 - Error In Channel 19
30353  *  0b0..No error in this channel has occurred
30354  *  0b1..An error in this channel has occurred
30355  */
30356 #define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
30357 
30358 #define DMA_ERR_ERR20_MASK                       (0x100000U)
30359 #define DMA_ERR_ERR20_SHIFT                      (20U)
30360 /*! ERR20 - Error In Channel 20
30361  *  0b0..No error in this channel has occurred
30362  *  0b1..An error in this channel has occurred
30363  */
30364 #define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
30365 
30366 #define DMA_ERR_ERR21_MASK                       (0x200000U)
30367 #define DMA_ERR_ERR21_SHIFT                      (21U)
30368 /*! ERR21 - Error In Channel 21
30369  *  0b0..No error in this channel has occurred
30370  *  0b1..An error in this channel has occurred
30371  */
30372 #define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
30373 
30374 #define DMA_ERR_ERR22_MASK                       (0x400000U)
30375 #define DMA_ERR_ERR22_SHIFT                      (22U)
30376 /*! ERR22 - Error In Channel 22
30377  *  0b0..No error in this channel has occurred
30378  *  0b1..An error in this channel has occurred
30379  */
30380 #define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
30381 
30382 #define DMA_ERR_ERR23_MASK                       (0x800000U)
30383 #define DMA_ERR_ERR23_SHIFT                      (23U)
30384 /*! ERR23 - Error In Channel 23
30385  *  0b0..No error in this channel has occurred
30386  *  0b1..An error in this channel has occurred
30387  */
30388 #define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
30389 
30390 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
30391 #define DMA_ERR_ERR24_SHIFT                      (24U)
30392 /*! ERR24 - Error In Channel 24
30393  *  0b0..No error in this channel has occurred
30394  *  0b1..An error in this channel has occurred
30395  */
30396 #define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
30397 
30398 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
30399 #define DMA_ERR_ERR25_SHIFT                      (25U)
30400 /*! ERR25 - Error In Channel 25
30401  *  0b0..No error in this channel has occurred
30402  *  0b1..An error in this channel has occurred
30403  */
30404 #define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
30405 
30406 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
30407 #define DMA_ERR_ERR26_SHIFT                      (26U)
30408 /*! ERR26 - Error In Channel 26
30409  *  0b0..No error in this channel has occurred
30410  *  0b1..An error in this channel has occurred
30411  */
30412 #define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
30413 
30414 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
30415 #define DMA_ERR_ERR27_SHIFT                      (27U)
30416 /*! ERR27 - Error In Channel 27
30417  *  0b0..No error in this channel has occurred
30418  *  0b1..An error in this channel has occurred
30419  */
30420 #define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
30421 
30422 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
30423 #define DMA_ERR_ERR28_SHIFT                      (28U)
30424 /*! ERR28 - Error In Channel 28
30425  *  0b0..No error in this channel has occurred
30426  *  0b1..An error in this channel has occurred
30427  */
30428 #define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
30429 
30430 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
30431 #define DMA_ERR_ERR29_SHIFT                      (29U)
30432 /*! ERR29 - Error In Channel 29
30433  *  0b0..No error in this channel has occurred
30434  *  0b1..An error in this channel has occurred
30435  */
30436 #define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
30437 
30438 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
30439 #define DMA_ERR_ERR30_SHIFT                      (30U)
30440 /*! ERR30 - Error In Channel 30
30441  *  0b0..No error in this channel has occurred
30442  *  0b1..An error in this channel has occurred
30443  */
30444 #define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
30445 
30446 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
30447 #define DMA_ERR_ERR31_SHIFT                      (31U)
30448 /*! ERR31 - Error In Channel 31
30449  *  0b0..No error in this channel has occurred
30450  *  0b1..An error in this channel has occurred
30451  */
30452 #define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
30453 /*! @} */
30454 
30455 /*! @name HRS - Hardware Request Status */
30456 /*! @{ */
30457 
30458 #define DMA_HRS_HRS0_MASK                        (0x1U)
30459 #define DMA_HRS_HRS0_SHIFT                       (0U)
30460 /*! HRS0 - Hardware Request Status Channel 0
30461  *  0b0..A hardware service request for channel 0 is not present
30462  *  0b1..A hardware service request for channel 0 is present
30463  */
30464 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
30465 
30466 #define DMA_HRS_HRS1_MASK                        (0x2U)
30467 #define DMA_HRS_HRS1_SHIFT                       (1U)
30468 /*! HRS1 - Hardware Request Status Channel 1
30469  *  0b0..A hardware service request for channel 1 is not present
30470  *  0b1..A hardware service request for channel 1 is present
30471  */
30472 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
30473 
30474 #define DMA_HRS_HRS2_MASK                        (0x4U)
30475 #define DMA_HRS_HRS2_SHIFT                       (2U)
30476 /*! HRS2 - Hardware Request Status Channel 2
30477  *  0b0..A hardware service request for channel 2 is not present
30478  *  0b1..A hardware service request for channel 2 is present
30479  */
30480 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
30481 
30482 #define DMA_HRS_HRS3_MASK                        (0x8U)
30483 #define DMA_HRS_HRS3_SHIFT                       (3U)
30484 /*! HRS3 - Hardware Request Status Channel 3
30485  *  0b0..A hardware service request for channel 3 is not present
30486  *  0b1..A hardware service request for channel 3 is present
30487  */
30488 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
30489 
30490 #define DMA_HRS_HRS4_MASK                        (0x10U)
30491 #define DMA_HRS_HRS4_SHIFT                       (4U)
30492 /*! HRS4 - Hardware Request Status Channel 4
30493  *  0b0..A hardware service request for channel 4 is not present
30494  *  0b1..A hardware service request for channel 4 is present
30495  */
30496 #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
30497 
30498 #define DMA_HRS_HRS5_MASK                        (0x20U)
30499 #define DMA_HRS_HRS5_SHIFT                       (5U)
30500 /*! HRS5 - Hardware Request Status Channel 5
30501  *  0b0..A hardware service request for channel 5 is not present
30502  *  0b1..A hardware service request for channel 5 is present
30503  */
30504 #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
30505 
30506 #define DMA_HRS_HRS6_MASK                        (0x40U)
30507 #define DMA_HRS_HRS6_SHIFT                       (6U)
30508 /*! HRS6 - Hardware Request Status Channel 6
30509  *  0b0..A hardware service request for channel 6 is not present
30510  *  0b1..A hardware service request for channel 6 is present
30511  */
30512 #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
30513 
30514 #define DMA_HRS_HRS7_MASK                        (0x80U)
30515 #define DMA_HRS_HRS7_SHIFT                       (7U)
30516 /*! HRS7 - Hardware Request Status Channel 7
30517  *  0b0..A hardware service request for channel 7 is not present
30518  *  0b1..A hardware service request for channel 7 is present
30519  */
30520 #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
30521 
30522 #define DMA_HRS_HRS8_MASK                        (0x100U)
30523 #define DMA_HRS_HRS8_SHIFT                       (8U)
30524 /*! HRS8 - Hardware Request Status Channel 8
30525  *  0b0..A hardware service request for channel 8 is not present
30526  *  0b1..A hardware service request for channel 8 is present
30527  */
30528 #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
30529 
30530 #define DMA_HRS_HRS9_MASK                        (0x200U)
30531 #define DMA_HRS_HRS9_SHIFT                       (9U)
30532 /*! HRS9 - Hardware Request Status Channel 9
30533  *  0b0..A hardware service request for channel 9 is not present
30534  *  0b1..A hardware service request for channel 9 is present
30535  */
30536 #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
30537 
30538 #define DMA_HRS_HRS10_MASK                       (0x400U)
30539 #define DMA_HRS_HRS10_SHIFT                      (10U)
30540 /*! HRS10 - Hardware Request Status Channel 10
30541  *  0b0..A hardware service request for channel 10 is not present
30542  *  0b1..A hardware service request for channel 10 is present
30543  */
30544 #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
30545 
30546 #define DMA_HRS_HRS11_MASK                       (0x800U)
30547 #define DMA_HRS_HRS11_SHIFT                      (11U)
30548 /*! HRS11 - Hardware Request Status Channel 11
30549  *  0b0..A hardware service request for channel 11 is not present
30550  *  0b1..A hardware service request for channel 11 is present
30551  */
30552 #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
30553 
30554 #define DMA_HRS_HRS12_MASK                       (0x1000U)
30555 #define DMA_HRS_HRS12_SHIFT                      (12U)
30556 /*! HRS12 - Hardware Request Status Channel 12
30557  *  0b0..A hardware service request for channel 12 is not present
30558  *  0b1..A hardware service request for channel 12 is present
30559  */
30560 #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
30561 
30562 #define DMA_HRS_HRS13_MASK                       (0x2000U)
30563 #define DMA_HRS_HRS13_SHIFT                      (13U)
30564 /*! HRS13 - Hardware Request Status Channel 13
30565  *  0b0..A hardware service request for channel 13 is not present
30566  *  0b1..A hardware service request for channel 13 is present
30567  */
30568 #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
30569 
30570 #define DMA_HRS_HRS14_MASK                       (0x4000U)
30571 #define DMA_HRS_HRS14_SHIFT                      (14U)
30572 /*! HRS14 - Hardware Request Status Channel 14
30573  *  0b0..A hardware service request for channel 14 is not present
30574  *  0b1..A hardware service request for channel 14 is present
30575  */
30576 #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
30577 
30578 #define DMA_HRS_HRS15_MASK                       (0x8000U)
30579 #define DMA_HRS_HRS15_SHIFT                      (15U)
30580 /*! HRS15 - Hardware Request Status Channel 15
30581  *  0b0..A hardware service request for channel 15 is not present
30582  *  0b1..A hardware service request for channel 15 is present
30583  */
30584 #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
30585 
30586 #define DMA_HRS_HRS16_MASK                       (0x10000U)
30587 #define DMA_HRS_HRS16_SHIFT                      (16U)
30588 /*! HRS16 - Hardware Request Status Channel 16
30589  *  0b0..A hardware service request for channel 16 is not present
30590  *  0b1..A hardware service request for channel 16 is present
30591  */
30592 #define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
30593 
30594 #define DMA_HRS_HRS17_MASK                       (0x20000U)
30595 #define DMA_HRS_HRS17_SHIFT                      (17U)
30596 /*! HRS17 - Hardware Request Status Channel 17
30597  *  0b0..A hardware service request for channel 17 is not present
30598  *  0b1..A hardware service request for channel 17 is present
30599  */
30600 #define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
30601 
30602 #define DMA_HRS_HRS18_MASK                       (0x40000U)
30603 #define DMA_HRS_HRS18_SHIFT                      (18U)
30604 /*! HRS18 - Hardware Request Status Channel 18
30605  *  0b0..A hardware service request for channel 18 is not present
30606  *  0b1..A hardware service request for channel 18 is present
30607  */
30608 #define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
30609 
30610 #define DMA_HRS_HRS19_MASK                       (0x80000U)
30611 #define DMA_HRS_HRS19_SHIFT                      (19U)
30612 /*! HRS19 - Hardware Request Status Channel 19
30613  *  0b0..A hardware service request for channel 19 is not present
30614  *  0b1..A hardware service request for channel 19 is present
30615  */
30616 #define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
30617 
30618 #define DMA_HRS_HRS20_MASK                       (0x100000U)
30619 #define DMA_HRS_HRS20_SHIFT                      (20U)
30620 /*! HRS20 - Hardware Request Status Channel 20
30621  *  0b0..A hardware service request for channel 20 is not present
30622  *  0b1..A hardware service request for channel 20 is present
30623  */
30624 #define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
30625 
30626 #define DMA_HRS_HRS21_MASK                       (0x200000U)
30627 #define DMA_HRS_HRS21_SHIFT                      (21U)
30628 /*! HRS21 - Hardware Request Status Channel 21
30629  *  0b0..A hardware service request for channel 21 is not present
30630  *  0b1..A hardware service request for channel 21 is present
30631  */
30632 #define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
30633 
30634 #define DMA_HRS_HRS22_MASK                       (0x400000U)
30635 #define DMA_HRS_HRS22_SHIFT                      (22U)
30636 /*! HRS22 - Hardware Request Status Channel 22
30637  *  0b0..A hardware service request for channel 22 is not present
30638  *  0b1..A hardware service request for channel 22 is present
30639  */
30640 #define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
30641 
30642 #define DMA_HRS_HRS23_MASK                       (0x800000U)
30643 #define DMA_HRS_HRS23_SHIFT                      (23U)
30644 /*! HRS23 - Hardware Request Status Channel 23
30645  *  0b0..A hardware service request for channel 23 is not present
30646  *  0b1..A hardware service request for channel 23 is present
30647  */
30648 #define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
30649 
30650 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
30651 #define DMA_HRS_HRS24_SHIFT                      (24U)
30652 /*! HRS24 - Hardware Request Status Channel 24
30653  *  0b0..A hardware service request for channel 24 is not present
30654  *  0b1..A hardware service request for channel 24 is present
30655  */
30656 #define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
30657 
30658 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
30659 #define DMA_HRS_HRS25_SHIFT                      (25U)
30660 /*! HRS25 - Hardware Request Status Channel 25
30661  *  0b0..A hardware service request for channel 25 is not present
30662  *  0b1..A hardware service request for channel 25 is present
30663  */
30664 #define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
30665 
30666 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
30667 #define DMA_HRS_HRS26_SHIFT                      (26U)
30668 /*! HRS26 - Hardware Request Status Channel 26
30669  *  0b0..A hardware service request for channel 26 is not present
30670  *  0b1..A hardware service request for channel 26 is present
30671  */
30672 #define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
30673 
30674 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
30675 #define DMA_HRS_HRS27_SHIFT                      (27U)
30676 /*! HRS27 - Hardware Request Status Channel 27
30677  *  0b0..A hardware service request for channel 27 is not present
30678  *  0b1..A hardware service request for channel 27 is present
30679  */
30680 #define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
30681 
30682 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
30683 #define DMA_HRS_HRS28_SHIFT                      (28U)
30684 /*! HRS28 - Hardware Request Status Channel 28
30685  *  0b0..A hardware service request for channel 28 is not present
30686  *  0b1..A hardware service request for channel 28 is present
30687  */
30688 #define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
30689 
30690 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
30691 #define DMA_HRS_HRS29_SHIFT                      (29U)
30692 /*! HRS29 - Hardware Request Status Channel 29
30693  *  0b0..A hardware service request for channel 29 is not preset
30694  *  0b1..A hardware service request for channel 29 is present
30695  */
30696 #define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
30697 
30698 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
30699 #define DMA_HRS_HRS30_SHIFT                      (30U)
30700 /*! HRS30 - Hardware Request Status Channel 30
30701  *  0b0..A hardware service request for channel 30 is not present
30702  *  0b1..A hardware service request for channel 30 is present
30703  */
30704 #define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
30705 
30706 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
30707 #define DMA_HRS_HRS31_SHIFT                      (31U)
30708 /*! HRS31 - Hardware Request Status Channel 31
30709  *  0b0..A hardware service request for channel 31 is not present
30710  *  0b1..A hardware service request for channel 31 is present
30711  */
30712 #define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
30713 /*! @} */
30714 
30715 /*! @name EARS - Enable Asynchronous Request in Stop */
30716 /*! @{ */
30717 
30718 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
30719 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
30720 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
30721  *  0b0..Disable asynchronous DMA request for channel 0
30722  *  0b1..Enable asynchronous DMA request for channel 0
30723  */
30724 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
30725 
30726 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
30727 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
30728 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
30729  *  0b0..Disable asynchronous DMA request for channel 1
30730  *  0b1..Enable asynchronous DMA request for channel 1
30731  */
30732 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
30733 
30734 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
30735 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
30736 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
30737  *  0b0..Disable asynchronous DMA request for channel 2
30738  *  0b1..Enable asynchronous DMA request for channel 2
30739  */
30740 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
30741 
30742 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
30743 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
30744 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
30745  *  0b0..Disable asynchronous DMA request for channel 3
30746  *  0b1..Enable asynchronous DMA request for channel 3
30747  */
30748 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
30749 
30750 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
30751 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
30752 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4.
30753  *  0b0..Disable asynchronous DMA request for channel 4
30754  *  0b1..Enable asynchronous DMA request for channel 4
30755  */
30756 #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
30757 
30758 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
30759 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
30760 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5.
30761  *  0b0..Disable asynchronous DMA request for channel 5
30762  *  0b1..Enable asynchronous DMA request for channel 5
30763  */
30764 #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
30765 
30766 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
30767 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
30768 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6.
30769  *  0b0..Disable asynchronous DMA request for channel 6
30770  *  0b1..Enable asynchronous DMA request for channel 6
30771  */
30772 #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
30773 
30774 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
30775 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
30776 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7.
30777  *  0b0..Disable asynchronous DMA request for channel 7
30778  *  0b1..Enable asynchronous DMA request for channel 7
30779  */
30780 #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
30781 
30782 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
30783 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
30784 /*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8.
30785  *  0b0..Disable asynchronous DMA request for channel 8
30786  *  0b1..Enable asynchronous DMA request for channel 8
30787  */
30788 #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
30789 
30790 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
30791 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
30792 /*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9.
30793  *  0b0..Disable asynchronous DMA request for channel 9
30794  *  0b1..Enable asynchronous DMA request for channel 9
30795  */
30796 #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
30797 
30798 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
30799 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
30800 /*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10.
30801  *  0b0..Disable asynchronous DMA request for channel 10
30802  *  0b1..Enable asynchronous DMA request for channel 10
30803  */
30804 #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
30805 
30806 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
30807 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
30808 /*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11.
30809  *  0b0..Disable asynchronous DMA request for channel 11
30810  *  0b1..Enable asynchronous DMA request for channel 11
30811  */
30812 #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
30813 
30814 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
30815 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
30816 /*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12.
30817  *  0b0..Disable asynchronous DMA request for channel 12
30818  *  0b1..Enable asynchronous DMA request for channel 12
30819  */
30820 #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
30821 
30822 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
30823 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
30824 /*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13.
30825  *  0b0..Disable asynchronous DMA request for channel 13
30826  *  0b1..Enable asynchronous DMA request for channel 13
30827  */
30828 #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
30829 
30830 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
30831 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
30832 /*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14.
30833  *  0b0..Disable asynchronous DMA request for channel 14
30834  *  0b1..Enable asynchronous DMA request for channel 14
30835  */
30836 #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
30837 
30838 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
30839 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
30840 /*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15.
30841  *  0b0..Disable asynchronous DMA request for channel 15
30842  *  0b1..Enable asynchronous DMA request for channel 15
30843  */
30844 #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
30845 
30846 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
30847 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
30848 /*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16.
30849  *  0b0..Disable asynchronous DMA request for channel 16
30850  *  0b1..Enable asynchronous DMA request for channel 16
30851  */
30852 #define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
30853 
30854 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
30855 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
30856 /*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17.
30857  *  0b0..Disable asynchronous DMA request for channel 17
30858  *  0b1..Enable asynchronous DMA request for channel 17
30859  */
30860 #define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
30861 
30862 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
30863 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
30864 /*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18.
30865  *  0b0..Disable asynchronous DMA request for channel 18
30866  *  0b1..Enable asynchronous DMA request for channel 18
30867  */
30868 #define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
30869 
30870 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
30871 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
30872 /*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19.
30873  *  0b0..Disable asynchronous DMA request for channel 19
30874  *  0b1..Enable asynchronous DMA request for channel 19
30875  */
30876 #define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
30877 
30878 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
30879 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
30880 /*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20.
30881  *  0b0..Disable asynchronous DMA request for channel 20
30882  *  0b1..Enable asynchronous DMA request for channel 20
30883  */
30884 #define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
30885 
30886 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
30887 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
30888 /*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21.
30889  *  0b0..Disable asynchronous DMA request for channel 21
30890  *  0b1..Enable asynchronous DMA request for channel 21
30891  */
30892 #define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
30893 
30894 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
30895 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
30896 /*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22.
30897  *  0b0..Disable asynchronous DMA request for channel 22
30898  *  0b1..Enable asynchronous DMA request for channel 22
30899  */
30900 #define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
30901 
30902 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
30903 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
30904 /*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23.
30905  *  0b0..Disable asynchronous DMA request for channel 23
30906  *  0b1..Enable asynchronous DMA request for channel 23
30907  */
30908 #define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
30909 
30910 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
30911 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
30912 /*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24.
30913  *  0b0..Disable asynchronous DMA request for channel 24
30914  *  0b1..Enable asynchronous DMA request for channel 24
30915  */
30916 #define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
30917 
30918 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
30919 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
30920 /*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25.
30921  *  0b0..Disable asynchronous DMA request for channel 25
30922  *  0b1..Enable asynchronous DMA request for channel 25
30923  */
30924 #define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
30925 
30926 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
30927 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
30928 /*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26.
30929  *  0b0..Disable asynchronous DMA request for channel 26
30930  *  0b1..Enable asynchronous DMA request for channel 26
30931  */
30932 #define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
30933 
30934 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
30935 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
30936 /*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27.
30937  *  0b0..Disable asynchronous DMA request for channel 27
30938  *  0b1..Enable asynchronous DMA request for channel 27
30939  */
30940 #define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
30941 
30942 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
30943 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
30944 /*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28.
30945  *  0b0..Disable asynchronous DMA request for channel 28
30946  *  0b1..Enable asynchronous DMA request for channel 28
30947  */
30948 #define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
30949 
30950 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
30951 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
30952 /*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29.
30953  *  0b0..Disable asynchronous DMA request for channel 29
30954  *  0b1..Enable asynchronous DMA request for channel 29
30955  */
30956 #define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
30957 
30958 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
30959 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
30960 /*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30.
30961  *  0b0..Disable asynchronous DMA request for channel 30
30962  *  0b1..Enable asynchronous DMA request for channel 30
30963  */
30964 #define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
30965 
30966 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
30967 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
30968 /*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31.
30969  *  0b0..Disable asynchronous DMA request for channel 31
30970  *  0b1..Enable asynchronous DMA request for channel 31
30971  */
30972 #define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
30973 /*! @} */
30974 
30975 /*! @name DCHPRI3 - Channel Priority */
30976 /*! @{ */
30977 
30978 #define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
30979 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
30980 /*! CHPRI - Channel n Arbitration Priority
30981  */
30982 #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
30983 
30984 #define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
30985 #define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
30986 /*! GRPPRI - Channel n Current Group Priority
30987  */
30988 #define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
30989 
30990 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
30991 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
30992 /*! DPA - Disable Preempt Ability. This field resets to 0.
30993  *  0b0..Channel n can suspend a lower priority channel
30994  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30995  */
30996 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
30997 
30998 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
30999 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
31000 /*! ECP - Enable Channel Preemption. This field resets to 0.
31001  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31002  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31003  */
31004 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
31005 /*! @} */
31006 
31007 /*! @name DCHPRI2 - Channel Priority */
31008 /*! @{ */
31009 
31010 #define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
31011 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
31012 /*! CHPRI - Channel n Arbitration Priority
31013  */
31014 #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
31015 
31016 #define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
31017 #define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
31018 /*! GRPPRI - Channel n Current Group Priority
31019  */
31020 #define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
31021 
31022 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
31023 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
31024 /*! DPA - Disable Preempt Ability. This field resets to 0.
31025  *  0b0..Channel n can suspend a lower priority channel
31026  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31027  */
31028 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
31029 
31030 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
31031 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
31032 /*! ECP - Enable Channel Preemption. This field resets to 0.
31033  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31034  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31035  */
31036 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
31037 /*! @} */
31038 
31039 /*! @name DCHPRI1 - Channel Priority */
31040 /*! @{ */
31041 
31042 #define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
31043 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
31044 /*! CHPRI - Channel n Arbitration Priority
31045  */
31046 #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
31047 
31048 #define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
31049 #define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
31050 /*! GRPPRI - Channel n Current Group Priority
31051  */
31052 #define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
31053 
31054 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
31055 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
31056 /*! DPA - Disable Preempt Ability. This field resets to 0.
31057  *  0b0..Channel n can suspend a lower priority channel
31058  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31059  */
31060 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
31061 
31062 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
31063 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
31064 /*! ECP - Enable Channel Preemption. This field resets to 0.
31065  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31066  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31067  */
31068 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
31069 /*! @} */
31070 
31071 /*! @name DCHPRI0 - Channel Priority */
31072 /*! @{ */
31073 
31074 #define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
31075 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
31076 /*! CHPRI - Channel n Arbitration Priority
31077  */
31078 #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
31079 
31080 #define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
31081 #define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
31082 /*! GRPPRI - Channel n Current Group Priority
31083  */
31084 #define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
31085 
31086 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
31087 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
31088 /*! DPA - Disable Preempt Ability. This field resets to 0.
31089  *  0b0..Channel n can suspend a lower priority channel
31090  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31091  */
31092 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
31093 
31094 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
31095 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
31096 /*! ECP - Enable Channel Preemption. This field resets to 0.
31097  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31098  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31099  */
31100 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
31101 /*! @} */
31102 
31103 /*! @name DCHPRI7 - Channel Priority */
31104 /*! @{ */
31105 
31106 #define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
31107 #define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
31108 /*! CHPRI - Channel n Arbitration Priority
31109  */
31110 #define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
31111 
31112 #define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
31113 #define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
31114 /*! GRPPRI - Channel n Current Group Priority
31115  */
31116 #define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
31117 
31118 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
31119 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
31120 /*! DPA - Disable Preempt Ability. This field resets to 0.
31121  *  0b0..Channel n can suspend a lower priority channel
31122  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31123  */
31124 #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
31125 
31126 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
31127 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
31128 /*! ECP - Enable Channel Preemption. This field resets to 0.
31129  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31130  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31131  */
31132 #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
31133 /*! @} */
31134 
31135 /*! @name DCHPRI6 - Channel Priority */
31136 /*! @{ */
31137 
31138 #define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
31139 #define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
31140 /*! CHPRI - Channel n Arbitration Priority
31141  */
31142 #define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
31143 
31144 #define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
31145 #define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
31146 /*! GRPPRI - Channel n Current Group Priority
31147  */
31148 #define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
31149 
31150 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
31151 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
31152 /*! DPA - Disable Preempt Ability. This field resets to 0.
31153  *  0b0..Channel n can suspend a lower priority channel
31154  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31155  */
31156 #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
31157 
31158 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
31159 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
31160 /*! ECP - Enable Channel Preemption. This field resets to 0.
31161  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31162  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31163  */
31164 #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
31165 /*! @} */
31166 
31167 /*! @name DCHPRI5 - Channel Priority */
31168 /*! @{ */
31169 
31170 #define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
31171 #define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
31172 /*! CHPRI - Channel n Arbitration Priority
31173  */
31174 #define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
31175 
31176 #define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
31177 #define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
31178 /*! GRPPRI - Channel n Current Group Priority
31179  */
31180 #define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
31181 
31182 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
31183 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
31184 /*! DPA - Disable Preempt Ability. This field resets to 0.
31185  *  0b0..Channel n can suspend a lower priority channel
31186  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31187  */
31188 #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
31189 
31190 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
31191 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
31192 /*! ECP - Enable Channel Preemption. This field resets to 0.
31193  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31194  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31195  */
31196 #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
31197 /*! @} */
31198 
31199 /*! @name DCHPRI4 - Channel Priority */
31200 /*! @{ */
31201 
31202 #define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
31203 #define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
31204 /*! CHPRI - Channel n Arbitration Priority
31205  */
31206 #define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
31207 
31208 #define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
31209 #define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
31210 /*! GRPPRI - Channel n Current Group Priority
31211  */
31212 #define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
31213 
31214 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
31215 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
31216 /*! DPA - Disable Preempt Ability. This field resets to 0.
31217  *  0b0..Channel n can suspend a lower priority channel
31218  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31219  */
31220 #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
31221 
31222 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
31223 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
31224 /*! ECP - Enable Channel Preemption. This field resets to 0.
31225  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31226  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31227  */
31228 #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
31229 /*! @} */
31230 
31231 /*! @name DCHPRI11 - Channel Priority */
31232 /*! @{ */
31233 
31234 #define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
31235 #define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
31236 /*! CHPRI - Channel n Arbitration Priority
31237  */
31238 #define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
31239 
31240 #define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
31241 #define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
31242 /*! GRPPRI - Channel n Current Group Priority
31243  */
31244 #define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
31245 
31246 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
31247 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
31248 /*! DPA - Disable Preempt Ability. This field resets to 0.
31249  *  0b0..Channel n can suspend a lower priority channel
31250  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31251  */
31252 #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
31253 
31254 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
31255 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
31256 /*! ECP - Enable Channel Preemption. This field resets to 0.
31257  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31258  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31259  */
31260 #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
31261 /*! @} */
31262 
31263 /*! @name DCHPRI10 - Channel Priority */
31264 /*! @{ */
31265 
31266 #define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
31267 #define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
31268 /*! CHPRI - Channel n Arbitration Priority
31269  */
31270 #define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
31271 
31272 #define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
31273 #define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
31274 /*! GRPPRI - Channel n Current Group Priority
31275  */
31276 #define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
31277 
31278 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
31279 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
31280 /*! DPA - Disable Preempt Ability. This field resets to 0.
31281  *  0b0..Channel n can suspend a lower priority channel
31282  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31283  */
31284 #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
31285 
31286 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
31287 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
31288 /*! ECP - Enable Channel Preemption. This field resets to 0.
31289  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31290  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31291  */
31292 #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
31293 /*! @} */
31294 
31295 /*! @name DCHPRI9 - Channel Priority */
31296 /*! @{ */
31297 
31298 #define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
31299 #define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
31300 /*! CHPRI - Channel n Arbitration Priority
31301  */
31302 #define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
31303 
31304 #define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
31305 #define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
31306 /*! GRPPRI - Channel n Current Group Priority
31307  */
31308 #define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
31309 
31310 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
31311 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
31312 /*! DPA - Disable Preempt Ability. This field resets to 0.
31313  *  0b0..Channel n can suspend a lower priority channel
31314  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31315  */
31316 #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
31317 
31318 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
31319 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
31320 /*! ECP - Enable Channel Preemption. This field resets to 0.
31321  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31322  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31323  */
31324 #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
31325 /*! @} */
31326 
31327 /*! @name DCHPRI8 - Channel Priority */
31328 /*! @{ */
31329 
31330 #define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
31331 #define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
31332 /*! CHPRI - Channel n Arbitration Priority
31333  */
31334 #define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
31335 
31336 #define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
31337 #define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
31338 /*! GRPPRI - Channel n Current Group Priority
31339  */
31340 #define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
31341 
31342 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
31343 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
31344 /*! DPA - Disable Preempt Ability. This field resets to 0.
31345  *  0b0..Channel n can suspend a lower priority channel
31346  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31347  */
31348 #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
31349 
31350 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
31351 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
31352 /*! ECP - Enable Channel Preemption. This field resets to 0.
31353  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31354  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31355  */
31356 #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
31357 /*! @} */
31358 
31359 /*! @name DCHPRI15 - Channel Priority */
31360 /*! @{ */
31361 
31362 #define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
31363 #define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
31364 /*! CHPRI - Channel n Arbitration Priority
31365  */
31366 #define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
31367 
31368 #define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
31369 #define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
31370 /*! GRPPRI - Channel n Current Group Priority
31371  */
31372 #define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
31373 
31374 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
31375 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
31376 /*! DPA - Disable Preempt Ability. This field resets to 0.
31377  *  0b0..Channel n can suspend a lower priority channel
31378  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31379  */
31380 #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
31381 
31382 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
31383 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
31384 /*! ECP - Enable Channel Preemption. This field resets to 0.
31385  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31386  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31387  */
31388 #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
31389 /*! @} */
31390 
31391 /*! @name DCHPRI14 - Channel Priority */
31392 /*! @{ */
31393 
31394 #define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
31395 #define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
31396 /*! CHPRI - Channel n Arbitration Priority
31397  */
31398 #define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
31399 
31400 #define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
31401 #define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
31402 /*! GRPPRI - Channel n Current Group Priority
31403  */
31404 #define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
31405 
31406 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
31407 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
31408 /*! DPA - Disable Preempt Ability. This field resets to 0.
31409  *  0b0..Channel n can suspend a lower priority channel
31410  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31411  */
31412 #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
31413 
31414 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
31415 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
31416 /*! ECP - Enable Channel Preemption. This field resets to 0.
31417  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31418  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31419  */
31420 #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
31421 /*! @} */
31422 
31423 /*! @name DCHPRI13 - Channel Priority */
31424 /*! @{ */
31425 
31426 #define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
31427 #define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
31428 /*! CHPRI - Channel n Arbitration Priority
31429  */
31430 #define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
31431 
31432 #define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
31433 #define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
31434 /*! GRPPRI - Channel n Current Group Priority
31435  */
31436 #define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
31437 
31438 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
31439 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
31440 /*! DPA - Disable Preempt Ability. This field resets to 0.
31441  *  0b0..Channel n can suspend a lower priority channel
31442  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31443  */
31444 #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
31445 
31446 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
31447 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
31448 /*! ECP - Enable Channel Preemption. This field resets to 0.
31449  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31450  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31451  */
31452 #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
31453 /*! @} */
31454 
31455 /*! @name DCHPRI12 - Channel Priority */
31456 /*! @{ */
31457 
31458 #define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
31459 #define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
31460 /*! CHPRI - Channel n Arbitration Priority
31461  */
31462 #define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
31463 
31464 #define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
31465 #define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
31466 /*! GRPPRI - Channel n Current Group Priority
31467  */
31468 #define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
31469 
31470 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
31471 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
31472 /*! DPA - Disable Preempt Ability. This field resets to 0.
31473  *  0b0..Channel n can suspend a lower priority channel
31474  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31475  */
31476 #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
31477 
31478 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
31479 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
31480 /*! ECP - Enable Channel Preemption. This field resets to 0.
31481  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31482  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31483  */
31484 #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
31485 /*! @} */
31486 
31487 /*! @name DCHPRI19 - Channel Priority */
31488 /*! @{ */
31489 
31490 #define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
31491 #define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
31492 /*! CHPRI - Channel n Arbitration Priority
31493  */
31494 #define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
31495 
31496 #define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
31497 #define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
31498 /*! GRPPRI - Channel n Current Group Priority
31499  */
31500 #define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
31501 
31502 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
31503 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
31504 /*! DPA - Disable Preempt Ability. This field resets to 0.
31505  *  0b0..Channel n can suspend a lower priority channel
31506  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31507  */
31508 #define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
31509 
31510 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
31511 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
31512 /*! ECP - Enable Channel Preemption. This field resets to 0.
31513  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31514  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31515  */
31516 #define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
31517 /*! @} */
31518 
31519 /*! @name DCHPRI18 - Channel Priority */
31520 /*! @{ */
31521 
31522 #define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
31523 #define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
31524 /*! CHPRI - Channel n Arbitration Priority
31525  */
31526 #define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
31527 
31528 #define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
31529 #define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
31530 /*! GRPPRI - Channel n Current Group Priority
31531  */
31532 #define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
31533 
31534 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
31535 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
31536 /*! DPA - Disable Preempt Ability. This field resets to 0.
31537  *  0b0..Channel n can suspend a lower priority channel
31538  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31539  */
31540 #define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
31541 
31542 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
31543 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
31544 /*! ECP - Enable Channel Preemption. This field resets to 0.
31545  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31546  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31547  */
31548 #define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
31549 /*! @} */
31550 
31551 /*! @name DCHPRI17 - Channel Priority */
31552 /*! @{ */
31553 
31554 #define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
31555 #define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
31556 /*! CHPRI - Channel n Arbitration Priority
31557  */
31558 #define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
31559 
31560 #define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
31561 #define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
31562 /*! GRPPRI - Channel n Current Group Priority
31563  */
31564 #define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
31565 
31566 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
31567 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
31568 /*! DPA - Disable Preempt Ability. This field resets to 0.
31569  *  0b0..Channel n can suspend a lower priority channel
31570  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31571  */
31572 #define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
31573 
31574 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
31575 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
31576 /*! ECP - Enable Channel Preemption. This field resets to 0.
31577  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31578  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31579  */
31580 #define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
31581 /*! @} */
31582 
31583 /*! @name DCHPRI16 - Channel Priority */
31584 /*! @{ */
31585 
31586 #define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
31587 #define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
31588 /*! CHPRI - Channel n Arbitration Priority
31589  */
31590 #define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
31591 
31592 #define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
31593 #define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
31594 /*! GRPPRI - Channel n Current Group Priority
31595  */
31596 #define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
31597 
31598 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
31599 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
31600 /*! DPA - Disable Preempt Ability. This field resets to 0.
31601  *  0b0..Channel n can suspend a lower priority channel
31602  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31603  */
31604 #define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
31605 
31606 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
31607 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
31608 /*! ECP - Enable Channel Preemption. This field resets to 0.
31609  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31610  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31611  */
31612 #define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
31613 /*! @} */
31614 
31615 /*! @name DCHPRI23 - Channel Priority */
31616 /*! @{ */
31617 
31618 #define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
31619 #define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
31620 /*! CHPRI - Channel n Arbitration Priority
31621  */
31622 #define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
31623 
31624 #define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
31625 #define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
31626 /*! GRPPRI - Channel n Current Group Priority
31627  */
31628 #define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
31629 
31630 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
31631 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
31632 /*! DPA - Disable Preempt Ability. This field resets to 0.
31633  *  0b0..Channel n can suspend a lower priority channel
31634  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31635  */
31636 #define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
31637 
31638 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
31639 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
31640 /*! ECP - Enable Channel Preemption. This field resets to 0.
31641  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31642  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31643  */
31644 #define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
31645 /*! @} */
31646 
31647 /*! @name DCHPRI22 - Channel Priority */
31648 /*! @{ */
31649 
31650 #define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
31651 #define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
31652 /*! CHPRI - Channel n Arbitration Priority
31653  */
31654 #define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
31655 
31656 #define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
31657 #define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
31658 /*! GRPPRI - Channel n Current Group Priority
31659  */
31660 #define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
31661 
31662 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
31663 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
31664 /*! DPA - Disable Preempt Ability. This field resets to 0.
31665  *  0b0..Channel n can suspend a lower priority channel
31666  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31667  */
31668 #define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
31669 
31670 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
31671 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
31672 /*! ECP - Enable Channel Preemption. This field resets to 0.
31673  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31674  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31675  */
31676 #define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
31677 /*! @} */
31678 
31679 /*! @name DCHPRI21 - Channel Priority */
31680 /*! @{ */
31681 
31682 #define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
31683 #define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
31684 /*! CHPRI - Channel n Arbitration Priority
31685  */
31686 #define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
31687 
31688 #define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
31689 #define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
31690 /*! GRPPRI - Channel n Current Group Priority
31691  */
31692 #define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
31693 
31694 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
31695 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
31696 /*! DPA - Disable Preempt Ability. This field resets to 0.
31697  *  0b0..Channel n can suspend a lower priority channel
31698  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31699  */
31700 #define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
31701 
31702 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
31703 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
31704 /*! ECP - Enable Channel Preemption. This field resets to 0.
31705  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31706  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31707  */
31708 #define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
31709 /*! @} */
31710 
31711 /*! @name DCHPRI20 - Channel Priority */
31712 /*! @{ */
31713 
31714 #define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
31715 #define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
31716 /*! CHPRI - Channel n Arbitration Priority
31717  */
31718 #define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
31719 
31720 #define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
31721 #define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
31722 /*! GRPPRI - Channel n Current Group Priority
31723  */
31724 #define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
31725 
31726 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
31727 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
31728 /*! DPA - Disable Preempt Ability. This field resets to 0.
31729  *  0b0..Channel n can suspend a lower priority channel
31730  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31731  */
31732 #define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
31733 
31734 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
31735 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
31736 /*! ECP - Enable Channel Preemption. This field resets to 0.
31737  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31738  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31739  */
31740 #define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
31741 /*! @} */
31742 
31743 /*! @name DCHPRI27 - Channel Priority */
31744 /*! @{ */
31745 
31746 #define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
31747 #define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
31748 /*! CHPRI - Channel n Arbitration Priority
31749  */
31750 #define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
31751 
31752 #define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
31753 #define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
31754 /*! GRPPRI - Channel n Current Group Priority
31755  */
31756 #define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
31757 
31758 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
31759 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
31760 /*! DPA - Disable Preempt Ability. This field resets to 0.
31761  *  0b0..Channel n can suspend a lower priority channel
31762  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31763  */
31764 #define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
31765 
31766 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
31767 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
31768 /*! ECP - Enable Channel Preemption. This field resets to 0.
31769  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31770  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31771  */
31772 #define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
31773 /*! @} */
31774 
31775 /*! @name DCHPRI26 - Channel Priority */
31776 /*! @{ */
31777 
31778 #define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
31779 #define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
31780 /*! CHPRI - Channel n Arbitration Priority
31781  */
31782 #define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
31783 
31784 #define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
31785 #define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
31786 /*! GRPPRI - Channel n Current Group Priority
31787  */
31788 #define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
31789 
31790 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
31791 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
31792 /*! DPA - Disable Preempt Ability. This field resets to 0.
31793  *  0b0..Channel n can suspend a lower priority channel
31794  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31795  */
31796 #define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
31797 
31798 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
31799 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
31800 /*! ECP - Enable Channel Preemption. This field resets to 0.
31801  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31802  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31803  */
31804 #define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
31805 /*! @} */
31806 
31807 /*! @name DCHPRI25 - Channel Priority */
31808 /*! @{ */
31809 
31810 #define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
31811 #define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
31812 /*! CHPRI - Channel n Arbitration Priority
31813  */
31814 #define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
31815 
31816 #define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
31817 #define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
31818 /*! GRPPRI - Channel n Current Group Priority
31819  */
31820 #define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
31821 
31822 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
31823 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
31824 /*! DPA - Disable Preempt Ability. This field resets to 0.
31825  *  0b0..Channel n can suspend a lower priority channel
31826  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31827  */
31828 #define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
31829 
31830 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
31831 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
31832 /*! ECP - Enable Channel Preemption. This field resets to 0.
31833  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31834  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31835  */
31836 #define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
31837 /*! @} */
31838 
31839 /*! @name DCHPRI24 - Channel Priority */
31840 /*! @{ */
31841 
31842 #define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
31843 #define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
31844 /*! CHPRI - Channel n Arbitration Priority
31845  */
31846 #define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
31847 
31848 #define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
31849 #define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
31850 /*! GRPPRI - Channel n Current Group Priority
31851  */
31852 #define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
31853 
31854 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
31855 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
31856 /*! DPA - Disable Preempt Ability. This field resets to 0.
31857  *  0b0..Channel n can suspend a lower priority channel
31858  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31859  */
31860 #define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
31861 
31862 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
31863 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
31864 /*! ECP - Enable Channel Preemption. This field resets to 0.
31865  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31866  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31867  */
31868 #define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
31869 /*! @} */
31870 
31871 /*! @name DCHPRI31 - Channel Priority */
31872 /*! @{ */
31873 
31874 #define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
31875 #define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
31876 /*! CHPRI - Channel n Arbitration Priority
31877  */
31878 #define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
31879 
31880 #define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
31881 #define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
31882 /*! GRPPRI - Channel n Current Group Priority
31883  */
31884 #define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
31885 
31886 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
31887 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
31888 /*! DPA - Disable Preempt Ability. This field resets to 0.
31889  *  0b0..Channel n can suspend a lower priority channel
31890  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31891  */
31892 #define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
31893 
31894 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
31895 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
31896 /*! ECP - Enable Channel Preemption. This field resets to 0.
31897  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31898  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31899  */
31900 #define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
31901 /*! @} */
31902 
31903 /*! @name DCHPRI30 - Channel Priority */
31904 /*! @{ */
31905 
31906 #define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
31907 #define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
31908 /*! CHPRI - Channel n Arbitration Priority
31909  */
31910 #define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
31911 
31912 #define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
31913 #define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
31914 /*! GRPPRI - Channel n Current Group Priority
31915  */
31916 #define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
31917 
31918 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
31919 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
31920 /*! DPA - Disable Preempt Ability. This field resets to 0.
31921  *  0b0..Channel n can suspend a lower priority channel
31922  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31923  */
31924 #define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
31925 
31926 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
31927 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
31928 /*! ECP - Enable Channel Preemption. This field resets to 0.
31929  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31930  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31931  */
31932 #define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
31933 /*! @} */
31934 
31935 /*! @name DCHPRI29 - Channel Priority */
31936 /*! @{ */
31937 
31938 #define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
31939 #define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
31940 /*! CHPRI - Channel n Arbitration Priority
31941  */
31942 #define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
31943 
31944 #define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
31945 #define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
31946 /*! GRPPRI - Channel n Current Group Priority
31947  */
31948 #define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
31949 
31950 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
31951 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
31952 /*! DPA - Disable Preempt Ability. This field resets to 0.
31953  *  0b0..Channel n can suspend a lower priority channel
31954  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31955  */
31956 #define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
31957 
31958 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
31959 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
31960 /*! ECP - Enable Channel Preemption. This field resets to 0.
31961  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31962  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31963  */
31964 #define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
31965 /*! @} */
31966 
31967 /*! @name DCHPRI28 - Channel Priority */
31968 /*! @{ */
31969 
31970 #define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
31971 #define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
31972 /*! CHPRI - Channel n Arbitration Priority
31973  */
31974 #define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
31975 
31976 #define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
31977 #define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
31978 /*! GRPPRI - Channel n Current Group Priority
31979  */
31980 #define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
31981 
31982 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
31983 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
31984 /*! DPA - Disable Preempt Ability. This field resets to 0.
31985  *  0b0..Channel n can suspend a lower priority channel
31986  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31987  */
31988 #define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
31989 
31990 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
31991 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
31992 /*! ECP - Enable Channel Preemption. This field resets to 0.
31993  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31994  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31995  */
31996 #define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
31997 /*! @} */
31998 
31999 /*! @name SADDR - TCD Source Address */
32000 /*! @{ */
32001 
32002 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
32003 #define DMA_SADDR_SADDR_SHIFT                    (0U)
32004 /*! SADDR - Source Address
32005  */
32006 #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
32007 /*! @} */
32008 
32009 /* The count of DMA_SADDR */
32010 #define DMA_SADDR_COUNT                          (32U)
32011 
32012 /*! @name SOFF - TCD Signed Source Address Offset */
32013 /*! @{ */
32014 
32015 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
32016 #define DMA_SOFF_SOFF_SHIFT                      (0U)
32017 /*! SOFF - Source address signed offset
32018  */
32019 #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
32020 /*! @} */
32021 
32022 /* The count of DMA_SOFF */
32023 #define DMA_SOFF_COUNT                           (32U)
32024 
32025 /*! @name ATTR - TCD Transfer Attributes */
32026 /*! @{ */
32027 
32028 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
32029 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
32030 /*! DSIZE - Destination data transfer size
32031  */
32032 #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
32033 
32034 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
32035 #define DMA_ATTR_DMOD_SHIFT                      (3U)
32036 /*! DMOD - Destination Address Modulo
32037  */
32038 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
32039 
32040 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
32041 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
32042 /*! SSIZE - Source data transfer size
32043  *  0b000..8-bit
32044  *  0b001..16-bit
32045  *  0b010..32-bit
32046  *  0b011..64-bit
32047  *  0b100..Reserved
32048  *  0b101..32-byte burst (4 beats of 64 bits)
32049  *  0b110..Reserved
32050  *  0b111..Reserved
32051  */
32052 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
32053 
32054 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
32055 #define DMA_ATTR_SMOD_SHIFT                      (11U)
32056 /*! SMOD - Source Address Modulo
32057  *  0b00000..Source address modulo feature is disabled
32058  *  0b00001-0b11111..Value defines address range used to set up circular data queue
32059  */
32060 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
32061 /*! @} */
32062 
32063 /* The count of DMA_ATTR */
32064 #define DMA_ATTR_COUNT                           (32U)
32065 
32066 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
32067 /*! @{ */
32068 
32069 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
32070 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
32071 /*! NBYTES - Minor Byte Transfer Count
32072  */
32073 #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
32074 /*! @} */
32075 
32076 /* The count of DMA_NBYTES_MLNO */
32077 #define DMA_NBYTES_MLNO_COUNT                    (32U)
32078 
32079 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
32080 /*! @{ */
32081 
32082 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
32083 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
32084 /*! NBYTES - Minor Byte Transfer Count
32085  */
32086 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
32087 
32088 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
32089 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
32090 /*! DMLOE - Destination Minor Loop Offset Enable
32091  *  0b0..The minor loop offset is not applied to the DADDR
32092  *  0b1..The minor loop offset is applied to the DADDR
32093  */
32094 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
32095 
32096 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
32097 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
32098 /*! SMLOE - Source Minor Loop Offset Enable
32099  *  0b0..The minor loop offset is not applied to the SADDR
32100  *  0b1..The minor loop offset is applied to the SADDR
32101  */
32102 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
32103 /*! @} */
32104 
32105 /* The count of DMA_NBYTES_MLOFFNO */
32106 #define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
32107 
32108 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
32109 /*! @{ */
32110 
32111 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
32112 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
32113 /*! NBYTES - Minor Byte Transfer Count
32114  */
32115 #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
32116 
32117 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
32118 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
32119 /*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the
32120  *    source or destination address to form the next-state value after the minor loop completes.
32121  */
32122 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
32123 
32124 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
32125 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
32126 /*! DMLOE - Destination Minor Loop Offset Enable
32127  *  0b0..The minor loop offset is not applied to the DADDR
32128  *  0b1..The minor loop offset is applied to the DADDR
32129  */
32130 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
32131 
32132 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
32133 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
32134 /*! SMLOE - Source Minor Loop Offset Enable
32135  *  0b0..The minor loop offset is not applied to the SADDR
32136  *  0b1..The minor loop offset is applied to the SADDR
32137  */
32138 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
32139 /*! @} */
32140 
32141 /* The count of DMA_NBYTES_MLOFFYES */
32142 #define DMA_NBYTES_MLOFFYES_COUNT                (32U)
32143 
32144 /*! @name SLAST - TCD Last Source Address Adjustment */
32145 /*! @{ */
32146 
32147 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
32148 #define DMA_SLAST_SLAST_SHIFT                    (0U)
32149 /*! SLAST - Last Source Address Adjustment
32150  */
32151 #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
32152 /*! @} */
32153 
32154 /* The count of DMA_SLAST */
32155 #define DMA_SLAST_COUNT                          (32U)
32156 
32157 /*! @name DADDR - TCD Destination Address */
32158 /*! @{ */
32159 
32160 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
32161 #define DMA_DADDR_DADDR_SHIFT                    (0U)
32162 /*! DADDR - Destination Address
32163  */
32164 #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
32165 /*! @} */
32166 
32167 /* The count of DMA_DADDR */
32168 #define DMA_DADDR_COUNT                          (32U)
32169 
32170 /*! @name DOFF - TCD Signed Destination Address Offset */
32171 /*! @{ */
32172 
32173 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
32174 #define DMA_DOFF_DOFF_SHIFT                      (0U)
32175 /*! DOFF - Destination Address Signed Offset
32176  */
32177 #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
32178 /*! @} */
32179 
32180 /* The count of DMA_DOFF */
32181 #define DMA_DOFF_COUNT                           (32U)
32182 
32183 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
32184 /*! @{ */
32185 
32186 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
32187 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
32188 /*! CITER - Current Major Iteration Count
32189  */
32190 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
32191 
32192 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
32193 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
32194 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
32195  *  0b0..Channel-to-channel linking is disabled
32196  *  0b1..Channel-to-channel linking is enabled
32197  */
32198 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
32199 /*! @} */
32200 
32201 /* The count of DMA_CITER_ELINKNO */
32202 #define DMA_CITER_ELINKNO_COUNT                  (32U)
32203 
32204 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
32205 /*! @{ */
32206 
32207 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
32208 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
32209 /*! CITER - Current Major Iteration Count
32210  */
32211 #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
32212 
32213 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
32214 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
32215 /*! LINKCH - Minor Loop Link Channel Number
32216  */
32217 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
32218 
32219 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
32220 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
32221 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
32222  *  0b0..Channel-to-channel linking is disabled
32223  *  0b1..Channel-to-channel linking is enabled
32224  */
32225 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
32226 /*! @} */
32227 
32228 /* The count of DMA_CITER_ELINKYES */
32229 #define DMA_CITER_ELINKYES_COUNT                 (32U)
32230 
32231 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
32232 /*! @{ */
32233 
32234 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
32235 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
32236 /*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)
32237  */
32238 #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
32239 /*! @} */
32240 
32241 /* The count of DMA_DLAST_SGA */
32242 #define DMA_DLAST_SGA_COUNT                      (32U)
32243 
32244 /*! @name CSR - TCD Control and Status */
32245 /*! @{ */
32246 
32247 #define DMA_CSR_START_MASK                       (0x1U)
32248 #define DMA_CSR_START_SHIFT                      (0U)
32249 /*! START - Channel Start
32250  *  0b0..Channel is not explicitly started
32251  *  0b1..Channel is explicitly started via a software initiated service request
32252  */
32253 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
32254 
32255 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
32256 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
32257 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
32258  *  0b0..End of major loop interrupt is disabled
32259  *  0b1..End of major loop interrupt is enabled
32260  */
32261 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
32262 
32263 #define DMA_CSR_INTHALF_MASK                     (0x4U)
32264 #define DMA_CSR_INTHALF_SHIFT                    (2U)
32265 /*! INTHALF - Enable an interrupt when major counter is half complete.
32266  *  0b0..Half-point interrupt is disabled
32267  *  0b1..Half-point interrupt is enabled
32268  */
32269 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
32270 
32271 #define DMA_CSR_DREQ_MASK                        (0x8U)
32272 #define DMA_CSR_DREQ_SHIFT                       (3U)
32273 /*! DREQ - Disable Request
32274  *  0b0..The channel's ERQ field is not affected
32275  *  0b1..The channel's ERQ field value changes to 0 when the major loop is complete
32276  */
32277 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
32278 
32279 #define DMA_CSR_ESG_MASK                         (0x10U)
32280 #define DMA_CSR_ESG_SHIFT                        (4U)
32281 /*! ESG - Enable Scatter/Gather Processing
32282  *  0b0..The current channel's TCD is normal format
32283  *  0b1..The current channel's TCD specifies a scatter gather format
32284  */
32285 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
32286 
32287 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
32288 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
32289 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
32290  *  0b0..Channel-to-channel linking is disabled
32291  *  0b1..Channel-to-channel linking is enabled
32292  */
32293 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
32294 
32295 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
32296 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
32297 /*! ACTIVE - Channel Active
32298  */
32299 #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
32300 
32301 #define DMA_CSR_DONE_MASK                        (0x80U)
32302 #define DMA_CSR_DONE_SHIFT                       (7U)
32303 /*! DONE - Channel Done
32304  */
32305 #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
32306 
32307 #define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
32308 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
32309 /*! MAJORLINKCH - Major Loop Link Channel Number
32310  */
32311 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
32312 
32313 #define DMA_CSR_BWC_MASK                         (0xC000U)
32314 #define DMA_CSR_BWC_SHIFT                        (14U)
32315 /*! BWC - Bandwidth Control
32316  *  0b00..No eDMA engine stalls
32317  *  0b01..Reserved
32318  *  0b10..eDMA engine stalls for 4 cycles after each R/W
32319  *  0b11..eDMA engine stalls for 8 cycles after each R/W
32320  */
32321 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
32322 /*! @} */
32323 
32324 /* The count of DMA_CSR */
32325 #define DMA_CSR_COUNT                            (32U)
32326 
32327 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
32328 /*! @{ */
32329 
32330 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
32331 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
32332 /*! BITER - Starting Major Iteration Count
32333  */
32334 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
32335 
32336 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
32337 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
32338 /*! ELINK - Enables channel-to-channel linking on minor loop complete
32339  *  0b0..Channel-to-channel linking is disabled
32340  *  0b1..Channel-to-channel linking is enabled
32341  */
32342 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
32343 /*! @} */
32344 
32345 /* The count of DMA_BITER_ELINKNO */
32346 #define DMA_BITER_ELINKNO_COUNT                  (32U)
32347 
32348 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
32349 /*! @{ */
32350 
32351 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
32352 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
32353 /*! BITER - Starting major iteration count
32354  */
32355 #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
32356 
32357 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
32358 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
32359 /*! LINKCH - Link Channel Number
32360  */
32361 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
32362 
32363 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
32364 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
32365 /*! ELINK - Enables channel-to-channel linking on minor loop complete
32366  *  0b0..Channel-to-channel linking is disabled
32367  *  0b1..Channel-to-channel linking is enabled
32368  */
32369 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
32370 /*! @} */
32371 
32372 /* The count of DMA_BITER_ELINKYES */
32373 #define DMA_BITER_ELINKYES_COUNT                 (32U)
32374 
32375 
32376 /*!
32377  * @}
32378  */ /* end of group DMA_Register_Masks */
32379 
32380 
32381 /* DMA - Peripheral instance base addresses */
32382 /** Peripheral DMA1 base address */
32383 #define DMA1_BASE                                (0x40C14000u)
32384 /** Peripheral DMA1 base pointer */
32385 #define DMA1                                     ((DMA_Type *)DMA1_BASE)
32386 /** Array initializer of DMA peripheral base addresses */
32387 #define DMA_BASE_ADDRS                           { 0u, DMA1_BASE }
32388 /** Array initializer of DMA peripheral base pointers */
32389 #define DMA_BASE_PTRS                            { (DMA_Type *)0u, DMA1 }
32390 /** Interrupt vectors for the DMA peripheral type */
32391 #define DMA_CHN_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, \
32392                                                    { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
32393 #define DMA_ERROR_IRQS                           { NotAvail_IRQn, DMA_ERROR_IRQn }
32394 
32395 /*!
32396  * @}
32397  */ /* end of group DMA_Peripheral_Access_Layer */
32398 
32399 
32400 /* ----------------------------------------------------------------------------
32401    -- DMAMUX Peripheral Access Layer
32402    ---------------------------------------------------------------------------- */
32403 
32404 /*!
32405  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
32406  * @{
32407  */
32408 
32409 /** DMAMUX - Register Layout Typedef */
32410 typedef struct {
32411   __IO uint32_t CHCFG[32];                         /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
32412 } DMAMUX_Type;
32413 
32414 /* ----------------------------------------------------------------------------
32415    -- DMAMUX Register Masks
32416    ---------------------------------------------------------------------------- */
32417 
32418 /*!
32419  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
32420  * @{
32421  */
32422 
32423 /*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
32424 /*! @{ */
32425 
32426 #define DMAMUX_CHCFG_SOURCE_MASK                 (0xFFU)
32427 #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
32428 /*! SOURCE - DMA Channel Source (Slot Number)
32429  */
32430 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
32431 
32432 #define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
32433 #define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
32434 /*! A_ON - DMA Channel Always Enable
32435  *  0b0..DMA Channel Always ON function is disabled
32436  *  0b1..DMA Channel Always ON function is enabled
32437  */
32438 #define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
32439 
32440 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
32441 #define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
32442 /*! TRIG - DMA Channel Trigger Enable
32443  *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
32444  *       specified source to the DMA channel. (Normal mode)
32445  *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
32446  */
32447 #define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
32448 
32449 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
32450 #define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
32451 /*! ENBL - DMA Mux Channel Enable
32452  *  0b0..DMA Mux channel is disabled
32453  *  0b1..DMA Mux channel is enabled
32454  */
32455 #define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
32456 /*! @} */
32457 
32458 /* The count of DMAMUX_CHCFG */
32459 #define DMAMUX_CHCFG_COUNT                       (32U)
32460 
32461 
32462 /*!
32463  * @}
32464  */ /* end of group DMAMUX_Register_Masks */
32465 
32466 
32467 /* DMAMUX - Peripheral instance base addresses */
32468 /** Peripheral DMAMUX1 base address */
32469 #define DMAMUX1_BASE                             (0x40C18000u)
32470 /** Peripheral DMAMUX1 base pointer */
32471 #define DMAMUX1                                  ((DMAMUX_Type *)DMAMUX1_BASE)
32472 /** Array initializer of DMAMUX peripheral base addresses */
32473 #define DMAMUX_BASE_ADDRS                        { 0u, DMAMUX1_BASE }
32474 /** Array initializer of DMAMUX peripheral base pointers */
32475 #define DMAMUX_BASE_PTRS                         { (DMAMUX_Type *)0u, DMAMUX1 }
32476 
32477 /*!
32478  * @}
32479  */ /* end of group DMAMUX_Peripheral_Access_Layer */
32480 
32481 
32482 /* ----------------------------------------------------------------------------
32483    -- DSI_HOST Peripheral Access Layer
32484    ---------------------------------------------------------------------------- */
32485 
32486 /*!
32487  * @addtogroup DSI_HOST_Peripheral_Access_Layer DSI_HOST Peripheral Access Layer
32488  * @{
32489  */
32490 
32491 /** DSI_HOST - Register Layout Typedef */
32492 typedef struct {
32493   __IO uint32_t CFG_NUM_LANES;                     /**< CFG_NUM_LANES, offset: 0x0 */
32494   __IO uint32_t CFG_NONCONTINUOUS_CLK;             /**< CFG_NONCONTINUOUS_CLK, offset: 0x4 */
32495   __IO uint32_t CFG_T_PRE;                         /**< CFG_T_PRE, offset: 0x8 */
32496   __IO uint32_t CFG_T_POST;                        /**< CFG_T_POST, offset: 0xC */
32497   __IO uint32_t CFG_TX_GAP;                        /**< CFG_TX_GAP, offset: 0x10 */
32498   __IO uint32_t CFG_AUTOINSERT_EOTP;               /**< CFG_AUTOINSERT_ETOP, offset: 0x14 */
32499   __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;         /**< CFG_EXTRA_CMDS_AFTER_ETOP, offset: 0x18 */
32500   __IO uint32_t CFG_HTX_TO_COUNT;                  /**< CFG_HTX_TO_COUNT, offset: 0x1C */
32501   __IO uint32_t CFG_LRX_H_TO_COUNT;                /**< CFG_LRX_H_TO_COUNT, offset: 0x20 */
32502   __IO uint32_t CFG_BTA_H_TO_COUNT;                /**< CFG_BTA_H_TO_COUNT, offset: 0x24 */
32503   __IO uint32_t CFG_TWAKEUP;                       /**< CFG_TWAKEUP, offset: 0x28 */
32504   __I  uint32_t CFG_STATUS_OUT;                    /**< CFG_STATUS_OUT, offset: 0x2C */
32505   __I  uint32_t RX_ERROR_STATUS;                   /**< RX_ERROR_STATUS, offset: 0x30 */
32506 } DSI_HOST_Type;
32507 
32508 /* ----------------------------------------------------------------------------
32509    -- DSI_HOST Register Masks
32510    ---------------------------------------------------------------------------- */
32511 
32512 /*!
32513  * @addtogroup DSI_HOST_Register_Masks DSI_HOST Register Masks
32514  * @{
32515  */
32516 
32517 /*! @name CFG_NUM_LANES - CFG_NUM_LANES */
32518 /*! @{ */
32519 
32520 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK    (0x3U)
32521 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT   (0U)
32522 /*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data.
32523  *  0b00..1 lane
32524  *  0b01..2 lanes
32525  */
32526 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
32527 /*! @} */
32528 
32529 /*! @name CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK */
32530 /*! @{ */
32531 
32532 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
32533 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
32534 /*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous
32535  *    clock mode, the high speed clock will transition into low power mode between transmissions.
32536  *  0b0..Continuous high speed clock
32537  *  0b1..Non-Continuous high speed clock
32538  */
32539 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
32540 /*! @} */
32541 
32542 /*! @name CFG_T_PRE - CFG_T_PRE */
32543 /*! @{ */
32544 
32545 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK      (0xFFU)
32546 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT     (0U)
32547 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
32548  *    wait after enabling the clock lane for HS operation before enabling the data lanes for HS
32549  *    operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this
32550  *    port is 1.
32551  */
32552 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
32553 /*! @} */
32554 
32555 /*! @name CFG_T_POST - CFG_T_POST */
32556 /*! @{ */
32557 
32558 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK     (0xFFU)
32559 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT    (0U)
32560 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting
32561  *    the clock lane into LP mode after the data lanes have been detected to be in Stop State. This
32562  *    setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE
32563  *    requirement for the clock lane before the data lane is allowed to change from LP11 to start a high
32564  *    speed transmission. The minimum value for this port is 1.
32565  */
32566 #define DSI_HOST_CFG_T_POST_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
32567 /*! @} */
32568 
32569 /*! @name CFG_TX_GAP - CFG_TX_GAP */
32570 /*! @{ */
32571 
32572 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK     (0xFFU)
32573 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT    (0U)
32574 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
32575  *    wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode
32576  *    again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this
32577  *    port is 1.
32578  */
32579 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
32580 /*! @} */
32581 
32582 /*! @name CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP */
32583 /*! @{ */
32584 
32585 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
32586 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
32587 /*! AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
32588  *  0b0..EoTp is not automatically inserted
32589  *  0b1..EoTp is automatically inserted
32590  */
32591 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
32592 /*! @} */
32593 
32594 /*! @name CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP */
32595 /*! @{ */
32596 
32597 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
32598 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
32599 /*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after
32600  *    the end of a packet. The value is the number of extra EOTP packets sent.
32601  */
32602 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
32603 /*! @} */
32604 
32605 /*! @name CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT */
32606 /*! @{ */
32607 
32608 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK     (0xFFFFFFU)
32609 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT    (0U)
32610 /*! COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods
32611  *    that once reached will initiate a timeout error and follow the recovery procedure documented in
32612  *    the DSI specification.
32613  */
32614 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
32615 /*! @} */
32616 
32617 /*! @name CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT */
32618 /*! @{ */
32619 
32620 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
32621 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT  (0U)
32622 /*! COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that
32623  *    once reached will initiate a timeout error and follow the recovery procedure documented in
32624  *    the DSI specification.
32625  */
32626 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
32627 /*! @} */
32628 
32629 /*! @name CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT */
32630 /*! @{ */
32631 
32632 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
32633 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT  (0U)
32634 /*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods
32635  *    that once reached will initiate a timeout error.
32636  */
32637 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
32638 /*! @} */
32639 
32640 /*! @name CFG_TWAKEUP - CFG_TWAKEUP */
32641 /*! @{ */
32642 
32643 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK    (0x7FFFFU)
32644 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT   (0U)
32645 /*! NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a
32646  *    clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum
32647  *    of 1ms in Mark-1 state after leaving ULPS.
32648  */
32649 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
32650 /*! @} */
32651 
32652 /*! @name CFG_STATUS_OUT - CFG_STATUS_OUT */
32653 /*! @{ */
32654 
32655 #define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK      (0xFFFFFFFFU)
32656 #define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT     (0U)
32657 /*! STATUS - Status Register
32658  */
32659 #define DSI_HOST_CFG_STATUS_OUT_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
32660 /*! @} */
32661 
32662 /*! @name RX_ERROR_STATUS - RX_ERROR_STATUS */
32663 /*! @{ */
32664 
32665 #define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK     (0x7FFU)
32666 #define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT    (0U)
32667 /*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators
32668  */
32669 #define DSI_HOST_RX_ERROR_STATUS_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)
32670 /*! @} */
32671 
32672 
32673 /*!
32674  * @}
32675  */ /* end of group DSI_HOST_Register_Masks */
32676 
32677 
32678 /* DSI_HOST - Peripheral instance base addresses */
32679 /** Peripheral DSI_HOST base address */
32680 #define DSI_HOST_BASE                            (0x4080C000u)
32681 /** Peripheral DSI_HOST base pointer */
32682 #define DSI_HOST                                 ((DSI_HOST_Type *)DSI_HOST_BASE)
32683 /** Array initializer of DSI_HOST peripheral base addresses */
32684 #define DSI_HOST_BASE_ADDRS                      { DSI_HOST_BASE }
32685 /** Array initializer of DSI_HOST peripheral base pointers */
32686 #define DSI_HOST_BASE_PTRS                       { DSI_HOST }
32687 /** Interrupt vectors for the DSI_HOST peripheral type */
32688 #define DSI_HOST_DSI_IRQS                        { MIPI_DSI_IRQn }
32689 
32690 /*!
32691  * @}
32692  */ /* end of group DSI_HOST_Peripheral_Access_Layer */
32693 
32694 
32695 /* ----------------------------------------------------------------------------
32696    -- DSI_HOST_APB_PKT_IF Peripheral Access Layer
32697    ---------------------------------------------------------------------------- */
32698 
32699 /*!
32700  * @addtogroup DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer DSI_HOST_APB_PKT_IF Peripheral Access Layer
32701  * @{
32702  */
32703 
32704 /** DSI_HOST_APB_PKT_IF - Register Layout Typedef */
32705 typedef struct {
32706   __IO uint32_t TX_PAYLOAD;                        /**< TX_PAYLOAD, offset: 0x0 */
32707   __IO uint32_t PKT_CONTROL;                       /**< PKT_CONTROL, offset: 0x4 */
32708   __IO uint32_t SEND_PACKET;                       /**< SEND_PACKET, offset: 0x8 */
32709   __I  uint32_t PKT_STATUS;                        /**< PKT_STATUS, offset: 0xC */
32710   __I  uint32_t PKT_FIFO_WR_LEVEL;                 /**< PKT_FIFO_WR_LEVEL, offset: 0x10 */
32711   __I  uint32_t PKT_FIFO_RD_LEVEL;                 /**< PKT_FIFO_RD_LEVEL, offset: 0x14 */
32712   __I  uint32_t PKT_RX_PAYLOAD;                    /**< PKT_RX_PAYLOAD, offset: 0x18 */
32713   __I  uint32_t PKT_RX_PKT_HEADER;                 /**< PKT_RX_PKT_HEADER, offset: 0x1C */
32714   __I  uint32_t IRQ_STATUS;                        /**< IRQ_STATUS, offset: 0x20 */
32715   __I  uint32_t IRQ_STATUS2;                       /**< IRQ_STATUS2, offset: 0x24 */
32716   __IO uint32_t IRQ_MASK;                          /**< IRQ_MASK, offset: 0x28 */
32717   __IO uint32_t IRQ_MASK2;                         /**< IRQ_MASK2, offset: 0x2C */
32718 } DSI_HOST_APB_PKT_IF_Type;
32719 
32720 /* ----------------------------------------------------------------------------
32721    -- DSI_HOST_APB_PKT_IF Register Masks
32722    ---------------------------------------------------------------------------- */
32723 
32724 /*!
32725  * @addtogroup DSI_HOST_APB_PKT_IF_Register_Masks DSI_HOST_APB_PKT_IF Register Masks
32726  * @{
32727  */
32728 
32729 /*! @name TX_PAYLOAD - TX_PAYLOAD */
32730 /*! @{ */
32731 
32732 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
32733 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U)
32734 /*! PAYLOAD - Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values.
32735  */
32736 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK)
32737 /*! @} */
32738 
32739 /*! @name PKT_CONTROL - PKT_CONTROL */
32740 /*! @{ */
32741 
32742 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU)
32743 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U)
32744 /*! CTRL - Tx packet control
32745  */
32746 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK)
32747 /*! @} */
32748 
32749 /*! @name SEND_PACKET - SEND_PACKET */
32750 /*! @{ */
32751 
32752 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U)
32753 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U)
32754 /*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
32755  *  0b0..Packet not sent
32756  *  0b1..Packet is sent
32757  */
32758 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK)
32759 /*! @} */
32760 
32761 /*! @name PKT_STATUS - PKT_STATUS */
32762 /*! @{ */
32763 
32764 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU)
32765 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U)
32766 /*! STATUS - Status of APB to packet interface.
32767  */
32768 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK)
32769 /*! @} */
32770 
32771 /*! @name PKT_FIFO_WR_LEVEL - PKT_FIFO_WR_LEVEL */
32772 /*! @{ */
32773 
32774 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU)
32775 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
32776 /*! WR - Write level of APB to pkt interface FIFO
32777  */
32778 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK)
32779 /*! @} */
32780 
32781 /*! @name PKT_FIFO_RD_LEVEL - PKT_FIFO_RD_LEVEL */
32782 /*! @{ */
32783 
32784 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU)
32785 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
32786 /*! RD - Read level of APB to pkt interface FIFO
32787  */
32788 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK)
32789 /*! @} */
32790 
32791 /*! @name PKT_RX_PAYLOAD - PKT_RX_PAYLOAD */
32792 /*! @{ */
32793 
32794 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
32795 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
32796 /*! PAYLOAD - APB to pkt interface Rx payload read
32797  */
32798 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK)
32799 /*! @} */
32800 
32801 /*! @name PKT_RX_PKT_HEADER - PKT_RX_PKT_HEADER */
32802 /*! @{ */
32803 
32804 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
32805 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
32806 /*! HEADER - APB to pkt interface Rx packet header
32807  */
32808 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK)
32809 /*! @} */
32810 
32811 /*! @name IRQ_STATUS - IRQ_STATUS */
32812 /*! @{ */
32813 
32814 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU)
32815 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U)
32816 /*! STATUS - Status of APB to packet interface.
32817  */
32818 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK)
32819 /*! @} */
32820 
32821 /*! @name IRQ_STATUS2 - IRQ_STATUS2 */
32822 /*! @{ */
32823 
32824 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U)
32825 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U)
32826 /*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
32827  *    Reading dsi_host_irq_status will clear both status and status2.
32828  */
32829 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK)
32830 /*! @} */
32831 
32832 /*! @name IRQ_MASK - IRQ_MASK */
32833 /*! @{ */
32834 
32835 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK   (0xFFFFFFFFU)
32836 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT  (0U)
32837 /*! MASK - IRQ Mask
32838  */
32839 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK)
32840 /*! @} */
32841 
32842 /*! @name IRQ_MASK2 - IRQ_MASK2 */
32843 /*! @{ */
32844 
32845 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U)
32846 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U)
32847 /*! MASK2 - IRQ mask 2
32848  */
32849 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK)
32850 /*! @} */
32851 
32852 
32853 /*!
32854  * @}
32855  */ /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */
32856 
32857 
32858 /* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
32859 /** Peripheral DSI_HOST_APB_PKT_IF base address */
32860 #define DSI_HOST_APB_PKT_IF_BASE                 (0x4080C280u)
32861 /** Peripheral DSI_HOST_APB_PKT_IF base pointer */
32862 #define DSI_HOST_APB_PKT_IF                      ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
32863 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base addresses */
32864 #define DSI_HOST_APB_PKT_IF_BASE_ADDRS           { DSI_HOST_APB_PKT_IF_BASE }
32865 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base pointers */
32866 #define DSI_HOST_APB_PKT_IF_BASE_PTRS            { DSI_HOST_APB_PKT_IF }
32867 
32868 /*!
32869  * @}
32870  */ /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
32871 
32872 
32873 /* ----------------------------------------------------------------------------
32874    -- DSI_HOST_DPI_INTFC Peripheral Access Layer
32875    ---------------------------------------------------------------------------- */
32876 
32877 /*!
32878  * @addtogroup DSI_HOST_DPI_INTFC_Peripheral_Access_Layer DSI_HOST_DPI_INTFC Peripheral Access Layer
32879  * @{
32880  */
32881 
32882 /** DSI_HOST_DPI_INTFC - Register Layout Typedef */
32883 typedef struct {
32884   __IO uint32_t PIXEL_PAYLOAD_SIZE;                /**< PEXEL_PAYLOAD_SIZE, offset: 0x0 */
32885   __IO uint32_t PIXEL_FIFO_SEND_LEVEL;             /**< PIXEL_FIFO_SEND_LEVEL, offset: 0x4 */
32886   __IO uint32_t INTERFACE_COLOR_CODING;            /**< INTERFACE_COLOR_CODING, offset: 0x8 */
32887   __IO uint32_t PIXEL_FORMAT;                      /**< PIXEL_FORMAT, offset: 0xC */
32888   __IO uint32_t VSYNC_POLARITY;                    /**< VSYNC_POLARITY, offset: 0x10 */
32889   __IO uint32_t HSYNC_POLARITY;                    /**< HSYNC_POLARITY, offset: 0x14 */
32890   __IO uint32_t VIDEO_MODE;                        /**< VIDEO_MODE, offset: 0x18 */
32891   __IO uint32_t HFP;                               /**< HFP, offset: 0x1C */
32892   __IO uint32_t HBP;                               /**< HBP, offset: 0x20 */
32893   __IO uint32_t HSA;                               /**< HSA, offset: 0x24 */
32894   __IO uint32_t ENABLE_MULT_PKTS;                  /**< ENABLE_MULT_PKTS, offset: 0x28 */
32895   __IO uint32_t VBP;                               /**< VBP, offset: 0x2C */
32896   __IO uint32_t VFP;                               /**< VFP, offset: 0x30 */
32897   __IO uint32_t BLLP_MODE;                         /**< BLLP_MODE, offset: 0x34 */
32898   __IO uint32_t USE_NULL_PKT_BLLP;                 /**< USE_NULL_PKT_BLLP, offset: 0x38 */
32899   __IO uint32_t VACTIVE;                           /**< VACTIVE, offset: 0x3C */
32900 } DSI_HOST_DPI_INTFC_Type;
32901 
32902 /* ----------------------------------------------------------------------------
32903    -- DSI_HOST_DPI_INTFC Register Masks
32904    ---------------------------------------------------------------------------- */
32905 
32906 /*!
32907  * @addtogroup DSI_HOST_DPI_INTFC_Register_Masks DSI_HOST_DPI_INTFC Register Masks
32908  * @{
32909  */
32910 
32911 /*! @name PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE */
32912 /*! @{ */
32913 
32914 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
32915 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
32916 /*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be
32917  *    evenly divisible by the line size (in pixels).
32918  */
32919 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
32920 /*! @} */
32921 
32922 /*! @name PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL */
32923 /*! @{ */
32924 
32925 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
32926 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
32927 /*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of
32928  *    DPI pixels before initiating a DSI packet. This configuration port controls the level at which
32929  *    the DPI Host bridge begins sending pixels.
32930  */
32931 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
32932 /*! @} */
32933 
32934 /*! @name INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING */
32935 /*! @{ */
32936 
32937 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
32938 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
32939 /*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
32940  *  0b000..16-bit Configuration 1
32941  *  0b001..16-bit Configuration 2
32942  *  0b010..16-bit Configuration 3
32943  *  0b011..18-bit Configuration 1
32944  *  0b100..18-bit Configuration 2
32945  *  0b101..24-bit
32946  *  0b110, 0b111..Reserved
32947  */
32948 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
32949 /*! @} */
32950 
32951 /*! @name PIXEL_FORMAT - PIXEL_FORMAT */
32952 /*! @{ */
32953 
32954 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
32955 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
32956 /*! PIXEL_FORMAT - Sets the DSI packet type of the pixels
32957  *  0b00..16 bit
32958  *  0b01..18 bit
32959  *  0b10..18 bit loosely packed
32960  *  0b11..24 bit
32961  */
32962 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
32963 /*! @} */
32964 
32965 /*! @name VSYNC_POLARITY - VSYNC_POLARITY */
32966 /*! @{ */
32967 
32968 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
32969 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
32970 /*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input
32971  *  0b0..active low
32972  *  0b1..active high
32973  */
32974 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
32975 /*! @} */
32976 
32977 /*! @name HSYNC_POLARITY - HSYNC_POLARITY */
32978 /*! @{ */
32979 
32980 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
32981 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
32982 /*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input
32983  *  0b0..active low
32984  *  0b1..active high
32985  */
32986 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
32987 /*! @} */
32988 
32989 /*! @name VIDEO_MODE - VIDEO_MODE */
32990 /*! @{ */
32991 
32992 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
32993 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
32994 /*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for.
32995  *  0b00..Non-Burst mode with Sync Pulses
32996  *  0b01..Non-Burst mode with Sync Events
32997  *  0b10..Burst mode
32998  *  0b11..Reserved, not valid
32999  */
33000 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
33001 /*! @} */
33002 
33003 /*! @name HFP - HFP */
33004 /*! @{ */
33005 
33006 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
33007 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U)
33008 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
33009  */
33010 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
33011 /*! @} */
33012 
33013 /*! @name HBP - HBP */
33014 /*! @{ */
33015 
33016 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
33017 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U)
33018 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
33019  */
33020 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
33021 /*! @} */
33022 
33023 /*! @name HSA - HSA */
33024 /*! @{ */
33025 
33026 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
33027 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U)
33028 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
33029  */
33030 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
33031 /*! @} */
33032 
33033 /*! @name ENABLE_MULT_PKTS - ENABLE_MULT_PKTS */
33034 /*! @{ */
33035 
33036 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
33037 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
33038 /*! ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled,
33039  *    PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line
33040  *  0b0..Video Line is sent in a single packet
33041  *  0b1..Video Line is sent in two packets
33042  */
33043 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
33044 /*! @} */
33045 
33046 /*! @name VBP - VBP */
33047 /*! @{ */
33048 
33049 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK    (0xFFU)
33050 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
33051 /*! NUM_LINES - Sets the number of lines in the vertical back porch.
33052  */
33053 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
33054 /*! @} */
33055 
33056 /*! @name VFP - VFP */
33057 /*! @{ */
33058 
33059 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK    (0xFFU)
33060 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
33061 /*! NUM_LINES - Sets the number of lines in the vertical front porch.
33062  */
33063 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
33064 /*! @} */
33065 
33066 /*! @name BLLP_MODE - BLLP_MODE */
33067 /*! @{ */
33068 
33069 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK     (0x1U)
33070 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT    (0U)
33071 /*! LP - Optimize bllp periods to Low Power mode when possible
33072  *  0b0..Blanking packets are sent during BLLP periods
33073  *  0b1..LP mode is used for BLLP periods
33074  */
33075 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
33076 /*! @} */
33077 
33078 /*! @name USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP */
33079 /*! @{ */
33080 
33081 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
33082 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
33083 /*! NULL - Selects type of blanking packet to be sent during bllp
33084  *  0b0..Blanking packet used in bllp region 1
33085  *  0b1..Null packet used in bllp region
33086  */
33087 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
33088 /*! @} */
33089 
33090 /*! @name VACTIVE - VACTIVE */
33091 /*! @{ */
33092 
33093 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU)
33094 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U)
33095 /*! NUM_LINES - Sets the number of lines in the vertical active aread.
33096  */
33097 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
33098 /*! @} */
33099 
33100 
33101 /*!
33102  * @}
33103  */ /* end of group DSI_HOST_DPI_INTFC_Register_Masks */
33104 
33105 
33106 /* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
33107 /** Peripheral DSI_HOST_DPI_INTFC base address */
33108 #define DSI_HOST_DPI_INTFC_BASE                  (0x4080C200u)
33109 /** Peripheral DSI_HOST_DPI_INTFC base pointer */
33110 #define DSI_HOST_DPI_INTFC                       ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
33111 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base addresses */
33112 #define DSI_HOST_DPI_INTFC_BASE_ADDRS            { DSI_HOST_DPI_INTFC_BASE }
33113 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base pointers */
33114 #define DSI_HOST_DPI_INTFC_BASE_PTRS             { DSI_HOST_DPI_INTFC }
33115 
33116 /*!
33117  * @}
33118  */ /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
33119 
33120 
33121 /* ----------------------------------------------------------------------------
33122    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
33123    ---------------------------------------------------------------------------- */
33124 
33125 /*!
33126  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
33127  * @{
33128  */
33129 
33130 /** DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Register Layout Typedef */
33131 typedef struct {
33132   __IO uint32_t PD_TX;                             /**< PD_TX, offset: 0x0 */
33133   __IO uint32_t M_PRG_HS_PREPARE;                  /**< M_PRG_HS_PREPARE, offset: 0x4 */
33134   __IO uint32_t MC_PRG_HS_PREPARE;                 /**< MC_PRG_HS_PREPARE, offset: 0x8 */
33135   __IO uint32_t M_PRG_HS_ZERO;                     /**< M_PRG_HS_ZERO, offset: 0xC */
33136   __IO uint32_t MC_PRG_HS_ZERO;                    /**< MC_PRG_HS_ZERO, offset: 0x10 */
33137   __IO uint32_t M_PRG_HS_TRAIL;                    /**< M_PRG_HS_TRAIL, offset: 0x14 */
33138   __IO uint32_t MC_PRG_HS_TRAIL;                   /**< MC_PRG_HS_TRAIL, offset: 0x18 */
33139   __IO uint32_t PD_PLL;                            /**< PD_PLL, offset: 0x1C */
33140   __IO uint32_t TST;                               /**< TST, offset: 0x20 */
33141   __IO uint32_t CN;                                /**< CN, offset: 0x24 */
33142   __IO uint32_t CM;                                /**< CM, offset: 0x28 */
33143   __IO uint32_t CO;                                /**< CO, offset: 0x2C */
33144   __I  uint32_t LOCK;                              /**< LOCK, offset: 0x30 */
33145   __IO uint32_t LOCK_BYP;                          /**< LOCK_BYP, offset: 0x34 */
33146   __IO uint32_t TX_RCAL;                           /**< TX_RCAL, offset: 0x38 */
33147   __IO uint32_t AUTO_PD_EN;                        /**< AUTO_PD_EN, offset: 0x3C */
33148   __IO uint32_t RXLPRP;                            /**< RXLPRP, offset: 0x40 */
33149   __IO uint32_t RXCDRP;                            /**< RXCDRP, offset: 0x44 */
33150 } DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type;
33151 
33152 /* ----------------------------------------------------------------------------
33153    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
33154    ---------------------------------------------------------------------------- */
33155 
33156 /*!
33157  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
33158  * @{
33159  */
33160 
33161 /*! @name PD_TX - PD_TX */
33162 /*! @{ */
33163 
33164 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U)
33165 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U)
33166 /*! PD_TX - Power Down input for D-PHY
33167  *  0b1..Power Down
33168  *  0b0..Power Up
33169  */
33170 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK)
33171 /*! @} */
33172 
33173 /*! @name M_PRG_HS_PREPARE - M_PRG_HS_PREPARE */
33174 /*! @{ */
33175 
33176 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
33177 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
33178 /*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE input
33179  */
33180 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
33181 /*! @} */
33182 
33183 /*! @name MC_PRG_HS_PREPARE - MC_PRG_HS_PREPARE */
33184 /*! @{ */
33185 
33186 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
33187 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
33188 /*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input
33189  */
33190 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
33191 /*! @} */
33192 
33193 /*! @name M_PRG_HS_ZERO - M_PRG_HS_ZERO */
33194 /*! @{ */
33195 
33196 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
33197 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
33198 /*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO input
33199  */
33200 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
33201 /*! @} */
33202 
33203 /*! @name MC_PRG_HS_ZERO - MC_PRG_HS_ZERO */
33204 /*! @{ */
33205 
33206 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
33207 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
33208 /*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO input
33209  */
33210 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
33211 /*! @} */
33212 
33213 /*! @name M_PRG_HS_TRAIL - M_PRG_HS_TRAIL */
33214 /*! @{ */
33215 
33216 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
33217 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
33218 /*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL input
33219  */
33220 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
33221 /*! @} */
33222 
33223 /*! @name MC_PRG_HS_TRAIL - MC_PRG_HS_TRAIL */
33224 /*! @{ */
33225 
33226 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
33227 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
33228 /*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input
33229  */
33230 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
33231 /*! @} */
33232 
33233 /*! @name PD_PLL - PD_PLL */
33234 /*! @{ */
33235 
33236 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U)
33237 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U)
33238 /*! PD_PLL - Power-down signal
33239  *  0b1..Power down PLL
33240  *  0b0..Power up PLL
33241  */
33242 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK)
33243 /*! @} */
33244 
33245 /*! @name TST - TST */
33246 /*! @{ */
33247 
33248 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU)
33249 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U)
33250 /*! TST - Test
33251  */
33252 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK)
33253 /*! @} */
33254 
33255 /*! @name CN - CN */
33256 /*! @{ */
33257 
33258 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU)
33259 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U)
33260 /*! CN - Control N divider
33261  */
33262 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK)
33263 /*! @} */
33264 
33265 /*! @name CM - CM */
33266 /*! @{ */
33267 
33268 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU)
33269 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U)
33270 /*! CM - Control M divider
33271  */
33272 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK)
33273 /*! @} */
33274 
33275 /*! @name CO - CO */
33276 /*! @{ */
33277 
33278 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U)
33279 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U)
33280 /*! CO - Control O divider
33281  *  0b00..Divide by 1
33282  *  0b01..Divide by 2
33283  *  0b10..Divide by 4
33284  *  0b11..Divide by 8
33285  */
33286 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK)
33287 /*! @} */
33288 
33289 /*! @name LOCK - LOCK */
33290 /*! @{ */
33291 
33292 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U)
33293 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U)
33294 /*! LOCK - Lock Detect output
33295  *  0b1..PLL has achieved frequency lock
33296  *  0b0..PLL not locked
33297  */
33298 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK)
33299 /*! @} */
33300 
33301 /*! @name LOCK_BYP - LOCK_BYP */
33302 /*! @{ */
33303 
33304 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U)
33305 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U)
33306 /*! LOCK_BYP - DPHY LOCK_BYP input
33307  *  0b0..PLL LOCK signal will gate TxByteClkHS clock
33308  *  0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS
33309  */
33310 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK)
33311 /*! @} */
33312 
33313 /*! @name TX_RCAL - TX_RCAL */
33314 /*! @{ */
33315 
33316 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U)
33317 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U)
33318 /*! TX_RCAL - On-chip termination control bits for manual calibration of HS-TX
33319  *  0b00..20% higher than mid-range. Highest impedance setting
33320  *  0b01..Mid-range impedance setting (default)
33321  *  0b10..15% lower than mid-range
33322  *  0b11..25% lower than mid-range. Lowest impedance setting
33323  */
33324 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK)
33325 /*! @} */
33326 
33327 /*! @name AUTO_PD_EN - AUTO_PD_EN */
33328 /*! @{ */
33329 
33330 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
33331 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
33332 /*! AUTO_PD_EN - DPHY AUTO_PD_EN input
33333  *  0b0..Inactive lanes are powered up and driving LP11
33334  *  0b1..inactive lanes are powered down
33335  */
33336 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK)
33337 /*! @} */
33338 
33339 /*! @name RXLPRP - RXLPRP */
33340 /*! @{ */
33341 
33342 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U)
33343 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U)
33344 /*! RXLPRP - DPHY RXLPRP input
33345  */
33346 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK)
33347 /*! @} */
33348 
33349 /*! @name RXCDRP - RXCDRP */
33350 /*! @{ */
33351 
33352 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U)
33353 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U)
33354 /*! RXCDRP - DPHY RXCDRP input
33355  *  0b00..344mV
33356  *  0b01..325mV (Default)
33357  *  0b10..307mV
33358  *  0b11..Invalid
33359  */
33360 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK)
33361 /*! @} */
33362 
33363 
33364 /*!
33365  * @}
33366  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */
33367 
33368 
33369 /* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */
33370 /** Peripheral DSI_HOST_DPHY_INTFC base address */
33371 #define DSI_HOST_DPHY_INTFC_BASE                 (0x4080C300u)
33372 /** Peripheral DSI_HOST_DPHY_INTFC base pointer */
33373 #define DSI_HOST_DPHY_INTFC                      ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
33374 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
33375  * addresses */
33376 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE }
33377 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
33378  * pointers */
33379 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC }
33380 
33381 /*!
33382  * @}
33383  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */
33384 
33385 
33386 /* ----------------------------------------------------------------------------
33387    -- EMVSIM Peripheral Access Layer
33388    ---------------------------------------------------------------------------- */
33389 
33390 /*!
33391  * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
33392  * @{
33393  */
33394 
33395 /** EMVSIM - Register Layout Typedef */
33396 typedef struct {
33397   __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
33398   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
33399   __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
33400   __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
33401   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
33402   __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
33403   __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
33404   __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
33405   __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
33406   __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
33407   __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
33408   __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
33409   __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
33410   __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
33411   __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
33412   __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
33413   __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
33414   __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
33415   __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
33416 } EMVSIM_Type;
33417 
33418 /* ----------------------------------------------------------------------------
33419    -- EMVSIM Register Masks
33420    ---------------------------------------------------------------------------- */
33421 
33422 /*!
33423  * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
33424  * @{
33425  */
33426 
33427 /*! @name VER_ID - Version ID Register */
33428 /*! @{ */
33429 
33430 #define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
33431 #define EMVSIM_VER_ID_VER_SHIFT                  (0U)
33432 /*! VER - Version ID of the module
33433  */
33434 #define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
33435 /*! @} */
33436 
33437 /*! @name PARAM - Parameter Register */
33438 /*! @{ */
33439 
33440 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
33441 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
33442 /*! RX_FIFO_DEPTH - Receive FIFO Depth
33443  */
33444 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
33445 
33446 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
33447 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
33448 /*! TX_FIFO_DEPTH - Transmit FIFO Depth
33449  */
33450 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
33451 /*! @} */
33452 
33453 /*! @name CLKCFG - Clock Configuration Register */
33454 /*! @{ */
33455 
33456 #define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
33457 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
33458 /*! CLK_PRSC - Clock Prescaler Value
33459  */
33460 #define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
33461 
33462 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
33463 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
33464 /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
33465  *  0b00..Disabled / Reset
33466  *  0b01..Card Clock
33467  *  0b10..Receive Clock
33468  *  0b11..ETU Clock (transmit clock)
33469  */
33470 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
33471 
33472 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
33473 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
33474 /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
33475  *  0b00..Disabled / Reset
33476  *  0b01..Card Clock
33477  *  0b10..Receive Clock
33478  *  0b11..ETU Clock (transmit clock)
33479  */
33480 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
33481 /*! @} */
33482 
33483 /*! @name DIVISOR - Baud Rate Divisor Register */
33484 /*! @{ */
33485 
33486 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
33487 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
33488 /*! DIVISOR_VALUE - Divisor (F/D) Value
33489  *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
33490  *  0b000000101-0b011111111..Divisor value F/D
33491  */
33492 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
33493 /*! @} */
33494 
33495 /*! @name CTRL - Control Register */
33496 /*! @{ */
33497 
33498 #define EMVSIM_CTRL_IC_MASK                      (0x1U)
33499 #define EMVSIM_CTRL_IC_SHIFT                     (0U)
33500 /*! IC - Inverse Convention
33501  *  0b0..Direction convention transfers enabled
33502  *  0b1..Inverse convention transfers enabled
33503  */
33504 #define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
33505 
33506 #define EMVSIM_CTRL_ICM_MASK                     (0x2U)
33507 #define EMVSIM_CTRL_ICM_SHIFT                    (1U)
33508 /*! ICM - Initial Character Mode
33509  *  0b0..Initial Character Mode disabled
33510  *  0b1..Initial Character Mode enabled
33511  */
33512 #define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
33513 
33514 #define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
33515 #define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
33516 /*! ANACK - Auto NACK Enable
33517  *  0b0..NACK generation on errors disabled
33518  *  0b1..NACK generation on errors enabled
33519  */
33520 #define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
33521 
33522 #define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
33523 #define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
33524 /*! ONACK - Overrun NACK Enable
33525  *  0b0..NACK generation on overrun is disabled
33526  *  0b1..NACK generation on overrun is enabled
33527  */
33528 #define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
33529 
33530 #define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
33531 #define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
33532 /*! FLSH_RX - Flush Receiver Bit
33533  *  0b0..EMVSIM Receiver normal operation
33534  *  0b1..EMVSIM Receiver held in Reset
33535  */
33536 #define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
33537 
33538 #define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
33539 #define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
33540 /*! FLSH_TX - Flush Transmitter Bit
33541  *  0b0..EMVSIM Transmitter normal operation
33542  *  0b1..EMVSIM Transmitter held in Reset
33543  */
33544 #define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
33545 
33546 #define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
33547 #define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
33548 /*! SW_RST - Software Reset Bit
33549  *  0b0..EMVSIM Normal operation
33550  *  0b1..EMVSIM held in Reset
33551  */
33552 #define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
33553 
33554 #define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
33555 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
33556 /*! KILL_CLOCKS - Kill all internal clocks
33557  *  0b0..EMVSIM input clock enabled
33558  *  0b1..EMVSIM input clock is disabled
33559  */
33560 #define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
33561 
33562 #define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
33563 #define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
33564 /*! DOZE_EN - Doze Enable
33565  *  0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty
33566  *  0b1..DOZE instruction has no effect on EMVSIM module
33567  */
33568 #define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
33569 
33570 #define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
33571 #define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
33572 /*! STOP_EN - STOP Enable
33573  *  0b0..STOP instruction shuts down all EMVSIM clocks
33574  *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
33575  */
33576 #define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
33577 
33578 #define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
33579 #define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
33580 /*! RCV_EN - Receiver Enable
33581  *  0b0..EMVSIM Receiver disabled
33582  *  0b1..EMVSIM Receiver enabled
33583  */
33584 #define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
33585 
33586 #define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
33587 #define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
33588 /*! XMT_EN - Transmitter Enable
33589  *  0b0..EMVSIM Transmitter disabled
33590  *  0b1..EMVSIM Transmitter enabled
33591  */
33592 #define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
33593 
33594 #define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
33595 #define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
33596 /*! RCVR_11 - Receiver 11 ETU Mode Enable
33597  *  0b0..Receiver configured for 12 ETU operation mode
33598  *  0b1..Receiver configured for 11 ETU operation mode
33599  */
33600 #define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
33601 
33602 #define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
33603 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
33604 /*! RX_DMA_EN - Receive DMA Enable
33605  *  0b0..No DMA Read Request asserted for Receiver
33606  *  0b1..DMA Read Request asserted for Receiver
33607  */
33608 #define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
33609 
33610 #define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
33611 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
33612 /*! TX_DMA_EN - Transmit DMA Enable
33613  *  0b0..No DMA Write Request asserted for Transmitter
33614  *  0b1..DMA Write Request asserted for Transmitter
33615  */
33616 #define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
33617 
33618 #define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
33619 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
33620 /*! INV_CRC_VAL - Invert bits in the CRC Output Value
33621  *  0b0..Bits in CRC Output value are not inverted.
33622  *  0b1..Bits in CRC Output value are inverted.
33623  */
33624 #define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
33625 
33626 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
33627 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
33628 /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
33629  *  0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0
33630  *  0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}
33631  */
33632 #define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
33633 
33634 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
33635 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
33636 /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
33637  *  0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation
33638  *  0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation
33639  */
33640 #define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
33641 
33642 #define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
33643 #define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
33644 /*! CWT_EN - Character Wait Time Counter Enable
33645  *  0b0..Character Wait time Counter is disabled
33646  *  0b1..Character Wait time counter is enabled
33647  */
33648 #define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
33649 
33650 #define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
33651 #define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
33652 /*! LRC_EN - LRC Enable
33653  *  0b0..8-bit Linear Redundancy Checking disabled
33654  *  0b1..8-bit Linear Redundancy Checking enabled
33655  */
33656 #define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
33657 
33658 #define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
33659 #define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
33660 /*! CRC_EN - CRC Enable
33661  *  0b0..16-bit Cyclic Redundancy Checking disabled
33662  *  0b1..16-bit Cyclic Redundancy Checking enabled
33663  */
33664 #define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
33665 
33666 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
33667 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
33668 /*! XMT_CRC_LRC - Transmit CRC or LRC Enable
33669  *  0b0..No CRC or LRC value is transmitted
33670  *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
33671  */
33672 #define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
33673 
33674 #define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
33675 #define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
33676 /*! BWT_EN - Block Wait Time Counter Enable
33677  *  0b0..Disable BWT, BGT Counters
33678  *  0b1..Enable BWT, BGT Counters
33679  */
33680 #define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
33681 /*! @} */
33682 
33683 /*! @name INT_MASK - Interrupt Mask Register */
33684 /*! @{ */
33685 
33686 #define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
33687 #define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
33688 /*! RDT_IM - Receive Data Threshold Interrupt Mask
33689  *  0b0..RDTF interrupt enabled
33690  *  0b1..RDTF interrupt masked
33691  */
33692 #define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
33693 
33694 #define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
33695 #define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
33696 /*! TC_IM - Transmit Complete Interrupt Mask
33697  *  0b0..TCF interrupt enabled
33698  *  0b1..TCF interrupt masked
33699  */
33700 #define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
33701 
33702 #define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
33703 #define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
33704 /*! RFO_IM - Receive FIFO Overflow Interrupt Mask
33705  *  0b0..RFO interrupt enabled
33706  *  0b1..RFO interrupt masked
33707  */
33708 #define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
33709 
33710 #define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
33711 #define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
33712 /*! ETC_IM - Early Transmit Complete Interrupt Mask
33713  *  0b0..ETC interrupt enabled
33714  *  0b1..ETC interrupt masked
33715  */
33716 #define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
33717 
33718 #define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
33719 #define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
33720 /*! TFE_IM - Transmit FIFO Empty Interrupt Mask
33721  *  0b0..TFE interrupt enabled
33722  *  0b1..TFE interrupt masked
33723  */
33724 #define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
33725 
33726 #define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
33727 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
33728 /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
33729  *  0b0..TNTE interrupt enabled
33730  *  0b1..TNTE interrupt masked
33731  */
33732 #define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
33733 
33734 #define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
33735 #define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
33736 /*! TFF_IM - Transmit FIFO Full Interrupt Mask
33737  *  0b0..TFF interrupt enabled
33738  *  0b1..TFF interrupt masked
33739  */
33740 #define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
33741 
33742 #define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
33743 #define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
33744 /*! TDT_IM - Transmit Data Threshold Interrupt Mask
33745  *  0b0..TDTF interrupt enabled
33746  *  0b1..TDTF interrupt masked
33747  */
33748 #define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
33749 
33750 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
33751 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
33752 /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
33753  *  0b0..GPCNT0_TO interrupt enabled
33754  *  0b1..GPCNT0_TO interrupt masked
33755  */
33756 #define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
33757 
33758 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
33759 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
33760 /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
33761  *  0b0..CWT_ERR interrupt enabled
33762  *  0b1..CWT_ERR interrupt masked
33763  */
33764 #define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
33765 
33766 #define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
33767 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
33768 /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
33769  *  0b0..RTE interrupt enabled
33770  *  0b1..RTE interrupt masked
33771  */
33772 #define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
33773 
33774 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
33775 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
33776 /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
33777  *  0b0..BWT_ERR interrupt enabled
33778  *  0b1..BWT_ERR interrupt masked
33779  */
33780 #define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
33781 
33782 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
33783 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
33784 /*! BGT_ERR_IM - Block Guard Time Error Interrupt
33785  *  0b0..BGT_ERR interrupt enabled
33786  *  0b1..BGT_ERR interrupt masked
33787  */
33788 #define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
33789 
33790 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
33791 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
33792 /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
33793  *  0b0..GPCNT1_TO interrupt enabled
33794  *  0b1..GPCNT1_TO interrupt masked
33795  */
33796 #define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
33797 
33798 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
33799 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
33800 /*! RX_DATA_IM - Receive Data Interrupt Mask
33801  *  0b0..RX_DATA interrupt enabled
33802  *  0b1..RX_DATA interrupt masked
33803  */
33804 #define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
33805 
33806 #define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
33807 #define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
33808 /*! PEF_IM - Parity Error Interrupt Mask
33809  *  0b0..PEF interrupt enabled
33810  *  0b1..PEF interrupt masked
33811  */
33812 #define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
33813 /*! @} */
33814 
33815 /*! @name RX_THD - Receiver Threshold Register */
33816 /*! @{ */
33817 
33818 #define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
33819 #define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
33820 /*! RDT - Receiver Data Threshold Value
33821  */
33822 #define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
33823 
33824 #define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
33825 #define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
33826 /*! RNCK_THD - Receiver NACK Threshold Value
33827  */
33828 #define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
33829 /*! @} */
33830 
33831 /*! @name TX_THD - Transmitter Threshold Register */
33832 /*! @{ */
33833 
33834 #define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
33835 #define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
33836 /*! TDT - Transmitter Data Threshold Value
33837  */
33838 #define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
33839 
33840 #define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
33841 #define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
33842 /*! TNCK_THD - Transmitter NACK Threshold Value
33843  */
33844 #define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
33845 /*! @} */
33846 
33847 /*! @name RX_STATUS - Receive Status Register */
33848 /*! @{ */
33849 
33850 #define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
33851 #define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
33852 /*! RFO - Receive FIFO Overflow Flag
33853  *  0b0..No overrun error has occurred
33854  *  0b1..A byte was received when the received FIFO was already full
33855  */
33856 #define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
33857 
33858 #define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
33859 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
33860 /*! RX_DATA - Receive Data Interrupt Flag
33861  *  0b0..No new byte is received
33862  *  0b1..New byte is received ans stored in Receive FIFO
33863  */
33864 #define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
33865 
33866 #define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
33867 #define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
33868 /*! RDTF - Receive Data Threshold Interrupt Flag
33869  *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT
33870  *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.
33871  */
33872 #define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
33873 
33874 #define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
33875 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
33876 /*! LRC_OK - LRC Check OK Flag
33877  *  0b0..Current LRC value does not match remainder.
33878  *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
33879  */
33880 #define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
33881 
33882 #define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
33883 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
33884 /*! CRC_OK - CRC Check OK Flag
33885  *  0b0..Current CRC value does not match remainder.
33886  *  0b1..Current calculated CRC value matches the expected result.
33887  */
33888 #define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
33889 
33890 #define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
33891 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
33892 /*! CWT_ERR - Character Wait Time Error Flag
33893  *  0b0..No CWT violation has occurred
33894  *  0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.
33895  */
33896 #define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
33897 
33898 #define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
33899 #define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
33900 /*! RTE - Received NACK Threshold Error Flag
33901  *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD
33902  *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD
33903  */
33904 #define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
33905 
33906 #define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
33907 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
33908 /*! BWT_ERR - Block Wait Time Error Flag
33909  *  0b0..Block wait time not exceeded
33910  *  0b1..Block wait time was exceeded
33911  */
33912 #define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
33913 
33914 #define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
33915 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
33916 /*! BGT_ERR - Block Guard Time Error Flag
33917  *  0b0..Block guard time was sufficient
33918  *  0b1..Block guard time was too small
33919  */
33920 #define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
33921 
33922 #define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
33923 #define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
33924 /*! PEF - Parity Error Flag
33925  *  0b0..No parity error detected
33926  *  0b1..Parity error detected
33927  */
33928 #define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
33929 
33930 #define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
33931 #define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
33932 /*! FEF - Frame Error Flag
33933  *  0b0..No frame error detected
33934  *  0b1..Frame error detected
33935  */
33936 #define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
33937 
33938 #define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
33939 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
33940 /*! RX_WPTR - Receive FIFO Write Pointer Value
33941  */
33942 #define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
33943 
33944 #define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
33945 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
33946 /*! RX_CNT - Receive FIFO Byte Count
33947  *  0b0000..FIFO is emtpy
33948  */
33949 #define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
33950 /*! @} */
33951 
33952 /*! @name TX_STATUS - Transmitter Status Register */
33953 /*! @{ */
33954 
33955 #define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
33956 #define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
33957 /*! TNTE - Transmit NACK Threshold Error Flag
33958  *  0b0..Transmit NACK threshold has not been reached
33959  *  0b1..Transmit NACK threshold reached; transmitter frozen
33960  */
33961 #define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
33962 
33963 #define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
33964 #define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
33965 /*! TFE - Transmit FIFO Empty Flag
33966  *  0b0..Transmit FIFO is not empty
33967  *  0b1..Transmit FIFO is empty
33968  */
33969 #define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
33970 
33971 #define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
33972 #define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
33973 /*! ETCF - Early Transmit Complete Flag
33974  *  0b0..Transmit pending or in progress
33975  *  0b1..Transmit complete
33976  */
33977 #define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
33978 
33979 #define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
33980 #define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
33981 /*! TCF - Transmit Complete Flag
33982  *  0b0..Transmit pending or in progress
33983  *  0b1..Transmit complete
33984  */
33985 #define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
33986 
33987 #define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
33988 #define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
33989 /*! TFF - Transmit FIFO Full Flag
33990  *  0b0..Transmit FIFO Full condition has not occurred
33991  *  0b1..A Transmit FIFO Full condition has occurred
33992  */
33993 #define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
33994 
33995 #define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
33996 #define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
33997 /*! TDTF - Transmit Data Threshold Flag
33998  *  0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared
33999  *  0b1..Number of bytes in FIFO is less than or equal to TDT
34000  */
34001 #define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
34002 
34003 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
34004 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
34005 /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
34006  *  0b0..GPCNT0 time not reached, or bit has been cleared.
34007  *  0b1..General Purpose counter has reached the GPCNT0 value
34008  */
34009 #define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
34010 
34011 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
34012 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
34013 /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
34014  *  0b0..GPCNT1 time not reached, or bit has been cleared.
34015  *  0b1..General Purpose counter has reached the GPCNT1 value
34016  */
34017 #define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
34018 
34019 #define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
34020 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
34021 /*! TX_RPTR - Transmit FIFO Read Pointer
34022  */
34023 #define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
34024 
34025 #define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
34026 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
34027 /*! TX_CNT - Transmit FIFO Byte Count
34028  *  0b0000..FIFO is emtpy
34029  */
34030 #define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
34031 /*! @} */
34032 
34033 /*! @name PCSR - Port Control and Status Register */
34034 /*! @{ */
34035 
34036 #define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
34037 #define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
34038 /*! SAPD - Auto Power Down Enable
34039  *  0b0..Auto power down disabled
34040  *  0b1..Auto power down enabled
34041  */
34042 #define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
34043 
34044 #define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
34045 #define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
34046 /*! SVCC_EN - Vcc Enable for Smart Card
34047  *  0b0..Smart Card Voltage disabled
34048  *  0b1..Smart Card Voltage enabled
34049  */
34050 #define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
34051 
34052 #define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
34053 #define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
34054 /*! VCCENP - VCC Enable Polarity Control
34055  *  0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged.
34056  *  0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.
34057  */
34058 #define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
34059 
34060 #define EMVSIM_PCSR_SRST_MASK                    (0x8U)
34061 #define EMVSIM_PCSR_SRST_SHIFT                   (3U)
34062 /*! SRST - Reset to Smart Card
34063  *  0b0..Smart Card Reset is asserted
34064  *  0b1..Smart Card Reset is de-asserted
34065  */
34066 #define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
34067 
34068 #define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
34069 #define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
34070 /*! SCEN - Clock Enable for Smart Card
34071  *  0b0..Smart Card Clock Disabled
34072  *  0b1..Smart Card Clock Enabled
34073  */
34074 #define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
34075 
34076 #define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
34077 #define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
34078 /*! SCSP - Smart Card Clock Stop Polarity
34079  *  0b0..Clock is logic 0 when stopped by SCEN
34080  *  0b1..Clock is logic 1 when stopped by SCEN
34081  */
34082 #define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
34083 
34084 #define EMVSIM_PCSR_SPD_MASK                     (0x80U)
34085 #define EMVSIM_PCSR_SPD_SHIFT                    (7U)
34086 /*! SPD - Auto Power Down Control
34087  *  0b0..No effect
34088  *  0b1..Start Auto Powerdown or Power Down is in progress
34089  */
34090 #define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
34091 
34092 #define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
34093 #define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
34094 /*! SPDIM - Smart Card Presence Detect Interrupt Mask
34095  *  0b0..SIM presence detect interrupt is enabled
34096  *  0b1..SIM presence detect interrupt is masked
34097  */
34098 #define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
34099 
34100 #define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
34101 #define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
34102 /*! SPDIF - Smart Card Presence Detect Interrupt Flag
34103  *  0b0..No insertion or removal of Smart Card detected on Port
34104  *  0b1..Insertion or removal of Smart Card detected on Port
34105  */
34106 #define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
34107 
34108 #define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
34109 #define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
34110 /*! SPDP - Smart Card Presence Detect Pin Status
34111  *  0b0..SIM Presence Detect pin is logic low
34112  *  0b1..SIM Presence Detectpin is logic high
34113  */
34114 #define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
34115 
34116 #define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
34117 #define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
34118 /*! SPDES - SIM Presence Detect Edge Select
34119  *  0b0..Falling edge on the pin
34120  *  0b1..Rising edge on the pin
34121  */
34122 #define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
34123 /*! @} */
34124 
34125 /*! @name RX_BUF - Receive Data Read Buffer */
34126 /*! @{ */
34127 
34128 #define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
34129 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
34130 /*! RX_BYTE - Receive Data Byte Read
34131  */
34132 #define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
34133 /*! @} */
34134 
34135 /*! @name TX_BUF - Transmit Data Buffer */
34136 /*! @{ */
34137 
34138 #define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
34139 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
34140 /*! TX_BYTE - Transmit Data Byte
34141  */
34142 #define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
34143 /*! @} */
34144 
34145 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
34146 /*! @{ */
34147 
34148 #define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
34149 #define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
34150 /*! GETU - Transmitter Guard Time Value in ETU
34151  */
34152 #define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
34153 /*! @} */
34154 
34155 /*! @name CWT_VAL - Character Wait Time Value Register */
34156 /*! @{ */
34157 
34158 #define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
34159 #define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
34160 /*! CWT - Character Wait Time Value
34161  */
34162 #define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
34163 /*! @} */
34164 
34165 /*! @name BWT_VAL - Block Wait Time Value Register */
34166 /*! @{ */
34167 
34168 #define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
34169 #define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
34170 /*! BWT - Block Wait Time Value
34171  */
34172 #define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
34173 /*! @} */
34174 
34175 /*! @name BGT_VAL - Block Guard Time Value Register */
34176 /*! @{ */
34177 
34178 #define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
34179 #define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
34180 /*! BGT - Block Guard Time Value
34181  */
34182 #define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
34183 /*! @} */
34184 
34185 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
34186 /*! @{ */
34187 
34188 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
34189 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
34190 /*! GPCNT0 - General Purpose Counter 0 Timeout Value
34191  */
34192 #define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
34193 /*! @} */
34194 
34195 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
34196 /*! @{ */
34197 
34198 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
34199 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
34200 /*! GPCNT1 - General Purpose Counter 1 Timeout Value
34201  */
34202 #define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
34203 /*! @} */
34204 
34205 
34206 /*!
34207  * @}
34208  */ /* end of group EMVSIM_Register_Masks */
34209 
34210 
34211 /* EMVSIM - Peripheral instance base addresses */
34212 /** Peripheral EMVSIM1 base address */
34213 #define EMVSIM1_BASE                             (0x40154000u)
34214 /** Peripheral EMVSIM1 base pointer */
34215 #define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
34216 /** Peripheral EMVSIM2 base address */
34217 #define EMVSIM2_BASE                             (0x40158000u)
34218 /** Peripheral EMVSIM2 base pointer */
34219 #define EMVSIM2                                  ((EMVSIM_Type *)EMVSIM2_BASE)
34220 /** Array initializer of EMVSIM peripheral base addresses */
34221 #define EMVSIM_BASE_ADDRS                        { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
34222 /** Array initializer of EMVSIM peripheral base pointers */
34223 #define EMVSIM_BASE_PTRS                         { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
34224 /** Interrupt vectors for the EMVSIM peripheral type */
34225 #define EMVSIM_IRQS                              { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
34226 
34227 /*!
34228  * @}
34229  */ /* end of group EMVSIM_Peripheral_Access_Layer */
34230 
34231 
34232 /* ----------------------------------------------------------------------------
34233    -- ENC Peripheral Access Layer
34234    ---------------------------------------------------------------------------- */
34235 
34236 /*!
34237  * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
34238  * @{
34239  */
34240 
34241 /** ENC - Register Layout Typedef */
34242 typedef struct {
34243   __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
34244   __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x2 */
34245   __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x4 */
34246   __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x6 */
34247   __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x8 */
34248   __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0xA */
34249   __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0xC */
34250   __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xE */
34251   __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0x10 */
34252   __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x12 */
34253   __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x14 */
34254   __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x16 */
34255   __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x18 */
34256   __I  uint16_t IMR;                               /**< Input Monitor Register, offset: 0x1A */
34257   __IO uint16_t TST;                               /**< Test Register, offset: 0x1C */
34258   __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x1E */
34259   __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x20 */
34260   __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x22 */
34261   __IO uint16_t UCOMP;                             /**< Upper Position Compare Register, offset: 0x24 */
34262   __IO uint16_t LCOMP;                             /**< Lower Position Compare Register, offset: 0x26 */
34263   __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x28 */
34264   __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x2A */
34265   __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x2C */
34266   __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0x2E */
34267   __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x30 */
34268   __IO uint16_t CTRL3;                             /**< Control 3 Register, offset: 0x32 */
34269 } ENC_Type;
34270 
34271 /* ----------------------------------------------------------------------------
34272    -- ENC Register Masks
34273    ---------------------------------------------------------------------------- */
34274 
34275 /*!
34276  * @addtogroup ENC_Register_Masks ENC Register Masks
34277  * @{
34278  */
34279 
34280 /*! @name CTRL - Control Register */
34281 /*! @{ */
34282 
34283 #define ENC_CTRL_CMPIE_MASK                      (0x1U)
34284 #define ENC_CTRL_CMPIE_SHIFT                     (0U)
34285 /*! CMPIE - Compare Interrupt Enable
34286  *  0b0..Disabled
34287  *  0b1..Enabled
34288  */
34289 #define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
34290 
34291 #define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
34292 #define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
34293 /*! CMPIRQ - Compare Interrupt Request
34294  *  0b0..No match has occurred (the counter does not match the COMP value)
34295  *  0b1..COMP match has occurred (the counter matches the COMP value)
34296  */
34297 #define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
34298 
34299 #define ENC_CTRL_WDE_MASK                        (0x4U)
34300 #define ENC_CTRL_WDE_SHIFT                       (2U)
34301 /*! WDE - Watchdog Enable
34302  *  0b0..Disabled
34303  *  0b1..Enabled
34304  */
34305 #define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
34306 
34307 #define ENC_CTRL_DIE_MASK                        (0x8U)
34308 #define ENC_CTRL_DIE_SHIFT                       (3U)
34309 /*! DIE - Watchdog Timeout Interrupt Enable
34310  *  0b0..Disabled
34311  *  0b1..Enabled
34312  */
34313 #define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
34314 
34315 #define ENC_CTRL_DIRQ_MASK                       (0x10U)
34316 #define ENC_CTRL_DIRQ_SHIFT                      (4U)
34317 /*! DIRQ - Watchdog Timeout Interrupt Request
34318  *  0b0..No Watchdog timeout interrupt has occurred
34319  *  0b1..Watchdog timeout interrupt has occurred
34320  */
34321 #define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
34322 
34323 #define ENC_CTRL_XNE_MASK                        (0x20U)
34324 #define ENC_CTRL_XNE_SHIFT                       (5U)
34325 /*! XNE - Use Negative Edge of INDEX Pulse
34326  *  0b0..Use positive edge of INDEX pulse
34327  *  0b1..Use negative edge of INDEX pulse
34328  */
34329 #define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
34330 
34331 #define ENC_CTRL_XIP_MASK                        (0x40U)
34332 #define ENC_CTRL_XIP_SHIFT                       (6U)
34333 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
34334  *  0b0..INDEX pulse does not initialize the position counter
34335  *  0b1..INDEX pulse initializes the position counter
34336  */
34337 #define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
34338 
34339 #define ENC_CTRL_XIE_MASK                        (0x80U)
34340 #define ENC_CTRL_XIE_SHIFT                       (7U)
34341 /*! XIE - INDEX Pulse Interrupt Enable
34342  *  0b0..Disabled
34343  *  0b1..Enabled
34344  */
34345 #define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
34346 
34347 #define ENC_CTRL_XIRQ_MASK                       (0x100U)
34348 #define ENC_CTRL_XIRQ_SHIFT                      (8U)
34349 /*! XIRQ - INDEX Pulse Interrupt Request
34350  *  0b0..INDEX pulse has not occurred
34351  *  0b1..INDEX pulse has occurred
34352  */
34353 #define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
34354 
34355 #define ENC_CTRL_PH1_MASK                        (0x200U)
34356 #define ENC_CTRL_PH1_SHIFT                       (9U)
34357 /*! PH1 - Enable Signal Phase Count Mode
34358  *  0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
34359  *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
34360  *       PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
34361  *       CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
34362  *       PHASEB = 0, then count down
34363  */
34364 #define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
34365 
34366 #define ENC_CTRL_REV_MASK                        (0x400U)
34367 #define ENC_CTRL_REV_SHIFT                       (10U)
34368 /*! REV - Enable Reverse Direction Counting
34369  *  0b0..Count normally
34370  *  0b1..Count in the reverse direction
34371  */
34372 #define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
34373 
34374 #define ENC_CTRL_SWIP_MASK                       (0x800U)
34375 #define ENC_CTRL_SWIP_SHIFT                      (11U)
34376 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
34377  *  0b0..No action
34378  *  0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
34379  */
34380 #define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
34381 
34382 #define ENC_CTRL_HNE_MASK                        (0x1000U)
34383 #define ENC_CTRL_HNE_SHIFT                       (12U)
34384 /*! HNE - Use Negative Edge of HOME Input
34385  *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
34386  *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
34387  */
34388 #define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
34389 
34390 #define ENC_CTRL_HIP_MASK                        (0x2000U)
34391 #define ENC_CTRL_HIP_SHIFT                       (13U)
34392 /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
34393  *  0b0..No action
34394  *  0b1..HOME signal initializes the position counter
34395  */
34396 #define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
34397 
34398 #define ENC_CTRL_HIE_MASK                        (0x4000U)
34399 #define ENC_CTRL_HIE_SHIFT                       (14U)
34400 /*! HIE - HOME Interrupt Enable
34401  *  0b0..Disabled
34402  *  0b1..Enabled
34403  */
34404 #define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
34405 
34406 #define ENC_CTRL_HIRQ_MASK                       (0x8000U)
34407 #define ENC_CTRL_HIRQ_SHIFT                      (15U)
34408 /*! HIRQ - HOME Signal Transition Interrupt Request
34409  *  0b0..No transition on the HOME signal has occurred
34410  *  0b1..A transition on the HOME signal has occurred
34411  */
34412 #define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
34413 /*! @} */
34414 
34415 /*! @name FILT - Input Filter Register */
34416 /*! @{ */
34417 
34418 #define ENC_FILT_FILT_PER_MASK                   (0xFFU)
34419 #define ENC_FILT_FILT_PER_SHIFT                  (0U)
34420 /*! FILT_PER - Input Filter Sample Period
34421  */
34422 #define ENC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
34423 
34424 #define ENC_FILT_FILT_CNT_MASK                   (0x700U)
34425 #define ENC_FILT_FILT_CNT_SHIFT                  (8U)
34426 /*! FILT_CNT - Input Filter Sample Count
34427  */
34428 #define ENC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
34429 
34430 #define ENC_FILT_FILT_PRSC_MASK                  (0xE000U)
34431 #define ENC_FILT_FILT_PRSC_SHIFT                 (13U)
34432 /*! FILT_PRSC - prescaler divide IPbus clock to FILT clk
34433  */
34434 #define ENC_FILT_FILT_PRSC(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)
34435 /*! @} */
34436 
34437 /*! @name WTR - Watchdog Timeout Register */
34438 /*! @{ */
34439 
34440 #define ENC_WTR_WDOG_MASK                        (0xFFFFU)
34441 #define ENC_WTR_WDOG_SHIFT                       (0U)
34442 /*! WDOG - WDOG
34443  */
34444 #define ENC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
34445 /*! @} */
34446 
34447 /*! @name POSD - Position Difference Counter Register */
34448 /*! @{ */
34449 
34450 #define ENC_POSD_POSD_MASK                       (0xFFFFU)
34451 #define ENC_POSD_POSD_SHIFT                      (0U)
34452 /*! POSD - POSD
34453  */
34454 #define ENC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
34455 /*! @} */
34456 
34457 /*! @name POSDH - Position Difference Hold Register */
34458 /*! @{ */
34459 
34460 #define ENC_POSDH_POSDH_MASK                     (0xFFFFU)
34461 #define ENC_POSDH_POSDH_SHIFT                    (0U)
34462 /*! POSDH - POSDH
34463  */
34464 #define ENC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
34465 /*! @} */
34466 
34467 /*! @name REV - Revolution Counter Register */
34468 /*! @{ */
34469 
34470 #define ENC_REV_REV_MASK                         (0xFFFFU)
34471 #define ENC_REV_REV_SHIFT                        (0U)
34472 /*! REV - REV
34473  */
34474 #define ENC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
34475 /*! @} */
34476 
34477 /*! @name REVH - Revolution Hold Register */
34478 /*! @{ */
34479 
34480 #define ENC_REVH_REVH_MASK                       (0xFFFFU)
34481 #define ENC_REVH_REVH_SHIFT                      (0U)
34482 /*! REVH - REVH
34483  */
34484 #define ENC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
34485 /*! @} */
34486 
34487 /*! @name UPOS - Upper Position Counter Register */
34488 /*! @{ */
34489 
34490 #define ENC_UPOS_POS_MASK                        (0xFFFFU)
34491 #define ENC_UPOS_POS_SHIFT                       (0U)
34492 /*! POS - POS
34493  */
34494 #define ENC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
34495 /*! @} */
34496 
34497 /*! @name LPOS - Lower Position Counter Register */
34498 /*! @{ */
34499 
34500 #define ENC_LPOS_POS_MASK                        (0xFFFFU)
34501 #define ENC_LPOS_POS_SHIFT                       (0U)
34502 /*! POS - POS
34503  */
34504 #define ENC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
34505 /*! @} */
34506 
34507 /*! @name UPOSH - Upper Position Hold Register */
34508 /*! @{ */
34509 
34510 #define ENC_UPOSH_POSH_MASK                      (0xFFFFU)
34511 #define ENC_UPOSH_POSH_SHIFT                     (0U)
34512 /*! POSH - POSH
34513  */
34514 #define ENC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
34515 /*! @} */
34516 
34517 /*! @name LPOSH - Lower Position Hold Register */
34518 /*! @{ */
34519 
34520 #define ENC_LPOSH_POSH_MASK                      (0xFFFFU)
34521 #define ENC_LPOSH_POSH_SHIFT                     (0U)
34522 /*! POSH - POSH
34523  */
34524 #define ENC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
34525 /*! @} */
34526 
34527 /*! @name UINIT - Upper Initialization Register */
34528 /*! @{ */
34529 
34530 #define ENC_UINIT_INIT_MASK                      (0xFFFFU)
34531 #define ENC_UINIT_INIT_SHIFT                     (0U)
34532 /*! INIT - INIT
34533  */
34534 #define ENC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
34535 /*! @} */
34536 
34537 /*! @name LINIT - Lower Initialization Register */
34538 /*! @{ */
34539 
34540 #define ENC_LINIT_INIT_MASK                      (0xFFFFU)
34541 #define ENC_LINIT_INIT_SHIFT                     (0U)
34542 /*! INIT - INIT
34543  */
34544 #define ENC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
34545 /*! @} */
34546 
34547 /*! @name IMR - Input Monitor Register */
34548 /*! @{ */
34549 
34550 #define ENC_IMR_HOME_MASK                        (0x1U)
34551 #define ENC_IMR_HOME_SHIFT                       (0U)
34552 /*! HOME - HOME
34553  */
34554 #define ENC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
34555 
34556 #define ENC_IMR_INDEX_MASK                       (0x2U)
34557 #define ENC_IMR_INDEX_SHIFT                      (1U)
34558 /*! INDEX - INDEX
34559  */
34560 #define ENC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
34561 
34562 #define ENC_IMR_PHB_MASK                         (0x4U)
34563 #define ENC_IMR_PHB_SHIFT                        (2U)
34564 /*! PHB - PHB
34565  */
34566 #define ENC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
34567 
34568 #define ENC_IMR_PHA_MASK                         (0x8U)
34569 #define ENC_IMR_PHA_SHIFT                        (3U)
34570 /*! PHA - PHA
34571  */
34572 #define ENC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
34573 
34574 #define ENC_IMR_FHOM_MASK                        (0x10U)
34575 #define ENC_IMR_FHOM_SHIFT                       (4U)
34576 /*! FHOM - FHOM
34577  */
34578 #define ENC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
34579 
34580 #define ENC_IMR_FIND_MASK                        (0x20U)
34581 #define ENC_IMR_FIND_SHIFT                       (5U)
34582 /*! FIND - FIND
34583  */
34584 #define ENC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
34585 
34586 #define ENC_IMR_FPHB_MASK                        (0x40U)
34587 #define ENC_IMR_FPHB_SHIFT                       (6U)
34588 /*! FPHB - FPHB
34589  */
34590 #define ENC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
34591 
34592 #define ENC_IMR_FPHA_MASK                        (0x80U)
34593 #define ENC_IMR_FPHA_SHIFT                       (7U)
34594 /*! FPHA - FPHA
34595  */
34596 #define ENC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
34597 /*! @} */
34598 
34599 /*! @name TST - Test Register */
34600 /*! @{ */
34601 
34602 #define ENC_TST_TEST_COUNT_MASK                  (0xFFU)
34603 #define ENC_TST_TEST_COUNT_SHIFT                 (0U)
34604 /*! TEST_COUNT - TEST_COUNT
34605  */
34606 #define ENC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
34607 
34608 #define ENC_TST_TEST_PERIOD_MASK                 (0x1F00U)
34609 #define ENC_TST_TEST_PERIOD_SHIFT                (8U)
34610 /*! TEST_PERIOD - TEST_PERIOD
34611  */
34612 #define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
34613 
34614 #define ENC_TST_QDN_MASK                         (0x2000U)
34615 #define ENC_TST_QDN_SHIFT                        (13U)
34616 /*! QDN - Quadrature Decoder Negative Signal
34617  *  0b0..Generates a positive quadrature decoder signal
34618  *  0b1..Generates a negative quadrature decoder signal
34619  */
34620 #define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
34621 
34622 #define ENC_TST_TCE_MASK                         (0x4000U)
34623 #define ENC_TST_TCE_SHIFT                        (14U)
34624 /*! TCE - Test Counter Enable
34625  *  0b0..Disabled
34626  *  0b1..Enabled
34627  */
34628 #define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
34629 
34630 #define ENC_TST_TEN_MASK                         (0x8000U)
34631 #define ENC_TST_TEN_SHIFT                        (15U)
34632 /*! TEN - Test Mode Enable
34633  *  0b0..Disabled
34634  *  0b1..Enabled
34635  */
34636 #define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
34637 /*! @} */
34638 
34639 /*! @name CTRL2 - Control 2 Register */
34640 /*! @{ */
34641 
34642 #define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
34643 #define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
34644 /*! UPDHLD - Update Hold Registers
34645  *  0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
34646  *  0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
34647  */
34648 #define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
34649 
34650 #define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
34651 #define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
34652 /*! UPDPOS - Update Position Registers
34653  *  0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
34654  *  0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
34655  */
34656 #define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
34657 
34658 #define ENC_CTRL2_MOD_MASK                       (0x4U)
34659 #define ENC_CTRL2_MOD_SHIFT                      (2U)
34660 /*! MOD - Enable Modulo Counting
34661  *  0b0..Disable modulo counting
34662  *  0b1..Enable modulo counting
34663  */
34664 #define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
34665 
34666 #define ENC_CTRL2_DIR_MASK                       (0x8U)
34667 #define ENC_CTRL2_DIR_SHIFT                      (3U)
34668 /*! DIR - Count Direction Flag
34669  *  0b0..Last count was in the down direction
34670  *  0b1..Last count was in the up direction
34671  */
34672 #define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
34673 
34674 #define ENC_CTRL2_RUIE_MASK                      (0x10U)
34675 #define ENC_CTRL2_RUIE_SHIFT                     (4U)
34676 /*! RUIE - Roll-under Interrupt Enable
34677  *  0b0..Disabled
34678  *  0b1..Enabled
34679  */
34680 #define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
34681 
34682 #define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
34683 #define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
34684 /*! RUIRQ - Roll-under Interrupt Request
34685  *  0b0..No roll-under has occurred
34686  *  0b1..Roll-under has occurred
34687  */
34688 #define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
34689 
34690 #define ENC_CTRL2_ROIE_MASK                      (0x40U)
34691 #define ENC_CTRL2_ROIE_SHIFT                     (6U)
34692 /*! ROIE - Roll-over Interrupt Enable
34693  *  0b0..Disabled
34694  *  0b1..Enabled
34695  */
34696 #define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
34697 
34698 #define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
34699 #define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
34700 /*! ROIRQ - Roll-over Interrupt Request
34701  *  0b0..No roll-over has occurred
34702  *  0b1..Roll-over has occurred
34703  */
34704 #define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
34705 
34706 #define ENC_CTRL2_REVMOD_MASK                    (0x100U)
34707 #define ENC_CTRL2_REVMOD_SHIFT                   (8U)
34708 /*! REVMOD - Revolution Counter Modulus Enable
34709  *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
34710  *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
34711  */
34712 #define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
34713 
34714 #define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
34715 #define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
34716 /*! OUTCTL - Output Control
34717  *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
34718  *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
34719  */
34720 #define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
34721 
34722 #define ENC_CTRL2_SABIE_MASK                     (0x400U)
34723 #define ENC_CTRL2_SABIE_SHIFT                    (10U)
34724 /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
34725  *  0b0..Disabled
34726  *  0b1..Enabled
34727  */
34728 #define ENC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
34729 
34730 #define ENC_CTRL2_SABIRQ_MASK                    (0x800U)
34731 #define ENC_CTRL2_SABIRQ_SHIFT                   (11U)
34732 /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
34733  *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
34734  *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
34735  */
34736 #define ENC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
34737 /*! @} */
34738 
34739 /*! @name UMOD - Upper Modulus Register */
34740 /*! @{ */
34741 
34742 #define ENC_UMOD_MOD_MASK                        (0xFFFFU)
34743 #define ENC_UMOD_MOD_SHIFT                       (0U)
34744 /*! MOD - MOD
34745  */
34746 #define ENC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
34747 /*! @} */
34748 
34749 /*! @name LMOD - Lower Modulus Register */
34750 /*! @{ */
34751 
34752 #define ENC_LMOD_MOD_MASK                        (0xFFFFU)
34753 #define ENC_LMOD_MOD_SHIFT                       (0U)
34754 /*! MOD - MOD
34755  */
34756 #define ENC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
34757 /*! @} */
34758 
34759 /*! @name UCOMP - Upper Position Compare Register */
34760 /*! @{ */
34761 
34762 #define ENC_UCOMP_COMP_MASK                      (0xFFFFU)
34763 #define ENC_UCOMP_COMP_SHIFT                     (0U)
34764 /*! COMP - COMP
34765  */
34766 #define ENC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
34767 /*! @} */
34768 
34769 /*! @name LCOMP - Lower Position Compare Register */
34770 /*! @{ */
34771 
34772 #define ENC_LCOMP_COMP_MASK                      (0xFFFFU)
34773 #define ENC_LCOMP_COMP_SHIFT                     (0U)
34774 /*! COMP - COMP
34775  */
34776 #define ENC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
34777 /*! @} */
34778 
34779 /*! @name LASTEDGE - Last Edge Time Register */
34780 /*! @{ */
34781 
34782 #define ENC_LASTEDGE_LASTEDGE_MASK               (0xFFFFU)
34783 #define ENC_LASTEDGE_LASTEDGE_SHIFT              (0U)
34784 /*! LASTEDGE - Last Edge Time Counter
34785  */
34786 #define ENC_LASTEDGE_LASTEDGE(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
34787 /*! @} */
34788 
34789 /*! @name LASTEDGEH - Last Edge Time Hold Register */
34790 /*! @{ */
34791 
34792 #define ENC_LASTEDGEH_LASTEDGEH_MASK             (0xFFFFU)
34793 #define ENC_LASTEDGEH_LASTEDGEH_SHIFT            (0U)
34794 /*! LASTEDGEH - Last Edge Time Hold
34795  */
34796 #define ENC_LASTEDGEH_LASTEDGEH(x)               (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
34797 /*! @} */
34798 
34799 /*! @name POSDPER - Position Difference Period Counter Register */
34800 /*! @{ */
34801 
34802 #define ENC_POSDPER_POSDPER_MASK                 (0xFFFFU)
34803 #define ENC_POSDPER_POSDPER_SHIFT                (0U)
34804 /*! POSDPER - Position difference period
34805  */
34806 #define ENC_POSDPER_POSDPER(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
34807 /*! @} */
34808 
34809 /*! @name POSDPERBFR - Position Difference Period Buffer Register */
34810 /*! @{ */
34811 
34812 #define ENC_POSDPERBFR_POSDPERBFR_MASK           (0xFFFFU)
34813 #define ENC_POSDPERBFR_POSDPERBFR_SHIFT          (0U)
34814 /*! POSDPERBFR - Position difference period buffer
34815  */
34816 #define ENC_POSDPERBFR_POSDPERBFR(x)             (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
34817 /*! @} */
34818 
34819 /*! @name POSDPERH - Position Difference Period Hold Register */
34820 /*! @{ */
34821 
34822 #define ENC_POSDPERH_POSDPERH_MASK               (0xFFFFU)
34823 #define ENC_POSDPERH_POSDPERH_SHIFT              (0U)
34824 /*! POSDPERH - Position difference period hold
34825  */
34826 #define ENC_POSDPERH_POSDPERH(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
34827 /*! @} */
34828 
34829 /*! @name CTRL3 - Control 3 Register */
34830 /*! @{ */
34831 
34832 #define ENC_CTRL3_PMEN_MASK                      (0x1U)
34833 #define ENC_CTRL3_PMEN_SHIFT                     (0U)
34834 /*! PMEN - Period measurement function enable
34835  *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read.
34836  *  0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.
34837  */
34838 #define ENC_CTRL3_PMEN(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)
34839 
34840 #define ENC_CTRL3_PRSC_MASK                      (0xF0U)
34841 #define ENC_CTRL3_PRSC_SHIFT                     (4U)
34842 /*! PRSC - Prescaler
34843  */
34844 #define ENC_CTRL3_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)
34845 /*! @} */
34846 
34847 
34848 /*!
34849  * @}
34850  */ /* end of group ENC_Register_Masks */
34851 
34852 
34853 /* ENC - Peripheral instance base addresses */
34854 /** Peripheral ENC1 base address */
34855 #define ENC1_BASE                                (0x40174000u)
34856 /** Peripheral ENC1 base pointer */
34857 #define ENC1                                     ((ENC_Type *)ENC1_BASE)
34858 /** Peripheral ENC2 base address */
34859 #define ENC2_BASE                                (0x40178000u)
34860 /** Peripheral ENC2 base pointer */
34861 #define ENC2                                     ((ENC_Type *)ENC2_BASE)
34862 /** Peripheral ENC3 base address */
34863 #define ENC3_BASE                                (0x4017C000u)
34864 /** Peripheral ENC3 base pointer */
34865 #define ENC3                                     ((ENC_Type *)ENC3_BASE)
34866 /** Peripheral ENC4 base address */
34867 #define ENC4_BASE                                (0x40180000u)
34868 /** Peripheral ENC4 base pointer */
34869 #define ENC4                                     ((ENC_Type *)ENC4_BASE)
34870 /** Array initializer of ENC peripheral base addresses */
34871 #define ENC_BASE_ADDRS                           { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
34872 /** Array initializer of ENC peripheral base pointers */
34873 #define ENC_BASE_PTRS                            { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
34874 /** Interrupt vectors for the ENC peripheral type */
34875 #define ENC_COMPARE_IRQS                         { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34876 #define ENC_HOME_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34877 #define ENC_WDOG_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34878 #define ENC_INDEX_IRQS                           { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34879 #define ENC_INPUT_SWITCH_IRQS                    { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34880 
34881 /*!
34882  * @}
34883  */ /* end of group ENC_Peripheral_Access_Layer */
34884 
34885 
34886 /* ----------------------------------------------------------------------------
34887    -- ENET Peripheral Access Layer
34888    ---------------------------------------------------------------------------- */
34889 
34890 /*!
34891  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
34892  * @{
34893  */
34894 
34895 /** ENET - Register Layout Typedef */
34896 typedef struct {
34897        uint8_t RESERVED_0[4];
34898   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
34899   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
34900        uint8_t RESERVED_1[4];
34901   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
34902   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
34903        uint8_t RESERVED_2[12];
34904   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
34905        uint8_t RESERVED_3[24];
34906   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
34907   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
34908        uint8_t RESERVED_4[28];
34909   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
34910        uint8_t RESERVED_5[28];
34911   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
34912        uint8_t RESERVED_6[60];
34913   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
34914        uint8_t RESERVED_7[28];
34915   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
34916   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
34917   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
34918   __IO uint32_t TXIC[3];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
34919        uint8_t RESERVED_8[4];
34920   __IO uint32_t RXIC[3];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
34921        uint8_t RESERVED_9[12];
34922   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
34923   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
34924   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
34925   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
34926        uint8_t RESERVED_10[28];
34927   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
34928        uint8_t RESERVED_11[24];
34929   __IO uint32_t RDSR1;                             /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
34930   __IO uint32_t TDSR1;                             /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
34931   __IO uint32_t MRBR1;                             /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
34932   __IO uint32_t RDSR2;                             /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
34933   __IO uint32_t TDSR2;                             /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
34934   __IO uint32_t MRBR2;                             /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
34935        uint8_t RESERVED_12[8];
34936   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
34937   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
34938   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
34939        uint8_t RESERVED_13[4];
34940   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
34941   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
34942   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
34943   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
34944   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
34945   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
34946   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
34947   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
34948   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
34949        uint8_t RESERVED_14[12];
34950   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
34951   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
34952   __IO uint32_t RCMR[2];                           /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
34953        uint8_t RESERVED_15[8];
34954   __IO uint32_t DMACFG[2];                         /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
34955   __IO uint32_t RDAR1;                             /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
34956   __IO uint32_t TDAR1;                             /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
34957   __IO uint32_t RDAR2;                             /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
34958   __IO uint32_t TDAR2;                             /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
34959   __IO uint32_t QOS;                               /**< QOS Scheme, offset: 0x1F0 */
34960        uint8_t RESERVED_16[16];
34961   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
34962   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
34963   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
34964   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
34965   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
34966   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
34967   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
34968   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
34969   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
34970   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
34971   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
34972   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
34973   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
34974   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
34975   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
34976   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
34977   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
34978        uint32_t IEEE_T_DROP;                       /**< Reserved Statistic Register, offset: 0x248 */
34979   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
34980   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
34981   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
34982   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
34983   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
34984   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
34985   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
34986   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
34987   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
34988   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
34989   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
34990        uint8_t RESERVED_17[12];
34991   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
34992   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
34993   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
34994   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
34995   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
34996   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
34997   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
34998   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
34999        uint8_t RESERVED_18[4];
35000   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
35001   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
35002   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
35003   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
35004   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
35005   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
35006   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
35007   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
35008   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
35009   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
35010   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
35011   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
35012   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
35013   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
35014   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
35015        uint8_t RESERVED_19[284];
35016   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
35017   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
35018   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
35019   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
35020   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
35021   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
35022   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
35023        uint8_t RESERVED_20[488];
35024   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
35025   struct {                                         /* offset: 0x608, array step: 0x8 */
35026     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
35027     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
35028   } CHANNEL[4];
35029 } ENET_Type;
35030 
35031 /* ----------------------------------------------------------------------------
35032    -- ENET Register Masks
35033    ---------------------------------------------------------------------------- */
35034 
35035 /*!
35036  * @addtogroup ENET_Register_Masks ENET Register Masks
35037  * @{
35038  */
35039 
35040 /*! @name EIR - Interrupt Event Register */
35041 /*! @{ */
35042 
35043 #define ENET_EIR_RXB1_MASK                       (0x1U)
35044 #define ENET_EIR_RXB1_SHIFT                      (0U)
35045 /*! RXB1 - Receive buffer interrupt, class 1
35046  */
35047 #define ENET_EIR_RXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
35048 
35049 #define ENET_EIR_RXF1_MASK                       (0x2U)
35050 #define ENET_EIR_RXF1_SHIFT                      (1U)
35051 /*! RXF1 - Receive frame interrupt, class 1
35052  */
35053 #define ENET_EIR_RXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
35054 
35055 #define ENET_EIR_TXB1_MASK                       (0x4U)
35056 #define ENET_EIR_TXB1_SHIFT                      (2U)
35057 /*! TXB1 - Transmit buffer interrupt, class 1
35058  */
35059 #define ENET_EIR_TXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
35060 
35061 #define ENET_EIR_TXF1_MASK                       (0x8U)
35062 #define ENET_EIR_TXF1_SHIFT                      (3U)
35063 /*! TXF1 - Transmit frame interrupt, class 1
35064  */
35065 #define ENET_EIR_TXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
35066 
35067 #define ENET_EIR_RXB2_MASK                       (0x10U)
35068 #define ENET_EIR_RXB2_SHIFT                      (4U)
35069 /*! RXB2 - Receive buffer interrupt, class 2
35070  */
35071 #define ENET_EIR_RXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
35072 
35073 #define ENET_EIR_RXF2_MASK                       (0x20U)
35074 #define ENET_EIR_RXF2_SHIFT                      (5U)
35075 /*! RXF2 - Receive frame interrupt, class 2
35076  */
35077 #define ENET_EIR_RXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
35078 
35079 #define ENET_EIR_TXB2_MASK                       (0x40U)
35080 #define ENET_EIR_TXB2_SHIFT                      (6U)
35081 /*! TXB2 - Transmit buffer interrupt, class 2
35082  */
35083 #define ENET_EIR_TXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
35084 
35085 #define ENET_EIR_TXF2_MASK                       (0x80U)
35086 #define ENET_EIR_TXF2_SHIFT                      (7U)
35087 /*! TXF2 - Transmit frame interrupt, class 2
35088  */
35089 #define ENET_EIR_TXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
35090 
35091 #define ENET_EIR_RXFLUSH_0_MASK                  (0x1000U)
35092 #define ENET_EIR_RXFLUSH_0_SHIFT                 (12U)
35093 #define ENET_EIR_RXFLUSH_0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
35094 
35095 #define ENET_EIR_RXFLUSH_1_MASK                  (0x2000U)
35096 #define ENET_EIR_RXFLUSH_1_SHIFT                 (13U)
35097 #define ENET_EIR_RXFLUSH_1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
35098 
35099 #define ENET_EIR_RXFLUSH_2_MASK                  (0x4000U)
35100 #define ENET_EIR_RXFLUSH_2_SHIFT                 (14U)
35101 #define ENET_EIR_RXFLUSH_2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
35102 
35103 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
35104 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
35105 /*! TS_TIMER - Timestamp Timer
35106  */
35107 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
35108 
35109 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
35110 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
35111 /*! TS_AVAIL - Transmit Timestamp Available
35112  */
35113 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
35114 
35115 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
35116 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
35117 /*! WAKEUP - Node Wakeup Request Indication
35118  */
35119 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
35120 
35121 #define ENET_EIR_PLR_MASK                        (0x40000U)
35122 #define ENET_EIR_PLR_SHIFT                       (18U)
35123 /*! PLR - Payload Receive Error
35124  */
35125 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
35126 
35127 #define ENET_EIR_UN_MASK                         (0x80000U)
35128 #define ENET_EIR_UN_SHIFT                        (19U)
35129 /*! UN - Transmit FIFO Underrun
35130  */
35131 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
35132 
35133 #define ENET_EIR_RL_MASK                         (0x100000U)
35134 #define ENET_EIR_RL_SHIFT                        (20U)
35135 /*! RL - Collision Retry Limit
35136  */
35137 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
35138 
35139 #define ENET_EIR_LC_MASK                         (0x200000U)
35140 #define ENET_EIR_LC_SHIFT                        (21U)
35141 /*! LC - Late Collision
35142  */
35143 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
35144 
35145 #define ENET_EIR_EBERR_MASK                      (0x400000U)
35146 #define ENET_EIR_EBERR_SHIFT                     (22U)
35147 /*! EBERR - Ethernet Bus Error
35148  */
35149 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
35150 
35151 #define ENET_EIR_MII_MASK                        (0x800000U)
35152 #define ENET_EIR_MII_SHIFT                       (23U)
35153 /*! MII - MII Interrupt.
35154  */
35155 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
35156 
35157 #define ENET_EIR_RXB_MASK                        (0x1000000U)
35158 #define ENET_EIR_RXB_SHIFT                       (24U)
35159 /*! RXB - Receive Buffer Interrupt
35160  */
35161 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
35162 
35163 #define ENET_EIR_RXF_MASK                        (0x2000000U)
35164 #define ENET_EIR_RXF_SHIFT                       (25U)
35165 /*! RXF - Receive Frame Interrupt
35166  */
35167 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
35168 
35169 #define ENET_EIR_TXB_MASK                        (0x4000000U)
35170 #define ENET_EIR_TXB_SHIFT                       (26U)
35171 /*! TXB - Transmit Buffer Interrupt
35172  */
35173 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
35174 
35175 #define ENET_EIR_TXF_MASK                        (0x8000000U)
35176 #define ENET_EIR_TXF_SHIFT                       (27U)
35177 /*! TXF - Transmit Frame Interrupt
35178  */
35179 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
35180 
35181 #define ENET_EIR_GRA_MASK                        (0x10000000U)
35182 #define ENET_EIR_GRA_SHIFT                       (28U)
35183 /*! GRA - Graceful Stop Complete
35184  */
35185 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
35186 
35187 #define ENET_EIR_BABT_MASK                       (0x20000000U)
35188 #define ENET_EIR_BABT_SHIFT                      (29U)
35189 /*! BABT - Babbling Transmit Error
35190  */
35191 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
35192 
35193 #define ENET_EIR_BABR_MASK                       (0x40000000U)
35194 #define ENET_EIR_BABR_SHIFT                      (30U)
35195 /*! BABR - Babbling Receive Error
35196  */
35197 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
35198 /*! @} */
35199 
35200 /*! @name EIMR - Interrupt Mask Register */
35201 /*! @{ */
35202 
35203 #define ENET_EIMR_RXB1_MASK                      (0x1U)
35204 #define ENET_EIMR_RXB1_SHIFT                     (0U)
35205 /*! RXB1 - Receive buffer interrupt, class 1
35206  *  0b0..The corresponding interrupt source is masked.
35207  *  0b1..The corresponding interrupt source is not masked.
35208  */
35209 #define ENET_EIMR_RXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
35210 
35211 #define ENET_EIMR_RXF1_MASK                      (0x2U)
35212 #define ENET_EIMR_RXF1_SHIFT                     (1U)
35213 /*! RXF1 - Receive frame interrupt, class 1
35214  *  0b0..The corresponding interrupt source is masked.
35215  *  0b1..The corresponding interrupt source is not masked.
35216  */
35217 #define ENET_EIMR_RXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
35218 
35219 #define ENET_EIMR_TXB1_MASK                      (0x4U)
35220 #define ENET_EIMR_TXB1_SHIFT                     (2U)
35221 /*! TXB1 - Transmit buffer interrupt, class 1
35222  *  0b0..The corresponding interrupt source is masked.
35223  *  0b1..The corresponding interrupt source is not masked.
35224  */
35225 #define ENET_EIMR_TXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
35226 
35227 #define ENET_EIMR_TXF1_MASK                      (0x8U)
35228 #define ENET_EIMR_TXF1_SHIFT                     (3U)
35229 /*! TXF1 - Transmit frame interrupt, class 1
35230  *  0b0..The corresponding interrupt source is masked.
35231  *  0b1..The corresponding interrupt source is not masked.
35232  */
35233 #define ENET_EIMR_TXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
35234 
35235 #define ENET_EIMR_RXB2_MASK                      (0x10U)
35236 #define ENET_EIMR_RXB2_SHIFT                     (4U)
35237 /*! RXB2 - Receive buffer interrupt, class 2
35238  *  0b0..The corresponding interrupt source is masked.
35239  *  0b1..The corresponding interrupt source is not masked.
35240  */
35241 #define ENET_EIMR_RXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
35242 
35243 #define ENET_EIMR_RXF2_MASK                      (0x20U)
35244 #define ENET_EIMR_RXF2_SHIFT                     (5U)
35245 /*! RXF2 - Receive frame interrupt, class 2
35246  *  0b0..The corresponding interrupt source is masked.
35247  *  0b1..The corresponding interrupt source is not masked.
35248  */
35249 #define ENET_EIMR_RXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
35250 
35251 #define ENET_EIMR_TXB2_MASK                      (0x40U)
35252 #define ENET_EIMR_TXB2_SHIFT                     (6U)
35253 /*! TXB2 - Transmit buffer interrupt, class 2
35254  *  0b0..The corresponding interrupt source is masked.
35255  *  0b1..The corresponding interrupt source is not masked.
35256  */
35257 #define ENET_EIMR_TXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
35258 
35259 #define ENET_EIMR_TXF2_MASK                      (0x80U)
35260 #define ENET_EIMR_TXF2_SHIFT                     (7U)
35261 /*! TXF2 - Transmit frame interrupt, class 2
35262  *  0b0..The corresponding interrupt source is masked.
35263  *  0b1..The corresponding interrupt source is not masked.
35264  */
35265 #define ENET_EIMR_TXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
35266 
35267 #define ENET_EIMR_RXFLUSH_0_MASK                 (0x1000U)
35268 #define ENET_EIMR_RXFLUSH_0_SHIFT                (12U)
35269 /*! RXFLUSH_0
35270  *  0b0..The corresponding interrupt source is masked.
35271  *  0b1..The corresponding interrupt source is not masked.
35272  */
35273 #define ENET_EIMR_RXFLUSH_0(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
35274 
35275 #define ENET_EIMR_RXFLUSH_1_MASK                 (0x2000U)
35276 #define ENET_EIMR_RXFLUSH_1_SHIFT                (13U)
35277 /*! RXFLUSH_1
35278  *  0b0..The corresponding interrupt source is masked.
35279  *  0b1..The corresponding interrupt source is not masked.
35280  */
35281 #define ENET_EIMR_RXFLUSH_1(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
35282 
35283 #define ENET_EIMR_RXFLUSH_2_MASK                 (0x4000U)
35284 #define ENET_EIMR_RXFLUSH_2_SHIFT                (14U)
35285 /*! RXFLUSH_2
35286  *  0b0..The corresponding interrupt source is masked.
35287  *  0b1..The corresponding interrupt source is not masked.
35288  */
35289 #define ENET_EIMR_RXFLUSH_2(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
35290 
35291 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
35292 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
35293 /*! TS_TIMER - TS_TIMER Interrupt Mask
35294  *  0b0..The corresponding interrupt source is masked.
35295  *  0b1..The corresponding interrupt source is not masked.
35296  */
35297 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
35298 
35299 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
35300 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
35301 /*! TS_AVAIL - TS_AVAIL Interrupt Mask
35302  *  0b0..The corresponding interrupt source is masked.
35303  *  0b1..The corresponding interrupt source is not masked.
35304  */
35305 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
35306 
35307 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
35308 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
35309 /*! WAKEUP - WAKEUP Interrupt Mask
35310  *  0b0..The corresponding interrupt source is masked.
35311  *  0b1..The corresponding interrupt source is not masked.
35312  */
35313 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
35314 
35315 #define ENET_EIMR_PLR_MASK                       (0x40000U)
35316 #define ENET_EIMR_PLR_SHIFT                      (18U)
35317 /*! PLR - PLR Interrupt Mask
35318  *  0b0..The corresponding interrupt source is masked.
35319  *  0b1..The corresponding interrupt source is not masked.
35320  */
35321 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
35322 
35323 #define ENET_EIMR_UN_MASK                        (0x80000U)
35324 #define ENET_EIMR_UN_SHIFT                       (19U)
35325 /*! UN - UN Interrupt Mask
35326  *  0b0..The corresponding interrupt source is masked.
35327  *  0b1..The corresponding interrupt source is not masked.
35328  */
35329 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
35330 
35331 #define ENET_EIMR_RL_MASK                        (0x100000U)
35332 #define ENET_EIMR_RL_SHIFT                       (20U)
35333 /*! RL - RL Interrupt Mask
35334  *  0b0..The corresponding interrupt source is masked.
35335  *  0b1..The corresponding interrupt source is not masked.
35336  */
35337 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
35338 
35339 #define ENET_EIMR_LC_MASK                        (0x200000U)
35340 #define ENET_EIMR_LC_SHIFT                       (21U)
35341 /*! LC - LC Interrupt Mask
35342  *  0b0..The corresponding interrupt source is masked.
35343  *  0b1..The corresponding interrupt source is not masked.
35344  */
35345 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
35346 
35347 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
35348 #define ENET_EIMR_EBERR_SHIFT                    (22U)
35349 /*! EBERR - EBERR Interrupt Mask
35350  *  0b0..The corresponding interrupt source is masked.
35351  *  0b1..The corresponding interrupt source is not masked.
35352  */
35353 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
35354 
35355 #define ENET_EIMR_MII_MASK                       (0x800000U)
35356 #define ENET_EIMR_MII_SHIFT                      (23U)
35357 /*! MII - MII Interrupt Mask
35358  *  0b0..The corresponding interrupt source is masked.
35359  *  0b1..The corresponding interrupt source is not masked.
35360  */
35361 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
35362 
35363 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
35364 #define ENET_EIMR_RXB_SHIFT                      (24U)
35365 /*! RXB - RXB Interrupt Mask
35366  *  0b0..The corresponding interrupt source is masked.
35367  *  0b1..The corresponding interrupt source is not masked.
35368  */
35369 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
35370 
35371 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
35372 #define ENET_EIMR_RXF_SHIFT                      (25U)
35373 /*! RXF - RXF Interrupt Mask
35374  *  0b0..The corresponding interrupt source is masked.
35375  *  0b1..The corresponding interrupt source is not masked.
35376  */
35377 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
35378 
35379 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
35380 #define ENET_EIMR_TXB_SHIFT                      (26U)
35381 /*! TXB - TXB Interrupt Mask
35382  *  0b0..The corresponding interrupt source is masked.
35383  *  0b1..The corresponding interrupt source is not masked.
35384  */
35385 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
35386 
35387 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
35388 #define ENET_EIMR_TXF_SHIFT                      (27U)
35389 /*! TXF - TXF Interrupt Mask
35390  *  0b0..The corresponding interrupt source is masked.
35391  *  0b1..The corresponding interrupt source is not masked.
35392  */
35393 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
35394 
35395 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
35396 #define ENET_EIMR_GRA_SHIFT                      (28U)
35397 /*! GRA - GRA Interrupt Mask
35398  *  0b0..The corresponding interrupt source is masked.
35399  *  0b1..The corresponding interrupt source is not masked.
35400  */
35401 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
35402 
35403 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
35404 #define ENET_EIMR_BABT_SHIFT                     (29U)
35405 /*! BABT - BABT Interrupt Mask
35406  *  0b0..The corresponding interrupt source is masked.
35407  *  0b1..The corresponding interrupt source is not masked.
35408  */
35409 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
35410 
35411 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
35412 #define ENET_EIMR_BABR_SHIFT                     (30U)
35413 /*! BABR - BABR Interrupt Mask
35414  *  0b0..The corresponding interrupt source is masked.
35415  *  0b1..The corresponding interrupt source is not masked.
35416  */
35417 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
35418 /*! @} */
35419 
35420 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
35421 /*! @{ */
35422 
35423 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
35424 #define ENET_RDAR_RDAR_SHIFT                     (24U)
35425 /*! RDAR - Receive Descriptor Active
35426  */
35427 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
35428 /*! @} */
35429 
35430 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
35431 /*! @{ */
35432 
35433 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
35434 #define ENET_TDAR_TDAR_SHIFT                     (24U)
35435 /*! TDAR - Transmit Descriptor Active
35436  */
35437 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
35438 /*! @} */
35439 
35440 /*! @name ECR - Ethernet Control Register */
35441 /*! @{ */
35442 
35443 #define ENET_ECR_RESET_MASK                      (0x1U)
35444 #define ENET_ECR_RESET_SHIFT                     (0U)
35445 /*! RESET - Ethernet MAC Reset
35446  */
35447 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
35448 
35449 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
35450 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
35451 /*! ETHEREN - Ethernet Enable
35452  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
35453  *  0b1..MAC is enabled, and reception and transmission are possible.
35454  */
35455 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
35456 
35457 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
35458 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
35459 /*! MAGICEN - Magic Packet Detection Enable
35460  *  0b0..Magic detection logic disabled.
35461  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
35462  */
35463 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
35464 
35465 #define ENET_ECR_SLEEP_MASK                      (0x8U)
35466 #define ENET_ECR_SLEEP_SHIFT                     (3U)
35467 /*! SLEEP - Sleep Mode Enable
35468  *  0b0..Normal operating mode.
35469  *  0b1..Sleep mode.
35470  */
35471 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
35472 
35473 #define ENET_ECR_EN1588_MASK                     (0x10U)
35474 #define ENET_ECR_EN1588_SHIFT                    (4U)
35475 /*! EN1588 - EN1588 Enable
35476  *  0b0..Legacy FEC buffer descriptors and functions enabled.
35477  *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
35478  */
35479 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
35480 
35481 #define ENET_ECR_SPEED_MASK                      (0x20U)
35482 #define ENET_ECR_SPEED_SHIFT                     (5U)
35483 /*! SPEED
35484  *  0b0..10/100-Mbit/s mode
35485  *  0b1..1000-Mbit/s mode
35486  */
35487 #define ENET_ECR_SPEED(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
35488 
35489 #define ENET_ECR_DBGEN_MASK                      (0x40U)
35490 #define ENET_ECR_DBGEN_SHIFT                     (6U)
35491 /*! DBGEN - Debug Enable
35492  *  0b0..MAC continues operation in debug mode.
35493  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
35494  */
35495 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
35496 
35497 #define ENET_ECR_DBSWP_MASK                      (0x100U)
35498 #define ENET_ECR_DBSWP_SHIFT                     (8U)
35499 /*! DBSWP - Descriptor Byte Swapping Enable
35500  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
35501  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
35502  */
35503 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
35504 
35505 #define ENET_ECR_SVLANEN_MASK                    (0x200U)
35506 #define ENET_ECR_SVLANEN_SHIFT                   (9U)
35507 /*! SVLANEN - S-VLAN enable
35508  *  0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
35509  *  0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
35510  *       receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
35511  *       classification match comparators, RCMRn.
35512  */
35513 #define ENET_ECR_SVLANEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
35514 
35515 #define ENET_ECR_VLANUSE2ND_MASK                 (0x400U)
35516 #define ENET_ECR_VLANUSE2ND_SHIFT                (10U)
35517 /*! VLANUSE2ND - VLAN use second tag
35518  *  0b0..Always extract data from the first VLAN tag if it exists.
35519  *  0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
35520  *       double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
35521  *       second tag must be a C-VLAN
35522  */
35523 #define ENET_ECR_VLANUSE2ND(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
35524 
35525 #define ENET_ECR_SVLANDBL_MASK                   (0x800U)
35526 #define ENET_ECR_SVLANDBL_SHIFT                  (11U)
35527 /*! SVLANDBL - S-VLAN double tag
35528  *  0b0..Disable S-VLAN double tag
35529  *  0b1..Enable S-VLAN double tag
35530  */
35531 #define ENET_ECR_SVLANDBL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
35532 
35533 #define ENET_ECR_TXC_DLY_MASK                    (0x10000U)
35534 #define ENET_ECR_TXC_DLY_SHIFT                   (16U)
35535 /*! TXC_DLY - Transmit clock delay
35536  *  0b0..RGMII_TXC is not delayed.
35537  *  0b1..Generate delayed version of RGMII_TXC.
35538  */
35539 #define ENET_ECR_TXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
35540 /*! @} */
35541 
35542 /*! @name MMFR - MII Management Frame Register */
35543 /*! @{ */
35544 
35545 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
35546 #define ENET_MMFR_DATA_SHIFT                     (0U)
35547 /*! DATA - Management Frame Data
35548  */
35549 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
35550 
35551 #define ENET_MMFR_TA_MASK                        (0x30000U)
35552 #define ENET_MMFR_TA_SHIFT                       (16U)
35553 /*! TA - Turn Around
35554  */
35555 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
35556 
35557 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
35558 #define ENET_MMFR_RA_SHIFT                       (18U)
35559 /*! RA - Register Address
35560  */
35561 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
35562 
35563 #define ENET_MMFR_PA_MASK                        (0xF800000U)
35564 #define ENET_MMFR_PA_SHIFT                       (23U)
35565 /*! PA - PHY Address
35566  */
35567 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
35568 
35569 #define ENET_MMFR_OP_MASK                        (0x30000000U)
35570 #define ENET_MMFR_OP_SHIFT                       (28U)
35571 /*! OP - Operation Code
35572  */
35573 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
35574 
35575 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
35576 #define ENET_MMFR_ST_SHIFT                       (30U)
35577 /*! ST - Start Of Frame Delimiter
35578  */
35579 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
35580 /*! @} */
35581 
35582 /*! @name MSCR - MII Speed Control Register */
35583 /*! @{ */
35584 
35585 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
35586 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
35587 /*! MII_SPEED - MII Speed
35588  */
35589 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
35590 
35591 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
35592 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
35593 /*! DIS_PRE - Disable Preamble
35594  *  0b0..Preamble enabled.
35595  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
35596  */
35597 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
35598 
35599 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
35600 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
35601 /*! HOLDTIME - Hold time On MDIO Output
35602  *  0b000..1 internal module clock cycle
35603  *  0b001..2 internal module clock cycles
35604  *  0b010..3 internal module clock cycles
35605  *  0b111..8 internal module clock cycles
35606  */
35607 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
35608 /*! @} */
35609 
35610 /*! @name MIBC - MIB Control Register */
35611 /*! @{ */
35612 
35613 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
35614 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
35615 /*! MIB_CLEAR - MIB Clear
35616  *  0b0..See note above.
35617  *  0b1..All statistics counters are reset to 0.
35618  */
35619 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
35620 
35621 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
35622 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
35623 /*! MIB_IDLE - MIB Idle
35624  *  0b0..The MIB block is updating MIB counters.
35625  *  0b1..The MIB block is not currently updating any MIB counters.
35626  */
35627 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
35628 
35629 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
35630 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
35631 /*! MIB_DIS - Disable MIB Logic
35632  *  0b0..MIB logic is enabled.
35633  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
35634  */
35635 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
35636 /*! @} */
35637 
35638 /*! @name RCR - Receive Control Register */
35639 /*! @{ */
35640 
35641 #define ENET_RCR_LOOP_MASK                       (0x1U)
35642 #define ENET_RCR_LOOP_SHIFT                      (0U)
35643 /*! LOOP - Internal Loopback
35644  *  0b0..Loopback disabled.
35645  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
35646  */
35647 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
35648 
35649 #define ENET_RCR_DRT_MASK                        (0x2U)
35650 #define ENET_RCR_DRT_SHIFT                       (1U)
35651 /*! DRT - Disable Receive On Transmit
35652  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
35653  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
35654  */
35655 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
35656 
35657 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
35658 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
35659 /*! MII_MODE - Media Independent Interface Mode
35660  *  0b0..Reserved.
35661  *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
35662  */
35663 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
35664 
35665 #define ENET_RCR_PROM_MASK                       (0x8U)
35666 #define ENET_RCR_PROM_SHIFT                      (3U)
35667 /*! PROM - Promiscuous Mode
35668  *  0b0..Disabled.
35669  *  0b1..Enabled.
35670  */
35671 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
35672 
35673 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
35674 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
35675 /*! BC_REJ - Broadcast Frame Reject
35676  *  0b0..Will not reject frames as described above
35677  *  0b1..Will reject frames as described above
35678  */
35679 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
35680 
35681 #define ENET_RCR_FCE_MASK                        (0x20U)
35682 #define ENET_RCR_FCE_SHIFT                       (5U)
35683 /*! FCE - Flow Control Enable
35684  *  0b0..Disable flow control
35685  *  0b1..Enable flow control
35686  */
35687 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
35688 
35689 #define ENET_RCR_RGMII_EN_MASK                   (0x40U)
35690 #define ENET_RCR_RGMII_EN_SHIFT                  (6U)
35691 /*! RGMII_EN - RGMII Mode Enable
35692  *  0b0..MAC configured for non-RGMII operation
35693  *  0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
35694  *       ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
35695  */
35696 #define ENET_RCR_RGMII_EN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
35697 
35698 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
35699 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
35700 /*! RMII_MODE - RMII Mode Enable
35701  *  0b0..MAC configured for MII mode.
35702  *  0b1..MAC configured for RMII operation.
35703  */
35704 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
35705 
35706 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
35707 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
35708 /*! RMII_10T
35709  *  0b0..100-Mbit/s or 1-Gbit/s operation.
35710  *  0b1..10-Mbit/s operation.
35711  */
35712 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
35713 
35714 #define ENET_RCR_PADEN_MASK                      (0x1000U)
35715 #define ENET_RCR_PADEN_SHIFT                     (12U)
35716 /*! PADEN - Enable Frame Padding Remove On Receive
35717  *  0b0..No padding is removed on receive by the MAC.
35718  *  0b1..Padding is removed from received frames.
35719  */
35720 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
35721 
35722 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
35723 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
35724 /*! PAUFWD - Terminate/Forward Pause Frames
35725  *  0b0..Pause frames are terminated and discarded in the MAC.
35726  *  0b1..Pause frames are forwarded to the user application.
35727  */
35728 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
35729 
35730 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
35731 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
35732 /*! CRCFWD - Terminate/Forward Received CRC
35733  *  0b0..The CRC field of received frames is transmitted to the user application.
35734  *  0b1..The CRC field is stripped from the frame.
35735  */
35736 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
35737 
35738 #define ENET_RCR_CFEN_MASK                       (0x8000U)
35739 #define ENET_RCR_CFEN_SHIFT                      (15U)
35740 /*! CFEN - MAC Control Frame Enable
35741  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
35742  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
35743  */
35744 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
35745 
35746 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
35747 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
35748 /*! MAX_FL - Maximum Frame Length
35749  */
35750 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
35751 
35752 #define ENET_RCR_NLC_MASK                        (0x40000000U)
35753 #define ENET_RCR_NLC_SHIFT                       (30U)
35754 /*! NLC - Payload Length Check Disable
35755  *  0b0..The payload length check is disabled.
35756  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
35757  */
35758 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
35759 
35760 #define ENET_RCR_GRS_MASK                        (0x80000000U)
35761 #define ENET_RCR_GRS_SHIFT                       (31U)
35762 /*! GRS - Graceful Receive Stopped
35763  *  0b0..Receive not stopped
35764  *  0b1..Receive stopped
35765  */
35766 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
35767 /*! @} */
35768 
35769 /*! @name TCR - Transmit Control Register */
35770 /*! @{ */
35771 
35772 #define ENET_TCR_GTS_MASK                        (0x1U)
35773 #define ENET_TCR_GTS_SHIFT                       (0U)
35774 /*! GTS - Graceful Transmit Stop
35775  *  0b0..Disable graceful transmit stop
35776  *  0b1..Enable graceful transmit stop
35777  */
35778 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
35779 
35780 #define ENET_TCR_FDEN_MASK                       (0x4U)
35781 #define ENET_TCR_FDEN_SHIFT                      (2U)
35782 /*! FDEN - Full-Duplex Enable
35783  *  0b0..Disable full-duplex
35784  *  0b1..Enable full-duplex
35785  */
35786 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
35787 
35788 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
35789 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
35790 /*! TFC_PAUSE - Transmit Frame Control Pause
35791  *  0b0..No PAUSE frame transmitted.
35792  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
35793  */
35794 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
35795 
35796 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
35797 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
35798 /*! RFC_PAUSE - Receive Frame Control Pause
35799  */
35800 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
35801 
35802 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
35803 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
35804 /*! ADDSEL - Source MAC Address Select On Transmit
35805  *  0b000..Node MAC address programmed on PADDR1/2 registers.
35806  *  0b100..Reserved.
35807  *  0b101..Reserved.
35808  *  0b110..Reserved.
35809  */
35810 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
35811 
35812 #define ENET_TCR_ADDINS_MASK                     (0x100U)
35813 #define ENET_TCR_ADDINS_SHIFT                    (8U)
35814 /*! ADDINS - Set MAC Address On Transmit
35815  *  0b0..The source MAC address is not modified by the MAC.
35816  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
35817  */
35818 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
35819 
35820 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
35821 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
35822 /*! CRCFWD - Forward Frame From Application With CRC
35823  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
35824  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
35825  */
35826 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
35827 /*! @} */
35828 
35829 /*! @name PALR - Physical Address Lower Register */
35830 /*! @{ */
35831 
35832 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
35833 #define ENET_PALR_PADDR1_SHIFT                   (0U)
35834 /*! PADDR1 - Pause Address
35835  */
35836 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
35837 /*! @} */
35838 
35839 /*! @name PAUR - Physical Address Upper Register */
35840 /*! @{ */
35841 
35842 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
35843 #define ENET_PAUR_TYPE_SHIFT                     (0U)
35844 /*! TYPE - Type Field In PAUSE Frames
35845  */
35846 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
35847 
35848 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
35849 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
35850 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
35851 /*! @} */
35852 
35853 /*! @name OPD - Opcode/Pause Duration Register */
35854 /*! @{ */
35855 
35856 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
35857 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
35858 /*! PAUSE_DUR - Pause Duration
35859  */
35860 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
35861 
35862 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
35863 #define ENET_OPD_OPCODE_SHIFT                    (16U)
35864 /*! OPCODE - Opcode Field In PAUSE Frames
35865  */
35866 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
35867 /*! @} */
35868 
35869 /*! @name TXIC - Transmit Interrupt Coalescing Register */
35870 /*! @{ */
35871 
35872 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
35873 #define ENET_TXIC_ICTT_SHIFT                     (0U)
35874 /*! ICTT - Interrupt coalescing timer threshold
35875  */
35876 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
35877 
35878 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
35879 #define ENET_TXIC_ICFT_SHIFT                     (20U)
35880 /*! ICFT - Interrupt coalescing frame count threshold
35881  */
35882 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
35883 
35884 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
35885 #define ENET_TXIC_ICCS_SHIFT                     (30U)
35886 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
35887  *  0b0..Use MII/GMII TX clocks.
35888  *  0b1..Use ENET system clock.
35889  */
35890 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
35891 
35892 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
35893 #define ENET_TXIC_ICEN_SHIFT                     (31U)
35894 /*! ICEN - Interrupt Coalescing Enable
35895  *  0b0..Disable Interrupt coalescing.
35896  *  0b1..Enable Interrupt coalescing.
35897  */
35898 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
35899 /*! @} */
35900 
35901 /* The count of ENET_TXIC */
35902 #define ENET_TXIC_COUNT                          (3U)
35903 
35904 /*! @name RXIC - Receive Interrupt Coalescing Register */
35905 /*! @{ */
35906 
35907 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
35908 #define ENET_RXIC_ICTT_SHIFT                     (0U)
35909 /*! ICTT - Interrupt coalescing timer threshold
35910  */
35911 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
35912 
35913 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
35914 #define ENET_RXIC_ICFT_SHIFT                     (20U)
35915 /*! ICFT - Interrupt coalescing frame count threshold
35916  */
35917 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
35918 
35919 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
35920 #define ENET_RXIC_ICCS_SHIFT                     (30U)
35921 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
35922  *  0b0..Use MII/GMII TX clocks.
35923  *  0b1..Use ENET system clock.
35924  */
35925 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
35926 
35927 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
35928 #define ENET_RXIC_ICEN_SHIFT                     (31U)
35929 /*! ICEN - Interrupt Coalescing Enable
35930  *  0b0..Disable Interrupt coalescing.
35931  *  0b1..Enable Interrupt coalescing.
35932  */
35933 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
35934 /*! @} */
35935 
35936 /* The count of ENET_RXIC */
35937 #define ENET_RXIC_COUNT                          (3U)
35938 
35939 /*! @name IAUR - Descriptor Individual Upper Address Register */
35940 /*! @{ */
35941 
35942 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
35943 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
35944 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
35945 /*! @} */
35946 
35947 /*! @name IALR - Descriptor Individual Lower Address Register */
35948 /*! @{ */
35949 
35950 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
35951 #define ENET_IALR_IADDR2_SHIFT                   (0U)
35952 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
35953 /*! @} */
35954 
35955 /*! @name GAUR - Descriptor Group Upper Address Register */
35956 /*! @{ */
35957 
35958 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
35959 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
35960 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
35961 /*! @} */
35962 
35963 /*! @name GALR - Descriptor Group Lower Address Register */
35964 /*! @{ */
35965 
35966 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
35967 #define ENET_GALR_GADDR2_SHIFT                   (0U)
35968 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
35969 /*! @} */
35970 
35971 /*! @name TFWR - Transmit FIFO Watermark Register */
35972 /*! @{ */
35973 
35974 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
35975 #define ENET_TFWR_TFWR_SHIFT                     (0U)
35976 /*! TFWR - Transmit FIFO Write
35977  *  0b000000..64 bytes written.
35978  *  0b000001..64 bytes written.
35979  *  0b000010..128 bytes written.
35980  *  0b000011..192 bytes written.
35981  *  0b111111..4032 bytes written.
35982  */
35983 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
35984 
35985 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
35986 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
35987 /*! STRFWD - Store And Forward Enable
35988  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
35989  *  0b1..Enabled.
35990  */
35991 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
35992 /*! @} */
35993 
35994 /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
35995 /*! @{ */
35996 
35997 #define ENET_RDSR1_R_DES_START_MASK              (0xFFFFFFF8U)
35998 #define ENET_RDSR1_R_DES_START_SHIFT             (3U)
35999 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
36000 /*! @} */
36001 
36002 /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
36003 /*! @{ */
36004 
36005 #define ENET_TDSR1_X_DES_START_MASK              (0xFFFFFFF8U)
36006 #define ENET_TDSR1_X_DES_START_SHIFT             (3U)
36007 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
36008 /*! @} */
36009 
36010 /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
36011 /*! @{ */
36012 
36013 #define ENET_MRBR1_R_BUF_SIZE_MASK               (0x7F0U)
36014 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              (4U)
36015 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
36016 /*! @} */
36017 
36018 /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
36019 /*! @{ */
36020 
36021 #define ENET_RDSR2_R_DES_START_MASK              (0xFFFFFFF8U)
36022 #define ENET_RDSR2_R_DES_START_SHIFT             (3U)
36023 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
36024 /*! @} */
36025 
36026 /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
36027 /*! @{ */
36028 
36029 #define ENET_TDSR2_X_DES_START_MASK              (0xFFFFFFF8U)
36030 #define ENET_TDSR2_X_DES_START_SHIFT             (3U)
36031 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
36032 /*! @} */
36033 
36034 /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
36035 /*! @{ */
36036 
36037 #define ENET_MRBR2_R_BUF_SIZE_MASK               (0x7F0U)
36038 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              (4U)
36039 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
36040 /*! @} */
36041 
36042 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
36043 /*! @{ */
36044 
36045 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
36046 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
36047 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
36048 /*! @} */
36049 
36050 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
36051 /*! @{ */
36052 
36053 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
36054 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
36055 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
36056 /*! @} */
36057 
36058 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
36059 /*! @{ */
36060 
36061 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36062 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
36063 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36064 /*! @} */
36065 
36066 /*! @name RSFL - Receive FIFO Section Full Threshold */
36067 /*! @{ */
36068 
36069 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36070 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
36071 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
36072  */
36073 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36074 /*! @} */
36075 
36076 /*! @name RSEM - Receive FIFO Section Empty Threshold */
36077 /*! @{ */
36078 
36079 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36080 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
36081 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
36082  */
36083 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36084 
36085 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
36086 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
36087 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
36088  */
36089 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
36090 /*! @} */
36091 
36092 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
36093 /*! @{ */
36094 
36095 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36096 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
36097 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
36098  */
36099 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36100 /*! @} */
36101 
36102 /*! @name RAFL - Receive FIFO Almost Full Threshold */
36103 /*! @{ */
36104 
36105 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36106 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
36107 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
36108  */
36109 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36110 /*! @} */
36111 
36112 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
36113 /*! @{ */
36114 
36115 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36116 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
36117 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
36118  */
36119 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36120 /*! @} */
36121 
36122 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
36123 /*! @{ */
36124 
36125 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36126 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
36127 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
36128  */
36129 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36130 /*! @} */
36131 
36132 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
36133 /*! @{ */
36134 
36135 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36136 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
36137 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
36138  */
36139 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36140 /*! @} */
36141 
36142 /*! @name TIPG - Transmit Inter-Packet Gap */
36143 /*! @{ */
36144 
36145 #define ENET_TIPG_IPG_MASK                       (0x1FU)
36146 #define ENET_TIPG_IPG_SHIFT                      (0U)
36147 /*! IPG - Transmit Inter-Packet Gap
36148  */
36149 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
36150 /*! @} */
36151 
36152 /*! @name FTRL - Frame Truncation Length */
36153 /*! @{ */
36154 
36155 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
36156 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
36157 /*! TRUNC_FL - Frame Truncation Length
36158  */
36159 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
36160 /*! @} */
36161 
36162 /*! @name TACC - Transmit Accelerator Function Configuration */
36163 /*! @{ */
36164 
36165 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
36166 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
36167 /*! SHIFT16 - TX FIFO Shift-16
36168  *  0b0..Disabled.
36169  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
36170  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
36171  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
36172  *       extended to a 16-byte header.
36173  */
36174 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
36175 
36176 #define ENET_TACC_IPCHK_MASK                     (0x8U)
36177 #define ENET_TACC_IPCHK_SHIFT                    (3U)
36178 /*! IPCHK
36179  *  0b0..Checksum is not inserted.
36180  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
36181  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
36182  */
36183 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
36184 
36185 #define ENET_TACC_PROCHK_MASK                    (0x10U)
36186 #define ENET_TACC_PROCHK_SHIFT                   (4U)
36187 /*! PROCHK
36188  *  0b0..Checksum not inserted.
36189  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
36190  *       frame. The checksum field must be cleared. The other frames are not modified.
36191  */
36192 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
36193 /*! @} */
36194 
36195 /*! @name RACC - Receive Accelerator Function Configuration */
36196 /*! @{ */
36197 
36198 #define ENET_RACC_PADREM_MASK                    (0x1U)
36199 #define ENET_RACC_PADREM_SHIFT                   (0U)
36200 /*! PADREM - Enable Padding Removal For Short IP Frames
36201  *  0b0..Padding not removed.
36202  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
36203  */
36204 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
36205 
36206 #define ENET_RACC_IPDIS_MASK                     (0x2U)
36207 #define ENET_RACC_IPDIS_SHIFT                    (1U)
36208 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
36209  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
36210  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
36211  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
36212  *       store and forward mode (RSFL cleared).
36213  */
36214 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
36215 
36216 #define ENET_RACC_PRODIS_MASK                    (0x4U)
36217 #define ENET_RACC_PRODIS_SHIFT                   (2U)
36218 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
36219  *  0b0..Frames with wrong checksum are not discarded.
36220  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
36221  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
36222  *       cleared).
36223  */
36224 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
36225 
36226 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
36227 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
36228 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
36229  *  0b0..Frames with errors are not discarded.
36230  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
36231  */
36232 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
36233 
36234 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
36235 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
36236 /*! SHIFT16 - RX FIFO Shift-16
36237  *  0b0..Disabled.
36238  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
36239  */
36240 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
36241 /*! @} */
36242 
36243 /*! @name RCMR - Receive Classification Match Register for Class n */
36244 /*! @{ */
36245 
36246 #define ENET_RCMR_CMP0_MASK                      (0x7U)
36247 #define ENET_RCMR_CMP0_SHIFT                     (0U)
36248 /*! CMP0 - Compare 0
36249  */
36250 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
36251 
36252 #define ENET_RCMR_CMP1_MASK                      (0x70U)
36253 #define ENET_RCMR_CMP1_SHIFT                     (4U)
36254 /*! CMP1 - Compare 1
36255  */
36256 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
36257 
36258 #define ENET_RCMR_CMP2_MASK                      (0x700U)
36259 #define ENET_RCMR_CMP2_SHIFT                     (8U)
36260 /*! CMP2 - Compare 2
36261  */
36262 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
36263 
36264 #define ENET_RCMR_CMP3_MASK                      (0x7000U)
36265 #define ENET_RCMR_CMP3_SHIFT                     (12U)
36266 /*! CMP3 - Compare 3
36267  */
36268 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
36269 
36270 #define ENET_RCMR_MATCHEN_MASK                   (0x10000U)
36271 #define ENET_RCMR_MATCHEN_SHIFT                  (16U)
36272 /*! MATCHEN - Match Enable
36273  *  0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
36274  *  0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
36275  */
36276 #define ENET_RCMR_MATCHEN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
36277 /*! @} */
36278 
36279 /* The count of ENET_RCMR */
36280 #define ENET_RCMR_COUNT                          (2U)
36281 
36282 /*! @name DMACFG - DMA Class Based Configuration */
36283 /*! @{ */
36284 
36285 #define ENET_DMACFG_IDLE_SLOPE_MASK              (0xFFFFU)
36286 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             (0U)
36287 /*! IDLE_SLOPE - Idle slope
36288  */
36289 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
36290 
36291 #define ENET_DMACFG_DMA_CLASS_EN_MASK            (0x10000U)
36292 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           (16U)
36293 /*! DMA_CLASS_EN - DMA class enable
36294  *  0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
36295  *       requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
36296  *       queues are disabled then their frames will be placed in queue 0.
36297  *  0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
36298  */
36299 #define ENET_DMACFG_DMA_CLASS_EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
36300 
36301 #define ENET_DMACFG_CALC_NOIPG_MASK              (0x20000U)
36302 #define ENET_DMACFG_CALC_NOIPG_SHIFT             (17U)
36303 /*! CALC_NOIPG - Calculate no IPG
36304  *  0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
36305  *       for a frame when doing bandwidth calculations. This is the default.
36306  *  0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
36307  *       when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
36308  *       frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
36309  *       will become more bandwidth than large frames due to the relation of data to IPG overhead).
36310  */
36311 #define ENET_DMACFG_CALC_NOIPG(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
36312 /*! @} */
36313 
36314 /* The count of ENET_DMACFG */
36315 #define ENET_DMACFG_COUNT                        (2U)
36316 
36317 /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
36318 /*! @{ */
36319 
36320 #define ENET_RDAR1_RDAR_MASK                     (0x1000000U)
36321 #define ENET_RDAR1_RDAR_SHIFT                    (24U)
36322 /*! RDAR - Receive Descriptor Active
36323  */
36324 #define ENET_RDAR1_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
36325 /*! @} */
36326 
36327 /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
36328 /*! @{ */
36329 
36330 #define ENET_TDAR1_TDAR_MASK                     (0x1000000U)
36331 #define ENET_TDAR1_TDAR_SHIFT                    (24U)
36332 /*! TDAR - Transmit Descriptor Active
36333  */
36334 #define ENET_TDAR1_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
36335 /*! @} */
36336 
36337 /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
36338 /*! @{ */
36339 
36340 #define ENET_RDAR2_RDAR_MASK                     (0x1000000U)
36341 #define ENET_RDAR2_RDAR_SHIFT                    (24U)
36342 /*! RDAR - Receive Descriptor Active
36343  */
36344 #define ENET_RDAR2_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
36345 /*! @} */
36346 
36347 /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
36348 /*! @{ */
36349 
36350 #define ENET_TDAR2_TDAR_MASK                     (0x1000000U)
36351 #define ENET_TDAR2_TDAR_SHIFT                    (24U)
36352 /*! TDAR - Transmit Descriptor Active
36353  */
36354 #define ENET_TDAR2_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
36355 /*! @} */
36356 
36357 /*! @name QOS - QOS Scheme */
36358 /*! @{ */
36359 
36360 #define ENET_QOS_TX_SCHEME_MASK                  (0x7U)
36361 #define ENET_QOS_TX_SCHEME_SHIFT                 (0U)
36362 /*! TX_SCHEME - TX scheme configuration
36363  *  0b000..Credit-based scheme
36364  *  0b001..Round-robin scheme
36365  *  0b010-0b111..Reserved
36366  */
36367 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
36368 
36369 #define ENET_QOS_RX_FLUSH0_MASK                  (0x8U)
36370 #define ENET_QOS_RX_FLUSH0_SHIFT                 (3U)
36371 /*! RX_FLUSH0 - RX Flush Ring 0
36372  *  0b0..Disable
36373  *  0b1..Enable
36374  */
36375 #define ENET_QOS_RX_FLUSH0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
36376 
36377 #define ENET_QOS_RX_FLUSH1_MASK                  (0x10U)
36378 #define ENET_QOS_RX_FLUSH1_SHIFT                 (4U)
36379 /*! RX_FLUSH1 - RX Flush Ring 1
36380  *  0b0..Disable
36381  *  0b1..Enable
36382  */
36383 #define ENET_QOS_RX_FLUSH1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
36384 
36385 #define ENET_QOS_RX_FLUSH2_MASK                  (0x20U)
36386 #define ENET_QOS_RX_FLUSH2_SHIFT                 (5U)
36387 /*! RX_FLUSH2 - RX Flush Ring 2
36388  *  0b0..Disable
36389  *  0b1..Enable
36390  */
36391 #define ENET_QOS_RX_FLUSH2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
36392 /*! @} */
36393 
36394 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
36395 /*! @{ */
36396 
36397 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
36398 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
36399 /*! TXPKTS - Packet count
36400  */
36401 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
36402 /*! @} */
36403 
36404 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
36405 /*! @{ */
36406 
36407 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
36408 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
36409 /*! TXPKTS - Broadcast packets
36410  */
36411 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
36412 /*! @} */
36413 
36414 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
36415 /*! @{ */
36416 
36417 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
36418 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
36419 /*! TXPKTS - Multicast packets
36420  */
36421 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
36422 /*! @} */
36423 
36424 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
36425 /*! @{ */
36426 
36427 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
36428 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
36429 /*! TXPKTS - Packets with CRC/align error
36430  */
36431 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
36432 /*! @} */
36433 
36434 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
36435 /*! @{ */
36436 
36437 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
36438 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
36439 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
36440  */
36441 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
36442 /*! @} */
36443 
36444 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
36445 /*! @{ */
36446 
36447 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
36448 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
36449 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
36450  */
36451 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
36452 /*! @} */
36453 
36454 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
36455 /*! @{ */
36456 
36457 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
36458 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
36459 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC
36460  */
36461 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
36462 /*! @} */
36463 
36464 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
36465 /*! @{ */
36466 
36467 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
36468 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
36469 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
36470  */
36471 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
36472 /*! @} */
36473 
36474 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
36475 /*! @{ */
36476 
36477 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
36478 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
36479 /*! TXPKTS - Number of transmit collisions
36480  */
36481 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
36482 /*! @} */
36483 
36484 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
36485 /*! @{ */
36486 
36487 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
36488 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
36489 /*! TXPKTS - Number of 64-byte transmit packets
36490  */
36491 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
36492 /*! @} */
36493 
36494 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
36495 /*! @{ */
36496 
36497 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
36498 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
36499 /*! TXPKTS - Number of 65- to 127-byte transmit packets
36500  */
36501 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
36502 /*! @} */
36503 
36504 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
36505 /*! @{ */
36506 
36507 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
36508 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
36509 /*! TXPKTS - Number of 128- to 255-byte transmit packets
36510  */
36511 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
36512 /*! @} */
36513 
36514 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
36515 /*! @{ */
36516 
36517 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
36518 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
36519 /*! TXPKTS - Number of 256- to 511-byte transmit packets
36520  */
36521 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
36522 /*! @} */
36523 
36524 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
36525 /*! @{ */
36526 
36527 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
36528 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
36529 /*! TXPKTS - Number of 512- to 1023-byte transmit packets
36530  */
36531 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
36532 /*! @} */
36533 
36534 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
36535 /*! @{ */
36536 
36537 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
36538 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
36539 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets
36540  */
36541 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
36542 /*! @} */
36543 
36544 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
36545 /*! @{ */
36546 
36547 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
36548 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
36549 /*! TXPKTS - Number of transmit packets greater than 2048 bytes
36550  */
36551 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
36552 /*! @} */
36553 
36554 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
36555 /*! @{ */
36556 
36557 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
36558 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
36559 /*! TXOCTS - Number of transmit octets
36560  */
36561 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
36562 /*! @} */
36563 
36564 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
36565 /*! @{ */
36566 
36567 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
36568 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
36569 /*! COUNT - Number of frames transmitted OK
36570  */
36571 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
36572 /*! @} */
36573 
36574 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
36575 /*! @{ */
36576 
36577 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
36578 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
36579 /*! COUNT - Number of frames transmitted with one collision
36580  */
36581 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
36582 /*! @} */
36583 
36584 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
36585 /*! @{ */
36586 
36587 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
36588 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
36589 /*! COUNT - Number of frames transmitted with multiple collisions
36590  */
36591 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
36592 /*! @} */
36593 
36594 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
36595 /*! @{ */
36596 
36597 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
36598 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
36599 /*! COUNT - Number of frames transmitted with deferral delay
36600  */
36601 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
36602 /*! @} */
36603 
36604 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
36605 /*! @{ */
36606 
36607 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
36608 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
36609 /*! COUNT - Number of frames transmitted with late collision
36610  */
36611 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
36612 /*! @} */
36613 
36614 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
36615 /*! @{ */
36616 
36617 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
36618 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
36619 /*! COUNT - Number of frames transmitted with excessive collisions
36620  */
36621 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
36622 /*! @} */
36623 
36624 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
36625 /*! @{ */
36626 
36627 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
36628 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
36629 /*! COUNT - Number of frames transmitted with transmit FIFO underrun
36630  */
36631 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
36632 /*! @} */
36633 
36634 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
36635 /*! @{ */
36636 
36637 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
36638 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
36639 /*! COUNT - Number of frames transmitted with carrier sense error
36640  */
36641 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
36642 /*! @} */
36643 
36644 /*! @name IEEE_T_SQE - Reserved Statistic Register */
36645 /*! @{ */
36646 
36647 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
36648 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
36649 /*! COUNT - This read-only field is reserved and always has the value 0
36650  */
36651 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
36652 /*! @} */
36653 
36654 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
36655 /*! @{ */
36656 
36657 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
36658 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
36659 /*! COUNT - Number of flow-control pause frames transmitted
36660  */
36661 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
36662 /*! @} */
36663 
36664 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
36665 /*! @{ */
36666 
36667 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
36668 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
36669 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
36670  */
36671 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
36672 /*! @} */
36673 
36674 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
36675 /*! @{ */
36676 
36677 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
36678 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
36679 /*! COUNT - Number of packets received
36680  */
36681 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
36682 /*! @} */
36683 
36684 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
36685 /*! @{ */
36686 
36687 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
36688 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
36689 /*! COUNT - Number of receive broadcast packets
36690  */
36691 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
36692 /*! @} */
36693 
36694 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
36695 /*! @{ */
36696 
36697 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
36698 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
36699 /*! COUNT - Number of receive multicast packets
36700  */
36701 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
36702 /*! @} */
36703 
36704 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
36705 /*! @{ */
36706 
36707 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
36708 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
36709 /*! COUNT - Number of receive packets with CRC or align error
36710  */
36711 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
36712 /*! @} */
36713 
36714 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
36715 /*! @{ */
36716 
36717 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
36718 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
36719 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC
36720  */
36721 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
36722 /*! @} */
36723 
36724 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
36725 /*! @{ */
36726 
36727 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
36728 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
36729 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC
36730  */
36731 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
36732 /*! @} */
36733 
36734 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
36735 /*! @{ */
36736 
36737 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
36738 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
36739 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
36740  */
36741 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
36742 /*! @} */
36743 
36744 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
36745 /*! @{ */
36746 
36747 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
36748 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
36749 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
36750  */
36751 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
36752 /*! @} */
36753 
36754 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
36755 /*! @{ */
36756 
36757 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
36758 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
36759 /*! COUNT - Number of 64-byte receive packets
36760  */
36761 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
36762 /*! @} */
36763 
36764 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
36765 /*! @{ */
36766 
36767 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
36768 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
36769 /*! COUNT - Number of 65- to 127-byte recieve packets
36770  */
36771 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
36772 /*! @} */
36773 
36774 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
36775 /*! @{ */
36776 
36777 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
36778 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
36779 /*! COUNT - Number of 128- to 255-byte recieve packets
36780  */
36781 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
36782 /*! @} */
36783 
36784 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
36785 /*! @{ */
36786 
36787 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
36788 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
36789 /*! COUNT - Number of 256- to 511-byte recieve packets
36790  */
36791 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
36792 /*! @} */
36793 
36794 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
36795 /*! @{ */
36796 
36797 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
36798 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
36799 /*! COUNT - Number of 512- to 1023-byte recieve packets
36800  */
36801 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
36802 /*! @} */
36803 
36804 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
36805 /*! @{ */
36806 
36807 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
36808 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
36809 /*! COUNT - Number of 1024- to 2047-byte recieve packets
36810  */
36811 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
36812 /*! @} */
36813 
36814 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
36815 /*! @{ */
36816 
36817 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
36818 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
36819 /*! COUNT - Number of greater-than-2048-byte recieve packets
36820  */
36821 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
36822 /*! @} */
36823 
36824 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
36825 /*! @{ */
36826 
36827 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
36828 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
36829 /*! COUNT - Number of receive octets
36830  */
36831 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
36832 /*! @} */
36833 
36834 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
36835 /*! @{ */
36836 
36837 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
36838 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
36839 /*! COUNT - Frame count
36840  */
36841 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
36842 /*! @} */
36843 
36844 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
36845 /*! @{ */
36846 
36847 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
36848 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
36849 /*! COUNT - Number of frames received OK
36850  */
36851 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
36852 /*! @} */
36853 
36854 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
36855 /*! @{ */
36856 
36857 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
36858 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
36859 /*! COUNT - Number of frames received with CRC error
36860  */
36861 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
36862 /*! @} */
36863 
36864 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
36865 /*! @{ */
36866 
36867 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
36868 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
36869 /*! COUNT - Number of frames received with alignment error
36870  */
36871 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
36872 /*! @} */
36873 
36874 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
36875 /*! @{ */
36876 
36877 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
36878 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
36879 /*! COUNT - Receive FIFO overflow count
36880  */
36881 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
36882 /*! @} */
36883 
36884 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
36885 /*! @{ */
36886 
36887 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
36888 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
36889 /*! COUNT - Number of flow-control pause frames received
36890  */
36891 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
36892 /*! @} */
36893 
36894 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
36895 /*! @{ */
36896 
36897 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
36898 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
36899 /*! COUNT - Number of octets for frames received without error
36900  */
36901 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
36902 /*! @} */
36903 
36904 /*! @name ATCR - Adjustable Timer Control Register */
36905 /*! @{ */
36906 
36907 #define ENET_ATCR_EN_MASK                        (0x1U)
36908 #define ENET_ATCR_EN_SHIFT                       (0U)
36909 /*! EN - Enable Timer
36910  *  0b0..The timer stops at the current value.
36911  *  0b1..The timer starts incrementing.
36912  */
36913 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
36914 
36915 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
36916 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
36917 /*! OFFEN - Enable One-Shot Offset Event
36918  *  0b0..Disable.
36919  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
36920  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
36921  *       offset value must be set before setting this field.
36922  */
36923 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
36924 
36925 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
36926 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
36927 /*! OFFRST - Reset Timer On Offset Event
36928  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
36929  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
36930  */
36931 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
36932 
36933 #define ENET_ATCR_PEREN_MASK                     (0x10U)
36934 #define ENET_ATCR_PEREN_SHIFT                    (4U)
36935 /*! PEREN - Enable Periodical Event
36936  *  0b0..Disable.
36937  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
36938  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
36939  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
36940  */
36941 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
36942 
36943 #define ENET_ATCR_PINPER_MASK                    (0x80U)
36944 #define ENET_ATCR_PINPER_SHIFT                   (7U)
36945 /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
36946  *  0b0..Disable.
36947  *  0b1..Enable.
36948  */
36949 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
36950 
36951 #define ENET_ATCR_RESTART_MASK                   (0x200U)
36952 #define ENET_ATCR_RESTART_SHIFT                  (9U)
36953 /*! RESTART - Reset Timer
36954  */
36955 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
36956 
36957 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
36958 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
36959 /*! CAPTURE - Capture Timer Value
36960  *  0b0..No effect.
36961  *  0b1..The current time is captured and can be read from the ATVR register.
36962  */
36963 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
36964 
36965 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
36966 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
36967 /*! SLAVE - Enable Timer Slave Mode
36968  *  0b0..The timer is active and all configuration fields in this register are relevant.
36969  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
36970  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
36971  */
36972 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
36973 /*! @} */
36974 
36975 /*! @name ATVR - Timer Value Register */
36976 /*! @{ */
36977 
36978 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
36979 #define ENET_ATVR_ATIME_SHIFT                    (0U)
36980 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
36981 /*! @} */
36982 
36983 /*! @name ATOFF - Timer Offset Register */
36984 /*! @{ */
36985 
36986 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
36987 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
36988 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
36989 /*! @} */
36990 
36991 /*! @name ATPER - Timer Period Register */
36992 /*! @{ */
36993 
36994 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
36995 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
36996 /*! PERIOD - Value for generating periodic events
36997  */
36998 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
36999 /*! @} */
37000 
37001 /*! @name ATCOR - Timer Correction Register */
37002 /*! @{ */
37003 
37004 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
37005 #define ENET_ATCOR_COR_SHIFT                     (0U)
37006 /*! COR - Correction Counter Wrap-Around Value
37007  */
37008 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
37009 /*! @} */
37010 
37011 /*! @name ATINC - Time-Stamping Clock Period Register */
37012 /*! @{ */
37013 
37014 #define ENET_ATINC_INC_MASK                      (0x7FU)
37015 #define ENET_ATINC_INC_SHIFT                     (0U)
37016 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
37017  */
37018 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
37019 
37020 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
37021 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
37022 /*! INC_CORR - Correction Increment Value
37023  */
37024 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
37025 /*! @} */
37026 
37027 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
37028 /*! @{ */
37029 
37030 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
37031 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
37032 /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
37033  *    ff_tx_ts_frm signal asserted from the user application
37034  */
37035 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
37036 /*! @} */
37037 
37038 /*! @name TGSR - Timer Global Status Register */
37039 /*! @{ */
37040 
37041 #define ENET_TGSR_TF0_MASK                       (0x1U)
37042 #define ENET_TGSR_TF0_SHIFT                      (0U)
37043 /*! TF0 - Copy Of Timer Flag For Channel 0
37044  *  0b0..Timer Flag for Channel 0 is clear
37045  *  0b1..Timer Flag for Channel 0 is set
37046  */
37047 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
37048 
37049 #define ENET_TGSR_TF1_MASK                       (0x2U)
37050 #define ENET_TGSR_TF1_SHIFT                      (1U)
37051 /*! TF1 - Copy Of Timer Flag For Channel 1
37052  *  0b0..Timer Flag for Channel 1 is clear
37053  *  0b1..Timer Flag for Channel 1 is set
37054  */
37055 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
37056 
37057 #define ENET_TGSR_TF2_MASK                       (0x4U)
37058 #define ENET_TGSR_TF2_SHIFT                      (2U)
37059 /*! TF2 - Copy Of Timer Flag For Channel 2
37060  *  0b0..Timer Flag for Channel 2 is clear
37061  *  0b1..Timer Flag for Channel 2 is set
37062  */
37063 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
37064 
37065 #define ENET_TGSR_TF3_MASK                       (0x8U)
37066 #define ENET_TGSR_TF3_SHIFT                      (3U)
37067 /*! TF3 - Copy Of Timer Flag For Channel 3
37068  *  0b0..Timer Flag for Channel 3 is clear
37069  *  0b1..Timer Flag for Channel 3 is set
37070  */
37071 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
37072 /*! @} */
37073 
37074 /*! @name TCSR - Timer Control Status Register */
37075 /*! @{ */
37076 
37077 #define ENET_TCSR_TDRE_MASK                      (0x1U)
37078 #define ENET_TCSR_TDRE_SHIFT                     (0U)
37079 /*! TDRE - Timer DMA Request Enable
37080  *  0b0..DMA request is disabled
37081  *  0b1..DMA request is enabled
37082  */
37083 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
37084 
37085 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
37086 #define ENET_TCSR_TMODE_SHIFT                    (2U)
37087 /*! TMODE - Timer Mode
37088  *  0b0000..Timer Channel is disabled.
37089  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
37090  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
37091  *  0b0011..Timer Channel is configured for Input Capture on both edges.
37092  *  0b0100..Timer Channel is configured for Output Compare - software only.
37093  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
37094  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
37095  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
37096  *  0b1000..Reserved
37097  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
37098  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
37099  *  0b110x..Reserved
37100  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
37101  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
37102  */
37103 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
37104 
37105 #define ENET_TCSR_TIE_MASK                       (0x40U)
37106 #define ENET_TCSR_TIE_SHIFT                      (6U)
37107 /*! TIE - Timer Interrupt Enable
37108  *  0b0..Interrupt is disabled
37109  *  0b1..Interrupt is enabled
37110  */
37111 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
37112 
37113 #define ENET_TCSR_TF_MASK                        (0x80U)
37114 #define ENET_TCSR_TF_SHIFT                       (7U)
37115 /*! TF - Timer Flag
37116  *  0b0..Input Capture or Output Compare has not occurred.
37117  *  0b1..Input Capture or Output Compare has occurred.
37118  */
37119 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
37120 
37121 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
37122 #define ENET_TCSR_TPWC_SHIFT                     (11U)
37123 /*! TPWC - Timer PulseWidth Control
37124  *  0b00000..Pulse width is one 1588-clock cycle.
37125  *  0b00001..Pulse width is two 1588-clock cycles.
37126  *  0b00010..Pulse width is three 1588-clock cycles.
37127  *  0b00011..Pulse width is four 1588-clock cycles.
37128  *  0b11111..Pulse width is 32 1588-clock cycles.
37129  */
37130 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
37131 /*! @} */
37132 
37133 /* The count of ENET_TCSR */
37134 #define ENET_TCSR_COUNT                          (4U)
37135 
37136 /*! @name TCCR - Timer Compare Capture Register */
37137 /*! @{ */
37138 
37139 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
37140 #define ENET_TCCR_TCC_SHIFT                      (0U)
37141 /*! TCC - Timer Capture Compare
37142  */
37143 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
37144 /*! @} */
37145 
37146 /* The count of ENET_TCCR */
37147 #define ENET_TCCR_COUNT                          (4U)
37148 
37149 
37150 /*!
37151  * @}
37152  */ /* end of group ENET_Register_Masks */
37153 
37154 
37155 /* ENET - Peripheral instance base addresses */
37156 /** Peripheral ENET base address */
37157 #define ENET_BASE                                (0x40424000u)
37158 /** Peripheral ENET base pointer */
37159 #define ENET                                     ((ENET_Type *)ENET_BASE)
37160 /** Peripheral ENET_1G base address */
37161 #define ENET_1G_BASE                             (0x40420000u)
37162 /** Peripheral ENET_1G base pointer */
37163 #define ENET_1G                                  ((ENET_Type *)ENET_1G_BASE)
37164 /** Array initializer of ENET peripheral base addresses */
37165 #define ENET_BASE_ADDRS                          { ENET_BASE, ENET_1G_BASE }
37166 /** Array initializer of ENET peripheral base pointers */
37167 #define ENET_BASE_PTRS                           { ENET, ENET_1G }
37168 /** Interrupt vectors for the ENET peripheral type */
37169 #define ENET_Transmit_IRQS                       { ENET_IRQn, ENET_1G_IRQn }
37170 #define ENET_Receive_IRQS                        { ENET_IRQn, ENET_1G_IRQn }
37171 #define ENET_Error_IRQS                          { ENET_IRQn, ENET_1G_IRQn }
37172 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
37173 #define ENET_Ts_IRQS                             { ENET_IRQn, ENET_1G_IRQn }
37174 /* ENET Buffer Descriptor and Buffer Address Alignment. */
37175 #define ENET_BUFF_ALIGNMENT                      (64U)
37176 
37177 
37178 /*!
37179  * @}
37180  */ /* end of group ENET_Peripheral_Access_Layer */
37181 
37182 
37183 /* ----------------------------------------------------------------------------
37184    -- ENET_QOS Peripheral Access Layer
37185    ---------------------------------------------------------------------------- */
37186 
37187 /*!
37188  * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
37189  * @{
37190  */
37191 
37192 /** ENET_QOS - Register Layout Typedef */
37193 typedef struct {
37194   __IO uint32_t MAC_CONFIGURATION;                 /**< MAC Configuration Register, offset: 0x0 */
37195   __IO uint32_t MAC_EXT_CONFIGURATION;             /**< MAC Extended Configuration Register, offset: 0x4 */
37196   __IO uint32_t MAC_PACKET_FILTER;                 /**< MAC Packet Filter, offset: 0x8 */
37197   __IO uint32_t MAC_WATCHDOG_TIMEOUT;              /**< Watchdog Timeout, offset: 0xC */
37198   __IO uint32_t MAC_HASH_TABLE_REG0;               /**< MAC Hash Table Register 0, offset: 0x10 */
37199   __IO uint32_t MAC_HASH_TABLE_REG1;               /**< MAC Hash Table Register 1, offset: 0x14 */
37200        uint8_t RESERVED_0[56];
37201   __IO uint32_t MAC_VLAN_TAG_CTRL;                 /**< MAC VLAN Tag Control, offset: 0x50 */
37202   __IO uint32_t MAC_VLAN_TAG_DATA;                 /**< MAC VLAN Tag Data, offset: 0x54 */
37203   __IO uint32_t MAC_VLAN_HASH_TABLE;               /**< MAC VLAN Hash Table, offset: 0x58 */
37204        uint8_t RESERVED_1[4];
37205   __IO uint32_t MAC_VLAN_INCL;                     /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
37206   __IO uint32_t MAC_INNER_VLAN_INCL;               /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
37207        uint8_t RESERVED_2[8];
37208   __IO uint32_t MAC_TX_FLOW_CTRL_Q[5];             /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
37209        uint8_t RESERVED_3[12];
37210   __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< MAC Rx Flow Control, offset: 0x90 */
37211   __IO uint32_t MAC_RXQ_CTRL4;                     /**< Receive Queue Control 4, offset: 0x94 */
37212   __IO uint32_t MAC_TXQ_PRTY_MAP0;                 /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
37213   __IO uint32_t MAC_TXQ_PRTY_MAP1;                 /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
37214   __IO uint32_t MAC_RXQ_CTRL[4];                   /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
37215   __I  uint32_t MAC_INTERRUPT_STATUS;              /**< Interrupt Status, offset: 0xB0 */
37216   __IO uint32_t MAC_INTERRUPT_ENABLE;              /**< Interrupt Enable, offset: 0xB4 */
37217   __I  uint32_t MAC_RX_TX_STATUS;                  /**< Receive Transmit Status, offset: 0xB8 */
37218        uint8_t RESERVED_4[4];
37219   __IO uint32_t MAC_PMT_CONTROL_STATUS;            /**< PMT Control and Status, offset: 0xC0 */
37220   __IO uint32_t MAC_RWK_PACKET_FILTER;             /**< Remote Wakeup Filter, offset: 0xC4 */
37221        uint8_t RESERVED_5[8];
37222   __IO uint32_t MAC_LPI_CONTROL_STATUS;            /**< LPI Control and Status, offset: 0xD0 */
37223   __IO uint32_t MAC_LPI_TIMERS_CONTROL;            /**< LPI Timers Control, offset: 0xD4 */
37224   __IO uint32_t MAC_LPI_ENTRY_TIMER;               /**< Tx LPI Entry Timer Control, offset: 0xD8 */
37225   __IO uint32_t MAC_ONEUS_TIC_COUNTER;             /**< One-microsecond Reference Timer, offset: 0xDC */
37226        uint8_t RESERVED_6[24];
37227   __IO uint32_t MAC_PHYIF_CONTROL_STATUS;          /**< PHY Interface Control and Status, offset: 0xF8 */
37228        uint8_t RESERVED_7[20];
37229   __I  uint32_t MAC_VERSION;                       /**< MAC Version, offset: 0x110 */
37230   __I  uint32_t MAC_DEBUG;                         /**< MAC Debug, offset: 0x114 */
37231        uint8_t RESERVED_8[4];
37232   __I  uint32_t MAC_HW_FEAT[4];                    /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
37233        uint8_t RESERVED_9[212];
37234   __IO uint32_t MAC_MDIO_ADDRESS;                  /**< MDIO Address, offset: 0x200 */
37235   __IO uint32_t MAC_MDIO_DATA;                     /**< MAC MDIO Data, offset: 0x204 */
37236        uint8_t RESERVED_10[40];
37237   __IO uint32_t MAC_CSR_SW_CTRL;                   /**< CSR Software Control, offset: 0x230 */
37238   __IO uint32_t MAC_FPE_CTRL_STS;                  /**< Frame Preemption Control, offset: 0x234 */
37239        uint8_t RESERVED_11[8];
37240   __I  uint32_t MAC_PRESN_TIME_NS;                 /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
37241   __IO uint32_t MAC_PRESN_TIME_UPDT;               /**< MAC 1722 Presentation Time, offset: 0x244 */
37242        uint8_t RESERVED_12[184];
37243   struct {                                         /* offset: 0x300, array step: 0x8 */
37244     __IO uint32_t HIGH;                              /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
37245     __IO uint32_t LOW;                               /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
37246   } MAC_ADDRESS[64];
37247        uint8_t RESERVED_13[512];
37248   __IO uint32_t MAC_MMC_CONTROL;                   /**< MMC Control, offset: 0x700 */
37249   __I  uint32_t MAC_MMC_RX_INTERRUPT;              /**< MMC Rx Interrupt, offset: 0x704 */
37250   __I  uint32_t MAC_MMC_TX_INTERRUPT;              /**< MMC Tx Interrupt, offset: 0x708 */
37251   __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK;         /**< MMC Rx Interrupt Mask, offset: 0x70C */
37252   __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK;         /**< MMC Tx Interrupt Mask, offset: 0x710 */
37253   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD;       /**< Tx Octet Count Good and Bad, offset: 0x714 */
37254   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD;      /**< Tx Packet Count Good and Bad, offset: 0x718 */
37255   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD;     /**< Tx Broadcast Packets Good, offset: 0x71C */
37256   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD;     /**< Tx Multicast Packets Good, offset: 0x720 */
37257   __I  uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD;  /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
37258   __I  uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
37259   __I  uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
37260   __I  uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
37261   __I  uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
37262   __I  uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
37263   __I  uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD;   /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
37264   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
37265   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
37266   __I  uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS;    /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
37267   __I  uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
37268   __I  uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
37269   __I  uint32_t MAC_TX_DEFERRED_PACKETS;           /**< Deferred Packets Transmitted, offset: 0x754 */
37270   __I  uint32_t MAC_TX_LATE_COLLISION_PACKETS;     /**< Late Collision Packets Transmitted, offset: 0x758 */
37271   __I  uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
37272   __I  uint32_t MAC_TX_CARRIER_ERROR_PACKETS;      /**< Carrier Error Packets Transmitted, offset: 0x760 */
37273   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD;           /**< Bytes Transmitted in Good Packets, offset: 0x764 */
37274   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD;          /**< Good Packets Transmitted, offset: 0x768 */
37275   __I  uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR;   /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
37276   __I  uint32_t MAC_TX_PAUSE_PACKETS;              /**< Pause Packets Transmitted, offset: 0x770 */
37277   __I  uint32_t MAC_TX_VLAN_PACKETS_GOOD;          /**< Good VLAN Packets Transmitted, offset: 0x774 */
37278   __I  uint32_t MAC_TX_OSIZE_PACKETS_GOOD;         /**< Good Oversize Packets Transmitted, offset: 0x778 */
37279        uint8_t RESERVED_14[4];
37280   __I  uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD;     /**< Good and Bad Packets Received, offset: 0x780 */
37281   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD;       /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
37282   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD;           /**< Bytes in Good Packets Received, offset: 0x788 */
37283   __I  uint32_t MAC_RX_BROADCAST_PACKETS_GOOD;     /**< Good Broadcast Packets Received, offset: 0x78C */
37284   __I  uint32_t MAC_RX_MULTICAST_PACKETS_GOOD;     /**< Good Multicast Packets Received, offset: 0x790 */
37285   __I  uint32_t MAC_RX_CRC_ERROR_PACKETS;          /**< CRC Error Packets Received, offset: 0x794 */
37286   __I  uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS;    /**< Alignment Error Packets Received, offset: 0x798 */
37287   __I  uint32_t MAC_RX_RUNT_ERROR_PACKETS;         /**< Runt Error Packets Received, offset: 0x79C */
37288   __I  uint32_t MAC_RX_JABBER_ERROR_PACKETS;       /**< Jabber Error Packets Received, offset: 0x7A0 */
37289   __I  uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD;     /**< Good Undersize Packets Received, offset: 0x7A4 */
37290   __I  uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD;      /**< Good Oversize Packets Received, offset: 0x7A8 */
37291   __I  uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD;  /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
37292   __I  uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
37293   __I  uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
37294   __I  uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
37295   __I  uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
37296   __I  uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
37297   __I  uint32_t MAC_RX_UNICAST_PACKETS_GOOD;       /**< Good Unicast Packets Received, offset: 0x7C4 */
37298   __I  uint32_t MAC_RX_LENGTH_ERROR_PACKETS;       /**< Length Error Packets Received, offset: 0x7C8 */
37299   __I  uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS;  /**< Out-of-range Type Packets Received, offset: 0x7CC */
37300   __I  uint32_t MAC_RX_PAUSE_PACKETS;              /**< Pause Packets Received, offset: 0x7D0 */
37301   __I  uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS;      /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
37302   __I  uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD;      /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
37303   __I  uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS;     /**< Watchdog Error Packets Received, offset: 0x7DC */
37304   __I  uint32_t MAC_RX_RECEIVE_ERROR_PACKETS;      /**< Receive Error Packets Received, offset: 0x7E0 */
37305   __I  uint32_t MAC_RX_CONTROL_PACKETS_GOOD;       /**< Good Control Packets Received, offset: 0x7E4 */
37306        uint8_t RESERVED_15[4];
37307   __I  uint32_t MAC_TX_LPI_USEC_CNTR;              /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
37308   __I  uint32_t MAC_TX_LPI_TRAN_CNTR;              /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
37309   __I  uint32_t MAC_RX_LPI_USEC_CNTR;              /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
37310   __I  uint32_t MAC_RX_LPI_TRAN_CNTR;              /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
37311        uint8_t RESERVED_16[4];
37312   __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK;     /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
37313        uint8_t RESERVED_17[4];
37314   __I  uint32_t MAC_MMC_IPC_RX_INTERRUPT;          /**< MMC IPC Receive Interrupt, offset: 0x808 */
37315        uint8_t RESERVED_18[4];
37316   __I  uint32_t MAC_RXIPV4_GOOD_PACKETS;           /**< Good IPv4 Datagrams Received, offset: 0x810 */
37317   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS;   /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
37318   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS;     /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
37319   __I  uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS;     /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
37320   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
37321   __I  uint32_t MAC_RXIPV6_GOOD_PACKETS;           /**< Good IPv6 Datagrams Received, offset: 0x824 */
37322   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS;   /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
37323   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS;     /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
37324   __I  uint32_t MAC_RXUDP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
37325   __I  uint32_t MAC_RXUDP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
37326   __I  uint32_t MAC_RXTCP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
37327   __I  uint32_t MAC_RXTCP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
37328   __I  uint32_t MAC_RXICMP_GOOD_PACKETS;           /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
37329   __I  uint32_t MAC_RXICMP_ERROR_PACKETS;          /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
37330        uint8_t RESERVED_19[8];
37331   __I  uint32_t MAC_RXIPV4_GOOD_OCTETS;            /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
37332   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
37333   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
37334   __I  uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS;      /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
37335   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
37336   __I  uint32_t MAC_RXIPV6_GOOD_OCTETS;            /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
37337   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
37338   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
37339   __I  uint32_t MAC_RXUDP_GOOD_OCTETS;             /**< Bytes Received in Good UDP Segment, offset: 0x870 */
37340   __I  uint32_t MAC_RXUDP_ERROR_OCTETS;            /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
37341   __I  uint32_t MAC_RXTCP_GOOD_OCTETS;             /**< Bytes Received in Good TCP Segment, offset: 0x878 */
37342   __I  uint32_t MAC_RXTCP_ERROR_OCTETS;            /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
37343   __I  uint32_t MAC_RXICMP_GOOD_OCTETS;            /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
37344   __I  uint32_t MAC_RXICMP_ERROR_OCTETS;           /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
37345        uint8_t RESERVED_20[24];
37346   __I  uint32_t MAC_MMC_FPE_TX_INTERRUPT;          /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
37347   __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK;     /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
37348   __I  uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
37349   __I  uint32_t MAC_MMC_TX_HOLD_REQ_CNTR;          /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
37350        uint8_t RESERVED_21[16];
37351   __I  uint32_t MAC_MMC_FPE_RX_INTERRUPT;          /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
37352   __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK;     /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
37353   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
37354   __I  uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR;    /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
37355   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
37356   __I  uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
37357        uint8_t RESERVED_22[40];
37358   __IO uint32_t MAC_L3_L4_CONTROL0;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
37359   __IO uint32_t MAC_LAYER4_ADDRESS0;               /**< Layer 4 Address 0, offset: 0x904 */
37360        uint8_t RESERVED_23[8];
37361   __IO uint32_t MAC_LAYER3_ADDR0_REG0;             /**< Layer 3 Address 0 Register 0, offset: 0x910 */
37362   __IO uint32_t MAC_LAYER3_ADDR1_REG0;             /**< Layer 3 Address 1 Register 0, offset: 0x914 */
37363   __IO uint32_t MAC_LAYER3_ADDR2_REG0;             /**< Layer 3 Address 2 Register 0, offset: 0x918 */
37364   __IO uint32_t MAC_LAYER3_ADDR3_REG0;             /**< Layer 3 Address 3 Register 0, offset: 0x91C */
37365        uint8_t RESERVED_24[16];
37366   __IO uint32_t MAC_L3_L4_CONTROL1;                /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
37367   __IO uint32_t MAC_LAYER4_ADDRESS1;               /**< Layer 4 Address 0, offset: 0x934 */
37368        uint8_t RESERVED_25[8];
37369   __IO uint32_t MAC_LAYER3_ADDR0_REG1;             /**< Layer 3 Address 0 Register 1, offset: 0x940 */
37370   __IO uint32_t MAC_LAYER3_ADDR1_REG1;             /**< Layer 3 Address 1 Register 1, offset: 0x944 */
37371   __IO uint32_t MAC_LAYER3_ADDR2_REG1;             /**< Layer 3 Address 2 Register 1, offset: 0x948 */
37372   __IO uint32_t MAC_LAYER3_ADDR3_REG1;             /**< Layer 3 Address 3 Register 1, offset: 0x94C */
37373        uint8_t RESERVED_26[16];
37374   __IO uint32_t MAC_L3_L4_CONTROL2;                /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
37375   __IO uint32_t MAC_LAYER4_ADDRESS2;               /**< Layer 4 Address 2, offset: 0x964 */
37376        uint8_t RESERVED_27[8];
37377   __IO uint32_t MAC_LAYER3_ADDR0_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x970 */
37378   __IO uint32_t MAC_LAYER3_ADDR1_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x974 */
37379   __IO uint32_t MAC_LAYER3_ADDR2_REG2;             /**< Layer 3 Address 2 Register 2, offset: 0x978 */
37380   __IO uint32_t MAC_LAYER3_ADDR3_REG2;             /**< Layer 3 Address 3 Register 2, offset: 0x97C */
37381        uint8_t RESERVED_28[16];
37382   __IO uint32_t MAC_L3_L4_CONTROL3;                /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
37383   __IO uint32_t MAC_LAYER4_ADDRESS3;               /**< Layer 4 Address 3, offset: 0x994 */
37384        uint8_t RESERVED_29[8];
37385   __IO uint32_t MAC_LAYER3_ADDR0_REG3;             /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
37386   __IO uint32_t MAC_LAYER3_ADDR1_REG3;             /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
37387   __IO uint32_t MAC_LAYER3_ADDR2_REG3;             /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
37388   __IO uint32_t MAC_LAYER3_ADDR3_REG3;             /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
37389        uint8_t RESERVED_30[16];
37390   __IO uint32_t MAC_L3_L4_CONTROL4;                /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
37391   __IO uint32_t MAC_LAYER4_ADDRESS4;               /**< Layer 4 Address 4, offset: 0x9C4 */
37392        uint8_t RESERVED_31[8];
37393   __IO uint32_t MAC_LAYER3_ADDR0_REG4;             /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
37394   __IO uint32_t MAC_LAYER3_ADDR1_REG4;             /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
37395   __IO uint32_t MAC_LAYER3_ADDR2_REG4;             /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
37396   __IO uint32_t MAC_LAYER3_ADDR3_REG4;             /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
37397        uint8_t RESERVED_32[16];
37398   __IO uint32_t MAC_L3_L4_CONTROL5;                /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
37399   __IO uint32_t MAC_LAYER4_ADDRESS5;               /**< Layer 4 Address 5, offset: 0x9F4 */
37400        uint8_t RESERVED_33[8];
37401   __IO uint32_t MAC_LAYER3_ADDR0_REG5;             /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
37402   __IO uint32_t MAC_LAYER3_ADDR1_REG5;             /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
37403   __IO uint32_t MAC_LAYER3_ADDR2_REG5;             /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
37404   __IO uint32_t MAC_LAYER3_ADDR3_REG5;             /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
37405        uint8_t RESERVED_34[16];
37406   __IO uint32_t MAC_L3_L4_CONTROL6;                /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
37407   __IO uint32_t MAC_LAYER4_ADDRESS6;               /**< Layer 4 Address 6, offset: 0xA24 */
37408        uint8_t RESERVED_35[8];
37409   __IO uint32_t MAC_LAYER3_ADDR0_REG6;             /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
37410   __IO uint32_t MAC_LAYER3_ADDR1_REG6;             /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
37411   __IO uint32_t MAC_LAYER3_ADDR2_REG6;             /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
37412   __IO uint32_t MAC_LAYER3_ADDR3_REG6;             /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
37413        uint8_t RESERVED_36[16];
37414   __IO uint32_t MAC_L3_L4_CONTROL7;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
37415   __IO uint32_t MAC_LAYER4_ADDRESS7;               /**< Layer 4 Address 7, offset: 0xA54 */
37416        uint8_t RESERVED_37[8];
37417   __IO uint32_t MAC_LAYER3_ADDR0_REG7;             /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
37418   __IO uint32_t MAC_LAYER3_ADDR1_REG7;             /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
37419   __IO uint32_t MAC_LAYER3_ADDR2_REG7;             /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
37420   __IO uint32_t MAC_LAYER3_ADDR3_REG7;             /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
37421        uint8_t RESERVED_38[144];
37422   __IO uint32_t MAC_TIMESTAMP_CONTROL;             /**< Timestamp Control, offset: 0xB00 */
37423   __IO uint32_t MAC_SUB_SECOND_INCREMENT;          /**< Subsecond Increment, offset: 0xB04 */
37424   __I  uint32_t MAC_SYSTEM_TIME_SECONDS;           /**< System Time Seconds, offset: 0xB08 */
37425   __I  uint32_t MAC_SYSTEM_TIME_NANOSECONDS;       /**< System Time Nanoseconds, offset: 0xB0C */
37426   __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE;    /**< System Time Seconds Update, offset: 0xB10 */
37427   __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
37428   __IO uint32_t MAC_TIMESTAMP_ADDEND;              /**< Timestamp Addend, offset: 0xB18 */
37429   __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
37430   __I  uint32_t MAC_TIMESTAMP_STATUS;              /**< Timestamp Status, offset: 0xB20 */
37431        uint8_t RESERVED_39[12];
37432   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
37433   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
37434        uint8_t RESERVED_40[8];
37435   __IO uint32_t MAC_AUXILIARY_CONTROL;             /**< Auxiliary Timestamp Control, offset: 0xB40 */
37436        uint8_t RESERVED_41[4];
37437   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
37438   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS;   /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
37439   __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR;   /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
37440   __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR;    /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
37441   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
37442   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
37443   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
37444   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
37445   __I  uint32_t MAC_TIMESTAMP_INGRESS_LATENCY;     /**< Timestamp Ingress Latency, offset: 0xB68 */
37446   __I  uint32_t MAC_TIMESTAMP_EGRESS_LATENCY;      /**< Timestamp Egress Latency, offset: 0xB6C */
37447   __IO uint32_t MAC_PPS_CONTROL;                   /**< PPS Control, offset: 0xB70 */
37448        uint8_t RESERVED_42[12];
37449   __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS;      /**< PPS0 Target Time Seconds, offset: 0xB80 */
37450   __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS;  /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
37451   __IO uint32_t MAC_PPS0_INTERVAL;                 /**< PPS0 Interval, offset: 0xB88 */
37452   __IO uint32_t MAC_PPS0_WIDTH;                    /**< PPS0 Width, offset: 0xB8C */
37453   __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS;      /**< PPS1 Target Time Seconds, offset: 0xB90 */
37454   __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS;  /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
37455   __IO uint32_t MAC_PPS1_INTERVAL;                 /**< PPS1 Interval, offset: 0xB98 */
37456   __IO uint32_t MAC_PPS1_WIDTH;                    /**< PPS1 Width, offset: 0xB9C */
37457   __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS;      /**< PPS2 Target Time Seconds, offset: 0xBA0 */
37458   __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS;  /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
37459   __IO uint32_t MAC_PPS2_INTERVAL;                 /**< PPS2 Interval, offset: 0xBA8 */
37460   __IO uint32_t MAC_PPS2_WIDTH;                    /**< PPS2 Width, offset: 0xBAC */
37461   __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS;      /**< PPS3 Target Time Seconds, offset: 0xBB0 */
37462   __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS;  /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
37463   __IO uint32_t MAC_PPS3_INTERVAL;                 /**< PPS3 Interval, offset: 0xBB8 */
37464   __IO uint32_t MAC_PPS3_WIDTH;                    /**< PPS3 Width, offset: 0xBBC */
37465   __IO uint32_t MAC_PTO_CONTROL;                   /**< PTP Offload Engine Control, offset: 0xBC0 */
37466   __IO uint32_t MAC_SOURCE_PORT_IDENTITY0;         /**< Source Port Identity 0, offset: 0xBC4 */
37467   __IO uint32_t MAC_SOURCE_PORT_IDENTITY1;         /**< Source Port Identity 1, offset: 0xBC8 */
37468   __IO uint32_t MAC_SOURCE_PORT_IDENTITY2;         /**< Source Port Identity 2, offset: 0xBCC */
37469   __IO uint32_t MAC_LOG_MESSAGE_INTERVAL;          /**< Log Message Interval, offset: 0xBD0 */
37470        uint8_t RESERVED_43[44];
37471   __IO uint32_t MTL_OPERATION_MODE;                /**< MTL Operation Mode, offset: 0xC00 */
37472        uint8_t RESERVED_44[4];
37473   __IO uint32_t MTL_DBG_CTL;                       /**< FIFO Debug Access Control and Status, offset: 0xC08 */
37474   __IO uint32_t MTL_DBG_STS;                       /**< FIFO Debug Status, offset: 0xC0C */
37475   __IO uint32_t MTL_FIFO_DEBUG_DATA;               /**< FIFO Debug Data, offset: 0xC10 */
37476        uint8_t RESERVED_45[12];
37477   __I  uint32_t MTL_INTERRUPT_STATUS;              /**< MTL Interrupt Status, offset: 0xC20 */
37478        uint8_t RESERVED_46[12];
37479   __IO uint32_t MTL_RXQ_DMA_MAP0;                  /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
37480   __IO uint32_t MTL_RXQ_DMA_MAP1;                  /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
37481        uint8_t RESERVED_47[8];
37482   __IO uint32_t MTL_TBS_CTRL;                      /**< Time Based Scheduling Control, offset: 0xC40 */
37483        uint8_t RESERVED_48[12];
37484   __IO uint32_t MTL_EST_CONTROL;                   /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
37485        uint8_t RESERVED_49[4];
37486   __IO uint32_t MTL_EST_STATUS;                    /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
37487        uint8_t RESERVED_50[4];
37488   __IO uint32_t MTL_EST_SCH_ERROR;                 /**< EST Scheduling Error, offset: 0xC60 */
37489   __IO uint32_t MTL_EST_FRM_SIZE_ERROR;            /**< EST Frame Size Error, offset: 0xC64 */
37490   __I  uint32_t MTL_EST_FRM_SIZE_CAPTURE;          /**< EST Frame Size Capture, offset: 0xC68 */
37491        uint8_t RESERVED_51[4];
37492   __IO uint32_t MTL_EST_INTR_ENABLE;               /**< EST Interrupt Enable, offset: 0xC70 */
37493        uint8_t RESERVED_52[12];
37494   __IO uint32_t MTL_EST_GCL_CONTROL;               /**< EST GCL Control, offset: 0xC80 */
37495   __IO uint32_t MTL_EST_GCL_DATA;                  /**< EST GCL Data, offset: 0xC84 */
37496        uint8_t RESERVED_53[8];
37497   __IO uint32_t MTL_FPE_CTRL_STS;                  /**< Frame Preemption Control and Status, offset: 0xC90 */
37498   __IO uint32_t MTL_FPE_ADVANCE;                   /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
37499        uint8_t RESERVED_54[8];
37500   __IO uint32_t MTL_RXP_CONTROL_STATUS;            /**< RXP Control Status, offset: 0xCA0 */
37501   __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS;  /**< RXP Interrupt Control Status, offset: 0xCA4 */
37502   __I  uint32_t MTL_RXP_DROP_CNT;                  /**< RXP Drop Count, offset: 0xCA8 */
37503   __I  uint32_t MTL_RXP_ERROR_CNT;                 /**< RXP Error Count, offset: 0xCAC */
37504   __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
37505   __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA;         /**< RXP Indirect Access Data, offset: 0xCB4 */
37506        uint8_t RESERVED_55[72];
37507   struct {                                         /* offset: 0xD00, array step: 0x40 */
37508     __IO uint32_t MTL_TXQX_OP_MODE;                  /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
37509     __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
37510     __I  uint32_t MTL_TXQX_DBG;                      /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
37511          uint8_t RESERVED_0[4];
37512     __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40 */
37513     __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
37514     __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
37515     __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40 */
37516     __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40 */
37517     __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40 */
37518          uint8_t RESERVED_1[4];
37519     __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
37520     __IO uint32_t MTL_RXQX_OP_MODE;                  /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
37521     __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
37522     __I  uint32_t MTL_RXQX_DBG;                      /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
37523     __IO uint32_t MTL_RXQX_CTRL;                     /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
37524   } MTL_QUEUE[5];
37525        uint8_t RESERVED_56[448];
37526   __IO uint32_t DMA_MODE;                          /**< DMA Bus Mode, offset: 0x1000 */
37527   __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus Mode, offset: 0x1004 */
37528   __I  uint32_t DMA_INTERRUPT_STATUS;              /**< DMA Interrupt Status, offset: 0x1008 */
37529   __I  uint32_t DMA_DEBUG_STATUS0;                 /**< DMA Debug Status 0, offset: 0x100C */
37530   __I  uint32_t DMA_DEBUG_STATUS1;                 /**< DMA Debug Status 1, offset: 0x1010 */
37531        uint8_t RESERVED_57[44];
37532   __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL;        /**< AXI LPI Entry Interval Control, offset: 0x1040 */
37533        uint8_t RESERVED_58[12];
37534   __IO uint32_t DMA_TBS_CTRL;                      /**< TBS Control, offset: 0x1050 */
37535        uint8_t RESERVED_59[172];
37536   struct {                                         /* offset: 0x1100, array step: 0x80 */
37537     __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
37538     __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
37539     __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
37540          uint8_t RESERVED_0[8];
37541     __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
37542          uint8_t RESERVED_1[4];
37543     __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
37544     __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
37545          uint8_t RESERVED_2[4];
37546     __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
37547     __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
37548     __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
37549     __IO uint32_t DMA_CHX_INT_EN;                    /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
37550     __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
37551     __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
37552          uint8_t RESERVED_3[4];
37553     __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
37554          uint8_t RESERVED_4[4];
37555     __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
37556          uint8_t RESERVED_5[4];
37557     __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
37558          uint8_t RESERVED_6[4];
37559     __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
37560     __IO uint32_t DMA_CHX_STAT;                      /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
37561     __I  uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
37562     __I  uint32_t DMA_CHX_RXP_ACCEPT_CNT;            /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
37563     __I  uint32_t DMA_CHX_RX_ERI_CNT;                /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
37564          uint8_t RESERVED_7[16];
37565   } DMA_CH[5];
37566 } ENET_QOS_Type;
37567 
37568 /* ----------------------------------------------------------------------------
37569    -- ENET_QOS Register Masks
37570    ---------------------------------------------------------------------------- */
37571 
37572 /*!
37573  * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
37574  * @{
37575  */
37576 
37577 /*! @name MAC_CONFIGURATION - MAC Configuration Register */
37578 /*! @{ */
37579 
37580 #define ENET_QOS_MAC_CONFIGURATION_RE_MASK       (0x1U)
37581 #define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT      (0U)
37582 /*! RE - Receiver Enable
37583  *  0b0..Receiver is disabled
37584  *  0b1..Receiver is enabled
37585  */
37586 #define ENET_QOS_MAC_CONFIGURATION_RE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
37587 
37588 #define ENET_QOS_MAC_CONFIGURATION_TE_MASK       (0x2U)
37589 #define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT      (1U)
37590 /*! TE - Transmitter Enable
37591  *  0b0..Transmitter is disabled
37592  *  0b1..Transmitter is enabled
37593  */
37594 #define ENET_QOS_MAC_CONFIGURATION_TE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
37595 
37596 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK   (0xCU)
37597 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT  (2U)
37598 /*! PRELEN - Preamble Length for Transmit packets
37599  *  0b10..3 bytes of preamble
37600  *  0b01..5 bytes of preamble
37601  *  0b00..7 bytes of preamble
37602  *  0b11..Reserved
37603  */
37604 #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
37605 
37606 #define ENET_QOS_MAC_CONFIGURATION_DC_MASK       (0x10U)
37607 #define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT      (4U)
37608 /*! DC - Deferral Check
37609  *  0b0..Deferral check function is disabled
37610  *  0b1..Deferral check function is enabled
37611  */
37612 #define ENET_QOS_MAC_CONFIGURATION_DC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
37613 
37614 #define ENET_QOS_MAC_CONFIGURATION_BL_MASK       (0x60U)
37615 #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT      (5U)
37616 /*! BL - Back-Off Limit
37617  *  0b11..k = min(n,1)
37618  *  0b00..k = min(n,10)
37619  *  0b10..k = min(n,4)
37620  *  0b01..k = min(n,8)
37621  */
37622 #define ENET_QOS_MAC_CONFIGURATION_BL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
37623 
37624 #define ENET_QOS_MAC_CONFIGURATION_DR_MASK       (0x100U)
37625 #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT      (8U)
37626 /*! DR - Disable Retry
37627  *  0b1..Disable Retry
37628  *  0b0..Enable Retry
37629  */
37630 #define ENET_QOS_MAC_CONFIGURATION_DR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
37631 
37632 #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK     (0x200U)
37633 #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT    (9U)
37634 /*! DCRS - Disable Carrier Sense During Transmission
37635  *  0b1..Disable Carrier Sense During Transmission
37636  *  0b0..Enable Carrier Sense During Transmission
37637  */
37638 #define ENET_QOS_MAC_CONFIGURATION_DCRS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
37639 
37640 #define ENET_QOS_MAC_CONFIGURATION_DO_MASK       (0x400U)
37641 #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT      (10U)
37642 /*! DO - Disable Receive Own
37643  *  0b1..Disable Receive Own
37644  *  0b0..Enable Receive Own
37645  */
37646 #define ENET_QOS_MAC_CONFIGURATION_DO(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
37647 
37648 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK   (0x800U)
37649 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT  (11U)
37650 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
37651  *  0b0..ECRSFD is disabled
37652  *  0b1..ECRSFD is enabled
37653  */
37654 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
37655 
37656 #define ENET_QOS_MAC_CONFIGURATION_LM_MASK       (0x1000U)
37657 #define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT      (12U)
37658 /*! LM - Loopback Mode
37659  *  0b0..Loopback is disabled
37660  *  0b1..Loopback is enabled
37661  */
37662 #define ENET_QOS_MAC_CONFIGURATION_LM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
37663 
37664 #define ENET_QOS_MAC_CONFIGURATION_DM_MASK       (0x2000U)
37665 #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT      (13U)
37666 /*! DM - Duplex Mode
37667  *  0b1..Full-duplex mode
37668  *  0b0..Half-duplex mode
37669  */
37670 #define ENET_QOS_MAC_CONFIGURATION_DM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
37671 
37672 #define ENET_QOS_MAC_CONFIGURATION_FES_MASK      (0x4000U)
37673 #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT     (14U)
37674 /*! FES - Speed
37675  *  0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
37676  *  0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
37677  */
37678 #define ENET_QOS_MAC_CONFIGURATION_FES(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
37679 
37680 #define ENET_QOS_MAC_CONFIGURATION_PS_MASK       (0x8000U)
37681 #define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT      (15U)
37682 /*! PS - Port Select
37683  *  0b0..For 1000 or 2500 Mbps operations
37684  *  0b1..For 10 or 100 Mbps operations
37685  */
37686 #define ENET_QOS_MAC_CONFIGURATION_PS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
37687 
37688 #define ENET_QOS_MAC_CONFIGURATION_JE_MASK       (0x10000U)
37689 #define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT      (16U)
37690 /*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
37691  *    (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
37692  *    status.
37693  *  0b0..Jumbo packet is disabled
37694  *  0b1..Jumbo packet is enabled
37695  */
37696 #define ENET_QOS_MAC_CONFIGURATION_JE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
37697 
37698 #define ENET_QOS_MAC_CONFIGURATION_JD_MASK       (0x20000U)
37699 #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT      (17U)
37700 /*! JD - Jabber Disable
37701  *  0b1..Jabber is disabled
37702  *  0b0..Jabber is enabled
37703  */
37704 #define ENET_QOS_MAC_CONFIGURATION_JD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
37705 
37706 #define ENET_QOS_MAC_CONFIGURATION_BE_MASK       (0x40000U)
37707 #define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT      (18U)
37708 /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
37709  *    transmission in the GMII half-duplex mode.
37710  *  0b0..Packet Burst is disabled
37711  *  0b1..Packet Burst is enabled
37712  */
37713 #define ENET_QOS_MAC_CONFIGURATION_BE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
37714 
37715 #define ENET_QOS_MAC_CONFIGURATION_WD_MASK       (0x80000U)
37716 #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT      (19U)
37717 /*! WD - Watchdog Disable
37718  *  0b1..Watchdog is disabled
37719  *  0b0..Watchdog is enabled
37720  */
37721 #define ENET_QOS_MAC_CONFIGURATION_WD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
37722 
37723 #define ENET_QOS_MAC_CONFIGURATION_ACS_MASK      (0x100000U)
37724 #define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT     (20U)
37725 /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
37726  *    on the incoming packets only if the value of the length field is less than 1,536 bytes.
37727  *  0b0..Automatic Pad or CRC Stripping is disabled
37728  *  0b1..Automatic Pad or CRC Stripping is enabled
37729  */
37730 #define ENET_QOS_MAC_CONFIGURATION_ACS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
37731 
37732 #define ENET_QOS_MAC_CONFIGURATION_CST_MASK      (0x200000U)
37733 #define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT     (21U)
37734 /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
37735  *    packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
37736  *    the packet to the application.
37737  *  0b0..CRC stripping for Type packets is disabled
37738  *  0b1..CRC stripping for Type packets is enabled
37739  */
37740 #define ENET_QOS_MAC_CONFIGURATION_CST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
37741 
37742 #define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK     (0x400000U)
37743 #define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT    (22U)
37744 /*! S2KP - IEEE 802.
37745  *  0b0..Support upto 2K packet is disabled
37746  *  0b1..Support upto 2K packet is Enabled
37747  */
37748 #define ENET_QOS_MAC_CONFIGURATION_S2KP(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
37749 
37750 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK   (0x800000U)
37751 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT  (23U)
37752 /*! GPSLCE - Giant Packet Size Limit Control Enable
37753  *  0b0..Giant Packet Size Limit Control is disabled
37754  *  0b1..Giant Packet Size Limit Control is enabled
37755  */
37756 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
37757 
37758 #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK      (0x7000000U)
37759 #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT     (24U)
37760 /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
37761  *  0b111..40 bit times IPG
37762  *  0b110..48 bit times IPG
37763  *  0b101..56 bit times IPG
37764  *  0b100..64 bit times IPG
37765  *  0b011..72 bit times IPG
37766  *  0b010..80 bit times IPG
37767  *  0b001..88 bit times IPG
37768  *  0b000..96 bit times IPG
37769  */
37770 #define ENET_QOS_MAC_CONFIGURATION_IPG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
37771 
37772 #define ENET_QOS_MAC_CONFIGURATION_IPC_MASK      (0x8000000U)
37773 #define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT     (27U)
37774 /*! IPC - Checksum Offload
37775  *  0b0..IP header/payload checksum checking is disabled
37776  *  0b1..IP header/payload checksum checking is enabled
37777  */
37778 #define ENET_QOS_MAC_CONFIGURATION_IPC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
37779 
37780 #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK     (0x70000000U)
37781 #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT    (28U)
37782 /*! SARC - Source Address Insertion or Replacement Control
37783  *  0b010..Contents of MAC Addr-0 inserted in SA field
37784  *  0b011..Contents of MAC Addr-0 replaces SA field
37785  *  0b110..Contents of MAC Addr-1 inserted in SA field
37786  *  0b111..Contents of MAC Addr-1 replaces SA field
37787  *  0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
37788  */
37789 #define ENET_QOS_MAC_CONFIGURATION_SARC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
37790 /*! @} */
37791 
37792 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
37793 /*! @{ */
37794 
37795 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
37796 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
37797 /*! GPSL - Giant Packet Size Limit
37798  */
37799 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
37800 
37801 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
37802 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
37803 /*! DCRCC - Disable CRC Checking for Received Packets
37804  *  0b1..CRC Checking is disabled
37805  *  0b0..CRC Checking is enabled
37806  */
37807 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
37808 
37809 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
37810 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
37811 /*! SPEN - Slow Protocol Detection Enable
37812  *  0b0..Slow Protocol Detection is disabled
37813  *  0b1..Slow Protocol Detection is enabled
37814  */
37815 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
37816 
37817 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK  (0x40000U)
37818 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
37819 /*! USP - Unicast Slow Protocol Packet Detect
37820  *  0b0..Unicast Slow Protocol Packet Detection is disabled
37821  *  0b1..Unicast Slow Protocol Packet Detection is enabled
37822  */
37823 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
37824 
37825 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK  (0x80000U)
37826 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
37827 /*! PDC - Packet Duplication Control
37828  *  0b0..Packet Duplication Control is disabled
37829  *  0b1..Packet Duplication Control is enabled
37830  */
37831 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
37832 
37833 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
37834 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
37835 /*! EIPGEN - Extended Inter-Packet Gap Enable
37836  *  0b0..Extended Inter-Packet Gap is disabled
37837  *  0b1..Extended Inter-Packet Gap is enabled
37838  */
37839 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
37840 
37841 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
37842 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
37843 /*! EIPG - Extended Inter-Packet Gap
37844  */
37845 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
37846 /*! @} */
37847 
37848 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */
37849 /*! @{ */
37850 
37851 #define ENET_QOS_MAC_PACKET_FILTER_PR_MASK       (0x1U)
37852 #define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT      (0U)
37853 /*! PR - Promiscuous Mode
37854  *  0b0..Promiscuous Mode is disabled
37855  *  0b1..Promiscuous Mode is enabled
37856  */
37857 #define ENET_QOS_MAC_PACKET_FILTER_PR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
37858 
37859 #define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK      (0x2U)
37860 #define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT     (1U)
37861 /*! HUC - Hash Unicast
37862  *  0b0..Hash Unicast is disabled
37863  *  0b1..Hash Unicast is enabled
37864  */
37865 #define ENET_QOS_MAC_PACKET_FILTER_HUC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
37866 
37867 #define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK      (0x4U)
37868 #define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT     (2U)
37869 /*! HMC - Hash Multicast
37870  *  0b0..Hash Multicast is disabled
37871  *  0b1..Hash Multicast is enabled
37872  */
37873 #define ENET_QOS_MAC_PACKET_FILTER_HMC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
37874 
37875 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK     (0x8U)
37876 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT    (3U)
37877 /*! DAIF - DA Inverse Filtering
37878  *  0b0..DA Inverse Filtering is disabled
37879  *  0b1..DA Inverse Filtering is enabled
37880  */
37881 #define ENET_QOS_MAC_PACKET_FILTER_DAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
37882 
37883 #define ENET_QOS_MAC_PACKET_FILTER_PM_MASK       (0x10U)
37884 #define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT      (4U)
37885 /*! PM - Pass All Multicast
37886  *  0b0..Pass All Multicast is disabled
37887  *  0b1..Pass All Multicast is enabled
37888  */
37889 #define ENET_QOS_MAC_PACKET_FILTER_PM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
37890 
37891 #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK      (0x20U)
37892 #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT     (5U)
37893 /*! DBF - Disable Broadcast Packets
37894  *  0b1..Disable Broadcast Packets
37895  *  0b0..Enable Broadcast Packets
37896  */
37897 #define ENET_QOS_MAC_PACKET_FILTER_DBF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
37898 
37899 #define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK      (0xC0U)
37900 #define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT     (6U)
37901 /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
37902  *    unicast and multicast Pause packets).
37903  *  0b00..MAC filters all control packets from reaching the application
37904  *  0b10..MAC forwards all control packets to the application even if they fail the Address filter
37905  *  0b11..MAC forwards the control packets that pass the Address filter
37906  *  0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
37907  */
37908 #define ENET_QOS_MAC_PACKET_FILTER_PCF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
37909 
37910 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK     (0x100U)
37911 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT    (8U)
37912 /*! SAIF - SA Inverse Filtering
37913  *  0b0..SA Inverse Filtering is disabled
37914  *  0b1..SA Inverse Filtering is enabled
37915  */
37916 #define ENET_QOS_MAC_PACKET_FILTER_SAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
37917 
37918 #define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK      (0x200U)
37919 #define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT     (9U)
37920 /*! SAF - Source Address Filter Enable
37921  *  0b0..SA Filtering is disabled
37922  *  0b1..SA Filtering is enabled
37923  */
37924 #define ENET_QOS_MAC_PACKET_FILTER_SAF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
37925 
37926 #define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK      (0x400U)
37927 #define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT     (10U)
37928 /*! HPF - Hash or Perfect Filter
37929  *  0b0..Hash or Perfect Filter is disabled
37930  *  0b1..Hash or Perfect Filter is enabled
37931  */
37932 #define ENET_QOS_MAC_PACKET_FILTER_HPF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
37933 
37934 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK     (0x10000U)
37935 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT    (16U)
37936 /*! VTFE - VLAN Tag Filter Enable
37937  *  0b0..VLAN Tag Filter is disabled
37938  *  0b1..VLAN Tag Filter is enabled
37939  */
37940 #define ENET_QOS_MAC_PACKET_FILTER_VTFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
37941 
37942 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK     (0x100000U)
37943 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT    (20U)
37944 /*! IPFE - Layer 3 and Layer 4 Filter Enable
37945  *  0b0..Layer 3 and Layer 4 Filters are disabled
37946  *  0b1..Layer 3 and Layer 4 Filters are enabled
37947  */
37948 #define ENET_QOS_MAC_PACKET_FILTER_IPFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
37949 
37950 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK     (0x200000U)
37951 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT    (21U)
37952 /*! DNTU - Drop Non-TCP/UDP over IP Packets
37953  *  0b1..Drop Non-TCP/UDP over IP Packets
37954  *  0b0..Forward Non-TCP/UDP over IP Packets
37955  */
37956 #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
37957 
37958 #define ENET_QOS_MAC_PACKET_FILTER_RA_MASK       (0x80000000U)
37959 #define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT      (31U)
37960 /*! RA - Receive All
37961  *  0b0..Receive All is disabled
37962  *  0b1..Receive All is enabled
37963  */
37964 #define ENET_QOS_MAC_PACKET_FILTER_RA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
37965 /*! @} */
37966 
37967 /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
37968 /*! @{ */
37969 
37970 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK   (0xFU)
37971 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT  (0U)
37972 /*! WTO - Watchdog Timeout
37973  *  0b1000..10 KB
37974  *  0b1001..11 KB
37975  *  0b1010..12 KB
37976  *  0b1011..13 KB
37977  *  0b1100..14 KB
37978  *  0b1101..15 KB
37979  *  0b1110..16383 Bytes
37980  *  0b0000..2 KB
37981  *  0b0001..3 KB
37982  *  0b0010..4 KB
37983  *  0b0011..5 KB
37984  *  0b0100..6 KB
37985  *  0b0101..7 KB
37986  *  0b0110..8 KB
37987  *  0b0111..9 KB
37988  *  0b1111..Reserved
37989  */
37990 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
37991 
37992 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK   (0x100U)
37993 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT  (8U)
37994 /*! PWE - Programmable Watchdog Enable
37995  *  0b0..Programmable Watchdog is disabled
37996  *  0b1..Programmable Watchdog is enabled
37997  */
37998 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
37999 /*! @} */
38000 
38001 /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
38002 /*! @{ */
38003 
38004 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
38005 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
38006 /*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table.
38007  */
38008 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
38009 /*! @} */
38010 
38011 /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
38012 /*! @{ */
38013 
38014 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
38015 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
38016 /*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table.
38017  */
38018 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
38019 /*! @} */
38020 
38021 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
38022 /*! @{ */
38023 
38024 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK       (0x1U)
38025 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT      (0U)
38026 /*! OB - Operation Busy
38027  *  0b0..Operation Busy is disabled
38028  *  0b1..Operation Busy is enabled
38029  */
38030 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
38031 
38032 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK       (0x2U)
38033 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT      (1U)
38034 /*! CT - Command Type
38035  *  0b1..Read operation
38036  *  0b0..Write operation
38037  */
38038 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
38039 
38040 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK      (0x7CU)
38041 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT     (2U)
38042 /*! OFS - Offset
38043  */
38044 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
38045 
38046 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK     (0x20000U)
38047 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT    (17U)
38048 /*! VTIM - VLAN Tag Inverse Match Enable
38049  *  0b0..VLAN Tag Inverse Match is disabled
38050  *  0b1..VLAN Tag Inverse Match is enabled
38051  */
38052 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
38053 
38054 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK     (0x40000U)
38055 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT    (18U)
38056 /*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
38057  *    packets (Type = 0x88A8) as valid VLAN tagged packets.
38058  *  0b0..S-VLAN is disabled
38059  *  0b1..S-VLAN is enabled
38060  */
38061 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
38062 
38063 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK     (0x600000U)
38064 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT    (21U)
38065 /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
38066  *    outer VLAN Tag in received packet.
38067  *  0b11..Always strip
38068  *  0b00..Do not strip
38069  *  0b10..Strip if VLAN filter fails
38070  *  0b01..Strip if VLAN filter passes
38071  */
38072 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
38073 
38074 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK   (0x1000000U)
38075 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT  (24U)
38076 /*! EVLRXS - Enable VLAN Tag in Rx status
38077  *  0b0..VLAN Tag in Rx status is disabled
38078  *  0b1..VLAN Tag in Rx status is enabled
38079  */
38080 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
38081 
38082 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK     (0x2000000U)
38083 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT    (25U)
38084 /*! VTHM - VLAN Tag Hash Table Match Enable
38085  *  0b0..VLAN Tag Hash Table Match is disabled
38086  *  0b1..VLAN Tag Hash Table Match is enabled
38087  */
38088 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
38089 
38090 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK    (0x4000000U)
38091 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT   (26U)
38092 /*! EDVLP - Enable Double VLAN Processing
38093  *  0b0..Double VLAN Processing is disabled
38094  *  0b1..Double VLAN Processing is enabled
38095  */
38096 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
38097 
38098 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK   (0x8000000U)
38099 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT  (27U)
38100 /*! ERIVLT - ERIVLT
38101  *  0b0..Inner VLAN tag is disabled
38102  *  0b1..Inner VLAN tag is enabled
38103  */
38104 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
38105 
38106 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK    (0x30000000U)
38107 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT   (28U)
38108 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
38109  *    on inner VLAN Tag in received packet.
38110  *  0b11..Always strip
38111  *  0b00..Do not strip
38112  *  0b10..Strip if VLAN filter fails
38113  *  0b01..Strip if VLAN filter passes
38114  */
38115 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
38116 
38117 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK  (0x80000000U)
38118 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
38119 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
38120  *  0b0..Inner VLAN Tag in Rx status is disabled
38121  *  0b1..Inner VLAN Tag in Rx status is enabled
38122  */
38123 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
38124 /*! @} */
38125 
38126 /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
38127 /*! @{ */
38128 
38129 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK      (0xFFFFU)
38130 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT     (0U)
38131 /*! VID - VLAN Tag ID
38132  */
38133 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
38134 
38135 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK      (0x10000U)
38136 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT     (16U)
38137 /*! VEN - VLAN Tag Enable
38138  *  0b0..VLAN Tag is disabled
38139  *  0b1..VLAN Tag is enabled
38140  */
38141 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
38142 
38143 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK      (0x20000U)
38144 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT     (17U)
38145 /*! ETV - 12bits or 16bits VLAN comparison
38146  *  0b1..12 bit VLAN comparison
38147  *  0b0..16 bit VLAN comparison
38148  */
38149 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
38150 
38151 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK   (0x40000U)
38152 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT  (18U)
38153 /*! DOVLTC - Disable VLAN Type Comparison
38154  *  0b1..VLAN type comparison is disabled
38155  *  0b0..VLAN type comparison is enabled
38156  */
38157 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
38158 
38159 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK   (0x80000U)
38160 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT  (19U)
38161 /*! ERSVLM - Enable S-VLAN Match for received Frames
38162  *  0b0..Receive S-VLAN Match is disabled
38163  *  0b1..Receive S-VLAN Match is enabled
38164  */
38165 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
38166 
38167 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK   (0x100000U)
38168 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT  (20U)
38169 /*! ERIVLT - Enable Inner VLAN Tag Comparison
38170  *  0b0..Inner VLAN tag comparison is disabled
38171  *  0b1..Inner VLAN tag comparison is enabled
38172  */
38173 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
38174 
38175 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK  (0x1000000U)
38176 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
38177 /*! DMACHEN - DMA Channel Number Enable
38178  *  0b0..DMA Channel Number is disabled
38179  *  0b1..DMA Channel Number is enabled
38180  */
38181 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
38182 
38183 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK   (0xE000000U)
38184 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT  (25U)
38185 /*! DMACHN - DMA Channel Number
38186  */
38187 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
38188 /*! @} */
38189 
38190 /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
38191 /*! @{ */
38192 
38193 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK   (0xFFFFU)
38194 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT  (0U)
38195 /*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table.
38196  */
38197 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
38198 /*! @} */
38199 
38200 /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
38201 /*! @{ */
38202 
38203 #define ENET_QOS_MAC_VLAN_INCL_VLT_MASK          (0xFFFFU)
38204 #define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT         (0U)
38205 /*! VLT - VLAN Tag for Transmit Packets
38206  */
38207 #define ENET_QOS_MAC_VLAN_INCL_VLT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
38208 
38209 #define ENET_QOS_MAC_VLAN_INCL_VLC_MASK          (0x30000U)
38210 #define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT         (16U)
38211 /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
38212  *    replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
38213  *    (bytes 15 and 16) of all transmitted packets with VLAN tags.
38214  *  0b01..VLAN tag deletion
38215  *  0b10..VLAN tag insertion
38216  *  0b00..No VLAN tag deletion, insertion, or replacement
38217  *  0b11..VLAN tag replacement
38218  */
38219 #define ENET_QOS_MAC_VLAN_INCL_VLC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
38220 
38221 #define ENET_QOS_MAC_VLAN_INCL_VLP_MASK          (0x40000U)
38222 #define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT         (18U)
38223 /*! VLP - VLAN Priority Control
38224  *  0b0..VLAN Priority Control is disabled
38225  *  0b1..VLAN Priority Control is enabled
38226  */
38227 #define ENET_QOS_MAC_VLAN_INCL_VLP(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
38228 
38229 #define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK         (0x80000U)
38230 #define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT        (19U)
38231 /*! CSVL - C-VLAN or S-VLAN
38232  *  0b0..C-VLAN type (0x8100) is inserted or replaced
38233  *  0b1..S-VLAN type (0x88A8) is inserted or replaced
38234  */
38235 #define ENET_QOS_MAC_VLAN_INCL_CSVL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
38236 
38237 #define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK         (0x100000U)
38238 #define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT        (20U)
38239 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
38240  *    replaced in Tx packet should be taken from: - The Tx descriptor
38241  *  0b0..VLAN Tag Input is disabled
38242  *  0b1..VLAN Tag Input is enabled
38243  */
38244 #define ENET_QOS_MAC_VLAN_INCL_VLTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
38245 
38246 #define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK         (0x200000U)
38247 #define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT        (21U)
38248 /*! CBTI - Channel based tag insertion
38249  *  0b0..Channel based tag insertion is disabled
38250  *  0b1..Channel based tag insertion is enabled
38251  */
38252 #define ENET_QOS_MAC_VLAN_INCL_CBTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
38253 
38254 #define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK         (0x7000000U)
38255 #define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT        (24U)
38256 /*! ADDR - Address
38257  */
38258 #define ENET_QOS_MAC_VLAN_INCL_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
38259 
38260 #define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK         (0x40000000U)
38261 #define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT        (30U)
38262 /*! RDWR - Read write control
38263  *  0b0..Read operation of indirect access
38264  *  0b1..Write operation of indirect access
38265  */
38266 #define ENET_QOS_MAC_VLAN_INCL_RDWR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
38267 
38268 #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK         (0x80000000U)
38269 #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT        (31U)
38270 /*! BUSY - Busy
38271  *  0b1..Busy status detected
38272  *  0b0..Busy status not detected
38273  */
38274 #define ENET_QOS_MAC_VLAN_INCL_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
38275 /*! @} */
38276 
38277 /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
38278 /*! @{ */
38279 
38280 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK    (0xFFFFU)
38281 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT   (0U)
38282 /*! VLT - VLAN Tag for Transmit Packets
38283  */
38284 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
38285 
38286 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK    (0x30000U)
38287 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT   (16U)
38288 /*! VLC - VLAN Tag Control in Transmit Packets
38289  *  0b01..VLAN tag deletion
38290  *  0b10..VLAN tag insertion
38291  *  0b00..No VLAN tag deletion, insertion, or replacement
38292  *  0b11..VLAN tag replacement
38293  */
38294 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
38295 
38296 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK    (0x40000U)
38297 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT   (18U)
38298 /*! VLP - VLAN Priority Control
38299  *  0b0..VLAN Priority Control is disabled
38300  *  0b1..VLAN Priority Control is enabled
38301  */
38302 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
38303 
38304 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK   (0x80000U)
38305 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT  (19U)
38306 /*! CSVL - C-VLAN or S-VLAN
38307  *  0b0..C-VLAN type (0x8100) is inserted
38308  *  0b1..S-VLAN type (0x88A8) is inserted
38309  */
38310 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
38311 
38312 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK   (0x100000U)
38313 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT  (20U)
38314 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
38315  *    replaced in Tx packet should be taken from: - The Tx descriptor
38316  *  0b0..VLAN Tag Input is disabled
38317  *  0b1..VLAN Tag Input is enabled
38318  */
38319 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
38320 /*! @} */
38321 
38322 /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
38323 /*! @{ */
38324 
38325 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
38326 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
38327 /*! FCB_BPA - Flow Control Busy or Backpressure Activate
38328  *  0b0..Flow Control Busy or Backpressure Activate is disabled
38329  *  0b1..Flow Control Busy or Backpressure Activate is enabled
38330  */
38331 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
38332 
38333 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK     (0x2U)
38334 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT    (1U)
38335 /*! TFE - Transmit Flow Control Enable
38336  *  0b0..Transmit Flow Control is disabled
38337  *  0b1..Transmit Flow Control is enabled
38338  */
38339 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
38340 
38341 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK     (0x70U)
38342 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT    (4U)
38343 /*! PLT - Pause Low Threshold
38344  *  0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
38345  *  0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
38346  *  0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
38347  *  0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
38348  *  0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
38349  *  0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
38350  *  0b110..Reserved
38351  */
38352 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
38353 
38354 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK    (0x80U)
38355 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT   (7U)
38356 /*! DZPQ - Disable Zero-Quanta Pause
38357  *  0b1..Zero-Quanta Pause packet generation is disabled
38358  *  0b0..Zero-Quanta Pause packet generation is enabled
38359  */
38360 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
38361 
38362 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK      (0xFFFF0000U)
38363 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT     (16U)
38364 /*! PT - Pause Time
38365  */
38366 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
38367 /*! @} */
38368 
38369 /* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
38370 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT        (5U)
38371 
38372 /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
38373 /*! @{ */
38374 
38375 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK       (0x1U)
38376 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT      (0U)
38377 /*! RFE - Receive Flow Control Enable
38378  *  0b0..Receive Flow Control is disabled
38379  *  0b1..Receive Flow Control is enabled
38380  */
38381 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
38382 
38383 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK        (0x2U)
38384 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT       (1U)
38385 /*! UP - Unicast Pause Packet Detect
38386  *  0b0..Unicast Pause Packet Detect disabled
38387  *  0b1..Unicast Pause Packet Detect enabled
38388  */
38389 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
38390 
38391 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK      (0x100U)
38392 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT     (8U)
38393 /*! PFCE - Priority Based Flow Control Enable
38394  *  0b0..Priority Based Flow Control is disabled
38395  *  0b1..Priority Based Flow Control is enabled
38396  */
38397 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
38398 /*! @} */
38399 
38400 /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
38401 /*! @{ */
38402 
38403 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK        (0x1U)
38404 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT       (0U)
38405 /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
38406  *  0b0..Unicast Address Filter Fail Packets Queuing is disabled
38407  *  0b1..Unicast Address Filter Fail Packets Queuing is enabled
38408  */
38409 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
38410 
38411 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK         (0xEU)
38412 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT        (1U)
38413 /*! UFFQ - Unicast Address Filter Fail Packets Queue.
38414  */
38415 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
38416 
38417 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK        (0x100U)
38418 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT       (8U)
38419 /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
38420  *  0b0..Multicast Address Filter Fail Packets Queuing is disabled
38421  *  0b1..Multicast Address Filter Fail Packets Queuing is enabled
38422  */
38423 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
38424 
38425 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK         (0xE00U)
38426 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT        (9U)
38427 /*! MFFQ - Multicast Address Filter Fail Packets Queue.
38428  */
38429 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
38430 
38431 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK        (0x10000U)
38432 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT       (16U)
38433 /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
38434  *  0b0..VLAN tag Filter Fail Packets Queuing is disabled
38435  *  0b1..VLAN tag Filter Fail Packets Queuing is enabled
38436  */
38437 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
38438 
38439 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK         (0xE0000U)
38440 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT        (17U)
38441 /*! VFFQ - VLAN Tag Filter Fail Packets Queue
38442  */
38443 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
38444 /*! @} */
38445 
38446 /*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
38447 /*! @{ */
38448 
38449 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK    (0xFFU)
38450 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT   (0U)
38451 /*! PSTQ0 - Priorities Selected in Transmit Queue 0
38452  */
38453 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
38454 
38455 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK    (0xFF00U)
38456 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT   (8U)
38457 /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
38458  */
38459 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
38460 
38461 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK    (0xFF0000U)
38462 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT   (16U)
38463 /*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit.
38464  */
38465 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
38466 
38467 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK    (0xFF000000U)
38468 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT   (24U)
38469 /*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit.
38470  */
38471 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
38472 /*! @} */
38473 
38474 /*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
38475 /*! @{ */
38476 
38477 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK    (0xFFU)
38478 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT   (0U)
38479 /*! PSTQ4 - Priorities Selected in Transmit Queue 4
38480  */
38481 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
38482 /*! @} */
38483 
38484 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
38485 /*! @{ */
38486 
38487 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK         (0x7U)
38488 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT        (0U)
38489 /*! AVCPQ - AV Untagged Control Packets Queue
38490  *  0b000..Receive Queue 0
38491  *  0b001..Receive Queue 1
38492  *  0b010..Receive Queue 2
38493  *  0b011..Receive Queue 3
38494  *  0b100..Receive Queue 4
38495  *  0b101..Reserved
38496  *  0b110..Reserved
38497  *  0b111..Reserved
38498  */
38499 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
38500 
38501 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK         (0xFFU)
38502 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT        (0U)
38503 /*! PSRQ0 - Priorities Selected in the Receive Queue 0
38504  */
38505 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
38506 
38507 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK         (0xFFU)
38508 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT        (0U)
38509 /*! PSRQ4 - Priorities Selected in the Receive Queue 4
38510  */
38511 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
38512 
38513 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK        (0x3U)
38514 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT       (0U)
38515 /*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
38516  *  0b00..Queue not enabled
38517  *  0b01..Queue enabled for AV
38518  *  0b10..Queue enabled for DCB/Generic
38519  *  0b11..Reserved
38520  */
38521 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
38522 
38523 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK        (0xCU)
38524 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT       (2U)
38525 /*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
38526  *  0b00..Queue not enabled
38527  *  0b01..Queue enabled for AV
38528  *  0b10..Queue enabled for DCB/Generic
38529  *  0b11..Reserved
38530  */
38531 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
38532 
38533 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK          (0x70U)
38534 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT         (4U)
38535 /*! PTPQ - PTP Packets Queue
38536  *  0b000..Receive Queue 0
38537  *  0b001..Receive Queue 1
38538  *  0b010..Receive Queue 2
38539  *  0b011..Receive Queue 3
38540  *  0b100..Receive Queue 4
38541  *  0b101..Reserved
38542  *  0b110..Reserved
38543  *  0b111..Reserved
38544  */
38545 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
38546 
38547 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK        (0x30U)
38548 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT       (4U)
38549 /*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
38550  *  0b00..Queue not enabled
38551  *  0b01..Queue enabled for AV
38552  *  0b10..Queue enabled for DCB/Generic
38553  *  0b11..Reserved
38554  */
38555 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
38556 
38557 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK        (0xC0U)
38558 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT       (6U)
38559 /*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
38560  *  0b00..Queue not enabled
38561  *  0b01..Queue enabled for AV
38562  *  0b10..Queue enabled for DCB/Generic
38563  *  0b11..Reserved
38564  */
38565 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
38566 
38567 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK        (0x700U)
38568 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT       (8U)
38569 /*! DCBCPQ - DCB Control Packets Queue
38570  *  0b000..Receive Queue 0
38571  *  0b001..Receive Queue 1
38572  *  0b010..Receive Queue 2
38573  *  0b011..Receive Queue 3
38574  *  0b100..Receive Queue 4
38575  *  0b101..Reserved
38576  *  0b110..Reserved
38577  *  0b111..Reserved
38578  */
38579 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
38580 
38581 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK         (0xFF00U)
38582 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT        (8U)
38583 /*! PSRQ1 - Priorities Selected in the Receive Queue 1
38584  */
38585 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
38586 
38587 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK        (0x300U)
38588 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT       (8U)
38589 /*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
38590  *  0b00..Queue not enabled
38591  *  0b01..Queue enabled for AV
38592  *  0b10..Queue enabled for DCB/Generic
38593  *  0b11..Reserved
38594  */
38595 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
38596 
38597 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK           (0x7000U)
38598 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT          (12U)
38599 /*! UPQ - Untagged Packet Queue
38600  *  0b000..Receive Queue 0
38601  *  0b001..Receive Queue 1
38602  *  0b010..Receive Queue 2
38603  *  0b011..Receive Queue 3
38604  *  0b100..Receive Queue 4
38605  *  0b101..Reserved
38606  *  0b110..Reserved
38607  *  0b111..Reserved
38608  */
38609 #define ENET_QOS_MAC_RXQ_CTRL_UPQ(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
38610 
38611 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK         (0x70000U)
38612 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT        (16U)
38613 /*! MCBCQ - Multicast and Broadcast Queue
38614  *  0b000..Receive Queue 0
38615  *  0b001..Receive Queue 1
38616  *  0b010..Receive Queue 2
38617  *  0b011..Receive Queue 3
38618  *  0b100..Receive Queue 4
38619  *  0b101..Reserved
38620  *  0b110..Reserved
38621  *  0b111..Reserved
38622  */
38623 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
38624 
38625 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK         (0xFF0000U)
38626 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT        (16U)
38627 /*! PSRQ2 - Priorities Selected in the Receive Queue 2
38628  */
38629 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
38630 
38631 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK       (0x100000U)
38632 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT      (20U)
38633 /*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
38634  *    packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
38635  *    to Rx Queue specified in MCBCQ field.
38636  *  0b0..Multicast and Broadcast Queue is disabled
38637  *  0b1..Multicast and Broadcast Queue is enabled
38638  */
38639 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
38640 
38641 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK        (0x200000U)
38642 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT       (21U)
38643 /*! TACPQE - Tagged AV Control Packets Queuing Enable.
38644  *  0b0..Tagged AV Control Packets Queuing is disabled
38645  *  0b1..Tagged AV Control Packets Queuing is enabled
38646  */
38647 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
38648 
38649 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK          (0xC00000U)
38650 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT         (22U)
38651 /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control.
38652  */
38653 #define ENET_QOS_MAC_RXQ_CTRL_TPQC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
38654 
38655 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK          (0x7000000U)
38656 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT         (24U)
38657 /*! FPRQ - Frame Preemption Residue Queue
38658  */
38659 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
38660 
38661 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK         (0xFF000000U)
38662 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT        (24U)
38663 /*! PSRQ3 - Priorities Selected in the Receive Queue 3
38664  */
38665 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
38666 /*! @} */
38667 
38668 /* The count of ENET_QOS_MAC_RXQ_CTRL */
38669 #define ENET_QOS_MAC_RXQ_CTRL_COUNT              (4U)
38670 
38671 /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
38672 /*! @{ */
38673 
38674 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
38675 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
38676 /*! RGSMIIIS - RGMII or SMII Interrupt Status
38677  *  0b1..RGMII or SMII Interrupt Status is active
38678  *  0b0..RGMII or SMII Interrupt Status is not active
38679  */
38680 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
38681 
38682 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
38683 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
38684 /*! PHYIS - PHY Interrupt
38685  *  0b1..PHY Interrupt detected
38686  *  0b0..PHY Interrupt not detected
38687  */
38688 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
38689 
38690 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
38691 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
38692 /*! PMTIS - PMT Interrupt Status
38693  *  0b1..PMT Interrupt status active
38694  *  0b0..PMT Interrupt status not active
38695  */
38696 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
38697 
38698 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
38699 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
38700 /*! LPIIS - LPI Interrupt Status
38701  *  0b1..LPI Interrupt status active
38702  *  0b0..LPI Interrupt status not active
38703  */
38704 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
38705 
38706 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
38707 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
38708 /*! MMCIS - MMC Interrupt Status
38709  *  0b1..MMC Interrupt status active
38710  *  0b0..MMC Interrupt status not active
38711  */
38712 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
38713 
38714 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
38715 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
38716 /*! MMCRXIS - MMC Receive Interrupt Status
38717  *  0b1..MMC Receive Interrupt status active
38718  *  0b0..MMC Receive Interrupt status not active
38719  */
38720 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
38721 
38722 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
38723 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
38724 /*! MMCTXIS - MMC Transmit Interrupt Status
38725  *  0b1..MMC Transmit Interrupt status active
38726  *  0b0..MMC Transmit Interrupt status not active
38727  */
38728 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
38729 
38730 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
38731 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
38732 /*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
38733  *  0b1..MMC Receive Checksum Offload Interrupt status active
38734  *  0b0..MMC Receive Checksum Offload Interrupt status not active
38735  */
38736 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
38737 
38738 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK  (0x1000U)
38739 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
38740 /*! TSIS - Timestamp Interrupt Status
38741  *  0b1..Timestamp Interrupt status active
38742  *  0b0..Timestamp Interrupt status not active
38743  */
38744 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
38745 
38746 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
38747 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
38748 /*! TXSTSIS - Transmit Status Interrupt
38749  *  0b1..Transmit Interrupt status active
38750  *  0b0..Transmit Interrupt status not active
38751  */
38752 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
38753 
38754 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
38755 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
38756 /*! RXSTSIS - Receive Status Interrupt
38757  *  0b1..Receive Interrupt status active
38758  *  0b0..Receive Interrupt status not active
38759  */
38760 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
38761 
38762 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
38763 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
38764 /*! FPEIS - Frame Preemption Interrupt Status
38765  *  0b1..Frame Preemption Interrupt status active
38766  *  0b0..Frame Preemption Interrupt status not active
38767  */
38768 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
38769 
38770 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
38771 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
38772 /*! MDIOIS - MDIO Interrupt Status
38773  *  0b1..MDIO Interrupt status active
38774  *  0b0..MDIO Interrupt status not active
38775  */
38776 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
38777 
38778 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
38779 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
38780 /*! MFTIS - MMC FPE Transmit Interrupt Status
38781  *  0b1..MMC FPE Transmit Interrupt status active
38782  *  0b0..MMC FPE Transmit Interrupt status not active
38783  */
38784 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
38785 
38786 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
38787 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
38788 /*! MFRIS - MMC FPE Receive Interrupt Status
38789  *  0b1..MMC FPE Receive Interrupt status active
38790  *  0b0..MMC FPE Receive Interrupt status not active
38791  */
38792 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
38793 /*! @} */
38794 
38795 /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
38796 /*! @{ */
38797 
38798 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
38799 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
38800 /*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
38801  *    interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
38802  *  0b0..RGMII or SMII Interrupt is disabled
38803  *  0b1..RGMII or SMII Interrupt is enabled
38804  */
38805 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
38806 
38807 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
38808 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
38809 /*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38810  *    signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
38811  *  0b0..PHY Interrupt is disabled
38812  *  0b1..PHY Interrupt is enabled
38813  */
38814 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
38815 
38816 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
38817 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
38818 /*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38819  *    signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
38820  *  0b0..PMT Interrupt is disabled
38821  *  0b1..PMT Interrupt is enabled
38822  */
38823 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
38824 
38825 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
38826 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
38827 /*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38828  *    signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
38829  *  0b0..LPI Interrupt is disabled
38830  *  0b1..LPI Interrupt is enabled
38831  */
38832 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
38833 
38834 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK  (0x1000U)
38835 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
38836 /*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
38837  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
38838  *  0b0..Timestamp Interrupt is disabled
38839  *  0b1..Timestamp Interrupt is enabled
38840  */
38841 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
38842 
38843 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
38844 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
38845 /*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
38846  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
38847  *  0b0..Timestamp Status Interrupt is disabled
38848  *  0b1..Timestamp Status Interrupt is enabled
38849  */
38850 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
38851 
38852 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
38853 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
38854 /*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
38855  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
38856  *  0b0..Receive Status Interrupt is disabled
38857  *  0b1..Receive Status Interrupt is enabled
38858  */
38859 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
38860 
38861 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
38862 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
38863 /*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
38864  *    interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
38865  *  0b0..Frame Preemption Interrupt is disabled
38866  *  0b1..Frame Preemption Interrupt is enabled
38867  */
38868 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
38869 
38870 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
38871 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
38872 /*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38873  *    when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
38874  *  0b0..MDIO Interrupt is disabled
38875  *  0b1..MDIO Interrupt is enabled
38876  */
38877 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
38878 /*! @} */
38879 
38880 /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
38881 /*! @{ */
38882 
38883 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK       (0x1U)
38884 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT      (0U)
38885 /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
38886  *    happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
38887  *    and JD bit is reset in the MAC_CONFIGURATION register.
38888  *  0b1..Transmit Jabber Timeout occurred
38889  *  0b0..No Transmit Jabber Timeout
38890  */
38891 #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
38892 
38893 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK     (0x2U)
38894 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT    (1U)
38895 /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38896  *    indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
38897  *  0b1..No carrier
38898  *  0b0..Carrier is present
38899  */
38900 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
38901 
38902 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK     (0x4U)
38903 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT    (2U)
38904 /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38905  *    indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
38906  *    signal was inactive for one or more transmission clock periods during packet transmission.
38907  *  0b1..Loss of carrier
38908  *  0b0..Carrier is present
38909  */
38910 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
38911 
38912 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK     (0x8U)
38913 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT    (3U)
38914 /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
38915  *    DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
38916  *    ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
38917  *    when Jumbo packet is enabled).
38918  *  0b1..Excessive deferral
38919  *  0b0..No Excessive deferral
38920  */
38921 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
38922 
38923 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK      (0x10U)
38924 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT     (4U)
38925 /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38926  *    indicates that the packet transmission aborted because a collision occurred after the collision
38927  *    window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
38928  *    Extension in GMII mode).
38929  *  0b1..Late collision is sensed
38930  *  0b0..No collision
38931  */
38932 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
38933 
38934 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK     (0x20U)
38935 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT    (5U)
38936 /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
38937  *    bit indicates that the transmission aborted after 16 successive collisions while attempting
38938  *    to transmit the current packet.
38939  *  0b1..Excessive collision is sensed
38940  *  0b0..No collision
38941  */
38942 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
38943 
38944 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK       (0x100U)
38945 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT      (8U)
38946 /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
38947  *    bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
38948  *    MAC_CONFIGURATION register.
38949  *  0b1..Receive watchdog timed out
38950  *  0b0..No receive watchdog timeout
38951  */
38952 #define ENET_QOS_MAC_RX_TX_STATUS_RWT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
38953 /*! @} */
38954 
38955 /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
38956 /*! @{ */
38957 
38958 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
38959 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
38960 /*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
38961  *    receives the expected magic packet or remote wake-up packet.
38962  *  0b0..Power down is disabled
38963  *  0b1..Power down is enabled
38964  */
38965 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
38966 
38967 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
38968 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
38969 /*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
38970  *  0b0..Magic Packet is disabled
38971  *  0b1..Magic Packet is enabled
38972  */
38973 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
38974 
38975 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
38976 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
38977 /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
38978  *    generated when the MAC receives a remote wake-up packet.
38979  *  0b0..Remote wake-up packet is disabled
38980  *  0b1..Remote wake-up packet is enabled
38981  */
38982 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
38983 
38984 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
38985 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
38986 /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
38987  *    event is generated because of the reception of a magic packet.
38988  *  0b1..Magic packet is received
38989  *  0b0..No Magic packet is received
38990  */
38991 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
38992 
38993 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
38994 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
38995 /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
38996  *    management event is generated because of the reception of a remote wake-up packet.
38997  *  0b1..Remote wake-up packet is received
38998  *  0b0..Remote wake-up packet is received
38999  */
39000 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
39001 
39002 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
39003 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
39004 /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
39005  *    address recognition is detected as a remote wake-up packet.
39006  *  0b0..Global unicast is disabled
39007  *  0b1..Global unicast is enabled
39008  */
39009 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
39010 
39011 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
39012 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
39013 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
39014  *    MAC receiver drops all received frames until it receives the expected Wake-up frame.
39015  *  0b0..Remote Wake-up Packet Forwarding is disabled
39016  *  0b1..Remote Wake-up Packet Forwarding is enabled
39017  */
39018 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
39019 
39020 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
39021 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
39022 /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
39023  *    4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
39024  *    register pointer.
39025  */
39026 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
39027 
39028 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
39029 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
39030 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
39031  *    remote wake-up packet filter register pointer is reset to 3'b000.
39032  *  0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
39033  *  0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
39034  */
39035 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
39036 /*! @} */
39037 
39038 /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
39039 /*! @{ */
39040 
39041 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
39042 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
39043 /*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter.
39044  */
39045 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
39046 /*! @} */
39047 
39048 /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
39049 /*! @{ */
39050 
39051 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
39052 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
39053 /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
39054  *    entered the LPI state because of the setting of the LPIEN bit.
39055  *  0b1..Transmit LPI entry detected
39056  *  0b0..Transmit LPI entry not detected
39057  */
39058 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
39059 
39060 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
39061 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
39062 /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
39063  *    the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
39064  *  0b1..Transmit LPI exit detected
39065  *  0b0..Transmit LPI exit not detected
39066  */
39067 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
39068 
39069 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
39070 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
39071 /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
39072  *    an LPI pattern and entered the LPI state.
39073  *  0b1..Receive LPI entry detected
39074  *  0b0..Receive LPI entry not detected
39075  */
39076 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
39077 
39078 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
39079 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
39080 /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
39081  *    receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
39082  *    normal reception.
39083  *  0b1..Receive LPI exit detected
39084  *  0b0..Receive LPI exit not detected
39085  */
39086 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
39087 
39088 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
39089 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
39090 /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
39091  *    LPI pattern on the GMII or MII interface.
39092  *  0b1..Transmit LPI state detected
39093  *  0b0..Transmit LPI state not detected
39094  */
39095 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
39096 
39097 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
39098 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
39099 /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
39100  *    pattern on the GMII or MII interface.
39101  *  0b1..Receive LPI state detected
39102  *  0b0..Receive LPI state not detected
39103  */
39104 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
39105 
39106 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
39107 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
39108 /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
39109  *  0b0..LPI state is disabled
39110  *  0b1..LPI state is enabled
39111  */
39112 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
39113 
39114 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
39115 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
39116 /*! PLS - PHY Link Status This bit indicates the link status of the PHY.
39117  *  0b0..link is down
39118  *  0b1..link is okay (UP)
39119  */
39120 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
39121 
39122 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
39123 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
39124 /*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
39125  *    SMII Receive paths to be used for activating the LPI LS TIMER.
39126  *  0b0..PHY Link Status is disabled
39127  *  0b1..PHY Link Status is enabled
39128  */
39129 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
39130 
39131 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
39132 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
39133 /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
39134  *    out of the LPI mode on the Transmit side.
39135  *  0b0..LPI Tx Automate is disabled
39136  *  0b1..LPI Tx Automate is enabled
39137  */
39138 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
39139 
39140 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
39141 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
39142 /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
39143  *  0b0..LPI Timer is disabled
39144  *  0b1..LPI Timer is enabled
39145  */
39146 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
39147 
39148 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
39149 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
39150 /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
39151  *    sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
39152  *  0b0..LPI Tx Clock Stop is disabled
39153  *  0b1..LPI Tx Clock Stop is enabled
39154  */
39155 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
39156 /*! @} */
39157 
39158 /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
39159 /*! @{ */
39160 
39161 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
39162 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
39163 /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
39164  *    waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
39165  *    transmission.
39166  */
39167 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
39168 
39169 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
39170 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
39171 /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
39172  *    status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
39173  */
39174 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
39175 /*! @} */
39176 
39177 /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
39178 /*! @{ */
39179 
39180 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK  (0xFFFF8U)
39181 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
39182 /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
39183  *    mode, after it has transmitted all the frames.
39184  */
39185 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
39186 /*! @} */
39187 
39188 /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
39189 /*! @{ */
39190 
39191 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
39192 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
39193 /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
39194  */
39195 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
39196 /*! @} */
39197 
39198 /*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
39199 /*! @{ */
39200 
39201 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
39202 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
39203 /*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
39204  *    of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
39205  *    SGMII port.
39206  *  0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
39207  *  0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
39208  */
39209 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
39210 
39211 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
39212 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
39213 /*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
39214  *    configuration in the RGMII, SGMII, or SMII interface.
39215  *  0b0..Link down
39216  *  0b1..Link up
39217  */
39218 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
39219 
39220 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
39221 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
39222 /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
39223  *  0b1..Full-duplex mode
39224  *  0b0..Half-duplex mode
39225  */
39226 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
39227 
39228 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
39229 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
39230 /*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
39231  *  0b10..125 MHz
39232  *  0b00..2.5 MHz
39233  *  0b01..25 MHz
39234  *  0b11..Reserved
39235  */
39236 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
39237 
39238 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
39239 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
39240 /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
39241  *  0b1..Link up
39242  *  0b0..Link down
39243  */
39244 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
39245 /*! @} */
39246 
39247 /*! @name MAC_VERSION - MAC Version */
39248 /*! @{ */
39249 
39250 #define ENET_QOS_MAC_VERSION_SNPSVER_MASK        (0xFFU)
39251 #define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT       (0U)
39252 /*! SNPSVER - Synopsys-defined Version
39253  */
39254 #define ENET_QOS_MAC_VERSION_SNPSVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
39255 
39256 #define ENET_QOS_MAC_VERSION_USERVER_MASK        (0xFF00U)
39257 #define ENET_QOS_MAC_VERSION_USERVER_SHIFT       (8U)
39258 /*! USERVER - User-defined Version (8'h10)
39259  */
39260 #define ENET_QOS_MAC_VERSION_USERVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
39261 /*! @} */
39262 
39263 /*! @name MAC_DEBUG - MAC Debug */
39264 /*! @{ */
39265 
39266 #define ENET_QOS_MAC_DEBUG_RPESTS_MASK           (0x1U)
39267 #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT          (0U)
39268 /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
39269  *    the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
39270  *    Idle state.
39271  *  0b1..MAC GMII or MII Receive Protocol Engine Status detected
39272  *  0b0..MAC GMII or MII Receive Protocol Engine Status not detected
39273  */
39274 #define ENET_QOS_MAC_DEBUG_RPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
39275 
39276 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK         (0x6U)
39277 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT        (1U)
39278 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
39279  *    the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
39280  *    Controller module.
39281  */
39282 #define ENET_QOS_MAC_DEBUG_RFCFCSTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
39283 
39284 #define ENET_QOS_MAC_DEBUG_TPESTS_MASK           (0x10000U)
39285 #define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT          (16U)
39286 /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
39287  *    the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
39288  *    the Idle state.
39289  *  0b1..MAC GMII or MII Transmit Protocol Engine Status detected
39290  *  0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
39291  */
39292 #define ENET_QOS_MAC_DEBUG_TPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
39293 
39294 #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK           (0x60000U)
39295 #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT          (17U)
39296 /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
39297  *  0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
39298  *  0b00..Idle state
39299  *  0b11..Transferring input packet for transmission
39300  *  0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
39301  */
39302 #define ENET_QOS_MAC_DEBUG_TFCSTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
39303 /*! @} */
39304 
39305 /*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
39306 /*! @{ */
39307 
39308 #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK         (0x1U)
39309 #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT        (0U)
39310 /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
39311  *  0b1..10 or 100 Mbps support
39312  *  0b0..No 10 or 100 Mbps support
39313  */
39314 #define ENET_QOS_MAC_HW_FEAT_MIISEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
39315 
39316 #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK           (0x7U)
39317 #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT          (0U)
39318 /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
39319  *  0b011..16 Extended Rx VLAN Filters
39320  *  0b100..24 Extended Rx VLAN Filters
39321  *  0b101..32 Extended Rx VLAN Filters
39322  *  0b001..4 Extended Rx VLAN Filters
39323  *  0b010..8 Extended Rx VLAN Filters
39324  *  0b000..No Extended Rx VLAN Filters
39325  *  0b110..Reserved
39326  */
39327 #define ENET_QOS_MAC_HW_FEAT_NRVF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
39328 
39329 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK     (0x1FU)
39330 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT    (0U)
39331 /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
39332  *    bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
39333  *  0b00011..1024 bytes
39334  *  0b00000..128 bytes
39335  *  0b01010..128 KB
39336  *  0b00111..16384 bytes
39337  *  0b00100..2048 bytes
39338  *  0b00001..256 bytes
39339  *  0b01011..256 KB
39340  *  0b01000..32 KB
39341  *  0b00101..4096 bytes
39342  *  0b00010..512 bytes
39343  *  0b01001..64 KB
39344  *  0b00110..8192 bytes
39345  *  0b01100..Reserved
39346  */
39347 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
39348 
39349 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK         (0xFU)
39350 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT        (0U)
39351 /*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
39352  *  0b0000..1 MTL Rx Queue
39353  *  0b0001..2 MTL Rx Queues
39354  *  0b0010..3 MTL Rx Queues
39355  *  0b0011..4 MTL Rx Queues
39356  *  0b0100..5 MTL Rx Queues
39357  *  0b0101..Reserved
39358  *  0b0110..Reserved
39359  *  0b0111..Reserved
39360  */
39361 #define ENET_QOS_MAC_HW_FEAT_RXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
39362 
39363 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK        (0x2U)
39364 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT       (1U)
39365 /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
39366  *  0b1..1000 Mbps support
39367  *  0b0..No 1000 Mbps support
39368  */
39369 #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
39370 
39371 #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK          (0x4U)
39372 #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT         (2U)
39373 /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
39374  *  0b1..Half-duplex support
39375  *  0b0..No Half-duplex support
39376  */
39377 #define ENET_QOS_MAC_HW_FEAT_HDSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
39378 
39379 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK         (0x8U)
39380 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT        (3U)
39381 /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
39382  *    SGMII, or RTBI PHY interface option is selected
39383  *  0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
39384  *  0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
39385  */
39386 #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
39387 
39388 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK        (0x10U)
39389 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT       (4U)
39390 /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
39391  *    Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
39392  *  0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
39393  *  0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
39394  */
39395 #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
39396 
39397 #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK         (0x10U)
39398 #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT        (4U)
39399 /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
39400  *  0b1..VLAN Hash Filter selected
39401  *  0b0..VLAN Hash Filter not selected
39402  */
39403 #define ENET_QOS_MAC_HW_FEAT_VLHASH(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
39404 
39405 #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK          (0x20U)
39406 #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT         (5U)
39407 /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
39408  *  0b1..Double VLAN option is selected
39409  *  0b0..Double VLAN option is not selected
39410  */
39411 #define ENET_QOS_MAC_HW_FEAT_DVLAN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
39412 
39413 #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK         (0x20U)
39414 #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT        (5U)
39415 /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
39416  *  0b1..SMA (MDIO) Interface selected
39417  *  0b0..SMA (MDIO) Interface not selected
39418  */
39419 #define ENET_QOS_MAC_HW_FEAT_SMASEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
39420 
39421 #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK          (0x20U)
39422 #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT         (5U)
39423 /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
39424  *  0b1..Single Port RAM feature is selected
39425  *  0b0..Single Port RAM feature is not selected
39426  */
39427 #define ENET_QOS_MAC_HW_FEAT_SPRAM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
39428 
39429 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK         (0x40U)
39430 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT        (6U)
39431 /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
39432  *  0b1..PMT Remote Wake-up Packet Enable option is selected
39433  *  0b0..PMT Remote Wake-up Packet Enable option is not selected
39434  */
39435 #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
39436 
39437 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK     (0x7C0U)
39438 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT    (6U)
39439 /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
39440  *    bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
39441  *  0b00011..1024 bytes
39442  *  0b00000..128 bytes
39443  *  0b01010..128 KB
39444  *  0b00111..16384 bytes
39445  *  0b00100..2048 bytes
39446  *  0b00001..256 bytes
39447  *  0b01000..32 KB
39448  *  0b00101..4096 bytes
39449  *  0b00010..512 bytes
39450  *  0b01001..64 KB
39451  *  0b00110..8192 bytes
39452  *  0b01011..Reserved
39453  */
39454 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
39455 
39456 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK         (0x3C0U)
39457 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT        (6U)
39458 /*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
39459  *  0b0000..1 MTL Tx Queue
39460  *  0b0001..2 MTL Tx Queues
39461  *  0b0010..3 MTL Tx Queues
39462  *  0b0011..4 MTL Tx Queues
39463  *  0b0100..5 MTL Tx Queues
39464  *  0b0101..Reserved
39465  *  0b0110..Reserved
39466  *  0b0111..Reserved
39467  */
39468 #define ENET_QOS_MAC_HW_FEAT_TXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
39469 
39470 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK         (0x80U)
39471 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT        (7U)
39472 /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
39473  *  0b1..PMT Magic Packet Enable option is selected
39474  *  0b0..PMT Magic Packet Enable option is not selected
39475  */
39476 #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
39477 
39478 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK         (0x100U)
39479 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT        (8U)
39480 /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
39481  *  0b1..RMON Module Enable option is selected
39482  *  0b0..RMON Module Enable option is not selected
39483  */
39484 #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
39485 
39486 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK      (0x200U)
39487 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT     (9U)
39488 /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
39489  *  0b1..ARP Offload Enable option is selected
39490  *  0b0..ARP Offload Enable option is not selected
39491  */
39492 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
39493 
39494 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK        (0x200U)
39495 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT       (9U)
39496 /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
39497  *    Broadcast/Multicast Packet Duplication feature is selected.
39498  *  0b1..Broadcast/Multicast Packet Duplication feature is selected
39499  *  0b0..Broadcast/Multicast Packet Duplication feature is not selected
39500  */
39501 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
39502 
39503 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK         (0x400U)
39504 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT        (10U)
39505 /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
39506  *    Programmable Receive Parser option is selected.
39507  *  0b1..Flexible Receive Parser feature is selected
39508  *  0b0..Flexible Receive Parser feature is not selected
39509  */
39510 #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
39511 
39512 #define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK          (0x1800U)
39513 #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT         (11U)
39514 /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
39515  *    bytes of the packet data to be Parsed by Flexible Receive Parser.
39516  *  0b01..128 Bytes
39517  *  0b10..256 Bytes
39518  *  0b00..64 Bytes
39519  *  0b11..Reserved
39520  */
39521 #define ENET_QOS_MAC_HW_FEAT_FRPBS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
39522 
39523 #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK          (0x800U)
39524 #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT         (11U)
39525 /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
39526  *  0b1..One-Step Timestamping feature is selected
39527  *  0b0..One-Step Timestamping feature is not selected
39528  */
39529 #define ENET_QOS_MAC_HW_FEAT_OSTEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
39530 
39531 #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK          (0x1000U)
39532 #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT         (12U)
39533 /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
39534  *  0b1..PTP Offload feature is selected
39535  *  0b0..PTP Offload feature is not selected
39536  */
39537 #define ENET_QOS_MAC_HW_FEAT_PTOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
39538 
39539 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK        (0xF000U)
39540 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT       (12U)
39541 /*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
39542  *  0b0000..1 MTL Rx Channel
39543  *  0b0001..2 MTL Rx Channels
39544  *  0b0010..3 MTL Rx Channels
39545  *  0b0011..4 MTL Rx Channels
39546  *  0b0100..5 MTL Rx Channels
39547  *  0b0101..Reserved
39548  *  0b0110..Reserved
39549  *  0b0111..Reserved
39550  */
39551 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
39552 
39553 #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK          (0x1000U)
39554 #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT         (12U)
39555 /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
39556  *  0b1..IEEE 1588-2008 Timestamp Enable option is selected
39557  *  0b0..IEEE 1588-2008 Timestamp Enable option is not selected
39558  */
39559 #define ENET_QOS_MAC_HW_FEAT_TSSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
39560 
39561 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK      (0x2000U)
39562 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT     (13U)
39563 /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
39564  *  0b1..IEEE 1588 High Word Register option is selected
39565  *  0b0..IEEE 1588 High Word Register option is not selected
39566  */
39567 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
39568 
39569 #define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK         (0x2000U)
39570 #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT        (13U)
39571 /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
39572  *    Ethernet (EEE) option is selected
39573  *  0b1..Energy Efficient Ethernet Enable option is selected
39574  *  0b0..Energy Efficient Ethernet Enable option is not selected
39575  */
39576 #define ENET_QOS_MAC_HW_FEAT_EEESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
39577 
39578 #define ENET_QOS_MAC_HW_FEAT_FRPES_MASK          (0x6000U)
39579 #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT         (13U)
39580 /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
39581  *    Entries supported by Flexible Receive Parser.
39582  *  0b01..128 Entries
39583  *  0b10..256 Entries
39584  *  0b00..64 Entries
39585  *  0b11..Reserved
39586  */
39587 #define ENET_QOS_MAC_HW_FEAT_FRPES(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
39588 
39589 #define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK         (0xC000U)
39590 #define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT        (14U)
39591 /*! ADDR64 - Address Width.
39592  *  0b00..32
39593  *  0b01..40
39594  *  0b10..48
39595  *  0b11..Reserved
39596  */
39597 #define ENET_QOS_MAC_HW_FEAT_ADDR64(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
39598 
39599 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK       (0x4000U)
39600 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT      (14U)
39601 /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
39602  *    TCP/IP Checksum Insertion option is selected
39603  *  0b1..Transmit Checksum Offload Enable option is selected
39604  *  0b0..Transmit Checksum Offload Enable option is not selected
39605  */
39606 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
39607 
39608 #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK          (0x10000U)
39609 #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT         (16U)
39610 /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
39611  *  0b1..DCB Feature is selected
39612  *  0b0..DCB Feature is not selected
39613  */
39614 #define ENET_QOS_MAC_HW_FEAT_DCBEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
39615 
39616 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK         (0x10000U)
39617 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT        (16U)
39618 /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
39619  *    Enhancements to Scheduling Traffic feature is selected.
39620  *  0b1..Enable Enhancements to Scheduling Traffic feature is selected
39621  *  0b0..Enable Enhancements to Scheduling Traffic feature is not selected
39622  */
39623 #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
39624 
39625 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK       (0x10000U)
39626 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT      (16U)
39627 /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
39628  *  0b1..Receive Checksum Offload Enable option is selected
39629  *  0b0..Receive Checksum Offload Enable option is not selected
39630  */
39631 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
39632 
39633 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK         (0xE0000U)
39634 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT        (17U)
39635 /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
39636  *  0b101..1024
39637  *  0b010..128
39638  *  0b011..256
39639  *  0b100..512
39640  *  0b001..64
39641  *  0b000..No Depth configured
39642  *  0b110..Reserved
39643  */
39644 #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
39645 
39646 #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK          (0x20000U)
39647 #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT         (17U)
39648 /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
39649  *  0b1..Split Header Feature is selected
39650  *  0b0..Split Header Feature is not selected
39651  */
39652 #define ENET_QOS_MAC_HW_FEAT_SPHEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
39653 
39654 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK   (0x7C0000U)
39655 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT  (18U)
39656 /*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
39657  *    selected for Enable Additional 1-31 MAC Address Registers option
39658  */
39659 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
39660 
39661 #define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK          (0x40000U)
39662 #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT         (18U)
39663 /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
39664  *    Offloading for TCP/IP Packets option is selected
39665  *  0b1..TCP Segmentation Offload Feature is selected
39666  *  0b0..TCP Segmentation Offload Feature is not selected
39667  */
39668 #define ENET_QOS_MAC_HW_FEAT_TSOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
39669 
39670 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK        (0x3C0000U)
39671 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT       (18U)
39672 /*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
39673  *  0b0000..1 MTL Tx Channel
39674  *  0b0001..2 MTL Tx Channels
39675  *  0b0010..3 MTL Tx Channels
39676  *  0b0011..4 MTL Tx Channels
39677  *  0b0100..5 MTL Tx Channels
39678  *  0b0101..Reserved
39679  *  0b0110..Reserved
39680  *  0b0111..Reserved
39681  */
39682 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
39683 
39684 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK        (0x80000U)
39685 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT       (19U)
39686 /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
39687  *  0b1..DMA Debug Registers option is selected
39688  *  0b0..DMA Debug Registers option is not selected
39689  */
39690 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
39691 
39692 #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK          (0x100000U)
39693 #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT         (20U)
39694 /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
39695  *  0b1..AV Feature is selected
39696  *  0b0..AV Feature is not selected
39697  */
39698 #define ENET_QOS_MAC_HW_FEAT_AVSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
39699 
39700 #define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK         (0x300000U)
39701 #define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT        (20U)
39702 /*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
39703  *    width of the Configured Time Interval Field
39704  *  0b00..Width not configured
39705  *  0b01..16
39706  *  0b10..20
39707  *  0b11..24
39708  */
39709 #define ENET_QOS_MAC_HW_FEAT_ESTWID(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
39710 
39711 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK         (0x200000U)
39712 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT        (21U)
39713 /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
39714  *    Bridging option on Rx Side Only is selected.
39715  *  0b1..Rx Side Only AV Feature is selected
39716  *  0b0..Rx Side Only AV Feature is not selected
39717  */
39718 #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
39719 
39720 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK    (0x800000U)
39721 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT   (23U)
39722 /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
39723  *    MAC Address Registers (32-63) option is selected
39724  *  0b1..MAC Addresses 32-63 Select option is selected
39725  *  0b0..MAC Addresses 32-63 Select option is not selected
39726  */
39727 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
39728 
39729 #define ENET_QOS_MAC_HW_FEAT_POUOST_MASK         (0x800000U)
39730 #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT        (23U)
39731 /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
39732  *    step timestamp for PTP over UDP/IP feature is selected.
39733  *  0b1..One Step for PTP over UDP/IP Feature is selected
39734  *  0b0..One Step for PTP over UDP/IP Feature is not selected
39735  */
39736 #define ENET_QOS_MAC_HW_FEAT_POUOST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
39737 
39738 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK      (0x3000000U)
39739 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT     (24U)
39740 /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
39741  *  0b10..128
39742  *  0b11..256
39743  *  0b01..64
39744  *  0b00..No hash table
39745  */
39746 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
39747 
39748 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK    (0x1000000U)
39749 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT   (24U)
39750 /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
39751  *    MAC Address Registers (64-127) option is selected
39752  *  0b1..MAC Addresses 64-127 Select option is selected
39753  *  0b0..MAC Addresses 64-127 Select option is not selected
39754  */
39755 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
39756 
39757 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK      (0x7000000U)
39758 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT     (24U)
39759 /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
39760  *  0b001..1 PPS output
39761  *  0b010..2 PPS output
39762  *  0b011..3 PPS output
39763  *  0b100..4 PPS output
39764  *  0b000..No PPS output
39765  *  0b101..Reserved
39766  */
39767 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
39768 
39769 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK       (0x6000000U)
39770 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT      (25U)
39771 /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
39772  *    time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
39773  *  0b10..Both
39774  *  0b01..External
39775  *  0b00..Internal
39776  *  0b11..Reserved
39777  */
39778 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
39779 
39780 #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK         (0x4000000U)
39781 #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT        (26U)
39782 /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
39783  *  0b1..Frame Preemption Enable feature is selected
39784  *  0b0..Frame Preemption Enable feature is not selected
39785  */
39786 #define ENET_QOS_MAC_HW_FEAT_FPESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
39787 
39788 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK       (0x78000000U)
39789 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT      (27U)
39790 /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
39791  *  0b0001..1 L3 or L4 Filter
39792  *  0b0010..2 L3 or L4 Filters
39793  *  0b0011..3 L3 or L4 Filters
39794  *  0b0100..4 L3 or L4 Filters
39795  *  0b0101..5 L3 or L4 Filters
39796  *  0b0110..6 L3 or L4 Filters
39797  *  0b0111..7 L3 or L4 Filters
39798  *  0b1000..8 L3 or L4 Filters
39799  *  0b0000..No L3 or L4 Filter
39800  */
39801 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
39802 
39803 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK      (0x8000000U)
39804 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT     (27U)
39805 /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
39806  *    VLAN Insertion on Tx option is selected
39807  *  0b1..Source Address or VLAN Insertion Enable option is selected
39808  *  0b0..Source Address or VLAN Insertion Enable option is not selected
39809  */
39810 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
39811 
39812 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK         (0x8000000U)
39813 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT        (27U)
39814 /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
39815  *  0b1..Time Based Scheduling Enable feature is selected
39816  *  0b0..Time Based Scheduling Enable feature is not selected
39817  */
39818 #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
39819 
39820 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK      (0x70000000U)
39821 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT     (28U)
39822 /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
39823  *    this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
39824  *  0b000..GMII or MII
39825  *  0b111..RevMII
39826  *  0b001..RGMII
39827  *  0b100..RMII
39828  *  0b101..RTBI
39829  *  0b010..SGMII
39830  *  0b110..SMII
39831  *  0b011..TBI
39832  */
39833 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
39834 
39835 #define ENET_QOS_MAC_HW_FEAT_ASP_MASK            (0x30000000U)
39836 #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT           (28U)
39837 /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
39838  *  0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
39839  *  0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
39840  *  0b01..Only "ECC protection for external memory" feature is selected
39841  *  0b00..No Safety features selected
39842  */
39843 #define ENET_QOS_MAC_HW_FEAT_ASP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
39844 
39845 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK     (0x70000000U)
39846 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT    (28U)
39847 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
39848  *  0b001..1 auxiliary input
39849  *  0b010..2 auxiliary input
39850  *  0b011..3 auxiliary input
39851  *  0b100..4 auxiliary input
39852  *  0b000..No auxiliary input
39853  *  0b101..Reserved
39854  */
39855 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
39856 /*! @} */
39857 
39858 /* The count of ENET_QOS_MAC_HW_FEAT */
39859 #define ENET_QOS_MAC_HW_FEAT_COUNT               (4U)
39860 
39861 /*! @name MAC_MDIO_ADDRESS - MDIO Address */
39862 /*! @{ */
39863 
39864 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK        (0x1U)
39865 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT       (0U)
39866 /*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
39867  *  0b0..GMII Busy is disabled
39868  *  0b1..GMII Busy is enabled
39869  */
39870 #define ENET_QOS_MAC_MDIO_ADDRESS_GB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
39871 
39872 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK      (0x2U)
39873 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT     (1U)
39874 /*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
39875  *  0b0..Clause 45 PHY is disabled
39876  *  0b1..Clause 45 PHY is enabled
39877  */
39878 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
39879 
39880 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK     (0x4U)
39881 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT    (2U)
39882 /*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
39883  *  0b0..GMII Operation Command 0 is disabled
39884  *  0b1..GMII Operation Command 0 is enabled
39885  */
39886 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
39887 
39888 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK     (0x8U)
39889 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT    (3U)
39890 /*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
39891  *    RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
39892  *    Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
39893  *    and Read commands are valid.
39894  *  0b0..GMII Operation Command 1 is disabled
39895  *  0b1..GMII Operation Command 1 is enabled
39896  */
39897 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
39898 
39899 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK      (0x10U)
39900 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT     (4U)
39901 /*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
39902  *    before read, write, or post-read increment address packets.
39903  *  0b0..Skip Address Packet is disabled
39904  *  0b1..Skip Address Packet is enabled
39905  */
39906 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
39907 
39908 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK        (0xF00U)
39909 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT       (8U)
39910 /*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
39911  *    according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
39912  *    clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
39913  *    = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
39914  *    - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
39915  *    MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
39916  *    clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
39917  *    applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
39918  */
39919 #define ENET_QOS_MAC_MDIO_ADDRESS_CR(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
39920 
39921 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK       (0x7000U)
39922 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT      (12U)
39923 /*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
39924  *    generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
39925  */
39926 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
39927 
39928 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK       (0x1F0000U)
39929 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT      (16U)
39930 /*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device.
39931  */
39932 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
39933 
39934 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK        (0x3E00000U)
39935 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT       (21U)
39936 /*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing.
39937  */
39938 #define ENET_QOS_MAC_MDIO_ADDRESS_PA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
39939 
39940 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK       (0x4000000U)
39941 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT      (26U)
39942 /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
39943  *    the MAC informs the completion of a read or write command at the end of frame transfer (before
39944  *    the trailing clocks are transmitted).
39945  *  0b0..Back to Back transactions disabled
39946  *  0b1..Back to Back transactions enabled
39947  */
39948 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
39949 
39950 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK       (0x8000000U)
39951 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT      (27U)
39952 /*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
39953  *    and transmits MDIO frames with only 1 preamble bit.
39954  *  0b0..Preamble Suppression disabled
39955  *  0b1..Preamble Suppression enabled
39956  */
39957 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
39958 /*! @} */
39959 
39960 /*! @name MAC_MDIO_DATA - MAC MDIO Data */
39961 /*! @{ */
39962 
39963 #define ENET_QOS_MAC_MDIO_DATA_GD_MASK           (0xFFFFU)
39964 #define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT          (0U)
39965 /*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
39966  *    Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
39967  *    Management Write operation.
39968  */
39969 #define ENET_QOS_MAC_MDIO_DATA_GD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
39970 
39971 #define ENET_QOS_MAC_MDIO_DATA_RA_MASK           (0xFFFF0000U)
39972 #define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT          (16U)
39973 /*! RA - Register Address This field is valid only when C45E is set.
39974  */
39975 #define ENET_QOS_MAC_MDIO_DATA_RA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
39976 /*! @} */
39977 
39978 /*! @name MAC_CSR_SW_CTRL - CSR Software Control */
39979 /*! @{ */
39980 
39981 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK       (0x1U)
39982 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT      (0U)
39983 /*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
39984  *    fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
39985  *    clear it.
39986  *  0b0..Register Clear on Write 1 is disabled
39987  *  0b1..Register Clear on Write 1 is enabled
39988  */
39989 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
39990 /*! @} */
39991 
39992 /*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
39993 /*! @{ */
39994 
39995 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK      (0x1U)
39996 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT     (0U)
39997 /*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
39998  *  0b0..Tx Frame Preemption is disabled
39999  *  0b1..Tx Frame Preemption is enabled
40000  */
40001 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
40002 
40003 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK      (0x2U)
40004 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT     (1U)
40005 /*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
40006  *  0b0..Send Verify mPacket is disabled
40007  *  0b1..Send Verify mPacket is enabled
40008  */
40009 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
40010 
40011 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK      (0x4U)
40012 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT     (2U)
40013 /*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
40014  *  0b0..Send Respond mPacket is disabled
40015  *  0b1..Send Respond mPacket is enabled
40016  */
40017 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
40018 
40019 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK  (0x8U)
40020 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
40021 /*! S1_SET_0 - Synopsys Reserved, Must be set to "0".
40022  */
40023 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
40024 
40025 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK      (0x10000U)
40026 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT     (16U)
40027 /*! RVER - Received Verify Frame Set when a Verify mPacket is received.
40028  *  0b1..Received Verify Frame
40029  *  0b0..Not received Verify Frame
40030  */
40031 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
40032 
40033 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK      (0x20000U)
40034 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT     (17U)
40035 /*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
40036  *  0b1..Received Respond Frame
40037  *  0b0..Not received Respond Frame
40038  */
40039 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
40040 
40041 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK      (0x40000U)
40042 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT     (18U)
40043 /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
40044  *  0b1..transmitted Verify Frame
40045  *  0b0..Not transmitted Verify Frame
40046  */
40047 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
40048 
40049 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK      (0x80000U)
40050 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT     (19U)
40051 /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
40052  *  0b1..transmitted Respond Frame
40053  *  0b0..Not transmitted Respond Frame
40054  */
40055 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
40056 /*! @} */
40057 
40058 /*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
40059 /*! @{ */
40060 
40061 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK     (0xFFFFFFFFU)
40062 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT    (0U)
40063 /*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
40064  *    rollover equivalent time of the PTP System Time in ns
40065  */
40066 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
40067 /*! @} */
40068 
40069 /*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
40070 /*! @{ */
40071 
40072 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK   (0xFFFFFFFFU)
40073 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT  (0U)
40074 /*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time.
40075  */
40076 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
40077 /*! @} */
40078 
40079 /*! @name HIGH - MAC Address0 High..MAC Address63 High */
40080 /*! @{ */
40081 
40082 #define ENET_QOS_HIGH_ADDRHI_MASK                (0xFFFFU)
40083 #define ENET_QOS_HIGH_ADDRHI_SHIFT               (0U)
40084 /*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address.
40085  */
40086 #define ENET_QOS_HIGH_ADDRHI(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
40087 
40088 #define ENET_QOS_HIGH_DCS_MASK                   (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
40089 #define ENET_QOS_HIGH_DCS_SHIFT                  (16U)
40090 /*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
40091  *    contains the binary representation of the DMA Channel number to which an Rx packet whose DA
40092  *    matches the MAC Address(#i) content is routed.
40093  */
40094 #define ENET_QOS_HIGH_DCS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
40095 
40096 #define ENET_QOS_HIGH_MBC_MASK                   (0x3F000000U)
40097 #define ENET_QOS_HIGH_MBC_SHIFT                  (24U)
40098 /*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes.
40099  */
40100 #define ENET_QOS_HIGH_MBC(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
40101 
40102 #define ENET_QOS_HIGH_SA_MASK                    (0x40000000U)
40103 #define ENET_QOS_HIGH_SA_SHIFT                   (30U)
40104 /*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
40105  *    fields of the received packet.
40106  *  0b0..Compare with Destination Address
40107  *  0b1..Compare with Source Address
40108  */
40109 #define ENET_QOS_HIGH_SA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
40110 
40111 #define ENET_QOS_HIGH_AE_MASK                    (0x80000000U)
40112 #define ENET_QOS_HIGH_AE_SHIFT                   (31U)
40113 /*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
40114  *  0b0..INVALID : This bit must be always set to 1
40115  *  0b1..This bit is always set to 1
40116  */
40117 #define ENET_QOS_HIGH_AE(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
40118 /*! @} */
40119 
40120 /* The count of ENET_QOS_HIGH */
40121 #define ENET_QOS_HIGH_COUNT                      (64U)
40122 
40123 /*! @name LOW - MAC Address0 Low..MAC Address63 Low */
40124 /*! @{ */
40125 
40126 #define ENET_QOS_LOW_ADDRLO_MASK                 (0xFFFFFFFFU)
40127 #define ENET_QOS_LOW_ADDRLO_SHIFT                (0U)
40128 /*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address.
40129  */
40130 #define ENET_QOS_LOW_ADDRLO(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
40131 /*! @} */
40132 
40133 /* The count of ENET_QOS_LOW */
40134 #define ENET_QOS_LOW_COUNT                       (64U)
40135 
40136 /*! @name MAC_MMC_CONTROL - MMC Control */
40137 /*! @{ */
40138 
40139 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK     (0x1U)
40140 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT    (0U)
40141 /*! CNTRST - Counters Reset When this bit is set, all counters are reset.
40142  *  0b0..Counters are not reset
40143  *  0b1..All counters are reset
40144  */
40145 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
40146 
40147 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK  (0x2U)
40148 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
40149 /*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
40150  *  0b0..Counter Stop Rollover is disabled
40151  *  0b1..Counter Stop Rollover is enabled
40152  */
40153 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
40154 
40155 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK    (0x4U)
40156 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT   (2U)
40157 /*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
40158  *  0b0..Reset on Read is disabled
40159  *  0b1..Reset on Read is enabled
40160  */
40161 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
40162 
40163 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK   (0x8U)
40164 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT  (3U)
40165 /*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
40166  *  0b0..MMC Counter Freeze is disabled
40167  *  0b1..MMC Counter Freeze is enabled
40168  */
40169 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
40170 
40171 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK    (0x10U)
40172 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT   (4U)
40173 /*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
40174  *    full or almost half according to the CNTPRSTLVL bit.
40175  *  0b0..Counters Preset is disabled
40176  *  0b1..Counters Preset is enabled
40177  */
40178 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
40179 
40180 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
40181 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
40182 /*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
40183  *  0b0..Full-Half Preset is disabled
40184  *  0b1..Full-Half Preset is enabled
40185  */
40186 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
40187 
40188 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK      (0x100U)
40189 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT     (8U)
40190 /*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
40191  *  0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
40192  *  0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
40193  */
40194 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
40195 /*! @} */
40196 
40197 /*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
40198 /*! @{ */
40199 
40200 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
40201 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
40202 /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
40203  *    rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
40204  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
40205  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
40206  */
40207 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
40208 
40209 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
40210 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
40211 /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
40212  *    rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
40213  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
40214  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
40215  */
40216 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
40217 
40218 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
40219 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
40220 /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
40221  *    rxoctetcount_g counter reaches half of the maximum value or the maximum value.
40222  *  0b1..MMC Receive Good Octet Counter Interrupt Status detected
40223  *  0b0..MMC Receive Good Octet Counter Interrupt Status not detected
40224  */
40225 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
40226 
40227 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
40228 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
40229 /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
40230  *    rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
40231  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
40232  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
40233  */
40234 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
40235 
40236 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
40237 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
40238 /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
40239  *    rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
40240  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
40241  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
40242  */
40243 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
40244 
40245 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
40246 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
40247 /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
40248  *    rxcrcerror counter reaches half of the maximum value or the maximum value.
40249  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
40250  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
40251  */
40252 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
40253 
40254 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
40255 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
40256 /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
40257  *    the rxalignmenterror counter reaches half of the maximum value or the maximum value.
40258  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
40259  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
40260  */
40261 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
40262 
40263 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
40264 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
40265 /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
40266  *    rxrunterror counter reaches half of the maximum value or the maximum value.
40267  *  0b1..MMC Receive Runt Packet Counter Interrupt Status detected
40268  *  0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
40269  */
40270 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
40271 
40272 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
40273 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
40274 /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
40275  *    rxjabbererror counter reaches half of the maximum value or the maximum value.
40276  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
40277  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
40278  */
40279 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
40280 
40281 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
40282 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
40283 /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
40284  *    the rxundersize_g counter reaches half of the maximum value or the maximum value.
40285  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
40286  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
40287  */
40288 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
40289 
40290 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
40291 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
40292 /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
40293  *    rxoversize_g counter reaches half of the maximum value or the maximum value.
40294  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
40295  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
40296  */
40297 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
40298 
40299 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
40300 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
40301 /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
40302  *    when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
40303  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
40304  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
40305  */
40306 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
40307 
40308 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
40309 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
40310 /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
40311  *    is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
40312  *    value.
40313  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
40314  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
40315  */
40316 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
40317 
40318 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
40319 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
40320 /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
40321  *    bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
40322  *    maximum value.
40323  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
40324  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
40325  */
40326 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
40327 
40328 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
40329 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
40330 /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
40331  *    bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
40332  *    maximum value.
40333  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
40334  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
40335  */
40336 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
40337 
40338 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
40339 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
40340 /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
40341  *    bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
40342  *    maximum value.
40343  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
40344  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
40345  */
40346 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
40347 
40348 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
40349 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
40350 /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
40351  *    This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
40352  *    maximum value.
40353  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
40354  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
40355  */
40356 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
40357 
40358 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
40359 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
40360 /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
40361  *    rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
40362  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
40363  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
40364  */
40365 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
40366 
40367 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
40368 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
40369 /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
40370  *    rxlengtherror counter reaches half of the maximum value or the maximum value.
40371  *  0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
40372  *  0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
40373  */
40374 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
40375 
40376 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
40377 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
40378 /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
40379  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
40380  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
40381  */
40382 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
40383 
40384 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
40385 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
40386 /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
40387  *    rxpausepackets counter reaches half of the maximum value or the maximum value.
40388  *  0b1..MMC Receive Pause Packet Counter Interrupt Status detected
40389  *  0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
40390  */
40391 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
40392 
40393 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
40394 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
40395 /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
40396  *    rxfifooverflow counter reaches half of the maximum value or the maximum value.
40397  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
40398  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
40399  */
40400 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
40401 
40402 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
40403 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
40404 /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
40405  *    rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
40406  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
40407  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
40408  */
40409 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
40410 
40411 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
40412 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
40413 /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
40414  *    rxwatchdog error counter reaches half of the maximum value or the maximum value.
40415  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
40416  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
40417  */
40418 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
40419 
40420 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
40421 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
40422 /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
40423  *    rxrcverror counter reaches half of the maximum value or the maximum value.
40424  *  0b1..MMC Receive Error Packet Counter Interrupt Status detected
40425  *  0b0..MMC Receive Error Packet Counter Interrupt Status not detected
40426  */
40427 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
40428 
40429 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
40430 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
40431 /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
40432  *    rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
40433  *  0b1..MMC Receive Control Packet Counter Interrupt Status detected
40434  *  0b0..MMC Receive Control Packet Counter Interrupt Status not detected
40435  */
40436 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
40437 
40438 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
40439 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
40440 /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
40441  *    Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40442  *  0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
40443  *  0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
40444  */
40445 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
40446 
40447 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
40448 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
40449 /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
40450  *    Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40451  *  0b1..MMC Receive LPI transition Counter Interrupt Status detected
40452  *  0b0..MMC Receive LPI transition Counter Interrupt Status not detected
40453  */
40454 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
40455 /*! @} */
40456 
40457 /*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
40458 /*! @{ */
40459 
40460 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
40461 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
40462 /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
40463  *    txoctetcount_gb counter reaches half of the maximum value or the maximum value.
40464  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
40465  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
40466  */
40467 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
40468 
40469 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
40470 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
40471 /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
40472  *    txpacketcount_gb counter reaches half of the maximum value or the maximum value.
40473  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
40474  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
40475  */
40476 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
40477 
40478 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
40479 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
40480 /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
40481  *    txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
40482  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
40483  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
40484  */
40485 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
40486 
40487 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
40488 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
40489 /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
40490  *    txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
40491  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
40492  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
40493  */
40494 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
40495 
40496 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
40497 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
40498 /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
40499  *    when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
40500  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
40501  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
40502  */
40503 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
40504 
40505 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
40506 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
40507 /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
40508  *    bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
40509  *    reaches the maximum value.
40510  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
40511  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
40512  */
40513 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
40514 
40515 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
40516 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
40517 /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
40518  *    bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
40519  *    maximum value.
40520  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
40521  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
40522  */
40523 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
40524 
40525 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
40526 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
40527 /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
40528  *    bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
40529  *    maximum value.
40530  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
40531  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
40532  */
40533 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
40534 
40535 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
40536 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
40537 /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
40538  *    This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
40539  *    maximum value.
40540  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
40541  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
40542  */
40543 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
40544 
40545 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
40546 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
40547 /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
40548  *    This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
40549  *    the maximum value.
40550  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
40551  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
40552  */
40553 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
40554 
40555 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
40556 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
40557 /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
40558  *    the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
40559  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
40560  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
40561  */
40562 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
40563 
40564 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
40565 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
40566 /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
40567  *    the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
40568  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
40569  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
40570  */
40571 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
40572 
40573 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
40574 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
40575 /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
40576  *    the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
40577  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
40578  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
40579  */
40580 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
40581 
40582 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
40583 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
40584 /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
40585  *    the txunderflowerror counter reaches half of the maximum value or the maximum value.
40586  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
40587  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
40588  */
40589 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
40590 
40591 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
40592 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
40593 /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
40594  *    when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
40595  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
40596  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
40597  */
40598 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
40599 
40600 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
40601 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
40602 /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
40603  *    set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
40604  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
40605  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
40606  */
40607 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
40608 
40609 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
40610 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
40611 /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
40612  *    txdeferred counter reaches half of the maximum value or the maximum value.
40613  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
40614  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
40615  */
40616 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
40617 
40618 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
40619 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
40620 /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
40621  *    the txlatecol counter reaches half of the maximum value or the maximum value.
40622  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
40623  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
40624  */
40625 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
40626 
40627 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
40628 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
40629 /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
40630  *    when the txexesscol counter reaches half of the maximum value or the maximum value.
40631  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
40632  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
40633  */
40634 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
40635 
40636 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
40637 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
40638 /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
40639  *    txcarriererror counter reaches half of the maximum value or the maximum value.
40640  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
40641  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
40642  */
40643 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
40644 
40645 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
40646 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
40647 /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
40648  *    txoctetcount_g counter reaches half of the maximum value or the maximum value.
40649  *  0b1..MMC Transmit Good Octet Counter Interrupt Status detected
40650  *  0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
40651  */
40652 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
40653 
40654 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
40655 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
40656 /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
40657  *    txpacketcount_g counter reaches half of the maximum value or the maximum value.
40658  *  0b1..MMC Transmit Good Packet Counter Interrupt Status detected
40659  *  0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
40660  */
40661 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
40662 
40663 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
40664 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
40665 /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
40666  *    when the txexcessdef counter reaches half of the maximum value or the maximum value.
40667  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
40668  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
40669  */
40670 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
40671 
40672 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
40673 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
40674 /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
40675  *    txpausepacketserror counter reaches half of the maximum value or the maximum value.
40676  *  0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
40677  *  0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
40678  */
40679 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
40680 
40681 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
40682 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
40683 /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
40684  *    txvlanpackets_g counter reaches half of the maximum value or the maximum value.
40685  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
40686  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
40687  */
40688 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
40689 
40690 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
40691 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
40692 /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
40693  *    the txoversize_g counter reaches half of the maximum value or the maximum value.
40694  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
40695  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
40696  */
40697 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
40698 
40699 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
40700 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
40701 /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
40702  *    Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40703  *  0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
40704  *  0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
40705  */
40706 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
40707 
40708 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
40709 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
40710 /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
40711  *    Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40712  *  0b1..MMC Transmit LPI transition Counter Interrupt Status detected
40713  *  0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
40714  */
40715 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
40716 /*! @} */
40717 
40718 /*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
40719 /*! @{ */
40720 
40721 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
40722 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
40723 /*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
40724  *    interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
40725  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
40726  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
40727  */
40728 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
40729 
40730 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
40731 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
40732 /*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
40733  *    interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
40734  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
40735  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
40736  */
40737 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
40738 
40739 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
40740 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
40741 /*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
40742  *    when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
40743  *  0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
40744  *  0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
40745  */
40746 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
40747 
40748 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
40749 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
40750 /*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
40751  *    interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
40752  *    maximum value.
40753  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
40754  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
40755  */
40756 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
40757 
40758 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
40759 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
40760 /*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
40761  *    interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
40762  *    maximum value.
40763  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
40764  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
40765  */
40766 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
40767 
40768 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
40769 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
40770 /*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
40771  *    interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
40772  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
40773  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
40774  */
40775 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
40776 
40777 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
40778 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
40779 /*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
40780  *    the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
40781  *    maximum value.
40782  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
40783  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
40784  */
40785 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
40786 
40787 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
40788 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
40789 /*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
40790  *    when the rxrunterror counter reaches half of the maximum value or the maximum value.
40791  *  0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
40792  *  0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
40793  */
40794 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
40795 
40796 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
40797 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
40798 /*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
40799  *    interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
40800  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
40801  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
40802  */
40803 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
40804 
40805 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
40806 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
40807 /*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
40808  *    the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
40809  *    value.
40810  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
40811  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
40812  */
40813 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
40814 
40815 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
40816 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
40817 /*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
40818  *    interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
40819  *    value.
40820  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
40821  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
40822  */
40823 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
40824 
40825 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
40826 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
40827 /*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
40828  *    masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
40829  *    maximum value.
40830  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
40831  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
40832  */
40833 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
40834 
40835 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
40836 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
40837 /*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
40838  *    this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
40839  *    value or the maximum value.
40840  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
40841  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
40842  */
40843 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
40844 
40845 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
40846 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
40847 /*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
40848  *    this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
40849  *    value or the maximum value.
40850  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
40851  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
40852  */
40853 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
40854 
40855 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
40856 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
40857 /*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
40858  *    this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
40859  *    value or the maximum value.
40860  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
40861  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
40862  */
40863 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
40864 
40865 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
40866 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
40867 /*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
40868  *    Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
40869  *    maximum value or the maximum value.
40870  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
40871  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
40872  */
40873 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
40874 
40875 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
40876 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
40877 /*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
40878  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
40879  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
40880  */
40881 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
40882 
40883 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
40884 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
40885 /*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
40886  *    interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
40887  *    value.
40888  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
40889  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
40890  */
40891 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
40892 
40893 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
40894 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
40895 /*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
40896  *    interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
40897  *  0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
40898  *  0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
40899  */
40900 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
40901 
40902 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
40903 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
40904 /*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
40905  *    masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
40906  *    maximum value.
40907  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
40908  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
40909  */
40910 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
40911 
40912 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
40913 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
40914 /*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
40915  *    when the rxpausepackets counter reaches half of the maximum value or the maximum value.
40916  *  0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
40917  *  0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
40918  */
40919 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
40920 
40921 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
40922 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
40923 /*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
40924  *    interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
40925  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
40926  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
40927  */
40928 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
40929 
40930 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
40931 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
40932 /*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
40933  *    interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
40934  *    value.
40935  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
40936  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
40937  */
40938 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
40939 
40940 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
40941 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
40942 /*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
40943  *    interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
40944  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
40945  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
40946  */
40947 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
40948 
40949 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
40950 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
40951 /*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
40952  *    interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
40953  *  0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
40954  *  0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
40955  */
40956 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
40957 
40958 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
40959 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
40960 /*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
40961  *    interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
40962  *  0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
40963  *  0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
40964  */
40965 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
40966 
40967 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
40968 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
40969 /*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
40970  *    interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40971  *  0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
40972  *  0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
40973  */
40974 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
40975 
40976 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
40977 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
40978 /*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
40979  *    interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40980  *  0b0..MMC Receive LPI transition counter interrupt Mask is disabled
40981  *  0b1..MMC Receive LPI transition counter interrupt Mask is enabled
40982  */
40983 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
40984 /*! @} */
40985 
40986 /*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
40987 /*! @{ */
40988 
40989 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
40990 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
40991 /*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
40992  *    interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
40993  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
40994  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
40995  */
40996 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
40997 
40998 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
40999 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
41000 /*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
41001  *    interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
41002  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
41003  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
41004  */
41005 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
41006 
41007 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
41008 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
41009 /*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
41010  *    interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
41011  *    maximum value.
41012  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
41013  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
41014  */
41015 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
41016 
41017 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
41018 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
41019 /*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
41020  *    interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
41021  *    maximum value.
41022  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
41023  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
41024  */
41025 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
41026 
41027 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
41028 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
41029 /*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
41030  *    masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
41031  *    maximum value.
41032  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
41033  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
41034  */
41035 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
41036 
41037 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
41038 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
41039 /*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
41040  *    this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
41041  *    value or the maximum value.
41042  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
41043  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
41044  */
41045 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
41046 
41047 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
41048 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
41049 /*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
41050  *    this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
41051  *    value or the maximum value.
41052  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
41053  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
41054  */
41055 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
41056 
41057 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
41058 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
41059 /*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
41060  *    this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
41061  *    value or the maximum value.
41062  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
41063  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
41064  */
41065 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
41066 
41067 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
41068 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
41069 /*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
41070  *    Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
41071  *    maximum value or the maximum value.
41072  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
41073  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
41074  */
41075 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
41076 
41077 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
41078 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
41079 /*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
41080  *    Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
41081  *    maximum value or the maximum value.
41082  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
41083  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
41084  */
41085 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
41086 
41087 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
41088 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
41089 /*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41090  *    the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
41091  *    maximum value.
41092  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
41093  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
41094  */
41095 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
41096 
41097 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
41098 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
41099 /*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41100  *    the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
41101  *    maximum value.
41102  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
41103  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
41104  */
41105 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
41106 
41107 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
41108 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
41109 /*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41110  *    the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
41111  *    maximum value.
41112  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
41113  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
41114  */
41115 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
41116 
41117 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
41118 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
41119 /*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
41120  *    the interrupt when the txunderflowerror counter reaches half of the maximum value or the
41121  *    maximum value.
41122  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
41123  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
41124  */
41125 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
41126 
41127 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
41128 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
41129 /*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
41130  *    masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
41131  *    maximum value.
41132  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
41133  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
41134  */
41135 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
41136 
41137 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
41138 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
41139 /*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
41140  *    masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
41141  *    maximum value.
41142  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
41143  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
41144  */
41145 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
41146 
41147 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
41148 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
41149 /*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
41150  *    interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
41151  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
41152  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
41153  */
41154 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
41155 
41156 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
41157 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
41158 /*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
41159  *    the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
41160  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
41161  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
41162  */
41163 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
41164 
41165 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
41166 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
41167 /*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
41168  *    masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
41169  *    value.
41170  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
41171  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
41172  */
41173 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
41174 
41175 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
41176 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
41177 /*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
41178  *    interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
41179  *    value.
41180  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
41181  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
41182  */
41183 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
41184 
41185 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
41186 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
41187 /*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
41188  *    when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
41189  *  0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
41190  *  0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
41191  */
41192 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
41193 
41194 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
41195 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
41196 /*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
41197  *    when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
41198  *  0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
41199  *  0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
41200  */
41201 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
41202 
41203 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
41204 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
41205 /*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
41206  *    masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
41207  *    value.
41208  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
41209  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
41210  */
41211 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
41212 
41213 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
41214 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
41215 /*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
41216  *    interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
41217  *  0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
41218  *  0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
41219  */
41220 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
41221 
41222 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
41223 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
41224 /*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
41225  *    interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
41226  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
41227  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
41228  */
41229 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
41230 
41231 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
41232 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
41233 /*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
41234  *    the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
41235  *    value.
41236  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
41237  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
41238  */
41239 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
41240 
41241 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
41242 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
41243 /*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
41244  *    interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
41245  *  0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
41246  *  0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
41247  */
41248 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
41249 
41250 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
41251 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
41252 /*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
41253  *    interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
41254  *  0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
41255  *  0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
41256  */
41257 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
41258 /*! @} */
41259 
41260 /*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
41261 /*! @{ */
41262 
41263 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
41264 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
41265 /*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
41266  *    exclusive of preamble and retried bytes, in good and bad packets.
41267  */
41268 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
41269 /*! @} */
41270 
41271 /*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
41272 /*! @{ */
41273 
41274 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
41275 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
41276 /*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
41277  *    transmitted, exclusive of retried packets.
41278  */
41279 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
41280 /*! @} */
41281 
41282 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
41283 /*! @{ */
41284 
41285 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
41286 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
41287 /*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted.
41288  */
41289 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
41290 /*! @} */
41291 
41292 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
41293 /*! @{ */
41294 
41295 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
41296 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
41297 /*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted.
41298  */
41299 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
41300 /*! @} */
41301 
41302 /*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
41303 /*! @{ */
41304 
41305 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
41306 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
41307 /*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
41308  *    transmitted with length 64 bytes, exclusive of preamble and retried packets.
41309  */
41310 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
41311 /*! @} */
41312 
41313 /*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
41314 /*! @{ */
41315 
41316 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
41317 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
41318 /*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
41319  *    bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
41320  *    and retried packets.
41321  */
41322 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
41323 /*! @} */
41324 
41325 /*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
41326 /*! @{ */
41327 
41328 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
41329 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
41330 /*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
41331  *    bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
41332  *    preamble and retried packets.
41333  */
41334 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
41335 /*! @} */
41336 
41337 /*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
41338 /*! @{ */
41339 
41340 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
41341 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
41342 /*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
41343  *    bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
41344  *    preamble and retried packets.
41345  */
41346 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
41347 /*! @} */
41348 
41349 /*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
41350 /*! @{ */
41351 
41352 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
41353 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
41354 /*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
41355  *    and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
41356  *    preamble and retried packets.
41357  */
41358 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
41359 /*! @} */
41360 
41361 /*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
41362 /*! @{ */
41363 
41364 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
41365 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
41366 /*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
41367  *    and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
41368  *    preamble and retried packets.
41369  */
41370 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
41371 /*! @} */
41372 
41373 /*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
41374 /*! @{ */
41375 
41376 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
41377 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
41378 /*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted.
41379  */
41380 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
41381 /*! @} */
41382 
41383 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
41384 /*! @{ */
41385 
41386 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
41387 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
41388 /*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted.
41389  */
41390 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
41391 /*! @} */
41392 
41393 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
41394 /*! @{ */
41395 
41396 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
41397 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
41398 /*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted.
41399  */
41400 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
41401 /*! @} */
41402 
41403 /*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
41404 /*! @{ */
41405 
41406 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
41407 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
41408 /*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error.
41409  */
41410 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
41411 /*! @} */
41412 
41413 /*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
41414 /*! @{ */
41415 
41416 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
41417 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
41418 /*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
41419  *    transmitted packets after a single collision in the half-duplex mode.
41420  */
41421 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
41422 /*! @} */
41423 
41424 /*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
41425 /*! @{ */
41426 
41427 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
41428 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
41429 /*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
41430  *    transmitted packets after multiple collisions in the half-duplex mode.
41431  */
41432 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
41433 /*! @} */
41434 
41435 /*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
41436 /*! @{ */
41437 
41438 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
41439 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
41440 /*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
41441  *    a deferral in the half-duplex mode.
41442  */
41443 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
41444 /*! @} */
41445 
41446 /*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
41447 /*! @{ */
41448 
41449 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
41450 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
41451 /*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error.
41452  */
41453 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
41454 /*! @} */
41455 
41456 /*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
41457 /*! @{ */
41458 
41459 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
41460 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
41461 /*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
41462  *    because of excessive (16) collision errors.
41463  */
41464 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
41465 /*! @} */
41466 
41467 /*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
41468 /*! @{ */
41469 
41470 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
41471 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
41472 /*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
41473  *    carrier sense error (no carrier or loss of carrier).
41474  */
41475 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
41476 /*! @} */
41477 
41478 /*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
41479 /*! @{ */
41480 
41481 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
41482 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
41483 /*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets.
41484  */
41485 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
41486 /*! @} */
41487 
41488 /*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
41489 /*! @{ */
41490 
41491 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
41492 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
41493 /*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted.
41494  */
41495 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
41496 /*! @} */
41497 
41498 /*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
41499 /*! @{ */
41500 
41501 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
41502 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
41503 /*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
41504  *    because of excessive deferral error (deferred for more than two max-sized packet times).
41505  */
41506 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
41507 /*! @} */
41508 
41509 /*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
41510 /*! @{ */
41511 
41512 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
41513 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
41514 /*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted.
41515  */
41516 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
41517 /*! @} */
41518 
41519 /*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
41520 /*! @{ */
41521 
41522 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
41523 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
41524 /*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted.
41525  */
41526 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
41527 /*! @} */
41528 
41529 /*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
41530 /*! @{ */
41531 
41532 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
41533 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
41534 /*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
41535  *    errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
41536  *    2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
41537  */
41538 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
41539 /*! @} */
41540 
41541 /*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
41542 /*! @{ */
41543 
41544 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
41545 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
41546 /*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received.
41547  */
41548 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
41549 /*! @} */
41550 
41551 /*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
41552 /*! @{ */
41553 
41554 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
41555 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
41556 /*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
41557  *    of preamble, in good and bad packets.
41558  */
41559 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
41560 /*! @} */
41561 
41562 /*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
41563 /*! @{ */
41564 
41565 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
41566 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
41567 /*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets.
41568  */
41569 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
41570 /*! @} */
41571 
41572 /*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
41573 /*! @{ */
41574 
41575 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
41576 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
41577 /*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received.
41578  */
41579 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
41580 /*! @} */
41581 
41582 /*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
41583 /*! @{ */
41584 
41585 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
41586 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
41587 /*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received.
41588  */
41589 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
41590 /*! @} */
41591 
41592 /*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
41593 /*! @{ */
41594 
41595 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
41596 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
41597 /*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error.
41598  */
41599 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
41600 /*! @} */
41601 
41602 /*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
41603 /*! @{ */
41604 
41605 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
41606 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
41607 /*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error.
41608  */
41609 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
41610 /*! @} */
41611 
41612 /*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
41613 /*! @{ */
41614 
41615 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
41616 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
41617 /*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
41618  *    (length less than 64 bytes and CRC error) error.
41619  */
41620 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
41621 /*! @} */
41622 
41623 /*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
41624 /*! @{ */
41625 
41626 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
41627 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
41628 /*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
41629  *    with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
41630  *    error.
41631  */
41632 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
41633 /*! @} */
41634 
41635 /*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
41636 /*! @{ */
41637 
41638 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
41639 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
41640 /*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
41641  *    length less than 64 bytes, without any errors.
41642  */
41643 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
41644 /*! @} */
41645 
41646 /*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
41647 /*! @{ */
41648 
41649 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
41650 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
41651 /*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
41652  *    errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
41653  *    packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
41654  */
41655 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
41656 /*! @} */
41657 
41658 /*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
41659 /*! @{ */
41660 
41661 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
41662 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
41663 /*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
41664  *    packets received with length 64 bytes, exclusive of the preamble.
41665  */
41666 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
41667 /*! @} */
41668 
41669 /*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
41670 /*! @{ */
41671 
41672 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
41673 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
41674 /*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
41675  *    bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
41676  */
41677 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
41678 /*! @} */
41679 
41680 /*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
41681 /*! @{ */
41682 
41683 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
41684 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
41685 /*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
41686  *    bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
41687  *    preamble.
41688  */
41689 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
41690 /*! @} */
41691 
41692 /*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
41693 /*! @{ */
41694 
41695 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
41696 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
41697 /*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
41698  *    bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
41699  *    preamble.
41700  */
41701 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
41702 /*! @} */
41703 
41704 /*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
41705 /*! @{ */
41706 
41707 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
41708 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
41709 /*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
41710  *    and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
41711  *    preamble.
41712  */
41713 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
41714 /*! @} */
41715 
41716 /*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
41717 /*! @{ */
41718 
41719 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
41720 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
41721 /*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
41722  *    packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
41723  *    preamble.
41724  */
41725 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
41726 /*! @} */
41727 
41728 /*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
41729 /*! @{ */
41730 
41731 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
41732 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
41733 /*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received.
41734  */
41735 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
41736 /*! @} */
41737 
41738 /*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
41739 /*! @{ */
41740 
41741 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
41742 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
41743 /*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
41744  *    length error (Length Type field not equal to packet size), for all packets with valid length field.
41745  */
41746 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
41747 /*! @} */
41748 
41749 /*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
41750 /*! @{ */
41751 
41752 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
41753 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
41754 /*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
41755  *    with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
41756  */
41757 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
41758 /*! @} */
41759 
41760 /*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
41761 /*! @{ */
41762 
41763 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
41764 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
41765 /*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received.
41766  */
41767 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
41768 /*! @} */
41769 
41770 /*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
41771 /*! @{ */
41772 
41773 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
41774 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
41775 /*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow.
41776  */
41777 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
41778 /*! @} */
41779 
41780 /*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
41781 /*! @{ */
41782 
41783 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
41784 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
41785 /*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received.
41786  */
41787 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
41788 /*! @} */
41789 
41790 /*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
41791 /*! @{ */
41792 
41793 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
41794 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
41795 /*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
41796  *    error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
41797  *    JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
41798  *    WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
41799  *    MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
41800  */
41801 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
41802 /*! @} */
41803 
41804 /*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
41805 /*! @{ */
41806 
41807 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
41808 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
41809 /*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
41810  *    Receive error or Packet Extension error on the GMII or MII interface.
41811  */
41812 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
41813 /*! @} */
41814 
41815 /*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
41816 /*! @{ */
41817 
41818 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
41819 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
41820 /*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received.
41821  */
41822 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
41823 /*! @} */
41824 
41825 /*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
41826 /*! @{ */
41827 
41828 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
41829 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
41830 /*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted.
41831  */
41832 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
41833 /*! @} */
41834 
41835 /*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
41836 /*! @{ */
41837 
41838 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
41839 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
41840 /*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred.
41841  */
41842 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
41843 /*! @} */
41844 
41845 /*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
41846 /*! @{ */
41847 
41848 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
41849 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
41850 /*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted.
41851  */
41852 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
41853 /*! @} */
41854 
41855 /*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
41856 /*! @{ */
41857 
41858 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
41859 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
41860 /*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred.
41861  */
41862 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
41863 /*! @} */
41864 
41865 /*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
41866 /*! @{ */
41867 
41868 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
41869 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
41870 /*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
41871  *    interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
41872  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
41873  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
41874  */
41875 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
41876 
41877 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
41878 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
41879 /*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
41880  *    masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
41881  *    maximum value.
41882  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
41883  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
41884  */
41885 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
41886 
41887 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
41888 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
41889 /*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
41890  *    masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
41891  *    maximum value.
41892  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
41893  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
41894  */
41895 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
41896 
41897 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
41898 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
41899 /*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
41900  *    the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
41901  *    maximum value.
41902  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
41903  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
41904  */
41905 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
41906 
41907 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
41908 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
41909 /*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
41910  *    this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
41911  *    value or the maximum value.
41912  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
41913  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
41914  */
41915 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
41916 
41917 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
41918 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
41919 /*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
41920  *    interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
41921  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
41922  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
41923  */
41924 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
41925 
41926 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
41927 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
41928 /*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
41929  *    masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
41930  *    maximum value.
41931  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
41932  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
41933  */
41934 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
41935 
41936 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
41937 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
41938 /*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
41939  *    masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
41940  *    maximum value.
41941  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
41942  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
41943  */
41944 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
41945 
41946 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
41947 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
41948 /*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
41949  *    interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
41950  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
41951  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
41952  */
41953 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
41954 
41955 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
41956 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
41957 /*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
41958  *    interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
41959  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
41960  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
41961  */
41962 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
41963 
41964 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
41965 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
41966 /*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
41967  *    interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
41968  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
41969  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
41970  */
41971 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
41972 
41973 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
41974 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
41975 /*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
41976  *    interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
41977  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
41978  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
41979  */
41980 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
41981 
41982 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
41983 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
41984 /*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
41985  *    interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
41986  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
41987  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
41988  */
41989 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
41990 
41991 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
41992 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
41993 /*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
41994  *    interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
41995  *    value.
41996  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
41997  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
41998  */
41999 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
42000 
42001 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
42002 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
42003 /*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
42004  *    interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
42005  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
42006  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
42007  */
42008 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
42009 
42010 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
42011 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
42012 /*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
42013  *    the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
42014  *    maximum value.
42015  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
42016  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
42017  */
42018 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
42019 
42020 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
42021 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
42022 /*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
42023  *    the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
42024  *    maximum value.
42025  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
42026  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
42027  */
42028 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
42029 
42030 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
42031 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
42032 /*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
42033  *    the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
42034  *    maximum value.
42035  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
42036  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
42037  */
42038 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
42039 
42040 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
42041 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
42042 /*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
42043  *    this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
42044  *    value or the maximum value.
42045  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
42046  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
42047  */
42048 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
42049 
42050 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
42051 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
42052 /*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
42053  *    interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
42054  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
42055  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
42056  */
42057 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
42058 
42059 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
42060 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
42061 /*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
42062  *    interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
42063  *    value.
42064  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
42065  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
42066  */
42067 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
42068 
42069 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
42070 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
42071 /*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
42072  *    masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
42073  *    maximum value.
42074  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
42075  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
42076  */
42077 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
42078 
42079 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
42080 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
42081 /*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
42082  *    interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
42083  *    value.
42084  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
42085  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
42086  */
42087 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
42088 
42089 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
42090 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
42091 /*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
42092  *    interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
42093  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
42094  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
42095  */
42096 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
42097 
42098 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
42099 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
42100 /*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
42101  *    interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
42102  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
42103  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
42104  */
42105 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
42106 
42107 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
42108 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
42109 /*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
42110  *    interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
42111  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
42112  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
42113  */
42114 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
42115 
42116 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
42117 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
42118 /*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
42119  *    interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
42120  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
42121  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
42122  */
42123 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
42124 
42125 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
42126 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
42127 /*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
42128  *    interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
42129  *    value.
42130  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
42131  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
42132  */
42133 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
42134 /*! @} */
42135 
42136 /*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
42137 /*! @{ */
42138 
42139 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
42140 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
42141 /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
42142  *    rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
42143  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
42144  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
42145  */
42146 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
42147 
42148 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
42149 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
42150 /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
42151  *    when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
42152  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
42153  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
42154  */
42155 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
42156 
42157 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
42158 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
42159 /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
42160  *    when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
42161  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
42162  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
42163  */
42164 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
42165 
42166 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
42167 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
42168 /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
42169  *    the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
42170  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
42171  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
42172  */
42173 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
42174 
42175 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
42176 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
42177 /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
42178  *    is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
42179  *    value.
42180  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
42181  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
42182  */
42183 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
42184 
42185 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
42186 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
42187 /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
42188  *    rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
42189  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
42190  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
42191  */
42192 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
42193 
42194 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
42195 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
42196 /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
42197  *    when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
42198  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
42199  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
42200  */
42201 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
42202 
42203 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
42204 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
42205 /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
42206  *    when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
42207  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
42208  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
42209  */
42210 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
42211 
42212 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
42213 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
42214 /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
42215  *    rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
42216  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
42217  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
42218  */
42219 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
42220 
42221 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
42222 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
42223 /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
42224  *    rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
42225  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
42226  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
42227  */
42228 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
42229 
42230 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
42231 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
42232 /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
42233  *    rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
42234  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
42235  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
42236  */
42237 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
42238 
42239 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
42240 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
42241 /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
42242  *    rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
42243  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
42244  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
42245  */
42246 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
42247 
42248 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
42249 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
42250 /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
42251  *    rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
42252  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
42253  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
42254  */
42255 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
42256 
42257 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
42258 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
42259 /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
42260  *    rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
42261  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
42262  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
42263  */
42264 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
42265 
42266 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
42267 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
42268 /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
42269  *    rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
42270  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
42271  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
42272  */
42273 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
42274 
42275 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
42276 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
42277 /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
42278  *    the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
42279  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
42280  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
42281  */
42282 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
42283 
42284 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
42285 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
42286 /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
42287  *    the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
42288  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
42289  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
42290  */
42291 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
42292 
42293 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
42294 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
42295 /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
42296  *    the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
42297  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
42298  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
42299  */
42300 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
42301 
42302 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
42303 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
42304 /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
42305  *    is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
42306  *    value.
42307  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
42308  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
42309  */
42310 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
42311 
42312 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
42313 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
42314 /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
42315  *    rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
42316  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
42317  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
42318  */
42319 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
42320 
42321 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
42322 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
42323 /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
42324  *    the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
42325  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
42326  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
42327  */
42328 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
42329 
42330 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
42331 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
42332 /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
42333  *    the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
42334  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
42335  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
42336  */
42337 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
42338 
42339 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
42340 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
42341 /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
42342  *    rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
42343  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
42344  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
42345  */
42346 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
42347 
42348 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
42349 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
42350 /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
42351  *    rxudp_err_octets counter reaches half of the maximum value or the maximum value.
42352  *  0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
42353  *  0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
42354  */
42355 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
42356 
42357 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
42358 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
42359 /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
42360  *    rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
42361  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
42362  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
42363  */
42364 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
42365 
42366 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
42367 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
42368 /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
42369  *    rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
42370  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
42371  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
42372  */
42373 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
42374 
42375 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
42376 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
42377 /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
42378  *    rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
42379  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
42380  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
42381  */
42382 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
42383 
42384 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
42385 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
42386 /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
42387  *    rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
42388  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
42389  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
42390  */
42391 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
42392 /*! @} */
42393 
42394 /*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
42395 /*! @{ */
42396 
42397 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
42398 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
42399 /*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
42400  */
42401 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
42402 /*! @} */
42403 
42404 /*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
42405 /*! @{ */
42406 
42407 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
42408 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
42409 /*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
42410  *    received with header (checksum, length, or version mismatch) errors.
42411  */
42412 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
42413 /*! @} */
42414 
42415 /*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
42416 /*! @{ */
42417 
42418 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
42419 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
42420 /*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
42421  *    received that did not have a TCP, UDP, or ICMP payload.
42422  */
42423 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
42424 /*! @} */
42425 
42426 /*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
42427 /*! @{ */
42428 
42429 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
42430 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
42431 /*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation.
42432  */
42433 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
42434 /*! @} */
42435 
42436 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
42437 /*! @{ */
42438 
42439 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
42440 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
42441 /*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
42442  *    IPv4 datagrams received that had a UDP payload with checksum disabled.
42443  */
42444 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
42445 /*! @} */
42446 
42447 /*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
42448 /*! @{ */
42449 
42450 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
42451 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
42452 /*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload.
42453  */
42454 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
42455 /*! @} */
42456 
42457 /*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
42458 /*! @{ */
42459 
42460 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
42461 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
42462 /*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
42463  *    received with header (length or version mismatch) errors.
42464  */
42465 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
42466 /*! @} */
42467 
42468 /*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
42469 /*! @{ */
42470 
42471 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
42472 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
42473 /*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
42474  *    received that did not have a TCP, UDP, or ICMP payload.
42475  */
42476 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
42477 /*! @} */
42478 
42479 /*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
42480 /*! @{ */
42481 
42482 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
42483 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
42484 /*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload.
42485  */
42486 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
42487 /*! @} */
42488 
42489 /*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
42490 /*! @{ */
42491 
42492 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
42493 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
42494 /*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
42495  *    whose UDP payload has a checksum error.
42496  */
42497 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
42498 /*! @} */
42499 
42500 /*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
42501 /*! @{ */
42502 
42503 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
42504 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
42505 /*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload.
42506  */
42507 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
42508 /*! @} */
42509 
42510 /*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
42511 /*! @{ */
42512 
42513 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
42514 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
42515 /*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
42516  *    whose TCP payload has a checksum error.
42517  */
42518 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
42519 /*! @} */
42520 
42521 /*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
42522 /*! @{ */
42523 
42524 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
42525 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
42526 /*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload.
42527  */
42528 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
42529 /*! @} */
42530 
42531 /*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
42532 /*! @{ */
42533 
42534 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
42535 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
42536 /*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
42537  *    received whose ICMP payload has a checksum error.
42538  */
42539 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
42540 /*! @} */
42541 
42542 /*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
42543 /*! @{ */
42544 
42545 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
42546 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
42547 /*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
42548  *    datagrams encapsulating TCP, UDP, or ICMP data.
42549  */
42550 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
42551 /*! @} */
42552 
42553 /*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
42554 /*! @{ */
42555 
42556 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
42557 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
42558 /*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
42559  *    in IPv4 datagrams with header errors (checksum, length, version mismatch).
42560  */
42561 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
42562 /*! @} */
42563 
42564 /*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
42565 /*! @{ */
42566 
42567 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
42568 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
42569 /*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
42570  *    datagrams that did not have a TCP, UDP, or ICMP payload.
42571  */
42572 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
42573 /*! @} */
42574 
42575 /*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
42576 /*! @{ */
42577 
42578 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
42579 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
42580 /*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams.
42581  */
42582 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
42583 /*! @} */
42584 
42585 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
42586 /*! @{ */
42587 
42588 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
42589 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
42590 /*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
42591  *    received in a UDP segment that had the UDP checksum disabled.
42592  */
42593 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
42594 /*! @} */
42595 
42596 /*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
42597 /*! @{ */
42598 
42599 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
42600 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
42601 /*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
42602  *    datagrams encapsulating TCP, UDP, or ICMP data.
42603  */
42604 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
42605 /*! @} */
42606 
42607 /*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
42608 /*! @{ */
42609 
42610 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
42611 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
42612 /*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
42613  *    in IPv6 datagrams with header errors (length, version mismatch).
42614  */
42615 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
42616 /*! @} */
42617 
42618 /*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
42619 /*! @{ */
42620 
42621 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
42622 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
42623 /*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
42624  *    datagrams that did not have a TCP, UDP, or ICMP payload.
42625  */
42626 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
42627 /*! @} */
42628 
42629 /*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
42630 /*! @{ */
42631 
42632 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
42633 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
42634 /*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment.
42635  */
42636 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
42637 /*! @} */
42638 
42639 /*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
42640 /*! @{ */
42641 
42642 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
42643 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
42644 /*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors.
42645  */
42646 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
42647 /*! @} */
42648 
42649 /*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
42650 /*! @{ */
42651 
42652 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
42653 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
42654 /*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment.
42655  */
42656 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
42657 /*! @} */
42658 
42659 /*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
42660 /*! @{ */
42661 
42662 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
42663 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
42664 /*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors.
42665  */
42666 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
42667 /*! @} */
42668 
42669 /*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
42670 /*! @{ */
42671 
42672 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
42673 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
42674 /*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment.
42675  */
42676 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
42677 /*! @} */
42678 
42679 /*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
42680 /*! @{ */
42681 
42682 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
42683 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
42684 /*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors.
42685  */
42686 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
42687 /*! @} */
42688 
42689 /*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
42690 /*! @{ */
42691 
42692 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
42693 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
42694 /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
42695  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42696  *  0b1..MMC Tx FPE Fragment Counter Interrupt status detected
42697  *  0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
42698  */
42699 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
42700 
42701 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
42702 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
42703 /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
42704  *    counter reaches half of the maximum value or the maximum value.
42705  *  0b1..MMC Tx Hold Request Counter Interrupt Status detected
42706  *  0b0..MMC Tx Hold Request Counter Interrupt Status not detected
42707  */
42708 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
42709 /*! @} */
42710 
42711 /*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
42712 /*! @{ */
42713 
42714 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
42715 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
42716 /*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
42717  *    the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42718  *  0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
42719  *  0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
42720  */
42721 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
42722 
42723 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
42724 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
42725 /*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
42726  *    when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
42727  *  0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
42728  *  0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
42729  */
42730 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
42731 /*! @} */
42732 
42733 /*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
42734 /*! @{ */
42735 
42736 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
42737 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
42738 /*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
42739  *    been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
42740  *    during FPE Enabled configuration.
42741  */
42742 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
42743 /*! @} */
42744 
42745 /*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
42746 /*! @{ */
42747 
42748 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
42749 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
42750 /*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC.
42751  */
42752 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
42753 /*! @} */
42754 
42755 /*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
42756 /*! @{ */
42757 
42758 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
42759 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
42760 /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
42761  *    Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
42762  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
42763  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
42764  */
42765 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
42766 
42767 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
42768 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
42769 /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
42770  *    Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
42771  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
42772  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
42773  */
42774 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
42775 
42776 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
42777 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
42778 /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
42779  *    Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
42780  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
42781  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
42782  */
42783 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
42784 
42785 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
42786 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
42787 /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
42788  *    Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42789  *  0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
42790  *  0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
42791  */
42792 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
42793 /*! @} */
42794 
42795 /*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
42796 /*! @{ */
42797 
42798 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
42799 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
42800 /*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
42801  *    interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
42802  *    maximum value.
42803  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
42804  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
42805  */
42806 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
42807 
42808 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
42809 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
42810 /*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
42811  *    when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
42812  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
42813  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
42814  */
42815 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
42816 
42817 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
42818 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
42819 /*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
42820  *    when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
42821  *    value.
42822  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
42823  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
42824  */
42825 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
42826 
42827 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
42828 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
42829 /*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
42830  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42831  *  0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
42832  *  0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
42833  */
42834 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
42835 /*! @} */
42836 
42837 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
42838 /*! @{ */
42839 
42840 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
42841 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
42842 /*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
42843  *    reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
42844  */
42845 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
42846 /*! @} */
42847 
42848 /*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
42849 /*! @{ */
42850 
42851 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
42852 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
42853 /*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
42854  *    unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
42855  *    was no preceding preempted frame.
42856  */
42857 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
42858 /*! @} */
42859 
42860 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
42861 /*! @{ */
42862 
42863 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
42864 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
42865 /*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
42866  *    successfully reassembled and delivered to MAC.
42867  */
42868 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
42869 /*! @} */
42870 
42871 /*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
42872 /*! @{ */
42873 
42874 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
42875 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
42876 /*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
42877  *    due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
42878  *    Enabled configuration.
42879  */
42880 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
42881 /*! @} */
42882 
42883 /*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
42884 /*! @{ */
42885 
42886 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK  (0x1U)
42887 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
42888 /*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42889  *    Address matching is enabled for IPv6 packets.
42890  *  0b0..Layer 3 Protocol is disabled
42891  *  0b1..Layer 3 Protocol is enabled
42892  */
42893 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
42894 
42895 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK  (0x4U)
42896 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
42897 /*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
42898  *  0b0..Layer 3 IP SA Match is disabled
42899  *  0b1..Layer 3 IP SA Match is enabled
42900  */
42901 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
42902 
42903 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
42904 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
42905 /*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
42906  *    field is enabled for inverse matching.
42907  *  0b0..Layer 3 IP SA Inverse Match is disabled
42908  *  0b1..Layer 3 IP SA Inverse Match is enabled
42909  */
42910 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
42911 
42912 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK  (0x10U)
42913 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
42914 /*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
42915  *  0b0..Layer 3 IP DA Match is disabled
42916  *  0b1..Layer 3 IP DA Match is enabled
42917  */
42918 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
42919 
42920 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
42921 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
42922 /*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
42923  *    Address field is enabled for inverse matching.
42924  *  0b0..Layer 3 IP DA Inverse Match is disabled
42925  *  0b1..Layer 3 IP DA Inverse Match is enabled
42926  */
42927 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
42928 
42929 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
42930 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
42931 /*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
42932  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
42933  */
42934 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
42935 
42936 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
42937 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
42938 /*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
42939  *    bits of IP Destination Address that are matched in the IPv4 packets.
42940  */
42941 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
42942 
42943 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK  (0x10000U)
42944 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
42945 /*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
42946  *    fields of UDP packets are used for matching.
42947  *  0b0..Layer 4 Protocol is disabled
42948  *  0b1..Layer 4 Protocol is enabled
42949  */
42950 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
42951 
42952 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK  (0x40000U)
42953 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
42954 /*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
42955  *  0b0..Layer 4 Source Port Match is disabled
42956  *  0b1..Layer 4 Source Port Match is enabled
42957  */
42958 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
42959 
42960 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
42961 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
42962 /*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
42963  *    number field is enabled for inverse matching.
42964  *  0b0..Layer 4 Source Port Inverse Match is disabled
42965  *  0b1..Layer 4 Source Port Inverse Match is enabled
42966  */
42967 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
42968 
42969 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK  (0x100000U)
42970 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
42971 /*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
42972  *    Port number field is enabled for matching.
42973  *  0b0..Layer 4 Destination Port Match is disabled
42974  *  0b1..Layer 4 Destination Port Match is enabled
42975  */
42976 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
42977 
42978 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
42979 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
42980 /*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
42981  *    Destination Port number field is enabled for inverse matching.
42982  *  0b0..Layer 4 Destination Port Inverse Match is disabled
42983  *  0b1..Layer 4 Destination Port Inverse Match is enabled
42984  */
42985 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
42986 
42987 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK  (0x7000000U)
42988 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
42989 /*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
42990  *    to which the packet passed by this filter is routed.
42991  */
42992 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
42993 
42994 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
42995 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
42996 /*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
42997  *    number for the packet that is passed by this L3_L4 filter.
42998  *  0b0..DMA Channel Select is disabled
42999  *  0b1..DMA Channel Select is enabled
43000  */
43001 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
43002 /*! @} */
43003 
43004 /*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
43005 /*! @{ */
43006 
43007 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK  (0xFFFFU)
43008 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
43009 /*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43010  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43011  *    Source Port Number field in the IPv4 or IPv6 packets.
43012  */
43013 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
43014 
43015 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK  (0xFFFF0000U)
43016 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
43017 /*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43018  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43019  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43020  */
43021 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
43022 /*! @} */
43023 
43024 /*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
43025 /*! @{ */
43026 
43027 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
43028 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
43029 /*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43030  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43031  *    Address field in the IPv6 packets.
43032  */
43033 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
43034 /*! @} */
43035 
43036 /*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
43037 /*! @{ */
43038 
43039 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
43040 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
43041 /*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43042  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43043  *    Address field in the IPv6 packets.
43044  */
43045 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
43046 /*! @} */
43047 
43048 /*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
43049 /*! @{ */
43050 
43051 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
43052 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
43053 /*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43054  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43055  *    Address field in the IPv6 packets.
43056  */
43057 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
43058 /*! @} */
43059 
43060 /*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
43061 /*! @{ */
43062 
43063 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
43064 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
43065 /*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43066  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43067  *    Address field in the IPv6 packets.
43068  */
43069 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
43070 /*! @} */
43071 
43072 /*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
43073 /*! @{ */
43074 
43075 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK  (0x1U)
43076 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
43077 /*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43078  *    Address matching is enabled for IPv6 packets.
43079  *  0b0..Layer 3 Protocol is disabled
43080  *  0b1..Layer 3 Protocol is enabled
43081  */
43082 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
43083 
43084 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK  (0x4U)
43085 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
43086 /*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43087  *  0b0..Layer 3 IP SA Match is disabled
43088  *  0b1..Layer 3 IP SA Match is enabled
43089  */
43090 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
43091 
43092 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
43093 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
43094 /*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43095  *    field is enabled for inverse matching.
43096  *  0b0..Layer 3 IP SA Inverse Match is disabled
43097  *  0b1..Layer 3 IP SA Inverse Match is enabled
43098  */
43099 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
43100 
43101 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK  (0x10U)
43102 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
43103 /*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43104  *  0b0..Layer 3 IP DA Match is disabled
43105  *  0b1..Layer 3 IP DA Match is enabled
43106  */
43107 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
43108 
43109 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
43110 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
43111 /*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43112  *    Address field is enabled for inverse matching.
43113  *  0b0..Layer 3 IP DA Inverse Match is disabled
43114  *  0b1..Layer 3 IP DA Inverse Match is enabled
43115  */
43116 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
43117 
43118 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
43119 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
43120 /*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43121  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43122  */
43123 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
43124 
43125 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
43126 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
43127 /*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43128  *    bits of IP Destination Address that are matched in the IPv4 packets.
43129  */
43130 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
43131 
43132 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK  (0x10000U)
43133 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
43134 /*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43135  *    fields of UDP packets are used for matching.
43136  *  0b0..Layer 4 Protocol is disabled
43137  *  0b1..Layer 4 Protocol is enabled
43138  */
43139 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
43140 
43141 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK  (0x40000U)
43142 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
43143 /*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43144  *  0b0..Layer 4 Source Port Match is disabled
43145  *  0b1..Layer 4 Source Port Match is enabled
43146  */
43147 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
43148 
43149 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
43150 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
43151 /*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43152  *    number field is enabled for inverse matching.
43153  *  0b0..Layer 4 Source Port Inverse Match is disabled
43154  *  0b1..Layer 4 Source Port Inverse Match is enabled
43155  */
43156 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
43157 
43158 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK  (0x100000U)
43159 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
43160 /*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43161  *    Port number field is enabled for matching.
43162  *  0b0..Layer 4 Destination Port Match is disabled
43163  *  0b1..Layer 4 Destination Port Match is enabled
43164  */
43165 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
43166 
43167 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
43168 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
43169 /*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43170  *    Destination Port number field is enabled for inverse matching.
43171  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43172  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43173  */
43174 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
43175 
43176 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK  (0x7000000U)
43177 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
43178 /*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43179  *    to which the packet passed by this filter is routed.
43180  */
43181 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
43182 
43183 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
43184 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
43185 /*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43186  *    number for the packet that is passed by this L3_L4 filter.
43187  *  0b0..DMA Channel Select is disabled
43188  *  0b1..DMA Channel Select is enabled
43189  */
43190 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
43191 /*! @} */
43192 
43193 /*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
43194 /*! @{ */
43195 
43196 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK  (0xFFFFU)
43197 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
43198 /*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43199  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43200  *    Source Port Number field in the IPv4 or IPv6 packets.
43201  */
43202 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
43203 
43204 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK  (0xFFFF0000U)
43205 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
43206 /*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43207  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43208  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43209  */
43210 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
43211 /*! @} */
43212 
43213 /*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
43214 /*! @{ */
43215 
43216 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
43217 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
43218 /*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43219  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43220  *    Address field in the IPv6 packets.
43221  */
43222 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
43223 /*! @} */
43224 
43225 /*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
43226 /*! @{ */
43227 
43228 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
43229 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
43230 /*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43231  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43232  *    Address field in the IPv6 packets.
43233  */
43234 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
43235 /*! @} */
43236 
43237 /*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
43238 /*! @{ */
43239 
43240 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
43241 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
43242 /*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43243  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43244  *    Address field in the IPv6 packets.
43245  */
43246 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
43247 /*! @} */
43248 
43249 /*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
43250 /*! @{ */
43251 
43252 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
43253 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
43254 /*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43255  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43256  *    Address field in the IPv6 packets.
43257  */
43258 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
43259 /*! @} */
43260 
43261 /*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
43262 /*! @{ */
43263 
43264 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK  (0x1U)
43265 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
43266 /*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43267  *    Address matching is enabled for IPv6 packets.
43268  *  0b0..Layer 3 Protocol is disabled
43269  *  0b1..Layer 3 Protocol is enabled
43270  */
43271 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
43272 
43273 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK  (0x4U)
43274 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
43275 /*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43276  *  0b0..Layer 3 IP SA Match is disabled
43277  *  0b1..Layer 3 IP SA Match is enabled
43278  */
43279 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
43280 
43281 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
43282 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
43283 /*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43284  *    field is enabled for inverse matching.
43285  *  0b0..Layer 3 IP SA Inverse Match is disabled
43286  *  0b1..Layer 3 IP SA Inverse Match is enabled
43287  */
43288 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
43289 
43290 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK  (0x10U)
43291 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
43292 /*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43293  *  0b0..Layer 3 IP DA Match is disabled
43294  *  0b1..Layer 3 IP DA Match is enabled
43295  */
43296 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
43297 
43298 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
43299 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
43300 /*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43301  *    Address field is enabled for inverse matching.
43302  *  0b0..Layer 3 IP DA Inverse Match is disabled
43303  *  0b1..Layer 3 IP DA Inverse Match is enabled
43304  */
43305 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
43306 
43307 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
43308 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
43309 /*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43310  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43311  */
43312 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
43313 
43314 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
43315 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
43316 /*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43317  *    bits of IP Destination Address that are matched in the IPv4 packets.
43318  */
43319 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
43320 
43321 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK  (0x10000U)
43322 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
43323 /*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43324  *    fields of UDP packets are used for matching.
43325  *  0b0..Layer 4 Protocol is disabled
43326  *  0b1..Layer 4 Protocol is enabled
43327  */
43328 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
43329 
43330 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK  (0x40000U)
43331 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
43332 /*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43333  *  0b0..Layer 4 Source Port Match is disabled
43334  *  0b1..Layer 4 Source Port Match is enabled
43335  */
43336 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
43337 
43338 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
43339 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
43340 /*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43341  *    number field is enabled for inverse matching.
43342  *  0b0..Layer 4 Source Port Inverse Match is disabled
43343  *  0b1..Layer 4 Source Port Inverse Match is enabled
43344  */
43345 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
43346 
43347 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK  (0x100000U)
43348 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
43349 /*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43350  *    Port number field is enabled for matching.
43351  *  0b0..Layer 4 Destination Port Match is disabled
43352  *  0b1..Layer 4 Destination Port Match is enabled
43353  */
43354 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
43355 
43356 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
43357 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
43358 /*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43359  *    Destination Port number field is enabled for inverse matching.
43360  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43361  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43362  */
43363 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
43364 
43365 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK  (0x7000000U)
43366 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
43367 /*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43368  *    to which the packet passed by this filter is routed.
43369  */
43370 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
43371 
43372 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
43373 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
43374 /*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43375  *    number for the packet that is passed by this L3_L4 filter.
43376  *  0b0..DMA Channel Select is disabled
43377  *  0b1..DMA Channel Select is enabled
43378  */
43379 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
43380 /*! @} */
43381 
43382 /*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
43383 /*! @{ */
43384 
43385 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK  (0xFFFFU)
43386 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
43387 /*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43388  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43389  *    Source Port Number field in the IPv4 or IPv6 packets.
43390  */
43391 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
43392 
43393 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK  (0xFFFF0000U)
43394 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
43395 /*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43396  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43397  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43398  */
43399 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
43400 /*! @} */
43401 
43402 /*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
43403 /*! @{ */
43404 
43405 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
43406 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
43407 /*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43408  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43409  *    Address field in the IPv6 packets.
43410  */
43411 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
43412 /*! @} */
43413 
43414 /*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
43415 /*! @{ */
43416 
43417 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
43418 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
43419 /*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43420  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43421  *    Address field in the IPv6 packets.
43422  */
43423 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
43424 /*! @} */
43425 
43426 /*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
43427 /*! @{ */
43428 
43429 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
43430 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
43431 /*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43432  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43433  *    Address field in the IPv6 packets.
43434  */
43435 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
43436 /*! @} */
43437 
43438 /*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
43439 /*! @{ */
43440 
43441 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
43442 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
43443 /*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43444  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43445  *    Address field in the IPv6 packets.
43446  */
43447 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
43448 /*! @} */
43449 
43450 /*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
43451 /*! @{ */
43452 
43453 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK  (0x1U)
43454 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
43455 /*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43456  *    Address matching is enabled for IPv6 packets.
43457  *  0b0..Layer 3 Protocol is disabled
43458  *  0b1..Layer 3 Protocol is enabled
43459  */
43460 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
43461 
43462 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK  (0x4U)
43463 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
43464 /*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43465  *  0b0..Layer 3 IP SA Match is disabled
43466  *  0b1..Layer 3 IP SA Match is enabled
43467  */
43468 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
43469 
43470 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
43471 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
43472 /*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43473  *    field is enabled for inverse matching.
43474  *  0b0..Layer 3 IP SA Inverse Match is disabled
43475  *  0b1..Layer 3 IP SA Inverse Match is enabled
43476  */
43477 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
43478 
43479 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK  (0x10U)
43480 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
43481 /*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43482  *  0b0..Layer 3 IP DA Match is disabled
43483  *  0b1..Layer 3 IP DA Match is enabled
43484  */
43485 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
43486 
43487 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
43488 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
43489 /*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43490  *    Address field is enabled for inverse matching.
43491  *  0b0..Layer 3 IP DA Inverse Match is disabled
43492  *  0b1..Layer 3 IP DA Inverse Match is enabled
43493  */
43494 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
43495 
43496 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
43497 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
43498 /*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43499  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43500  */
43501 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
43502 
43503 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
43504 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
43505 /*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43506  *    bits of IP Destination Address that are matched in the IPv4 packets.
43507  */
43508 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
43509 
43510 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK  (0x10000U)
43511 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
43512 /*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43513  *    fields of UDP packets are used for matching.
43514  *  0b0..Layer 4 Protocol is disabled
43515  *  0b1..Layer 4 Protocol is enabled
43516  */
43517 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
43518 
43519 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK  (0x40000U)
43520 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
43521 /*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43522  *  0b0..Layer 4 Source Port Match is disabled
43523  *  0b1..Layer 4 Source Port Match is enabled
43524  */
43525 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
43526 
43527 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
43528 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
43529 /*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43530  *    number field is enabled for inverse matching.
43531  *  0b0..Layer 4 Source Port Inverse Match is disabled
43532  *  0b1..Layer 4 Source Port Inverse Match is enabled
43533  */
43534 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
43535 
43536 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK  (0x100000U)
43537 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
43538 /*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43539  *    Port number field is enabled for matching.
43540  *  0b0..Layer 4 Destination Port Match is disabled
43541  *  0b1..Layer 4 Destination Port Match is enabled
43542  */
43543 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
43544 
43545 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
43546 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
43547 /*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43548  *    Destination Port number field is enabled for inverse matching.
43549  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43550  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43551  */
43552 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
43553 
43554 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK  (0x7000000U)
43555 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
43556 /*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43557  *    to which the packet passed by this filter is routed.
43558  */
43559 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
43560 
43561 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
43562 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
43563 /*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43564  *    number for the packet that is passed by this L3_L4 filter.
43565  *  0b0..DMA Channel Select is disabled
43566  *  0b1..DMA Channel Select is enabled
43567  */
43568 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
43569 /*! @} */
43570 
43571 /*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
43572 /*! @{ */
43573 
43574 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK  (0xFFFFU)
43575 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
43576 /*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43577  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43578  *    Source Port Number field in the IPv4 or IPv6 packets.
43579  */
43580 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
43581 
43582 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK  (0xFFFF0000U)
43583 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
43584 /*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43585  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43586  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43587  */
43588 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
43589 /*! @} */
43590 
43591 /*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
43592 /*! @{ */
43593 
43594 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
43595 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
43596 /*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43597  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43598  *    Address field in the IPv6 packets.
43599  */
43600 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
43601 /*! @} */
43602 
43603 /*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
43604 /*! @{ */
43605 
43606 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
43607 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
43608 /*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43609  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43610  *    Address field in the IPv6 packets.
43611  */
43612 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
43613 /*! @} */
43614 
43615 /*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
43616 /*! @{ */
43617 
43618 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
43619 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
43620 /*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43621  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43622  *    Address field in the IPv6 packets.
43623  */
43624 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
43625 /*! @} */
43626 
43627 /*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
43628 /*! @{ */
43629 
43630 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
43631 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
43632 /*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43633  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43634  *    Address field in the IPv6 packets.
43635  */
43636 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
43637 /*! @} */
43638 
43639 /*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
43640 /*! @{ */
43641 
43642 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK  (0x1U)
43643 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
43644 /*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43645  *    Address matching is enabled for IPv6 packets.
43646  *  0b0..Layer 3 Protocol is disabled
43647  *  0b1..Layer 3 Protocol is enabled
43648  */
43649 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
43650 
43651 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK  (0x4U)
43652 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
43653 /*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43654  *  0b0..Layer 3 IP SA Match is disabled
43655  *  0b1..Layer 3 IP SA Match is enabled
43656  */
43657 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
43658 
43659 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
43660 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
43661 /*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43662  *    field is enabled for inverse matching.
43663  *  0b0..Layer 3 IP SA Inverse Match is disabled
43664  *  0b1..Layer 3 IP SA Inverse Match is enabled
43665  */
43666 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
43667 
43668 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK  (0x10U)
43669 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
43670 /*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43671  *  0b0..Layer 3 IP DA Match is disabled
43672  *  0b1..Layer 3 IP DA Match is enabled
43673  */
43674 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
43675 
43676 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
43677 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
43678 /*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43679  *    Address field is enabled for inverse matching.
43680  *  0b0..Layer 3 IP DA Inverse Match is disabled
43681  *  0b1..Layer 3 IP DA Inverse Match is enabled
43682  */
43683 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
43684 
43685 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
43686 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
43687 /*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43688  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43689  */
43690 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
43691 
43692 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
43693 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
43694 /*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43695  *    bits of IP Destination Address that are matched in the IPv4 packets.
43696  */
43697 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
43698 
43699 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK  (0x10000U)
43700 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
43701 /*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43702  *    fields of UDP packets are used for matching.
43703  *  0b0..Layer 4 Protocol is disabled
43704  *  0b1..Layer 4 Protocol is enabled
43705  */
43706 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
43707 
43708 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK  (0x40000U)
43709 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
43710 /*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43711  *  0b0..Layer 4 Source Port Match is disabled
43712  *  0b1..Layer 4 Source Port Match is enabled
43713  */
43714 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
43715 
43716 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
43717 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
43718 /*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43719  *    number field is enabled for inverse matching.
43720  *  0b0..Layer 4 Source Port Inverse Match is disabled
43721  *  0b1..Layer 4 Source Port Inverse Match is enabled
43722  */
43723 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
43724 
43725 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK  (0x100000U)
43726 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
43727 /*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43728  *    Port number field is enabled for matching.
43729  *  0b0..Layer 4 Destination Port Match is disabled
43730  *  0b1..Layer 4 Destination Port Match is enabled
43731  */
43732 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
43733 
43734 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
43735 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
43736 /*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43737  *    Destination Port number field is enabled for inverse matching.
43738  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43739  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43740  */
43741 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
43742 
43743 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK  (0x7000000U)
43744 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
43745 /*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43746  *    to which the packet passed by this filter is routed.
43747  */
43748 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
43749 
43750 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
43751 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
43752 /*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43753  *    number for the packet that is passed by this L3_L4 filter.
43754  *  0b0..DMA Channel Select is disabled
43755  *  0b1..DMA Channel Select is enabled
43756  */
43757 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
43758 /*! @} */
43759 
43760 /*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
43761 /*! @{ */
43762 
43763 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK  (0xFFFFU)
43764 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
43765 /*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43766  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43767  *    Source Port Number field in the IPv4 or IPv6 packets.
43768  */
43769 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
43770 
43771 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK  (0xFFFF0000U)
43772 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
43773 /*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43774  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43775  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43776  */
43777 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
43778 /*! @} */
43779 
43780 /*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
43781 /*! @{ */
43782 
43783 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
43784 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
43785 /*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43786  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43787  *    Address field in the IPv6 packets.
43788  */
43789 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
43790 /*! @} */
43791 
43792 /*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
43793 /*! @{ */
43794 
43795 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
43796 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
43797 /*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43798  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43799  *    Address field in the IPv6 packets.
43800  */
43801 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
43802 /*! @} */
43803 
43804 /*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
43805 /*! @{ */
43806 
43807 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
43808 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
43809 /*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43810  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43811  *    Address field in the IPv6 packets.
43812  */
43813 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
43814 /*! @} */
43815 
43816 /*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
43817 /*! @{ */
43818 
43819 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
43820 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
43821 /*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43822  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43823  *    Address field in the IPv6 packets.
43824  */
43825 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
43826 /*! @} */
43827 
43828 /*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
43829 /*! @{ */
43830 
43831 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK  (0x1U)
43832 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
43833 /*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43834  *    Address matching is enabled for IPv6 packets.
43835  *  0b0..Layer 3 Protocol is disabled
43836  *  0b1..Layer 3 Protocol is enabled
43837  */
43838 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
43839 
43840 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK  (0x4U)
43841 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
43842 /*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43843  *  0b0..Layer 3 IP SA Match is disabled
43844  *  0b1..Layer 3 IP SA Match is enabled
43845  */
43846 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
43847 
43848 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
43849 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
43850 /*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43851  *    field is enabled for inverse matching.
43852  *  0b0..Layer 3 IP SA Inverse Match is disabled
43853  *  0b1..Layer 3 IP SA Inverse Match is enabled
43854  */
43855 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
43856 
43857 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK  (0x10U)
43858 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
43859 /*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43860  *  0b0..Layer 3 IP DA Match is disabled
43861  *  0b1..Layer 3 IP DA Match is enabled
43862  */
43863 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
43864 
43865 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
43866 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
43867 /*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43868  *    Address field is enabled for inverse matching.
43869  *  0b0..Layer 3 IP DA Inverse Match is disabled
43870  *  0b1..Layer 3 IP DA Inverse Match is enabled
43871  */
43872 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
43873 
43874 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
43875 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
43876 /*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43877  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43878  */
43879 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
43880 
43881 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
43882 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
43883 /*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43884  *    bits of IP Destination Address that are matched in the IPv4 packets.
43885  */
43886 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
43887 
43888 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK  (0x10000U)
43889 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
43890 /*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43891  *    fields of UDP packets are used for matching.
43892  *  0b0..Layer 4 Protocol is disabled
43893  *  0b1..Layer 4 Protocol is enabled
43894  */
43895 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
43896 
43897 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK  (0x40000U)
43898 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
43899 /*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43900  *  0b0..Layer 4 Source Port Match is disabled
43901  *  0b1..Layer 4 Source Port Match is enabled
43902  */
43903 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
43904 
43905 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
43906 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
43907 /*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43908  *    number field is enabled for inverse matching.
43909  *  0b0..Layer 4 Source Port Inverse Match is disabled
43910  *  0b1..Layer 4 Source Port Inverse Match is enabled
43911  */
43912 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
43913 
43914 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK  (0x100000U)
43915 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
43916 /*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43917  *    Port number field is enabled for matching.
43918  *  0b0..Layer 4 Destination Port Match is disabled
43919  *  0b1..Layer 4 Destination Port Match is enabled
43920  */
43921 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
43922 
43923 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
43924 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
43925 /*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43926  *    Destination Port number field is enabled for inverse matching.
43927  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43928  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43929  */
43930 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
43931 
43932 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK  (0x7000000U)
43933 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
43934 /*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43935  *    to which the packet passed by this filter is routed.
43936  */
43937 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
43938 
43939 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
43940 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
43941 /*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43942  *    number for the packet that is passed by this L3_L4 filter.
43943  *  0b0..DMA Channel Select is disabled
43944  *  0b1..DMA Channel Select is enabled
43945  */
43946 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
43947 /*! @} */
43948 
43949 /*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
43950 /*! @{ */
43951 
43952 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK  (0xFFFFU)
43953 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
43954 /*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43955  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43956  *    Source Port Number field in the IPv4 or IPv6 packets.
43957  */
43958 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
43959 
43960 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK  (0xFFFF0000U)
43961 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
43962 /*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43963  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43964  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43965  */
43966 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
43967 /*! @} */
43968 
43969 /*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
43970 /*! @{ */
43971 
43972 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
43973 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
43974 /*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43975  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43976  *    Address field in the IPv6 packets.
43977  */
43978 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
43979 /*! @} */
43980 
43981 /*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
43982 /*! @{ */
43983 
43984 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
43985 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
43986 /*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43987  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43988  *    Address field in the IPv6 packets.
43989  */
43990 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
43991 /*! @} */
43992 
43993 /*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
43994 /*! @{ */
43995 
43996 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
43997 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
43998 /*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43999  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44000  *    Address field in the IPv6 packets.
44001  */
44002 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
44003 /*! @} */
44004 
44005 /*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
44006 /*! @{ */
44007 
44008 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
44009 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
44010 /*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44011  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44012  *    Address field in the IPv6 packets.
44013  */
44014 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
44015 /*! @} */
44016 
44017 /*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
44018 /*! @{ */
44019 
44020 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK  (0x1U)
44021 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
44022 /*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44023  *    Address matching is enabled for IPv6 packets.
44024  *  0b0..Layer 3 Protocol is disabled
44025  *  0b1..Layer 3 Protocol is enabled
44026  */
44027 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
44028 
44029 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK  (0x4U)
44030 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
44031 /*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44032  *  0b0..Layer 3 IP SA Match is disabled
44033  *  0b1..Layer 3 IP SA Match is enabled
44034  */
44035 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
44036 
44037 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
44038 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
44039 /*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44040  *    field is enabled for inverse matching.
44041  *  0b0..Layer 3 IP SA Inverse Match is disabled
44042  *  0b1..Layer 3 IP SA Inverse Match is enabled
44043  */
44044 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
44045 
44046 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK  (0x10U)
44047 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
44048 /*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44049  *  0b0..Layer 3 IP DA Match is disabled
44050  *  0b1..Layer 3 IP DA Match is enabled
44051  */
44052 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
44053 
44054 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
44055 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
44056 /*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44057  *    Address field is enabled for inverse matching.
44058  *  0b0..Layer 3 IP DA Inverse Match is disabled
44059  *  0b1..Layer 3 IP DA Inverse Match is enabled
44060  */
44061 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
44062 
44063 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
44064 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
44065 /*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44066  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44067  */
44068 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
44069 
44070 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
44071 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
44072 /*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44073  *    bits of IP Destination Address that are matched in the IPv4 packets.
44074  */
44075 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
44076 
44077 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK  (0x10000U)
44078 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
44079 /*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44080  *    fields of UDP packets are used for matching.
44081  *  0b0..Layer 4 Protocol is disabled
44082  *  0b1..Layer 4 Protocol is enabled
44083  */
44084 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
44085 
44086 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK  (0x40000U)
44087 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
44088 /*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44089  *  0b0..Layer 4 Source Port Match is disabled
44090  *  0b1..Layer 4 Source Port Match is enabled
44091  */
44092 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
44093 
44094 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
44095 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
44096 /*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44097  *    number field is enabled for inverse matching.
44098  *  0b0..Layer 4 Source Port Inverse Match is disabled
44099  *  0b1..Layer 4 Source Port Inverse Match is enabled
44100  */
44101 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
44102 
44103 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK  (0x100000U)
44104 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
44105 /*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44106  *    Port number field is enabled for matching.
44107  *  0b0..Layer 4 Destination Port Match is disabled
44108  *  0b1..Layer 4 Destination Port Match is enabled
44109  */
44110 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
44111 
44112 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
44113 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
44114 /*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44115  *    Destination Port number field is enabled for inverse matching.
44116  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44117  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44118  */
44119 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
44120 
44121 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK  (0x7000000U)
44122 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
44123 /*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44124  *    to which the packet passed by this filter is routed.
44125  */
44126 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
44127 
44128 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
44129 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
44130 /*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44131  *    number for the packet that is passed by this L3_L4 filter.
44132  *  0b0..DMA Channel Select is disabled
44133  *  0b1..DMA Channel Select is enabled
44134  */
44135 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
44136 /*! @} */
44137 
44138 /*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
44139 /*! @{ */
44140 
44141 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK  (0xFFFFU)
44142 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
44143 /*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44144  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44145  *    Source Port Number field in the IPv4 or IPv6 packets.
44146  */
44147 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
44148 
44149 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK  (0xFFFF0000U)
44150 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
44151 /*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44152  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44153  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44154  */
44155 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
44156 /*! @} */
44157 
44158 /*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
44159 /*! @{ */
44160 
44161 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
44162 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
44163 /*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44164  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44165  *    Address field in the IPv6 packets.
44166  */
44167 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
44168 /*! @} */
44169 
44170 /*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
44171 /*! @{ */
44172 
44173 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
44174 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
44175 /*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44176  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44177  *    Address field in the IPv6 packets.
44178  */
44179 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
44180 /*! @} */
44181 
44182 /*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
44183 /*! @{ */
44184 
44185 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
44186 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
44187 /*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44188  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44189  *    Address field in the IPv6 packets.
44190  */
44191 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
44192 /*! @} */
44193 
44194 /*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
44195 /*! @{ */
44196 
44197 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
44198 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
44199 /*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44200  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44201  *    Address field in the IPv6 packets.
44202  */
44203 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
44204 /*! @} */
44205 
44206 /*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
44207 /*! @{ */
44208 
44209 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK  (0x1U)
44210 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
44211 /*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44212  *    Address matching is enabled for IPv6 packets.
44213  *  0b0..Layer 3 Protocol is disabled
44214  *  0b1..Layer 3 Protocol is enabled
44215  */
44216 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
44217 
44218 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK  (0x4U)
44219 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
44220 /*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44221  *  0b0..Layer 3 IP SA Match is disabled
44222  *  0b1..Layer 3 IP SA Match is enabled
44223  */
44224 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
44225 
44226 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
44227 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
44228 /*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44229  *    field is enabled for inverse matching.
44230  *  0b0..Layer 3 IP SA Inverse Match is disabled
44231  *  0b1..Layer 3 IP SA Inverse Match is enabled
44232  */
44233 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
44234 
44235 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK  (0x10U)
44236 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
44237 /*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44238  *  0b0..Layer 3 IP DA Match is disabled
44239  *  0b1..Layer 3 IP DA Match is enabled
44240  */
44241 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
44242 
44243 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
44244 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
44245 /*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44246  *    Address field is enabled for inverse matching.
44247  *  0b0..Layer 3 IP DA Inverse Match is disabled
44248  *  0b1..Layer 3 IP DA Inverse Match is enabled
44249  */
44250 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
44251 
44252 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
44253 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
44254 /*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44255  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44256  */
44257 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
44258 
44259 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
44260 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
44261 /*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44262  *    bits of IP Destination Address that are matched in the IPv4 packets.
44263  */
44264 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
44265 
44266 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK  (0x10000U)
44267 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
44268 /*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44269  *    fields of UDP packets are used for matching.
44270  *  0b0..Layer 4 Protocol is disabled
44271  *  0b1..Layer 4 Protocol is enabled
44272  */
44273 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
44274 
44275 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK  (0x40000U)
44276 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
44277 /*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44278  *  0b0..Layer 4 Source Port Match is disabled
44279  *  0b1..Layer 4 Source Port Match is enabled
44280  */
44281 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
44282 
44283 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
44284 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
44285 /*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44286  *    number field is enabled for inverse matching.
44287  *  0b0..Layer 4 Source Port Inverse Match is disabled
44288  *  0b1..Layer 4 Source Port Inverse Match is enabled
44289  */
44290 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
44291 
44292 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK  (0x100000U)
44293 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
44294 /*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44295  *    Port number field is enabled for matching.
44296  *  0b0..Layer 4 Destination Port Match is disabled
44297  *  0b1..Layer 4 Destination Port Match is enabled
44298  */
44299 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
44300 
44301 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
44302 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
44303 /*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44304  *    Destination Port number field is enabled for inverse matching.
44305  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44306  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44307  */
44308 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
44309 
44310 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK  (0x7000000U)
44311 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
44312 /*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44313  *    to which the packet passed by this filter is routed.
44314  */
44315 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
44316 
44317 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
44318 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
44319 /*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44320  *    number for the packet that is passed by this L3_L4 filter.
44321  *  0b0..DMA Channel Select is disabled
44322  *  0b1..DMA Channel Select is enabled
44323  */
44324 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
44325 /*! @} */
44326 
44327 /*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
44328 /*! @{ */
44329 
44330 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK  (0xFFFFU)
44331 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
44332 /*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44333  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44334  *    Source Port Number field in the IPv4 or IPv6 packets.
44335  */
44336 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
44337 
44338 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK  (0xFFFF0000U)
44339 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
44340 /*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44341  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44342  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44343  */
44344 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
44345 /*! @} */
44346 
44347 /*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
44348 /*! @{ */
44349 
44350 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
44351 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
44352 /*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44353  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44354  *    Address field in the IPv6 packets.
44355  */
44356 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
44357 /*! @} */
44358 
44359 /*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
44360 /*! @{ */
44361 
44362 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
44363 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
44364 /*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44365  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44366  *    Address field in the IPv6 packets.
44367  */
44368 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
44369 /*! @} */
44370 
44371 /*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
44372 /*! @{ */
44373 
44374 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
44375 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
44376 /*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44377  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44378  *    Address field in the IPv6 packets.
44379  */
44380 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
44381 /*! @} */
44382 
44383 /*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
44384 /*! @{ */
44385 
44386 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
44387 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
44388 /*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44389  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44390  *    Address field in the IPv6 packets.
44391  */
44392 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
44393 /*! @} */
44394 
44395 /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
44396 /*! @{ */
44397 
44398 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
44399 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
44400 /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
44401  *  0b0..Timestamp is disabled
44402  *  0b1..Timestamp is enabled
44403  */
44404 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
44405 
44406 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
44407 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
44408 /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
44409  *  0b0..Coarse method is used to update system timestamp
44410  *  0b1..Fine method is used to update system timestamp
44411  */
44412 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
44413 
44414 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
44415 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
44416 /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
44417  *    with the value specified in the MAC_System_Time_Seconds_Update and
44418  *    MAC_System_Time_Nanoseconds_Update registers.
44419  *  0b0..Timestamp is not initialized
44420  *  0b1..Timestamp is initialized
44421  */
44422 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
44423 
44424 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
44425 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
44426 /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
44427  *    with the value specified in MAC_System_Time_Seconds_Update and
44428  *    MAC_System_Time_Nanoseconds_Update registers.
44429  *  0b0..Timestamp is not updated
44430  *  0b1..Timestamp is updated
44431  */
44432 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
44433 
44434 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
44435 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
44436 /*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
44437  *    register is updated in the PTP block for fine correction.
44438  *  0b0..Addend Register is not updated
44439  *  0b1..Addend Register is updated
44440  */
44441 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
44442 
44443 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
44444 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
44445 /*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
44446  *  0b0..Presentation Time Generation is disabled
44447  *  0b1..Presentation Time Generation is enabled
44448  */
44449 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
44450 
44451 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
44452 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
44453 /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
44454  *    enabled for all packets received by the MAC.
44455  *  0b0..Timestamp for All Packets disabled
44456  *  0b1..Timestamp for All Packets enabled
44457  */
44458 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
44459 
44460 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
44461 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
44462 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
44463  *    register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
44464  *    the timestamp (High) seconds.
44465  *  0b0..Timestamp Digital or Binary Rollover Control is disabled
44466  *  0b1..Timestamp Digital or Binary Rollover Control is enabled
44467  */
44468 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
44469 
44470 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
44471 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
44472 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
44473  *    1588 version 2 format is used to process the PTP packets.
44474  *  0b0..PTP Packet Processing for Version 2 Format is disabled
44475  *  0b1..PTP Packet Processing for Version 2 Format is enabled
44476  */
44477 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
44478 
44479 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
44480 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
44481 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
44482  *    processes the PTP packets encapsulated directly in the Ethernet packets.
44483  *  0b0..Processing of PTP over Ethernet Packets is disabled
44484  *  0b1..Processing of PTP over Ethernet Packets is enabled
44485  */
44486 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
44487 
44488 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
44489 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
44490 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
44491  *    receiver processes the PTP packets encapsulated in IPv6-UDP packets.
44492  *  0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
44493  *  0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
44494  */
44495 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
44496 
44497 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
44498 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
44499 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
44500  *    receiver processes the PTP packets encapsulated in IPv4-UDP packets.
44501  *  0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
44502  *  0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
44503  */
44504 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
44505 
44506 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
44507 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
44508 /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
44509  *    snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
44510  *  0b0..Timestamp Snapshot for Event Messages is disabled
44511  *  0b1..Timestamp Snapshot for Event Messages is enabled
44512  */
44513 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
44514 
44515 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
44516 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
44517 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
44518  *    is taken only for the messages that are relevant to the master node.
44519  *  0b0..Snapshot for Messages Relevant to Master is disabled
44520  *  0b1..Snapshot for Messages Relevant to Master is enabled
44521  */
44522 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
44523 
44524 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
44525 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
44526 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
44527  *    decide the set of PTP packet types for which snapshot needs to be taken.
44528  */
44529 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
44530 
44531 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
44532 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
44533 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
44534  *    address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
44535  *    directly sent over Ethernet.
44536  *  0b0..MAC Address for PTP Packet Filtering is disabled
44537  *  0b1..MAC Address for PTP Packet Filtering is enabled
44538  */
44539 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
44540 
44541 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK  (0x80000U)
44542 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
44543 /*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
44544  *    the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
44545  *    correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
44546  *    operation.
44547  *  0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
44548  *  0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
44549  */
44550 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
44551 
44552 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
44553 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
44554 /*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
44555  *    reference System Time input for the following: - To take the timestamp provided as status - To insert
44556  *    the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
44557  *    enabled.
44558  *  0b0..External System Time Input is disabled
44559  *  0b1..External System Time Input is enabled
44560  */
44561 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
44562 
44563 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
44564 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
44565 /*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
44566  *    transmit timestamp status even if it is not read by the software.
44567  *  0b0..Transmit Timestamp Status Mode is disabled
44568  *  0b1..Transmit Timestamp Status Mode is enabled
44569  */
44570 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
44571 
44572 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
44573 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
44574 /*! AV8021ASMEN - AV 802.
44575  *  0b0..AV 802.1AS Mode is disabled
44576  *  0b1..AV 802.1AS Mode is enabled
44577  */
44578 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
44579 /*! @} */
44580 
44581 /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
44582 /*! @{ */
44583 
44584 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
44585 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
44586 /*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
44587  *    represented in nanoseconds multiplied by 2^8.
44588  */
44589 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
44590 
44591 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
44592 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
44593 /*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
44594  *    cycle (of clk_ptp_i) with the contents of the sub-second register.
44595  */
44596 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
44597 /*! @} */
44598 
44599 /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
44600 /*! @{ */
44601 
44602 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
44603 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
44604 /*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
44605  *    System Time maintained by the MAC.
44606  */
44607 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
44608 /*! @} */
44609 
44610 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
44611 /*! @{ */
44612 
44613 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
44614 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
44615 /*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0.
44616  */
44617 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
44618 /*! @} */
44619 
44620 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
44621 /*! @{ */
44622 
44623 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
44624 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
44625 /*! TSS - Timestamp Seconds The value in this field is the seconds part of the update.
44626  */
44627 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
44628 /*! @} */
44629 
44630 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
44631 /*! @{ */
44632 
44633 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
44634 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
44635 /*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update.
44636  */
44637 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
44638 
44639 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
44640 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
44641 /*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
44642  *  0b0..Add time
44643  *  0b1..Subtract time
44644  */
44645 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
44646 /*! @} */
44647 
44648 /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
44649 /*! @{ */
44650 
44651 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK  (0xFFFFFFFFU)
44652 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
44653 /*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
44654  *    Accumulator register to achieve time synchronization.
44655  */
44656 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
44657 /*! @} */
44658 
44659 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
44660 /*! @{ */
44661 
44662 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
44663 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
44664 /*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value.
44665  */
44666 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
44667 /*! @} */
44668 
44669 /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
44670 /*! @{ */
44671 
44672 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
44673 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
44674 /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
44675  *    the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
44676  *  0b1..Timestamp Seconds Overflow status detected
44677  *  0b0..Timestamp Seconds Overflow status not detected
44678  */
44679 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
44680 
44681 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
44682 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
44683 /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
44684  *    time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
44685  *    MAC_PPS0_Target_Time_Nanoseconds registers.
44686  *  0b1..Timestamp Target Time Reached status detected
44687  *  0b0..Timestamp Target Time Reached status not detected
44688  */
44689 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
44690 
44691 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
44692 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
44693 /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
44694  *  0b1..Auxiliary Timestamp Trigger Snapshot status detected
44695  *  0b0..Auxiliary Timestamp Trigger Snapshot status not detected
44696  */
44697 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
44698 
44699 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
44700 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
44701 /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
44702  *    in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
44703  *  0b1..Timestamp Target Time Error status detected
44704  *  0b0..Timestamp Target Time Error status not detected
44705  */
44706 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
44707 
44708 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
44709 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
44710 /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
44711  *    the value of system time is greater than or equal to the value specified in the
44712  *    MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
44713  *  0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
44714  *  0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
44715  */
44716 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
44717 
44718 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
44719 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
44720 /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
44721  *    in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
44722  *  0b1..Timestamp Target Time Error status detected
44723  *  0b0..Timestamp Target Time Error status not detected
44724  */
44725 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
44726 
44727 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
44728 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
44729 /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
44730  *    the value of system time is greater than or equal to the value specified in the
44731  *    MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
44732  *  0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
44733  *  0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
44734  */
44735 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
44736 
44737 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
44738 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
44739 /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
44740  *    in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
44741  *  0b1..Timestamp Target Time Error status detected
44742  *  0b0..Timestamp Target Time Error status not detected
44743  */
44744 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
44745 
44746 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
44747 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
44748 /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
44749  *    that the value of system time is greater than or equal to the value specified in the
44750  *    MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
44751  *  0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
44752  *  0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
44753  */
44754 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
44755 
44756 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
44757 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
44758 /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
44759  *    in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
44760  *  0b1..Timestamp Target Time Error status detected
44761  *  0b0..Timestamp Target Time Error status not detected
44762  */
44763 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
44764 
44765 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
44766 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
44767 /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
44768  *    transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
44769  *    the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
44770  *  0b1..Tx Timestamp Status Interrupt status detected
44771  *  0b0..Tx Timestamp Status Interrupt status not detected
44772  */
44773 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
44774 
44775 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
44776 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
44777 /*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
44778  *    trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
44779  */
44780 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
44781 
44782 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
44783 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
44784 /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
44785  *    timestamp snapshot FIFO is full and external trigger was set.
44786  *  0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
44787  *  0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
44788  */
44789 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
44790 
44791 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
44792 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
44793 /*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO.
44794  */
44795 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
44796 /*! @} */
44797 
44798 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
44799 /*! @{ */
44800 
44801 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
44802 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
44803 /*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
44804  *    of the Transmit packet's captured timestamp.
44805  */
44806 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
44807 
44808 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
44809 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
44810 /*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
44811  *    following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
44812  *    register is reset - The timestamp of the previous packet is overwritten with timestamp of the
44813  *    current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
44814  *  0b1..Transmit Timestamp Status Missed status detected
44815  *  0b0..Transmit Timestamp Status Missed status not detected
44816  */
44817 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
44818 /*! @} */
44819 
44820 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
44821 /*! @{ */
44822 
44823 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
44824 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
44825 /*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
44826  *    field of Transmit packet's captured timestamp.
44827  */
44828 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
44829 /*! @} */
44830 
44831 /*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
44832 /*! @{ */
44833 
44834 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
44835 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
44836 /*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
44837  *  0b0..Auxiliary Snapshot FIFO Clear is disabled
44838  *  0b1..Auxiliary Snapshot FIFO Clear is enabled
44839  */
44840 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
44841 
44842 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
44843 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
44844 /*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
44845  *  0b0..Auxiliary Snapshot $i is disabled
44846  *  0b1..Auxiliary Snapshot $i is enabled
44847  */
44848 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
44849 
44850 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
44851 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
44852 /*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
44853  *  0b0..Auxiliary Snapshot $i is disabled
44854  *  0b1..Auxiliary Snapshot $i is enabled
44855  */
44856 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
44857 
44858 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
44859 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
44860 /*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
44861  *  0b0..Auxiliary Snapshot $i is disabled
44862  *  0b1..Auxiliary Snapshot $i is enabled
44863  */
44864 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
44865 
44866 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
44867 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
44868 /*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
44869  *  0b0..Auxiliary Snapshot $i is disabled
44870  *  0b1..Auxiliary Snapshot $i is enabled
44871  */
44872 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
44873 /*! @} */
44874 
44875 /*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
44876 /*! @{ */
44877 
44878 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
44879 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
44880 /*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp.
44881  */
44882 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
44883 /*! @} */
44884 
44885 /*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
44886 /*! @{ */
44887 
44888 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
44889 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
44890 /*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp.
44891  */
44892 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
44893 /*! @} */
44894 
44895 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
44896 /*! @{ */
44897 
44898 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
44899 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
44900 /*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
44901  *    asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
44902  */
44903 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
44904 /*! @} */
44905 
44906 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
44907 /*! @{ */
44908 
44909 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
44910 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
44911 /*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
44912  *    asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
44913  */
44914 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
44915 /*! @} */
44916 
44917 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
44918 /*! @{ */
44919 
44920 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
44921 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
44922 /*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
44923  *    defined by the Ingress Correction expression.
44924  */
44925 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
44926 /*! @} */
44927 
44928 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
44929 /*! @{ */
44930 
44931 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
44932 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
44933 /*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
44934  *    correction value as defined by the Egress Correction expression.
44935  */
44936 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
44937 /*! @} */
44938 
44939 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
44940 /*! @{ */
44941 
44942 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
44943 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
44944 /*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
44945  *    part of the ingress path correction value as defined by the "Ingress Correction" expression.
44946  */
44947 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
44948 /*! @} */
44949 
44950 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
44951 /*! @{ */
44952 
44953 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
44954 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
44955 /*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
44956  *    part of the egress path correction value as defined by the "Egress Correction" expression.
44957  */
44958 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
44959 /*! @} */
44960 
44961 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
44962 /*! @{ */
44963 
44964 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
44965 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
44966 /*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
44967  *    nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
44968  *    ingress timestamp is taken.
44969  */
44970 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
44971 
44972 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
44973 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
44974 /*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
44975  *    sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
44976  *    where the ingress timestamp is taken.
44977  */
44978 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
44979 /*! @} */
44980 
44981 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
44982 /*! @{ */
44983 
44984 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
44985 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
44986 /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
44987  *    sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
44988  *    the output ports (phy_txd_o) of the MAC.
44989  */
44990 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
44991 
44992 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
44993 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
44994 /*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
44995  *    nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
44996  *    ports (phy_txd_o) of the MAC.
44997  */
44998 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
44999 /*! @} */
45000 
45001 /*! @name MAC_PPS_CONTROL - PPS Control */
45002 /*! @{ */
45003 
45004 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
45005 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
45006 /*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal.
45007  */
45008 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
45009 
45010 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK     (0x10U)
45011 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT    (4U)
45012 /*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
45013  *  0b0..Flexible PPS Output Mode is disabled
45014  *  0b1..Flexible PPS Output Mode is enabled
45015  */
45016 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
45017 
45018 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
45019 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
45020 /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
45021  *    registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
45022  *    output signal:
45023  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45024  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45025  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45026  *        ptp_pps_o output port
45027  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45028  *  0b01..Reserved
45029  */
45030 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
45031 
45032 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK    (0x80U)
45033 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT   (7U)
45034 /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
45035  *  0b1..0th PPS instance is enabled to operate in MCGR mode
45036  *  0b0..0th PPS instance is enabled to operate in PPS mode
45037  */
45038 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
45039 
45040 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK    (0xF00U)
45041 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT   (8U)
45042 /*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal.
45043  */
45044 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
45045 
45046 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
45047 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
45048 /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
45049  *    registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
45050  *    output signal.
45051  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45052  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45053  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45054  *        ptp_pps_o output port
45055  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45056  *  0b01..Reserved
45057  */
45058 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
45059 
45060 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK    (0x8000U)
45061 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT   (15U)
45062 /*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
45063  *  0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
45064  *  0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
45065  */
45066 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
45067 
45068 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK    (0xF0000U)
45069 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT   (16U)
45070 /*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal.
45071  */
45072 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
45073 
45074 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
45075 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
45076 /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
45077  *    registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
45078  *    output signal.
45079  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45080  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45081  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45082  *        ptp_pps_o output port
45083  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45084  *  0b01..Reserved
45085  */
45086 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
45087 
45088 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK    (0x800000U)
45089 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT   (23U)
45090 /*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
45091  *  0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
45092  *  0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
45093  */
45094 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
45095 
45096 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK    (0xF000000U)
45097 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT   (24U)
45098 /*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal.
45099  */
45100 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
45101 
45102 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
45103 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
45104 /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
45105  *    registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
45106  *    output signal.
45107  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45108  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45109  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45110  *        ptp_pps_o output port
45111  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45112  *  0b01..Reserved
45113  */
45114 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
45115 
45116 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK    (0x80000000U)
45117 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT   (31U)
45118 /*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode.
45119  */
45120 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
45121 /*! @} */
45122 
45123 /*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
45124 /*! @{ */
45125 
45126 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
45127 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
45128 /*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds.
45129  */
45130 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
45131 /*! @} */
45132 
45133 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
45134 /*! @{ */
45135 
45136 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
45137 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
45138 /*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45139  */
45140 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
45141 
45142 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
45143 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
45144 /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45145  *    PPS_CONTROL register is programmed to 010 or 011.
45146  *  0b1..PPS Target Time Register Busy is detected
45147  *  0b0..PPS Target Time Register Busy status is not detected
45148  */
45149 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
45150 /*! @} */
45151 
45152 /*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
45153 /*! @{ */
45154 
45155 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK  (0xFFFFFFFFU)
45156 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
45157 /*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45158  */
45159 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
45160 /*! @} */
45161 
45162 /*! @name MAC_PPS0_WIDTH - PPS0 Width */
45163 /*! @{ */
45164 
45165 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK   (0xFFFFFFFFU)
45166 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT  (0U)
45167 /*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
45168  *    corresponding falling edge of PPS0 signal output.
45169  */
45170 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
45171 /*! @} */
45172 
45173 /*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
45174 /*! @{ */
45175 
45176 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
45177 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
45178 /*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds.
45179  */
45180 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
45181 /*! @} */
45182 
45183 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
45184 /*! @{ */
45185 
45186 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
45187 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
45188 /*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45189  */
45190 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
45191 
45192 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
45193 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
45194 /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45195  *    PPS_CONTROL register is programmed to 010 or 011.
45196  *  0b1..PPS Target Time Register Busy is detected
45197  *  0b0..PPS Target Time Register Busy status is not detected
45198  */
45199 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
45200 /*! @} */
45201 
45202 /*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
45203 /*! @{ */
45204 
45205 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK  (0xFFFFFFFFU)
45206 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
45207 /*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45208  */
45209 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
45210 /*! @} */
45211 
45212 /*! @name MAC_PPS1_WIDTH - PPS1 Width */
45213 /*! @{ */
45214 
45215 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK   (0xFFFFFFFFU)
45216 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT  (0U)
45217 /*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
45218  *    corresponding falling edge of PPS0 signal output.
45219  */
45220 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
45221 /*! @} */
45222 
45223 /*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
45224 /*! @{ */
45225 
45226 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
45227 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
45228 /*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds.
45229  */
45230 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
45231 /*! @} */
45232 
45233 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
45234 /*! @{ */
45235 
45236 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
45237 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
45238 /*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45239  */
45240 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
45241 
45242 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
45243 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
45244 /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45245  *    PPS_CONTROL register is programmed to 010 or 011.
45246  *  0b1..PPS Target Time Register Busy is detected
45247  *  0b0..PPS Target Time Register Busy status is not detected
45248  */
45249 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
45250 /*! @} */
45251 
45252 /*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
45253 /*! @{ */
45254 
45255 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK  (0xFFFFFFFFU)
45256 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
45257 /*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45258  */
45259 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
45260 /*! @} */
45261 
45262 /*! @name MAC_PPS2_WIDTH - PPS2 Width */
45263 /*! @{ */
45264 
45265 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK   (0xFFFFFFFFU)
45266 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT  (0U)
45267 /*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
45268  *    corresponding falling edge of PPS0 signal output.
45269  */
45270 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
45271 /*! @} */
45272 
45273 /*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
45274 /*! @{ */
45275 
45276 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
45277 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
45278 /*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds.
45279  */
45280 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
45281 /*! @} */
45282 
45283 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
45284 /*! @{ */
45285 
45286 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
45287 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
45288 /*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45289  */
45290 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
45291 
45292 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
45293 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
45294 /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45295  *    PPS_CONTROL register is programmed to 010 or 011.
45296  *  0b1..PPS Target Time Register Busy is detected
45297  *  0b0..PPS Target Time Register Busy status is not detected
45298  */
45299 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
45300 /*! @} */
45301 
45302 /*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
45303 /*! @{ */
45304 
45305 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK  (0xFFFFFFFFU)
45306 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
45307 /*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45308  */
45309 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
45310 /*! @} */
45311 
45312 /*! @name MAC_PPS3_WIDTH - PPS3 Width */
45313 /*! @{ */
45314 
45315 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK   (0xFFFFFFFFU)
45316 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT  (0U)
45317 /*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
45318  *    corresponding falling edge of PPS0 signal output.
45319  */
45320 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
45321 /*! @} */
45322 
45323 /*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
45324 /*! @{ */
45325 
45326 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK      (0x1U)
45327 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT     (0U)
45328 /*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
45329  *  0b0..PTP Offload feature is disabled
45330  *  0b1..PTP Offload feature is enabled
45331  */
45332 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
45333 
45334 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK    (0x2U)
45335 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT   (1U)
45336 /*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
45337  *    periodically based on interval programmed or trigger from application, when the MAC is
45338  *    programmed to be in Clock Master mode.
45339  *  0b0..Automatic PTP SYNC message is disabled
45340  *  0b1..Automatic PTP SYNC message is enabled
45341  */
45342 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
45343 
45344 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK   (0x4U)
45345 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT  (2U)
45346 /*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
45347  *    is generated periodically based on interval programmed or trigger from application, when the
45348  *    MAC is programmed to be in Peer-to-Peer Transparent mode.
45349  *  0b0..Automatic PTP Pdelay_Req message is disabled
45350  *  0b1..Automatic PTP Pdelay_Req message is enabled
45351  */
45352 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
45353 
45354 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK  (0x10U)
45355 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
45356 /*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
45357  *  0b0..Automatic PTP SYNC message Trigger is disabled
45358  *  0b1..Automatic PTP SYNC message Trigger is enabled
45359  */
45360 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
45361 
45362 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
45363 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
45364 /*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
45365  *  0b0..Automatic PTP Pdelay_Req message Trigger is disabled
45366  *  0b1..Automatic PTP Pdelay_Req message Trigger is enabled
45367  */
45368 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
45369 
45370 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK     (0x40U)
45371 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT    (6U)
45372 /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
45373  *    Request and Delay response is not generated for received SYNC and Delay request packet
45374  *    respectively, as required by the programmed mode.
45375  *  0b1..PTO Delay Request/Response response generation is disabled
45376  *  0b0..PTO Delay Request/Response response generation is enabled
45377  */
45378 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
45379 
45380 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK     (0x80U)
45381 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT    (7U)
45382 /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
45383  *    Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
45384  *    request packet, as required by the programmed mode.
45385  *  0b1..Peer Delay Response response generation is disabled
45386  *  0b0..Peer Delay Response response generation is enabled
45387  */
45388 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
45389 
45390 #define ENET_QOS_MAC_PTO_CONTROL_DN_MASK         (0xFF00U)
45391 #define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT        (8U)
45392 /*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating.
45393  */
45394 #define ENET_QOS_MAC_PTO_CONTROL_DN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
45395 /*! @} */
45396 
45397 /*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
45398 /*! @{ */
45399 
45400 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
45401 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
45402 /*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node.
45403  */
45404 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
45405 /*! @} */
45406 
45407 /*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
45408 /*! @{ */
45409 
45410 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
45411 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
45412 /*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node.
45413  */
45414 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
45415 /*! @} */
45416 
45417 /*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
45418 /*! @{ */
45419 
45420 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
45421 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
45422 /*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node.
45423  */
45424 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
45425 /*! @} */
45426 
45427 /*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
45428 /*! @{ */
45429 
45430 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
45431 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
45432 /*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
45433  *    message when the PTP node is Master.
45434  */
45435 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
45436 
45437 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
45438 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
45439 /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
45440  *  0b110..Reserved
45441  *  0b000..DelayReq generated for every received SYNC
45442  *  0b100..for every 16 SYNC messages
45443  *  0b001..DelayReq generated every alternate reception of SYNC
45444  *  0b101..for every 32 SYNC messages
45445  *  0b010..for every 4 SYNC messages
45446  *  0b011..for every 8 SYNC messages
45447  */
45448 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
45449 
45450 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
45451 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
45452 /*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node.
45453  */
45454 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
45455 /*! @} */
45456 
45457 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */
45458 /*! @{ */
45459 
45460 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK  (0x2U)
45461 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
45462 /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
45463  *  0b0..Drop Transmit Status is disabled
45464  *  0b1..Drop Transmit Status is enabled
45465  */
45466 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
45467 
45468 #define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK     (0x4U)
45469 #define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT    (2U)
45470 /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
45471  *  0b0..Strict priority (SP)
45472  *  0b1..Weighted Strict Priority (WSP)
45473  */
45474 #define ENET_QOS_MTL_OPERATION_MODE_RAA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
45475 
45476 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK  (0x60U)
45477 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
45478 /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
45479  *  0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
45480  *  0b11..Strict priority algorithm
45481  *  0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
45482  *  0b00..WRR algorithm
45483  */
45484 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
45485 
45486 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
45487 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
45488 /*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
45489  *  0b0..Counters Preset is disabled
45490  *  0b1..Counters Preset is enabled
45491  */
45492 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
45493 
45494 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK  (0x200U)
45495 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
45496 /*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
45497  *  0b0..Counters are not reset
45498  *  0b1..All counters are reset
45499  */
45500 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
45501 
45502 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK    (0x8000U)
45503 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT   (15U)
45504 /*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
45505  *  0b0..Flexible Rx parser is disabled
45506  *  0b1..Flexible Rx parser is enabled
45507  */
45508 #define ENET_QOS_MTL_OPERATION_MODE_FRPE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
45509 /*! @} */
45510 
45511 /*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
45512 /*! @{ */
45513 
45514 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK         (0x1U)
45515 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT        (0U)
45516 /*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
45517  *  0b0..FIFO Debug Access is disabled
45518  *  0b1..FIFO Debug Access is enabled
45519  */
45520 #define ENET_QOS_MTL_DBG_CTL_FDBGEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
45521 
45522 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK         (0x2U)
45523 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT        (1U)
45524 /*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
45525  *    the FIFO is read, write, and debug access.
45526  *  0b0..Debug Mode Access to FIFO is disabled
45527  *  0b1..Debug Mode Access to FIFO is enabled
45528  */
45529 #define ENET_QOS_MTL_DBG_CTL_DBGMOD(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
45530 
45531 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK         (0xCU)
45532 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT        (2U)
45533 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
45534  *  0b11..All four bytes are valid
45535  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
45536  *  0b01..Byte 0 and Byte 1 are valid
45537  *  0b00..Byte 0 valid
45538  */
45539 #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
45540 
45541 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK       (0x60U)
45542 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT      (5U)
45543 /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
45544  *  0b01..Control Word/Normal Status
45545  *  0b11..EOP Data/EOP
45546  *  0b00..Packet Data
45547  *  0b10..SOP Data/Last Status
45548  */
45549 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
45550 
45551 #define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK         (0x100U)
45552 #define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT        (8U)
45553 /*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
45554  *  0b0..Reset All Pointers is disabled
45555  *  0b1..Reset All Pointers is enabled
45556  */
45557 #define ENET_QOS_MTL_DBG_CTL_RSTALL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
45558 
45559 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK         (0x200U)
45560 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT        (9U)
45561 /*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
45562  *    currently-selected FIFO are reset when FIFO Debug Access is enabled.
45563  *  0b0..Reset Pointers of Selected FIFO is disabled
45564  *  0b1..Reset Pointers of Selected FIFO is enabled
45565  */
45566 #define ENET_QOS_MTL_DBG_CTL_RSTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
45567 
45568 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK       (0x400U)
45569 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT      (10U)
45570 /*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
45571  *  0b0..FIFO Read is disabled
45572  *  0b1..FIFO Read is enabled
45573  */
45574 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
45575 
45576 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK       (0x800U)
45577 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT      (11U)
45578 /*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
45579  *    FIFO when FIFO Debug Access is enabled.
45580  *  0b0..FIFO Write is disabled
45581  *  0b1..FIFO Write is enabled
45582  */
45583 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
45584 
45585 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK        (0x3000U)
45586 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT       (12U)
45587 /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
45588  *  0b11..Rx FIFO
45589  *  0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
45590  *  0b00..Tx FIFO
45591  *  0b01..Tx Status FIFO (only read access when SLVMOD is set)
45592  */
45593 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
45594 
45595 #define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK          (0x4000U)
45596 #define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT         (14U)
45597 /*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
45598  *    generated when EOP of received packet is written to the Rx FIFO.
45599  *  0b0..Receive Packet Available Interrupt Status is disabled
45600  *  0b1..Receive Packet Available Interrupt Status is enabled
45601  */
45602 #define ENET_QOS_MTL_DBG_CTL_PKTIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
45603 
45604 #define ENET_QOS_MTL_DBG_CTL_STSIE_MASK          (0x8000U)
45605 #define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT         (15U)
45606 /*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
45607  *    generated when Transmit status is available in slave mode.
45608  *  0b0..Transmit Packet Available Interrupt Status is disabled
45609  *  0b1..Transmit Packet Available Interrupt Status is enabled
45610  */
45611 #define ENET_QOS_MTL_DBG_CTL_STSIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
45612 /*! @} */
45613 
45614 /*! @name MTL_DBG_STS - FIFO Debug Status */
45615 /*! @{ */
45616 
45617 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK       (0x1U)
45618 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT      (0U)
45619 /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
45620  *    MAC and content of the following fields is not valid: - All other fields of this register - All
45621  *    fields of the MTL_FIFO_DEBUG_DATA register
45622  *  0b1..FIFO Busy detected
45623  *  0b0..FIFO Busy not detected
45624  */
45625 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
45626 
45627 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK       (0x6U)
45628 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT      (1U)
45629 /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
45630  *  0b01..Control Word/Normal Status
45631  *  0b11..EOP Data/EOP
45632  *  0b00..Packet Data
45633  *  0b10..SOP Data/Last Status
45634  */
45635 #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
45636 
45637 #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK         (0x18U)
45638 #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT        (3U)
45639 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
45640  *  0b11..All four bytes are valid
45641  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
45642  *  0b01..Byte 0 and Byte 1 are valid
45643  *  0b00..Byte 0 valid
45644  */
45645 #define ENET_QOS_MTL_DBG_STS_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
45646 
45647 #define ENET_QOS_MTL_DBG_STS_PKTI_MASK           (0x100U)
45648 #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT          (8U)
45649 /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
45650  *    written the EOP of received packet to the Rx FIFO.
45651  *  0b1..Receive Packet Available Interrupt Status detected
45652  *  0b0..Receive Packet Available Interrupt Status not detected
45653  */
45654 #define ENET_QOS_MTL_DBG_STS_PKTI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
45655 
45656 #define ENET_QOS_MTL_DBG_STS_STSI_MASK           (0x200U)
45657 #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT          (9U)
45658 /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
45659  *    mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
45660  *  0b1..Transmit Status Available Interrupt Status detected
45661  *  0b0..Transmit Status Available Interrupt Status not detected
45662  */
45663 #define ENET_QOS_MTL_DBG_STS_STSI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
45664 
45665 #define ENET_QOS_MTL_DBG_STS_LOCR_MASK           (0xFFFF8000U)
45666 #define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT          (15U)
45667 /*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO.
45668  */
45669 #define ENET_QOS_MTL_DBG_STS_LOCR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
45670 /*! @} */
45671 
45672 /*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
45673 /*! @{ */
45674 
45675 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
45676 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
45677 /*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
45678  *    data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
45679  */
45680 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
45681 /*! @} */
45682 
45683 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
45684 /*! @{ */
45685 
45686 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK  (0x1U)
45687 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
45688 /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
45689  *  0b1..Queue 0 Interrupt status detected
45690  *  0b0..Queue 0 Interrupt status not detected
45691  */
45692 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
45693 
45694 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK  (0x2U)
45695 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
45696 /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
45697  *  0b1..Queue 1 Interrupt status detected
45698  *  0b0..Queue 1 Interrupt status not detected
45699  */
45700 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
45701 
45702 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK  (0x4U)
45703 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
45704 /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
45705  *  0b1..Queue 2 Interrupt status detected
45706  *  0b0..Queue 2 Interrupt status not detected
45707  */
45708 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
45709 
45710 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK  (0x8U)
45711 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
45712 /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
45713  *  0b1..Queue 3 Interrupt status detected
45714  *  0b0..Queue 3 Interrupt status not detected
45715  */
45716 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
45717 
45718 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK  (0x10U)
45719 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
45720 /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
45721  *  0b1..Queue 4 Interrupt status detected
45722  *  0b0..Queue 4 Interrupt status not detected
45723  */
45724 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
45725 
45726 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
45727 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
45728 /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
45729  *  0b1..Debug Interrupt status detected
45730  *  0b0..Debug Interrupt status not detected
45731  */
45732 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
45733 
45734 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
45735 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
45736 /*! ESTIS - EST (TAS- 802.
45737  *  0b1..EST (TAS- 802.1Qbv) Interrupt status detected
45738  *  0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
45739  */
45740 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
45741 
45742 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
45743 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
45744 /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
45745  *  0b1..MTL Rx Parser Interrupt status detected
45746  *  0b0..MTL Rx Parser Interrupt status not detected
45747  */
45748 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
45749 /*! @} */
45750 
45751 /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
45752 /*! @{ */
45753 
45754 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK  (0x7U)
45755 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
45756 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
45757  *    in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45758  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45759  *    field is valid when the Q0DDMACH field is reset.
45760  */
45761 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
45762 
45763 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK  (0x10U)
45764 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
45765 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45766  *    the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
45767  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45768  *    Ethernet DA address.
45769  *  0b0..Queue 0 disabled for DA-based DMA Channel Selection
45770  *  0b1..Queue 0 enabled for DA-based DMA Channel Selection
45771  */
45772 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
45773 
45774 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK  (0x700U)
45775 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
45776 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
45777  *    in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45778  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45779  *    field is valid when the Q1DDMACH field is reset.
45780  */
45781 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
45782 
45783 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK  (0x1000U)
45784 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
45785 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45786  *    the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
45787  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45788  *    Ethernet DA address.
45789  *  0b0..Queue 1 disabled for DA-based DMA Channel Selection
45790  *  0b1..Queue 1 enabled for DA-based DMA Channel Selection
45791  */
45792 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
45793 
45794 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK  (0x70000U)
45795 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
45796 /*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
45797  *    in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45798  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45799  *    field is valid when the Q2DDMACH field is reset.
45800  */
45801 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
45802 
45803 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK  (0x100000U)
45804 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
45805 /*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45806  *    the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
45807  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45808  *    Ethernet DA address.
45809  *  0b0..Queue 2 disabled for DA-based DMA Channel Selection
45810  *  0b1..Queue 2 enabled for DA-based DMA Channel Selection
45811  */
45812 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
45813 
45814 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK  (0x7000000U)
45815 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
45816 /*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
45817  *    in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45818  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45819  *    field is valid when the Q3DDMACH field is reset.
45820  */
45821 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
45822 
45823 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK  (0x10000000U)
45824 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
45825 /*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
45826  *    indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
45827  *    in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
45828  *    or the Ethernet DA address.
45829  *  0b0..Queue 3 disabled for DA-based DMA Channel Selection
45830  *  0b1..Queue 3 enabled for DA-based DMA Channel Selection
45831  */
45832 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
45833 /*! @} */
45834 
45835 /*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
45836 /*! @{ */
45837 
45838 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK  (0x7U)
45839 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
45840 /*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
45841  *    in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45842  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45843  *    field is valid when the Q4DDMACH field is reset.
45844  */
45845 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
45846 
45847 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK  (0x10U)
45848 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
45849 /*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45850  *    the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
45851  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45852  *    Ethernet DA address.
45853  *  0b0..Queue 4 disabled for DA-based DMA Channel Selection
45854  *  0b1..Queue 4 enabled for DA-based DMA Channel Selection
45855  */
45856 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
45857 /*! @} */
45858 
45859 /*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
45860 /*! @{ */
45861 
45862 #define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK          (0x1U)
45863 #define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT         (0U)
45864 /*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
45865  *    is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
45866  *    current list.
45867  *  0b0..EST offset Mode is disabled
45868  *  0b1..EST offset Mode is enabled
45869  */
45870 #define ENET_QOS_MTL_TBS_CTRL_ESTM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
45871 
45872 #define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK          (0x2U)
45873 #define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT         (1U)
45874 /*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
45875  *  0b0..LEOS field is invalid
45876  *  0b1..LEOS field is valid
45877  */
45878 #define ENET_QOS_MTL_TBS_CTRL_LEOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
45879 
45880 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK         (0x70U)
45881 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT        (4U)
45882 /*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time.
45883  */
45884 #define ENET_QOS_MTL_TBS_CTRL_LEGOS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
45885 
45886 #define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK          (0xFFFFFF00U)
45887 #define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT         (8U)
45888 /*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
45889  *    Launch time to compute the Launch Expiry time.
45890  */
45891 #define ENET_QOS_MTL_TBS_CTRL_LEOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
45892 /*! @} */
45893 
45894 /*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
45895 /*! @{ */
45896 
45897 #define ENET_QOS_MTL_EST_CONTROL_EEST_MASK       (0x1U)
45898 #define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT      (0U)
45899 /*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
45900  *  0b0..EST is disabled
45901  *  0b1..EST is enabled
45902  */
45903 #define ENET_QOS_MTL_EST_CONTROL_EEST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
45904 
45905 #define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK       (0x2U)
45906 #define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT      (1U)
45907 /*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
45908  *    that it currently owns (SWOL) and the hardware should switch to the new list based on the new
45909  *    BTR.
45910  *  0b0..Switch to S/W owned list is disabled
45911  *  0b1..Switch to S/W owned list is enabled
45912  */
45913 #define ENET_QOS_MTL_EST_CONTROL_SSWL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
45914 
45915 #define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK       (0x10U)
45916 #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT      (4U)
45917 /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
45918  *    Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
45919  *  0b1..Do not Drop frames during Frame Size Error
45920  *  0b0..Drop frames during Frame Size Error
45921  */
45922 #define ENET_QOS_MTL_EST_CONTROL_DDBF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
45923 
45924 #define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK       (0x20U)
45925 #define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT      (5U)
45926 /*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
45927  *    to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
45928  *    field of this register) GCL iterations are dropped.
45929  *  0b0..Do not Drop Frames causing Scheduling Error
45930  *  0b1..Drop Frames causing Scheduling Error
45931  */
45932 #define ENET_QOS_MTL_EST_CONTROL_DFBS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
45933 
45934 #define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK       (0xC0U)
45935 #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT      (6U)
45936 /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
45937  *    reporting an HLBS error defined in EST_STATUS register.
45938  *  0b10..16 iterations
45939  *  0b11..32 iterations
45940  *  0b00..4 iterations
45941  *  0b01..8 iterations
45942  */
45943 #define ENET_QOS_MTL_EST_CONTROL_LCSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
45944 
45945 #define ENET_QOS_MTL_EST_CONTROL_TILS_MASK       (0x700U)
45946 #define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT      (8U)
45947 /*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
45948  *    programmed Time Interval values used in the Gate Control Lists.
45949  */
45950 #define ENET_QOS_MTL_EST_CONTROL_TILS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
45951 
45952 #define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK       (0xFFF000U)
45953 #define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT      (12U)
45954 /*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
45955  *    added to the current time to compensate for all the implementation pipeline delays such as the CDC
45956  *    sync delay, buffering delays, data path delays etc.
45957  */
45958 #define ENET_QOS_MTL_EST_CONTROL_CTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
45959 
45960 #define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK       (0xFF000000U)
45961 #define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT      (24U)
45962 /*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds.
45963  */
45964 #define ENET_QOS_MTL_EST_CONTROL_PTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
45965 /*! @} */
45966 
45967 /*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
45968 /*! @{ */
45969 
45970 #define ENET_QOS_MTL_EST_STATUS_SWLC_MASK        (0x1U)
45971 #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT       (0U)
45972 /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
45973  *    switched to the SWOL, and the SWOL bit has been updated to that effect.
45974  *  0b1..Switch to S/W owned list Complete detected
45975  *  0b0..Switch to S/W owned list Complete not detected
45976  */
45977 #define ENET_QOS_MTL_EST_STATUS_SWLC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
45978 
45979 #define ENET_QOS_MTL_EST_STATUS_BTRE_MASK        (0x2U)
45980 #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT       (1U)
45981 /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
45982  *    value is less than current time.
45983  *  0b1..BTR Error detected
45984  *  0b0..BTR Error not detected
45985  */
45986 #define ENET_QOS_MTL_EST_STATUS_BTRE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
45987 
45988 #define ENET_QOS_MTL_EST_STATUS_HLBF_MASK        (0x4U)
45989 #define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT       (2U)
45990 /*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
45991  *    Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
45992  *    equal to the duration needed for frame size (or frame fragment size when preemption is
45993  *    enabled) transmission.
45994  *  0b1..Head-Of-Line Blocking due to Frame Size detected
45995  *  0b0..Head-Of-Line Blocking due to Frame Size not detected
45996  */
45997 #define ENET_QOS_MTL_EST_STATUS_HLBF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
45998 
45999 #define ENET_QOS_MTL_EST_STATUS_HLBS_MASK        (0x8U)
46000 #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT       (3U)
46001 /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
46002  *    and get scheduled even after 4 iterations of the GCL.
46003  *  0b1..Head-Of-Line Blocking due to Scheduling detected
46004  *  0b0..Head-Of-Line Blocking due to Scheduling not detected
46005  */
46006 #define ENET_QOS_MTL_EST_STATUS_HLBS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
46007 
46008 #define ENET_QOS_MTL_EST_STATUS_CGCE_MASK        (0x10U)
46009 #define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT       (4U)
46010 /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
46011  *    programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
46012  *    Cycle Time (CTR).
46013  *  0b1..Constant Gate Control Error detected
46014  *  0b0..Constant Gate Control Error not detected
46015  */
46016 #define ENET_QOS_MTL_EST_STATUS_CGCE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
46017 
46018 #define ENET_QOS_MTL_EST_STATUS_SWOL_MASK        (0x80U)
46019 #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT       (7U)
46020 /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
46021  *    when "1" indicates the Gate Control list "1" is owned by the software.
46022  *  0b1..Gate control list number "1" is owned by software
46023  *  0b0..Gate control list number "0" is owned by software
46024  */
46025 #define ENET_QOS_MTL_EST_STATUS_SWOL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
46026 
46027 #define ENET_QOS_MTL_EST_STATUS_BTRL_MASK        (0xF00U)
46028 #define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT       (8U)
46029 /*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
46030  *    =< New BTR + (N * New Cycle Time) becomes true.
46031  */
46032 #define ENET_QOS_MTL_EST_STATUS_BTRL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
46033 
46034 #define ENET_QOS_MTL_EST_STATUS_CGSN_MASK        (0xF0000U)
46035 #define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT       (16U)
46036 /*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list.
46037  */
46038 #define ENET_QOS_MTL_EST_STATUS_CGSN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
46039 /*! @} */
46040 
46041 /*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
46042 /*! @{ */
46043 
46044 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK     (0x1FU)
46045 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT    (0U)
46046 /*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
46047  *    error/timeout described in HLBS field of status register.
46048  */
46049 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
46050 /*! @} */
46051 
46052 /*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
46053 /*! @{ */
46054 
46055 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
46056 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
46057 /*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
46058  *    error described in HLBF field of status register.
46059  */
46060 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
46061 /*! @} */
46062 
46063 /*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
46064 /*! @{ */
46065 
46066 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
46067 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
46068 /*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
46069  *    indicated in HBFQ field of this register.
46070  */
46071 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
46072 
46073 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
46074 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
46075 /*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
46076  *    experiencing HLBF error (see HLBF field of status register).
46077  */
46078 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
46079 /*! @} */
46080 
46081 /*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
46082 /*! @{ */
46083 
46084 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK   (0x1U)
46085 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT  (0U)
46086 /*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
46087  *    change is successful and the hardware has switched to the new list.
46088  *  0b0..Interrupt for Switch List is disabled
46089  *  0b1..Interrupt for Switch List is enabled
46090  */
46091 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
46092 
46093 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK   (0x2U)
46094 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT  (1U)
46095 /*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
46096  *  0b0..Interrupt for BTR Error is disabled
46097  *  0b1..Interrupt for BTR Error is enabled
46098  */
46099 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
46100 
46101 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK   (0x4U)
46102 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT  (2U)
46103 /*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
46104  *    due to Frame Size error occurs and is indicated in the status.
46105  *  0b0..Interrupt for HLBF is disabled
46106  *  0b1..Interrupt for HLBF is enabled
46107  */
46108 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
46109 
46110 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK   (0x8U)
46111 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT  (3U)
46112 /*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
46113  *    due to Scheduling issue and is indicated in the status.
46114  *  0b0..Interrupt for HLBS is disabled
46115  *  0b1..Interrupt for HLBS is enabled
46116  */
46117 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
46118 
46119 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK   (0x10U)
46120 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT  (4U)
46121 /*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
46122  *    Error occurs and is indicated in the status.
46123  *  0b0..Interrupt for CGCE is disabled
46124  *  0b1..Interrupt for CGCE is enabled
46125  */
46126 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
46127 /*! @} */
46128 
46129 /*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
46130 /*! @{ */
46131 
46132 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK   (0x1U)
46133 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT  (0U)
46134 /*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
46135  *  0b0..Start Read/Write Op disabled
46136  *  0b1..Start Read/Write Op enabled
46137  */
46138 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
46139 
46140 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK   (0x2U)
46141 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT  (1U)
46142 /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
46143  *  0b1..Read Operation
46144  *  0b0..Write Operation
46145  */
46146 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
46147 
46148 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK   (0x4U)
46149 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT  (2U)
46150 /*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
46151  *    related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
46152  *  0b0..Gate Control Related Registers are disabled
46153  *  0b1..Gate Control Related Registers are enabled
46154  */
46155 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
46156 
46157 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK   (0x10U)
46158 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT  (4U)
46159 /*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
46160  *    Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
46161  *    used to determine which bank to use.
46162  *  0b0..Debug Mode is disabled
46163  *  0b1..Debug Mode is enabled
46164  */
46165 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
46166 
46167 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK   (0x20U)
46168 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT  (5U)
46169 /*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
46170  *    Bank 0 (GCL0 and corresponding Time related registers).
46171  *  0b0..R/W in debug mode should be directed to Bank 0
46172  *  0b1..R/W in debug mode should be directed to Bank 1
46173  */
46174 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
46175 
46176 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK   (0x1FF00U)
46177 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT  (8U)
46178 /*! ADDR - Gate Control List Address: (GCLA when GCRR is "0").
46179  */
46180 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
46181 
46182 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK   (0x100000U)
46183 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT  (20U)
46184 /*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
46185  *    registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
46186  *  0b0..ERR0 is disabled
46187  *  0b1..ERR1 is enabled
46188  */
46189 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
46190 
46191 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
46192 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
46193 /*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
46194  *    enables the ECC error injection feature.
46195  *  0b0..EST ECC Inject Error is disabled
46196  *  0b1..EST ECC Inject Error is enabled
46197  */
46198 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
46199 
46200 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
46201 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
46202 /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
46203  *    following are the errors inserted based on the value encoded in this field.
46204  *  0b00..Insert 1 bit error
46205  *  0b11..Insert 1 bit error in address field
46206  *  0b01..Insert 2 bit errors
46207  *  0b10..Insert 3 bit errors
46208  */
46209 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
46210 /*! @} */
46211 
46212 /*! @name MTL_EST_GCL_DATA - EST GCL Data */
46213 /*! @{ */
46214 
46215 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK       (0xFFFFFFFFU)
46216 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT      (0U)
46217 /*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register.
46218  */
46219 #define ENET_QOS_MTL_EST_GCL_DATA_GCD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
46220 /*! @} */
46221 
46222 /*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
46223 /*! @{ */
46224 
46225 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK      (0x3U)
46226 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT     (0U)
46227 /*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
46228  *    bytes over 64 bytes required in non-final fragments of preempted frames.
46229  */
46230 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
46231 
46232 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK       (0x1F00U)
46233 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT      (8U)
46234 /*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
46235  *    preemptable, when '0' Queue is classified as express.
46236  */
46237 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
46238 
46239 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK       (0x10000000U)
46240 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT      (28U)
46241 /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
46242  *  0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
46243  *  0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
46244  */
46245 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
46246 /*! @} */
46247 
46248 /*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
46249 /*! @{ */
46250 
46251 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK       (0xFFFFU)
46252 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT      (0U)
46253 /*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
46254  *    the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
46255  *    transmission or any preemptable frames that are queued for transmission.
46256  */
46257 #define ENET_QOS_MTL_FPE_ADVANCE_HADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
46258 
46259 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK       (0xFFFF0000U)
46260 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT      (16U)
46261 /*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
46262  *    to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
46263  *    absence of there being any express frames available for transmission.
46264  */
46265 #define ENET_QOS_MTL_FPE_ADVANCE_RADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
46266 /*! @} */
46267 
46268 /*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
46269 /*! @{ */
46270 
46271 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
46272 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
46273 /*! NVE - Number of valid entries in the Instruction table This control indicates the number of
46274  *    valid entries in the Instruction Memory.
46275  */
46276 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
46277 
46278 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
46279 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
46280 /*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
46281  *    parsable entries in the Instruction Memory.
46282  */
46283 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
46284 
46285 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
46286 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
46287 /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
46288  *    and waiting for a new packet for processing.
46289  *  0b1..RX Parser in Idle state
46290  *  0b0..RX Parser not in Idle state
46291  */
46292 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
46293 /*! @} */
46294 
46295 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
46296 /*! @{ */
46297 
46298 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
46299 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
46300 /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
46301  *    address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
46302  *    this bit is set to 1.
46303  *  0b1..Number of Valid Entries Overflow Interrupt Status detected
46304  *  0b0..Number of Valid Entries Overflow Interrupt Status not detected
46305  */
46306 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
46307 
46308 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
46309 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
46310 /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
46311  *    number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
46312  *    MTL_RXP_CONTROL register),then this bit is set to 1.
46313  *  0b1..Number of Parsable Entries Overflow Interrupt Status detected
46314  *  0b0..Number of Parsable Entries Overflow Interrupt Status not detected
46315  */
46316 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
46317 
46318 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
46319 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
46320 /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
46321  *    'Frame Offset' found to be more than EOF offset, then then this bit is set.
46322  *  0b1..Frame Offset Overflow Interrupt Status detected
46323  *  0b0..Frame Offset Overflow Interrupt Status not detected
46324  */
46325 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
46326 
46327 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
46328 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
46329 /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
46330  *    packet by setting RF=1 in the instruction memory, then this bit is set to 1.
46331  *  0b1..Packet Dropped due to RF Interrupt Status detected
46332  *  0b0..Packet Dropped due to RF Interrupt Status not detected
46333  */
46334 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
46335 
46336 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
46337 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
46338 /*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
46339  *  0b0..Number of Valid Entries Overflow Interrupt is disabled
46340  *  0b1..Number of Valid Entries Overflow Interrupt is enabled
46341  */
46342 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
46343 
46344 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
46345 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
46346 /*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
46347  *  0b0..Number of Parsable Entries Overflow Interrupt is disabled
46348  *  0b1..Number of Parsable Entries Overflow Interrupt is enabled
46349  */
46350 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
46351 
46352 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
46353 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
46354 /*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
46355  *  0b0..Frame Offset Overflow Interrupt is disabled
46356  *  0b1..Frame Offset Overflow Interrupt is enabled
46357  */
46358 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
46359 
46360 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
46361 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
46362 /*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
46363  *  0b0..Packet Drop due to RF Interrupt is disabled
46364  *  0b1..Packet Drop due to RF Interrupt is enabled
46365  */
46366 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
46367 /*! @} */
46368 
46369 /*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
46370 /*! @{ */
46371 
46372 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK     (0x7FFFFFFFU)
46373 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT    (0U)
46374 /*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1.
46375  */
46376 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
46377 
46378 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK  (0x80000000U)
46379 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
46380 /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
46381  *    MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
46382  *  0b1..Rx Parser Drop count overflow occurred
46383  *  0b0..Rx Parser Drop count overflow not occurred
46384  */
46385 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
46386 /*! @} */
46387 
46388 /*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
46389 /*! @{ */
46390 
46391 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK    (0x7FFFFFFFU)
46392 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT   (0U)
46393 /*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
46394  *    following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
46395  *    address > EOF data entry address The counter is cleared when the register is read.
46396  */
46397 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
46398 
46399 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
46400 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
46401 /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
46402  *    MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
46403  *  0b1..Rx Parser Error count overflow occurred
46404  *  0b0..Rx Parser Error count overflow not occurred
46405  */
46406 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
46407 /*! @} */
46408 
46409 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
46410 /*! @{ */
46411 
46412 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
46413 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
46414 /*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table.
46415  */
46416 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
46417 
46418 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
46419 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
46420 /*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
46421  *  0b0..Read operation to the Rx Parser Memory
46422  *  0b1..Write operation to the Rx Parser Memory
46423  */
46424 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
46425 
46426 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
46427 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
46428 /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
46429  *    indicates to start the Read/Write operation from/to the Rx Parser Memory.
46430  *  0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
46431  *  0b0..hardware not busy
46432  */
46433 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
46434 /*! @} */
46435 
46436 /*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
46437 /*! @{ */
46438 
46439 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
46440 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
46441 /*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command.
46442  */
46443 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
46444 /*! @} */
46445 
46446 /*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
46447 /*! @{ */
46448 
46449 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK       (0x1U)
46450 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT      (0U)
46451 /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
46452  *  0b0..Flush Transmit Queue is disabled
46453  *  0b1..Flush Transmit Queue is enabled
46454  */
46455 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
46456 
46457 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK       (0x2U)
46458 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT      (1U)
46459 /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
46460  *  0b0..Transmit Store and Forward is disabled
46461  *  0b1..Transmit Store and Forward is enabled
46462  */
46463 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
46464 
46465 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK     (0xCU)
46466 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT    (2U)
46467 /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
46468  *  0b00..Not enabled
46469  *  0b10..Enabled
46470  *  0b01..Enable in AV mode (Reserved in non-AV)
46471  *  0b11..Reserved
46472  */
46473 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
46474 
46475 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK       (0x70U)
46476 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT      (4U)
46477 /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
46478  *  0b011..128
46479  *  0b100..192
46480  *  0b101..256
46481  *  0b000..32
46482  *  0b110..384
46483  *  0b111..512
46484  *  0b001..64
46485  *  0b010..96
46486  */
46487 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
46488 
46489 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK       (0x1F0000U)
46490 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT      (16U)
46491 /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
46492  */
46493 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
46494 /*! @} */
46495 
46496 /* The count of ENET_QOS_MTL_TXQX_OP_MODE */
46497 #define ENET_QOS_MTL_TXQX_OP_MODE_COUNT          (5U)
46498 
46499 /*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
46500 /*! @{ */
46501 
46502 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK  (0x7FFU)
46503 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
46504 /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
46505  *    controller because of Tx Queue Underflow.
46506  */
46507 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
46508 
46509 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK  (0x800U)
46510 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
46511 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
46512  *    Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
46513  *  0b1..Overflow detected for Underflow Packet Counter
46514  *  0b0..Overflow not detected for Underflow Packet Counter
46515  */
46516 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
46517 /*! @} */
46518 
46519 /* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
46520 #define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT          (5U)
46521 
46522 /*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
46523 /*! @{ */
46524 
46525 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK     (0x1U)
46526 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT    (0U)
46527 /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
46528  *    indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
46529  *    of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
46530  *    when PFC is enabled - Reception of 802.
46531  *  0b1..Transmit Queue in Pause status is detected
46532  *  0b0..Transmit Queue in Pause status is not detected
46533  */
46534 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
46535 
46536 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK        (0x6U)
46537 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT       (1U)
46538 /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
46539  *  0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
46540  *  0b00..Idle state
46541  *  0b01..Read state (transferring data to the MAC transmitter)
46542  *  0b10..Waiting for pending Tx Status from the MAC transmitter
46543  */
46544 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
46545 
46546 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK        (0x8U)
46547 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT       (3U)
46548 /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
46549  *    Queue Write Controller is active, and it is transferring the data to the Tx Queue.
46550  *  0b1..MTL Tx Queue Write Controller status is detected
46551  *  0b0..MTL Tx Queue Write Controller status is not detected
46552  */
46553 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
46554 
46555 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK        (0x10U)
46556 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT       (4U)
46557 /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
46558  *    is not empty and some data is left for transmission.
46559  *  0b1..MTL Tx Queue Not Empty status is detected
46560  *  0b0..MTL Tx Queue Not Empty status is not detected
46561  */
46562 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
46563 
46564 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK     (0x20U)
46565 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT    (5U)
46566 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
46567  *  0b1..MTL Tx Status FIFO Full status is detected
46568  *  0b0..MTL Tx Status FIFO Full status is not detected
46569  */
46570 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
46571 
46572 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK          (0x70000U)
46573 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT         (16U)
46574 /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
46575  */
46576 #define ENET_QOS_MTL_TXQX_DBG_PTXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
46577 
46578 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK       (0x700000U)
46579 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT      (20U)
46580 /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
46581  *    number of status in the Tx Status FIFO of this queue.
46582  */
46583 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
46584 /*! @} */
46585 
46586 /* The count of ENET_QOS_MTL_TXQX_DBG */
46587 #define ENET_QOS_MTL_TXQX_DBG_COUNT              (5U)
46588 
46589 /*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
46590 /*! @{ */
46591 
46592 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK    (0x4U)
46593 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT   (2U)
46594 /*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
46595  *    algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
46596  *    selected for Queue 1 traffic.
46597  *  0b0..CBS Algorithm is disabled
46598  *  0b1..CBS Algorithm is enabled
46599  */
46600 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
46601 
46602 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK       (0x8U)
46603 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT      (3U)
46604 /*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
46605  *    shaper algorithm logic is not reset to zero when there is positive credit and no packet to
46606  *    transmit in Channel 1.
46607  *  0b0..Credit Control is disabled
46608  *  0b1..Credit Control is enabled
46609  */
46610 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
46611 
46612 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK      (0x70U)
46613 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT     (4U)
46614 /*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
46615  *    number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
46616  *    average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
46617  *    computed for Queue.
46618  *  0b100..16 slots
46619  *  0b000..1 slot
46620  *  0b001..2 slots
46621  *  0b010..4 slots
46622  *  0b011..8 slots
46623  *  0b101..Reserved
46624  */
46625 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
46626 /*! @} */
46627 
46628 /* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
46629 #define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT         (5U)
46630 
46631 /*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
46632 /*! @{ */
46633 
46634 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK      (0xFFFFFFU)
46635 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT     (0U)
46636 /*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot.
46637  */
46638 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
46639 /*! @} */
46640 
46641 /* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
46642 #define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT         (5U)
46643 
46644 /*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
46645 /*! @{ */
46646 
46647 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK   (0x1FFFFFU)
46648 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT  (0U)
46649 /*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
46650  *    traffic, this field contains the quantum value in bytes to be added to credit during every queue
46651  *    scanning cycle.
46652  */
46653 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
46654 /*! @} */
46655 
46656 /* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
46657 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT        (5U)
46658 
46659 /*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
46660 /*! @{ */
46661 
46662 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK   (0x3FFFU)
46663 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT  (0U)
46664 /*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
46665  *    sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
46666  */
46667 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
46668 /*! @} */
46669 
46670 /* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
46671 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT      (5U)
46672 
46673 /*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
46674 /*! @{ */
46675 
46676 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK        (0x1FFFFFFFU)
46677 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT       (0U)
46678 /*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
46679  *    required for the credit-based shaper algorithm.
46680  */
46681 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
46682 /*! @} */
46683 
46684 /* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
46685 #define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT          (5U)
46686 
46687 /*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
46688 /*! @{ */
46689 
46690 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK        (0x1FFFFFFFU)
46691 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT       (0U)
46692 /*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
46693  *    required for the credit-based shaper algorithm.
46694  */
46695 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
46696 /*! @} */
46697 
46698 /* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
46699 #define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT          (5U)
46700 
46701 /*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
46702 /*! @{ */
46703 
46704 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
46705 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
46706 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
46707  *    had an underflow while transmitting the packet.
46708  *  0b1..Transmit Queue Underflow Interrupt Status detected
46709  *  0b0..Transmit Queue Underflow Interrupt Status not detected
46710  */
46711 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
46712 
46713 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
46714 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
46715 /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
46716  *  0b1..Average Bits Per Slot Interrupt Status detected
46717  *  0b0..Average Bits Per Slot Interrupt Status not detected
46718  */
46719 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
46720 
46721 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
46722 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
46723 /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
46724  *  0b0..Transmit Queue Underflow Interrupt Status is disabled
46725  *  0b1..Transmit Queue Underflow Interrupt Status is enabled
46726  */
46727 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
46728 
46729 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
46730 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
46731 /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
46732  *    sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
46733  *  0b0..Average Bits Per Slot Interrupt is disabled
46734  *  0b1..Average Bits Per Slot Interrupt is enabled
46735  */
46736 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
46737 
46738 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
46739 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
46740 /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
46741  *    an overflow while receiving the packet.
46742  *  0b1..Receive Queue Overflow Interrupt Status detected
46743  *  0b0..Receive Queue Overflow Interrupt Status not detected
46744  */
46745 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
46746 
46747 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
46748 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
46749 /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
46750  *  0b0..Receive Queue Overflow Interrupt is disabled
46751  *  0b1..Receive Queue Overflow Interrupt is enabled
46752  */
46753 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
46754 /*! @} */
46755 
46756 /* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
46757 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT     (5U)
46758 
46759 /*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
46760 /*! @{ */
46761 
46762 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK       (0x3U)
46763 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT      (0U)
46764 /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
46765  *    (in bytes): The received packet is transferred to the application or DMA when the packet size
46766  *    within the MTL Rx queue is larger than the threshold.
46767  *  0b11..128
46768  *  0b01..32
46769  *  0b00..64
46770  *  0b10..96
46771  */
46772 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
46773 
46774 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK       (0x8U)
46775 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT      (3U)
46776 /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
46777  *    good packets (packets with no error and length less than 64 bytes), including pad-bytes and
46778  *    CRC.
46779  *  0b0..Forward Undersized Good Packets is disabled
46780  *  0b1..Forward Undersized Good Packets is enabled
46781  */
46782 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
46783 
46784 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK       (0x10U)
46785 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT      (4U)
46786 /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
46787  *    (CRC error, GMII_ER, watchdog timeout, or overflow).
46788  *  0b0..Forward Error Packets is disabled
46789  *  0b1..Forward Error Packets is enabled
46790  */
46791 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
46792 
46793 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK       (0x20U)
46794 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT      (5U)
46795 /*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
46796  *    from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
46797  *    of this register.
46798  *  0b0..Receive Queue Store and Forward is disabled
46799  *  0b1..Receive Queue Store and Forward is enabled
46800  */
46801 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
46802 
46803 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
46804 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
46805 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
46806  *    does not drop the packets which only have the errors detected by the Receive Checksum Offload
46807  *    engine.
46808  *  0b1..Dropping of TCP/IP Checksum Error Packets is disabled
46809  *  0b0..Dropping of TCP/IP Checksum Error Packets is enabled
46810  */
46811 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
46812 
46813 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK      (0x80U)
46814 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT     (7U)
46815 /*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
46816  *    based on the fill-level of Rx queue, is enabled.
46817  *  0b0..Hardware Flow Control is disabled
46818  *  0b1..Hardware Flow Control is enabled
46819  */
46820 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
46821 
46822 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK       (0xF00U)
46823 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT      (8U)
46824 /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
46825  *    the threshold (fill-level of Rx queue) at which the flow control is activated: For more
46826  *    information on encoding for this field, see RFD.
46827  */
46828 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
46829 
46830 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK       (0x3C000U)
46831 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT      (14U)
46832 /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
46833  *    control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
46834  *    activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
46835  */
46836 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
46837 
46838 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK       (0x1F00000U)
46839 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT      (20U)
46840 /*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
46841  */
46842 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
46843 /*! @} */
46844 
46845 /* The count of ENET_QOS_MTL_RXQX_OP_MODE */
46846 #define ENET_QOS_MTL_RXQX_OP_MODE_COUNT          (5U)
46847 
46848 /*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
46849 /*! @{ */
46850 
46851 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
46852 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
46853 /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
46854  *    DWC_ether_qos because of Receive queue overflow.
46855  */
46856 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
46857 
46858 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
46859 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
46860 /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
46861  *    Overflow Packet Counter field crossed the maximum limit.
46862  *  0b1..Overflow Counter overflow detected
46863  *  0b0..Overflow Counter overflow not detected
46864  */
46865 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
46866 
46867 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
46868 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
46869 /*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
46870  *    DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
46871  */
46872 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
46873 
46874 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
46875 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
46876 /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
46877  *    Missed Packet Counter crossed the maximum limit.
46878  *  0b1..Missed Packet Counter overflow detected
46879  *  0b0..Missed Packet Counter overflow not detected
46880  */
46881 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
46882 /*! @} */
46883 
46884 /* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
46885 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
46886 
46887 /*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
46888 /*! @{ */
46889 
46890 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK        (0x1U)
46891 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT       (0U)
46892 /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
46893  *    Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
46894  *  0b1..MTL Rx Queue Write Controller Active Status detected
46895  *  0b0..MTL Rx Queue Write Controller Active Status not detected
46896  */
46897 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
46898 
46899 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK        (0x6U)
46900 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT       (1U)
46901 /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
46902  *  0b11..Flushing the packet data and status
46903  *  0b00..Idle state
46904  *  0b01..Reading packet data
46905  *  0b10..Reading packet status (or timestamp)
46906  */
46907 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
46908 
46909 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK        (0x30U)
46910 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT       (4U)
46911 /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
46912  *  0b10..Rx Queue fill-level above flow-control activate threshold
46913  *  0b01..Rx Queue fill-level below flow-control deactivate threshold
46914  *  0b00..Rx Queue empty
46915  *  0b11..Rx Queue full
46916  */
46917 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
46918 
46919 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK          (0x3FFF0000U)
46920 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT         (16U)
46921 /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
46922  */
46923 #define ENET_QOS_MTL_RXQX_DBG_PRXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
46924 /*! @} */
46925 
46926 /* The count of ENET_QOS_MTL_RXQX_DBG */
46927 #define ENET_QOS_MTL_RXQX_DBG_COUNT              (5U)
46928 
46929 /*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
46930 /*! @{ */
46931 
46932 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK     (0x7U)
46933 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT    (0U)
46934 /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
46935  */
46936 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
46937 
46938 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
46939 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
46940 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
46941  *    the packet data to the ARI interface such that the entire packet data of currently-selected
46942  *    queue is transmitted before switching to other queue.
46943  *  0b0..Receive Queue Packet Arbitration is disabled
46944  *  0b1..Receive Queue Packet Arbitration is enabled
46945  */
46946 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
46947 /*! @} */
46948 
46949 /* The count of ENET_QOS_MTL_RXQX_CTRL */
46950 #define ENET_QOS_MTL_RXQX_CTRL_COUNT             (5U)
46951 
46952 /*! @name DMA_MODE - DMA Bus Mode */
46953 /*! @{ */
46954 
46955 #define ENET_QOS_DMA_MODE_SWR_MASK               (0x1U)
46956 #define ENET_QOS_DMA_MODE_SWR_SHIFT              (0U)
46957 /*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
46958  *    all internal registers of the DMA, MTL, and MAC.
46959  *  0b0..Software Reset is disabled
46960  *  0b1..Software Reset is enabled
46961  */
46962 #define ENET_QOS_DMA_MODE_SWR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
46963 
46964 #define ENET_QOS_DMA_MODE_DSPW_MASK              (0x100U)
46965 #define ENET_QOS_DMA_MODE_DSPW_SHIFT             (8U)
46966 /*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
46967  *  0b0..Descriptor Posted Write is disabled
46968  *  0b1..Descriptor Posted Write is enabled
46969  */
46970 #define ENET_QOS_DMA_MODE_DSPW(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
46971 
46972 #define ENET_QOS_DMA_MODE_INTM_MASK              (0x30000U)
46973 #define ENET_QOS_DMA_MODE_INTM_SHIFT             (16U)
46974 /*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
46975  *  0b00..See above description
46976  *  0b01..See above description
46977  *  0b10..See above description
46978  *  0b11..Reserved
46979  */
46980 #define ENET_QOS_DMA_MODE_INTM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
46981 /*! @} */
46982 
46983 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
46984 /*! @{ */
46985 
46986 #define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK         (0x1U)
46987 #define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT        (0U)
46988 /*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
46989  *    of specified lengths as given below.
46990  *  0b0..Fixed Burst Length is disabled
46991  *  0b1..Fixed Burst Length is enabled
46992  */
46993 #define ENET_QOS_DMA_SYSBUS_MODE_FB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
46994 
46995 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK      (0x2U)
46996 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT     (1U)
46997 /*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
46998  *    master can select a burst length of 4 on the AXI interface.
46999  *  0b0..No effect
47000  *  0b1..AXI Burst Length 4
47001  */
47002 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
47003 
47004 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK      (0x4U)
47005 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT     (2U)
47006 /*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
47007  *    master can select a burst length of 8 on the AXI interface.
47008  *  0b0..No effect
47009  *  0b1..AXI Burst Length 8
47010  */
47011 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
47012 
47013 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK     (0x8U)
47014 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT    (3U)
47015 /*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
47016  *    master can select a burst length of 16 on the AXI interface.
47017  *  0b0..No effect
47018  *  0b1..AXI Burst Length 16
47019  */
47020 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
47021 
47022 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK       (0x400U)
47023 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT      (10U)
47024 /*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
47025  *    when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
47026  *    the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
47027  *  0b0..Automatic AXI LPI is disabled
47028  *  0b1..Automatic AXI LPI is enabled
47029  */
47030 #define ENET_QOS_DMA_SYSBUS_MODE_AALE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
47031 
47032 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK        (0x1000U)
47033 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT       (12U)
47034 /*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
47035  *    address-aligned burst transfers on Read and Write channels.
47036  *  0b0..Address-Aligned Beats is disabled
47037  *  0b1..Address-Aligned Beats is enabled
47038  */
47039 #define ENET_QOS_DMA_SYSBUS_MODE_AAL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
47040 
47041 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK    (0x2000U)
47042 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT   (13U)
47043 /*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
47044  *    performed by the EQOS-AXI master do not cross 1 KB boundary.
47045  *  0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
47046  *  0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
47047  */
47048 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
47049 
47050 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
47051 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
47052 /*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface.
47053  */
47054 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
47055 
47056 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
47057 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
47058 /*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
47059  *    outstanding request on the AXI write interface.
47060  */
47061 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
47062 
47063 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
47064 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
47065 /*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
47066  *    the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
47067  *    is received.
47068  *  0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
47069  *  0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
47070  */
47071 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
47072 
47073 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK     (0x80000000U)
47074 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT    (31U)
47075 /*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
47076  *    by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
47077  *    controller.
47078  *  0b0..Low Power Interface (LPI) is disabled
47079  *  0b1..Low Power Interface (LPI) is enabled
47080  */
47081 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
47082 /*! @} */
47083 
47084 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
47085 /*! @{ */
47086 
47087 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
47088 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
47089 /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
47090  *  0b1..DMA Channel 0 Interrupt Status detected
47091  *  0b0..DMA Channel 0 Interrupt Status not detected
47092  */
47093 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
47094 
47095 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
47096 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
47097 /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
47098  *  0b1..DMA Channel 1 Interrupt Status detected
47099  *  0b0..DMA Channel 1 Interrupt Status not detected
47100  */
47101 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
47102 
47103 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
47104 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
47105 /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
47106  *  0b1..DMA Channel 2 Interrupt Status detected
47107  *  0b0..DMA Channel 2 Interrupt Status not detected
47108  */
47109 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
47110 
47111 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
47112 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
47113 /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
47114  *  0b1..DMA Channel 3 Interrupt Status detected
47115  *  0b0..DMA Channel 3 Interrupt Status not detected
47116  */
47117 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
47118 
47119 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
47120 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
47121 /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
47122  *  0b1..DMA Channel 4 Interrupt Status detected
47123  *  0b0..DMA Channel 4 Interrupt Status not detected
47124  */
47125 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
47126 
47127 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
47128 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
47129 /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
47130  *  0b1..MTL Interrupt Status detected
47131  *  0b0..MTL Interrupt Status not detected
47132  */
47133 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
47134 
47135 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
47136 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
47137 /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
47138  *  0b1..MAC Interrupt Status detected
47139  *  0b0..MAC Interrupt Status not detected
47140  */
47141 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
47142 /*! @} */
47143 
47144 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
47145 /*! @{ */
47146 
47147 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK  (0x1U)
47148 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
47149 /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
47150  *    AXI master is active, and it is transferring data.
47151  *  0b1..AXI Master Write Channel or AHB Master Status detected
47152  *  0b0..AXI Master Write Channel or AHB Master Status not detected
47153  */
47154 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
47155 
47156 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK  (0x2U)
47157 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
47158 /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
47159  *    the AXI master is active, and it is transferring the data.
47160  *  0b1..AXI Master Read Channel Status detected
47161  *  0b0..AXI Master Read Channel Status not detected
47162  */
47163 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
47164 
47165 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK     (0xF00U)
47166 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT    (8U)
47167 /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
47168  *  0b0010..Reserved for future use
47169  *  0b0101..Running (Closing the Rx Descriptor)
47170  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47171  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47172  *  0b0011..Running (Waiting for Rx packet)
47173  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47174  *  0b0100..Suspended (Rx Descriptor Unavailable)
47175  *  0b0110..Timestamp write state
47176  */
47177 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
47178 
47179 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK     (0xF000U)
47180 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT    (12U)
47181 /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
47182  *  0b0101..Reserved for future use
47183  *  0b0111..Running (Closing Tx Descriptor)
47184  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47185  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47186  *  0b0010..Running (Waiting for status)
47187  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47188  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47189  *  0b0100..Timestamp write state
47190  */
47191 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
47192 
47193 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK     (0xF0000U)
47194 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT    (16U)
47195 /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
47196  *  0b0010..Reserved for future use
47197  *  0b0101..Running (Closing the Rx Descriptor)
47198  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47199  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47200  *  0b0011..Running (Waiting for Rx packet)
47201  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47202  *  0b0100..Suspended (Rx Descriptor Unavailable)
47203  *  0b0110..Timestamp write state
47204  */
47205 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
47206 
47207 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK     (0xF00000U)
47208 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT    (20U)
47209 /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
47210  *  0b0101..Reserved for future use
47211  *  0b0111..Running (Closing Tx Descriptor)
47212  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47213  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47214  *  0b0010..Running (Waiting for status)
47215  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47216  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47217  *  0b0100..Timestamp write state
47218  */
47219 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
47220 
47221 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK     (0xF000000U)
47222 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT    (24U)
47223 /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
47224  *  0b0010..Reserved for future use
47225  *  0b0101..Running (Closing the Rx Descriptor)
47226  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47227  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47228  *  0b0011..Running (Waiting for Rx packet)
47229  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47230  *  0b0100..Suspended (Rx Descriptor Unavailable)
47231  *  0b0110..Timestamp write state
47232  */
47233 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
47234 
47235 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK     (0xF0000000U)
47236 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT    (28U)
47237 /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
47238  *  0b0101..Reserved for future use
47239  *  0b0111..Running (Closing Tx Descriptor)
47240  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47241  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47242  *  0b0010..Running (Waiting for status)
47243  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47244  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47245  *  0b0100..Timestamp write state
47246  */
47247 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
47248 /*! @} */
47249 
47250 /*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
47251 /*! @{ */
47252 
47253 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK     (0xFU)
47254 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT    (0U)
47255 /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
47256  *  0b0010..Reserved for future use
47257  *  0b0101..Running (Closing the Rx Descriptor)
47258  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47259  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47260  *  0b0011..Running (Waiting for Rx packet)
47261  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47262  *  0b0100..Suspended (Rx Descriptor Unavailable)
47263  *  0b0110..Timestamp write state
47264  */
47265 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
47266 
47267 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK     (0xF0U)
47268 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT    (4U)
47269 /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
47270  *  0b0101..Reserved for future use
47271  *  0b0111..Running (Closing Tx Descriptor)
47272  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47273  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47274  *  0b0010..Running (Waiting for status)
47275  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47276  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47277  *  0b0100..Timestamp write state
47278  */
47279 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
47280 
47281 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK     (0xF00U)
47282 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT    (8U)
47283 /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
47284  *  0b0010..Reserved for future use
47285  *  0b0101..Running (Closing the Rx Descriptor)
47286  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47287  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47288  *  0b0011..Running (Waiting for Rx packet)
47289  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47290  *  0b0100..Suspended (Rx Descriptor Unavailable)
47291  *  0b0110..Timestamp write state
47292  */
47293 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
47294 
47295 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK     (0xF000U)
47296 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT    (12U)
47297 /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
47298  *  0b0101..Reserved for future use
47299  *  0b0111..Running (Closing Tx Descriptor)
47300  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47301  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47302  *  0b0010..Running (Waiting for status)
47303  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47304  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47305  *  0b0100..Timestamp write state
47306  */
47307 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
47308 /*! @} */
47309 
47310 /*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
47311 /*! @{ */
47312 
47313 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
47314 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
47315 /*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
47316  *    for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
47317  *    clock cycles
47318  */
47319 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
47320 /*! @} */
47321 
47322 /*! @name DMA_TBS_CTRL - TBS Control */
47323 /*! @{ */
47324 
47325 #define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK          (0x1U)
47326 #define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT         (0U)
47327 /*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
47328  *  0b0..Fetch Time Offset is invalid
47329  *  0b1..Fetch Time Offset is valid
47330  */
47331 #define ENET_QOS_DMA_TBS_CTRL_FTOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
47332 
47333 #define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK          (0x70U)
47334 #define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT         (4U)
47335 /*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN.
47336  */
47337 #define ENET_QOS_DMA_TBS_CTRL_FGOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
47338 
47339 #define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK          (0xFFFFFF00U)
47340 #define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT         (8U)
47341 /*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
47342  *    Launch time to compute the Fetch Time.
47343  */
47344 #define ENET_QOS_DMA_TBS_CTRL_FTOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
47345 /*! @} */
47346 
47347 /*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
47348 /*! @{ */
47349 
47350 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK         (0x10000U)
47351 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT        (16U)
47352 /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
47353  *    DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
47354  *  0b0..8xPBL mode is disabled
47355  *  0b1..8xPBL mode is enabled
47356  */
47357 #define ENET_QOS_DMA_CHX_CTRL_PBLx8(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
47358 
47359 #define ENET_QOS_DMA_CHX_CTRL_DSL_MASK           (0x1C0000U)
47360 #define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT          (18U)
47361 /*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
47362  *    the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
47363  */
47364 #define ENET_QOS_DMA_CHX_CTRL_DSL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
47365 /*! @} */
47366 
47367 /* The count of ENET_QOS_DMA_CHX_CTRL */
47368 #define ENET_QOS_DMA_CHX_CTRL_COUNT              (5U)
47369 
47370 /*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
47371 /*! @{ */
47372 
47373 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK         (0x1U)
47374 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT        (0U)
47375 /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
47376  *  0b1..Start Transmission Command
47377  *  0b0..Stop Transmission Command
47378  */
47379 #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
47380 
47381 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK        (0x10U)
47382 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT       (4U)
47383 /*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
47384  *    packet of the Transmit data even before the status for the first packet is obtained.
47385  *  0b0..Operate on Second Packet disabled
47386  *  0b1..Operate on Second Packet enabled
47387  */
47388 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
47389 
47390 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK       (0x8000U)
47391 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT      (15U)
47392 /*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
47393  *    locations in the MTL before initiating a transfer.
47394  *  0b0..Ignore PBL Requirement is disabled
47395  *  0b1..Ignore PBL Requirement is enabled
47396  */
47397 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
47398 
47399 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK      (0x3F0000U)
47400 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT     (16U)
47401 /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
47402  *    transferred in one DMA block data transfer.
47403  */
47404 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
47405 
47406 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK       (0x10000000U)
47407 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT      (28U)
47408 /*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
47409  *    Descriptors that are 32 Bytes for both Normal and Context Descriptors.
47410  *  0b0..Enhanced Descriptor is disabled
47411  *  0b1..Enhanced Descriptor is enabled
47412  */
47413 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
47414 /*! @} */
47415 
47416 /* The count of ENET_QOS_DMA_CHX_TX_CTRL */
47417 #define ENET_QOS_DMA_CHX_TX_CTRL_COUNT           (5U)
47418 
47419 /*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
47420 /*! @{ */
47421 
47422 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK         (0x1U)
47423 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT        (0U)
47424 /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
47425  *    the Receive list and processes the incoming packets.
47426  *  0b1..Start Receive
47427  *  0b0..Stop Receive
47428  */
47429 #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
47430 
47431 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK   (0xEU)
47432 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT  (1U)
47433 /*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0.
47434  */
47435 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
47436 
47437 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK  (0x7FF0U)
47438 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
47439 /*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0.
47440  */
47441 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
47442 
47443 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK      (0x3F0000U)
47444 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT     (16U)
47445 /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
47446  *    transferred in one DMA block data transfer.
47447  */
47448 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
47449 
47450 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK        (0x80000000U)
47451 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT       (31U)
47452 /*! RPF - Rx Packet Flush.
47453  *  0b0..Rx Packet Flush is disabled
47454  *  0b1..Rx Packet Flush is enabled
47455  */
47456 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
47457 /*! @} */
47458 
47459 /* The count of ENET_QOS_DMA_CHX_RX_CTRL */
47460 #define ENET_QOS_DMA_CHX_RX_CTRL_COUNT           (5U)
47461 
47462 /*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
47463 /*! @{ */
47464 
47465 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
47466 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
47467 /*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list.
47468  */
47469 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
47470 /*! @} */
47471 
47472 /* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
47473 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT  (5U)
47474 
47475 /*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
47476 /*! @{ */
47477 
47478 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
47479 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
47480 /*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list.
47481  */
47482 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
47483 /*! @} */
47484 
47485 /* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
47486 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT  (5U)
47487 
47488 /*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
47489 /*! @{ */
47490 
47491 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
47492 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
47493 /*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring.
47494  */
47495 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
47496 /*! @} */
47497 
47498 /* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
47499 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT   (5U)
47500 
47501 /*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
47502 /*! @{ */
47503 
47504 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
47505 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
47506 /*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring.
47507  */
47508 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
47509 /*! @} */
47510 
47511 /* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
47512 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT   (5U)
47513 
47514 /*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
47515 /*! @{ */
47516 
47517 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
47518 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
47519 /*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring.
47520  */
47521 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
47522 /*! @} */
47523 
47524 /* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
47525 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
47526 
47527 /*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
47528 /*! @{ */
47529 
47530 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
47531 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
47532 /*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring.
47533  */
47534 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
47535 /*! @} */
47536 
47537 /* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
47538 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
47539 
47540 /*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
47541 /*! @{ */
47542 
47543 #define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK         (0x1U)
47544 #define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT        (0U)
47545 /*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
47546  *  0b0..Transmit Interrupt is disabled
47547  *  0b1..Transmit Interrupt is enabled
47548  */
47549 #define ENET_QOS_DMA_CHX_INT_EN_TIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
47550 
47551 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK        (0x2U)
47552 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT       (1U)
47553 /*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
47554  *  0b0..Transmit Stopped is disabled
47555  *  0b1..Transmit Stopped is enabled
47556  */
47557 #define ENET_QOS_DMA_CHX_INT_EN_TXSE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
47558 
47559 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK        (0x4U)
47560 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT       (2U)
47561 /*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
47562  *    Transmit Buffer Unavailable interrupt is enabled.
47563  *  0b0..Transmit Buffer Unavailable is disabled
47564  *  0b1..Transmit Buffer Unavailable is enabled
47565  */
47566 #define ENET_QOS_DMA_CHX_INT_EN_TBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
47567 
47568 #define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK         (0x40U)
47569 #define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT        (6U)
47570 /*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
47571  *  0b0..Receive Interrupt is disabled
47572  *  0b1..Receive Interrupt is enabled
47573  */
47574 #define ENET_QOS_DMA_CHX_INT_EN_RIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
47575 
47576 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK        (0x80U)
47577 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT       (7U)
47578 /*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
47579  *    Receive Buffer Unavailable interrupt is enabled.
47580  *  0b0..Receive Buffer Unavailable is disabled
47581  *  0b1..Receive Buffer Unavailable is enabled
47582  */
47583 #define ENET_QOS_DMA_CHX_INT_EN_RBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
47584 
47585 #define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK         (0x100U)
47586 #define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT        (8U)
47587 /*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
47588  *  0b0..Receive Stopped is disabled
47589  *  0b1..Receive Stopped is enabled
47590  */
47591 #define ENET_QOS_DMA_CHX_INT_EN_RSE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
47592 
47593 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK        (0x200U)
47594 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT       (9U)
47595 /*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
47596  *    Watchdog Timeout interrupt is enabled.
47597  *  0b0..Receive Watchdog Timeout is disabled
47598  *  0b1..Receive Watchdog Timeout is enabled
47599  */
47600 #define ENET_QOS_DMA_CHX_INT_EN_RWTE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
47601 
47602 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK        (0x400U)
47603 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT       (10U)
47604 /*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
47605  *  0b0..Early Transmit Interrupt is disabled
47606  *  0b1..Early Transmit Interrupt is enabled
47607  */
47608 #define ENET_QOS_DMA_CHX_INT_EN_ETIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
47609 
47610 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK        (0x800U)
47611 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT       (11U)
47612 /*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
47613  *  0b0..Early Receive Interrupt is disabled
47614  *  0b1..Early Receive Interrupt is enabled
47615  */
47616 #define ENET_QOS_DMA_CHX_INT_EN_ERIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
47617 
47618 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK        (0x1000U)
47619 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT       (12U)
47620 /*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
47621  *  0b0..Fatal Bus Error is disabled
47622  *  0b1..Fatal Bus Error is enabled
47623  */
47624 #define ENET_QOS_DMA_CHX_INT_EN_FBEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
47625 
47626 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK        (0x2000U)
47627 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT       (13U)
47628 /*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
47629  *  0b0..Context Descriptor Error is disabled
47630  *  0b1..Context Descriptor Error is enabled
47631  */
47632 #define ENET_QOS_DMA_CHX_INT_EN_CDEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
47633 
47634 #define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK         (0x4000U)
47635 #define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT        (14U)
47636 /*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
47637  *  0b0..Abnormal Interrupt Summary is disabled
47638  *  0b1..Abnormal Interrupt Summary is enabled
47639  */
47640 #define ENET_QOS_DMA_CHX_INT_EN_AIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
47641 
47642 #define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK         (0x8000U)
47643 #define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT        (15U)
47644 /*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
47645  *  0b0..Normal Interrupt Summary is disabled
47646  *  0b1..Normal Interrupt Summary is enabled
47647  */
47648 #define ENET_QOS_DMA_CHX_INT_EN_NIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
47649 /*! @} */
47650 
47651 /* The count of ENET_QOS_DMA_CHX_INT_EN */
47652 #define ENET_QOS_DMA_CHX_INT_EN_COUNT            (5U)
47653 
47654 /*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
47655 /*! @{ */
47656 
47657 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
47658 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
47659 /*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
47660  *    cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
47661  */
47662 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
47663 
47664 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
47665 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
47666 /*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
47667  *    clock cycles corresponding to one unit in RWT field.
47668  */
47669 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
47670 /*! @} */
47671 
47672 /* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
47673 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT    (5U)
47674 
47675 /*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
47676 /*! @{ */
47677 
47678 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
47679 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
47680 /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
47681  *    programmed in the Tx descriptor with the current reference given in the RSN field.
47682  *  0b0..Slot Comparison is disabled
47683  *  0b1..Slot Comparison is enabled
47684  */
47685 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
47686 
47687 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
47688 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
47689 /*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
47690  *    when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
47691  *    number given in the RSN field or - ahead of the reference slot number by up to two slots This
47692  *    bit is applicable only when the ESC bit is set.
47693  *  0b0..Advance Slot Check is disabled
47694  *  0b1..Advance Slot Check is enabled
47695  */
47696 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
47697 
47698 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
47699 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
47700 /*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
47701  *    fetches the scheduled packets.
47702  */
47703 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
47704 
47705 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
47706 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
47707 /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
47708  */
47709 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
47710 /*! @} */
47711 
47712 /* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
47713 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
47714 
47715 /*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
47716 /*! @{ */
47717 
47718 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
47719 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
47720 /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation.
47721  */
47722 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
47723 /*! @} */
47724 
47725 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
47726 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT    (5U)
47727 
47728 /*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
47729 /*! @{ */
47730 
47731 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
47732 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
47733 /*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation.
47734  */
47735 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
47736 /*! @} */
47737 
47738 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
47739 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT    (5U)
47740 
47741 /*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
47742 /*! @{ */
47743 
47744 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
47745 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
47746 /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation.
47747  */
47748 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
47749 /*! @} */
47750 
47751 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
47752 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT     (5U)
47753 
47754 /*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
47755 /*! @{ */
47756 
47757 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
47758 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
47759 /*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation.
47760  */
47761 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
47762 /*! @} */
47763 
47764 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
47765 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT     (5U)
47766 
47767 /*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
47768 /*! @{ */
47769 
47770 #define ENET_QOS_DMA_CHX_STAT_TI_MASK            (0x1U)
47771 #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT           (0U)
47772 /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
47773  *  0b1..Transmit Interrupt status detected
47774  *  0b0..Transmit Interrupt status not detected
47775  */
47776 #define ENET_QOS_DMA_CHX_STAT_TI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
47777 
47778 #define ENET_QOS_DMA_CHX_STAT_TPS_MASK           (0x2U)
47779 #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT          (1U)
47780 /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
47781  *  0b1..Transmit Process Stopped status detected
47782  *  0b0..Transmit Process Stopped status not detected
47783  */
47784 #define ENET_QOS_DMA_CHX_STAT_TPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
47785 
47786 #define ENET_QOS_DMA_CHX_STAT_TBU_MASK           (0x4U)
47787 #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT          (2U)
47788 /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
47789  *    descriptor in the Transmit list, and the DMA cannot acquire it.
47790  *  0b1..Transmit Buffer Unavailable status detected
47791  *  0b0..Transmit Buffer Unavailable status not detected
47792  */
47793 #define ENET_QOS_DMA_CHX_STAT_TBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
47794 
47795 #define ENET_QOS_DMA_CHX_STAT_RI_MASK            (0x40U)
47796 #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT           (6U)
47797 /*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
47798  *  0b1..Receive Interrupt status detected
47799  *  0b0..Receive Interrupt status not detected
47800  */
47801 #define ENET_QOS_DMA_CHX_STAT_RI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
47802 
47803 #define ENET_QOS_DMA_CHX_STAT_RBU_MASK           (0x80U)
47804 #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT          (7U)
47805 /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
47806  *    descriptor in the Receive list, and the DMA cannot acquire it.
47807  *  0b1..Receive Buffer Unavailable status detected
47808  *  0b0..Receive Buffer Unavailable status not detected
47809  */
47810 #define ENET_QOS_DMA_CHX_STAT_RBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
47811 
47812 #define ENET_QOS_DMA_CHX_STAT_RPS_MASK           (0x100U)
47813 #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT          (8U)
47814 /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
47815  *  0b1..Receive Process Stopped status detected
47816  *  0b0..Receive Process Stopped status not detected
47817  */
47818 #define ENET_QOS_DMA_CHX_STAT_RPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
47819 
47820 #define ENET_QOS_DMA_CHX_STAT_RWT_MASK           (0x200U)
47821 #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT          (9U)
47822 /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
47823  *    bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
47824  *  0b1..Receive Watchdog Timeout status detected
47825  *  0b0..Receive Watchdog Timeout status not detected
47826  */
47827 #define ENET_QOS_DMA_CHX_STAT_RWT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
47828 
47829 #define ENET_QOS_DMA_CHX_STAT_ETI_MASK           (0x400U)
47830 #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT          (10U)
47831 /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
47832  *    transfer of packet data to the MTL TXFIFO memory.
47833  *  0b1..Early Transmit Interrupt status detected
47834  *  0b0..Early Transmit Interrupt status not detected
47835  */
47836 #define ENET_QOS_DMA_CHX_STAT_ETI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
47837 
47838 #define ENET_QOS_DMA_CHX_STAT_ERI_MASK           (0x800U)
47839 #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT          (11U)
47840 /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
47841  *    transfer of packet data to the memory.
47842  *  0b1..Early Receive Interrupt status detected
47843  *  0b0..Early Receive Interrupt status not detected
47844  */
47845 #define ENET_QOS_DMA_CHX_STAT_ERI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
47846 
47847 #define ENET_QOS_DMA_CHX_STAT_FBE_MASK           (0x1000U)
47848 #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT          (12U)
47849 /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
47850  *  0b1..Fatal Bus Error status detected
47851  *  0b0..Fatal Bus Error status not detected
47852  */
47853 #define ENET_QOS_DMA_CHX_STAT_FBE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
47854 
47855 #define ENET_QOS_DMA_CHX_STAT_CDE_MASK           (0x2000U)
47856 #define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT          (13U)
47857 /*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
47858  *    descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
47859  *    descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
47860  *    with either of the buffer address as ones which is considered to be invalid.
47861  *  0b1..Context Descriptor Error status detected
47862  *  0b0..Context Descriptor Error status not detected
47863  */
47864 #define ENET_QOS_DMA_CHX_STAT_CDE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
47865 
47866 #define ENET_QOS_DMA_CHX_STAT_AIS_MASK           (0x4000U)
47867 #define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT          (14U)
47868 /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
47869  *    following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
47870  *    register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
47871  *    Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
47872  *    Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
47873  *  0b1..Abnormal Interrupt Summary status detected
47874  *  0b0..Abnormal Interrupt Summary status not detected
47875  */
47876 #define ENET_QOS_DMA_CHX_STAT_AIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
47877 
47878 #define ENET_QOS_DMA_CHX_STAT_NIS_MASK           (0x8000U)
47879 #define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT          (15U)
47880 /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
47881  *    following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
47882  *    register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
47883  *    Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
47884  *    enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
47885  *  0b1..Normal Interrupt Summary status detected
47886  *  0b0..Normal Interrupt Summary status not detected
47887  */
47888 #define ENET_QOS_DMA_CHX_STAT_NIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
47889 
47890 #define ENET_QOS_DMA_CHX_STAT_TEB_MASK           (0x70000U)
47891 #define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT          (16U)
47892 /*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error.
47893  */
47894 #define ENET_QOS_DMA_CHX_STAT_TEB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
47895 
47896 #define ENET_QOS_DMA_CHX_STAT_REB_MASK           (0x380000U)
47897 #define ENET_QOS_DMA_CHX_STAT_REB_SHIFT          (19U)
47898 /*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error.
47899  */
47900 #define ENET_QOS_DMA_CHX_STAT_REB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
47901 /*! @} */
47902 
47903 /* The count of ENET_QOS_DMA_CHX_STAT */
47904 #define ENET_QOS_DMA_CHX_STAT_COUNT              (5U)
47905 
47906 /*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
47907 /*! @{ */
47908 
47909 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
47910 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
47911 /*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
47912  *    dropped by the DMA either because of bus error or because of programming RPF field in
47913  *    DMA_CH2_RX_CONTROL register.
47914  */
47915 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
47916 
47917 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
47918 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
47919 /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
47920  *  0b1..Miss Frame Counter overflow occurred
47921  *  0b0..Miss Frame Counter overflow not occurred
47922  */
47923 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
47924 /*! @} */
47925 
47926 /* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
47927 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT    (5U)
47928 
47929 /*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
47930 /*! @{ */
47931 
47932 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
47933 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
47934 /*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1.
47935  */
47936 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
47937 
47938 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
47939 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
47940 /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
47941  *    Counter field crossed the maximum limit.
47942  *  0b1..Rx Parser Accept Counter overflow occurred
47943  *  0b0..Rx Parser Accept Counter overflow not occurred
47944  */
47945 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
47946 /*! @} */
47947 
47948 /* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
47949 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT    (5U)
47950 
47951 /*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
47952 /*! @{ */
47953 
47954 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK    (0xFFFU)
47955 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT   (0U)
47956 /*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
47957  *    for burst transfer completed by the Rx DMA from the start of packet transfer.
47958  */
47959 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
47960 /*! @} */
47961 
47962 /* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
47963 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT        (5U)
47964 
47965 
47966 /*!
47967  * @}
47968  */ /* end of group ENET_QOS_Register_Masks */
47969 
47970 
47971 /* ENET_QOS - Peripheral instance base addresses */
47972 /** Peripheral ENET_QOS base address */
47973 #define ENET_QOS_BASE                            (0x4043C000u)
47974 /** Peripheral ENET_QOS base pointer */
47975 #define ENET_QOS                                 ((ENET_QOS_Type *)ENET_QOS_BASE)
47976 /** Array initializer of ENET_QOS peripheral base addresses */
47977 #define ENET_QOS_BASE_ADDRS                      { ENET_QOS_BASE }
47978 /** Array initializer of ENET_QOS peripheral base pointers */
47979 #define ENET_QOS_BASE_PTRS                       { ENET_QOS }
47980 /** Interrupt vectors for the ENET_QOS peripheral type */
47981 #define ENET_QOS_IRQS                            { ENET_QOS_IRQn }
47982 #define ENET_QOS_PMT_IRQS                        { ENET_QOS_PMT_IRQn }
47983 
47984 /*!
47985  * @}
47986  */ /* end of group ENET_QOS_Peripheral_Access_Layer */
47987 
47988 
47989 /* ----------------------------------------------------------------------------
47990    -- ETHERNET_PLL Peripheral Access Layer
47991    ---------------------------------------------------------------------------- */
47992 
47993 /*!
47994  * @addtogroup ETHERNET_PLL_Peripheral_Access_Layer ETHERNET_PLL Peripheral Access Layer
47995  * @{
47996  */
47997 
47998 /** ETHERNET_PLL - Register Layout Typedef */
47999 typedef struct {
48000   struct {                                         /* offset: 0x0 */
48001     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
48002     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
48003     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
48004     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
48005   } CTRL0;
48006   struct {                                         /* offset: 0x10 */
48007     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
48008     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
48009     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
48010     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
48011   } SPREAD_SPECTRUM;
48012   struct {                                         /* offset: 0x20 */
48013     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
48014     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
48015     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
48016     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
48017   } NUMERATOR;
48018   struct {                                         /* offset: 0x30 */
48019     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
48020     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
48021     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
48022     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
48023   } DENOMINATOR;
48024 } ETHERNET_PLL_Type;
48025 
48026 /* ----------------------------------------------------------------------------
48027    -- ETHERNET_PLL Register Masks
48028    ---------------------------------------------------------------------------- */
48029 
48030 /*!
48031  * @addtogroup ETHERNET_PLL_Register_Masks ETHERNET_PLL Register Masks
48032  * @{
48033  */
48034 
48035 /*! @name CTRL0 - Fractional PLL Control Register */
48036 /*! @{ */
48037 
48038 #define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK       (0x7FU)
48039 #define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT      (0U)
48040 /*! DIV_SELECT - DIV_SELECT
48041  */
48042 #define ETHERNET_PLL_CTRL0_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK)
48043 
48044 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK       (0x100U)
48045 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT      (8U)
48046 /*! ENABLE_ALT - ENABLE_ALT
48047  *  0b0..Disable the alternate clock output
48048  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
48049  */
48050 #define ETHERNET_PLL_CTRL0_ENABLE_ALT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK)
48051 
48052 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK    (0x2000U)
48053 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
48054 /*! HOLD_RING_OFF - PLL Start up initialization
48055  *  0b0..Normal operation
48056  *  0b1..Initialize PLL start up
48057  */
48058 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x)      (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK)
48059 
48060 #define ETHERNET_PLL_CTRL0_POWERUP_MASK          (0x4000U)
48061 #define ETHERNET_PLL_CTRL0_POWERUP_SHIFT         (14U)
48062 /*! POWERUP - POWERUP
48063  *  0b1..Power Up the PLL
48064  *  0b0..Power down the PLL
48065  */
48066 #define ETHERNET_PLL_CTRL0_POWERUP(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK)
48067 
48068 #define ETHERNET_PLL_CTRL0_ENABLE_MASK           (0x8000U)
48069 #define ETHERNET_PLL_CTRL0_ENABLE_SHIFT          (15U)
48070 /*! ENABLE - ENABLE
48071  *  0b1..Enable the clock output
48072  *  0b0..Disable the clock output
48073  */
48074 #define ETHERNET_PLL_CTRL0_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK)
48075 
48076 #define ETHERNET_PLL_CTRL0_BYPASS_MASK           (0x10000U)
48077 #define ETHERNET_PLL_CTRL0_BYPASS_SHIFT          (16U)
48078 /*! BYPASS - BYPASS
48079  *  0b1..Bypass the PLL
48080  *  0b0..No Bypass
48081  */
48082 #define ETHERNET_PLL_CTRL0_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK)
48083 
48084 #define ETHERNET_PLL_CTRL0_DITHER_EN_MASK        (0x20000U)
48085 #define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT       (17U)
48086 /*! DITHER_EN - DITHER_EN
48087  *  0b0..Disable Dither
48088  *  0b1..Enable Dither
48089  */
48090 #define ETHERNET_PLL_CTRL0_DITHER_EN(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK)
48091 
48092 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK        (0x380000U)
48093 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT       (19U)
48094 /*! BIAS_TRIM - BIAS_TRIM
48095  */
48096 #define ETHERNET_PLL_CTRL0_BIAS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK)
48097 
48098 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK       (0x400000U)
48099 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT      (22U)
48100 /*! PLL_REG_EN - PLL_REG_EN
48101  */
48102 #define ETHERNET_PLL_CTRL0_PLL_REG_EN(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK)
48103 
48104 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK     (0xE000000U)
48105 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT    (25U)
48106 /*! POST_DIV_SEL - Post Divide Select
48107  *  0b000..Divide by 1
48108  *  0b001..Divide by 2
48109  *  0b010..Divide by 4
48110  *  0b011..Divide by 8
48111  *  0b100..Divide by 16
48112  *  0b101..Divide by 32
48113  */
48114 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK)
48115 
48116 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK      (0x20000000U)
48117 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT     (29U)
48118 /*! BIAS_SELECT - BIAS_SELECT
48119  *  0b0..Used in SoCs with a bias current of 10uA
48120  *  0b1..Used in SoCs with a bias current of 2uA
48121  */
48122 #define ETHERNET_PLL_CTRL0_BIAS_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK)
48123 /*! @} */
48124 
48125 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
48126 /*! @{ */
48127 
48128 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
48129 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT  (0U)
48130 /*! STEP - Step
48131  */
48132 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK)
48133 
48134 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
48135 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
48136 /*! ENABLE - Enable
48137  */
48138 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
48139 
48140 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
48141 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT  (16U)
48142 /*! STOP - Stop
48143  */
48144 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK)
48145 /*! @} */
48146 
48147 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
48148 /*! @{ */
48149 
48150 #define ETHERNET_PLL_NUMERATOR_NUM_MASK          (0x3FFFFFFFU)
48151 #define ETHERNET_PLL_NUMERATOR_NUM_SHIFT         (0U)
48152 /*! NUM - Numerator
48153  */
48154 #define ETHERNET_PLL_NUMERATOR_NUM(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK)
48155 /*! @} */
48156 
48157 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
48158 /*! @{ */
48159 
48160 #define ETHERNET_PLL_DENOMINATOR_DENOM_MASK      (0x3FFFFFFFU)
48161 #define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT     (0U)
48162 /*! DENOM - Denominator
48163  */
48164 #define ETHERNET_PLL_DENOMINATOR_DENOM(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK)
48165 /*! @} */
48166 
48167 
48168 /*!
48169  * @}
48170  */ /* end of group ETHERNET_PLL_Register_Masks */
48171 
48172 
48173 /* ETHERNET_PLL - Peripheral instance base addresses */
48174 /** Peripheral ETHERNET_PLL base address */
48175 #define ETHERNET_PLL_BASE                        (0u)
48176 /** Peripheral ETHERNET_PLL base pointer */
48177 #define ETHERNET_PLL                             ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
48178 /** Array initializer of ETHERNET_PLL peripheral base addresses */
48179 #define ETHERNET_PLL_BASE_ADDRS                  { ETHERNET_PLL_BASE }
48180 /** Array initializer of ETHERNET_PLL peripheral base pointers */
48181 #define ETHERNET_PLL_BASE_PTRS                   { ETHERNET_PLL }
48182 
48183 /*!
48184  * @}
48185  */ /* end of group ETHERNET_PLL_Peripheral_Access_Layer */
48186 
48187 
48188 /* ----------------------------------------------------------------------------
48189    -- EWM Peripheral Access Layer
48190    ---------------------------------------------------------------------------- */
48191 
48192 /*!
48193  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
48194  * @{
48195  */
48196 
48197 /** EWM - Register Layout Typedef */
48198 typedef struct {
48199   __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
48200   __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
48201   __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
48202   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
48203   __IO uint8_t CLKCTRL;                            /**< Clock Control Register, offset: 0x4 */
48204   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
48205 } EWM_Type;
48206 
48207 /* ----------------------------------------------------------------------------
48208    -- EWM Register Masks
48209    ---------------------------------------------------------------------------- */
48210 
48211 /*!
48212  * @addtogroup EWM_Register_Masks EWM Register Masks
48213  * @{
48214  */
48215 
48216 /*! @name CTRL - Control Register */
48217 /*! @{ */
48218 
48219 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
48220 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
48221 /*! EWMEN - EWM enable.
48222  *  0b0..EWM module is disabled.
48223  *  0b1..EWM module is enabled.
48224  */
48225 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
48226 
48227 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
48228 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
48229 /*! ASSIN - EWM_in's Assertion State Select.
48230  *  0b0..Default assert state of the EWM_in signal.
48231  *  0b1..Inverts the assert state of EWM_in signal.
48232  */
48233 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
48234 
48235 #define EWM_CTRL_INEN_MASK                       (0x4U)
48236 #define EWM_CTRL_INEN_SHIFT                      (2U)
48237 /*! INEN - Input Enable.
48238  *  0b0..EWM_in port is disabled.
48239  *  0b1..EWM_in port is enabled.
48240  */
48241 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
48242 
48243 #define EWM_CTRL_INTEN_MASK                      (0x8U)
48244 #define EWM_CTRL_INTEN_SHIFT                     (3U)
48245 /*! INTEN - Interrupt Enable.
48246  *  0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
48247  *  0b0..Deasserts the interrupt request.
48248  */
48249 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
48250 /*! @} */
48251 
48252 /*! @name SERV - Service Register */
48253 /*! @{ */
48254 
48255 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
48256 #define EWM_SERV_SERVICE_SHIFT                   (0U)
48257 /*! SERVICE - SERVICE
48258  */
48259 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
48260 /*! @} */
48261 
48262 /*! @name CMPL - Compare Low Register */
48263 /*! @{ */
48264 
48265 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
48266 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
48267 /*! COMPAREL - COMPAREL
48268  */
48269 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
48270 /*! @} */
48271 
48272 /*! @name CMPH - Compare High Register */
48273 /*! @{ */
48274 
48275 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
48276 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
48277 /*! COMPAREH - COMPAREH
48278  */
48279 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
48280 /*! @} */
48281 
48282 /*! @name CLKCTRL - Clock Control Register */
48283 /*! @{ */
48284 
48285 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
48286 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
48287 /*! CLKSEL - CLKSEL
48288  */
48289 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
48290 /*! @} */
48291 
48292 /*! @name CLKPRESCALER - Clock Prescaler Register */
48293 /*! @{ */
48294 
48295 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
48296 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
48297 /*! CLK_DIV - CLK_DIV
48298  */
48299 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
48300 /*! @} */
48301 
48302 
48303 /*!
48304  * @}
48305  */ /* end of group EWM_Register_Masks */
48306 
48307 
48308 /* EWM - Peripheral instance base addresses */
48309 /** Peripheral EWM base address */
48310 #define EWM_BASE                                 (0x4002C000u)
48311 /** Peripheral EWM base pointer */
48312 #define EWM                                      ((EWM_Type *)EWM_BASE)
48313 /** Array initializer of EWM peripheral base addresses */
48314 #define EWM_BASE_ADDRS                           { EWM_BASE }
48315 /** Array initializer of EWM peripheral base pointers */
48316 #define EWM_BASE_PTRS                            { EWM }
48317 /** Interrupt vectors for the EWM peripheral type */
48318 #define EWM_IRQS                                 { EWM_IRQn }
48319 
48320 /*!
48321  * @}
48322  */ /* end of group EWM_Peripheral_Access_Layer */
48323 
48324 
48325 /* ----------------------------------------------------------------------------
48326    -- FLEXIO Peripheral Access Layer
48327    ---------------------------------------------------------------------------- */
48328 
48329 /*!
48330  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
48331  * @{
48332  */
48333 
48334 /** FLEXIO - Register Layout Typedef */
48335 typedef struct {
48336   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
48337   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
48338   __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
48339   __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
48340   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
48341   __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
48342   __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
48343        uint8_t RESERVED_0[4];
48344   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
48345   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
48346   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
48347        uint8_t RESERVED_1[4];
48348   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
48349        uint8_t RESERVED_2[4];
48350   __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
48351        uint8_t RESERVED_3[4];
48352   __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
48353        uint8_t RESERVED_4[60];
48354   __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
48355        uint8_t RESERVED_5[96];
48356   __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
48357        uint8_t RESERVED_6[224];
48358   __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
48359        uint8_t RESERVED_7[96];
48360   __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
48361        uint8_t RESERVED_8[96];
48362   __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
48363        uint8_t RESERVED_9[96];
48364   __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
48365        uint8_t RESERVED_10[96];
48366   __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
48367        uint8_t RESERVED_11[96];
48368   __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
48369        uint8_t RESERVED_12[96];
48370   __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
48371        uint8_t RESERVED_13[352];
48372   __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
48373        uint8_t RESERVED_14[96];
48374   __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
48375        uint8_t RESERVED_15[96];
48376   __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
48377        uint8_t RESERVED_16[96];
48378   __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
48379        uint8_t RESERVED_17[96];
48380   __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
48381 } FLEXIO_Type;
48382 
48383 /* ----------------------------------------------------------------------------
48384    -- FLEXIO Register Masks
48385    ---------------------------------------------------------------------------- */
48386 
48387 /*!
48388  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
48389  * @{
48390  */
48391 
48392 /*! @name VERID - Version ID Register */
48393 /*! @{ */
48394 
48395 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
48396 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
48397 /*! FEATURE - Feature Specification Number
48398  *  0b0000000000000000..Standard features implemented.
48399  *  0b0000000000000001..Supports state, logic and parallel modes.
48400  *  0b0000000000000010..Supports pin control registers.
48401  *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
48402  */
48403 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
48404 
48405 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
48406 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
48407 /*! MINOR - Minor Version Number
48408  */
48409 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
48410 
48411 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
48412 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
48413 /*! MAJOR - Major Version Number
48414  */
48415 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
48416 /*! @} */
48417 
48418 /*! @name PARAM - Parameter Register */
48419 /*! @{ */
48420 
48421 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
48422 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
48423 /*! SHIFTER - Shifter Number
48424  */
48425 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
48426 
48427 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
48428 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
48429 /*! TIMER - Timer Number
48430  */
48431 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
48432 
48433 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
48434 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
48435 /*! PIN - Pin Number
48436  */
48437 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
48438 
48439 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
48440 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
48441 /*! TRIGGER - Trigger Number
48442  */
48443 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
48444 /*! @} */
48445 
48446 /*! @name CTRL - FlexIO Control Register */
48447 /*! @{ */
48448 
48449 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
48450 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
48451 /*! FLEXEN - FlexIO Enable
48452  *  0b0..FlexIO module is disabled.
48453  *  0b1..FlexIO module is enabled.
48454  */
48455 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
48456 
48457 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
48458 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
48459 /*! SWRST - Software Reset
48460  *  0b0..Software reset is disabled
48461  *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
48462  */
48463 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
48464 
48465 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
48466 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
48467 /*! FASTACC - Fast Access
48468  *  0b0..Configures for normal register accesses to FlexIO
48469  *  0b1..Configures for fast register accesses to FlexIO
48470  */
48471 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
48472 
48473 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
48474 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
48475 /*! DBGE - Debug Enable
48476  *  0b0..FlexIO is disabled in debug modes.
48477  *  0b1..FlexIO is enabled in debug modes
48478  */
48479 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
48480 
48481 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
48482 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
48483 /*! DOZEN - Doze Enable
48484  *  0b0..FlexIO enabled in Doze modes.
48485  *  0b1..FlexIO disabled in Doze modes.
48486  */
48487 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
48488 /*! @} */
48489 
48490 /*! @name PIN - Pin State Register */
48491 /*! @{ */
48492 
48493 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
48494 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
48495 /*! PDI - Pin Data Input
48496  */
48497 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
48498 /*! @} */
48499 
48500 /*! @name SHIFTSTAT - Shifter Status Register */
48501 /*! @{ */
48502 
48503 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
48504 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
48505 /*! SSF - Shifter Status Flag
48506  */
48507 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
48508 /*! @} */
48509 
48510 /*! @name SHIFTERR - Shifter Error Register */
48511 /*! @{ */
48512 
48513 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
48514 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
48515 /*! SEF - Shifter Error Flags
48516  */
48517 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
48518 /*! @} */
48519 
48520 /*! @name TIMSTAT - Timer Status Register */
48521 /*! @{ */
48522 
48523 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
48524 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
48525 /*! TSF - Timer Status Flags
48526  */
48527 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
48528 /*! @} */
48529 
48530 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
48531 /*! @{ */
48532 
48533 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
48534 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
48535 /*! SSIE - Shifter Status Interrupt Enable
48536  */
48537 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
48538 /*! @} */
48539 
48540 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
48541 /*! @{ */
48542 
48543 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
48544 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
48545 /*! SEIE - Shifter Error Interrupt Enable
48546  */
48547 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
48548 /*! @} */
48549 
48550 /*! @name TIMIEN - Timer Interrupt Enable Register */
48551 /*! @{ */
48552 
48553 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
48554 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
48555 /*! TEIE - Timer Status Interrupt Enable
48556  */
48557 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
48558 /*! @} */
48559 
48560 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
48561 /*! @{ */
48562 
48563 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
48564 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
48565 /*! SSDE - Shifter Status DMA Enable
48566  */
48567 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
48568 /*! @} */
48569 
48570 /*! @name TIMERSDEN - Timer Status DMA Enable */
48571 /*! @{ */
48572 
48573 #define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
48574 #define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
48575 /*! TSDE - Timer Status DMA Enable
48576  */
48577 #define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
48578 /*! @} */
48579 
48580 /*! @name SHIFTSTATE - Shifter State Register */
48581 /*! @{ */
48582 
48583 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
48584 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
48585 /*! STATE - Current State Pointer
48586  */
48587 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
48588 /*! @} */
48589 
48590 /*! @name SHIFTCTL - Shifter Control N Register */
48591 /*! @{ */
48592 
48593 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
48594 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
48595 /*! SMOD - Shifter Mode
48596  *  0b000..Disabled.
48597  *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
48598  *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
48599  *  0b011..Reserved.
48600  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
48601  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
48602  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
48603  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
48604  */
48605 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
48606 
48607 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
48608 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
48609 /*! PINPOL - Shifter Pin Polarity
48610  *  0b0..Pin is active high
48611  *  0b1..Pin is active low
48612  */
48613 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
48614 
48615 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
48616 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
48617 /*! PINSEL - Shifter Pin Select
48618  */
48619 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
48620 
48621 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
48622 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
48623 /*! PINCFG - Shifter Pin Configuration
48624  *  0b00..Shifter pin output disabled
48625  *  0b01..Shifter pin open drain or bidirectional output enable
48626  *  0b10..Shifter pin bidirectional output data
48627  *  0b11..Shifter pin output
48628  */
48629 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
48630 
48631 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
48632 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
48633 /*! TIMPOL - Timer Polarity
48634  *  0b0..Shift on posedge of Shift clock
48635  *  0b1..Shift on negedge of Shift clock
48636  */
48637 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
48638 
48639 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
48640 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
48641 /*! TIMSEL - Timer Select
48642  */
48643 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
48644 /*! @} */
48645 
48646 /* The count of FLEXIO_SHIFTCTL */
48647 #define FLEXIO_SHIFTCTL_COUNT                    (8U)
48648 
48649 /*! @name SHIFTCFG - Shifter Configuration N Register */
48650 /*! @{ */
48651 
48652 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
48653 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
48654 /*! SSTART - Shifter Start bit
48655  *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
48656  *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
48657  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
48658  *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
48659  */
48660 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
48661 
48662 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
48663 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
48664 /*! SSTOP - Shifter Stop bit
48665  *  0b00..Stop bit disabled for transmitter/receiver/match store
48666  *  0b01..Reserved for transmitter/receiver/match store
48667  *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
48668  *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
48669  */
48670 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
48671 
48672 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
48673 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
48674 /*! INSRC - Input Source
48675  *  0b0..Pin
48676  *  0b1..Shifter N+1 Output
48677  */
48678 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
48679 
48680 #define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
48681 #define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
48682 /*! LATST - Late Store
48683  *  0b0..Shift register stores the pre-shift register state.
48684  *  0b1..Shift register stores the post-shift register state.
48685  */
48686 #define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
48687 
48688 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
48689 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
48690 /*! PWIDTH - Parallel Width
48691  */
48692 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
48693 /*! @} */
48694 
48695 /* The count of FLEXIO_SHIFTCFG */
48696 #define FLEXIO_SHIFTCFG_COUNT                    (8U)
48697 
48698 /*! @name SHIFTBUF - Shifter Buffer N Register */
48699 /*! @{ */
48700 
48701 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
48702 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
48703 /*! SHIFTBUF - Shift Buffer
48704  */
48705 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
48706 /*! @} */
48707 
48708 /* The count of FLEXIO_SHIFTBUF */
48709 #define FLEXIO_SHIFTBUF_COUNT                    (8U)
48710 
48711 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
48712 /*! @{ */
48713 
48714 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
48715 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
48716 /*! SHIFTBUFBIS - Shift Buffer
48717  */
48718 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
48719 /*! @} */
48720 
48721 /* The count of FLEXIO_SHIFTBUFBIS */
48722 #define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
48723 
48724 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
48725 /*! @{ */
48726 
48727 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
48728 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
48729 /*! SHIFTBUFBYS - Shift Buffer
48730  */
48731 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
48732 /*! @} */
48733 
48734 /* The count of FLEXIO_SHIFTBUFBYS */
48735 #define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
48736 
48737 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
48738 /*! @{ */
48739 
48740 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
48741 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
48742 /*! SHIFTBUFBBS - Shift Buffer
48743  */
48744 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
48745 /*! @} */
48746 
48747 /* The count of FLEXIO_SHIFTBUFBBS */
48748 #define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
48749 
48750 /*! @name TIMCTL - Timer Control N Register */
48751 /*! @{ */
48752 
48753 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
48754 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
48755 /*! TIMOD - Timer Mode
48756  *  0b000..Timer Disabled.
48757  *  0b001..Dual 8-bit counters baud mode.
48758  *  0b010..Dual 8-bit counters PWM high mode.
48759  *  0b011..Single 16-bit counter mode.
48760  *  0b100..Single 16-bit counter disable mode.
48761  *  0b101..Dual 8-bit counters word mode.
48762  *  0b110..Dual 8-bit counters PWM low mode.
48763  *  0b111..Single 16-bit input capture mode.
48764  */
48765 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
48766 
48767 #define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
48768 #define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
48769 /*! ONETIM - Timer One Time Operation
48770  *  0b0..The timer enable event is generated as normal.
48771  *  0b1..The timer enable event is blocked unless timer status flag is clear.
48772  */
48773 #define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
48774 
48775 #define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
48776 #define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
48777 /*! PININS - Timer Pin Input Select
48778  *  0b0..Timer pin input and output are selected by PINSEL.
48779  *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
48780  */
48781 #define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
48782 
48783 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
48784 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
48785 /*! PINPOL - Timer Pin Polarity
48786  *  0b0..Pin is active high
48787  *  0b1..Pin is active low
48788  */
48789 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
48790 
48791 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
48792 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
48793 /*! PINSEL - Timer Pin Select
48794  */
48795 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
48796 
48797 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
48798 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
48799 /*! PINCFG - Timer Pin Configuration
48800  *  0b00..Timer pin output disabled
48801  *  0b01..Timer pin open drain or bidirectional output enable
48802  *  0b10..Timer pin bidirectional output data
48803  *  0b11..Timer pin output
48804  */
48805 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
48806 
48807 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
48808 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
48809 /*! TRGSRC - Trigger Source
48810  *  0b0..External trigger selected
48811  *  0b1..Internal trigger selected
48812  */
48813 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
48814 
48815 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
48816 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
48817 /*! TRGPOL - Trigger Polarity
48818  *  0b0..Trigger active high
48819  *  0b1..Trigger active low
48820  */
48821 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
48822 
48823 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
48824 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
48825 /*! TRGSEL - Trigger Select
48826  */
48827 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
48828 /*! @} */
48829 
48830 /* The count of FLEXIO_TIMCTL */
48831 #define FLEXIO_TIMCTL_COUNT                      (8U)
48832 
48833 /*! @name TIMCFG - Timer Configuration N Register */
48834 /*! @{ */
48835 
48836 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
48837 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
48838 /*! TSTART - Timer Start Bit
48839  *  0b0..Start bit disabled
48840  *  0b1..Start bit enabled
48841  */
48842 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
48843 
48844 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
48845 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
48846 /*! TSTOP - Timer Stop Bit
48847  *  0b00..Stop bit disabled
48848  *  0b01..Stop bit is enabled on timer compare
48849  *  0b10..Stop bit is enabled on timer disable
48850  *  0b11..Stop bit is enabled on timer compare and timer disable
48851  */
48852 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
48853 
48854 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
48855 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
48856 /*! TIMENA - Timer Enable
48857  *  0b000..Timer always enabled
48858  *  0b001..Timer enabled on Timer N-1 enable
48859  *  0b010..Timer enabled on Trigger high
48860  *  0b011..Timer enabled on Trigger high and Pin high
48861  *  0b100..Timer enabled on Pin rising edge
48862  *  0b101..Timer enabled on Pin rising edge and Trigger high
48863  *  0b110..Timer enabled on Trigger rising edge
48864  *  0b111..Timer enabled on Trigger rising or falling edge
48865  */
48866 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
48867 
48868 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
48869 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
48870 /*! TIMDIS - Timer Disable
48871  *  0b000..Timer never disabled
48872  *  0b001..Timer disabled on Timer N-1 disable
48873  *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
48874  *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
48875  *  0b100..Timer disabled on Pin rising or falling edge
48876  *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
48877  *  0b110..Timer disabled on Trigger falling edge
48878  *  0b111..Reserved
48879  */
48880 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
48881 
48882 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
48883 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
48884 /*! TIMRST - Timer Reset
48885  *  0b000..Timer never reset
48886  *  0b001..Timer reset on Timer Output high.
48887  *  0b010..Timer reset on Timer Pin equal to Timer Output
48888  *  0b011..Timer reset on Timer Trigger equal to Timer Output
48889  *  0b100..Timer reset on Timer Pin rising edge
48890  *  0b101..Reserved
48891  *  0b110..Timer reset on Trigger rising edge
48892  *  0b111..Timer reset on Trigger rising or falling edge
48893  */
48894 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
48895 
48896 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
48897 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
48898 /*! TIMDEC - Timer Decrement
48899  *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
48900  *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
48901  *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
48902  *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
48903  *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
48904  *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
48905  *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
48906  *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
48907  */
48908 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
48909 
48910 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
48911 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
48912 /*! TIMOUT - Timer Output
48913  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
48914  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
48915  *  0b10..Timer output is logic one when enabled and on timer reset
48916  *  0b11..Timer output is logic zero when enabled and on timer reset
48917  */
48918 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
48919 /*! @} */
48920 
48921 /* The count of FLEXIO_TIMCFG */
48922 #define FLEXIO_TIMCFG_COUNT                      (8U)
48923 
48924 /*! @name TIMCMP - Timer Compare N Register */
48925 /*! @{ */
48926 
48927 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
48928 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
48929 /*! CMP - Timer Compare Value
48930  */
48931 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
48932 /*! @} */
48933 
48934 /* The count of FLEXIO_TIMCMP */
48935 #define FLEXIO_TIMCMP_COUNT                      (8U)
48936 
48937 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
48938 /*! @{ */
48939 
48940 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
48941 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
48942 /*! SHIFTBUFNBS - Shift Buffer
48943  */
48944 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
48945 /*! @} */
48946 
48947 /* The count of FLEXIO_SHIFTBUFNBS */
48948 #define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
48949 
48950 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
48951 /*! @{ */
48952 
48953 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
48954 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
48955 /*! SHIFTBUFHWS - Shift Buffer
48956  */
48957 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
48958 /*! @} */
48959 
48960 /* The count of FLEXIO_SHIFTBUFHWS */
48961 #define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
48962 
48963 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
48964 /*! @{ */
48965 
48966 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
48967 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
48968 /*! SHIFTBUFNIS - Shift Buffer
48969  */
48970 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
48971 /*! @} */
48972 
48973 /* The count of FLEXIO_SHIFTBUFNIS */
48974 #define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
48975 
48976 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
48977 /*! @{ */
48978 
48979 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
48980 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
48981 /*! SHIFTBUFOES - Shift Buffer
48982  */
48983 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
48984 /*! @} */
48985 
48986 /* The count of FLEXIO_SHIFTBUFOES */
48987 #define FLEXIO_SHIFTBUFOES_COUNT                 (8U)
48988 
48989 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
48990 /*! @{ */
48991 
48992 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
48993 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
48994 /*! SHIFTBUFEOS - Shift Buffer
48995  */
48996 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
48997 /*! @} */
48998 
48999 /* The count of FLEXIO_SHIFTBUFEOS */
49000 #define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)
49001 
49002 
49003 /*!
49004  * @}
49005  */ /* end of group FLEXIO_Register_Masks */
49006 
49007 
49008 /* FLEXIO - Peripheral instance base addresses */
49009 /** Peripheral FLEXIO1 base address */
49010 #define FLEXIO1_BASE                             (0x400AC000u)
49011 /** Peripheral FLEXIO1 base pointer */
49012 #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
49013 /** Peripheral FLEXIO2 base address */
49014 #define FLEXIO2_BASE                             (0x400B0000u)
49015 /** Peripheral FLEXIO2 base pointer */
49016 #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
49017 /** Array initializer of FLEXIO peripheral base addresses */
49018 #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
49019 /** Array initializer of FLEXIO peripheral base pointers */
49020 #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
49021 /** Interrupt vectors for the FLEXIO peripheral type */
49022 #define FLEXIO_IRQS                              { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
49023 
49024 /*!
49025  * @}
49026  */ /* end of group FLEXIO_Peripheral_Access_Layer */
49027 
49028 
49029 /* ----------------------------------------------------------------------------
49030    -- FLEXRAM Peripheral Access Layer
49031    ---------------------------------------------------------------------------- */
49032 
49033 /*!
49034  * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
49035  * @{
49036  */
49037 
49038 /** FLEXRAM - Register Layout Typedef */
49039 typedef struct {
49040   __IO uint32_t TCM_CTRL;                          /**< TCM CRTL Register, offset: 0x0 */
49041   __IO uint32_t OCRAM_MAGIC_ADDR;                  /**< OCRAM Magic Address Register, offset: 0x4 */
49042   __IO uint32_t DTCM_MAGIC_ADDR;                   /**< DTCM Magic Address Register, offset: 0x8 */
49043   __IO uint32_t ITCM_MAGIC_ADDR;                   /**< ITCM Magic Address Register, offset: 0xC */
49044   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x10 */
49045   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable Register, offset: 0x14 */
49046   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable Register, offset: 0x18 */
49047   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_INFO;       /**< OCRAM single-bit ECC Error Information Register, offset: 0x1C */
49048   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR;       /**< OCRAM single-bit ECC Error Address Register, offset: 0x20 */
49049   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x24 */
49050   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x28 */
49051   __I  uint32_t OCRAM_ECC_MULTI_ERROR_INFO;        /**< OCRAM multi-bit ECC Error Information Register, offset: 0x2C */
49052   __I  uint32_t OCRAM_ECC_MULTI_ERROR_ADDR;        /**< OCRAM multi-bit ECC Error Address Register, offset: 0x30 */
49053   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_LSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x34 */
49054   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_MSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x38 */
49055   __I  uint32_t ITCM_ECC_SINGLE_ERROR_INFO;        /**< ITCM single-bit ECC Error Information Register, offset: 0x3C */
49056   __I  uint32_t ITCM_ECC_SINGLE_ERROR_ADDR;        /**< ITCM single-bit ECC Error Address Register, offset: 0x40 */
49057   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x44 */
49058   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x48 */
49059   __I  uint32_t ITCM_ECC_MULTI_ERROR_INFO;         /**< ITCM multi-bit ECC Error Information Register, offset: 0x4C */
49060   __I  uint32_t ITCM_ECC_MULTI_ERROR_ADDR;         /**< ITCM multi-bit ECC Error Address Register, offset: 0x50 */
49061   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x54 */
49062   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x58 */
49063   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_INFO;       /**< D0TCM single-bit ECC Error Information Register, offset: 0x5C */
49064   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR;       /**< D0TCM single-bit ECC Error Address Register, offset: 0x60 */
49065   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_DATA;       /**< D0TCM single-bit ECC Error Data Register, offset: 0x64 */
49066   __I  uint32_t D0TCM_ECC_MULTI_ERROR_INFO;        /**< D0TCM multi-bit ECC Error Information Register, offset: 0x68 */
49067   __I  uint32_t D0TCM_ECC_MULTI_ERROR_ADDR;        /**< D0TCM multi-bit ECC Error Address Register, offset: 0x6C */
49068   __I  uint32_t D0TCM_ECC_MULTI_ERROR_DATA;        /**< D0TCM multi-bit ECC Error Data Register, offset: 0x70 */
49069   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_INFO;       /**< D1TCM single-bit ECC Error Information Register, offset: 0x74 */
49070   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR;       /**< D1TCM single-bit ECC Error Address Register, offset: 0x78 */
49071   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_DATA;       /**< D1TCM single-bit ECC Error Data Register, offset: 0x7C */
49072   __I  uint32_t D1TCM_ECC_MULTI_ERROR_INFO;        /**< D1TCM multi-bit ECC Error Information Register, offset: 0x80 */
49073   __I  uint32_t D1TCM_ECC_MULTI_ERROR_ADDR;        /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */
49074   __I  uint32_t D1TCM_ECC_MULTI_ERROR_DATA;        /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */
49075        uint8_t RESERVED_0[124];
49076   __IO uint32_t FLEXRAM_CTRL;                      /**< FlexRAM feature Control register, offset: 0x108 */
49077   __I  uint32_t OCRAM_PIPELINE_STATUS;             /**< OCRAM Pipeline Status register, offset: 0x10C */
49078 } FLEXRAM_Type;
49079 
49080 /* ----------------------------------------------------------------------------
49081    -- FLEXRAM Register Masks
49082    ---------------------------------------------------------------------------- */
49083 
49084 /*!
49085  * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
49086  * @{
49087  */
49088 
49089 /*! @name TCM_CTRL - TCM CRTL Register */
49090 /*! @{ */
49091 
49092 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK       (0x1U)
49093 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT      (0U)
49094 /*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
49095  *  0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
49096  *  0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
49097  */
49098 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
49099 
49100 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK       (0x2U)
49101 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT      (1U)
49102 /*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
49103  *  0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
49104  *  0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
49105  */
49106 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
49107 
49108 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK       (0x4U)
49109 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT      (2U)
49110 /*! FORCE_CLK_ON - Force RAM Clock Always On
49111  */
49112 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
49113 
49114 #define FLEXRAM_TCM_CTRL_Reserved_MASK           (0xFFFFFFF8U)
49115 #define FLEXRAM_TCM_CTRL_Reserved_SHIFT          (3U)
49116 /*! Reserved - Reserved
49117  */
49118 #define FLEXRAM_TCM_CTRL_Reserved(x)             (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
49119 /*! @} */
49120 
49121 /*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
49122 /*! @{ */
49123 
49124 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
49125 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
49126 /*! OCRAM_WR_RD_SEL - OCRAM Write Read Select
49127  *  0b0..When OCRAM read access hits magic address, it will generate interrupt.
49128  *  0b1..When OCRAM write access hits magic address, it will generate interrupt.
49129  */
49130 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
49131 
49132 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU)
49133 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
49134 /*! OCRAM_MAGIC_ADDR - OCRAM Magic Address
49135  */
49136 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
49137 
49138 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK   (0xFFFC0000U)
49139 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT  (18U)
49140 /*! Reserved - Reserved
49141  */
49142 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
49143 /*! @} */
49144 
49145 /*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
49146 /*! @{ */
49147 
49148 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
49149 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
49150 /*! DTCM_WR_RD_SEL - DTCM Write Read Select
49151  *  0b0..When DTCM read access hits magic address, it will generate interrupt.
49152  *  0b1..When DTCM write access hits magic address, it will generate interrupt.
49153  */
49154 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
49155 
49156 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
49157 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
49158 /*! DTCM_MAGIC_ADDR - DTCM Magic Address
49159  */
49160 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
49161 
49162 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
49163 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
49164 /*! Reserved - Reserved
49165  */
49166 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
49167 /*! @} */
49168 
49169 /*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
49170 /*! @{ */
49171 
49172 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
49173 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
49174 /*! ITCM_WR_RD_SEL - ITCM Write Read Select
49175  *  0b0..When ITCM read access hits magic address, it will generate interrupt.
49176  *  0b1..When ITCM write access hits magic address, it will generate interrupt.
49177  */
49178 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
49179 
49180 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
49181 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
49182 /*! ITCM_MAGIC_ADDR - ITCM Magic Address
49183  */
49184 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
49185 
49186 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
49187 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
49188 /*! Reserved - Reserved
49189  */
49190 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
49191 /*! @} */
49192 
49193 /*! @name INT_STATUS - Interrupt Status Register */
49194 /*! @{ */
49195 
49196 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK  (0x1U)
49197 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
49198 /*! ITCM_MAM_STATUS - ITCM Magic Address Match Status
49199  *  0b0..ITCM did not access magic address.
49200  *  0b1..ITCM accessed magic address.
49201  */
49202 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
49203 
49204 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK  (0x2U)
49205 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
49206 /*! DTCM_MAM_STATUS - DTCM Magic Address Match Status
49207  *  0b0..DTCM did not access magic address.
49208  *  0b1..DTCM accessed magic address.
49209  */
49210 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
49211 
49212 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
49213 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
49214 /*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status
49215  *  0b0..OCRAM did not access magic address.
49216  *  0b1..OCRAM accessed magic address.
49217  */
49218 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
49219 
49220 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK  (0x8U)
49221 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
49222 /*! ITCM_ERR_STATUS - ITCM Access Error Status
49223  *  0b0..ITCM access error does not happen
49224  *  0b1..ITCM access error happens.
49225  */
49226 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
49227 
49228 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK  (0x10U)
49229 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
49230 /*! DTCM_ERR_STATUS - DTCM Access Error Status
49231  *  0b0..DTCM access error does not happen
49232  *  0b1..DTCM access error happens.
49233  */
49234 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
49235 
49236 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
49237 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
49238 /*! OCRAM_ERR_STATUS - OCRAM Access Error Status
49239  *  0b0..OCRAM access error does not happen
49240  *  0b1..OCRAM access error happens.
49241  */
49242 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
49243 
49244 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U)
49245 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U)
49246 /*! OCRAM_ECC_ERRM_INT - OCRAM access multi-bit ECC Error Interrupt Status
49247  *  0b0..OCRAM multi-bit ECC error does not happen
49248  *  0b1..OCRAM multi-bit ECC error happens.
49249  */
49250 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK)
49251 
49252 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U)
49253 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U)
49254 /*! OCRAM_ECC_ERRS_INT - OCRAM access single-bit ECC Error Interrupt Status
49255  *  0b0..OCRAM single-bit ECC error does not happen
49256  *  0b1..OCRAM single-bit ECC error happens.
49257  */
49258 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK)
49259 
49260 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U)
49261 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U)
49262 /*! ITCM_ECC_ERRM_INT - ITCM Access multi-bit ECC Error Interrupt Status
49263  *  0b0..ITCM multi-bit ECC error does not happen
49264  *  0b1..ITCM multi-bit ECC error happens.
49265  */
49266 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK)
49267 
49268 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U)
49269 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U)
49270 /*! ITCM_ECC_ERRS_INT - ITCM access single-bit ECC Error Interrupt Status
49271  *  0b0..ITCM single-bit ECC error does not happen
49272  *  0b1..ITCM single-bit ECC error happens.
49273  */
49274 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK)
49275 
49276 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U)
49277 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U)
49278 /*! D0TCM_ECC_ERRM_INT - D0TCM access multi-bit ECC Error Interrupt Status
49279  *  0b0..D0TCM multi-bit ECC error does not happen
49280  *  0b1..D0TCM multi-bit ECC error happens.
49281  */
49282 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK)
49283 
49284 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U)
49285 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U)
49286 /*! D0TCM_ECC_ERRS_INT - D0TCM access single-bit ECC Error Interrupt Status
49287  *  0b0..D0TCM single-bit ECC error does not happen
49288  *  0b1..D0TCM single-bit ECC error happens.
49289  */
49290 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK)
49291 
49292 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U)
49293 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U)
49294 /*! D1TCM_ECC_ERRM_INT - D1TCM access multi-bit ECC Error Interrupt Status
49295  *  0b0..D1TCM multi-bit ECC error does not happen
49296  *  0b1..D1TCM multi-bit ECC error happens.
49297  */
49298 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK)
49299 
49300 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U)
49301 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U)
49302 /*! D1TCM_ECC_ERRS_INT - D1TCM access single-bit ECC Error Interrupt Status
49303  *  0b0..D1TCM single-bit ECC error does not happen
49304  *  0b1..D1TCM single-bit ECC error happens.
49305  */
49306 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK)
49307 
49308 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U)
49309 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U)
49310 /*! ITCM_PARTIAL_WR_INT_S - ITCM Partial Write Interrupt Status
49311  *  0b0..ITCM Partial Write does not happen
49312  *  0b1..ITCM Partial Write happens.
49313  */
49314 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK)
49315 
49316 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U)
49317 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U)
49318 /*! D0TCM_PARTIAL_WR_INT_S - D0TCM Partial Write Interrupt Status
49319  *  0b0..D0TCM Partial Write does not happen
49320  *  0b1..D0TCM Partial Write happens.
49321  */
49322 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK)
49323 
49324 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U)
49325 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U)
49326 /*! D1TCM_PARTIAL_WR_INT_S - D1TCM Partial Write Interrupt Status
49327  *  0b0..D1TCM Partial Write does not happen
49328  *  0b1..D1TCM Partial Write happens.
49329  */
49330 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK)
49331 
49332 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U)
49333 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U)
49334 /*! OCRAM_PARTIAL_WR_INT_S - OCRAM Partial Write Interrupt Status
49335  *  0b0..OCRAM Partial Write does not happen
49336  *  0b1..OCRAM Partial Write happens.
49337  */
49338 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK)
49339 
49340 #define FLEXRAM_INT_STATUS_Reserved_MASK         (0xFFFC0000U)
49341 #define FLEXRAM_INT_STATUS_Reserved_SHIFT        (18U)
49342 /*! Reserved - Reserved
49343  */
49344 #define FLEXRAM_INT_STATUS_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
49345 /*! @} */
49346 
49347 /*! @name INT_STAT_EN - Interrupt Status Enable Register */
49348 /*! @{ */
49349 
49350 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
49351 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
49352 /*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable
49353  *  0b0..Masked
49354  *  0b1..Enabled
49355  */
49356 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
49357 
49358 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
49359 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
49360 /*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable
49361  *  0b0..Masked
49362  *  0b1..Enabled
49363  */
49364 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
49365 
49366 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
49367 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
49368 /*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable
49369  *  0b0..Masked
49370  *  0b1..Enabled
49371  */
49372 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
49373 
49374 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
49375 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
49376 /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
49377  *  0b0..Masked
49378  *  0b1..Enabled
49379  */
49380 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
49381 
49382 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
49383 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
49384 /*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
49385  *  0b0..Masked
49386  *  0b1..Enabled
49387  */
49388 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
49389 
49390 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
49391 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
49392 /*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
49393  *  0b0..Masked
49394  *  0b1..Enabled
49395  */
49396 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
49397 
49398 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U)
49399 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U)
49400 /*! OCRAM_ERRM_INT_EN - OCRAM Access multi-bit ECC Error Interrupt Status Enable
49401  *  0b0..Masked
49402  *  0b1..Enabled
49403  */
49404 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK)
49405 
49406 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U)
49407 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U)
49408 /*! OCRAM_ERRS_INT_EN - OCRAM Access single-bit ECC Error Interrupt Status Enable
49409  *  0b0..Masked
49410  *  0b1..Enabled
49411  */
49412 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK)
49413 
49414 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U)
49415 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U)
49416 /*! ITCM_ERRM_INT_EN - ITCM Access multi-bit ECC Error Interrupt Status Enable
49417  *  0b0..Masked
49418  *  0b1..Enabled
49419  */
49420 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK)
49421 
49422 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U)
49423 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U)
49424 /*! ITCM_ERRS_INT_EN - ITCM Access single-bit ECC Error Interrupt Status Enable
49425  *  0b0..Masked
49426  *  0b1..Enabled
49427  */
49428 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK)
49429 
49430 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U)
49431 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U)
49432 /*! D0TCM_ERRM_INT_EN - D0TCM Access multi-bit ECC Error Interrupt Status Enable
49433  *  0b0..Masked
49434  *  0b1..Enabled
49435  */
49436 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK)
49437 
49438 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U)
49439 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U)
49440 /*! D0TCM_ERRS_INT_EN - D0TCM Access single-bit ECC Error Interrupt Status Enable
49441  *  0b0..Masked
49442  *  0b1..Enabled
49443  */
49444 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK)
49445 
49446 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U)
49447 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U)
49448 /*! D1TCM_ERRM_INT_EN - D1TCM Access multi-bit ECC Error Interrupt Status Enable
49449  *  0b0..Masked
49450  *  0b1..Enabled
49451  */
49452 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK)
49453 
49454 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U)
49455 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U)
49456 /*! D1TCM_ERRS_INT_EN - D1TCM Access single-bit ECC Error Interrupt Status Enable
49457  *  0b0..Masked
49458  *  0b1..Enabled
49459  */
49460 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK)
49461 
49462 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U)
49463 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U)
49464 /*! ITCM_PARTIAL_WR_INT_S_EN - ITCM Partial Write Interrupt Status Enable
49465  *  0b0..Masked
49466  *  0b1..Enabled
49467  */
49468 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK)
49469 
49470 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U)
49471 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U)
49472 /*! D0TCM_PARTIAL_WR_INT_S_EN - D0TCM Partial Write Interrupt Status Enable
49473  *  0b0..Masked
49474  *  0b1..Enabled
49475  */
49476 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK)
49477 
49478 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U)
49479 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U)
49480 /*! D1TCM_PARTIAL_WR_INT_S_EN - D1TCM Partial Write Interrupt Status EN
49481  *  0b0..Masked
49482  *  0b1..Enbaled
49483  */
49484 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK)
49485 
49486 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U)
49487 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U)
49488 /*! OCRAM_PARTIAL_WR_INT_S_EN - OCRAM Partial Write Interrupt Status
49489  *  0b0..Masked
49490  *  0b1..Enabled
49491  */
49492 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK)
49493 
49494 #define FLEXRAM_INT_STAT_EN_Reserved_MASK        (0xFFFC0000U)
49495 #define FLEXRAM_INT_STAT_EN_Reserved_SHIFT       (18U)
49496 /*! Reserved - Reserved
49497  */
49498 #define FLEXRAM_INT_STAT_EN_Reserved(x)          (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
49499 /*! @} */
49500 
49501 /*! @name INT_SIG_EN - Interrupt Enable Register */
49502 /*! @{ */
49503 
49504 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK  (0x1U)
49505 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
49506 /*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable
49507  *  0b0..Masked
49508  *  0b1..Enabled
49509  */
49510 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
49511 
49512 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK  (0x2U)
49513 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
49514 /*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable
49515  *  0b0..Masked
49516  *  0b1..Enabled
49517  */
49518 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
49519 
49520 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
49521 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
49522 /*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable
49523  *  0b0..Masked
49524  *  0b1..Enabled
49525  */
49526 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
49527 
49528 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK  (0x8U)
49529 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
49530 /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
49531  *  0b0..Masked
49532  *  0b1..Enabled
49533  */
49534 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
49535 
49536 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK  (0x10U)
49537 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
49538 /*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
49539  *  0b0..Masked
49540  *  0b1..Enabled
49541  */
49542 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
49543 
49544 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
49545 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
49546 /*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
49547  *  0b0..Masked
49548  *  0b1..Enabled
49549  */
49550 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
49551 
49552 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U)
49553 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U)
49554 /*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi-bit ECC Error Interrupt Signal Enable
49555  *  0b0..Masked
49556  *  0b1..Enabled
49557  */
49558 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK)
49559 
49560 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U)
49561 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U)
49562 /*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single-bit ECC Error Interrupt Signal Enable
49563  *  0b0..Masked
49564  *  0b1..Enabled
49565  */
49566 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK)
49567 
49568 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U)
49569 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U)
49570 /*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi-bit ECC Error Interrupt Signal Enable
49571  *  0b0..Masked
49572  *  0b1..Enabled
49573  */
49574 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK)
49575 
49576 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U)
49577 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U)
49578 /*! ITCM_ERRS_INT_SIG_EN - ITCM Access single-bit ECC Error Interrupt Signal Enable
49579  *  0b0..Masked
49580  *  0b1..Enabled
49581  */
49582 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK)
49583 
49584 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U)
49585 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U)
49586 /*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi-bit ECC Error Interrupt Signal Enable
49587  *  0b0..Masked
49588  *  0b1..Enabled
49589  */
49590 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK)
49591 
49592 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U)
49593 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U)
49594 /*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single-bit ECC Error Interrupt Signal Enable
49595  *  0b0..Masked
49596  *  0b1..Enabled
49597  */
49598 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK)
49599 
49600 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
49601 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U)
49602 /*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi-bit ECC Error Interrupt Signal Enable
49603  *  0b0..Masked
49604  *  0b1..Enabled
49605  */
49606 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK)
49607 
49608 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
49609 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U)
49610 /*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single-bit ECC Error Interrupt Signal Enable
49611  *  0b0..Masked
49612  *  0b1..Enabled
49613  */
49614 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK)
49615 
49616 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U)
49617 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U)
49618 /*! ITCM_PARTIAL_WR_INT_SIG_EN - ITCM Partial Write Interrupt Signal Enable Enable
49619  *  0b0..Masked
49620  *  0b1..Enabled
49621  */
49622 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK)
49623 
49624 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U)
49625 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U)
49626 /*! D0TCM_PARTIAL_WR_INT_SIG_EN - D0TCM Partial Write Interrupt Signal Enable Enable
49627  *  0b0..Masked
49628  *  0b1..Enabled
49629  */
49630 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK)
49631 
49632 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U)
49633 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U)
49634 /*! D1TCM_PARTIAL_WR_INT_SIG_EN - D1TCM Partial Write Interrupt Signal Enable EN
49635  *  0b0..Masked
49636  *  0b1..Enbaled
49637  */
49638 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK)
49639 
49640 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U)
49641 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U)
49642 /*! OCRAM_PARTIAL_WR_INT_SIG_EN - OCRAM Partial Write Interrupt Signal Enable
49643  *  0b0..Masked
49644  *  0b1..Enabled
49645  */
49646 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK)
49647 
49648 #define FLEXRAM_INT_SIG_EN_Reserved_MASK         (0xFFFC0000U)
49649 #define FLEXRAM_INT_SIG_EN_Reserved_SHIFT        (18U)
49650 /*! Reserved - Reserved
49651  */
49652 #define FLEXRAM_INT_SIG_EN_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
49653 /*! @} */
49654 
49655 /*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register */
49656 /*! @{ */
49657 
49658 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU)
49659 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U)
49660 /*! OCRAM_ECCS_ERRED_ECC - corresponding ECC cipher of OCRAM single-bit ECC error
49661  */
49662 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK)
49663 
49664 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U)
49665 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U)
49666 /*! OCRAM_ECCS_ERRED_SYN - corresponding ECC syndrome of OCRAM single-bit ECC error
49667  */
49668 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK)
49669 
49670 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U)
49671 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U)
49672 /*! Reserved - Reserved
49673  */
49674 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49675 /*! @} */
49676 
49677 /*! @name OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register */
49678 /*! @{ */
49679 
49680 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49681 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U)
49682 /*! OCRAM_ECCS_ERRED_ADDR - OCRAM single-bit ECC error address
49683  */
49684 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK)
49685 /*! @} */
49686 
49687 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register */
49688 /*! @{ */
49689 
49690 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49691 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
49692 /*! OCRAM_ECCS_ERRED_DATA_LSB - OCRAM single-bit ECC error data [31:0]
49693  */
49694 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK)
49695 /*! @} */
49696 
49697 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register */
49698 /*! @{ */
49699 
49700 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49701 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
49702 /*! OCRAM_ECCS_ERRED_DATA_MSB - OCRAM single-bit ECC error data [63:32]
49703  */
49704 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK)
49705 /*! @} */
49706 
49707 /*! @name OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register */
49708 /*! @{ */
49709 
49710 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU)
49711 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U)
49712 /*! OCRAM_ECCM_ERRED_ECC - OCRAM multi-bit ECC error corresponding ECC value
49713  */
49714 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK)
49715 
49716 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U)
49717 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U)
49718 /*! Reserved - Reserved
49719  */
49720 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49721 /*! @} */
49722 
49723 /*! @name OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register */
49724 /*! @{ */
49725 
49726 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49727 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U)
49728 /*! OCRAM_ECCM_ERRED_ADDR - OCRAM multi-bit ECC error address
49729  */
49730 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK)
49731 /*! @} */
49732 
49733 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register */
49734 /*! @{ */
49735 
49736 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49737 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
49738 /*! OCRAM_ECCM_ERRED_DATA_LSB - OCRAM multi-bit ECC error data [31:0]
49739  */
49740 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK)
49741 /*! @} */
49742 
49743 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register */
49744 /*! @{ */
49745 
49746 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49747 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
49748 /*! OCRAM_ECCM_ERRED_DATA_MSB - OCRAM multi-bit ECC error data [63:32]
49749  */
49750 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK)
49751 /*! @} */
49752 
49753 /*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register */
49754 /*! @{ */
49755 
49756 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U)
49757 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U)
49758 /*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding TCM_WR value.
49759  */
49760 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK)
49761 
49762 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU)
49763 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U)
49764 /*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding TCM size
49765  */
49766 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK)
49767 
49768 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U)
49769 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U)
49770 /*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding TCM_MASTER.
49771  */
49772 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK)
49773 
49774 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U)
49775 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U)
49776 /*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding TCM_PRIV.
49777  */
49778 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK)
49779 
49780 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U)
49781 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U)
49782 /*! ITCM_ECCS_EFSYN - ITCM single-bit ECC error corresponding syndrome
49783  */
49784 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK)
49785 
49786 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U)
49787 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U)
49788 /*! Reserved - Reserved
49789  */
49790 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49791 /*! @} */
49792 
49793 /*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */
49794 /*! @{ */
49795 
49796 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49797 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U)
49798 /*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address
49799  */
49800 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK)
49801 /*! @} */
49802 
49803 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */
49804 /*! @{ */
49805 
49806 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49807 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
49808 /*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0]
49809  */
49810 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK)
49811 /*! @} */
49812 
49813 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */
49814 /*! @{ */
49815 
49816 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49817 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
49818 /*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32]
49819  */
49820 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK)
49821 /*! @} */
49822 
49823 /*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */
49824 /*! @{ */
49825 
49826 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U)
49827 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U)
49828 /*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding TCM_WR value
49829  */
49830 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK)
49831 
49832 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU)
49833 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U)
49834 /*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size
49835  */
49836 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK)
49837 
49838 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U)
49839 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U)
49840 /*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding TCM_MASTER
49841  */
49842 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK)
49843 
49844 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U)
49845 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U)
49846 /*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding TCM_PRIV
49847  */
49848 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK)
49849 
49850 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U)
49851 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U)
49852 /*! ITCM_ECCM_EFSYN - ITCM multi-bit ECC error corresponding syndrome
49853  */
49854 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK)
49855 
49856 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U)
49857 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U)
49858 /*! Reserved - Reserved
49859  */
49860 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49861 /*! @} */
49862 
49863 /*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */
49864 /*! @{ */
49865 
49866 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49867 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U)
49868 /*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address
49869  */
49870 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK)
49871 /*! @} */
49872 
49873 /*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */
49874 /*! @{ */
49875 
49876 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49877 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
49878 /*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0]
49879  */
49880 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK)
49881 /*! @} */
49882 
49883 /*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */
49884 /*! @{ */
49885 
49886 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49887 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
49888 /*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32]
49889  */
49890 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK)
49891 /*! @} */
49892 
49893 /*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */
49894 /*! @{ */
49895 
49896 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U)
49897 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U)
49898 /*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding TCM_WR value
49899  */
49900 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK)
49901 
49902 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU)
49903 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U)
49904 /*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size
49905  */
49906 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK)
49907 
49908 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U)
49909 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U)
49910 /*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding TCM_MASTER
49911  */
49912 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK)
49913 
49914 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U)
49915 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U)
49916 /*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding TCM_PRIV
49917  */
49918 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK)
49919 
49920 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U)
49921 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U)
49922 /*! D0TCM_ECCS_EFSYN - D0TCM single-bit ECC error corresponding syndrome
49923  */
49924 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK)
49925 
49926 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49927 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
49928 /*! Reserved - Reserved
49929  */
49930 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49931 /*! @} */
49932 
49933 /*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */
49934 /*! @{ */
49935 
49936 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49937 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U)
49938 /*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address
49939  */
49940 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK)
49941 /*! @} */
49942 
49943 /*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */
49944 /*! @{ */
49945 
49946 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
49947 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U)
49948 /*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data
49949  */
49950 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK)
49951 /*! @} */
49952 
49953 /*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */
49954 /*! @{ */
49955 
49956 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U)
49957 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U)
49958 /*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding TCM_WR value
49959  */
49960 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK)
49961 
49962 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU)
49963 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U)
49964 /*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size
49965  */
49966 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK)
49967 
49968 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U)
49969 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U)
49970 /*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding TCM_MASTER
49971  */
49972 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK)
49973 
49974 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U)
49975 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U)
49976 /*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding TCM_PRIV
49977  */
49978 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK)
49979 
49980 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U)
49981 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U)
49982 /*! D0TCM_ECCM_EFSYN - D0TCM multi-bit ECC error corresponding syndrome
49983  */
49984 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK)
49985 
49986 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49987 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
49988 /*! Reserved - Reserved
49989  */
49990 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49991 /*! @} */
49992 
49993 /*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */
49994 /*! @{ */
49995 
49996 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49997 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U)
49998 /*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address
49999  */
50000 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK)
50001 /*! @} */
50002 
50003 /*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */
50004 /*! @{ */
50005 
50006 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
50007 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U)
50008 /*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data
50009  */
50010 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK)
50011 /*! @} */
50012 
50013 /*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */
50014 /*! @{ */
50015 
50016 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U)
50017 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U)
50018 /*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding TCM_WR value
50019  */
50020 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK)
50021 
50022 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU)
50023 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U)
50024 /*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size
50025  */
50026 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK)
50027 
50028 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U)
50029 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U)
50030 /*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding TCM_MASTER
50031  */
50032 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK)
50033 
50034 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U)
50035 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U)
50036 /*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding TCM_PRIV
50037  */
50038 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK)
50039 
50040 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U)
50041 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U)
50042 /*! D1TCM_ECCS_EFSYN - D1TCM single-bit ECC error corresponding syndrome
50043  */
50044 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK)
50045 
50046 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50047 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
50048 /*! Reserved - Reserved
50049  */
50050 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
50051 /*! @} */
50052 
50053 /*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */
50054 /*! @{ */
50055 
50056 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
50057 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U)
50058 /*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address
50059  */
50060 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK)
50061 /*! @} */
50062 
50063 /*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */
50064 /*! @{ */
50065 
50066 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
50067 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U)
50068 /*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data
50069  */
50070 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK)
50071 /*! @} */
50072 
50073 /*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */
50074 /*! @{ */
50075 
50076 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U)
50077 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U)
50078 /*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding TCM_WR value
50079  */
50080 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK)
50081 
50082 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU)
50083 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U)
50084 /*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size
50085  */
50086 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK)
50087 
50088 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U)
50089 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U)
50090 /*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding TCM_MASTER
50091  */
50092 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK)
50093 
50094 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U)
50095 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U)
50096 /*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding TCM_PRIV
50097  */
50098 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK)
50099 
50100 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U)
50101 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U)
50102 /*! D1TCM_ECCM_EFSYN - D1TCM multi-bit ECC error corresponding syndrome
50103  */
50104 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK)
50105 
50106 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50107 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
50108 /*! Reserved - Reserved
50109  */
50110 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
50111 /*! @} */
50112 
50113 /*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */
50114 /*! @{ */
50115 
50116 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
50117 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U)
50118 /*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address
50119  */
50120 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK)
50121 /*! @} */
50122 
50123 /*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */
50124 /*! @{ */
50125 
50126 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
50127 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U)
50128 /*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data
50129  */
50130 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK)
50131 /*! @} */
50132 
50133 /*! @name FLEXRAM_CTRL - FlexRAM feature Control register */
50134 /*! @{ */
50135 
50136 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U)
50137 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U)
50138 /*! OCRAM_RDATA_WAIT_EN - Read Data Wait Enable
50139  */
50140 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK)
50141 
50142 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U)
50143 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U)
50144 /*! OCRAM_RADDR_PIPELINE_EN - Read Address Pipeline Enable
50145  */
50146 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK)
50147 
50148 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U)
50149 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U)
50150 /*! OCRAM_WRDATA_PIPELINE_EN - Write Data Pipeline Enable
50151  */
50152 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK)
50153 
50154 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U)
50155 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U)
50156 /*! OCRAM_WRADDR_PIPELINE_EN - Write Address Pipeline Enable
50157  */
50158 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK)
50159 
50160 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK   (0x10U)
50161 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT  (4U)
50162 /*! OCRAM_ECC_EN - OCRAM ECC enable
50163  */
50164 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK)
50165 
50166 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK     (0x20U)
50167 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT    (5U)
50168 /*! TCM_ECC_EN - TCM ECC enable
50169  */
50170 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x)       (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK)
50171 
50172 #define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK       (0xFFFFFFC0U)
50173 #define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT      (6U)
50174 /*! Reserved - Reserved
50175  */
50176 #define FLEXRAM_FLEXRAM_CTRL_Reserved(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK)
50177 /*! @} */
50178 
50179 /*! @name OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register */
50180 /*! @{ */
50181 
50182 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U)
50183 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U)
50184 /*! OCRAM_RDATA_WAIT_EN_UPDATA_PENDING - Read Data Wait Enable Pending
50185  */
50186 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK)
50187 
50188 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U)
50189 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U)
50190 /*! OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING - Read Address Pipeline Enable Pending
50191  */
50192 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
50193 
50194 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U)
50195 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U)
50196 /*! OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING - Write Data Pipeline Enable Pending
50197  */
50198 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK)
50199 
50200 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U)
50201 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U)
50202 /*! OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING - Write Address Pipeline Enable Pending
50203  */
50204 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
50205 
50206 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U)
50207 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U)
50208 /*! Reserved - Reserved
50209  */
50210 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK)
50211 /*! @} */
50212 
50213 
50214 /*!
50215  * @}
50216  */ /* end of group FLEXRAM_Register_Masks */
50217 
50218 
50219 /* FLEXRAM - Peripheral instance base addresses */
50220 /** Peripheral FLEXRAM base address */
50221 #define FLEXRAM_BASE                             (0x40028000u)
50222 /** Peripheral FLEXRAM base pointer */
50223 #define FLEXRAM                                  ((FLEXRAM_Type *)FLEXRAM_BASE)
50224 /** Array initializer of FLEXRAM peripheral base addresses */
50225 #define FLEXRAM_BASE_ADDRS                       { FLEXRAM_BASE }
50226 /** Array initializer of FLEXRAM peripheral base pointers */
50227 #define FLEXRAM_BASE_PTRS                        { FLEXRAM }
50228 /** Interrupt vectors for the FLEXRAM peripheral type */
50229 #define FLEXRAM_ECC_IRQS                         { FLEXRAM_ECC_IRQn }
50230 
50231 /*!
50232  * @}
50233  */ /* end of group FLEXRAM_Peripheral_Access_Layer */
50234 
50235 
50236 /* ----------------------------------------------------------------------------
50237    -- FLEXSPI Peripheral Access Layer
50238    ---------------------------------------------------------------------------- */
50239 
50240 /*!
50241  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
50242  * @{
50243  */
50244 
50245 /** FLEXSPI - Register Layout Typedef */
50246 typedef struct {
50247   __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
50248   __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
50249   __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
50250   __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
50251   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
50252   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
50253   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
50254   __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
50255   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
50256        uint8_t RESERVED_0[32];
50257   __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
50258   __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
50259   __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
50260        uint8_t RESERVED_1[4];
50261   __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
50262        uint8_t RESERVED_2[8];
50263   __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
50264   __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
50265        uint8_t RESERVED_3[8];
50266   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
50267        uint8_t RESERVED_4[4];
50268   __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
50269   __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
50270   __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
50271        uint8_t RESERVED_5[8];
50272   __I  uint32_t MISCCR4;                           /**< Misc Control Register 4, offset: 0xD0 */
50273   __I  uint32_t MISCCR5;                           /**< Misc Control Register 5, offset: 0xD4 */
50274   __I  uint32_t MISCCR6;                           /**< Misc Control Register 6, offset: 0xD8 */
50275   __I  uint32_t MISCCR7;                           /**< Misc Control Register 7, offset: 0xDC */
50276   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
50277   __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
50278   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
50279   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
50280   __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
50281   __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
50282        uint8_t RESERVED_6[8];
50283   __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
50284   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
50285   __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
50286        uint8_t RESERVED_7[256];
50287   __IO uint32_t HMSTRCR[8];                        /**< AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4 */
50288   __IO uint32_t HADDRSTART;                        /**< HADDR REMAP START ADDR, offset: 0x420 */
50289   __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
50290   __IO uint32_t HADDROFFSET;                       /**< HADDR REMAP OFFSET, offset: 0x428 */
50291        uint8_t RESERVED_8[4];
50292   __IO uint32_t IPSNSZSTART0;                      /**< IPS nonsecure region Start address of region 0, offset: 0x430 */
50293   __IO uint32_t IPSNSZEND0;                        /**< IPS nonsecure region End address of region 0, offset: 0x434 */
50294   __IO uint32_t IPSNSZSTART1;                      /**< IPS nonsecure region Start address of region 1, offset: 0x438 */
50295   __IO uint32_t IPSNSZEND1;                        /**< IPS nonsecure region End address of region 1, offset: 0x43C */
50296   __IO uint32_t AHBBUFREGIONSTART0;                /**< RX BUF Start address of region 0, offset: 0x440 */
50297   __IO uint32_t AHBBUFREGIONEND0;                  /**< RX BUF region End address of region 0, offset: 0x444 */
50298   __IO uint32_t AHBBUFREGIONSTART1;                /**< RX BUF Start address of region 1, offset: 0x448 */
50299   __IO uint32_t AHBBUFREGIONEND1;                  /**< RX BUF region End address of region 1, offset: 0x44C */
50300   __IO uint32_t AHBBUFREGIONSTART2;                /**< RX BUF Start address of region 2, offset: 0x450 */
50301   __IO uint32_t AHBBUFREGIONEND2;                  /**< RX BUF region End address of region 2, offset: 0x454 */
50302   __IO uint32_t AHBBUFREGIONSTART3;                /**< RX BUF Start address of region 3, offset: 0x458 */
50303   __IO uint32_t AHBBUFREGIONEND3;                  /**< RX BUF region End address of region 3, offset: 0x45C */
50304 } FLEXSPI_Type;
50305 
50306 /* ----------------------------------------------------------------------------
50307    -- FLEXSPI Register Masks
50308    ---------------------------------------------------------------------------- */
50309 
50310 /*!
50311  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
50312  * @{
50313  */
50314 
50315 /*! @name MCR0 - Module Control Register 0 */
50316 /*! @{ */
50317 
50318 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
50319 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
50320 /*! SWRESET - Software Reset
50321  */
50322 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
50323 
50324 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
50325 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
50326 /*! MDIS - Module Disable
50327  */
50328 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
50329 
50330 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
50331 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
50332 /*! RXCLKSRC - Sample Clock source selection for Flash Reading
50333  *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
50334  *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
50335  *  0b10..Reserved
50336  *  0b11..Flash provided Read strobe and input from DQS pad
50337  */
50338 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
50339 
50340 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
50341 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
50342 /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
50343  *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
50344  *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
50345  */
50346 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
50347 
50348 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
50349 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
50350 /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
50351  *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
50352  *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
50353  */
50354 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
50355 
50356 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
50357 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
50358 /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
50359  *  0b000..Divided by 1
50360  *  0b001..Divided by 2
50361  *  0b010..Divided by 3
50362  *  0b011..Divided by 4
50363  *  0b100..Divided by 5
50364  *  0b101..Divided by 6
50365  *  0b110..Divided by 7
50366  *  0b111..Divided by 8
50367  */
50368 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
50369 
50370 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
50371 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
50372 /*! HSEN - Half Speed Serial Flash access Enable.
50373  *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
50374  *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
50375  */
50376 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
50377 
50378 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
50379 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
50380 /*! DOZEEN - Doze mode enable bit
50381  *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
50382  *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
50383  */
50384 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
50385 
50386 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
50387 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
50388 /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data
50389  *    pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.
50390  *  0b0..Disable.
50391  *  0b1..Enable.
50392  */
50393 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
50394 
50395 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
50396 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
50397 /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
50398  *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
50399  *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
50400  *  0b0..Disable.
50401  *  0b1..Enable.
50402  */
50403 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
50404 
50405 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
50406 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
50407 /*! IPGRANTWAIT - Time out wait cycle for IP command grant.
50408  */
50409 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
50410 
50411 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
50412 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
50413 /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
50414  */
50415 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
50416 /*! @} */
50417 
50418 /*! @name MCR1 - Module Control Register 1 */
50419 /*! @{ */
50420 
50421 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
50422 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
50423 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
50424 
50425 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
50426 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
50427 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
50428 /*! @} */
50429 
50430 /*! @name MCR2 - Module Control Register 2 */
50431 /*! @{ */
50432 
50433 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
50434 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
50435 /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
50436  *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
50437  *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
50438  *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
50439  *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
50440  *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
50441  */
50442 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
50443 
50444 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
50445 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
50446 /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
50447  *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
50448  *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
50449  *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
50450  *       ignored.
50451  *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
50452  */
50453 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
50454 
50455 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
50456 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
50457 /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
50458  *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
50459  *    field, MCR0[SWRESET] should be set.
50460  *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
50461  *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
50462  */
50463 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
50464 
50465 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
50466 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
50467 /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
50468  */
50469 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
50470 /*! @} */
50471 
50472 /*! @name AHBCR - AHB Bus Control Register */
50473 /*! @{ */
50474 
50475 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
50476 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
50477 /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
50478  *  0b0..Flash will be accessed in Individual mode.
50479  *  0b1..Flash will be accessed in Parallel mode.
50480  */
50481 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
50482 
50483 #define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
50484 #define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
50485 /*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
50486  */
50487 #define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
50488 
50489 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
50490 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
50491 /*! CACHABLEEN - Enable AHB bus cachable read access support.
50492  *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
50493  *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
50494  */
50495 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
50496 
50497 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
50498 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
50499 /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
50500  *    of AHB write access, refer for more details about AHB bufferable write.
50501  *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
50502  *       ready after all data is transmitted to External device and AHB command finished.
50503  *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
50504  *       granted by arbitrator and will not wait for AHB command finished.
50505  */
50506 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
50507 
50508 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
50509 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
50510 /*! PREFETCHEN - AHB Read Prefetch Enable.
50511  */
50512 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
50513 
50514 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
50515 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
50516 /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
50517  *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.
50518  *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
50519  *       burst required to meet the alignment requirement.
50520  */
50521 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
50522 
50523 #define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
50524 #define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
50525 /*! READSZALIGN - AHB Read Size Alignment
50526  *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
50527  *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
50528  */
50529 #define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
50530 
50531 #define FLEXSPI_AHBCR_ECCEN_MASK                 (0x800U)
50532 #define FLEXSPI_AHBCR_ECCEN_SHIFT                (11U)
50533 /*! ECCEN - AHB Read ECC Enable
50534  *  0b0..AHB read ECC check disabled
50535  *  0b1..AHB read ECC check enabled
50536  */
50537 #define FLEXSPI_AHBCR_ECCEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK)
50538 
50539 #define FLEXSPI_AHBCR_SPLITEN_MASK               (0x1000U)
50540 #define FLEXSPI_AHBCR_SPLITEN_SHIFT              (12U)
50541 /*! SPLITEN - AHB transaction SPLIT
50542  *  0b0..AHB Split disabled
50543  *  0b1..AHB Split enabled
50544  */
50545 #define FLEXSPI_AHBCR_SPLITEN(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK)
50546 
50547 #define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK           (0x6000U)
50548 #define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT          (13U)
50549 /*! SPLIT_LIMIT - AHB SPLIT SIZE
50550  *  0b00..AHB Split Size=8bytes
50551  *  0b01..AHB Split Size=16bytes
50552  *  0b10..AHB Split Size=32bytes
50553  *  0b11..AHB Split Size=64bytes
50554  */
50555 #define FLEXSPI_AHBCR_SPLIT_LIMIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK)
50556 
50557 #define FLEXSPI_AHBCR_KEYECCEN_MASK              (0x8000U)
50558 #define FLEXSPI_AHBCR_KEYECCEN_SHIFT             (15U)
50559 /*! KEYECCEN - OTFAD KEY BLOC ECC Enable
50560  *  0b0..AHB KEY ECC check disabled
50561  *  0b1..AHB KEY ECC check enabled
50562  */
50563 #define FLEXSPI_AHBCR_KEYECCEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK)
50564 
50565 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK       (0x10000U)
50566 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT      (16U)
50567 /*! ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR
50568  */
50569 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK)
50570 
50571 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK        (0x20000U)
50572 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT       (17U)
50573 /*! ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR
50574  */
50575 #define FLEXSPI_AHBCR_ECCMULTIERRCLR(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK)
50576 
50577 #define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK          (0x40000U)
50578 #define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT         (18U)
50579 /*! HMSTRIDREMAP - AHB Master ID Remapping enable
50580  */
50581 #define FLEXSPI_AHBCR_HMSTRIDREMAP(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK)
50582 
50583 #define FLEXSPI_AHBCR_ECCSWAPEN_MASK             (0x80000U)
50584 #define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT            (19U)
50585 /*! ECCSWAPEN - ECC Read data swap function
50586  *  0b0..rdata send to ecc check without swap.
50587  *  0b1..rdata send to ecc ehck with swap.
50588  */
50589 #define FLEXSPI_AHBCR_ECCSWAPEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK)
50590 
50591 #define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
50592 #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
50593 /*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses.
50594  *  0b00..No limit
50595  *  0b01..1 KBytes
50596  *  0b10..512 Bytes
50597  *  0b11..256 Bytes
50598  */
50599 #define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
50600 /*! @} */
50601 
50602 /*! @name INTEN - Interrupt Enable Register */
50603 /*! @{ */
50604 
50605 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
50606 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
50607 /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
50608  */
50609 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
50610 
50611 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
50612 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
50613 /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
50614  */
50615 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
50616 
50617 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
50618 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
50619 /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
50620  */
50621 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
50622 
50623 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
50624 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
50625 /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
50626  */
50627 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
50628 
50629 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
50630 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
50631 /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
50632  */
50633 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
50634 
50635 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
50636 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
50637 /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
50638  */
50639 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
50640 
50641 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
50642 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
50643 /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
50644  */
50645 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
50646 
50647 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
50648 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
50649 /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
50650  */
50651 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
50652 
50653 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
50654 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
50655 /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
50656  */
50657 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
50658 
50659 #define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
50660 #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
50661 /*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
50662  */
50663 #define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
50664 
50665 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
50666 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
50667 /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
50668  */
50669 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
50670 
50671 #define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
50672 #define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
50673 /*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
50674  */
50675 #define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
50676 
50677 #define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
50678 #define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
50679 /*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
50680  */
50681 #define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
50682 
50683 #define FLEXSPI_INTEN_ECCMULTIERREN_MASK         (0x4000U)
50684 #define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT        (14U)
50685 /*! ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details.
50686  */
50687 #define FLEXSPI_INTEN_ECCMULTIERREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK)
50688 
50689 #define FLEXSPI_INTEN_ECCSINGLEERREN_MASK        (0x8000U)
50690 #define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT       (15U)
50691 /*! ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details.
50692  */
50693 #define FLEXSPI_INTEN_ECCSINGLEERREN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK)
50694 
50695 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK      (0x10000U)
50696 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT     (16U)
50697 /*! IPCMDSECUREVIOEN - IP command security violation interrupt enable.
50698  */
50699 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
50700 /*! @} */
50701 
50702 /*! @name INTR - Interrupt Register */
50703 /*! @{ */
50704 
50705 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
50706 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
50707 /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
50708  *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
50709  */
50710 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
50711 
50712 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
50713 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
50714 /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
50715  */
50716 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
50717 
50718 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
50719 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
50720 /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
50721  */
50722 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
50723 
50724 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
50725 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
50726 /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
50727  *    IP command, this command will be ignored and not executed at all.
50728  */
50729 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
50730 
50731 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
50732 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
50733 /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
50734  *    AHB command, this command will be ignored and not executed at all.
50735  */
50736 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
50737 
50738 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
50739 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
50740 /*! IPRXWA - IP RX FIFO watermark available interrupt.
50741  */
50742 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
50743 
50744 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
50745 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
50746 /*! IPTXWE - IP TX FIFO watermark empty interrupt.
50747  */
50748 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
50749 
50750 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
50751 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
50752 /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
50753  */
50754 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
50755 
50756 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
50757 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
50758 /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
50759  */
50760 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
50761 
50762 #define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
50763 #define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
50764 /*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
50765  */
50766 #define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
50767 
50768 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
50769 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
50770 /*! SEQTIMEOUT - Sequence execution timeout interrupt.
50771  */
50772 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
50773 
50774 #define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
50775 #define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
50776 /*! KEYDONE - OTFAD key blob processing done interrupt.
50777  */
50778 #define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
50779 
50780 #define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
50781 #define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
50782 /*! KEYERROR - OTFAD key blob processing error interrupt.
50783  */
50784 #define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
50785 
50786 #define FLEXSPI_INTR_ECCMULTIERR_MASK            (0x4000U)
50787 #define FLEXSPI_INTR_ECCMULTIERR_SHIFT           (14U)
50788 /*! ECCMULTIERR - ECC multi bits error interrupt.
50789  */
50790 #define FLEXSPI_INTR_ECCMULTIERR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK)
50791 
50792 #define FLEXSPI_INTR_ECCSINGLEERR_MASK           (0x8000U)
50793 #define FLEXSPI_INTR_ECCSINGLEERR_SHIFT          (15U)
50794 /*! ECCSINGLEERR - ECC single bit error interrupt.
50795  */
50796 #define FLEXSPI_INTR_ECCSINGLEERR(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK)
50797 
50798 #define FLEXSPI_INTR_IPCMDSECUREVIO_MASK         (0x10000U)
50799 #define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT        (16U)
50800 /*! IPCMDSECUREVIO - IP command security violation interrupt.
50801  */
50802 #define FLEXSPI_INTR_IPCMDSECUREVIO(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
50803 /*! @} */
50804 
50805 /*! @name LUTKEY - LUT Key Register */
50806 /*! @{ */
50807 
50808 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
50809 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
50810 /*! KEY - The Key to lock or unlock LUT.
50811  */
50812 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
50813 /*! @} */
50814 
50815 /*! @name LUTCR - LUT Control Register */
50816 /*! @{ */
50817 
50818 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
50819 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
50820 /*! LOCK - Lock LUT
50821  */
50822 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
50823 
50824 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
50825 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
50826 /*! UNLOCK - Unlock LUT
50827  */
50828 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
50829 
50830 #define FLEXSPI_LUTCR_PROTECT_MASK               (0x4U)
50831 #define FLEXSPI_LUTCR_PROTECT_SHIFT              (2U)
50832 /*! PROTECT - LUT protection
50833  */
50834 #define FLEXSPI_LUTCR_PROTECT(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
50835 /*! @} */
50836 
50837 /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
50838 /*! @{ */
50839 
50840 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x3FFU)
50841 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
50842 /*! BUFSZ - AHB RX Buffer Size in 64 bits.
50843  */
50844 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
50845 
50846 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
50847 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
50848 /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
50849  */
50850 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
50851 
50852 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
50853 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
50854 /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
50855  */
50856 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
50857 
50858 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK        (0x40000000U)
50859 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT       (30U)
50860 /*! REGIONEN - AHB RX Buffer address region funciton enable
50861  */
50862 #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
50863 
50864 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
50865 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
50866 /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
50867  */
50868 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
50869 /*! @} */
50870 
50871 /* The count of FLEXSPI_AHBRXBUFCR0 */
50872 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
50873 
50874 /*! @name FLSHCR0 - Flash Control Register 0 */
50875 /*! @{ */
50876 
50877 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
50878 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
50879 /*! FLSHSZ - Flash Size in KByte.
50880  */
50881 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
50882 
50883 #define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
50884 #define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
50885 /*! SPLITWREN - AHB write access split function control.
50886  */
50887 #define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
50888 
50889 #define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
50890 #define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
50891 /*! SPLITRDEN - AHB read access split function control.
50892  */
50893 #define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
50894 /*! @} */
50895 
50896 /* The count of FLEXSPI_FLSHCR0 */
50897 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
50898 
50899 /*! @name FLSHCR1 - Flash Control Register 1 */
50900 /*! @{ */
50901 
50902 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
50903 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
50904 /*! TCSS - Serial Flash CS setup time.
50905  */
50906 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
50907 
50908 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
50909 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
50910 /*! TCSH - Serial Flash CS Hold time.
50911  */
50912 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
50913 
50914 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
50915 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
50916 /*! WA - Word Addressable.
50917  */
50918 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
50919 
50920 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
50921 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
50922 /*! CAS - Column Address Size.
50923  */
50924 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
50925 
50926 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
50927 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
50928 /*! CSINTERVALUNIT - CS interval unit
50929  *  0b0..The CS interval unit is 1 serial clock cycle
50930  *  0b1..The CS interval unit is 256 serial clock cycle
50931  */
50932 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
50933 
50934 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
50935 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
50936 /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
50937  *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
50938  *    the interval between command sequences, this field should be set accordingly. If there is no
50939  *    limitation, set this field with value 0x0.
50940  */
50941 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
50942 /*! @} */
50943 
50944 /* The count of FLEXSPI_FLSHCR1 */
50945 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
50946 
50947 /*! @name FLSHCR2 - Flash Control Register 2 */
50948 /*! @{ */
50949 
50950 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
50951 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
50952 /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
50953  */
50954 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
50955 
50956 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
50957 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
50958 /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
50959  */
50960 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
50961 
50962 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
50963 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
50964 /*! AWRSEQID - Sequence Index for AHB Write triggered Command.
50965  */
50966 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
50967 
50968 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
50969 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
50970 /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
50971  */
50972 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
50973 
50974 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
50975 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
50976 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
50977 
50978 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
50979 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
50980 /*! AWRWAITUNIT - AWRWAIT unit
50981  *  0b000..The AWRWAIT unit is 2 ahb clock cycle
50982  *  0b001..The AWRWAIT unit is 8 ahb clock cycle
50983  *  0b010..The AWRWAIT unit is 32 ahb clock cycle
50984  *  0b011..The AWRWAIT unit is 128 ahb clock cycle
50985  *  0b100..The AWRWAIT unit is 512 ahb clock cycle
50986  *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
50987  *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
50988  *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
50989  */
50990 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
50991 
50992 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
50993 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
50994 /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
50995  *    Refer Programmable Sequence Engine for details.
50996  */
50997 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
50998 /*! @} */
50999 
51000 /* The count of FLEXSPI_FLSHCR2 */
51001 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
51002 
51003 /*! @name FLSHCR4 - Flash Control Register 4 */
51004 /*! @{ */
51005 
51006 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
51007 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
51008 /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
51009  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
51010  *       burst start address alignment when flash is accessed in individual mode.
51011  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
51012  *       burst start address alignment when flash is accessed in individual mode.
51013  */
51014 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
51015 
51016 #define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
51017 #define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
51018 /*! WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove
51019  *    AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set.
51020  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
51021  *       burst length when flash is accessed in individual mode.
51022  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
51023  *       burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
51024  */
51025 #define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
51026 
51027 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
51028 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
51029 /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
51030  *    memory device on port A, this bit must be set.
51031  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
51032  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
51033  */
51034 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
51035 
51036 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
51037 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
51038 /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
51039  *    memory device on port B, this bit must be set.
51040  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
51041  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
51042  */
51043 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
51044 
51045 #define FLEXSPI_FLSHCR4_PAR_WM_MASK              (0x600U)
51046 #define FLEXSPI_FLSHCR4_PAR_WM_SHIFT             (9U)
51047 /*! PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.
51048  */
51049 #define FLEXSPI_FLSHCR4_PAR_WM(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK)
51050 
51051 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK    (0x800U)
51052 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT   (11U)
51053 /*! PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM.
51054  */
51055 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK)
51056 /*! @} */
51057 
51058 /*! @name IPCR0 - IP Control Register 0 */
51059 /*! @{ */
51060 
51061 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
51062 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
51063 /*! SFAR - Serial Flash Address for IP command.
51064  */
51065 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
51066 /*! @} */
51067 
51068 /*! @name IPCR1 - IP Control Register 1 */
51069 /*! @{ */
51070 
51071 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
51072 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
51073 /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
51074  */
51075 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
51076 
51077 #define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
51078 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
51079 /*! ISEQID - Sequence Index in LUT for IP command.
51080  */
51081 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
51082 
51083 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
51084 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
51085 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
51086  */
51087 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
51088 
51089 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
51090 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
51091 /*! IPAREN - Parallel mode Enabled for IP command.
51092  *  0b0..Flash will be accessed in Individual mode.
51093  *  0b1..Flash will be accessed in Parallel mode.
51094  */
51095 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
51096 /*! @} */
51097 
51098 /*! @name IPCMD - IP Command Register */
51099 /*! @{ */
51100 
51101 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
51102 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
51103 /*! TRG - Setting this bit will trigger an IP Command.
51104  */
51105 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
51106 /*! @} */
51107 
51108 /*! @name IPRXFCR - IP RX FIFO Control Register */
51109 /*! @{ */
51110 
51111 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
51112 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
51113 /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
51114  */
51115 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
51116 
51117 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
51118 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
51119 /*! RXDMAEN - IP RX FIFO reading by DMA enabled.
51120  *  0b0..IP RX FIFO would be read by processor.
51121  *  0b1..IP RX FIFO would be read by DMA.
51122  */
51123 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
51124 
51125 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x7CU)
51126 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
51127 /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
51128  */
51129 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
51130 /*! @} */
51131 
51132 /*! @name IPTXFCR - IP TX FIFO Control Register */
51133 /*! @{ */
51134 
51135 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
51136 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
51137 /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
51138  */
51139 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
51140 
51141 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
51142 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
51143 /*! TXDMAEN - IP TX FIFO filling by DMA enabled.
51144  *  0b0..IP TX FIFO would be filled by processor.
51145  *  0b1..IP TX FIFO would be filled by DMA.
51146  */
51147 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
51148 
51149 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x7CU)
51150 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
51151 /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
51152  */
51153 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
51154 /*! @} */
51155 
51156 /*! @name DLLCR - DLL Control Register 0 */
51157 /*! @{ */
51158 
51159 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
51160 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
51161 /*! DLLEN - DLL calibration enable.
51162  */
51163 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
51164 
51165 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
51166 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
51167 /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
51168  *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
51169  *    action is edge triggered, so software need to clear this bit after set this bit (no delay
51170  *    limitation).
51171  */
51172 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
51173 
51174 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
51175 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
51176 /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
51177  *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
51178  *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
51179  */
51180 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
51181 
51182 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
51183 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
51184 /*! OVRDEN - Slave clock delay line delay cell number selection override enable.
51185  */
51186 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
51187 
51188 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
51189 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
51190 /*! OVRDVAL - Slave clock delay line delay cell number selection override value.
51191  */
51192 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
51193 /*! @} */
51194 
51195 /* The count of FLEXSPI_DLLCR */
51196 #define FLEXSPI_DLLCR_COUNT                      (2U)
51197 
51198 /*! @name MISCCR4 - Misc Control Register 4 */
51199 /*! @{ */
51200 
51201 #define FLEXSPI_MISCCR4_AHBADDRESS_MASK          (0xFFFFFFFFU)
51202 #define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT         (0U)
51203 /*! AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt.
51204  */
51205 #define FLEXSPI_MISCCR4_AHBADDRESS(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK)
51206 /*! @} */
51207 
51208 /*! @name MISCCR5 - Misc Control Register 5 */
51209 /*! @{ */
51210 
51211 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK  (0xFFFFFFFFU)
51212 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U)
51213 /*! ECCSINGLEERRORCORR - ECC single bit error correction indication.
51214  */
51215 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK)
51216 /*! @} */
51217 
51218 /*! @name MISCCR6 - Misc Control Register 6 */
51219 /*! @{ */
51220 
51221 #define FLEXSPI_MISCCR6_VALID_MASK               (0x1U)
51222 #define FLEXSPI_MISCCR6_VALID_SHIFT              (0U)
51223 /*! VALID - ECC single error information Valid
51224  */
51225 #define FLEXSPI_MISCCR6_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK)
51226 
51227 #define FLEXSPI_MISCCR6_HIT_MASK                 (0x2U)
51228 #define FLEXSPI_MISCCR6_HIT_SHIFT                (1U)
51229 /*! HIT - ECC single error information Hit
51230  */
51231 #define FLEXSPI_MISCCR6_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK)
51232 
51233 #define FLEXSPI_MISCCR6_ADDRESS_MASK             (0xFFFFFFFCU)
51234 #define FLEXSPI_MISCCR6_ADDRESS_SHIFT            (2U)
51235 /*! ADDRESS - ECC single error address
51236  */
51237 #define FLEXSPI_MISCCR6_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK)
51238 /*! @} */
51239 
51240 /*! @name MISCCR7 - Misc Control Register 7 */
51241 /*! @{ */
51242 
51243 #define FLEXSPI_MISCCR7_VALID_MASK               (0x1U)
51244 #define FLEXSPI_MISCCR7_VALID_SHIFT              (0U)
51245 /*! VALID - ECC multi error information Valid
51246  */
51247 #define FLEXSPI_MISCCR7_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK)
51248 
51249 #define FLEXSPI_MISCCR7_HIT_MASK                 (0x2U)
51250 #define FLEXSPI_MISCCR7_HIT_SHIFT                (1U)
51251 /*! HIT - ECC multi error information Hit
51252  */
51253 #define FLEXSPI_MISCCR7_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK)
51254 
51255 #define FLEXSPI_MISCCR7_ADDRESS_MASK             (0xFFFFFFFCU)
51256 #define FLEXSPI_MISCCR7_ADDRESS_SHIFT            (2U)
51257 /*! ADDRESS - ECC multi error address
51258  */
51259 #define FLEXSPI_MISCCR7_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK)
51260 /*! @} */
51261 
51262 /*! @name STS0 - Status Register 0 */
51263 /*! @{ */
51264 
51265 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
51266 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
51267 /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
51268  *    sequence executing on FlexSPI interface.
51269  */
51270 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
51271 
51272 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
51273 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
51274 /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
51275  *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
51276  *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
51277  *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
51278  */
51279 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
51280 
51281 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
51282 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
51283 /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
51284  *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
51285  *  0b00..Triggered by AHB read command (triggered by AHB read).
51286  *  0b01..Triggered by AHB write command (triggered by AHB Write).
51287  *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
51288  *  0b11..Triggered by suspended command (resumed).
51289  */
51290 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
51291 /*! @} */
51292 
51293 /*! @name STS1 - Status Register 1 */
51294 /*! @{ */
51295 
51296 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
51297 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
51298 /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
51299  *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
51300  */
51301 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
51302 
51303 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
51304 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
51305 /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
51306  *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
51307  *  0b0000..No error.
51308  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
51309  *  0b0011..There is unknown instruction opcode in the sequence.
51310  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
51311  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
51312  *  0b1110..Sequence execution timeout.
51313  */
51314 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
51315 
51316 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
51317 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
51318 /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
51319  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
51320  */
51321 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
51322 
51323 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
51324 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
51325 /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
51326  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
51327  *  0b0000..No error.
51328  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
51329  *  0b0011..There is unknown instruction opcode in the sequence.
51330  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
51331  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
51332  *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
51333  *  0b1110..Sequence execution timeout.
51334  *  0b1111..Flash boundary crossed.
51335  */
51336 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
51337 /*! @} */
51338 
51339 /*! @name STS2 - Status Register 2 */
51340 /*! @{ */
51341 
51342 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
51343 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
51344 /*! ASLVLOCK - Flash A sample clock slave delay line locked.
51345  */
51346 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
51347 
51348 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
51349 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
51350 /*! AREFLOCK - Flash A sample clock reference delay line locked.
51351  */
51352 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
51353 
51354 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
51355 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
51356 /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
51357  */
51358 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
51359 
51360 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
51361 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
51362 /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
51363  */
51364 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
51365 
51366 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
51367 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
51368 /*! BSLVLOCK - Flash B sample clock slave delay line locked.
51369  */
51370 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
51371 
51372 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
51373 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
51374 /*! BREFLOCK - Flash B sample clock reference delay line locked.
51375  */
51376 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
51377 
51378 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
51379 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
51380 /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
51381  */
51382 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
51383 
51384 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
51385 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
51386 /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
51387  */
51388 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
51389 /*! @} */
51390 
51391 /*! @name AHBSPNDSTS - AHB Suspend Status Register */
51392 /*! @{ */
51393 
51394 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
51395 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
51396 /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
51397  */
51398 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
51399 
51400 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
51401 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
51402 /*! BUFID - AHB RX BUF ID for suspended command sequence.
51403  */
51404 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
51405 
51406 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
51407 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
51408 /*! DATLFT - Left Data size for suspended command sequence (in byte).
51409  */
51410 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
51411 /*! @} */
51412 
51413 /*! @name IPRXFSTS - IP RX FIFO Status Register */
51414 /*! @{ */
51415 
51416 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
51417 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
51418 /*! FILL - Fill level of IP RX FIFO.
51419  */
51420 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
51421 
51422 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
51423 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
51424 /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
51425  */
51426 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
51427 /*! @} */
51428 
51429 /*! @name IPTXFSTS - IP TX FIFO Status Register */
51430 /*! @{ */
51431 
51432 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
51433 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
51434 /*! FILL - Fill level of IP TX FIFO.
51435  */
51436 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
51437 
51438 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
51439 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
51440 /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
51441  */
51442 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
51443 /*! @} */
51444 
51445 /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
51446 /*! @{ */
51447 
51448 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
51449 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
51450 /*! RXDATA - RX Data
51451  */
51452 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
51453 /*! @} */
51454 
51455 /* The count of FLEXSPI_RFDR */
51456 #define FLEXSPI_RFDR_COUNT                       (32U)
51457 
51458 /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
51459 /*! @{ */
51460 
51461 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
51462 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
51463 /*! TXDATA - TX Data
51464  */
51465 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
51466 /*! @} */
51467 
51468 /* The count of FLEXSPI_TFDR */
51469 #define FLEXSPI_TFDR_COUNT                       (32U)
51470 
51471 /*! @name LUT - LUT 0..LUT 63 */
51472 /*! @{ */
51473 
51474 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
51475 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
51476 /*! OPERAND0 - OPERAND0
51477  */
51478 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
51479 
51480 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
51481 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
51482 /*! NUM_PADS0 - NUM_PADS0
51483  */
51484 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
51485 
51486 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
51487 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
51488 /*! OPCODE0 - OPCODE
51489  */
51490 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
51491 
51492 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
51493 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
51494 /*! OPERAND1 - OPERAND1
51495  */
51496 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
51497 
51498 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
51499 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
51500 /*! NUM_PADS1 - NUM_PADS1
51501  */
51502 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
51503 
51504 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
51505 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
51506 /*! OPCODE1 - OPCODE1
51507  */
51508 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
51509 /*! @} */
51510 
51511 /* The count of FLEXSPI_LUT */
51512 #define FLEXSPI_LUT_COUNT                        (64U)
51513 
51514 /*! @name HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register */
51515 /*! @{ */
51516 
51517 #define FLEXSPI_HMSTRCR_MASK_MASK                (0xFFFFU)
51518 #define FLEXSPI_HMSTRCR_MASK_SHIFT               (0U)
51519 /*! MASK - Mask bits for AHB master ID.
51520  *  0b0000000000000000..Mask
51521  *  0b0000000000000001..Unmask
51522  */
51523 #define FLEXSPI_HMSTRCR_MASK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK)
51524 
51525 #define FLEXSPI_HMSTRCR_MSTRID_MASK              (0xFFFF0000U)
51526 #define FLEXSPI_HMSTRCR_MSTRID_SHIFT             (16U)
51527 /*! MSTRID - This is expected Master ID.
51528  */
51529 #define FLEXSPI_HMSTRCR_MSTRID(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK)
51530 /*! @} */
51531 
51532 /* The count of FLEXSPI_HMSTRCR */
51533 #define FLEXSPI_HMSTRCR_COUNT                    (8U)
51534 
51535 /*! @name HADDRSTART - HADDR REMAP START ADDR */
51536 /*! @{ */
51537 
51538 #define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
51539 #define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
51540 /*! REMAPEN
51541  *  0b0..HADDR REMAP Disabled
51542  *  0b1..HADDR REMAP Enabled
51543  */
51544 #define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
51545 
51546 #define FLEXSPI_HADDRSTART_KBINECC_MASK          (0x2U)
51547 #define FLEXSPI_HADDRSTART_KBINECC_SHIFT         (1U)
51548 /*! KBINECC
51549  *  0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset
51550  *  0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2
51551  */
51552 #define FLEXSPI_HADDRSTART_KBINECC(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK)
51553 
51554 #define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
51555 #define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
51556 #define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
51557 /*! @} */
51558 
51559 /*! @name HADDREND - HADDR REMAP END ADDR */
51560 /*! @{ */
51561 
51562 #define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
51563 #define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
51564 #define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
51565 /*! @} */
51566 
51567 /*! @name HADDROFFSET - HADDR REMAP OFFSET */
51568 /*! @{ */
51569 
51570 #define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
51571 #define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
51572 #define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
51573 /*! @} */
51574 
51575 /*! @name IPSNSZSTART0 - IPS nonsecure region Start address of region 0 */
51576 /*! @{ */
51577 
51578 #define FLEXSPI_IPSNSZSTART0_start_address_MASK  (0xFFFFF000U)
51579 #define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U)
51580 /*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address.
51581  */
51582 #define FLEXSPI_IPSNSZSTART0_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK)
51583 /*! @} */
51584 
51585 /*! @name IPSNSZEND0 - IPS nonsecure region End address of region 0 */
51586 /*! @{ */
51587 
51588 #define FLEXSPI_IPSNSZEND0_end_address_MASK      (0xFFFFF000U)
51589 #define FLEXSPI_IPSNSZEND0_end_address_SHIFT     (12U)
51590 /*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address.
51591  */
51592 #define FLEXSPI_IPSNSZEND0_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK)
51593 /*! @} */
51594 
51595 /*! @name IPSNSZSTART1 - IPS nonsecure region Start address of region 1 */
51596 /*! @{ */
51597 
51598 #define FLEXSPI_IPSNSZSTART1_start_address_MASK  (0xFFFFF000U)
51599 #define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U)
51600 /*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address.
51601  */
51602 #define FLEXSPI_IPSNSZSTART1_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK)
51603 /*! @} */
51604 
51605 /*! @name IPSNSZEND1 - IPS nonsecure region End address of region 1 */
51606 /*! @{ */
51607 
51608 #define FLEXSPI_IPSNSZEND1_end_address_MASK      (0xFFFFF000U)
51609 #define FLEXSPI_IPSNSZEND1_end_address_SHIFT     (12U)
51610 /*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address.
51611  */
51612 #define FLEXSPI_IPSNSZEND1_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK)
51613 /*! @} */
51614 
51615 /*! @name AHBBUFREGIONSTART0 - RX BUF Start address of region 0 */
51616 /*! @{ */
51617 
51618 #define FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U)
51619 #define FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U)
51620 /*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address.
51621  */
51622 #define FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK)
51623 /*! @} */
51624 
51625 /*! @name AHBBUFREGIONEND0 - RX BUF region End address of region 0 */
51626 /*! @{ */
51627 
51628 #define FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U)
51629 #define FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U)
51630 /*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address.
51631  */
51632 #define FLEXSPI_AHBBUFREGIONEND0_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK)
51633 /*! @} */
51634 
51635 /*! @name AHBBUFREGIONSTART1 - RX BUF Start address of region 1 */
51636 /*! @{ */
51637 
51638 #define FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U)
51639 #define FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U)
51640 /*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address.
51641  */
51642 #define FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK)
51643 /*! @} */
51644 
51645 /*! @name AHBBUFREGIONEND1 - RX BUF region End address of region 1 */
51646 /*! @{ */
51647 
51648 #define FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U)
51649 #define FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U)
51650 /*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address.
51651  */
51652 #define FLEXSPI_AHBBUFREGIONEND1_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK)
51653 /*! @} */
51654 
51655 /*! @name AHBBUFREGIONSTART2 - RX BUF Start address of region 2 */
51656 /*! @{ */
51657 
51658 #define FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U)
51659 #define FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U)
51660 /*! start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address.
51661  */
51662 #define FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK)
51663 /*! @} */
51664 
51665 /*! @name AHBBUFREGIONEND2 - RX BUF region End address of region 2 */
51666 /*! @{ */
51667 
51668 #define FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U)
51669 #define FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U)
51670 /*! end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address.
51671  */
51672 #define FLEXSPI_AHBBUFREGIONEND2_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK)
51673 /*! @} */
51674 
51675 /*! @name AHBBUFREGIONSTART3 - RX BUF Start address of region 3 */
51676 /*! @{ */
51677 
51678 #define FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U)
51679 #define FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U)
51680 /*! start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address.
51681  */
51682 #define FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK)
51683 /*! @} */
51684 
51685 /*! @name AHBBUFREGIONEND3 - RX BUF region End address of region 3 */
51686 /*! @{ */
51687 
51688 #define FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U)
51689 #define FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U)
51690 /*! end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address.
51691  */
51692 #define FLEXSPI_AHBBUFREGIONEND3_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK)
51693 /*! @} */
51694 
51695 
51696 /*!
51697  * @}
51698  */ /* end of group FLEXSPI_Register_Masks */
51699 
51700 
51701 /* FLEXSPI - Peripheral instance base addresses */
51702 /** Peripheral FLEXSPI1 base address */
51703 #define FLEXSPI1_BASE                            (0x400CC000u)
51704 /** Peripheral FLEXSPI1 base pointer */
51705 #define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
51706 /** Peripheral FLEXSPI2 base address */
51707 #define FLEXSPI2_BASE                            (0x400D0000u)
51708 /** Peripheral FLEXSPI2 base pointer */
51709 #define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
51710 /** Array initializer of FLEXSPI peripheral base addresses */
51711 #define FLEXSPI_BASE_ADDRS                       { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
51712 /** Array initializer of FLEXSPI peripheral base pointers */
51713 #define FLEXSPI_BASE_PTRS                        { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
51714 /** Interrupt vectors for the FLEXSPI peripheral type */
51715 #define FLEXSPI_IRQS                             { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
51716 /* FlexSPI1 AMBA address. */
51717 #define FlexSPI1_AMBA_BASE                       (0x30000000U)
51718 /* FlexSPI1 ASFM address. */
51719 #define FlexSPI1_ASFM_BASE                        (0x30000000U)
51720 /* Base Address of AHB address space mapped to IP RX FIFO. */
51721 #define FlexSPI1_ARDF_BASE                        (0x2FC00000U)
51722 /* Base Address of AHB address space mapped to IP TX FIFO. */
51723 #define FlexSPI1_ATDF_BASE                        (0x2F800000U)
51724 /* FlexSPI1 alias base address. */
51725 #define FlexSPI1_ALIAS_BASE                       (0x8000000U)
51726 /* FlexSPI2 AMBA address. */
51727 #define FlexSPI2_AMBA_BASE                        (0x60000000U)
51728 /* FlexSPI ASFM address. */
51729 #define FlexSPI2_ASFM_BASE                        (0x60000000U)
51730 /* Base Address of AHB address space mapped to IP RX FIFO. */
51731 #define FlexSPI2_ARDF_BASE                        (0x7FC00000U)
51732 /* Base Address of AHB address space mapped to IP TX FIFO. */
51733 #define FlexSPI2_ATDF_BASE                        (0x7F800000U)
51734 
51735 
51736 /*!
51737  * @}
51738  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
51739 
51740 
51741 /* ----------------------------------------------------------------------------
51742    -- GPC_CPU_MODE_CTRL Peripheral Access Layer
51743    ---------------------------------------------------------------------------- */
51744 
51745 /*!
51746  * @addtogroup GPC_CPU_MODE_CTRL_Peripheral_Access_Layer GPC_CPU_MODE_CTRL Peripheral Access Layer
51747  * @{
51748  */
51749 
51750 /** GPC_CPU_MODE_CTRL - Register Layout Typedef */
51751 typedef struct {
51752        uint8_t RESERVED_0[4];
51753   __IO uint32_t CM_AUTHEN_CTRL;                    /**< CM Authentication Control, offset: 0x4 */
51754   __IO uint32_t CM_INT_CTRL;                       /**< CM Interrupt Control, offset: 0x8 */
51755   __IO uint32_t CM_MISC;                           /**< Miscellaneous, offset: 0xC */
51756   __IO uint32_t CM_MODE_CTRL;                      /**< CPU mode control, offset: 0x10 */
51757   __I  uint32_t CM_MODE_STAT;                      /**< CM CPU mode Status, offset: 0x14 */
51758        uint8_t RESERVED_1[232];
51759   __IO uint32_t CM_IRQ_WAKEUP_MASK[8];             /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4 */
51760        uint8_t RESERVED_2[32];
51761   __IO uint32_t CM_NON_IRQ_WAKEUP_MASK;            /**< CM non-irq wakeup mask, offset: 0x140 */
51762        uint8_t RESERVED_3[12];
51763   __I  uint32_t CM_IRQ_WAKEUP_STAT[8];             /**< CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4 */
51764        uint8_t RESERVED_4[32];
51765   __I  uint32_t CM_NON_IRQ_WAKEUP_STAT;            /**< CM non-irq wakeup status, offset: 0x190 */
51766        uint8_t RESERVED_5[108];
51767   __IO uint32_t CM_SLEEP_SSAR_CTRL;                /**< CM sleep SSAR control, offset: 0x200 */
51768        uint8_t RESERVED_6[4];
51769   __IO uint32_t CM_SLEEP_LPCG_CTRL;                /**< CM sleep LPCG control, offset: 0x208 */
51770        uint8_t RESERVED_7[4];
51771   __IO uint32_t CM_SLEEP_PLL_CTRL;                 /**< CM sleep PLL control, offset: 0x210 */
51772        uint8_t RESERVED_8[4];
51773   __IO uint32_t CM_SLEEP_ISO_CTRL;                 /**< CM sleep isolation control, offset: 0x218 */
51774        uint8_t RESERVED_9[4];
51775   __IO uint32_t CM_SLEEP_RESET_CTRL;               /**< CM sleep reset control, offset: 0x220 */
51776        uint8_t RESERVED_10[4];
51777   __IO uint32_t CM_SLEEP_POWER_CTRL;               /**< CM sleep power control, offset: 0x228 */
51778        uint8_t RESERVED_11[100];
51779   __IO uint32_t CM_WAKEUP_POWER_CTRL;              /**< CM wakeup power control, offset: 0x290 */
51780        uint8_t RESERVED_12[4];
51781   __IO uint32_t CM_WAKEUP_RESET_CTRL;              /**< CM wakeup reset control, offset: 0x298 */
51782        uint8_t RESERVED_13[4];
51783   __IO uint32_t CM_WAKEUP_ISO_CTRL;                /**< CM wakeup isolation control, offset: 0x2A0 */
51784        uint8_t RESERVED_14[4];
51785   __IO uint32_t CM_WAKEUP_PLL_CTRL;                /**< CM wakeup PLL control, offset: 0x2A8 */
51786        uint8_t RESERVED_15[4];
51787   __IO uint32_t CM_WAKEUP_LPCG_CTRL;               /**< CM wakeup LPCG control, offset: 0x2B0 */
51788        uint8_t RESERVED_16[4];
51789   __IO uint32_t CM_WAKEUP_SSAR_CTRL;               /**< CM wakeup SSAR control, offset: 0x2B8 */
51790        uint8_t RESERVED_17[68];
51791   __IO uint32_t CM_SP_CTRL;                        /**< CM Setpoint Control, offset: 0x300 */
51792   __I  uint32_t CM_SP_STAT;                        /**< CM Setpoint Status, offset: 0x304 */
51793        uint8_t RESERVED_18[8];
51794   __IO uint32_t CM_RUN_MODE_MAPPING;               /**< CM Run Mode Setpoint Allowed, offset: 0x310 */
51795   __IO uint32_t CM_WAIT_MODE_MAPPING;              /**< CM Wait Mode Setpoint Allowed, offset: 0x314 */
51796   __IO uint32_t CM_STOP_MODE_MAPPING;              /**< CM Stop Mode Setpoint Allowed, offset: 0x318 */
51797   __IO uint32_t CM_SUSPEND_MODE_MAPPING;           /**< CM Suspend Mode Setpoint Allowed, offset: 0x31C */
51798   __IO uint32_t CM_SP_MAPPING[16];                 /**< CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4 */
51799        uint8_t RESERVED_19[32];
51800   __IO uint32_t CM_STBY_CTRL;                      /**< CM standby control, offset: 0x380 */
51801 } GPC_CPU_MODE_CTRL_Type;
51802 
51803 /* ----------------------------------------------------------------------------
51804    -- GPC_CPU_MODE_CTRL Register Masks
51805    ---------------------------------------------------------------------------- */
51806 
51807 /*!
51808  * @addtogroup GPC_CPU_MODE_CTRL_Register_Masks GPC_CPU_MODE_CTRL Register Masks
51809  * @{
51810  */
51811 
51812 /*! @name CM_AUTHEN_CTRL - CM Authentication Control */
51813 /*! @{ */
51814 
51815 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U)
51816 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U)
51817 /*! USER - Allow user mode access
51818  *  0b0..Allow only privilege mode to access CPU mode control registers
51819  *  0b1..Allow both privilege and user mode to access CPU mode control registers
51820  */
51821 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK)
51822 
51823 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
51824 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
51825 /*! NONSECURE - Allow non-secure mode access
51826  *  0b0..Allow only secure mode to access CPU mode control registers
51827  *  0b1..Allow both secure and non-secure mode to access CPU mode control registers
51828  */
51829 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
51830 
51831 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
51832 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
51833 /*! LOCK_SETTING - Lock NONSECURE and USER
51834  */
51835 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
51836 
51837 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
51838 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
51839 /*! WHITE_LIST - Domain ID white list
51840  */
51841 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
51842 
51843 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
51844 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
51845 /*! LOCK_LIST - White list lock
51846  */
51847 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
51848 
51849 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
51850 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
51851 /*! LOCK_CFG - Configuration lock
51852  */
51853 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
51854 /*! @} */
51855 
51856 /*! @name CM_INT_CTRL - CM Interrupt Control */
51857 /*! @{ */
51858 
51859 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U)
51860 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U)
51861 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT_EN - sp_req_not_allowed_for_sleep interrupt enable
51862  *  0b0..Interrupt disable
51863  *  0b1..Interrupt enable
51864  */
51865 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK)
51866 
51867 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U)
51868 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U)
51869 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN - sp_req_not_allowed_for_wakeup interrupt enable
51870  *  0b0..Interrupt disable
51871  *  0b1..Interrupt enable
51872  */
51873 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK)
51874 
51875 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U)
51876 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U)
51877 /*! SP_REQ_NOT_ALLOWED_SOFT_INT_EN - sp_req_not_allowed_for_soft interrupt enable
51878  *  0b0..Interrupt disable
51879  *  0b1..Interrupt enable
51880  */
51881 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK)
51882 
51883 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U)
51884 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U)
51885 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT - sp_req_not_allowed_for_sleep interrupt status and clear register
51886  */
51887 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK)
51888 
51889 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U)
51890 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U)
51891 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT - sp_req_not_allowed_for_wakeup interrupt status and clear register
51892  */
51893 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK)
51894 
51895 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U)
51896 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U)
51897 /*! SP_REQ_NOT_ALLOWED_SOFT_INT - sp_req_not_allowed_for_soft interrupt status and clear register
51898  */
51899 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
51900 /*! @} */
51901 
51902 /*! @name CM_MISC - Miscellaneous */
51903 /*! @{ */
51904 
51905 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK  (0x1U)
51906 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U)
51907 /*! NMI_STAT - Non-masked interrupt status
51908  *  0b0..NMI is not asserting
51909  *  0b1..NMI is asserting
51910  */
51911 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x)    (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK)
51912 
51913 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U)
51914 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
51915 /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status
51916  *  0b0..Disable cpu_sleep_hold_req
51917  *  0b1..Allow cpu_sleep_hold_req assert during CPU low power status
51918  */
51919 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
51920 
51921 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
51922 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
51923 /*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b
51924  */
51925 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
51926 
51927 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U)
51928 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U)
51929 /*! MASTER_CPU - Master CPU
51930  */
51931 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x)  (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK)
51932 /*! @} */
51933 
51934 /*! @name CM_MODE_CTRL - CPU mode control */
51935 /*! @{ */
51936 
51937 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
51938 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
51939 /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event
51940  *  0b00..Stay in RUN mode
51941  *  0b01..Transit to WAIT mode
51942  *  0b10..Transit to STOP mode
51943  *  0b11..Transit to SUSPEND mode
51944  */
51945 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
51946 
51947 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U)
51948 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U)
51949 /*! WFE_EN - WFE assertion can be sleep event
51950  *  0b0..WFE assertion can not trigger low power
51951  *  0b1..WFE assertion can trigger low power
51952  */
51953 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
51954 /*! @} */
51955 
51956 /*! @name CM_MODE_STAT - CM CPU mode Status */
51957 /*! @{ */
51958 
51959 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
51960 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
51961 /*! CPU_MODE_CURRENT - Current CPU mode
51962  *  0b00..CPU is currently in RUN mode
51963  *  0b01..CPU is currently in WAIT mode
51964  *  0b10..CPU is currently in STOP mode
51965  *  0b11..CPU is currently in SUSPEND mode
51966  */
51967 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
51968 
51969 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
51970 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
51971 /*! CPU_MODE_PREVIOUS - Previous CPU mode
51972  *  0b00..CPU was previously in RUN mode
51973  *  0b01..CPU was previously in WAIT mode
51974  *  0b10..CPU was previously in STOP mode
51975  *  0b11..CPU was previously in SUSPEND mode
51976  */
51977 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
51978 /*! @} */
51979 
51980 /*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */
51981 /*! @{ */
51982 
51983 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU)
51984 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U)
51985 /*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform
51986  */
51987 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK)
51988 
51989 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU)
51990 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U)
51991 /*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform
51992  */
51993 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK)
51994 
51995 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU)
51996 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U)
51997 /*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform
51998  */
51999 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK)
52000 
52001 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU)
52002 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U)
52003 /*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform
52004  */
52005 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK)
52006 
52007 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU)
52008 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U)
52009 /*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform
52010  */
52011 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK)
52012 
52013 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU)
52014 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U)
52015 /*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform
52016  */
52017 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK)
52018 
52019 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU)
52020 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U)
52021 /*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform
52022  */
52023 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK)
52024 
52025 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
52026 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
52027 /*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform
52028  */
52029 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK)
52030 /*! @} */
52031 
52032 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK */
52033 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U)
52034 
52035 /*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask */
52036 /*! @{ */
52037 
52038 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U)
52039 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U)
52040 /*! EVENT_WAKEUP_MASK - There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source.
52041  *  0b1..The event cannot wakeup CPU platform
52042  */
52043 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK)
52044 
52045 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
52046 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
52047 /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform
52048  */
52049 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
52050 /*! @} */
52051 
52052 /*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */
52053 /*! @{ */
52054 
52055 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
52056 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
52057 /*! IRQ_WAKEUP_MASK_224_255 - IRQ status
52058  *  0b00000000000000000000000000000000..None
52059  *  0b00000000000000000000000000000001..Valid
52060  */
52061 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK)
52062 
52063 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU)
52064 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U)
52065 /*! IRQ_WAKEUP_STAT_0_31 - IRQ status
52066  *  0b00000000000000000000000000000000..None
52067  *  0b00000000000000000000000000000001..Valid
52068  */
52069 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK)
52070 
52071 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU)
52072 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U)
52073 /*! IRQ_WAKEUP_STAT_32_63 - IRQ status
52074  *  0b00000000000000000000000000000000..None
52075  *  0b00000000000000000000000000000001..Valid
52076  */
52077 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK)
52078 
52079 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU)
52080 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U)
52081 /*! IRQ_WAKEUP_STAT_64_95 - IRQ status
52082  *  0b00000000000000000000000000000000..None
52083  *  0b00000000000000000000000000000001..Valid
52084  */
52085 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK)
52086 
52087 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU)
52088 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U)
52089 /*! IRQ_WAKEUP_STAT_96_127 - IRQ status
52090  *  0b00000000000000000000000000000000..None
52091  *  0b00000000000000000000000000000001..Valid
52092  */
52093 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK)
52094 
52095 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU)
52096 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U)
52097 /*! IRQ_WAKEUP_STAT_128_159 - IRQ status
52098  *  0b00000000000000000000000000000000..None
52099  *  0b00000000000000000000000000000001..Valid
52100  */
52101 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK)
52102 
52103 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU)
52104 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U)
52105 /*! IRQ_WAKEUP_STAT_160_191 - IRQ status
52106  *  0b00000000000000000000000000000000..None
52107  *  0b00000000000000000000000000000001..Valid
52108  */
52109 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK)
52110 
52111 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU)
52112 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U)
52113 /*! IRQ_WAKEUP_STAT_192_223 - IRQ status
52114  *  0b00000000000000000000000000000000..None
52115  *  0b00000000000000000000000000000001..Valid
52116  */
52117 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK)
52118 /*! @} */
52119 
52120 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT */
52121 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U)
52122 
52123 /*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */
52124 /*! @{ */
52125 
52126 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U)
52127 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U)
52128 /*! EVENT_WAKEUP_STAT - Event wakeup status
52129  *  0b1..Interrupt is asserting (pending)
52130  */
52131 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK)
52132 
52133 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
52134 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
52135 /*! DEBUG_WAKEUP_STAT - Debug wakeup status
52136  */
52137 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
52138 /*! @} */
52139 
52140 /*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */
52141 /*! @{ */
52142 
52143 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
52144 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
52145 /*! STEP_CNT - Step count, useage is depending on CNT_MODE.
52146  */
52147 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK)
52148 
52149 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
52150 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
52151 /*! CNT_MODE - Count mode
52152  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52153  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52154  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52155  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52156  */
52157 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK)
52158 
52159 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
52160 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
52161 /*! DISABLE - Disable this step
52162  */
52163 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
52164 /*! @} */
52165 
52166 /*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */
52167 /*! @{ */
52168 
52169 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
52170 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
52171 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52172  */
52173 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK)
52174 
52175 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
52176 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
52177 /*! CNT_MODE - Count mode
52178  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52179  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52180  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52181  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52182  */
52183 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK)
52184 
52185 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
52186 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
52187 /*! DISABLE - Disable this step
52188  */
52189 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
52190 /*! @} */
52191 
52192 /*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */
52193 /*! @{ */
52194 
52195 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
52196 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U)
52197 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52198  */
52199 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK)
52200 
52201 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
52202 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U)
52203 /*! CNT_MODE - Count mode
52204  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52205  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52206  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52207  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52208  */
52209 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK)
52210 
52211 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
52212 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
52213 /*! DISABLE - Disable this step
52214  */
52215 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
52216 /*! @} */
52217 
52218 /*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */
52219 /*! @{ */
52220 
52221 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
52222 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U)
52223 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52224  */
52225 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK)
52226 
52227 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
52228 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U)
52229 /*! CNT_MODE - Count mode
52230  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52231  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52232  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52233  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52234  */
52235 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK)
52236 
52237 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
52238 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
52239 /*! DISABLE - Disable this step
52240  */
52241 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
52242 /*! @} */
52243 
52244 /*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */
52245 /*! @{ */
52246 
52247 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
52248 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U)
52249 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52250  */
52251 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK)
52252 
52253 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
52254 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U)
52255 /*! CNT_MODE - Count mode
52256  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52257  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52258  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52259  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52260  */
52261 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK)
52262 
52263 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
52264 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
52265 /*! DISABLE - Disable this step
52266  */
52267 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
52268 /*! @} */
52269 
52270 /*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */
52271 /*! @{ */
52272 
52273 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
52274 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U)
52275 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52276  */
52277 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK)
52278 
52279 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
52280 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U)
52281 /*! CNT_MODE - Count mode
52282  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52283  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52284  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52285  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52286  */
52287 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK)
52288 
52289 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
52290 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
52291 /*! DISABLE - Disable this step
52292  */
52293 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
52294 /*! @} */
52295 
52296 /*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */
52297 /*! @{ */
52298 
52299 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
52300 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U)
52301 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52302  */
52303 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK)
52304 
52305 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
52306 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U)
52307 /*! CNT_MODE - Count mode
52308  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52309  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52310  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52311  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52312  */
52313 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK)
52314 
52315 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
52316 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
52317 /*! DISABLE - Disable this step
52318  */
52319 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
52320 /*! @} */
52321 
52322 /*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */
52323 /*! @{ */
52324 
52325 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
52326 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U)
52327 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52328  */
52329 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK)
52330 
52331 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
52332 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U)
52333 /*! CNT_MODE - Count mode
52334  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52335  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52336  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52337  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52338  */
52339 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK)
52340 
52341 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
52342 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
52343 /*! DISABLE - Disable this step
52344  */
52345 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
52346 /*! @} */
52347 
52348 /*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */
52349 /*! @{ */
52350 
52351 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
52352 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U)
52353 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52354  */
52355 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK)
52356 
52357 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
52358 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U)
52359 /*! CNT_MODE - Count mode
52360  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52361  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52362  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52363  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52364  */
52365 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK)
52366 
52367 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
52368 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
52369 /*! DISABLE - Disable this step
52370  */
52371 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
52372 /*! @} */
52373 
52374 /*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */
52375 /*! @{ */
52376 
52377 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
52378 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U)
52379 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52380  */
52381 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK)
52382 
52383 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
52384 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U)
52385 /*! CNT_MODE - Count mode
52386  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52387  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52388  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52389  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52390  */
52391 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK)
52392 
52393 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
52394 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
52395 /*! DISABLE - Disable this step
52396  */
52397 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
52398 /*! @} */
52399 
52400 /*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */
52401 /*! @{ */
52402 
52403 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
52404 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
52405 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52406  */
52407 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK)
52408 
52409 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
52410 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
52411 /*! CNT_MODE - Count mode
52412  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52413  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52414  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52415  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52416  */
52417 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK)
52418 
52419 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
52420 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
52421 /*! DISABLE - Disable this step
52422  */
52423 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
52424 /*! @} */
52425 
52426 /*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */
52427 /*! @{ */
52428 
52429 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
52430 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
52431 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52432  */
52433 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK)
52434 
52435 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
52436 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
52437 /*! CNT_MODE - Count mode
52438  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52439  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52440  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52441  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52442  */
52443 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK)
52444 
52445 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
52446 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
52447 /*! DISABLE - Disable this step
52448  */
52449 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
52450 /*! @} */
52451 
52452 /*! @name CM_SP_CTRL - CM Setpoint Control */
52453 /*! @{ */
52454 
52455 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U)
52456 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U)
52457 /*! CPU_SP_RUN_EN - Request a Setpoint transition when this bit is set
52458  */
52459 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK)
52460 
52461 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU)
52462 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U)
52463 /*! CPU_SP_RUN - The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set
52464  */
52465 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK)
52466 
52467 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U)
52468 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U)
52469 /*! CPU_SP_SLEEP_EN - 1 means enable Setpoint transition on next CPU platform sleep sequence
52470  */
52471 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK)
52472 
52473 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U)
52474 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U)
52475 /*! CPU_SP_SLEEP - The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence
52476  */
52477 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK)
52478 
52479 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U)
52480 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U)
52481 /*! CPU_SP_WAKEUP_EN - 1 means enable Setpoint transition on next CPU platform wakeup sequence
52482  */
52483 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK)
52484 
52485 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U)
52486 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U)
52487 /*! CPU_SP_WAKEUP - The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence
52488  */
52489 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK)
52490 
52491 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U)
52492 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U)
52493 /*! CPU_SP_WAKEUP_SEL - Select the Setpoint transiton on the next CPU platform wakeup sequence
52494  *  0b0..Request SP transition to CPU_SP_WAKEUP
52495  *  0b1..Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS
52496  */
52497 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK)
52498 /*! @} */
52499 
52500 /*! @name CM_SP_STAT - CM Setpoint Status */
52501 /*! @{ */
52502 
52503 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU)
52504 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U)
52505 /*! CPU_SP_CURRENT - The current Setpoint of the system
52506  */
52507 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK)
52508 
52509 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U)
52510 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U)
52511 /*! CPU_SP_PREVIOUS - The previous Setpoint of the system
52512  */
52513 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK)
52514 
52515 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U)
52516 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U)
52517 /*! CPU_SP_TARGET - The requested Setpoint from the CPU platform
52518  */
52519 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK)
52520 /*! @} */
52521 
52522 /*! @name CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed */
52523 /*! @{ */
52524 
52525 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU)
52526 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U)
52527 /*! CPU_RUN_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field
52528  */
52529 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK)
52530 /*! @} */
52531 
52532 /*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed */
52533 /*! @{ */
52534 
52535 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU)
52536 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U)
52537 /*! CPU_WAIT_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
52538  */
52539 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK)
52540 /*! @} */
52541 
52542 /*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed */
52543 /*! @{ */
52544 
52545 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU)
52546 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U)
52547 /*! CPU_STOP_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
52548  */
52549 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK)
52550 /*! @} */
52551 
52552 /*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed */
52553 /*! @{ */
52554 
52555 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU)
52556 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U)
52557 /*! CPU_SUSPEND_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
52558  */
52559 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK)
52560 /*! @} */
52561 
52562 /*! @name CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping */
52563 /*! @{ */
52564 
52565 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU)
52566 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U)
52567 /*! CPU_SP0_MAPPING - Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52568  */
52569 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK)
52570 
52571 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU)
52572 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U)
52573 /*! CPU_SP1_MAPPING - Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52574  */
52575 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK)
52576 
52577 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU)
52578 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U)
52579 /*! CPU_SP2_MAPPING - Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52580  */
52581 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK)
52582 
52583 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU)
52584 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U)
52585 /*! CPU_SP3_MAPPING - Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52586  */
52587 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK)
52588 
52589 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU)
52590 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U)
52591 /*! CPU_SP4_MAPPING - Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52592  */
52593 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK)
52594 
52595 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU)
52596 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U)
52597 /*! CPU_SP5_MAPPING - Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52598  */
52599 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK)
52600 
52601 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU)
52602 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U)
52603 /*! CPU_SP6_MAPPING - Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52604  */
52605 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK)
52606 
52607 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU)
52608 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U)
52609 /*! CPU_SP7_MAPPING - Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52610  */
52611 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK)
52612 
52613 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU)
52614 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U)
52615 /*! CPU_SP8_MAPPING - Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52616  */
52617 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK)
52618 
52619 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU)
52620 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U)
52621 /*! CPU_SP9_MAPPING - Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52622  */
52623 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK)
52624 
52625 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU)
52626 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U)
52627 /*! CPU_SP10_MAPPING - Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52628  */
52629 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK)
52630 
52631 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU)
52632 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U)
52633 /*! CPU_SP11_MAPPING - Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52634  */
52635 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK)
52636 
52637 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU)
52638 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U)
52639 /*! CPU_SP12_MAPPING - Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52640  */
52641 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK)
52642 
52643 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU)
52644 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U)
52645 /*! CPU_SP13_MAPPING - Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52646  */
52647 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK)
52648 
52649 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU)
52650 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U)
52651 /*! CPU_SP14_MAPPING - Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52652  */
52653 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK)
52654 
52655 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU)
52656 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U)
52657 /*! CPU_SP15_MAPPING - Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
52658  */
52659 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK)
52660 /*! @} */
52661 
52662 /* The count of GPC_CPU_MODE_CTRL_CM_SP_MAPPING */
52663 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT    (16U)
52664 
52665 /*! @name CM_STBY_CTRL - CM standby control */
52666 /*! @{ */
52667 
52668 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U)
52669 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U)
52670 /*! STBY_WAIT - 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field.
52671  */
52672 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK)
52673 
52674 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U)
52675 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U)
52676 /*! STBY_STOP - 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field.
52677  */
52678 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK)
52679 
52680 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U)
52681 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U)
52682 /*! STBY_SUSPEND - 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field.
52683  */
52684 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK)
52685 
52686 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U)
52687 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U)
52688 /*! STBY_SLEEP_BUSY - Indicate the CPU is busy entering standby mode.
52689  */
52690 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK)
52691 
52692 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U)
52693 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U)
52694 /*! STBY_WAKEUP_BUSY - Indicate the CPU is busy exiting standby mode.
52695  */
52696 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK)
52697 /*! @} */
52698 
52699 
52700 /*!
52701  * @}
52702  */ /* end of group GPC_CPU_MODE_CTRL_Register_Masks */
52703 
52704 
52705 /* GPC_CPU_MODE_CTRL - Peripheral instance base addresses */
52706 /** Peripheral GPC_CPU_MODE_CTRL_0 base address */
52707 #define GPC_CPU_MODE_CTRL_0_BASE                 (0x40C00000u)
52708 /** Peripheral GPC_CPU_MODE_CTRL_0 base pointer */
52709 #define GPC_CPU_MODE_CTRL_0                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
52710 /** Peripheral GPC_CPU_MODE_CTRL_1 base address */
52711 #define GPC_CPU_MODE_CTRL_1_BASE                 (0x40C00800u)
52712 /** Peripheral GPC_CPU_MODE_CTRL_1 base pointer */
52713 #define GPC_CPU_MODE_CTRL_1                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
52714 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses */
52715 #define GPC_CPU_MODE_CTRL_BASE_ADDRS             { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
52716 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers */
52717 #define GPC_CPU_MODE_CTRL_BASE_PTRS              { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
52718 
52719 /*!
52720  * @}
52721  */ /* end of group GPC_CPU_MODE_CTRL_Peripheral_Access_Layer */
52722 
52723 
52724 /* ----------------------------------------------------------------------------
52725    -- GPC_SET_POINT_CTRL Peripheral Access Layer
52726    ---------------------------------------------------------------------------- */
52727 
52728 /*!
52729  * @addtogroup GPC_SET_POINT_CTRL_Peripheral_Access_Layer GPC_SET_POINT_CTRL Peripheral Access Layer
52730  * @{
52731  */
52732 
52733 /** GPC_SET_POINT_CTRL - Register Layout Typedef */
52734 typedef struct {
52735        uint8_t RESERVED_0[4];
52736   __IO uint32_t SP_AUTHEN_CTRL;                    /**< SP Authentication Control, offset: 0x4 */
52737   __IO uint32_t SP_INT_CTRL;                       /**< SP Interrupt Control, offset: 0x8 */
52738        uint8_t RESERVED_1[4];
52739   __I  uint32_t SP_CPU_REQ;                        /**< CPU SP Request, offset: 0x10 */
52740   __I  uint32_t SP_SYS_STAT;                       /**< SP System Status, offset: 0x14 */
52741        uint8_t RESERVED_2[4];
52742   __IO uint32_t SP_ROSC_CTRL;                      /**< SP ROSC Control, offset: 0x1C */
52743        uint8_t RESERVED_3[32];
52744   __IO uint32_t SP_PRIORITY_0_7;                   /**< SP0~7 Priority, offset: 0x40 */
52745   __IO uint32_t SP_PRIORITY_8_15;                  /**< SP8~15 Priority, offset: 0x44 */
52746        uint8_t RESERVED_4[184];
52747   __IO uint32_t SP_SSAR_SAVE_CTRL;                 /**< SP SSAR save control, offset: 0x100 */
52748        uint8_t RESERVED_5[12];
52749   __IO uint32_t SP_LPCG_OFF_CTRL;                  /**< SP LPCG off control, offset: 0x110 */
52750        uint8_t RESERVED_6[12];
52751   __IO uint32_t SP_GROUP_DOWN_CTRL;                /**< SP group down control, offset: 0x120 */
52752        uint8_t RESERVED_7[12];
52753   __IO uint32_t SP_ROOT_DOWN_CTRL;                 /**< SP root down control, offset: 0x130 */
52754        uint8_t RESERVED_8[12];
52755   __IO uint32_t SP_PLL_OFF_CTRL;                   /**< SP PLL off control, offset: 0x140 */
52756        uint8_t RESERVED_9[12];
52757   __IO uint32_t SP_ISO_ON_CTRL;                    /**< SP ISO on control, offset: 0x150 */
52758        uint8_t RESERVED_10[12];
52759   __IO uint32_t SP_RESET_EARLY_CTRL;               /**< SP reset early control, offset: 0x160 */
52760        uint8_t RESERVED_11[12];
52761   __IO uint32_t SP_POWER_OFF_CTRL;                 /**< SP power off control, offset: 0x170 */
52762        uint8_t RESERVED_12[12];
52763   __IO uint32_t SP_BIAS_OFF_CTRL;                  /**< SP bias off control, offset: 0x180 */
52764        uint8_t RESERVED_13[12];
52765   __IO uint32_t SP_BG_PLDO_OFF_CTRL;               /**< SP bandgap and PLL_LDO off control, offset: 0x190 */
52766        uint8_t RESERVED_14[12];
52767   __IO uint32_t SP_LDO_PRE_CTRL;                   /**< SP LDO pre control, offset: 0x1A0 */
52768        uint8_t RESERVED_15[12];
52769   __IO uint32_t SP_DCDC_DOWN_CTRL;                 /**< SP DCDC down control, offset: 0x1B0 */
52770        uint8_t RESERVED_16[76];
52771   __IO uint32_t SP_DCDC_UP_CTRL;                   /**< SP DCDC up control, offset: 0x200 */
52772        uint8_t RESERVED_17[12];
52773   __IO uint32_t SP_LDO_POST_CTRL;                  /**< SP LDO post control, offset: 0x210 */
52774        uint8_t RESERVED_18[12];
52775   __IO uint32_t SP_BG_PLDO_ON_CTRL;                /**< SP bandgap and PLL_LDO on control, offset: 0x220 */
52776        uint8_t RESERVED_19[12];
52777   __IO uint32_t SP_BIAS_ON_CTRL;                   /**< SP bias on control, offset: 0x230 */
52778        uint8_t RESERVED_20[12];
52779   __IO uint32_t SP_POWER_ON_CTRL;                  /**< SP power on control, offset: 0x240 */
52780        uint8_t RESERVED_21[12];
52781   __IO uint32_t SP_RESET_LATE_CTRL;                /**< SP reset late control, offset: 0x250 */
52782        uint8_t RESERVED_22[12];
52783   __IO uint32_t SP_ISO_OFF_CTRL;                   /**< SP ISO off control, offset: 0x260 */
52784        uint8_t RESERVED_23[12];
52785   __IO uint32_t SP_PLL_ON_CTRL;                    /**< SP PLL on control, offset: 0x270 */
52786        uint8_t RESERVED_24[12];
52787   __IO uint32_t SP_ROOT_UP_CTRL;                   /**< SP root up control, offset: 0x280 */
52788        uint8_t RESERVED_25[12];
52789   __IO uint32_t SP_GROUP_UP_CTRL;                  /**< SP group up control, offset: 0x290 */
52790        uint8_t RESERVED_26[12];
52791   __IO uint32_t SP_LPCG_ON_CTRL;                   /**< SP LPCG on control, offset: 0x2A0 */
52792        uint8_t RESERVED_27[12];
52793   __IO uint32_t SP_SSAR_RESTORE_CTRL;              /**< SP SSAR restore control, offset: 0x2B0 */
52794 } GPC_SET_POINT_CTRL_Type;
52795 
52796 /* ----------------------------------------------------------------------------
52797    -- GPC_SET_POINT_CTRL Register Masks
52798    ---------------------------------------------------------------------------- */
52799 
52800 /*!
52801  * @addtogroup GPC_SET_POINT_CTRL_Register_Masks GPC_SET_POINT_CTRL Register Masks
52802  * @{
52803  */
52804 
52805 /*! @name SP_AUTHEN_CTRL - SP Authentication Control */
52806 /*! @{ */
52807 
52808 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U)
52809 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U)
52810 /*! USER - Allow user mode access
52811  *  0b0..Allow only privilege mode to access setpoint control registers
52812  *  0b1..Allow both privilege and user mode to access setpoint control registers
52813  */
52814 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK)
52815 
52816 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
52817 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
52818 /*! NONSECURE - Allow non-secure mode access
52819  *  0b0..Allow only secure mode to access setpoint control registers
52820  *  0b1..Allow both secure and non-secure mode to access setpoint control registers
52821  */
52822 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK)
52823 
52824 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
52825 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
52826 /*! LOCK_SETTING - Lock NONSECURE and USER
52827  */
52828 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK)
52829 
52830 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
52831 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
52832 /*! WHITE_LIST - Domain ID white list
52833  */
52834 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK)
52835 
52836 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
52837 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
52838 /*! LOCK_LIST - White list lock
52839  */
52840 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK)
52841 
52842 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
52843 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
52844 /*! LOCK_CFG - Configuration lock
52845  */
52846 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK)
52847 /*! @} */
52848 
52849 /*! @name SP_INT_CTRL - SP Interrupt Control */
52850 /*! @{ */
52851 
52852 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U)
52853 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U)
52854 /*! NO_ALLOWED_SP_INT_EN - no_allowed_set_point interrupt enable
52855  */
52856 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK)
52857 
52858 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U)
52859 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U)
52860 /*! NO_ALLOWED_SP_INT - no_allowed_set_point interrupt
52861  */
52862 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK)
52863 /*! @} */
52864 
52865 /*! @name SP_CPU_REQ - CPU SP Request */
52866 /*! @{ */
52867 
52868 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU)
52869 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U)
52870 /*! SP_REQ_CPU0 - Setpoint requested by CPU0
52871  */
52872 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK)
52873 
52874 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U)
52875 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U)
52876 /*! SP_REQ_CPU1 - Setpoint requested by CPU1
52877  */
52878 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK)
52879 
52880 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U)
52881 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U)
52882 /*! SP_REQ_CPU2 - Setpoint requested by CPU2
52883  */
52884 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK)
52885 
52886 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U)
52887 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U)
52888 /*! SP_REQ_CPU3 - Setpoint requested by CPU3
52889  */
52890 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK)
52891 
52892 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U)
52893 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U)
52894 /*! SP_ACCEPTED_CPU0 - CPU0 Setpoint accepted by SP controller
52895  */
52896 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK)
52897 
52898 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U)
52899 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U)
52900 /*! SP_ACCEPTED_CPU1 - CPU1 Setpoint accepted by SP controller
52901  */
52902 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK)
52903 
52904 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U)
52905 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U)
52906 /*! SP_ACCEPTED_CPU2 - CPU2 Setpoint accepted by SP controller
52907  */
52908 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK)
52909 
52910 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U)
52911 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U)
52912 /*! SP_ACCEPTED_CPU3 - CPU3 Setpoint accepted by SP controller
52913  */
52914 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK)
52915 /*! @} */
52916 
52917 /*! @name SP_SYS_STAT - SP System Status */
52918 /*! @{ */
52919 
52920 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU)
52921 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U)
52922 /*! SYS_SP_ALLOWED - Allowed Setpoints by all current CPU Setpoint requests
52923  */
52924 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK)
52925 
52926 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U)
52927 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U)
52928 /*! SYS_SP_TARGET - The Setpoint chosen as the target setpoint
52929  */
52930 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK)
52931 
52932 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U)
52933 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U)
52934 /*! SYS_SP_CURRENT - Current Setpoint, only valid when not SP trans busy
52935  */
52936 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK)
52937 
52938 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U)
52939 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U)
52940 /*! SYS_SP_PREVIOUS - Previous Setpoint, only valid when not SP trans busy
52941  */
52942 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK)
52943 /*! @} */
52944 
52945 /*! @name SP_ROSC_CTRL - SP ROSC Control */
52946 /*! @{ */
52947 
52948 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU)
52949 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U)
52950 /*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC
52951  */
52952 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK)
52953 /*! @} */
52954 
52955 /*! @name SP_PRIORITY_0_7 - SP0~7 Priority */
52956 /*! @{ */
52957 
52958 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU)
52959 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U)
52960 /*! SYS_SP0_PRIORITY - priority of Setpoint 0
52961  */
52962 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK)
52963 
52964 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U)
52965 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U)
52966 /*! SYS_SP1_PRIORITY - priority of Setpoint 1
52967  */
52968 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK)
52969 
52970 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U)
52971 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U)
52972 /*! SYS_SP2_PRIORITY - priority of Setpoint 2
52973  */
52974 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK)
52975 
52976 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U)
52977 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U)
52978 /*! SYS_SP3_PRIORITY - priority of Setpoint 3
52979  */
52980 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK)
52981 
52982 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U)
52983 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U)
52984 /*! SYS_SP4_PRIORITY - priority of Setpoint 4
52985  */
52986 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK)
52987 
52988 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U)
52989 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U)
52990 /*! SYS_SP5_PRIORITY - priority of Setpoint 5
52991  */
52992 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK)
52993 
52994 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U)
52995 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U)
52996 /*! SYS_SP6_PRIORITY - priority of Setpoint 6
52997  */
52998 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK)
52999 
53000 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U)
53001 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U)
53002 /*! SYS_SP7_PRIORITY - priority of Setpoint 7
53003  */
53004 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK)
53005 /*! @} */
53006 
53007 /*! @name SP_PRIORITY_8_15 - SP8~15 Priority */
53008 /*! @{ */
53009 
53010 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU)
53011 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U)
53012 /*! SYS_SP8_PRIORITY - priority of Setpoint 8
53013  */
53014 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK)
53015 
53016 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U)
53017 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U)
53018 /*! SYS_SP9_PRIORITY - priority of Setpoint 9
53019  */
53020 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK)
53021 
53022 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U)
53023 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U)
53024 /*! SYS_SP10_PRIORITY - priority of Setpoint 10
53025  */
53026 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK)
53027 
53028 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U)
53029 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U)
53030 /*! SYS_SP11_PRIORITY - priority of Setpoint 11
53031  */
53032 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK)
53033 
53034 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U)
53035 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U)
53036 /*! SYS_SP12_PRIORITY - priority of Setpoint 12
53037  */
53038 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK)
53039 
53040 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U)
53041 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U)
53042 /*! SYS_SP13_PRIORITY - priority of Setpoint 13
53043  */
53044 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK)
53045 
53046 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U)
53047 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U)
53048 /*! SYS_SP14_PRIORITY - priority of Setpoint 14
53049  */
53050 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK)
53051 
53052 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U)
53053 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U)
53054 /*! SYS_SP15_PRIORITY - priority of Setpoint 15
53055  */
53056 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK)
53057 /*! @} */
53058 
53059 /*! @name SP_SSAR_SAVE_CTRL - SP SSAR save control */
53060 /*! @{ */
53061 
53062 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU)
53063 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U)
53064 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53065  */
53066 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK)
53067 
53068 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U)
53069 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U)
53070 /*! CNT_MODE - Count mode
53071  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53072  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53073  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53074  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53075  */
53076 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK)
53077 
53078 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U)
53079 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U)
53080 /*! DISABLE - Disable this step
53081  */
53082 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK)
53083 /*! @} */
53084 
53085 /*! @name SP_LPCG_OFF_CTRL - SP LPCG off control */
53086 /*! @{ */
53087 
53088 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53089 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U)
53090 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53091  */
53092 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK)
53093 
53094 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53095 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U)
53096 /*! CNT_MODE - Count mode
53097  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53098  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53099  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53100  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53101  */
53102 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK)
53103 
53104 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U)
53105 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U)
53106 /*! DISABLE - Disable this step
53107  */
53108 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK)
53109 /*! @} */
53110 
53111 /*! @name SP_GROUP_DOWN_CTRL - SP group down control */
53112 /*! @{ */
53113 
53114 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53115 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53116 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53117  */
53118 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK)
53119 
53120 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53121 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53122 /*! CNT_MODE - Count mode
53123  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53124  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53125  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53126  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53127  */
53128 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK)
53129 
53130 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53131 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U)
53132 /*! DISABLE - Disable this step
53133  */
53134 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK)
53135 /*! @} */
53136 
53137 /*! @name SP_ROOT_DOWN_CTRL - SP root down control */
53138 /*! @{ */
53139 
53140 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53141 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53142 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53143  */
53144 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK)
53145 
53146 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53147 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53148 /*! CNT_MODE - Count mode
53149  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53150  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53151  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53152  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53153  */
53154 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK)
53155 
53156 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53157 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U)
53158 /*! DISABLE - Disable this step
53159  */
53160 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK)
53161 /*! @} */
53162 
53163 /*! @name SP_PLL_OFF_CTRL - SP PLL off control */
53164 /*! @{ */
53165 
53166 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53167 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U)
53168 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53169  */
53170 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK)
53171 
53172 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53173 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U)
53174 /*! CNT_MODE - Count mode
53175  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53176  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53177  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53178  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53179  */
53180 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK)
53181 
53182 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U)
53183 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U)
53184 /*! DISABLE - Disable this step
53185  */
53186 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK)
53187 /*! @} */
53188 
53189 /*! @name SP_ISO_ON_CTRL - SP ISO on control */
53190 /*! @{ */
53191 
53192 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53193 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U)
53194 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53195  */
53196 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK)
53197 
53198 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53199 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U)
53200 /*! CNT_MODE - Count mode
53201  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53202  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53203  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53204  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53205  */
53206 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK)
53207 
53208 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U)
53209 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U)
53210 /*! DISABLE - Disable this step
53211  */
53212 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK)
53213 /*! @} */
53214 
53215 /*! @name SP_RESET_EARLY_CTRL - SP reset early control */
53216 /*! @{ */
53217 
53218 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU)
53219 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U)
53220 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53221  */
53222 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK)
53223 
53224 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U)
53225 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U)
53226 /*! CNT_MODE - Count mode
53227  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53228  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53229  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53230  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53231  */
53232 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK)
53233 
53234 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U)
53235 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U)
53236 /*! DISABLE - Disable this step
53237  */
53238 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK)
53239 /*! @} */
53240 
53241 /*! @name SP_POWER_OFF_CTRL - SP power off control */
53242 /*! @{ */
53243 
53244 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53245 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U)
53246 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53247  */
53248 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK)
53249 
53250 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53251 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U)
53252 /*! CNT_MODE - Count mode
53253  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53254  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53255  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53256  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53257  */
53258 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK)
53259 
53260 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U)
53261 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U)
53262 /*! DISABLE - Disable this step
53263  */
53264 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK)
53265 /*! @} */
53266 
53267 /*! @name SP_BIAS_OFF_CTRL - SP bias off control */
53268 /*! @{ */
53269 
53270 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53271 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U)
53272 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53273  */
53274 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK)
53275 
53276 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53277 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U)
53278 /*! CNT_MODE - Count mode
53279  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53280  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53281  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53282  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53283  */
53284 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK)
53285 
53286 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U)
53287 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U)
53288 /*! DISABLE - Disable this step
53289  */
53290 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK)
53291 /*! @} */
53292 
53293 /*! @name SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control */
53294 /*! @{ */
53295 
53296 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53297 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U)
53298 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53299  */
53300 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK)
53301 
53302 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53303 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U)
53304 /*! CNT_MODE - Count mode
53305  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53306  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53307  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53308  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53309  */
53310 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK)
53311 
53312 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U)
53313 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U)
53314 /*! DISABLE - Disable this step
53315  */
53316 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK)
53317 /*! @} */
53318 
53319 /*! @name SP_LDO_PRE_CTRL - SP LDO pre control */
53320 /*! @{ */
53321 
53322 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU)
53323 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U)
53324 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53325  */
53326 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK)
53327 
53328 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U)
53329 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U)
53330 /*! CNT_MODE - Count mode
53331  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53332  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53333  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53334  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53335  */
53336 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK)
53337 
53338 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U)
53339 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U)
53340 /*! DISABLE - Disable this step
53341  */
53342 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK)
53343 /*! @} */
53344 
53345 /*! @name SP_DCDC_DOWN_CTRL - SP DCDC down control */
53346 /*! @{ */
53347 
53348 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53349 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53350 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53351  */
53352 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK)
53353 
53354 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53355 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53356 /*! CNT_MODE - Count mode
53357  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53358  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53359  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53360  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53361  */
53362 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK)
53363 
53364 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53365 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U)
53366 /*! DISABLE - Disable this step
53367  */
53368 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK)
53369 /*! @} */
53370 
53371 /*! @name SP_DCDC_UP_CTRL - SP DCDC up control */
53372 /*! @{ */
53373 
53374 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
53375 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U)
53376 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53377  */
53378 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK)
53379 
53380 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U)
53381 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U)
53382 /*! CNT_MODE - Count mode
53383  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53384  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53385  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53386  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53387  */
53388 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK)
53389 
53390 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U)
53391 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U)
53392 /*! DISABLE - Disable this step
53393  */
53394 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK)
53395 /*! @} */
53396 
53397 /*! @name SP_LDO_POST_CTRL - SP LDO post control */
53398 /*! @{ */
53399 
53400 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU)
53401 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U)
53402 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53403  */
53404 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK)
53405 
53406 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U)
53407 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U)
53408 /*! CNT_MODE - Count mode
53409  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53410  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53411  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53412  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53413  */
53414 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK)
53415 
53416 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U)
53417 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U)
53418 /*! DISABLE - Disable this step
53419  */
53420 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK)
53421 /*! @} */
53422 
53423 /*! @name SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control */
53424 /*! @{ */
53425 
53426 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53427 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U)
53428 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53429  */
53430 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK)
53431 
53432 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53433 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U)
53434 /*! CNT_MODE - Count mode
53435  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53436  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53437  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53438  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53439  */
53440 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK)
53441 
53442 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U)
53443 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U)
53444 /*! DISABLE - Disable this step
53445  */
53446 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK)
53447 /*! @} */
53448 
53449 /*! @name SP_BIAS_ON_CTRL - SP bias on control */
53450 /*! @{ */
53451 
53452 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53453 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U)
53454 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53455  */
53456 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK)
53457 
53458 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53459 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U)
53460 /*! CNT_MODE - Count mode
53461  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53462  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53463  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53464  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53465  */
53466 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK)
53467 
53468 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U)
53469 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U)
53470 /*! DISABLE - Disable this step
53471  */
53472 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK)
53473 /*! @} */
53474 
53475 /*! @name SP_POWER_ON_CTRL - SP power on control */
53476 /*! @{ */
53477 
53478 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53479 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U)
53480 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53481  */
53482 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK)
53483 
53484 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53485 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U)
53486 /*! CNT_MODE - Count mode
53487  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53488  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53489  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53490  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53491  */
53492 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK)
53493 
53494 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U)
53495 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U)
53496 /*! DISABLE - Disable this step
53497  */
53498 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK)
53499 /*! @} */
53500 
53501 /*! @name SP_RESET_LATE_CTRL - SP reset late control */
53502 /*! @{ */
53503 
53504 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU)
53505 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U)
53506 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53507  */
53508 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK)
53509 
53510 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U)
53511 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U)
53512 /*! CNT_MODE - Count mode
53513  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53514  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53515  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53516  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53517  */
53518 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK)
53519 
53520 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U)
53521 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U)
53522 /*! DISABLE - Disable this step
53523  */
53524 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK)
53525 /*! @} */
53526 
53527 /*! @name SP_ISO_OFF_CTRL - SP ISO off control */
53528 /*! @{ */
53529 
53530 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53531 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U)
53532 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53533  */
53534 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK)
53535 
53536 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53537 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U)
53538 /*! CNT_MODE - Count mode
53539  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53540  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53541  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53542  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53543  */
53544 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK)
53545 
53546 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U)
53547 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U)
53548 /*! DISABLE - Disable this step
53549  */
53550 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK)
53551 /*! @} */
53552 
53553 /*! @name SP_PLL_ON_CTRL - SP PLL on control */
53554 /*! @{ */
53555 
53556 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53557 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U)
53558 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53559  */
53560 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK)
53561 
53562 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53563 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U)
53564 /*! CNT_MODE - Count mode
53565  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53566  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53567  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53568  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53569  */
53570 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK)
53571 
53572 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U)
53573 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U)
53574 /*! DISABLE - Disable this step
53575  */
53576 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK)
53577 /*! @} */
53578 
53579 /*! @name SP_ROOT_UP_CTRL - SP root up control */
53580 /*! @{ */
53581 
53582 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
53583 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U)
53584 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53585  */
53586 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK)
53587 
53588 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U)
53589 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U)
53590 /*! CNT_MODE - Count mode
53591  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53592  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53593  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53594  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53595  */
53596 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK)
53597 
53598 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U)
53599 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U)
53600 /*! DISABLE - Disable this step
53601  */
53602 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK)
53603 /*! @} */
53604 
53605 /*! @name SP_GROUP_UP_CTRL - SP group up control */
53606 /*! @{ */
53607 
53608 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
53609 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U)
53610 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53611  */
53612 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK)
53613 
53614 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U)
53615 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U)
53616 /*! CNT_MODE - Count mode
53617  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53618  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53619  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53620  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53621  */
53622 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK)
53623 
53624 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U)
53625 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U)
53626 /*! DISABLE - Disable this step
53627  */
53628 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK)
53629 /*! @} */
53630 
53631 /*! @name SP_LPCG_ON_CTRL - SP LPCG on control */
53632 /*! @{ */
53633 
53634 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53635 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U)
53636 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53637  */
53638 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK)
53639 
53640 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53641 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U)
53642 /*! CNT_MODE - Count mode
53643  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53644  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53645  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53646  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53647  */
53648 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK)
53649 
53650 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U)
53651 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U)
53652 /*! DISABLE - Disable this step
53653  */
53654 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK)
53655 /*! @} */
53656 
53657 /*! @name SP_SSAR_RESTORE_CTRL - SP SSAR restore control */
53658 /*! @{ */
53659 
53660 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU)
53661 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U)
53662 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53663  */
53664 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK)
53665 
53666 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U)
53667 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U)
53668 /*! CNT_MODE - Count mode
53669  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53670  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53671  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53672  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53673  */
53674 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK)
53675 
53676 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U)
53677 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U)
53678 /*! DISABLE - Disable this step
53679  */
53680 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK)
53681 /*! @} */
53682 
53683 
53684 /*!
53685  * @}
53686  */ /* end of group GPC_SET_POINT_CTRL_Register_Masks */
53687 
53688 
53689 /* GPC_SET_POINT_CTRL - Peripheral instance base addresses */
53690 /** Peripheral GPC_SET_POINT_CTRL base address */
53691 #define GPC_SET_POINT_CTRL_BASE                  (0x40C02000u)
53692 /** Peripheral GPC_SET_POINT_CTRL base pointer */
53693 #define GPC_SET_POINT_CTRL                       ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
53694 /** Array initializer of GPC_SET_POINT_CTRL peripheral base addresses */
53695 #define GPC_SET_POINT_CTRL_BASE_ADDRS            { GPC_SET_POINT_CTRL_BASE }
53696 /** Array initializer of GPC_SET_POINT_CTRL peripheral base pointers */
53697 #define GPC_SET_POINT_CTRL_BASE_PTRS             { GPC_SET_POINT_CTRL }
53698 
53699 /*!
53700  * @}
53701  */ /* end of group GPC_SET_POINT_CTRL_Peripheral_Access_Layer */
53702 
53703 
53704 /* ----------------------------------------------------------------------------
53705    -- GPC_STBY_CTRL Peripheral Access Layer
53706    ---------------------------------------------------------------------------- */
53707 
53708 /*!
53709  * @addtogroup GPC_STBY_CTRL_Peripheral_Access_Layer GPC_STBY_CTRL Peripheral Access Layer
53710  * @{
53711  */
53712 
53713 /** GPC_STBY_CTRL - Register Layout Typedef */
53714 typedef struct {
53715        uint8_t RESERVED_0[4];
53716   __IO uint32_t STBY_AUTHEN_CTRL;                  /**< Standby Authentication Control, offset: 0x4 */
53717        uint8_t RESERVED_1[4];
53718   __IO uint32_t STBY_MISC;                         /**< STBY Misc, offset: 0xC */
53719        uint8_t RESERVED_2[224];
53720   __IO uint32_t STBY_LPCG_IN_CTRL;                 /**< STBY lpcg_in control, offset: 0xF0 */
53721        uint8_t RESERVED_3[12];
53722   __IO uint32_t STBY_PLL_IN_CTRL;                  /**< STBY pll_in control, offset: 0x100 */
53723        uint8_t RESERVED_4[12];
53724   __IO uint32_t STBY_BIAS_IN_CTRL;                 /**< STBY bias_in control, offset: 0x110 */
53725        uint8_t RESERVED_5[12];
53726   __IO uint32_t STBY_PLDO_IN_CTRL;                 /**< STBY pldo_in control, offset: 0x120 */
53727        uint8_t RESERVED_6[4];
53728   __IO uint32_t STBY_BANDGAP_IN_CTRL;              /**< STBY bandgap_in control, offset: 0x128 */
53729        uint8_t RESERVED_7[4];
53730   __IO uint32_t STBY_LDO_IN_CTRL;                  /**< STBY ldo_in control, offset: 0x130 */
53731        uint8_t RESERVED_8[12];
53732   __IO uint32_t STBY_DCDC_IN_CTRL;                 /**< STBY dcdc_in control, offset: 0x140 */
53733        uint8_t RESERVED_9[12];
53734   __IO uint32_t STBY_PMIC_IN_CTRL;                 /**< STBY PMIC in control, offset: 0x150 */
53735        uint8_t RESERVED_10[172];
53736   __IO uint32_t STBY_PMIC_OUT_CTRL;                /**< STBY PMIC out control, offset: 0x200 */
53737        uint8_t RESERVED_11[12];
53738   __IO uint32_t STBY_DCDC_OUT_CTRL;                /**< STBY DCDC out control, offset: 0x210 */
53739        uint8_t RESERVED_12[12];
53740   __IO uint32_t STBY_LDO_OUT_CTRL;                 /**< STBY LDO out control, offset: 0x220 */
53741        uint8_t RESERVED_13[12];
53742   __IO uint32_t STBY_BANDGAP_OUT_CTRL;             /**< STBY bandgap out control, offset: 0x230 */
53743        uint8_t RESERVED_14[4];
53744   __IO uint32_t STBY_PLDO_OUT_CTRL;                /**< STBY pldo out control, offset: 0x238 */
53745        uint8_t RESERVED_15[4];
53746   __IO uint32_t STBY_BIAS_OUT_CTRL;                /**< STBY bias out control, offset: 0x240 */
53747        uint8_t RESERVED_16[12];
53748   __IO uint32_t STBY_PLL_OUT_CTRL;                 /**< STBY PLL out control, offset: 0x250 */
53749        uint8_t RESERVED_17[12];
53750   __IO uint32_t STBY_LPCG_OUT_CTRL;                /**< STBY LPCG out control, offset: 0x260 */
53751 } GPC_STBY_CTRL_Type;
53752 
53753 /* ----------------------------------------------------------------------------
53754    -- GPC_STBY_CTRL Register Masks
53755    ---------------------------------------------------------------------------- */
53756 
53757 /*!
53758  * @addtogroup GPC_STBY_CTRL_Register_Masks GPC_STBY_CTRL Register Masks
53759  * @{
53760  */
53761 
53762 /*! @name STBY_AUTHEN_CTRL - Standby Authentication Control */
53763 /*! @{ */
53764 
53765 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
53766 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
53767 /*! LOCK_CFG - Configuration lock
53768  */
53769 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK)
53770 /*! @} */
53771 
53772 /*! @name STBY_MISC - STBY Misc */
53773 /*! @{ */
53774 
53775 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U)
53776 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U)
53777 /*! FORCE_CPU0_STBY - Force CPU0 requesting standby mode
53778  */
53779 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK)
53780 
53781 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U)
53782 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U)
53783 /*! FORCE_CPU1_STBY - Force CPU0 requesting standby mode
53784  */
53785 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK)
53786 
53787 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U)
53788 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U)
53789 /*! FORCE_CPU2_STBY - Force CPU2 requesting standby mode
53790  */
53791 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK)
53792 
53793 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U)
53794 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U)
53795 /*! FORCE_CPU3_STBY - Force CPU3 requesting standby mode
53796  */
53797 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK)
53798 /*! @} */
53799 
53800 /*! @name STBY_LPCG_IN_CTRL - STBY lpcg_in control */
53801 /*! @{ */
53802 
53803 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53804 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U)
53805 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53806  */
53807 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK)
53808 
53809 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53810 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U)
53811 /*! CNT_MODE - Count mode
53812  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53813  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53814  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53815  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53816  */
53817 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK)
53818 
53819 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U)
53820 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U)
53821 /*! DISABLE - Disable this step
53822  */
53823 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK)
53824 /*! @} */
53825 
53826 /*! @name STBY_PLL_IN_CTRL - STBY pll_in control */
53827 /*! @{ */
53828 
53829 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53830 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U)
53831 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53832  */
53833 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK)
53834 
53835 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53836 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U)
53837 /*! CNT_MODE - Count mode
53838  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53839  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53840  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53841  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53842  */
53843 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK)
53844 
53845 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U)
53846 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U)
53847 /*! DISABLE - Disable this step
53848  */
53849 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK)
53850 /*! @} */
53851 
53852 /*! @name STBY_BIAS_IN_CTRL - STBY bias_in control */
53853 /*! @{ */
53854 
53855 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53856 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U)
53857 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53858  */
53859 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK)
53860 
53861 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53862 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U)
53863 /*! CNT_MODE - Count mode
53864  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53865  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53866  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53867  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53868  */
53869 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK)
53870 
53871 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U)
53872 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U)
53873 /*! DISABLE - Disable this step
53874  */
53875 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK)
53876 /*! @} */
53877 
53878 /*! @name STBY_PLDO_IN_CTRL - STBY pldo_in control */
53879 /*! @{ */
53880 
53881 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53882 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U)
53883 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53884  */
53885 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK)
53886 
53887 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53888 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U)
53889 /*! CNT_MODE - Count mode
53890  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53891  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53892  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53893  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53894  */
53895 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK)
53896 
53897 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U)
53898 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U)
53899 /*! DISABLE - Disable this step
53900  */
53901 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK)
53902 /*! @} */
53903 
53904 /*! @name STBY_BANDGAP_IN_CTRL - STBY bandgap_in control */
53905 /*! @{ */
53906 
53907 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53908 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U)
53909 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53910  */
53911 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK)
53912 
53913 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53914 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U)
53915 /*! CNT_MODE - Count mode
53916  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53917  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53918  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53919  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53920  */
53921 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK)
53922 
53923 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U)
53924 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U)
53925 /*! DISABLE - Disable this step
53926  */
53927 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK)
53928 /*! @} */
53929 
53930 /*! @name STBY_LDO_IN_CTRL - STBY ldo_in control */
53931 /*! @{ */
53932 
53933 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53934 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U)
53935 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53936  */
53937 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK)
53938 
53939 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53940 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U)
53941 /*! CNT_MODE - Count mode
53942  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53943  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53944  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53945  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53946  */
53947 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK)
53948 
53949 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U)
53950 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U)
53951 /*! DISABLE - Disable this step
53952  */
53953 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK)
53954 /*! @} */
53955 
53956 /*! @name STBY_DCDC_IN_CTRL - STBY dcdc_in control */
53957 /*! @{ */
53958 
53959 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53960 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U)
53961 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53962  */
53963 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK)
53964 
53965 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53966 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U)
53967 /*! CNT_MODE - Count mode
53968  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53969  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53970  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53971  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53972  */
53973 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK)
53974 
53975 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
53976 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
53977 /*! DISABLE - Disable this step
53978  */
53979 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK)
53980 /*! @} */
53981 
53982 /*! @name STBY_PMIC_IN_CTRL - STBY PMIC in control */
53983 /*! @{ */
53984 
53985 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
53986 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U)
53987 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53988  */
53989 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK)
53990 
53991 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
53992 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U)
53993 /*! CNT_MODE - Count mode
53994  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53995  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53996  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53997  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53998  */
53999 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK)
54000 
54001 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
54002 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
54003 /*! DISABLE - Disable this step
54004  */
54005 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK)
54006 /*! @} */
54007 
54008 /*! @name STBY_PMIC_OUT_CTRL - STBY PMIC out control */
54009 /*! @{ */
54010 
54011 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54012 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U)
54013 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54014  */
54015 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK)
54016 
54017 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54018 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U)
54019 /*! CNT_MODE - Count mode
54020  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54021  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54022  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54023  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54024  */
54025 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK)
54026 
54027 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
54028 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
54029 /*! DISABLE - Disable this step
54030  */
54031 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK)
54032 /*! @} */
54033 
54034 /*! @name STBY_DCDC_OUT_CTRL - STBY DCDC out control */
54035 /*! @{ */
54036 
54037 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54038 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U)
54039 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54040  */
54041 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK)
54042 
54043 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54044 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U)
54045 /*! CNT_MODE - Count mode
54046  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54047  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54048  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54049  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54050  */
54051 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK)
54052 
54053 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
54054 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
54055 /*! DISABLE - Disable this step
54056  */
54057 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK)
54058 /*! @} */
54059 
54060 /*! @name STBY_LDO_OUT_CTRL - STBY LDO out control */
54061 /*! @{ */
54062 
54063 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54064 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
54065 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54066  */
54067 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK)
54068 
54069 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54070 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
54071 /*! CNT_MODE - Count mode
54072  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54073  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54074  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54075  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54076  */
54077 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK)
54078 
54079 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
54080 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U)
54081 /*! DISABLE - Disable this step
54082  */
54083 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK)
54084 /*! @} */
54085 
54086 /*! @name STBY_BANDGAP_OUT_CTRL - STBY bandgap out control */
54087 /*! @{ */
54088 
54089 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54090 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U)
54091 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54092  */
54093 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK)
54094 
54095 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54096 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U)
54097 /*! CNT_MODE - Count mode
54098  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54099  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54100  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54101  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54102  */
54103 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK)
54104 
54105 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U)
54106 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U)
54107 /*! DISABLE - Disable this step
54108  */
54109 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK)
54110 /*! @} */
54111 
54112 /*! @name STBY_PLDO_OUT_CTRL - STBY pldo out control */
54113 /*! @{ */
54114 
54115 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54116 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
54117 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54118  */
54119 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK)
54120 
54121 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54122 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
54123 /*! CNT_MODE - Count mode
54124  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54125  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54126  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54127  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54128  */
54129 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK)
54130 
54131 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
54132 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U)
54133 /*! DISABLE - Disable this step
54134  */
54135 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK)
54136 /*! @} */
54137 
54138 /*! @name STBY_BIAS_OUT_CTRL - STBY bias out control */
54139 /*! @{ */
54140 
54141 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54142 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U)
54143 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54144  */
54145 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK)
54146 
54147 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54148 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U)
54149 /*! CNT_MODE - Count mode
54150  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54151  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54152  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54153  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54154  */
54155 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK)
54156 
54157 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U)
54158 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U)
54159 /*! DISABLE - Disable this step
54160  */
54161 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK)
54162 /*! @} */
54163 
54164 /*! @name STBY_PLL_OUT_CTRL - STBY PLL out control */
54165 /*! @{ */
54166 
54167 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54168 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U)
54169 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54170  */
54171 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK)
54172 
54173 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54174 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U)
54175 /*! CNT_MODE - Count mode
54176  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54177  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54178  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54179  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54180  */
54181 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK)
54182 
54183 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U)
54184 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U)
54185 /*! DISABLE - Disable this step
54186  */
54187 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK)
54188 /*! @} */
54189 
54190 /*! @name STBY_LPCG_OUT_CTRL - STBY LPCG out control */
54191 /*! @{ */
54192 
54193 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54194 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U)
54195 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54196  */
54197 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK)
54198 
54199 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54200 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U)
54201 /*! CNT_MODE - Count mode
54202  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54203  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54204  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54205  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54206  */
54207 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK)
54208 
54209 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U)
54210 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U)
54211 /*! DISABLE - Disable this step
54212  */
54213 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK)
54214 /*! @} */
54215 
54216 
54217 /*!
54218  * @}
54219  */ /* end of group GPC_STBY_CTRL_Register_Masks */
54220 
54221 
54222 /* GPC_STBY_CTRL - Peripheral instance base addresses */
54223 /** Peripheral GPC_STBY_CTRL base address */
54224 #define GPC_STBY_CTRL_BASE                       (0x40C02800u)
54225 /** Peripheral GPC_STBY_CTRL base pointer */
54226 #define GPC_STBY_CTRL                            ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
54227 /** Array initializer of GPC_STBY_CTRL peripheral base addresses */
54228 #define GPC_STBY_CTRL_BASE_ADDRS                 { GPC_STBY_CTRL_BASE }
54229 /** Array initializer of GPC_STBY_CTRL peripheral base pointers */
54230 #define GPC_STBY_CTRL_BASE_PTRS                  { GPC_STBY_CTRL }
54231 
54232 /*!
54233  * @}
54234  */ /* end of group GPC_STBY_CTRL_Peripheral_Access_Layer */
54235 
54236 
54237 /* ----------------------------------------------------------------------------
54238    -- GPIO Peripheral Access Layer
54239    ---------------------------------------------------------------------------- */
54240 
54241 /*!
54242  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
54243  * @{
54244  */
54245 
54246 /** GPIO - Register Layout Typedef */
54247 typedef struct {
54248   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
54249   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
54250   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
54251   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
54252   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
54253   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
54254   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
54255   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
54256        uint8_t RESERVED_0[100];
54257   __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
54258   __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
54259   __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
54260 } GPIO_Type;
54261 
54262 /* ----------------------------------------------------------------------------
54263    -- GPIO Register Masks
54264    ---------------------------------------------------------------------------- */
54265 
54266 /*!
54267  * @addtogroup GPIO_Register_Masks GPIO Register Masks
54268  * @{
54269  */
54270 
54271 /*! @name DR - GPIO data register */
54272 /*! @{ */
54273 
54274 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
54275 #define GPIO_DR_DR_SHIFT                         (0U)
54276 /*! DR - DR data bits
54277  */
54278 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
54279 /*! @} */
54280 
54281 /*! @name GDIR - GPIO direction register */
54282 /*! @{ */
54283 
54284 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
54285 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
54286 /*! GDIR - GPIO direction bits
54287  */
54288 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
54289 /*! @} */
54290 
54291 /*! @name PSR - GPIO pad status register */
54292 /*! @{ */
54293 
54294 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
54295 #define GPIO_PSR_PSR_SHIFT                       (0U)
54296 /*! PSR - GPIO pad status bits
54297  */
54298 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
54299 /*! @} */
54300 
54301 /*! @name ICR1 - GPIO interrupt configuration register1 */
54302 /*! @{ */
54303 
54304 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
54305 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
54306 /*! ICR0 - Interrupt configuration field for GPIO interrupt 0
54307  *  0b00..Interrupt 0 is low-level sensitive.
54308  *  0b01..Interrupt 0 is high-level sensitive.
54309  *  0b10..Interrupt 0 is rising-edge sensitive.
54310  *  0b11..Interrupt 0 is falling-edge sensitive.
54311  */
54312 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
54313 
54314 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
54315 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
54316 /*! ICR1 - Interrupt configuration field for GPIO interrupt 1
54317  *  0b00..Interrupt 1 is low-level sensitive.
54318  *  0b01..Interrupt 1 is high-level sensitive.
54319  *  0b10..Interrupt 1 is rising-edge sensitive.
54320  *  0b11..Interrupt 1 is falling-edge sensitive.
54321  */
54322 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
54323 
54324 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
54325 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
54326 /*! ICR2 - Interrupt configuration field for GPIO interrupt 2
54327  *  0b00..Interrupt 2 is low-level sensitive.
54328  *  0b01..Interrupt 2 is high-level sensitive.
54329  *  0b10..Interrupt 2 is rising-edge sensitive.
54330  *  0b11..Interrupt 2 is falling-edge sensitive.
54331  */
54332 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
54333 
54334 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
54335 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
54336 /*! ICR3 - Interrupt configuration field for GPIO interrupt 3
54337  *  0b00..Interrupt 3 is low-level sensitive.
54338  *  0b01..Interrupt 3 is high-level sensitive.
54339  *  0b10..Interrupt 3 is rising-edge sensitive.
54340  *  0b11..Interrupt 3 is falling-edge sensitive.
54341  */
54342 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
54343 
54344 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
54345 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
54346 /*! ICR4 - Interrupt configuration field for GPIO interrupt 4
54347  *  0b00..Interrupt 4 is low-level sensitive.
54348  *  0b01..Interrupt 4 is high-level sensitive.
54349  *  0b10..Interrupt 4 is rising-edge sensitive.
54350  *  0b11..Interrupt 4 is falling-edge sensitive.
54351  */
54352 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
54353 
54354 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
54355 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
54356 /*! ICR5 - Interrupt configuration field for GPIO interrupt 5
54357  *  0b00..Interrupt 5 is low-level sensitive.
54358  *  0b01..Interrupt 5 is high-level sensitive.
54359  *  0b10..Interrupt 5 is rising-edge sensitive.
54360  *  0b11..Interrupt 5 is falling-edge sensitive.
54361  */
54362 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
54363 
54364 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
54365 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
54366 /*! ICR6 - Interrupt configuration field for GPIO interrupt 6
54367  *  0b00..Interrupt 6 is low-level sensitive.
54368  *  0b01..Interrupt 6 is high-level sensitive.
54369  *  0b10..Interrupt 6 is rising-edge sensitive.
54370  *  0b11..Interrupt 6 is falling-edge sensitive.
54371  */
54372 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
54373 
54374 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
54375 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
54376 /*! ICR7 - Interrupt configuration field for GPIO interrupt 7
54377  *  0b00..Interrupt 7 is low-level sensitive.
54378  *  0b01..Interrupt 7 is high-level sensitive.
54379  *  0b10..Interrupt 7 is rising-edge sensitive.
54380  *  0b11..Interrupt 7 is falling-edge sensitive.
54381  */
54382 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
54383 
54384 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
54385 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
54386 /*! ICR8 - Interrupt configuration field for GPIO interrupt 8
54387  *  0b00..Interrupt 8 is low-level sensitive.
54388  *  0b01..Interrupt 8 is high-level sensitive.
54389  *  0b10..Interrupt 8 is rising-edge sensitive.
54390  *  0b11..Interrupt 8 is falling-edge sensitive.
54391  */
54392 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
54393 
54394 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
54395 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
54396 /*! ICR9 - Interrupt configuration field for GPIO interrupt 9
54397  *  0b00..Interrupt 9 is low-level sensitive.
54398  *  0b01..Interrupt 9 is high-level sensitive.
54399  *  0b10..Interrupt 9 is rising-edge sensitive.
54400  *  0b11..Interrupt 9 is falling-edge sensitive.
54401  */
54402 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
54403 
54404 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
54405 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
54406 /*! ICR10 - Interrupt configuration field for GPIO interrupt 10
54407  *  0b00..Interrupt 10 is low-level sensitive.
54408  *  0b01..Interrupt 10 is high-level sensitive.
54409  *  0b10..Interrupt 10 is rising-edge sensitive.
54410  *  0b11..Interrupt 10 is falling-edge sensitive.
54411  */
54412 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
54413 
54414 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
54415 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
54416 /*! ICR11 - Interrupt configuration field for GPIO interrupt 11
54417  *  0b00..Interrupt 11 is low-level sensitive.
54418  *  0b01..Interrupt 11 is high-level sensitive.
54419  *  0b10..Interrupt 11 is rising-edge sensitive.
54420  *  0b11..Interrupt 11 is falling-edge sensitive.
54421  */
54422 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
54423 
54424 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
54425 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
54426 /*! ICR12 - Interrupt configuration field for GPIO interrupt 12
54427  *  0b00..Interrupt 12 is low-level sensitive.
54428  *  0b01..Interrupt 12 is high-level sensitive.
54429  *  0b10..Interrupt 12 is rising-edge sensitive.
54430  *  0b11..Interrupt 12 is falling-edge sensitive.
54431  */
54432 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
54433 
54434 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
54435 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
54436 /*! ICR13 - Interrupt configuration field for GPIO interrupt 13
54437  *  0b00..Interrupt 13 is low-level sensitive.
54438  *  0b01..Interrupt 13 is high-level sensitive.
54439  *  0b10..Interrupt 13 is rising-edge sensitive.
54440  *  0b11..Interrupt 13 is falling-edge sensitive.
54441  */
54442 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
54443 
54444 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
54445 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
54446 /*! ICR14 - Interrupt configuration field for GPIO interrupt 14
54447  *  0b00..Interrupt 14 is low-level sensitive.
54448  *  0b01..Interrupt 14 is high-level sensitive.
54449  *  0b10..Interrupt 14 is rising-edge sensitive.
54450  *  0b11..Interrupt 14 is falling-edge sensitive.
54451  */
54452 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
54453 
54454 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
54455 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
54456 /*! ICR15 - Interrupt configuration field for GPIO interrupt 15
54457  *  0b00..Interrupt 15 is low-level sensitive.
54458  *  0b01..Interrupt 15 is high-level sensitive.
54459  *  0b10..Interrupt 15 is rising-edge sensitive.
54460  *  0b11..Interrupt 15 is falling-edge sensitive.
54461  */
54462 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
54463 /*! @} */
54464 
54465 /*! @name ICR2 - GPIO interrupt configuration register2 */
54466 /*! @{ */
54467 
54468 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
54469 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
54470 /*! ICR16 - Interrupt configuration field for GPIO interrupt 16
54471  *  0b00..Interrupt 16 is low-level sensitive.
54472  *  0b01..Interrupt 16 is high-level sensitive.
54473  *  0b10..Interrupt 16 is rising-edge sensitive.
54474  *  0b11..Interrupt 16 is falling-edge sensitive.
54475  */
54476 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
54477 
54478 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
54479 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
54480 /*! ICR17 - Interrupt configuration field for GPIO interrupt 17
54481  *  0b00..Interrupt 17 is low-level sensitive.
54482  *  0b01..Interrupt 17 is high-level sensitive.
54483  *  0b10..Interrupt 17 is rising-edge sensitive.
54484  *  0b11..Interrupt 17 is falling-edge sensitive.
54485  */
54486 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
54487 
54488 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
54489 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
54490 /*! ICR18 - Interrupt configuration field for GPIO interrupt 18
54491  *  0b00..Interrupt 18 is low-level sensitive.
54492  *  0b01..Interrupt 18 is high-level sensitive.
54493  *  0b10..Interrupt 18 is rising-edge sensitive.
54494  *  0b11..Interrupt 18 is falling-edge sensitive.
54495  */
54496 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
54497 
54498 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
54499 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
54500 /*! ICR19 - Interrupt configuration field for GPIO interrupt 19
54501  *  0b00..Interrupt 19 is low-level sensitive.
54502  *  0b01..Interrupt 19 is high-level sensitive.
54503  *  0b10..Interrupt 19 is rising-edge sensitive.
54504  *  0b11..Interrupt 19 is falling-edge sensitive.
54505  */
54506 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
54507 
54508 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
54509 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
54510 /*! ICR20 - Interrupt configuration field for GPIO interrupt 20
54511  *  0b00..Interrupt 20 is low-level sensitive.
54512  *  0b01..Interrupt 20 is high-level sensitive.
54513  *  0b10..Interrupt 20 is rising-edge sensitive.
54514  *  0b11..Interrupt 20 is falling-edge sensitive.
54515  */
54516 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
54517 
54518 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
54519 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
54520 /*! ICR21 - Interrupt configuration field for GPIO interrupt 21
54521  *  0b00..Interrupt 21 is low-level sensitive.
54522  *  0b01..Interrupt 21 is high-level sensitive.
54523  *  0b10..Interrupt 21 is rising-edge sensitive.
54524  *  0b11..Interrupt 21 is falling-edge sensitive.
54525  */
54526 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
54527 
54528 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
54529 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
54530 /*! ICR22 - Interrupt configuration field for GPIO interrupt 22
54531  *  0b00..Interrupt 22 is low-level sensitive.
54532  *  0b01..Interrupt 22 is high-level sensitive.
54533  *  0b10..Interrupt 22 is rising-edge sensitive.
54534  *  0b11..Interrupt 22 is falling-edge sensitive.
54535  */
54536 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
54537 
54538 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
54539 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
54540 /*! ICR23 - Interrupt configuration field for GPIO interrupt 23
54541  *  0b00..Interrupt 23 is low-level sensitive.
54542  *  0b01..Interrupt 23 is high-level sensitive.
54543  *  0b10..Interrupt 23 is rising-edge sensitive.
54544  *  0b11..Interrupt 23 is falling-edge sensitive.
54545  */
54546 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
54547 
54548 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
54549 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
54550 /*! ICR24 - Interrupt configuration field for GPIO interrupt 24
54551  *  0b00..Interrupt 24 is low-level sensitive.
54552  *  0b01..Interrupt 24 is high-level sensitive.
54553  *  0b10..Interrupt 24 is rising-edge sensitive.
54554  *  0b11..Interrupt 24 is falling-edge sensitive.
54555  */
54556 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
54557 
54558 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
54559 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
54560 /*! ICR25 - Interrupt configuration field for GPIO interrupt 25
54561  *  0b00..Interrupt 25 is low-level sensitive.
54562  *  0b01..Interrupt 25 is high-level sensitive.
54563  *  0b10..Interrupt 25 is rising-edge sensitive.
54564  *  0b11..Interrupt 25 is falling-edge sensitive.
54565  */
54566 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
54567 
54568 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
54569 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
54570 /*! ICR26 - Interrupt configuration field for GPIO interrupt 26
54571  *  0b00..Interrupt 26 is low-level sensitive.
54572  *  0b01..Interrupt 26 is high-level sensitive.
54573  *  0b10..Interrupt 26 is rising-edge sensitive.
54574  *  0b11..Interrupt 26 is falling-edge sensitive.
54575  */
54576 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
54577 
54578 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
54579 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
54580 /*! ICR27 - Interrupt configuration field for GPIO interrupt 27
54581  *  0b00..Interrupt 27 is low-level sensitive.
54582  *  0b01..Interrupt 27 is high-level sensitive.
54583  *  0b10..Interrupt 27 is rising-edge sensitive.
54584  *  0b11..Interrupt 27 is falling-edge sensitive.
54585  */
54586 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
54587 
54588 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
54589 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
54590 /*! ICR28 - Interrupt configuration field for GPIO interrupt 28
54591  *  0b00..Interrupt 28 is low-level sensitive.
54592  *  0b01..Interrupt 28 is high-level sensitive.
54593  *  0b10..Interrupt 28 is rising-edge sensitive.
54594  *  0b11..Interrupt 28 is falling-edge sensitive.
54595  */
54596 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
54597 
54598 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
54599 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
54600 /*! ICR29 - Interrupt configuration field for GPIO interrupt 29
54601  *  0b00..Interrupt 29 is low-level sensitive.
54602  *  0b01..Interrupt 29 is high-level sensitive.
54603  *  0b10..Interrupt 29 is rising-edge sensitive.
54604  *  0b11..Interrupt 29 is falling-edge sensitive.
54605  */
54606 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
54607 
54608 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
54609 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
54610 /*! ICR30 - Interrupt configuration field for GPIO interrupt 30
54611  *  0b00..Interrupt 30 is low-level sensitive.
54612  *  0b01..Interrupt 30 is high-level sensitive.
54613  *  0b10..Interrupt 30 is rising-edge sensitive.
54614  *  0b11..Interrupt 30 is falling-edge sensitive.
54615  */
54616 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
54617 
54618 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
54619 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
54620 /*! ICR31 - Interrupt configuration field for GPIO interrupt 31
54621  *  0b00..Interrupt 31 is low-level sensitive.
54622  *  0b01..Interrupt 31 is high-level sensitive.
54623  *  0b10..Interrupt 31 is rising-edge sensitive.
54624  *  0b11..Interrupt 31 is falling-edge sensitive.
54625  */
54626 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
54627 /*! @} */
54628 
54629 /*! @name IMR - GPIO interrupt mask register */
54630 /*! @{ */
54631 
54632 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
54633 #define GPIO_IMR_IMR_SHIFT                       (0U)
54634 /*! IMR - Interrupt Mask bits
54635  */
54636 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
54637 /*! @} */
54638 
54639 /*! @name ISR - GPIO interrupt status register */
54640 /*! @{ */
54641 
54642 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
54643 #define GPIO_ISR_ISR_SHIFT                       (0U)
54644 /*! ISR - Interrupt status bits
54645  */
54646 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
54647 /*! @} */
54648 
54649 /*! @name EDGE_SEL - GPIO edge select register */
54650 /*! @{ */
54651 
54652 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
54653 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
54654 /*! GPIO_EDGE_SEL - Edge select
54655  */
54656 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
54657 /*! @} */
54658 
54659 /*! @name DR_SET - GPIO data register SET */
54660 /*! @{ */
54661 
54662 #define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
54663 #define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
54664 /*! DR_SET - Set
54665  */
54666 #define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
54667 /*! @} */
54668 
54669 /*! @name DR_CLEAR - GPIO data register CLEAR */
54670 /*! @{ */
54671 
54672 #define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
54673 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
54674 /*! DR_CLEAR - Clear
54675  */
54676 #define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
54677 /*! @} */
54678 
54679 /*! @name DR_TOGGLE - GPIO data register TOGGLE */
54680 /*! @{ */
54681 
54682 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
54683 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
54684 /*! DR_TOGGLE - Toggle
54685  */
54686 #define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
54687 /*! @} */
54688 
54689 
54690 /*!
54691  * @}
54692  */ /* end of group GPIO_Register_Masks */
54693 
54694 
54695 /* GPIO - Peripheral instance base addresses */
54696 /** Peripheral GPIO1 base address */
54697 #define GPIO1_BASE                               (0x4012C000u)
54698 /** Peripheral GPIO1 base pointer */
54699 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
54700 /** Peripheral GPIO2 base address */
54701 #define GPIO2_BASE                               (0x40130000u)
54702 /** Peripheral GPIO2 base pointer */
54703 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
54704 /** Peripheral GPIO3 base address */
54705 #define GPIO3_BASE                               (0x40134000u)
54706 /** Peripheral GPIO3 base pointer */
54707 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
54708 /** Peripheral GPIO4 base address */
54709 #define GPIO4_BASE                               (0x40138000u)
54710 /** Peripheral GPIO4 base pointer */
54711 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
54712 /** Peripheral GPIO5 base address */
54713 #define GPIO5_BASE                               (0x4013C000u)
54714 /** Peripheral GPIO5 base pointer */
54715 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
54716 /** Peripheral GPIO6 base address */
54717 #define GPIO6_BASE                               (0x40140000u)
54718 /** Peripheral GPIO6 base pointer */
54719 #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
54720 /** Peripheral GPIO7 base address */
54721 #define GPIO7_BASE                               (0x40C5C000u)
54722 /** Peripheral GPIO7 base pointer */
54723 #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
54724 /** Peripheral GPIO8 base address */
54725 #define GPIO8_BASE                               (0x40C60000u)
54726 /** Peripheral GPIO8 base pointer */
54727 #define GPIO8                                    ((GPIO_Type *)GPIO8_BASE)
54728 /** Peripheral GPIO9 base address */
54729 #define GPIO9_BASE                               (0x40C64000u)
54730 /** Peripheral GPIO9 base pointer */
54731 #define GPIO9                                    ((GPIO_Type *)GPIO9_BASE)
54732 /** Peripheral GPIO10 base address */
54733 #define GPIO10_BASE                              (0x40C68000u)
54734 /** Peripheral GPIO10 base pointer */
54735 #define GPIO10                                   ((GPIO_Type *)GPIO10_BASE)
54736 /** Peripheral GPIO11 base address */
54737 #define GPIO11_BASE                              (0x40C6C000u)
54738 /** Peripheral GPIO11 base pointer */
54739 #define GPIO11                                   ((GPIO_Type *)GPIO11_BASE)
54740 /** Peripheral GPIO12 base address */
54741 #define GPIO12_BASE                              (0x40C70000u)
54742 /** Peripheral GPIO12 base pointer */
54743 #define GPIO12                                   ((GPIO_Type *)GPIO12_BASE)
54744 /** Peripheral GPIO13 base address */
54745 #define GPIO13_BASE                              (0x40CA0000u)
54746 /** Peripheral GPIO13 base pointer */
54747 #define GPIO13                                   ((GPIO_Type *)GPIO13_BASE)
54748 /** Peripheral CM7_GPIO2 base address */
54749 #define CM7_GPIO2_BASE                           (0x42008000u)
54750 /** Peripheral CM7_GPIO2 base pointer */
54751 #define CM7_GPIO2                                ((GPIO_Type *)CM7_GPIO2_BASE)
54752 /** Peripheral CM7_GPIO3 base address */
54753 #define CM7_GPIO3_BASE                           (0x4200C000u)
54754 /** Peripheral CM7_GPIO3 base pointer */
54755 #define CM7_GPIO3                                ((GPIO_Type *)CM7_GPIO3_BASE)
54756 /** Array initializer of GPIO peripheral base addresses */
54757 #define GPIO_BASE_ADDRS                          { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
54758 /** Array initializer of GPIO peripheral base pointers */
54759 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
54760 /** Interrupt vectors for the GPIO peripheral type */
54761 #define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_0_15_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn }
54762 #define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_16_31_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn }
54763 
54764 /*!
54765  * @}
54766  */ /* end of group GPIO_Peripheral_Access_Layer */
54767 
54768 
54769 /* ----------------------------------------------------------------------------
54770    -- GPT Peripheral Access Layer
54771    ---------------------------------------------------------------------------- */
54772 
54773 /*!
54774  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
54775  * @{
54776  */
54777 
54778 /** GPT - Register Layout Typedef */
54779 typedef struct {
54780   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
54781   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
54782   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
54783   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
54784   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register, array offset: 0x10, array step: 0x4 */
54785   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register, array offset: 0x1C, array step: 0x4 */
54786   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
54787 } GPT_Type;
54788 
54789 /* ----------------------------------------------------------------------------
54790    -- GPT Register Masks
54791    ---------------------------------------------------------------------------- */
54792 
54793 /*!
54794  * @addtogroup GPT_Register_Masks GPT Register Masks
54795  * @{
54796  */
54797 
54798 /*! @name CR - GPT Control Register */
54799 /*! @{ */
54800 
54801 #define GPT_CR_EN_MASK                           (0x1U)
54802 #define GPT_CR_EN_SHIFT                          (0U)
54803 /*! EN - GPT Enable
54804  *  0b0..Disable
54805  *  0b1..Enable
54806  */
54807 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
54808 
54809 #define GPT_CR_ENMOD_MASK                        (0x2U)
54810 #define GPT_CR_ENMOD_SHIFT                       (1U)
54811 /*! ENMOD - GPT Enable Mode
54812  *  0b0..Restart counting from their frozen values after GPT is enabled (EN=1).
54813  *  0b1..Reset counting from 0 after GPT is enabled (EN=1).
54814  */
54815 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
54816 
54817 #define GPT_CR_DBGEN_MASK                        (0x4U)
54818 #define GPT_CR_DBGEN_SHIFT                       (2U)
54819 /*! DBGEN - GPT Debug Mode Enable
54820  *  0b0..Disable in Debug mode
54821  *  0b1..Enable in Debug mode
54822  */
54823 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
54824 
54825 #define GPT_CR_WAITEN_MASK                       (0x8U)
54826 #define GPT_CR_WAITEN_SHIFT                      (3U)
54827 /*! WAITEN - GPT Wait Mode Enable
54828  *  0b0..Disable in Wait mode
54829  *  0b1..Enable in Wait mode
54830  */
54831 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
54832 
54833 #define GPT_CR_DOZEEN_MASK                       (0x10U)
54834 #define GPT_CR_DOZEEN_SHIFT                      (4U)
54835 /*! DOZEEN - GPT Doze Mode Enable
54836  *  0b0..Disable in Doze mode
54837  *  0b1..Enable in Doze mode
54838  */
54839 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
54840 
54841 #define GPT_CR_STOPEN_MASK                       (0x20U)
54842 #define GPT_CR_STOPEN_SHIFT                      (5U)
54843 /*! STOPEN - GPT Stop Mode Enable
54844  *  0b0..Disable in Stop mode
54845  *  0b1..Enable in Stop mode
54846  */
54847 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
54848 
54849 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
54850 #define GPT_CR_CLKSRC_SHIFT                      (6U)
54851 /*! CLKSRC - Clock Source Select
54852  *  0b000..No clock
54853  *  0b001..Peripheral Clock (ipg_clk)
54854  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
54855  *  0b011..External Clock
54856  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
54857  *  0b101..Oscillator as Reference Clock (ipg_clk_16M)
54858  */
54859 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
54860 
54861 #define GPT_CR_FRR_MASK                          (0x200U)
54862 #define GPT_CR_FRR_SHIFT                         (9U)
54863 /*! FRR - Free-Run or Restart Mode
54864  *  0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting.
54865  *  0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.
54866  */
54867 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
54868 
54869 #define GPT_CR_EN_24M_MASK                       (0x400U)
54870 #define GPT_CR_EN_24M_SHIFT                      (10U)
54871 /*! EN_24M - Enable Oscillator Clock Input
54872  *  0b0..Disable
54873  *  0b1..Enable
54874  */
54875 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
54876 
54877 #define GPT_CR_SWR_MASK                          (0x8000U)
54878 #define GPT_CR_SWR_SHIFT                         (15U)
54879 /*! SWR - Software Reset
54880  *  0b0..GPT is not in software reset state
54881  *  0b1..GPT is in software reset state
54882  */
54883 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
54884 
54885 #define GPT_CR_IM1_MASK                          (0x30000U)
54886 #define GPT_CR_IM1_SHIFT                         (16U)
54887 /*! IM1 - Input Capture Operating Mode for Channel 1
54888  *  0b00..Capture disabled
54889  *  0b01..Capture on rising edge only
54890  *  0b10..Capture on falling edge only
54891  *  0b11..Capture on both edges
54892  */
54893 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
54894 
54895 #define GPT_CR_IM2_MASK                          (0xC0000U)
54896 #define GPT_CR_IM2_SHIFT                         (18U)
54897 /*! IM2 - Input Capture Operating Mode for Channel 2
54898  *  0b00..Capture disabled
54899  *  0b01..Capture on rising edge only
54900  *  0b10..Capture on falling edge only
54901  *  0b11..Capture on both edges
54902  */
54903 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
54904 
54905 #define GPT_CR_OM1_MASK                          (0x700000U)
54906 #define GPT_CR_OM1_SHIFT                         (20U)
54907 /*! OM1 - Output Compare Operating Mode for Channel 1
54908  *  0b000..Output disabled. No response on pin.
54909  *  0b001..Toggle output pin
54910  *  0b010..Clear output pin
54911  *  0b011..Set output pin
54912  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
54913  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
54914  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
54915  */
54916 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
54917 
54918 #define GPT_CR_OM2_MASK                          (0x3800000U)
54919 #define GPT_CR_OM2_SHIFT                         (23U)
54920 /*! OM2 - Output Compare Operating Mode for Channel 2
54921  *  0b000..Output disabled. No response on pin.
54922  *  0b001..Toggle output pin
54923  *  0b010..Clear output pin
54924  *  0b011..Set output pin
54925  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
54926  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
54927  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
54928  */
54929 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
54930 
54931 #define GPT_CR_OM3_MASK                          (0x1C000000U)
54932 #define GPT_CR_OM3_SHIFT                         (26U)
54933 /*! OM3 - Output Compare Operating Mode for Channel 3
54934  *  0b000..Output disabled. No response on pin.
54935  *  0b001..Toggle output pin
54936  *  0b010..Clear output pin
54937  *  0b011..Set output pin
54938  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
54939  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
54940  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
54941  */
54942 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
54943 
54944 #define GPT_CR_FO1_MASK                          (0x20000000U)
54945 #define GPT_CR_FO1_SHIFT                         (29U)
54946 /*! FO1 - Force Output Compare for Channel 1
54947  *  0b0..No effect
54948  *  0b1..Trigger the programmed response on the pin
54949  */
54950 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
54951 
54952 #define GPT_CR_FO2_MASK                          (0x40000000U)
54953 #define GPT_CR_FO2_SHIFT                         (30U)
54954 /*! FO2 - Force Output Compare for Channel 2
54955  *  0b0..No effect
54956  *  0b1..Trigger the programmed response on the pin
54957  */
54958 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
54959 
54960 #define GPT_CR_FO3_MASK                          (0x80000000U)
54961 #define GPT_CR_FO3_SHIFT                         (31U)
54962 /*! FO3 - Force Output Compare for Channel 3
54963  *  0b0..No effect
54964  *  0b1..Trigger the programmed response on the pin
54965  */
54966 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
54967 /*! @} */
54968 
54969 /*! @name PR - GPT Prescaler Register */
54970 /*! @{ */
54971 
54972 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
54973 #define GPT_PR_PRESCALER_SHIFT                   (0U)
54974 /*! PRESCALER - Prescaler divide value
54975  *  0b000000000000..Divide by 1
54976  *  0b000000000001..Divide by 2
54977  *  0b111111111111..Divide by 4096
54978  */
54979 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
54980 
54981 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
54982 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
54983 /*! PRESCALER24M - Prescaler divide value for the oscillator clock
54984  *  0b0000..Divide by 1
54985  *  0b0001..Divide by 2
54986  *  0b1111..Divide by 16
54987  */
54988 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
54989 /*! @} */
54990 
54991 /*! @name SR - GPT Status Register */
54992 /*! @{ */
54993 
54994 #define GPT_SR_OF1_MASK                          (0x1U)
54995 #define GPT_SR_OF1_SHIFT                         (0U)
54996 /*! OF1 - Output Compare Flag for Channel 1
54997  *  0b0..Compare event has not occurred.
54998  *  0b1..Compare event has occurred.
54999  */
55000 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
55001 
55002 #define GPT_SR_OF2_MASK                          (0x2U)
55003 #define GPT_SR_OF2_SHIFT                         (1U)
55004 /*! OF2 - Output Compare Flag for Channel 2
55005  *  0b0..Compare event has not occurred.
55006  *  0b1..Compare event has occurred.
55007  */
55008 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
55009 
55010 #define GPT_SR_OF3_MASK                          (0x4U)
55011 #define GPT_SR_OF3_SHIFT                         (2U)
55012 /*! OF3 - Output Compare Flag for Channel 3
55013  *  0b0..Compare event has not occurred.
55014  *  0b1..Compare event has occurred.
55015  */
55016 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
55017 
55018 #define GPT_SR_IF1_MASK                          (0x8U)
55019 #define GPT_SR_IF1_SHIFT                         (3U)
55020 /*! IF1 - Input Capture Flag for Channel 1
55021  *  0b0..Capture event has not occurred.
55022  *  0b1..Capture event has occurred.
55023  */
55024 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
55025 
55026 #define GPT_SR_IF2_MASK                          (0x10U)
55027 #define GPT_SR_IF2_SHIFT                         (4U)
55028 /*! IF2 - Input Capture Flag for Channel 2
55029  *  0b0..Capture event has not occurred.
55030  *  0b1..Capture event has occurred.
55031  */
55032 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
55033 
55034 #define GPT_SR_ROV_MASK                          (0x20U)
55035 #define GPT_SR_ROV_SHIFT                         (5U)
55036 /*! ROV - Rollover Flag
55037  *  0b0..Rollover has not occurred.
55038  *  0b1..Rollover has occurred.
55039  */
55040 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
55041 /*! @} */
55042 
55043 /*! @name IR - GPT Interrupt Register */
55044 /*! @{ */
55045 
55046 #define GPT_IR_OF1IE_MASK                        (0x1U)
55047 #define GPT_IR_OF1IE_SHIFT                       (0U)
55048 /*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable
55049  *  0b0..Disable
55050  *  0b1..Enable
55051  */
55052 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
55053 
55054 #define GPT_IR_OF2IE_MASK                        (0x2U)
55055 #define GPT_IR_OF2IE_SHIFT                       (1U)
55056 /*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable
55057  *  0b0..Disable
55058  *  0b1..Enable
55059  */
55060 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
55061 
55062 #define GPT_IR_OF3IE_MASK                        (0x4U)
55063 #define GPT_IR_OF3IE_SHIFT                       (2U)
55064 /*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable
55065  *  0b0..Disable
55066  *  0b1..Enable
55067  */
55068 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
55069 
55070 #define GPT_IR_IF1IE_MASK                        (0x8U)
55071 #define GPT_IR_IF1IE_SHIFT                       (3U)
55072 /*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable
55073  *  0b0..Disable
55074  *  0b1..Enable
55075  */
55076 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
55077 
55078 #define GPT_IR_IF2IE_MASK                        (0x10U)
55079 #define GPT_IR_IF2IE_SHIFT                       (4U)
55080 /*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable
55081  *  0b0..Disable
55082  *  0b1..Enable
55083  */
55084 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
55085 
55086 #define GPT_IR_ROVIE_MASK                        (0x20U)
55087 #define GPT_IR_ROVIE_SHIFT                       (5U)
55088 /*! ROVIE - Rollover Interrupt Enable
55089  *  0b0..Disable
55090  *  0b1..Enable
55091  */
55092 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
55093 /*! @} */
55094 
55095 /*! @name OCR - GPT Output Compare Register */
55096 /*! @{ */
55097 
55098 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
55099 #define GPT_OCR_COMP_SHIFT                       (0U)
55100 /*! COMP - Compare Value
55101  */
55102 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
55103 /*! @} */
55104 
55105 /* The count of GPT_OCR */
55106 #define GPT_OCR_COUNT                            (3U)
55107 
55108 /*! @name ICR - GPT Input Capture Register */
55109 /*! @{ */
55110 
55111 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
55112 #define GPT_ICR_CAPT_SHIFT                       (0U)
55113 /*! CAPT - Capture Value
55114  */
55115 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
55116 /*! @} */
55117 
55118 /* The count of GPT_ICR */
55119 #define GPT_ICR_COUNT                            (2U)
55120 
55121 /*! @name CNT - GPT Counter Register */
55122 /*! @{ */
55123 
55124 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
55125 #define GPT_CNT_COUNT_SHIFT                      (0U)
55126 /*! COUNT - Counter Value
55127  */
55128 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
55129 /*! @} */
55130 
55131 
55132 /*!
55133  * @}
55134  */ /* end of group GPT_Register_Masks */
55135 
55136 
55137 /* GPT - Peripheral instance base addresses */
55138 /** Peripheral GPT1 base address */
55139 #define GPT1_BASE                                (0x400EC000u)
55140 /** Peripheral GPT1 base pointer */
55141 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
55142 /** Peripheral GPT2 base address */
55143 #define GPT2_BASE                                (0x400F0000u)
55144 /** Peripheral GPT2 base pointer */
55145 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
55146 /** Peripheral GPT3 base address */
55147 #define GPT3_BASE                                (0x400F4000u)
55148 /** Peripheral GPT3 base pointer */
55149 #define GPT3                                     ((GPT_Type *)GPT3_BASE)
55150 /** Peripheral GPT4 base address */
55151 #define GPT4_BASE                                (0x400F8000u)
55152 /** Peripheral GPT4 base pointer */
55153 #define GPT4                                     ((GPT_Type *)GPT4_BASE)
55154 /** Peripheral GPT5 base address */
55155 #define GPT5_BASE                                (0x400FC000u)
55156 /** Peripheral GPT5 base pointer */
55157 #define GPT5                                     ((GPT_Type *)GPT5_BASE)
55158 /** Peripheral GPT6 base address */
55159 #define GPT6_BASE                                (0x40100000u)
55160 /** Peripheral GPT6 base pointer */
55161 #define GPT6                                     ((GPT_Type *)GPT6_BASE)
55162 /** Array initializer of GPT peripheral base addresses */
55163 #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
55164 /** Array initializer of GPT peripheral base pointers */
55165 #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
55166 /** Interrupt vectors for the GPT peripheral type */
55167 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
55168 
55169 /*!
55170  * @}
55171  */ /* end of group GPT_Peripheral_Access_Layer */
55172 
55173 
55174 /* ----------------------------------------------------------------------------
55175    -- I2S Peripheral Access Layer
55176    ---------------------------------------------------------------------------- */
55177 
55178 /*!
55179  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
55180  * @{
55181  */
55182 
55183 /** I2S - Register Layout Typedef */
55184 typedef struct {
55185   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
55186   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
55187   __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
55188   __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
55189   __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
55190   __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
55191   __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
55192   __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
55193   __O  uint32_t TDR[4];                            /**< Transmit Data, array offset: 0x20, array step: 0x4 */
55194        uint8_t RESERVED_0[16];
55195   __I  uint32_t TFR[4];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */
55196        uint8_t RESERVED_1[16];
55197   __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
55198        uint8_t RESERVED_2[36];
55199   __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
55200   __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
55201   __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
55202   __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
55203   __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
55204   __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
55205   __I  uint32_t RDR[4];                            /**< Receive Data, array offset: 0xA0, array step: 0x4 */
55206        uint8_t RESERVED_3[16];
55207   __I  uint32_t RFR[4];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */
55208        uint8_t RESERVED_4[16];
55209   __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
55210 } I2S_Type;
55211 
55212 /* ----------------------------------------------------------------------------
55213    -- I2S Register Masks
55214    ---------------------------------------------------------------------------- */
55215 
55216 /*!
55217  * @addtogroup I2S_Register_Masks I2S Register Masks
55218  * @{
55219  */
55220 
55221 /*! @name VERID - Version ID */
55222 /*! @{ */
55223 
55224 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
55225 #define I2S_VERID_FEATURE_SHIFT                  (0U)
55226 /*! FEATURE - Feature Specification Number
55227  *  0b0000000000000000..Standard feature set.
55228  */
55229 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
55230 
55231 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
55232 #define I2S_VERID_MINOR_SHIFT                    (16U)
55233 /*! MINOR - Minor Version Number
55234  */
55235 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
55236 
55237 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
55238 #define I2S_VERID_MAJOR_SHIFT                    (24U)
55239 /*! MAJOR - Major Version Number
55240  */
55241 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
55242 /*! @} */
55243 
55244 /*! @name PARAM - Parameter */
55245 /*! @{ */
55246 
55247 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
55248 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
55249 /*! DATALINE - Number of Datalines
55250  */
55251 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
55252 
55253 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
55254 #define I2S_PARAM_FIFO_SHIFT                     (8U)
55255 /*! FIFO - FIFO Size
55256  */
55257 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
55258 
55259 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
55260 #define I2S_PARAM_FRAME_SHIFT                    (16U)
55261 /*! FRAME - Frame Size
55262  */
55263 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
55264 /*! @} */
55265 
55266 /*! @name TCSR - Transmit Control */
55267 /*! @{ */
55268 
55269 #define I2S_TCSR_FRDE_MASK                       (0x1U)
55270 #define I2S_TCSR_FRDE_SHIFT                      (0U)
55271 /*! FRDE - FIFO Request DMA Enable
55272  *  0b0..Disables the DMA request.
55273  *  0b1..Enables the DMA request.
55274  */
55275 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
55276 
55277 #define I2S_TCSR_FWDE_MASK                       (0x2U)
55278 #define I2S_TCSR_FWDE_SHIFT                      (1U)
55279 /*! FWDE - FIFO Warning DMA Enable
55280  *  0b0..Disables the DMA request.
55281  *  0b1..Enables the DMA request.
55282  */
55283 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
55284 
55285 #define I2S_TCSR_FRIE_MASK                       (0x100U)
55286 #define I2S_TCSR_FRIE_SHIFT                      (8U)
55287 /*! FRIE - FIFO Request Interrupt Enable
55288  *  0b0..Disables the interrupt.
55289  *  0b1..Enables the interrupt.
55290  */
55291 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
55292 
55293 #define I2S_TCSR_FWIE_MASK                       (0x200U)
55294 #define I2S_TCSR_FWIE_SHIFT                      (9U)
55295 /*! FWIE - FIFO Warning Interrupt Enable
55296  *  0b0..Disables the interrupt.
55297  *  0b1..Enables the interrupt.
55298  */
55299 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
55300 
55301 #define I2S_TCSR_FEIE_MASK                       (0x400U)
55302 #define I2S_TCSR_FEIE_SHIFT                      (10U)
55303 /*! FEIE - FIFO Error Interrupt Enable
55304  *  0b0..Disables the interrupt.
55305  *  0b1..Enables the interrupt.
55306  */
55307 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
55308 
55309 #define I2S_TCSR_SEIE_MASK                       (0x800U)
55310 #define I2S_TCSR_SEIE_SHIFT                      (11U)
55311 /*! SEIE - Sync Error Interrupt Enable
55312  *  0b0..Disables interrupt.
55313  *  0b1..Enables interrupt.
55314  */
55315 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
55316 
55317 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
55318 #define I2S_TCSR_WSIE_SHIFT                      (12U)
55319 /*! WSIE - Word Start Interrupt Enable
55320  *  0b0..Disables interrupt.
55321  *  0b1..Enables interrupt.
55322  */
55323 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
55324 
55325 #define I2S_TCSR_FRF_MASK                        (0x10000U)
55326 #define I2S_TCSR_FRF_SHIFT                       (16U)
55327 /*! FRF - FIFO Request Flag
55328  *  0b0..Transmit FIFO watermark has not been reached.
55329  *  0b1..Transmit FIFO watermark has been reached.
55330  */
55331 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
55332 
55333 #define I2S_TCSR_FWF_MASK                        (0x20000U)
55334 #define I2S_TCSR_FWF_SHIFT                       (17U)
55335 /*! FWF - FIFO Warning Flag
55336  *  0b0..No enabled transmit FIFO is empty.
55337  *  0b1..Enabled transmit FIFO is empty.
55338  */
55339 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
55340 
55341 #define I2S_TCSR_FEF_MASK                        (0x40000U)
55342 #define I2S_TCSR_FEF_SHIFT                       (18U)
55343 /*! FEF - FIFO Error Flag
55344  *  0b0..Transmit underrun not detected.
55345  *  0b1..Transmit underrun detected.
55346  */
55347 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
55348 
55349 #define I2S_TCSR_SEF_MASK                        (0x80000U)
55350 #define I2S_TCSR_SEF_SHIFT                       (19U)
55351 /*! SEF - Sync Error Flag
55352  *  0b0..Sync error not detected.
55353  *  0b1..Frame sync error detected.
55354  */
55355 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
55356 
55357 #define I2S_TCSR_WSF_MASK                        (0x100000U)
55358 #define I2S_TCSR_WSF_SHIFT                       (20U)
55359 /*! WSF - Word Start Flag
55360  *  0b0..Start of word not detected.
55361  *  0b1..Start of word detected.
55362  */
55363 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
55364 
55365 #define I2S_TCSR_SR_MASK                         (0x1000000U)
55366 #define I2S_TCSR_SR_SHIFT                        (24U)
55367 /*! SR - Software Reset
55368  *  0b0..No effect.
55369  *  0b1..Software reset.
55370  */
55371 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
55372 
55373 #define I2S_TCSR_FR_MASK                         (0x2000000U)
55374 #define I2S_TCSR_FR_SHIFT                        (25U)
55375 /*! FR - FIFO Reset
55376  *  0b0..No effect.
55377  *  0b1..FIFO reset.
55378  */
55379 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
55380 
55381 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
55382 #define I2S_TCSR_BCE_SHIFT                       (28U)
55383 /*! BCE - Bit Clock Enable
55384  *  0b0..Transmit bit clock is disabled.
55385  *  0b1..Transmit bit clock is enabled.
55386  */
55387 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
55388 
55389 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
55390 #define I2S_TCSR_DBGE_SHIFT                      (29U)
55391 /*! DBGE - Debug Enable
55392  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
55393  *  0b1..Transmitter is enabled in Debug mode.
55394  */
55395 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
55396 
55397 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
55398 #define I2S_TCSR_STOPE_SHIFT                     (30U)
55399 /*! STOPE - Stop Enable
55400  *  0b0..Transmitter disabled in Stop mode.
55401  *  0b1..Transmitter enabled in Stop mode.
55402  */
55403 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
55404 
55405 #define I2S_TCSR_TE_MASK                         (0x80000000U)
55406 #define I2S_TCSR_TE_SHIFT                        (31U)
55407 /*! TE - Transmitter Enable
55408  *  0b0..Transmitter is disabled.
55409  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
55410  */
55411 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
55412 /*! @} */
55413 
55414 /*! @name TCR1 - Transmit Configuration 1 */
55415 /*! @{ */
55416 
55417 #define I2S_TCR1_TFW_MASK                        (0x1FU)
55418 #define I2S_TCR1_TFW_SHIFT                       (0U)
55419 /*! TFW - Transmit FIFO Watermark
55420  */
55421 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
55422 /*! @} */
55423 
55424 /*! @name TCR2 - Transmit Configuration 2 */
55425 /*! @{ */
55426 
55427 #define I2S_TCR2_DIV_MASK                        (0xFFU)
55428 #define I2S_TCR2_DIV_SHIFT                       (0U)
55429 /*! DIV - Bit Clock Divide
55430  */
55431 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
55432 
55433 #define I2S_TCR2_BYP_MASK                        (0x800000U)
55434 #define I2S_TCR2_BYP_SHIFT                       (23U)
55435 /*! BYP - Bit Clock Bypass
55436  *  0b0..Internal bit clock is generated from bit clock divider.
55437  *  0b1..Internal bit clock is divide by one of the audio master clock.
55438  */
55439 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
55440 
55441 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
55442 #define I2S_TCR2_BCD_SHIFT                       (24U)
55443 /*! BCD - Bit Clock Direction
55444  *  0b0..Bit clock is generated externally in Slave mode.
55445  *  0b1..Bit clock is generated internally in Master mode.
55446  */
55447 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
55448 
55449 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
55450 #define I2S_TCR2_BCP_SHIFT                       (25U)
55451 /*! BCP - Bit Clock Polarity
55452  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
55453  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
55454  */
55455 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
55456 
55457 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
55458 #define I2S_TCR2_MSEL_SHIFT                      (26U)
55459 /*! MSEL - MCLK Select
55460  *  0b00..Bus Clock selected.
55461  *  0b01..Master Clock (MCLK) 1 option selected.
55462  *  0b10..Master Clock (MCLK) 2 option selected.
55463  *  0b11..Master Clock (MCLK) 3 option selected.
55464  */
55465 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
55466 
55467 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
55468 #define I2S_TCR2_BCI_SHIFT                       (28U)
55469 /*! BCI - Bit Clock Input
55470  *  0b0..No effect.
55471  *  0b1..Internal logic is clocked as if bit clock was externally generated.
55472  */
55473 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
55474 
55475 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
55476 #define I2S_TCR2_BCS_SHIFT                       (29U)
55477 /*! BCS - Bit Clock Swap
55478  *  0b0..Use the normal bit clock source.
55479  *  0b1..Swap the bit clock source.
55480  */
55481 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
55482 
55483 #define I2S_TCR2_SYNC_MASK                       (0x40000000U)
55484 #define I2S_TCR2_SYNC_SHIFT                      (30U)
55485 /*! SYNC - Synchronous Mode
55486  *  0b0..Asynchronous mode.
55487  *  0b1..Synchronous with receiver.
55488  */
55489 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
55490 /*! @} */
55491 
55492 /*! @name TCR3 - Transmit Configuration 3 */
55493 /*! @{ */
55494 
55495 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
55496 #define I2S_TCR3_WDFL_SHIFT                      (0U)
55497 /*! WDFL - Word Flag Configuration
55498  */
55499 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
55500 
55501 #define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
55502 #define I2S_TCR3_TCE_SHIFT                       (16U)
55503 /*! TCE - Transmit Channel Enable
55504  */
55505 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
55506 
55507 #define I2S_TCR3_CFR_MASK                        (0xF000000U)
55508 #define I2S_TCR3_CFR_SHIFT                       (24U)
55509 /*! CFR - Channel FIFO Reset
55510  */
55511 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
55512 /*! @} */
55513 
55514 /*! @name TCR4 - Transmit Configuration 4 */
55515 /*! @{ */
55516 
55517 #define I2S_TCR4_FSD_MASK                        (0x1U)
55518 #define I2S_TCR4_FSD_SHIFT                       (0U)
55519 /*! FSD - Frame Sync Direction
55520  *  0b0..Frame sync is generated externally in Slave mode.
55521  *  0b1..Frame sync is generated internally in Master mode.
55522  */
55523 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
55524 
55525 #define I2S_TCR4_FSP_MASK                        (0x2U)
55526 #define I2S_TCR4_FSP_SHIFT                       (1U)
55527 /*! FSP - Frame Sync Polarity
55528  *  0b0..Frame sync is active high.
55529  *  0b1..Frame sync is active low.
55530  */
55531 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
55532 
55533 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
55534 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
55535 /*! ONDEM - On Demand Mode
55536  *  0b0..Internal frame sync is generated continuously.
55537  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
55538  */
55539 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
55540 
55541 #define I2S_TCR4_FSE_MASK                        (0x8U)
55542 #define I2S_TCR4_FSE_SHIFT                       (3U)
55543 /*! FSE - Frame Sync Early
55544  *  0b0..Frame sync asserts with the first bit of the frame.
55545  *  0b1..Frame sync asserts one bit before the first bit of the frame.
55546  */
55547 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
55548 
55549 #define I2S_TCR4_MF_MASK                         (0x10U)
55550 #define I2S_TCR4_MF_SHIFT                        (4U)
55551 /*! MF - MSB First
55552  *  0b0..LSB is transmitted first.
55553  *  0b1..MSB is transmitted first.
55554  */
55555 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
55556 
55557 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
55558 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
55559 /*! CHMOD - Channel Mode
55560  *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
55561  *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
55562  */
55563 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
55564 
55565 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
55566 #define I2S_TCR4_SYWD_SHIFT                      (8U)
55567 /*! SYWD - Sync Width
55568  */
55569 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
55570 
55571 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
55572 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
55573 /*! FRSZ - Frame size
55574  */
55575 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
55576 
55577 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
55578 #define I2S_TCR4_FPACK_SHIFT                     (24U)
55579 /*! FPACK - FIFO Packing Mode
55580  *  0b00..FIFO packing is disabled.
55581  *  0b01..Reserved
55582  *  0b10..8-bit FIFO packing is enabled.
55583  *  0b11..16-bit FIFO packing is enabled.
55584  */
55585 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
55586 
55587 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
55588 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
55589 /*! FCOMB - FIFO Combine Mode
55590  *  0b00..FIFO combine mode disabled.
55591  *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
55592  *  0b10..FIFO combine mode enabled on FIFO writes (by software).
55593  *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
55594  */
55595 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
55596 
55597 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
55598 #define I2S_TCR4_FCONT_SHIFT                     (28U)
55599 /*! FCONT - FIFO Continue on Error
55600  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
55601  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
55602  */
55603 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
55604 /*! @} */
55605 
55606 /*! @name TCR5 - Transmit Configuration 5 */
55607 /*! @{ */
55608 
55609 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
55610 #define I2S_TCR5_FBT_SHIFT                       (8U)
55611 /*! FBT - First Bit Shifted
55612  */
55613 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
55614 
55615 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
55616 #define I2S_TCR5_W0W_SHIFT                       (16U)
55617 /*! W0W - Word 0 Width
55618  */
55619 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
55620 
55621 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
55622 #define I2S_TCR5_WNW_SHIFT                       (24U)
55623 /*! WNW - Word N Width
55624  */
55625 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
55626 /*! @} */
55627 
55628 /*! @name TDR - Transmit Data */
55629 /*! @{ */
55630 
55631 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
55632 #define I2S_TDR_TDR_SHIFT                        (0U)
55633 /*! TDR - Transmit Data Register
55634  */
55635 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
55636 /*! @} */
55637 
55638 /* The count of I2S_TDR */
55639 #define I2S_TDR_COUNT                            (4U)
55640 
55641 /*! @name TFR - Transmit FIFO */
55642 /*! @{ */
55643 
55644 #define I2S_TFR_RFP_MASK                         (0x3FU)
55645 #define I2S_TFR_RFP_SHIFT                        (0U)
55646 /*! RFP - Read FIFO Pointer
55647  */
55648 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
55649 
55650 #define I2S_TFR_WFP_MASK                         (0x3F0000U)
55651 #define I2S_TFR_WFP_SHIFT                        (16U)
55652 /*! WFP - Write FIFO Pointer
55653  */
55654 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
55655 
55656 #define I2S_TFR_WCP_MASK                         (0x80000000U)
55657 #define I2S_TFR_WCP_SHIFT                        (31U)
55658 /*! WCP - Write Channel Pointer
55659  *  0b0..No effect.
55660  *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
55661  */
55662 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
55663 /*! @} */
55664 
55665 /* The count of I2S_TFR */
55666 #define I2S_TFR_COUNT                            (4U)
55667 
55668 /*! @name TMR - Transmit Mask */
55669 /*! @{ */
55670 
55671 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
55672 #define I2S_TMR_TWM_SHIFT                        (0U)
55673 /*! TWM - Transmit Word Mask
55674  *  0b00000000000000000000000000000000..Word N is enabled.
55675  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
55676  */
55677 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
55678 /*! @} */
55679 
55680 /*! @name RCSR - Receive Control */
55681 /*! @{ */
55682 
55683 #define I2S_RCSR_FRDE_MASK                       (0x1U)
55684 #define I2S_RCSR_FRDE_SHIFT                      (0U)
55685 /*! FRDE - FIFO Request DMA Enable
55686  *  0b0..Disables the DMA request.
55687  *  0b1..Enables the DMA request.
55688  */
55689 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
55690 
55691 #define I2S_RCSR_FWDE_MASK                       (0x2U)
55692 #define I2S_RCSR_FWDE_SHIFT                      (1U)
55693 /*! FWDE - FIFO Warning DMA Enable
55694  *  0b0..Disables the DMA request.
55695  *  0b1..Enables the DMA request.
55696  */
55697 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
55698 
55699 #define I2S_RCSR_FRIE_MASK                       (0x100U)
55700 #define I2S_RCSR_FRIE_SHIFT                      (8U)
55701 /*! FRIE - FIFO Request Interrupt Enable
55702  *  0b0..Disables the interrupt.
55703  *  0b1..Enables the interrupt.
55704  */
55705 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
55706 
55707 #define I2S_RCSR_FWIE_MASK                       (0x200U)
55708 #define I2S_RCSR_FWIE_SHIFT                      (9U)
55709 /*! FWIE - FIFO Warning Interrupt Enable
55710  *  0b0..Disables the interrupt.
55711  *  0b1..Enables the interrupt.
55712  */
55713 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
55714 
55715 #define I2S_RCSR_FEIE_MASK                       (0x400U)
55716 #define I2S_RCSR_FEIE_SHIFT                      (10U)
55717 /*! FEIE - FIFO Error Interrupt Enable
55718  *  0b0..Disables the interrupt.
55719  *  0b1..Enables the interrupt.
55720  */
55721 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
55722 
55723 #define I2S_RCSR_SEIE_MASK                       (0x800U)
55724 #define I2S_RCSR_SEIE_SHIFT                      (11U)
55725 /*! SEIE - Sync Error Interrupt Enable
55726  *  0b0..Disables interrupt.
55727  *  0b1..Enables interrupt.
55728  */
55729 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
55730 
55731 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
55732 #define I2S_RCSR_WSIE_SHIFT                      (12U)
55733 /*! WSIE - Word Start Interrupt Enable
55734  *  0b0..Disables interrupt.
55735  *  0b1..Enables interrupt.
55736  */
55737 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
55738 
55739 #define I2S_RCSR_FRF_MASK                        (0x10000U)
55740 #define I2S_RCSR_FRF_SHIFT                       (16U)
55741 /*! FRF - FIFO Request Flag
55742  *  0b0..Receive FIFO watermark not reached.
55743  *  0b1..Receive FIFO watermark has been reached.
55744  */
55745 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
55746 
55747 #define I2S_RCSR_FWF_MASK                        (0x20000U)
55748 #define I2S_RCSR_FWF_SHIFT                       (17U)
55749 /*! FWF - FIFO Warning Flag
55750  *  0b0..No enabled receive FIFO is full.
55751  *  0b1..Enabled receive FIFO is full.
55752  */
55753 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
55754 
55755 #define I2S_RCSR_FEF_MASK                        (0x40000U)
55756 #define I2S_RCSR_FEF_SHIFT                       (18U)
55757 /*! FEF - FIFO Error Flag
55758  *  0b0..Receive overflow not detected.
55759  *  0b1..Receive overflow detected.
55760  */
55761 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
55762 
55763 #define I2S_RCSR_SEF_MASK                        (0x80000U)
55764 #define I2S_RCSR_SEF_SHIFT                       (19U)
55765 /*! SEF - Sync Error Flag
55766  *  0b0..Sync error not detected.
55767  *  0b1..Frame sync error detected.
55768  */
55769 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
55770 
55771 #define I2S_RCSR_WSF_MASK                        (0x100000U)
55772 #define I2S_RCSR_WSF_SHIFT                       (20U)
55773 /*! WSF - Word Start Flag
55774  *  0b0..Start of word not detected.
55775  *  0b1..Start of word detected.
55776  */
55777 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
55778 
55779 #define I2S_RCSR_SR_MASK                         (0x1000000U)
55780 #define I2S_RCSR_SR_SHIFT                        (24U)
55781 /*! SR - Software Reset
55782  *  0b0..No effect.
55783  *  0b1..Software reset.
55784  */
55785 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
55786 
55787 #define I2S_RCSR_FR_MASK                         (0x2000000U)
55788 #define I2S_RCSR_FR_SHIFT                        (25U)
55789 /*! FR - FIFO Reset
55790  *  0b0..No effect.
55791  *  0b1..FIFO reset.
55792  */
55793 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
55794 
55795 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
55796 #define I2S_RCSR_BCE_SHIFT                       (28U)
55797 /*! BCE - Bit Clock Enable
55798  *  0b0..Receive bit clock is disabled.
55799  *  0b1..Receive bit clock is enabled.
55800  */
55801 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
55802 
55803 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
55804 #define I2S_RCSR_DBGE_SHIFT                      (29U)
55805 /*! DBGE - Debug Enable
55806  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
55807  *  0b1..Receiver is enabled in Debug mode.
55808  */
55809 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
55810 
55811 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
55812 #define I2S_RCSR_STOPE_SHIFT                     (30U)
55813 /*! STOPE - Stop Enable
55814  *  0b0..Receiver disabled in Stop mode.
55815  *  0b1..Receiver enabled in Stop mode.
55816  */
55817 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
55818 
55819 #define I2S_RCSR_RE_MASK                         (0x80000000U)
55820 #define I2S_RCSR_RE_SHIFT                        (31U)
55821 /*! RE - Receiver Enable
55822  *  0b0..Receiver is disabled.
55823  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
55824  */
55825 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
55826 /*! @} */
55827 
55828 /*! @name RCR1 - Receive Configuration 1 */
55829 /*! @{ */
55830 
55831 #define I2S_RCR1_RFW_MASK                        (0x1FU)
55832 #define I2S_RCR1_RFW_SHIFT                       (0U)
55833 /*! RFW - Receive FIFO Watermark
55834  */
55835 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
55836 /*! @} */
55837 
55838 /*! @name RCR2 - Receive Configuration 2 */
55839 /*! @{ */
55840 
55841 #define I2S_RCR2_DIV_MASK                        (0xFFU)
55842 #define I2S_RCR2_DIV_SHIFT                       (0U)
55843 /*! DIV - Bit Clock Divide
55844  */
55845 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
55846 
55847 #define I2S_RCR2_BYP_MASK                        (0x800000U)
55848 #define I2S_RCR2_BYP_SHIFT                       (23U)
55849 /*! BYP - Bit Clock Bypass
55850  *  0b0..Internal bit clock is generated from bit clock divider.
55851  *  0b1..Internal bit clock is divide by one of the audio master clock.
55852  */
55853 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
55854 
55855 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
55856 #define I2S_RCR2_BCD_SHIFT                       (24U)
55857 /*! BCD - Bit Clock Direction
55858  *  0b0..Bit clock is generated externally in Slave mode.
55859  *  0b1..Bit clock is generated internally in Master mode.
55860  */
55861 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
55862 
55863 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
55864 #define I2S_RCR2_BCP_SHIFT                       (25U)
55865 /*! BCP - Bit Clock Polarity
55866  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
55867  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
55868  */
55869 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
55870 
55871 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
55872 #define I2S_RCR2_MSEL_SHIFT                      (26U)
55873 /*! MSEL - MCLK Select
55874  *  0b00..Bus Clock selected.
55875  *  0b01..Master Clock (MCLK) 1 option selected.
55876  *  0b10..Master Clock (MCLK) 2 option selected.
55877  *  0b11..Master Clock (MCLK) 3 option selected.
55878  */
55879 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
55880 
55881 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
55882 #define I2S_RCR2_BCI_SHIFT                       (28U)
55883 /*! BCI - Bit Clock Input
55884  *  0b0..No effect.
55885  *  0b1..Internal logic is clocked as if bit clock was externally generated.
55886  */
55887 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
55888 
55889 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
55890 #define I2S_RCR2_BCS_SHIFT                       (29U)
55891 /*! BCS - Bit Clock Swap
55892  *  0b0..Use the normal bit clock source.
55893  *  0b1..Swap the bit clock source.
55894  */
55895 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
55896 
55897 #define I2S_RCR2_SYNC_MASK                       (0x40000000U)
55898 #define I2S_RCR2_SYNC_SHIFT                      (30U)
55899 /*! SYNC - Synchronous Mode
55900  *  0b0..Asynchronous mode.
55901  *  0b1..Synchronous with transmitter.
55902  */
55903 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
55904 /*! @} */
55905 
55906 /*! @name RCR3 - Receive Configuration 3 */
55907 /*! @{ */
55908 
55909 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
55910 #define I2S_RCR3_WDFL_SHIFT                      (0U)
55911 /*! WDFL - Word Flag Configuration
55912  */
55913 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
55914 
55915 #define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
55916 #define I2S_RCR3_RCE_SHIFT                       (16U)
55917 /*! RCE - Receive Channel Enable
55918  */
55919 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
55920 
55921 #define I2S_RCR3_CFR_MASK                        (0xF000000U)
55922 #define I2S_RCR3_CFR_SHIFT                       (24U)
55923 /*! CFR - Channel FIFO Reset
55924  */
55925 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
55926 /*! @} */
55927 
55928 /*! @name RCR4 - Receive Configuration 4 */
55929 /*! @{ */
55930 
55931 #define I2S_RCR4_FSD_MASK                        (0x1U)
55932 #define I2S_RCR4_FSD_SHIFT                       (0U)
55933 /*! FSD - Frame Sync Direction
55934  *  0b0..Frame Sync is generated externally in Slave mode.
55935  *  0b1..Frame Sync is generated internally in Master mode.
55936  */
55937 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
55938 
55939 #define I2S_RCR4_FSP_MASK                        (0x2U)
55940 #define I2S_RCR4_FSP_SHIFT                       (1U)
55941 /*! FSP - Frame Sync Polarity
55942  *  0b0..Frame sync is active high.
55943  *  0b1..Frame sync is active low.
55944  */
55945 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
55946 
55947 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
55948 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
55949 /*! ONDEM - On Demand Mode
55950  *  0b0..Internal frame sync is generated continuously.
55951  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
55952  */
55953 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
55954 
55955 #define I2S_RCR4_FSE_MASK                        (0x8U)
55956 #define I2S_RCR4_FSE_SHIFT                       (3U)
55957 /*! FSE - Frame Sync Early
55958  *  0b0..Frame sync asserts with the first bit of the frame.
55959  *  0b1..Frame sync asserts one bit before the first bit of the frame.
55960  */
55961 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
55962 
55963 #define I2S_RCR4_MF_MASK                         (0x10U)
55964 #define I2S_RCR4_MF_SHIFT                        (4U)
55965 /*! MF - MSB First
55966  *  0b0..LSB is received first.
55967  *  0b1..MSB is received first.
55968  */
55969 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
55970 
55971 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
55972 #define I2S_RCR4_SYWD_SHIFT                      (8U)
55973 /*! SYWD - Sync Width
55974  */
55975 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
55976 
55977 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
55978 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
55979 /*! FRSZ - Frame Size
55980  */
55981 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
55982 
55983 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
55984 #define I2S_RCR4_FPACK_SHIFT                     (24U)
55985 /*! FPACK - FIFO Packing Mode
55986  *  0b00..FIFO packing is disabled
55987  *  0b01..Reserved.
55988  *  0b10..8-bit FIFO packing is enabled
55989  *  0b11..16-bit FIFO packing is enabled
55990  */
55991 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
55992 
55993 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
55994 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
55995 /*! FCOMB - FIFO Combine Mode
55996  *  0b00..FIFO combine mode disabled.
55997  *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
55998  *  0b10..FIFO combine mode enabled on FIFO reads (by software).
55999  *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
56000  */
56001 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
56002 
56003 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
56004 #define I2S_RCR4_FCONT_SHIFT                     (28U)
56005 /*! FCONT - FIFO Continue on Error
56006  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
56007  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
56008  */
56009 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
56010 /*! @} */
56011 
56012 /*! @name RCR5 - Receive Configuration 5 */
56013 /*! @{ */
56014 
56015 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
56016 #define I2S_RCR5_FBT_SHIFT                       (8U)
56017 /*! FBT - First Bit Shifted
56018  */
56019 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
56020 
56021 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
56022 #define I2S_RCR5_W0W_SHIFT                       (16U)
56023 /*! W0W - Word 0 Width
56024  */
56025 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
56026 
56027 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
56028 #define I2S_RCR5_WNW_SHIFT                       (24U)
56029 /*! WNW - Word N Width
56030  */
56031 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
56032 /*! @} */
56033 
56034 /*! @name RDR - Receive Data */
56035 /*! @{ */
56036 
56037 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
56038 #define I2S_RDR_RDR_SHIFT                        (0U)
56039 /*! RDR - Receive Data Register
56040  */
56041 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
56042 /*! @} */
56043 
56044 /* The count of I2S_RDR */
56045 #define I2S_RDR_COUNT                            (4U)
56046 
56047 /*! @name RFR - Receive FIFO */
56048 /*! @{ */
56049 
56050 #define I2S_RFR_RFP_MASK                         (0x3FU)
56051 #define I2S_RFR_RFP_SHIFT                        (0U)
56052 /*! RFP - Read FIFO Pointer
56053  */
56054 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
56055 
56056 #define I2S_RFR_RCP_MASK                         (0x8000U)
56057 #define I2S_RFR_RCP_SHIFT                        (15U)
56058 /*! RCP - Receive Channel Pointer
56059  *  0b0..No effect.
56060  *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
56061  */
56062 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
56063 
56064 #define I2S_RFR_WFP_MASK                         (0x3F0000U)
56065 #define I2S_RFR_WFP_SHIFT                        (16U)
56066 /*! WFP - Write FIFO Pointer
56067  */
56068 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
56069 /*! @} */
56070 
56071 /* The count of I2S_RFR */
56072 #define I2S_RFR_COUNT                            (4U)
56073 
56074 /*! @name RMR - Receive Mask */
56075 /*! @{ */
56076 
56077 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
56078 #define I2S_RMR_RWM_SHIFT                        (0U)
56079 /*! RWM - Receive Word Mask
56080  *  0b00000000000000000000000000000000..Word N is enabled.
56081  *  0b00000000000000000000000000000001..Word N is masked.
56082  */
56083 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
56084 /*! @} */
56085 
56086 
56087 /*!
56088  * @}
56089  */ /* end of group I2S_Register_Masks */
56090 
56091 
56092 /* I2S - Peripheral instance base addresses */
56093 /** Peripheral SAI1 base address */
56094 #define SAI1_BASE                                (0x40404000u)
56095 /** Peripheral SAI1 base pointer */
56096 #define SAI1                                     ((I2S_Type *)SAI1_BASE)
56097 /** Peripheral SAI2 base address */
56098 #define SAI2_BASE                                (0x40408000u)
56099 /** Peripheral SAI2 base pointer */
56100 #define SAI2                                     ((I2S_Type *)SAI2_BASE)
56101 /** Peripheral SAI3 base address */
56102 #define SAI3_BASE                                (0x4040C000u)
56103 /** Peripheral SAI3 base pointer */
56104 #define SAI3                                     ((I2S_Type *)SAI3_BASE)
56105 /** Peripheral SAI4 base address */
56106 #define SAI4_BASE                                (0x40C40000u)
56107 /** Peripheral SAI4 base pointer */
56108 #define SAI4                                     ((I2S_Type *)SAI4_BASE)
56109 /** Array initializer of I2S peripheral base addresses */
56110 #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
56111 /** Array initializer of I2S peripheral base pointers */
56112 #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
56113 /** Interrupt vectors for the I2S peripheral type */
56114 #define I2S_RX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
56115 #define I2S_TX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
56116 
56117 /*!
56118  * @}
56119  */ /* end of group I2S_Peripheral_Access_Layer */
56120 
56121 
56122 /* ----------------------------------------------------------------------------
56123    -- IEE Peripheral Access Layer
56124    ---------------------------------------------------------------------------- */
56125 
56126 /*!
56127  * @addtogroup IEE_Peripheral_Access_Layer IEE Peripheral Access Layer
56128  * @{
56129  */
56130 
56131 /** IEE - Register Layout Typedef */
56132 typedef struct {
56133   __IO uint32_t GCFG;                              /**< IEE Global Configuration, offset: 0x0 */
56134   __I  uint32_t STA;                               /**< IEE Status, offset: 0x4 */
56135   __IO uint32_t TSTMD;                             /**< IEE Test Mode Register, offset: 0x8 */
56136   __O  uint32_t DPAMS;                             /**< AES Mask Generation Seed, offset: 0xC */
56137        uint8_t RESERVED_0[16];
56138   __IO uint32_t PC_S_LT;                           /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */
56139   __IO uint32_t PC_M_LT;                           /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */
56140        uint8_t RESERVED_1[24];
56141   __IO uint32_t PC_BLK_ENC;                        /**< Performance Counter, Number of AES Block Encryptions, offset: 0x40 */
56142   __IO uint32_t PC_BLK_DEC;                        /**< Performance Counter, Number of AES Block Decryptions, offset: 0x44 */
56143        uint8_t RESERVED_2[8];
56144   __IO uint32_t PC_SR_TRANS;                       /**< Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50 */
56145   __IO uint32_t PC_SW_TRANS;                       /**< Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54 */
56146   __IO uint32_t PC_MR_TRANS;                       /**< Performance Counter, Number of AXI Master Read Transactions, offset: 0x58 */
56147   __IO uint32_t PC_MW_TRANS;                       /**< Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C */
56148        uint8_t RESERVED_3[4];
56149   __IO uint32_t PC_M_MBR;                          /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */
56150        uint8_t RESERVED_4[8];
56151   __IO uint32_t PC_SR_TBC_U;                       /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */
56152   __IO uint32_t PC_SR_TBC_L;                       /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */
56153   __IO uint32_t PC_SW_TBC_U;                       /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */
56154   __IO uint32_t PC_SW_TBC_L;                       /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */
56155   __IO uint32_t PC_MR_TBC_U;                       /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */
56156   __IO uint32_t PC_MR_TBC_L;                       /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */
56157   __IO uint32_t PC_MW_TBC_U;                       /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */
56158   __IO uint32_t PC_MW_TBC_L;                       /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */
56159   __IO uint32_t PC_SR_TLGTT;                       /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */
56160   __IO uint32_t PC_SW_TLGTT;                       /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */
56161   __IO uint32_t PC_MR_TLGTT;                       /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */
56162   __IO uint32_t PC_MW_TLGTT;                       /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */
56163   __IO uint32_t PC_SR_TLAT_U;                      /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */
56164   __IO uint32_t PC_SR_TLAT_L;                      /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */
56165   __IO uint32_t PC_SW_TLAT_U;                      /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */
56166   __IO uint32_t PC_SW_TLAT_L;                      /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */
56167   __IO uint32_t PC_MR_TLAT_U;                      /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */
56168   __IO uint32_t PC_MR_TLAT_L;                      /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */
56169   __IO uint32_t PC_MW_TLAT_U;                      /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */
56170   __IO uint32_t PC_MW_TLAT_L;                      /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */
56171   __IO uint32_t PC_SR_TNRT_U;                      /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */
56172   __IO uint32_t PC_SR_TNRT_L;                      /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */
56173   __IO uint32_t PC_SW_TNRT_U;                      /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */
56174   __IO uint32_t PC_SW_TNRT_L;                      /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */
56175        uint8_t RESERVED_5[32];
56176   __I  uint32_t VIDR1;                             /**< IEE Version ID Register 1, offset: 0xF0 */
56177        uint8_t RESERVED_6[4];
56178   __I  uint32_t AESVID;                            /**< IEE AES Version ID Register, offset: 0xF8 */
56179        uint8_t RESERVED_7[4];
56180   struct {                                         /* offset: 0x100, array step: 0x100 */
56181     __IO uint32_t REGATTR;                           /**< IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100 */
56182          uint8_t RESERVED_0[4];
56183     __IO uint32_t REGPO;                             /**< IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100 */
56184          uint8_t RESERVED_1[52];
56185     __O  uint32_t REGKEY1[8];                        /**< IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4 */
56186          uint8_t RESERVED_2[32];
56187     __O  uint32_t REGKEY2[8];                        /**< IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4 */
56188          uint8_t RESERVED_3[96];
56189   } REGX[8];
56190        uint8_t RESERVED_8[1536];
56191   __IO uint32_t AES_TST_DB[32];                    /**< IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4 */
56192 } IEE_Type;
56193 
56194 /* ----------------------------------------------------------------------------
56195    -- IEE Register Masks
56196    ---------------------------------------------------------------------------- */
56197 
56198 /*!
56199  * @addtogroup IEE_Register_Masks IEE Register Masks
56200  * @{
56201  */
56202 
56203 /*! @name GCFG - IEE Global Configuration */
56204 /*! @{ */
56205 
56206 #define IEE_GCFG_RL0_MASK                        (0x1U)
56207 #define IEE_GCFG_RL0_SHIFT                       (0U)
56208 /*! RL0
56209  *  0b0..Unlocked.
56210  *  0b1..Key, Offset and Attribute registers are locked.
56211  */
56212 #define IEE_GCFG_RL0(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
56213 
56214 #define IEE_GCFG_RL1_MASK                        (0x2U)
56215 #define IEE_GCFG_RL1_SHIFT                       (1U)
56216 /*! RL1
56217  *  0b0..Unlocked.
56218  *  0b1..Key, Offset and Attribute registers are locked.
56219  */
56220 #define IEE_GCFG_RL1(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
56221 
56222 #define IEE_GCFG_RL2_MASK                        (0x4U)
56223 #define IEE_GCFG_RL2_SHIFT                       (2U)
56224 /*! RL2
56225  *  0b0..Unlocked.
56226  *  0b1..Key, Offset and Attribute registers are locked.
56227  */
56228 #define IEE_GCFG_RL2(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
56229 
56230 #define IEE_GCFG_RL3_MASK                        (0x8U)
56231 #define IEE_GCFG_RL3_SHIFT                       (3U)
56232 /*! RL3
56233  *  0b0..Unlocked.
56234  *  0b1..Key, Offset and Attribute registers are locked.
56235  */
56236 #define IEE_GCFG_RL3(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
56237 
56238 #define IEE_GCFG_RL4_MASK                        (0x10U)
56239 #define IEE_GCFG_RL4_SHIFT                       (4U)
56240 /*! RL4
56241  *  0b0..Unlocked.
56242  *  0b1..Key, Offset and Attribute registers are locked.
56243  */
56244 #define IEE_GCFG_RL4(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
56245 
56246 #define IEE_GCFG_RL5_MASK                        (0x20U)
56247 #define IEE_GCFG_RL5_SHIFT                       (5U)
56248 /*! RL5
56249  *  0b0..Unlocked.
56250  *  0b1..Key, Offset and Attribute registers are locked.
56251  */
56252 #define IEE_GCFG_RL5(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
56253 
56254 #define IEE_GCFG_RL6_MASK                        (0x40U)
56255 #define IEE_GCFG_RL6_SHIFT                       (6U)
56256 /*! RL6
56257  *  0b0..Unlocked.
56258  *  0b1..Key, Offset and Attribute registers are locked.
56259  */
56260 #define IEE_GCFG_RL6(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
56261 
56262 #define IEE_GCFG_RL7_MASK                        (0x80U)
56263 #define IEE_GCFG_RL7_SHIFT                       (7U)
56264 /*! RL7
56265  *  0b0..Unlocked.
56266  *  0b1..Key, Offset and Attribute registers are locked.
56267  */
56268 #define IEE_GCFG_RL7(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
56269 
56270 #define IEE_GCFG_TME_MASK                        (0x10000U)
56271 #define IEE_GCFG_TME_SHIFT                       (16U)
56272 /*! TME
56273  *  0b0..Disabled.
56274  *  0b1..Enabled.
56275  */
56276 #define IEE_GCFG_TME(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
56277 
56278 #define IEE_GCFG_TMD_MASK                        (0x20000U)
56279 #define IEE_GCFG_TMD_SHIFT                       (17U)
56280 /*! TMD
56281  *  0b0..Test mode is usable.
56282  *  0b1..Test mode is disabled.
56283  */
56284 #define IEE_GCFG_TMD(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
56285 
56286 #define IEE_GCFG_KEY_RD_DIS_MASK                 (0x2000000U)
56287 #define IEE_GCFG_KEY_RD_DIS_SHIFT                (25U)
56288 /*! KEY_RD_DIS
56289  *  0b0..Key read enabled. Reading the key registers is allowed.
56290  *  0b1..Key read disabled. Reading the key registers is disabled.
56291  */
56292 #define IEE_GCFG_KEY_RD_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
56293 
56294 #define IEE_GCFG_MON_EN_MASK                     (0x10000000U)
56295 #define IEE_GCFG_MON_EN_SHIFT                    (28U)
56296 /*! MON_EN
56297  *  0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled.
56298  *  0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.
56299  */
56300 #define IEE_GCFG_MON_EN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
56301 
56302 #define IEE_GCFG_CLR_MON_MASK                    (0x20000000U)
56303 #define IEE_GCFG_CLR_MON_SHIFT                   (29U)
56304 /*! CLR_MON
56305  *  0b0..Do not reset.
56306  *  0b1..Reset performance counters.
56307  */
56308 #define IEE_GCFG_CLR_MON(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
56309 
56310 #define IEE_GCFG_RST_MASK                        (0x80000000U)
56311 #define IEE_GCFG_RST_SHIFT                       (31U)
56312 /*! RST
56313  *  0b0..Do Not Reset.
56314  *  0b1..Reset IEE.
56315  */
56316 #define IEE_GCFG_RST(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
56317 /*! @} */
56318 
56319 /*! @name STA - IEE Status */
56320 /*! @{ */
56321 
56322 #define IEE_STA_DSR_MASK                         (0x1U)
56323 #define IEE_STA_DSR_SHIFT                        (0U)
56324 /*! DSR
56325  *  0b0..No seed request present
56326  *  0b1..Seed request present
56327  */
56328 #define IEE_STA_DSR(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
56329 
56330 #define IEE_STA_AFD_MASK                         (0x10U)
56331 #define IEE_STA_AFD_SHIFT                        (4U)
56332 /*! AFD
56333  *  0b0..No fault detected
56334  *  0b1..Fault detected
56335  */
56336 #define IEE_STA_AFD(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
56337 /*! @} */
56338 
56339 /*! @name TSTMD - IEE Test Mode Register */
56340 /*! @{ */
56341 
56342 #define IEE_TSTMD_TMRDY_MASK                     (0x1U)
56343 #define IEE_TSTMD_TMRDY_SHIFT                    (0U)
56344 /*! TMRDY
56345  *  0b0..Not Ready.
56346  *  0b1..Ready.
56347  */
56348 #define IEE_TSTMD_TMRDY(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
56349 
56350 #define IEE_TSTMD_TMR_MASK                       (0x2U)
56351 #define IEE_TSTMD_TMR_SHIFT                      (1U)
56352 /*! TMR
56353  *  0b0..Not running. May be written if IEE_GCFG[TME] = 1
56354  *  0b1..Run AES Test until TMDONE is indicated.
56355  */
56356 #define IEE_TSTMD_TMR(x)                         (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
56357 
56358 #define IEE_TSTMD_TMENCR_MASK                    (0x4U)
56359 #define IEE_TSTMD_TMENCR_SHIFT                   (2U)
56360 /*! TMENCR
56361  *  0b0..AES Test mode will do decryption.
56362  *  0b1..AES Test mode will do encryption.
56363  */
56364 #define IEE_TSTMD_TMENCR(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
56365 
56366 #define IEE_TSTMD_TMCONT_MASK                    (0x8U)
56367 #define IEE_TSTMD_TMCONT_SHIFT                   (3U)
56368 /*! TMCONT
56369  *  0b0..Do not continue. This is the last block of data for AES.
56370  *  0b1..Continue. Do not initialize AES after this block.
56371  */
56372 #define IEE_TSTMD_TMCONT(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
56373 
56374 #define IEE_TSTMD_TMDONE_MASK                    (0x10U)
56375 #define IEE_TSTMD_TMDONE_SHIFT                   (4U)
56376 /*! TMDONE
56377  *  0b0..Not Done.
56378  *  0b1..Test Done.
56379  */
56380 #define IEE_TSTMD_TMDONE(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
56381 
56382 #define IEE_TSTMD_TMLEN_MASK                     (0xF00U)
56383 #define IEE_TSTMD_TMLEN_SHIFT                    (8U)
56384 #define IEE_TSTMD_TMLEN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
56385 /*! @} */
56386 
56387 /*! @name DPAMS - AES Mask Generation Seed */
56388 /*! @{ */
56389 
56390 #define IEE_DPAMS_DPAMS_MASK                     (0xFFFFFFFFU)
56391 #define IEE_DPAMS_DPAMS_SHIFT                    (0U)
56392 #define IEE_DPAMS_DPAMS(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
56393 /*! @} */
56394 
56395 /*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */
56396 /*! @{ */
56397 
56398 #define IEE_PC_S_LT_SW_LT_MASK                   (0xFFFFU)
56399 #define IEE_PC_S_LT_SW_LT_SHIFT                  (0U)
56400 #define IEE_PC_S_LT_SW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
56401 
56402 #define IEE_PC_S_LT_SR_LT_MASK                   (0xFFFF0000U)
56403 #define IEE_PC_S_LT_SR_LT_SHIFT                  (16U)
56404 #define IEE_PC_S_LT_SR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
56405 /*! @} */
56406 
56407 /*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */
56408 /*! @{ */
56409 
56410 #define IEE_PC_M_LT_MW_LT_MASK                   (0xFFFU)
56411 #define IEE_PC_M_LT_MW_LT_SHIFT                  (0U)
56412 #define IEE_PC_M_LT_MW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
56413 
56414 #define IEE_PC_M_LT_MR_LT_MASK                   (0xFFF0000U)
56415 #define IEE_PC_M_LT_MR_LT_SHIFT                  (16U)
56416 #define IEE_PC_M_LT_MR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
56417 /*! @} */
56418 
56419 /*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */
56420 /*! @{ */
56421 
56422 #define IEE_PC_BLK_ENC_BLK_ENC_MASK              (0xFFFFFFFFU)
56423 #define IEE_PC_BLK_ENC_BLK_ENC_SHIFT             (0U)
56424 #define IEE_PC_BLK_ENC_BLK_ENC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
56425 /*! @} */
56426 
56427 /*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */
56428 /*! @{ */
56429 
56430 #define IEE_PC_BLK_DEC_BLK_DEC_MASK              (0xFFFFFFFFU)
56431 #define IEE_PC_BLK_DEC_BLK_DEC_SHIFT             (0U)
56432 #define IEE_PC_BLK_DEC_BLK_DEC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
56433 /*! @} */
56434 
56435 /*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */
56436 /*! @{ */
56437 
56438 #define IEE_PC_SR_TRANS_SR_TRANS_MASK            (0xFFFFFFFFU)
56439 #define IEE_PC_SR_TRANS_SR_TRANS_SHIFT           (0U)
56440 #define IEE_PC_SR_TRANS_SR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
56441 /*! @} */
56442 
56443 /*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */
56444 /*! @{ */
56445 
56446 #define IEE_PC_SW_TRANS_SW_TRANS_MASK            (0xFFFFFFFFU)
56447 #define IEE_PC_SW_TRANS_SW_TRANS_SHIFT           (0U)
56448 #define IEE_PC_SW_TRANS_SW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
56449 /*! @} */
56450 
56451 /*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */
56452 /*! @{ */
56453 
56454 #define IEE_PC_MR_TRANS_MR_TRANS_MASK            (0xFFFFFFFFU)
56455 #define IEE_PC_MR_TRANS_MR_TRANS_SHIFT           (0U)
56456 #define IEE_PC_MR_TRANS_MR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
56457 /*! @} */
56458 
56459 /*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */
56460 /*! @{ */
56461 
56462 #define IEE_PC_MW_TRANS_MW_TRANS_MASK            (0xFFFFFFFFU)
56463 #define IEE_PC_MW_TRANS_MW_TRANS_SHIFT           (0U)
56464 #define IEE_PC_MW_TRANS_MW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
56465 /*! @} */
56466 
56467 /*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */
56468 /*! @{ */
56469 
56470 #define IEE_PC_M_MBR_M_MBR_MASK                  (0xFFFFFFFFU)
56471 #define IEE_PC_M_MBR_M_MBR_SHIFT                 (0U)
56472 #define IEE_PC_M_MBR_M_MBR(x)                    (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
56473 /*! @} */
56474 
56475 /*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */
56476 /*! @{ */
56477 
56478 #define IEE_PC_SR_TBC_U_SR_TBC_MASK              (0xFFFFU)
56479 #define IEE_PC_SR_TBC_U_SR_TBC_SHIFT             (0U)
56480 #define IEE_PC_SR_TBC_U_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
56481 /*! @} */
56482 
56483 /*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */
56484 /*! @{ */
56485 
56486 #define IEE_PC_SR_TBC_L_SR_TBC_MASK              (0xFFFFFFFFU)
56487 #define IEE_PC_SR_TBC_L_SR_TBC_SHIFT             (0U)
56488 #define IEE_PC_SR_TBC_L_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
56489 /*! @} */
56490 
56491 /*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */
56492 /*! @{ */
56493 
56494 #define IEE_PC_SW_TBC_U_SW_TBC_MASK              (0xFFFFU)
56495 #define IEE_PC_SW_TBC_U_SW_TBC_SHIFT             (0U)
56496 #define IEE_PC_SW_TBC_U_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
56497 /*! @} */
56498 
56499 /*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */
56500 /*! @{ */
56501 
56502 #define IEE_PC_SW_TBC_L_SW_TBC_MASK              (0xFFFFFFFFU)
56503 #define IEE_PC_SW_TBC_L_SW_TBC_SHIFT             (0U)
56504 #define IEE_PC_SW_TBC_L_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
56505 /*! @} */
56506 
56507 /*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */
56508 /*! @{ */
56509 
56510 #define IEE_PC_MR_TBC_U_MR_TBC_MASK              (0xFFFFU)
56511 #define IEE_PC_MR_TBC_U_MR_TBC_SHIFT             (0U)
56512 #define IEE_PC_MR_TBC_U_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
56513 /*! @} */
56514 
56515 /*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */
56516 /*! @{ */
56517 
56518 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK          (0xFU)
56519 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT         (0U)
56520 #define IEE_PC_MR_TBC_L_MR_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
56521 
56522 #define IEE_PC_MR_TBC_L_MR_TBC_MASK              (0xFFFFFFF0U)
56523 #define IEE_PC_MR_TBC_L_MR_TBC_SHIFT             (4U)
56524 #define IEE_PC_MR_TBC_L_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
56525 /*! @} */
56526 
56527 /*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */
56528 /*! @{ */
56529 
56530 #define IEE_PC_MW_TBC_U_MW_TBC_MASK              (0xFFFFU)
56531 #define IEE_PC_MW_TBC_U_MW_TBC_SHIFT             (0U)
56532 #define IEE_PC_MW_TBC_U_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
56533 /*! @} */
56534 
56535 /*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */
56536 /*! @{ */
56537 
56538 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK          (0xFU)
56539 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT         (0U)
56540 #define IEE_PC_MW_TBC_L_MW_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
56541 
56542 #define IEE_PC_MW_TBC_L_MW_TBC_MASK              (0xFFFFFFF0U)
56543 #define IEE_PC_MW_TBC_L_MW_TBC_SHIFT             (4U)
56544 #define IEE_PC_MW_TBC_L_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
56545 /*! @} */
56546 
56547 /*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */
56548 /*! @{ */
56549 
56550 #define IEE_PC_SR_TLGTT_SR_TLGTT_MASK            (0xFFFFFFFFU)
56551 #define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT           (0U)
56552 #define IEE_PC_SR_TLGTT_SR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
56553 /*! @} */
56554 
56555 /*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */
56556 /*! @{ */
56557 
56558 #define IEE_PC_SW_TLGTT_SW_TLGTT_MASK            (0xFFFFFFFFU)
56559 #define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT           (0U)
56560 #define IEE_PC_SW_TLGTT_SW_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
56561 /*! @} */
56562 
56563 /*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */
56564 /*! @{ */
56565 
56566 #define IEE_PC_MR_TLGTT_MR_TLGTT_MASK            (0xFFFFFFFFU)
56567 #define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT           (0U)
56568 #define IEE_PC_MR_TLGTT_MR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
56569 /*! @} */
56570 
56571 /*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */
56572 /*! @{ */
56573 
56574 #define IEE_PC_MW_TLGTT_MW_TGTT_MASK             (0xFFFFFFFFU)
56575 #define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT            (0U)
56576 #define IEE_PC_MW_TLGTT_MW_TGTT(x)               (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
56577 /*! @} */
56578 
56579 /*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */
56580 /*! @{ */
56581 
56582 #define IEE_PC_SR_TLAT_U_SR_TLAT_MASK            (0xFFFFU)
56583 #define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT           (0U)
56584 #define IEE_PC_SR_TLAT_U_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
56585 /*! @} */
56586 
56587 /*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */
56588 /*! @{ */
56589 
56590 #define IEE_PC_SR_TLAT_L_SR_TLAT_MASK            (0xFFFFFFFFU)
56591 #define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT           (0U)
56592 #define IEE_PC_SR_TLAT_L_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
56593 /*! @} */
56594 
56595 /*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */
56596 /*! @{ */
56597 
56598 #define IEE_PC_SW_TLAT_U_SW_TLAT_MASK            (0xFFFFU)
56599 #define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT           (0U)
56600 #define IEE_PC_SW_TLAT_U_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
56601 /*! @} */
56602 
56603 /*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */
56604 /*! @{ */
56605 
56606 #define IEE_PC_SW_TLAT_L_SW_TLAT_MASK            (0xFFFFFFFFU)
56607 #define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT           (0U)
56608 #define IEE_PC_SW_TLAT_L_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
56609 /*! @} */
56610 
56611 /*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */
56612 /*! @{ */
56613 
56614 #define IEE_PC_MR_TLAT_U_MR_TLAT_MASK            (0xFFFFU)
56615 #define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT           (0U)
56616 #define IEE_PC_MR_TLAT_U_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
56617 /*! @} */
56618 
56619 /*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */
56620 /*! @{ */
56621 
56622 #define IEE_PC_MR_TLAT_L_MR_TLAT_MASK            (0xFFFFFFFFU)
56623 #define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT           (0U)
56624 #define IEE_PC_MR_TLAT_L_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
56625 /*! @} */
56626 
56627 /*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */
56628 /*! @{ */
56629 
56630 #define IEE_PC_MW_TLAT_U_MW_TLAT_MASK            (0xFFFFU)
56631 #define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT           (0U)
56632 #define IEE_PC_MW_TLAT_U_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
56633 /*! @} */
56634 
56635 /*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */
56636 /*! @{ */
56637 
56638 #define IEE_PC_MW_TLAT_L_MW_TLAT_MASK            (0xFFFFFFFFU)
56639 #define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT           (0U)
56640 #define IEE_PC_MW_TLAT_L_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
56641 /*! @} */
56642 
56643 /*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */
56644 /*! @{ */
56645 
56646 #define IEE_PC_SR_TNRT_U_SR_TNRT_MASK            (0xFFFFU)
56647 #define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT           (0U)
56648 #define IEE_PC_SR_TNRT_U_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
56649 /*! @} */
56650 
56651 /*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */
56652 /*! @{ */
56653 
56654 #define IEE_PC_SR_TNRT_L_SR_TNRT_MASK            (0xFFFFFFFFU)
56655 #define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT           (0U)
56656 #define IEE_PC_SR_TNRT_L_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
56657 /*! @} */
56658 
56659 /*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */
56660 /*! @{ */
56661 
56662 #define IEE_PC_SW_TNRT_U_SW_TNRT_MASK            (0xFFFFU)
56663 #define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT           (0U)
56664 #define IEE_PC_SW_TNRT_U_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
56665 /*! @} */
56666 
56667 /*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */
56668 /*! @{ */
56669 
56670 #define IEE_PC_SW_TNRT_L_SW_TNRT_MASK            (0xFFFFFFFFU)
56671 #define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT           (0U)
56672 #define IEE_PC_SW_TNRT_L_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
56673 /*! @} */
56674 
56675 /*! @name VIDR1 - IEE Version ID Register 1 */
56676 /*! @{ */
56677 
56678 #define IEE_VIDR1_MIN_REV_MASK                   (0xFFU)
56679 #define IEE_VIDR1_MIN_REV_SHIFT                  (0U)
56680 #define IEE_VIDR1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
56681 
56682 #define IEE_VIDR1_MAJ_REV_MASK                   (0xFF00U)
56683 #define IEE_VIDR1_MAJ_REV_SHIFT                  (8U)
56684 #define IEE_VIDR1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
56685 
56686 #define IEE_VIDR1_IP_ID_MASK                     (0xFFFF0000U)
56687 #define IEE_VIDR1_IP_ID_SHIFT                    (16U)
56688 #define IEE_VIDR1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
56689 /*! @} */
56690 
56691 /*! @name AESVID - IEE AES Version ID Register */
56692 /*! @{ */
56693 
56694 #define IEE_AESVID_AESRN_MASK                    (0xFU)
56695 #define IEE_AESVID_AESRN_SHIFT                   (0U)
56696 #define IEE_AESVID_AESRN(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
56697 
56698 #define IEE_AESVID_AESVID_MASK                   (0xF0U)
56699 #define IEE_AESVID_AESVID_SHIFT                  (4U)
56700 #define IEE_AESVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
56701 /*! @} */
56702 
56703 /*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */
56704 /*! @{ */
56705 
56706 #define IEE_REGATTR_KS_MASK                      (0x1U)
56707 #define IEE_REGATTR_KS_SHIFT                     (0U)
56708 /*! KS
56709  *  0b0..128 bits (CTR), 256 bits (XTS).
56710  *  0b1..256 bits (CTR), 512 bits (XTS).
56711  */
56712 #define IEE_REGATTR_KS(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
56713 
56714 #define IEE_REGATTR_MD_MASK                      (0x70U)
56715 #define IEE_REGATTR_MD_SHIFT                     (4U)
56716 /*! MD
56717  *  0b000..None (AXI error if accessed)
56718  *  0b001..XTS
56719  *  0b010..CTR w/ address binding
56720  *  0b011..CTR w/o address binding
56721  *  0b100..CTR keystream only
56722  *  0b101..Undefined, AXI error if used
56723  *  0b110..Undefined, AXI error if used
56724  *  0b111..Undefined, AXI error if used
56725  */
56726 #define IEE_REGATTR_MD(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
56727 
56728 #define IEE_REGATTR_BYP_MASK                     (0x80U)
56729 #define IEE_REGATTR_BYP_SHIFT                    (7U)
56730 /*! BYP
56731  *  0b0..use MD field
56732  *  0b1..Bypass AES, no encrypt/decrypt
56733  */
56734 #define IEE_REGATTR_BYP(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
56735 /*! @} */
56736 
56737 /* The count of IEE_REGATTR */
56738 #define IEE_REGATTR_COUNT                        (8U)
56739 
56740 /*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */
56741 /*! @{ */
56742 
56743 #define IEE_REGPO_PGOFF_MASK                     (0xFFFFFFU)
56744 #define IEE_REGPO_PGOFF_SHIFT                    (0U)
56745 #define IEE_REGPO_PGOFF(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
56746 /*! @} */
56747 
56748 /* The count of IEE_REGPO */
56749 #define IEE_REGPO_COUNT                          (8U)
56750 
56751 /*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */
56752 /*! @{ */
56753 
56754 #define IEE_REGKEY1_KEY1_MASK                    (0xFFFFFFFFU)
56755 #define IEE_REGKEY1_KEY1_SHIFT                   (0U)
56756 #define IEE_REGKEY1_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
56757 /*! @} */
56758 
56759 /* The count of IEE_REGKEY1 */
56760 #define IEE_REGKEY1_COUNT                        (8U)
56761 
56762 /* The count of IEE_REGKEY1 */
56763 #define IEE_REGKEY1_COUNT2                       (8U)
56764 
56765 /*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */
56766 /*! @{ */
56767 
56768 #define IEE_REGKEY2_KEY2_MASK                    (0xFFFFFFFFU)
56769 #define IEE_REGKEY2_KEY2_SHIFT                   (0U)
56770 #define IEE_REGKEY2_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
56771 /*! @} */
56772 
56773 /* The count of IEE_REGKEY2 */
56774 #define IEE_REGKEY2_COUNT                        (8U)
56775 
56776 /* The count of IEE_REGKEY2 */
56777 #define IEE_REGKEY2_COUNT2                       (8U)
56778 
56779 /*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */
56780 /*! @{ */
56781 
56782 #define IEE_AES_TST_DB_AES_TST_DB0_MASK          (0xFFFFFFFFU)
56783 #define IEE_AES_TST_DB_AES_TST_DB0_SHIFT         (0U)
56784 #define IEE_AES_TST_DB_AES_TST_DB0(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
56785 
56786 #define IEE_AES_TST_DB_AES_TST_DB1_MASK          (0xFFFFFFFFU)
56787 #define IEE_AES_TST_DB_AES_TST_DB1_SHIFT         (0U)
56788 #define IEE_AES_TST_DB_AES_TST_DB1(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
56789 
56790 #define IEE_AES_TST_DB_AES_TST_DB2_MASK          (0xFFFFFFFFU)
56791 #define IEE_AES_TST_DB_AES_TST_DB2_SHIFT         (0U)
56792 #define IEE_AES_TST_DB_AES_TST_DB2(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
56793 
56794 #define IEE_AES_TST_DB_AES_TST_DB3_MASK          (0xFFFFFFFFU)
56795 #define IEE_AES_TST_DB_AES_TST_DB3_SHIFT         (0U)
56796 #define IEE_AES_TST_DB_AES_TST_DB3(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
56797 
56798 #define IEE_AES_TST_DB_AES_TST_DB4_MASK          (0xFFFFFFFFU)
56799 #define IEE_AES_TST_DB_AES_TST_DB4_SHIFT         (0U)
56800 #define IEE_AES_TST_DB_AES_TST_DB4(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
56801 
56802 #define IEE_AES_TST_DB_AES_TST_DB5_MASK          (0xFFFFFFFFU)
56803 #define IEE_AES_TST_DB_AES_TST_DB5_SHIFT         (0U)
56804 #define IEE_AES_TST_DB_AES_TST_DB5(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
56805 
56806 #define IEE_AES_TST_DB_AES_TST_DB6_MASK          (0xFFFFFFFFU)
56807 #define IEE_AES_TST_DB_AES_TST_DB6_SHIFT         (0U)
56808 #define IEE_AES_TST_DB_AES_TST_DB6(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
56809 
56810 #define IEE_AES_TST_DB_AES_TST_DB7_MASK          (0xFFFFFFFFU)
56811 #define IEE_AES_TST_DB_AES_TST_DB7_SHIFT         (0U)
56812 #define IEE_AES_TST_DB_AES_TST_DB7(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
56813 
56814 #define IEE_AES_TST_DB_AES_TST_DB8_MASK          (0xFFFFFFFFU)
56815 #define IEE_AES_TST_DB_AES_TST_DB8_SHIFT         (0U)
56816 #define IEE_AES_TST_DB_AES_TST_DB8(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
56817 
56818 #define IEE_AES_TST_DB_AES_TST_DB9_MASK          (0xFFFFFFFFU)
56819 #define IEE_AES_TST_DB_AES_TST_DB9_SHIFT         (0U)
56820 #define IEE_AES_TST_DB_AES_TST_DB9(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
56821 
56822 #define IEE_AES_TST_DB_AES_TST_DB10_MASK         (0xFFFFFFFFU)
56823 #define IEE_AES_TST_DB_AES_TST_DB10_SHIFT        (0U)
56824 #define IEE_AES_TST_DB_AES_TST_DB10(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
56825 
56826 #define IEE_AES_TST_DB_AES_TST_DB11_MASK         (0xFFFFFFFFU)
56827 #define IEE_AES_TST_DB_AES_TST_DB11_SHIFT        (0U)
56828 #define IEE_AES_TST_DB_AES_TST_DB11(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
56829 
56830 #define IEE_AES_TST_DB_AES_TST_DB12_MASK         (0xFFFFFFFFU)
56831 #define IEE_AES_TST_DB_AES_TST_DB12_SHIFT        (0U)
56832 #define IEE_AES_TST_DB_AES_TST_DB12(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
56833 
56834 #define IEE_AES_TST_DB_AES_TST_DB13_MASK         (0xFFFFFFFFU)
56835 #define IEE_AES_TST_DB_AES_TST_DB13_SHIFT        (0U)
56836 #define IEE_AES_TST_DB_AES_TST_DB13(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
56837 
56838 #define IEE_AES_TST_DB_AES_TST_DB14_MASK         (0xFFFFFFFFU)
56839 #define IEE_AES_TST_DB_AES_TST_DB14_SHIFT        (0U)
56840 #define IEE_AES_TST_DB_AES_TST_DB14(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
56841 
56842 #define IEE_AES_TST_DB_AES_TST_DB15_MASK         (0xFFFFFFFFU)
56843 #define IEE_AES_TST_DB_AES_TST_DB15_SHIFT        (0U)
56844 #define IEE_AES_TST_DB_AES_TST_DB15(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
56845 
56846 #define IEE_AES_TST_DB_AES_TST_DB16_MASK         (0xFFFFFFFFU)
56847 #define IEE_AES_TST_DB_AES_TST_DB16_SHIFT        (0U)
56848 #define IEE_AES_TST_DB_AES_TST_DB16(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
56849 
56850 #define IEE_AES_TST_DB_AES_TST_DB17_MASK         (0xFFFFFFFFU)
56851 #define IEE_AES_TST_DB_AES_TST_DB17_SHIFT        (0U)
56852 #define IEE_AES_TST_DB_AES_TST_DB17(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
56853 
56854 #define IEE_AES_TST_DB_AES_TST_DB18_MASK         (0xFFFFFFFFU)
56855 #define IEE_AES_TST_DB_AES_TST_DB18_SHIFT        (0U)
56856 #define IEE_AES_TST_DB_AES_TST_DB18(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
56857 
56858 #define IEE_AES_TST_DB_AES_TST_DB19_MASK         (0xFFFFFFFFU)
56859 #define IEE_AES_TST_DB_AES_TST_DB19_SHIFT        (0U)
56860 #define IEE_AES_TST_DB_AES_TST_DB19(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
56861 
56862 #define IEE_AES_TST_DB_AES_TST_DB20_MASK         (0xFFFFFFFFU)
56863 #define IEE_AES_TST_DB_AES_TST_DB20_SHIFT        (0U)
56864 #define IEE_AES_TST_DB_AES_TST_DB20(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
56865 
56866 #define IEE_AES_TST_DB_AES_TST_DB21_MASK         (0xFFFFFFFFU)
56867 #define IEE_AES_TST_DB_AES_TST_DB21_SHIFT        (0U)
56868 #define IEE_AES_TST_DB_AES_TST_DB21(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
56869 
56870 #define IEE_AES_TST_DB_AES_TST_DB22_MASK         (0xFFFFFFFFU)
56871 #define IEE_AES_TST_DB_AES_TST_DB22_SHIFT        (0U)
56872 #define IEE_AES_TST_DB_AES_TST_DB22(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
56873 
56874 #define IEE_AES_TST_DB_AES_TST_DB23_MASK         (0xFFFFFFFFU)
56875 #define IEE_AES_TST_DB_AES_TST_DB23_SHIFT        (0U)
56876 #define IEE_AES_TST_DB_AES_TST_DB23(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
56877 
56878 #define IEE_AES_TST_DB_AES_TST_DB24_MASK         (0xFFFFFFFFU)
56879 #define IEE_AES_TST_DB_AES_TST_DB24_SHIFT        (0U)
56880 #define IEE_AES_TST_DB_AES_TST_DB24(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
56881 
56882 #define IEE_AES_TST_DB_AES_TST_DB25_MASK         (0xFFFFFFFFU)
56883 #define IEE_AES_TST_DB_AES_TST_DB25_SHIFT        (0U)
56884 #define IEE_AES_TST_DB_AES_TST_DB25(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
56885 
56886 #define IEE_AES_TST_DB_AES_TST_DB26_MASK         (0xFFFFFFFFU)
56887 #define IEE_AES_TST_DB_AES_TST_DB26_SHIFT        (0U)
56888 #define IEE_AES_TST_DB_AES_TST_DB26(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
56889 
56890 #define IEE_AES_TST_DB_AES_TST_DB27_MASK         (0xFFFFFFFFU)
56891 #define IEE_AES_TST_DB_AES_TST_DB27_SHIFT        (0U)
56892 #define IEE_AES_TST_DB_AES_TST_DB27(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
56893 
56894 #define IEE_AES_TST_DB_AES_TST_DB28_MASK         (0xFFFFFFFFU)
56895 #define IEE_AES_TST_DB_AES_TST_DB28_SHIFT        (0U)
56896 #define IEE_AES_TST_DB_AES_TST_DB28(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
56897 
56898 #define IEE_AES_TST_DB_AES_TST_DB29_MASK         (0xFFFFFFFFU)
56899 #define IEE_AES_TST_DB_AES_TST_DB29_SHIFT        (0U)
56900 #define IEE_AES_TST_DB_AES_TST_DB29(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
56901 
56902 #define IEE_AES_TST_DB_AES_TST_DB30_MASK         (0xFFFFFFFFU)
56903 #define IEE_AES_TST_DB_AES_TST_DB30_SHIFT        (0U)
56904 #define IEE_AES_TST_DB_AES_TST_DB30(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
56905 
56906 #define IEE_AES_TST_DB_AES_TST_DB31_MASK         (0xFFFFFFFFU)
56907 #define IEE_AES_TST_DB_AES_TST_DB31_SHIFT        (0U)
56908 #define IEE_AES_TST_DB_AES_TST_DB31(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
56909 /*! @} */
56910 
56911 /* The count of IEE_AES_TST_DB */
56912 #define IEE_AES_TST_DB_COUNT                     (32U)
56913 
56914 
56915 /*!
56916  * @}
56917  */ /* end of group IEE_Register_Masks */
56918 
56919 
56920 /* IEE - Peripheral instance base addresses */
56921 /** Peripheral IEE__IEE_RT1170 base address */
56922 #define IEE__IEE_RT1170_BASE                     (0x4006C000u)
56923 /** Peripheral IEE__IEE_RT1170 base pointer */
56924 #define IEE__IEE_RT1170                          ((IEE_Type *)IEE__IEE_RT1170_BASE)
56925 /** Array initializer of IEE peripheral base addresses */
56926 #define IEE_BASE_ADDRS                           { IEE__IEE_RT1170_BASE }
56927 /** Array initializer of IEE peripheral base pointers */
56928 #define IEE_BASE_PTRS                            { IEE__IEE_RT1170 }
56929 
56930 /*!
56931  * @}
56932  */ /* end of group IEE_Peripheral_Access_Layer */
56933 
56934 
56935 /* ----------------------------------------------------------------------------
56936    -- IEE_APC Peripheral Access Layer
56937    ---------------------------------------------------------------------------- */
56938 
56939 /*!
56940  * @addtogroup IEE_APC_Peripheral_Access_Layer IEE_APC Peripheral Access Layer
56941  * @{
56942  */
56943 
56944 /** IEE_APC - Register Layout Typedef */
56945 typedef struct {
56946   __IO uint32_t REGION0_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x0 */
56947   __IO uint32_t REGION0_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x4 */
56948   __IO uint32_t REGION0_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x8 */
56949   __IO uint32_t REGION0_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0xC */
56950   __IO uint32_t REGION1_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x10 */
56951   __IO uint32_t REGION1_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x14 */
56952   __IO uint32_t REGION1_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x18 */
56953   __IO uint32_t REGION1_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x1C */
56954   __IO uint32_t REGION2_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x20 */
56955   __IO uint32_t REGION2_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x24 */
56956   __IO uint32_t REGION2_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x28 */
56957   __IO uint32_t REGION2_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x2C */
56958   __IO uint32_t REGION3_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x30 */
56959   __IO uint32_t REGION3_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x34 */
56960   __IO uint32_t REGION3_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x38 */
56961   __IO uint32_t REGION3_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x3C */
56962   __IO uint32_t REGION4_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x40 */
56963   __IO uint32_t REGION4_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x44 */
56964   __IO uint32_t REGION4_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x48 */
56965   __IO uint32_t REGION4_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x4C */
56966   __IO uint32_t REGION5_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x50 */
56967   __IO uint32_t REGION5_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x54 */
56968   __IO uint32_t REGION5_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x58 */
56969   __IO uint32_t REGION5_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x5C */
56970   __IO uint32_t REGION6_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x60 */
56971   __IO uint32_t REGION6_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x64 */
56972   __IO uint32_t REGION6_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x68 */
56973   __IO uint32_t REGION6_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x6C */
56974   __IO uint32_t REGION7_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x70 */
56975   __IO uint32_t REGION7_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x74 */
56976   __IO uint32_t REGION7_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x78 */
56977   __IO uint32_t REGION7_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x7C */
56978 } IEE_APC_Type;
56979 
56980 /* ----------------------------------------------------------------------------
56981    -- IEE_APC Register Masks
56982    ---------------------------------------------------------------------------- */
56983 
56984 /*!
56985  * @addtogroup IEE_APC_Register_Masks IEE_APC Register Masks
56986  * @{
56987  */
56988 
56989 /*! @name REGION0_TOP_ADDR - End address of IEE region (n) */
56990 /*! @{ */
56991 
56992 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
56993 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
56994 /*! TOP_ADDR - End address of IEE region
56995  */
56996 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
56997 /*! @} */
56998 
56999 /*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */
57000 /*! @{ */
57001 
57002 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57003 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57004 /*! BOT_ADDR - Start address of IEE region
57005  */
57006 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
57007 /*! @} */
57008 
57009 /*! @name REGION0_RDC_D0 - Region control of core domain 0 for region (n) */
57010 /*! @{ */
57011 
57012 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57013 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57014 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57015  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57016  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57017  */
57018 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57019 
57020 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57021 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57022 /*! RDC_D0_LOCK - Lock bit for bit 0
57023  *  0b0..Bit 0 is unlocked
57024  *  0b1..Bit 0 is locked
57025  */
57026 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)
57027 /*! @} */
57028 
57029 /*! @name REGION0_RDC_D1 - Region control of core domain 1 for region (n) */
57030 /*! @{ */
57031 
57032 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57033 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57034 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57035  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57036  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57037  */
57038 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57039 
57040 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57041 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57042 /*! RDC_D1_LOCK - Lock bit for bit 0
57043  *  0b0..Bit 0 is unlocked
57044  *  0b1..Bit 0 is locked
57045  */
57046 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)
57047 /*! @} */
57048 
57049 /*! @name REGION1_TOP_ADDR - End address of IEE region (n) */
57050 /*! @{ */
57051 
57052 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57053 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57054 /*! TOP_ADDR - End address of IEE region
57055  */
57056 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
57057 /*! @} */
57058 
57059 /*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */
57060 /*! @{ */
57061 
57062 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57063 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57064 /*! BOT_ADDR - Start address of IEE region
57065  */
57066 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
57067 /*! @} */
57068 
57069 /*! @name REGION1_RDC_D0 - Region control of core domain 0 for region (n) */
57070 /*! @{ */
57071 
57072 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57073 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57074 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57075  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57076  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57077  */
57078 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57079 
57080 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57081 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57082 /*! RDC_D0_LOCK - Lock bit for bit 0
57083  *  0b0..Bit 0 is unlocked
57084  *  0b1..Bit 0 is locked
57085  */
57086 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)
57087 /*! @} */
57088 
57089 /*! @name REGION1_RDC_D1 - Region control of core domain 1 for region (n) */
57090 /*! @{ */
57091 
57092 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57093 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57094 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57095  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57096  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57097  */
57098 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57099 
57100 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57101 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57102 /*! RDC_D1_LOCK - Lock bit for bit 0
57103  *  0b0..Bit 0 is unlocked
57104  *  0b1..Bit 0 is locked
57105  */
57106 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)
57107 /*! @} */
57108 
57109 /*! @name REGION2_TOP_ADDR - End address of IEE region (n) */
57110 /*! @{ */
57111 
57112 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57113 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57114 /*! TOP_ADDR - End address of IEE region
57115  */
57116 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
57117 /*! @} */
57118 
57119 /*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */
57120 /*! @{ */
57121 
57122 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57123 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57124 /*! BOT_ADDR - Start address of IEE region
57125  */
57126 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
57127 /*! @} */
57128 
57129 /*! @name REGION2_RDC_D0 - Region control of core domain 0 for region (n) */
57130 /*! @{ */
57131 
57132 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57133 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57134 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57135  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57136  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57137  */
57138 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57139 
57140 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57141 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57142 /*! RDC_D0_LOCK - Lock bit for bit 0
57143  *  0b0..Bit 0 is unlocked
57144  *  0b1..Bit 0 is locked
57145  */
57146 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)
57147 /*! @} */
57148 
57149 /*! @name REGION2_RDC_D1 - Region control of core domain 1 for region (n) */
57150 /*! @{ */
57151 
57152 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57153 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57154 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57155  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57156  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57157  */
57158 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57159 
57160 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57161 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57162 /*! RDC_D1_LOCK - Lock bit for bit 0
57163  *  0b0..Bit 0 is unlocked
57164  *  0b1..Bit 0 is locked
57165  */
57166 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)
57167 /*! @} */
57168 
57169 /*! @name REGION3_TOP_ADDR - End address of IEE region (n) */
57170 /*! @{ */
57171 
57172 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57173 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57174 /*! TOP_ADDR - End address of IEE region
57175  */
57176 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
57177 /*! @} */
57178 
57179 /*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */
57180 /*! @{ */
57181 
57182 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57183 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57184 /*! BOT_ADDR - Start address of IEE region
57185  */
57186 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
57187 /*! @} */
57188 
57189 /*! @name REGION3_RDC_D0 - Region control of core domain 0 for region (n) */
57190 /*! @{ */
57191 
57192 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57193 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57194 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57195  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57196  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57197  */
57198 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57199 
57200 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57201 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57202 /*! RDC_D0_LOCK - Lock bit for bit 0
57203  *  0b0..Bit 0 is unlocked
57204  *  0b1..Bit 0 is locked
57205  */
57206 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)
57207 /*! @} */
57208 
57209 /*! @name REGION3_RDC_D1 - Region control of core domain 1 for region (n) */
57210 /*! @{ */
57211 
57212 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57213 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57214 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57215  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57216  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57217  */
57218 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57219 
57220 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57221 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57222 /*! RDC_D1_LOCK - Lock bit for bit 0
57223  *  0b0..Bit 0 is unlocked
57224  *  0b1..Bit 0 is locked
57225  */
57226 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)
57227 /*! @} */
57228 
57229 /*! @name REGION4_TOP_ADDR - End address of IEE region (n) */
57230 /*! @{ */
57231 
57232 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57233 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57234 /*! TOP_ADDR - End address of IEE region
57235  */
57236 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
57237 /*! @} */
57238 
57239 /*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */
57240 /*! @{ */
57241 
57242 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57243 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57244 /*! BOT_ADDR - Start address of IEE region
57245  */
57246 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
57247 /*! @} */
57248 
57249 /*! @name REGION4_RDC_D0 - Region control of core domain 0 for region (n) */
57250 /*! @{ */
57251 
57252 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57253 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57254 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57255  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57256  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57257  */
57258 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57259 
57260 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57261 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57262 /*! RDC_D0_LOCK - Lock bit for bit 0
57263  *  0b0..Bit 0 is unlocked
57264  *  0b1..Bit 0 is locked
57265  */
57266 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)
57267 /*! @} */
57268 
57269 /*! @name REGION4_RDC_D1 - Region control of core domain 1 for region (n) */
57270 /*! @{ */
57271 
57272 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57273 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57274 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57275  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57276  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57277  */
57278 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57279 
57280 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57281 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57282 /*! RDC_D1_LOCK - Lock bit for bit 0
57283  *  0b0..Bit 0 is unlocked
57284  *  0b1..Bit 0 is locked
57285  */
57286 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)
57287 /*! @} */
57288 
57289 /*! @name REGION5_TOP_ADDR - End address of IEE region (n) */
57290 /*! @{ */
57291 
57292 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57293 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57294 /*! TOP_ADDR - End address of IEE region
57295  */
57296 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
57297 /*! @} */
57298 
57299 /*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */
57300 /*! @{ */
57301 
57302 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57303 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57304 /*! BOT_ADDR - Start address of IEE region
57305  */
57306 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
57307 /*! @} */
57308 
57309 /*! @name REGION5_RDC_D0 - Region control of core domain 0 for region (n) */
57310 /*! @{ */
57311 
57312 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57313 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57314 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57315  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57316  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57317  */
57318 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57319 
57320 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57321 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57322 /*! RDC_D0_LOCK - Lock bit for bit 0
57323  *  0b0..Bit 0 is unlocked
57324  *  0b1..Bit 0 is locked
57325  */
57326 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)
57327 /*! @} */
57328 
57329 /*! @name REGION5_RDC_D1 - Region control of core domain 1 for region (n) */
57330 /*! @{ */
57331 
57332 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57333 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57334 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57335  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57336  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57337  */
57338 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57339 
57340 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57341 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57342 /*! RDC_D1_LOCK - Lock bit for bit 0
57343  *  0b0..Bit 0 is unlocked
57344  *  0b1..Bit 0 is locked
57345  */
57346 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)
57347 /*! @} */
57348 
57349 /*! @name REGION6_TOP_ADDR - End address of IEE region (n) */
57350 /*! @{ */
57351 
57352 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57353 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57354 /*! TOP_ADDR - End address of IEE region
57355  */
57356 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
57357 /*! @} */
57358 
57359 /*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */
57360 /*! @{ */
57361 
57362 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57363 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57364 /*! BOT_ADDR - Start address of IEE region
57365  */
57366 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
57367 /*! @} */
57368 
57369 /*! @name REGION6_RDC_D0 - Region control of core domain 0 for region (n) */
57370 /*! @{ */
57371 
57372 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57373 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57374 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57375  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57376  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57377  */
57378 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57379 
57380 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57381 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57382 /*! RDC_D0_LOCK - Lock bit for bit 0
57383  *  0b0..Bit 0 is unlocked
57384  *  0b1..Bit 0 is locked
57385  */
57386 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)
57387 /*! @} */
57388 
57389 /*! @name REGION6_RDC_D1 - Region control of core domain 1 for region (n) */
57390 /*! @{ */
57391 
57392 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57393 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57394 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57395  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57396  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57397  */
57398 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57399 
57400 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57401 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57402 /*! RDC_D1_LOCK - Lock bit for bit 0
57403  *  0b0..Bit 0 is unlocked
57404  *  0b1..Bit 0 is locked
57405  */
57406 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)
57407 /*! @} */
57408 
57409 /*! @name REGION7_TOP_ADDR - End address of IEE region (n) */
57410 /*! @{ */
57411 
57412 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57413 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57414 /*! TOP_ADDR - End address of IEE region
57415  */
57416 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
57417 /*! @} */
57418 
57419 /*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */
57420 /*! @{ */
57421 
57422 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57423 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57424 /*! BOT_ADDR - Start address of IEE region
57425  */
57426 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
57427 /*! @} */
57428 
57429 /*! @name REGION7_RDC_D0 - Region control of core domain 0 for region (n) */
57430 /*! @{ */
57431 
57432 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57433 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57434 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57435  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57436  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57437  */
57438 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57439 
57440 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57441 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57442 /*! RDC_D0_LOCK - Lock bit for bit 0
57443  *  0b0..Bit 0 is unlocked
57444  *  0b1..Bit 0 is locked
57445  */
57446 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)
57447 /*! @} */
57448 
57449 /*! @name REGION7_RDC_D1 - Region control of core domain 1 for region (n) */
57450 /*! @{ */
57451 
57452 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57453 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57454 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57455  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57456  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57457  */
57458 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57459 
57460 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57461 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57462 /*! RDC_D1_LOCK - Lock bit for bit 0
57463  *  0b0..Bit 0 is unlocked
57464  *  0b1..Bit 0 is locked
57465  */
57466 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)
57467 /*! @} */
57468 
57469 
57470 /*!
57471  * @}
57472  */ /* end of group IEE_APC_Register_Masks */
57473 
57474 
57475 /* IEE_APC - Peripheral instance base addresses */
57476 /** Peripheral IEE_APC base address */
57477 #define IEE_APC_BASE                             (0x40068000u)
57478 /** Peripheral IEE_APC base pointer */
57479 #define IEE_APC                                  ((IEE_APC_Type *)IEE_APC_BASE)
57480 /** Array initializer of IEE_APC peripheral base addresses */
57481 #define IEE_APC_BASE_ADDRS                       { IEE_APC_BASE }
57482 /** Array initializer of IEE_APC peripheral base pointers */
57483 #define IEE_APC_BASE_PTRS                        { IEE_APC }
57484 
57485 /*!
57486  * @}
57487  */ /* end of group IEE_APC_Peripheral_Access_Layer */
57488 
57489 
57490 /* ----------------------------------------------------------------------------
57491    -- IOMUXC Peripheral Access Layer
57492    ---------------------------------------------------------------------------- */
57493 
57494 /*!
57495  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
57496  * @{
57497  */
57498 
57499 /** IOMUXC - Register Layout Typedef */
57500 typedef struct {
57501        uint8_t RESERVED_0[16];
57502   __IO uint32_t SW_MUX_CTL_PAD[145];               /**< SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4 */
57503   __IO uint32_t SW_PAD_CTL_PAD[145];               /**< SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4 */
57504   __IO uint32_t SELECT_INPUT[160];                 /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4 */
57505 } IOMUXC_Type;
57506 
57507 /* ----------------------------------------------------------------------------
57508    -- IOMUXC Register Masks
57509    ---------------------------------------------------------------------------- */
57510 
57511 /*!
57512  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
57513  * @{
57514  */
57515 
57516 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register */
57517 /*! @{ */
57518 
57519 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0xFU)
57520 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
57521 /*! MUX_MODE - MUX Mode Select Field.
57522  *  0b0000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: SEMC
57523  *  0b0001..Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_A of instance: FLEXPWM4
57524  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX1_IO00 of instance: GPIO_MUX1
57525  *  0b1000..Select mux mode: ALT8 mux port: FLEXIO1_D00 of instance: FLEXIO1
57526  *  0b1010..Select mux mode: ALT10 mux port: GPIO7_IO00 of instance: GPIO7
57527  */
57528 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
57529 
57530 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
57531 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
57532 /*! SION - Software Input On Field.
57533  *  0b1..Force input path of pad GPIO_EMC_B1_00
57534  *  0b0..Input Path is determined by functionality
57535  */
57536 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
57537 /*! @} */
57538 
57539 /* The count of IOMUXC_SW_MUX_CTL_PAD */
57540 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (145U)
57541 
57542 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register */
57543 /*! @{ */
57544 
57545 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
57546 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
57547 /*! SRE - Slew Rate Field
57548  *  0b0..Slow Slew Rate
57549  *  0b1..Fast Slew Rate
57550  */
57551 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
57552 
57553 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x2U)
57554 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (1U)
57555 /*! DSE - Drive Strength Field
57556  *  0b0..normal drive strength
57557  *  0b1..high drive strength
57558  */
57559 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
57560 
57561 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK          (0x2U)
57562 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT         (1U)
57563 /*! PDRV - PDRV Field
57564  *  0b0..high drive strength
57565  *  0b1..normal drive strength
57566  */
57567 #define IOMUXC_SW_PAD_CTL_PAD_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
57568 
57569 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x4U)
57570 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (2U)
57571 /*! PUE - Pull / Keep Select Field
57572  *  0b0..Pull Disable, Highz
57573  *  0b1..Pull Enable
57574  */
57575 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
57576 
57577 #define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK          (0xCU)
57578 #define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT         (2U)
57579 /*! PULL - Pull Down Pull Up Field
57580  *  0b00..Forbidden
57581  *  0b01..Internal pullup resistor enabled
57582  *  0b10..Internal pulldown resistor enabled
57583  *  0b11..No Pull
57584  */
57585 #define IOMUXC_SW_PAD_CTL_PAD_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
57586 
57587 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0x8U)
57588 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (3U)
57589 /*! PUS - Pull Up / Down Config. Field
57590  *  0b0..Weak pull down
57591  *  0b1..Weak pull up
57592  */
57593 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
57594 
57595 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x10U)
57596 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (4U)
57597 /*! ODE - Open Drain Field
57598  *  0b0..Disabled
57599  *  0b1..Enabled
57600  */
57601 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
57602 
57603 #define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK           (0x30000000U)
57604 #define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT          (28U)
57605 /*! DWP - Domain write protection
57606  *  0b00..Both cores are allowed
57607  *  0b01..CM7 is forbidden
57608  *  0b10..CM4 is forbidden
57609  *  0b11..Both cores are forbidden
57610  */
57611 #define IOMUXC_SW_PAD_CTL_PAD_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
57612 
57613 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK      (0xC0000000U)
57614 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT     (30U)
57615 /*! DWP_LOCK - Domain write protection lock
57616  *  0b00..Neither of DWP bits is locked
57617  *  0b01..The lower DWP bit is locked
57618  *  0b10..The higher DWP bit is locked
57619  *  0b11..Both DWP bits are locked
57620  */
57621 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
57622 /*! @} */
57623 
57624 /* The count of IOMUXC_SW_PAD_CTL_PAD */
57625 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (145U)
57626 
57627 /*! @name SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register */
57628 /*! @{ */
57629 
57630 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
57631 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
57632 /*! DAISY - Selecting Pads Involved in Daisy Chain.
57633  *  0b00..Selecting Pad: GPIO_AD_07 for Mode: ALT1
57634  *  0b01..Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT2
57635  *  0b10..Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT6
57636  */
57637 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
57638 /*! @} */
57639 
57640 /* The count of IOMUXC_SELECT_INPUT */
57641 #define IOMUXC_SELECT_INPUT_COUNT                (160U)
57642 
57643 
57644 /*!
57645  * @}
57646  */ /* end of group IOMUXC_Register_Masks */
57647 
57648 
57649 /* IOMUXC - Peripheral instance base addresses */
57650 /** Peripheral IOMUXC base address */
57651 #define IOMUXC_BASE                              (0x400E8000u)
57652 /** Peripheral IOMUXC base pointer */
57653 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
57654 /** Array initializer of IOMUXC peripheral base addresses */
57655 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
57656 /** Array initializer of IOMUXC peripheral base pointers */
57657 #define IOMUXC_BASE_PTRS                         { IOMUXC }
57658 
57659 /*!
57660  * @}
57661  */ /* end of group IOMUXC_Peripheral_Access_Layer */
57662 
57663 
57664 /* ----------------------------------------------------------------------------
57665    -- IOMUXC_GPR Peripheral Access Layer
57666    ---------------------------------------------------------------------------- */
57667 
57668 /*!
57669  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
57670  * @{
57671  */
57672 
57673 /** IOMUXC_GPR - Register Layout Typedef */
57674 typedef struct {
57675   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
57676   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
57677   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
57678   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
57679   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
57680   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
57681   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
57682   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
57683   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
57684   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
57685   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
57686   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
57687   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
57688   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
57689   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
57690   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
57691   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
57692   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
57693   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
57694        uint8_t RESERVED_0[4];
57695   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
57696   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
57697   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
57698   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
57699   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
57700   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
57701   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
57702   __IO uint32_t GPR27;                             /**< GPR27 General Purpose Register, offset: 0x6C */
57703   __IO uint32_t GPR28;                             /**< GPR28 General Purpose Register, offset: 0x70 */
57704   __IO uint32_t GPR29;                             /**< GPR29 General Purpose Register, offset: 0x74 */
57705   __IO uint32_t GPR30;                             /**< GPR30 General Purpose Register, offset: 0x78 */
57706   __IO uint32_t GPR31;                             /**< GPR31 General Purpose Register, offset: 0x7C */
57707   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
57708   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
57709   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
57710   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
57711   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
57712   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
57713   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
57714   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
57715   __IO uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
57716   __IO uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
57717   __IO uint32_t GPR42;                             /**< GPR42 General Purpose Register, offset: 0xA8 */
57718   __IO uint32_t GPR43;                             /**< GPR43 General Purpose Register, offset: 0xAC */
57719   __IO uint32_t GPR44;                             /**< GPR44 General Purpose Register, offset: 0xB0 */
57720   __IO uint32_t GPR45;                             /**< GPR45 General Purpose Register, offset: 0xB4 */
57721   __IO uint32_t GPR46;                             /**< GPR46 General Purpose Register, offset: 0xB8 */
57722   __IO uint32_t GPR47;                             /**< GPR47 General Purpose Register, offset: 0xBC */
57723   __IO uint32_t GPR48;                             /**< GPR48 General Purpose Register, offset: 0xC0 */
57724   __IO uint32_t GPR49;                             /**< GPR49 General Purpose Register, offset: 0xC4 */
57725   __IO uint32_t GPR50;                             /**< GPR50 General Purpose Register, offset: 0xC8 */
57726   __IO uint32_t GPR51;                             /**< GPR51 General Purpose Register, offset: 0xCC */
57727   __IO uint32_t GPR52;                             /**< GPR52 General Purpose Register, offset: 0xD0 */
57728   __IO uint32_t GPR53;                             /**< GPR53 General Purpose Register, offset: 0xD4 */
57729   __IO uint32_t GPR54;                             /**< GPR54 General Purpose Register, offset: 0xD8 */
57730   __IO uint32_t GPR55;                             /**< GPR55 General Purpose Register, offset: 0xDC */
57731        uint8_t RESERVED_1[12];
57732   __IO uint32_t GPR59;                             /**< GPR59 General Purpose Register, offset: 0xEC */
57733        uint8_t RESERVED_2[8];
57734   __IO uint32_t GPR62;                             /**< GPR62 General Purpose Register, offset: 0xF8 */
57735   __I  uint32_t GPR63;                             /**< GPR63 General Purpose Register, offset: 0xFC */
57736   __IO uint32_t GPR64;                             /**< GPR64 General Purpose Register, offset: 0x100 */
57737   __IO uint32_t GPR65;                             /**< GPR65 General Purpose Register, offset: 0x104 */
57738   __IO uint32_t GPR66;                             /**< GPR66 General Purpose Register, offset: 0x108 */
57739   __IO uint32_t GPR67;                             /**< GPR67 General Purpose Register, offset: 0x10C */
57740   __IO uint32_t GPR68;                             /**< GPR68 General Purpose Register, offset: 0x110 */
57741   __IO uint32_t GPR69;                             /**< GPR69 General Purpose Register, offset: 0x114 */
57742   __IO uint32_t GPR70;                             /**< GPR70 General Purpose Register, offset: 0x118 */
57743   __IO uint32_t GPR71;                             /**< GPR71 General Purpose Register, offset: 0x11C */
57744   __IO uint32_t GPR72;                             /**< GPR72 General Purpose Register, offset: 0x120 */
57745   __IO uint32_t GPR73;                             /**< GPR73 General Purpose Register, offset: 0x124 */
57746   __IO uint32_t GPR74;                             /**< GPR74 General Purpose Register, offset: 0x128 */
57747   __I  uint32_t GPR75;                             /**< GPR75 General Purpose Register, offset: 0x12C */
57748   __I  uint32_t GPR76;                             /**< GPR76 General Purpose Register, offset: 0x130 */
57749 } IOMUXC_GPR_Type;
57750 
57751 /* ----------------------------------------------------------------------------
57752    -- IOMUXC_GPR Register Masks
57753    ---------------------------------------------------------------------------- */
57754 
57755 /*!
57756  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
57757  * @{
57758  */
57759 
57760 /*! @name GPR0 - GPR0 General Purpose Register */
57761 /*! @{ */
57762 
57763 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK      (0x7U)
57764 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT     (0U)
57765 /*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select
57766  */
57767 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
57768 
57769 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK      (0x38U)
57770 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT     (3U)
57771 /*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select
57772  */
57773 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
57774 
57775 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK      (0xC0U)
57776 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT     (6U)
57777 /*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select
57778  */
57779 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
57780 
57781 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK       (0x100U)
57782 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT      (8U)
57783 /*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control
57784  */
57785 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
57786 
57787 #define IOMUXC_GPR_GPR0_DWP_MASK                 (0x30000000U)
57788 #define IOMUXC_GPR_GPR0_DWP_SHIFT                (28U)
57789 /*! DWP - Domain write protection
57790  *  0b00..Both cores are allowed
57791  *  0b01..CM7 is forbidden
57792  *  0b10..CM4 is forbidden
57793  *  0b11..Both cores are forbidden
57794  */
57795 #define IOMUXC_GPR_GPR0_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
57796 
57797 #define IOMUXC_GPR_GPR0_DWP_LOCK_MASK            (0xC0000000U)
57798 #define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT           (30U)
57799 /*! DWP_LOCK - Domain write protection lock
57800  *  0b00..Neither of DWP bits is locked
57801  *  0b01..The lower DWP bit is locked
57802  *  0b10..The higher DWP bit is locked
57803  *  0b11..Both DWP bits are locked
57804  */
57805 #define IOMUXC_GPR_GPR0_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
57806 /*! @} */
57807 
57808 /*! @name GPR1 - GPR1 General Purpose Register */
57809 /*! @{ */
57810 
57811 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK      (0x3U)
57812 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT     (0U)
57813 /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select
57814  */
57815 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
57816 
57817 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK       (0x100U)
57818 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT      (8U)
57819 /*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control
57820  */
57821 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
57822 
57823 #define IOMUXC_GPR_GPR1_DWP_MASK                 (0x30000000U)
57824 #define IOMUXC_GPR_GPR1_DWP_SHIFT                (28U)
57825 /*! DWP - Domain write protection
57826  *  0b00..Both cores are allowed
57827  *  0b01..CM7 is forbidden
57828  *  0b10..CM4 is forbidden
57829  *  0b11..Both cores are forbidden
57830  */
57831 #define IOMUXC_GPR_GPR1_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
57832 
57833 #define IOMUXC_GPR_GPR1_DWP_LOCK_MASK            (0xC0000000U)
57834 #define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT           (30U)
57835 /*! DWP_LOCK - Domain write protection lock
57836  *  0b00..Neither of DWP bits is locked
57837  *  0b01..The lower DWP bit is locked
57838  *  0b10..The higher DWP bit is locked
57839  *  0b11..Both DWP bits are locked
57840  */
57841 #define IOMUXC_GPR_GPR1_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
57842 /*! @} */
57843 
57844 /*! @name GPR2 - GPR2 General Purpose Register */
57845 /*! @{ */
57846 
57847 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK      (0x3U)
57848 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT     (0U)
57849 /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select
57850  */
57851 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
57852 
57853 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK       (0x100U)
57854 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT      (8U)
57855 /*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control
57856  */
57857 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
57858 
57859 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK       (0x200U)
57860 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT      (9U)
57861 /*! SAI4_MCLK_DIR - SAI4_MCLK signal direction control
57862  */
57863 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
57864 
57865 #define IOMUXC_GPR_GPR2_DWP_MASK                 (0x30000000U)
57866 #define IOMUXC_GPR_GPR2_DWP_SHIFT                (28U)
57867 /*! DWP - Domain write protection
57868  *  0b00..Both cores are allowed
57869  *  0b01..CM7 is forbidden
57870  *  0b10..CM4 is forbidden
57871  *  0b11..Both cores are forbidden
57872  */
57873 #define IOMUXC_GPR_GPR2_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
57874 
57875 #define IOMUXC_GPR_GPR2_DWP_LOCK_MASK            (0xC0000000U)
57876 #define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT           (30U)
57877 /*! DWP_LOCK - Domain write protection lock
57878  *  0b00..Neither of DWP bits is locked
57879  *  0b01..The lower DWP bit is locked
57880  *  0b10..The higher DWP bit is locked
57881  *  0b11..Both DWP bits are locked
57882  */
57883 #define IOMUXC_GPR_GPR2_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
57884 /*! @} */
57885 
57886 /*! @name GPR3 - GPR3 General Purpose Register */
57887 /*! @{ */
57888 
57889 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK         (0xFFU)
57890 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT        (0U)
57891 /*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk.
57892  */
57893 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
57894 
57895 #define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK          (0x100U)
57896 #define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT         (8U)
57897 /*! MQS_SW_RST - MQS software reset
57898  */
57899 #define IOMUXC_GPR_GPR3_MQS_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
57900 
57901 #define IOMUXC_GPR_GPR3_MQS_EN_MASK              (0x200U)
57902 #define IOMUXC_GPR_GPR3_MQS_EN_SHIFT             (9U)
57903 /*! MQS_EN - MQS enable
57904  */
57905 #define IOMUXC_GPR_GPR3_MQS_EN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
57906 
57907 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK      (0x400U)
57908 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT     (10U)
57909 /*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample
57910  */
57911 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
57912 
57913 #define IOMUXC_GPR_GPR3_DWP_MASK                 (0x30000000U)
57914 #define IOMUXC_GPR_GPR3_DWP_SHIFT                (28U)
57915 /*! DWP - Domain write protection
57916  *  0b00..Both cores are allowed
57917  *  0b01..CM7 is forbidden
57918  *  0b10..CM4 is forbidden
57919  *  0b11..Both cores are forbidden
57920  */
57921 #define IOMUXC_GPR_GPR3_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
57922 
57923 #define IOMUXC_GPR_GPR3_DWP_LOCK_MASK            (0xC0000000U)
57924 #define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT           (30U)
57925 /*! DWP_LOCK - Domain write protection lock
57926  *  0b00..Neither of DWP bits is locked
57927  *  0b01..The lower DWP bit is locked
57928  *  0b10..The higher DWP bit is locked
57929  *  0b11..Both DWP bits are locked
57930  */
57931 #define IOMUXC_GPR_GPR3_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
57932 /*! @} */
57933 
57934 /*! @name GPR4 - GPR4 General Purpose Register */
57935 /*! @{ */
57936 
57937 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK     (0x1U)
57938 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT    (0U)
57939 /*! ENET_TX_CLK_SEL - ENET TX_CLK select
57940  */
57941 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
57942 
57943 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK    (0x2U)
57944 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
57945 /*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control
57946  */
57947 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
57948 
57949 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK       (0x4U)
57950 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT      (2U)
57951 /*! ENET_TIME_SEL - ENET master timer source select
57952  */
57953 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
57954 
57955 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
57956 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT  (3U)
57957 /*! ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select
57958  */
57959 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
57960 
57961 #define IOMUXC_GPR_GPR4_DWP_MASK                 (0x30000000U)
57962 #define IOMUXC_GPR_GPR4_DWP_SHIFT                (28U)
57963 /*! DWP - Domain write protection
57964  *  0b00..Both cores are allowed
57965  *  0b01..CM7 is forbidden
57966  *  0b10..CM4 is forbidden
57967  *  0b11..Both cores are forbidden
57968  */
57969 #define IOMUXC_GPR_GPR4_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
57970 
57971 #define IOMUXC_GPR_GPR4_DWP_LOCK_MASK            (0xC0000000U)
57972 #define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT           (30U)
57973 /*! DWP_LOCK - Domain write protection lock
57974  *  0b00..Neither of DWP bits is locked
57975  *  0b01..The lower DWP bit is locked
57976  *  0b10..The higher DWP bit is locked
57977  *  0b11..Both DWP bits are locked
57978  */
57979 #define IOMUXC_GPR_GPR4_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
57980 /*! @} */
57981 
57982 /*! @name GPR5 - GPR5 General Purpose Register */
57983 /*! @{ */
57984 
57985 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
57986 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT  (0U)
57987 /*! ENET1G_TX_CLK_SEL - ENET1G TX_CLK select
57988  */
57989 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
57990 
57991 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK  (0x2U)
57992 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U)
57993 /*! ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control
57994  */
57995 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
57996 
57997 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK     (0x4U)
57998 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT    (2U)
57999 /*! ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable
58000  */
58001 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
58002 
58003 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK     (0x8U)
58004 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT    (3U)
58005 /*! ENET1G_TIME_SEL - ENET1G master timer source select
58006  */
58007 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
58008 
58009 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U)
58010 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U)
58011 /*! ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select
58012  */
58013 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
58014 
58015 #define IOMUXC_GPR_GPR5_DWP_MASK                 (0x30000000U)
58016 #define IOMUXC_GPR_GPR5_DWP_SHIFT                (28U)
58017 /*! DWP - Domain write protection
58018  *  0b00..Both cores are allowed
58019  *  0b01..CM7 is forbidden
58020  *  0b10..CM4 is forbidden
58021  *  0b11..Both cores are forbidden
58022  */
58023 #define IOMUXC_GPR_GPR5_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
58024 
58025 #define IOMUXC_GPR_GPR5_DWP_LOCK_MASK            (0xC0000000U)
58026 #define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT           (30U)
58027 /*! DWP_LOCK - Domain write protection lock
58028  *  0b00..Neither of DWP bits is locked
58029  *  0b01..The lower DWP bit is locked
58030  *  0b10..The higher DWP bit is locked
58031  *  0b11..Both DWP bits are locked
58032  */
58033 #define IOMUXC_GPR_GPR5_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
58034 /*! @} */
58035 
58036 /*! @name GPR6 - GPR6 General Purpose Register */
58037 /*! @{ */
58038 
58039 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK (0x1U)
58040 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT (0U)
58041 /*! ENET_QOS_REF_CLK_DIR - ENET_QOS_REF_CLK direction control
58042  */
58043 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK)
58044 
58045 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK   (0x2U)
58046 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT  (1U)
58047 /*! ENET_QOS_RGMII_EN - ENET_QOS RGMII TX clock output enable
58048  */
58049 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK)
58050 
58051 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK   (0x4U)
58052 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT  (2U)
58053 /*! ENET_QOS_TIME_SEL - ENET_QOS master timer source select
58054  */
58055 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK)
58056 
58057 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK   (0x38U)
58058 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT  (3U)
58059 /*! ENET_QOS_INTF_SEL - ENET_QOS PHY Interface Select
58060  */
58061 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK)
58062 
58063 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK  (0x40U)
58064 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT (6U)
58065 /*! ENET_QOS_CLKGEN_EN - ENET_QOS clock generator enable
58066  */
58067 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK)
58068 
58069 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK (0x80U)
58070 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT (7U)
58071 /*! ENET_QOS_EVENT0IN_SEL - ENET_QOS ENET_1588_EVENT0_IN source select
58072  */
58073 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK)
58074 
58075 #define IOMUXC_GPR_GPR6_DWP_MASK                 (0x30000000U)
58076 #define IOMUXC_GPR_GPR6_DWP_SHIFT                (28U)
58077 /*! DWP - Domain write protection
58078  *  0b00..Both cores are allowed
58079  *  0b01..CM7 is forbidden
58080  *  0b10..CM4 is forbidden
58081  *  0b11..Both cores are forbidden
58082  */
58083 #define IOMUXC_GPR_GPR6_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_SHIFT)) & IOMUXC_GPR_GPR6_DWP_MASK)
58084 
58085 #define IOMUXC_GPR_GPR6_DWP_LOCK_MASK            (0xC0000000U)
58086 #define IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT           (30U)
58087 /*! DWP_LOCK - Domain write protection lock
58088  *  0b00..Neither of DWP bits is locked
58089  *  0b01..The lower DWP bit is locked
58090  *  0b10..The higher DWP bit is locked
58091  *  0b11..Both DWP bits are locked
58092  */
58093 #define IOMUXC_GPR_GPR6_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR6_DWP_LOCK_MASK)
58094 /*! @} */
58095 
58096 /*! @name GPR7 - GPR7 General Purpose Register */
58097 /*! @{ */
58098 
58099 #define IOMUXC_GPR_GPR7_GINT_MASK                (0x1U)
58100 #define IOMUXC_GPR_GPR7_GINT_SHIFT               (0U)
58101 /*! GINT - Global interrupt
58102  */
58103 #define IOMUXC_GPR_GPR7_GINT(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
58104 
58105 #define IOMUXC_GPR_GPR7_DWP_MASK                 (0x30000000U)
58106 #define IOMUXC_GPR_GPR7_DWP_SHIFT                (28U)
58107 /*! DWP - Domain write protection
58108  *  0b00..Both cores are allowed
58109  *  0b01..CM7 is forbidden
58110  *  0b10..CM4 is forbidden
58111  *  0b11..Both cores are forbidden
58112  */
58113 #define IOMUXC_GPR_GPR7_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
58114 
58115 #define IOMUXC_GPR_GPR7_DWP_LOCK_MASK            (0xC0000000U)
58116 #define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT           (30U)
58117 /*! DWP_LOCK - Domain write protection lock
58118  *  0b00..Neither of DWP bits is locked
58119  *  0b01..The lower DWP bit is locked
58120  *  0b10..The higher DWP bit is locked
58121  *  0b11..Both DWP bits are locked
58122  */
58123 #define IOMUXC_GPR_GPR7_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
58124 /*! @} */
58125 
58126 /*! @name GPR8 - GPR8 General Purpose Register */
58127 /*! @{ */
58128 
58129 #define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK          (0x1U)
58130 #define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT         (0U)
58131 /*! WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY
58132  */
58133 #define IOMUXC_GPR_GPR8_WDOG1_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
58134 
58135 #define IOMUXC_GPR_GPR8_DWP_MASK                 (0x30000000U)
58136 #define IOMUXC_GPR_GPR8_DWP_SHIFT                (28U)
58137 /*! DWP - Domain write protection
58138  *  0b00..Both cores are allowed
58139  *  0b01..CM7 is forbidden
58140  *  0b10..CM4 is forbidden
58141  *  0b11..Both cores are forbidden
58142  */
58143 #define IOMUXC_GPR_GPR8_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
58144 
58145 #define IOMUXC_GPR_GPR8_DWP_LOCK_MASK            (0xC0000000U)
58146 #define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT           (30U)
58147 /*! DWP_LOCK - Domain write protection lock
58148  *  0b00..Neither of DWP bits is locked
58149  *  0b01..The lower DWP bit is locked
58150  *  0b10..The higher DWP bit is locked
58151  *  0b11..Both DWP bits are locked
58152  */
58153 #define IOMUXC_GPR_GPR8_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
58154 /*! @} */
58155 
58156 /*! @name GPR9 - GPR9 General Purpose Register */
58157 /*! @{ */
58158 
58159 #define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK          (0x1U)
58160 #define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT         (0U)
58161 /*! WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY
58162  */
58163 #define IOMUXC_GPR_GPR9_WDOG2_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
58164 
58165 #define IOMUXC_GPR_GPR9_DWP_MASK                 (0x30000000U)
58166 #define IOMUXC_GPR_GPR9_DWP_SHIFT                (28U)
58167 /*! DWP - Domain write protection
58168  *  0b00..Both cores are allowed
58169  *  0b01..CM7 is forbidden
58170  *  0b10..CM4 is forbidden
58171  *  0b11..Both cores are forbidden
58172  */
58173 #define IOMUXC_GPR_GPR9_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
58174 
58175 #define IOMUXC_GPR_GPR9_DWP_LOCK_MASK            (0xC0000000U)
58176 #define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT           (30U)
58177 /*! DWP_LOCK - Domain write protection lock
58178  *  0b00..Neither of DWP bits is locked
58179  *  0b01..The lower DWP bit is locked
58180  *  0b10..The higher DWP bit is locked
58181  *  0b11..Both DWP bits are locked
58182  */
58183 #define IOMUXC_GPR_GPR9_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
58184 /*! @} */
58185 
58186 /*! @name GPR10 - GPR10 General Purpose Register */
58187 /*! @{ */
58188 
58189 #define IOMUXC_GPR_GPR10_DWP_MASK                (0x30000000U)
58190 #define IOMUXC_GPR_GPR10_DWP_SHIFT               (28U)
58191 /*! DWP - Domain write protection
58192  *  0b00..Both cores are allowed
58193  *  0b01..CM7 is forbidden
58194  *  0b10..CM4 is forbidden
58195  *  0b11..Both cores are forbidden
58196  */
58197 #define IOMUXC_GPR_GPR10_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
58198 
58199 #define IOMUXC_GPR_GPR10_DWP_LOCK_MASK           (0xC0000000U)
58200 #define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT          (30U)
58201 /*! DWP_LOCK - Domain write protection lock
58202  *  0b00..Neither of DWP bits is locked
58203  *  0b01..The lower DWP bit is locked
58204  *  0b10..The higher DWP bit is locked
58205  *  0b11..Both DWP bits are locked
58206  */
58207 #define IOMUXC_GPR_GPR10_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
58208 /*! @} */
58209 
58210 /*! @name GPR11 - GPR11 General Purpose Register */
58211 /*! @{ */
58212 
58213 #define IOMUXC_GPR_GPR11_DWP_MASK                (0x30000000U)
58214 #define IOMUXC_GPR_GPR11_DWP_SHIFT               (28U)
58215 /*! DWP - Domain write protection
58216  *  0b00..Both cores are allowed
58217  *  0b01..CM7 is forbidden
58218  *  0b10..CM4 is forbidden
58219  *  0b11..Both cores are forbidden
58220  */
58221 #define IOMUXC_GPR_GPR11_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
58222 
58223 #define IOMUXC_GPR_GPR11_DWP_LOCK_MASK           (0xC0000000U)
58224 #define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT          (30U)
58225 /*! DWP_LOCK - Domain write protection lock
58226  *  0b00..Neither of DWP bits is locked
58227  *  0b01..The lower DWP bit is locked
58228  *  0b10..The higher DWP bit is locked
58229  *  0b11..Both DWP bits are locked
58230  */
58231 #define IOMUXC_GPR_GPR11_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
58232 /*! @} */
58233 
58234 /*! @name GPR12 - GPR12 General Purpose Register */
58235 /*! @{ */
58236 
58237 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
58238 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
58239 /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze
58240  */
58241 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
58242 
58243 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U)
58244 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U)
58245 /*! QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select
58246  */
58247 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
58248 
58249 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U)
58250 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U)
58251 /*! QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select
58252  */
58253 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
58254 
58255 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U)
58256 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U)
58257 /*! QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select
58258  */
58259 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
58260 
58261 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U)
58262 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U)
58263 /*! QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select
58264  */
58265 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
58266 
58267 #define IOMUXC_GPR_GPR12_DWP_MASK                (0x30000000U)
58268 #define IOMUXC_GPR_GPR12_DWP_SHIFT               (28U)
58269 /*! DWP - Domain write protection
58270  *  0b00..Both cores are allowed
58271  *  0b01..CM7 is forbidden
58272  *  0b10..CM4 is forbidden
58273  *  0b11..Both cores are forbidden
58274  */
58275 #define IOMUXC_GPR_GPR12_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
58276 
58277 #define IOMUXC_GPR_GPR12_DWP_LOCK_MASK           (0xC0000000U)
58278 #define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT          (30U)
58279 /*! DWP_LOCK - Domain write protection lock
58280  *  0b00..Neither of DWP bits is locked
58281  *  0b01..The lower DWP bit is locked
58282  *  0b10..The higher DWP bit is locked
58283  *  0b11..Both DWP bits are locked
58284  */
58285 #define IOMUXC_GPR_GPR12_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
58286 /*! @} */
58287 
58288 /*! @name GPR13 - GPR13 General Purpose Register */
58289 /*! @{ */
58290 
58291 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U)
58292 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U)
58293 /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze
58294  */
58295 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
58296 
58297 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U)
58298 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U)
58299 /*! QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select
58300  */
58301 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
58302 
58303 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U)
58304 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U)
58305 /*! QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select
58306  */
58307 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
58308 
58309 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U)
58310 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U)
58311 /*! QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select
58312  */
58313 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
58314 
58315 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U)
58316 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U)
58317 /*! QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select
58318  */
58319 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
58320 
58321 #define IOMUXC_GPR_GPR13_DWP_MASK                (0x30000000U)
58322 #define IOMUXC_GPR_GPR13_DWP_SHIFT               (28U)
58323 /*! DWP - Domain write protection
58324  *  0b00..Both cores are allowed
58325  *  0b01..CM7 is forbidden
58326  *  0b10..CM4 is forbidden
58327  *  0b11..Both cores are forbidden
58328  */
58329 #define IOMUXC_GPR_GPR13_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
58330 
58331 #define IOMUXC_GPR_GPR13_DWP_LOCK_MASK           (0xC0000000U)
58332 #define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT          (30U)
58333 /*! DWP_LOCK - Domain write protection lock
58334  *  0b00..Neither of DWP bits is locked
58335  *  0b01..The lower DWP bit is locked
58336  *  0b10..The higher DWP bit is locked
58337  *  0b11..Both DWP bits are locked
58338  */
58339 #define IOMUXC_GPR_GPR13_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
58340 /*! @} */
58341 
58342 /*! @name GPR14 - GPR14 General Purpose Register */
58343 /*! @{ */
58344 
58345 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U)
58346 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U)
58347 /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze
58348  */
58349 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
58350 
58351 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
58352 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
58353 /*! QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select
58354  */
58355 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
58356 
58357 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
58358 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
58359 /*! QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select
58360  */
58361 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
58362 
58363 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
58364 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
58365 /*! QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select
58366  */
58367 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
58368 
58369 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
58370 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
58371 /*! QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select
58372  */
58373 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
58374 
58375 #define IOMUXC_GPR_GPR14_DWP_MASK                (0x30000000U)
58376 #define IOMUXC_GPR_GPR14_DWP_SHIFT               (28U)
58377 /*! DWP - Domain write protection
58378  *  0b00..Both cores are allowed
58379  *  0b01..CM7 is forbidden
58380  *  0b10..CM4 is forbidden
58381  *  0b11..Both cores are forbidden
58382  */
58383 #define IOMUXC_GPR_GPR14_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
58384 
58385 #define IOMUXC_GPR_GPR14_DWP_LOCK_MASK           (0xC0000000U)
58386 #define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT          (30U)
58387 /*! DWP_LOCK - Domain write protection lock
58388  *  0b00..Neither of DWP bits is locked
58389  *  0b01..The lower DWP bit is locked
58390  *  0b10..The higher DWP bit is locked
58391  *  0b11..Both DWP bits are locked
58392  */
58393 #define IOMUXC_GPR_GPR14_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
58394 /*! @} */
58395 
58396 /*! @name GPR15 - GPR15 General Purpose Register */
58397 /*! @{ */
58398 
58399 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U)
58400 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U)
58401 /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze
58402  */
58403 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
58404 
58405 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U)
58406 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U)
58407 /*! QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select
58408  */
58409 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
58410 
58411 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U)
58412 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U)
58413 /*! QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select
58414  */
58415 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
58416 
58417 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U)
58418 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U)
58419 /*! QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select
58420  */
58421 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
58422 
58423 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U)
58424 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U)
58425 /*! QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select
58426  */
58427 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
58428 
58429 #define IOMUXC_GPR_GPR15_DWP_MASK                (0x30000000U)
58430 #define IOMUXC_GPR_GPR15_DWP_SHIFT               (28U)
58431 /*! DWP - Domain write protection
58432  *  0b00..Both cores are allowed
58433  *  0b01..CM7 is forbidden
58434  *  0b10..CM4 is forbidden
58435  *  0b11..Both cores are forbidden
58436  */
58437 #define IOMUXC_GPR_GPR15_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
58438 
58439 #define IOMUXC_GPR_GPR15_DWP_LOCK_MASK           (0xC0000000U)
58440 #define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT          (30U)
58441 /*! DWP_LOCK - Domain write protection lock
58442  *  0b00..Neither of DWP bits is locked
58443  *  0b01..The lower DWP bit is locked
58444  *  0b10..The higher DWP bit is locked
58445  *  0b11..Both DWP bits are locked
58446  */
58447 #define IOMUXC_GPR_GPR15_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
58448 /*! @} */
58449 
58450 /*! @name GPR16 - GPR16 General Purpose Register */
58451 /*! @{ */
58452 
58453 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
58454 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
58455 /*! FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select
58456  */
58457 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
58458 
58459 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK  (0x8U)
58460 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U)
58461 /*! CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable
58462  */
58463 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
58464 
58465 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
58466 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT  (5U)
58467 /*! M7_GPC_SLEEP_SEL - CM7 sleep request selection
58468  */
58469 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
58470 
58471 #define IOMUXC_GPR_GPR16_DWP_MASK                (0x30000000U)
58472 #define IOMUXC_GPR_GPR16_DWP_SHIFT               (28U)
58473 /*! DWP - Domain write protection
58474  *  0b00..Both cores are allowed
58475  *  0b01..CM7 is forbidden
58476  *  0b10..CM4 is forbidden
58477  *  0b11..Both cores are forbidden
58478  */
58479 #define IOMUXC_GPR_GPR16_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
58480 
58481 #define IOMUXC_GPR_GPR16_DWP_LOCK_MASK           (0xC0000000U)
58482 #define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT          (30U)
58483 /*! DWP_LOCK - Domain write protection lock
58484  *  0b00..Neither of DWP bits is locked
58485  *  0b01..The lower DWP bit is locked
58486  *  0b10..The higher DWP bit is locked
58487  *  0b11..Both DWP bits are locked
58488  */
58489 #define IOMUXC_GPR_GPR16_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
58490 /*! @} */
58491 
58492 /*! @name GPR17 - GPR17 General Purpose Register */
58493 /*! @{ */
58494 
58495 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU)
58496 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U)
58497 /*! FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value
58498  */
58499 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
58500 
58501 #define IOMUXC_GPR_GPR17_DWP_MASK                (0x30000000U)
58502 #define IOMUXC_GPR_GPR17_DWP_SHIFT               (28U)
58503 /*! DWP - Domain write protection
58504  *  0b00..Both cores are allowed
58505  *  0b01..CM7 is forbidden
58506  *  0b10..CM4 is forbidden
58507  *  0b11..Both cores are forbidden
58508  */
58509 #define IOMUXC_GPR_GPR17_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
58510 
58511 #define IOMUXC_GPR_GPR17_DWP_LOCK_MASK           (0xC0000000U)
58512 #define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT          (30U)
58513 /*! DWP_LOCK - Domain write protection lock
58514  *  0b00..Neither of DWP bits is locked
58515  *  0b01..The lower DWP bit is locked
58516  *  0b10..The higher DWP bit is locked
58517  *  0b11..Both DWP bits are locked
58518  */
58519 #define IOMUXC_GPR_GPR17_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
58520 /*! @} */
58521 
58522 /*! @name GPR18 - GPR18 General Purpose Register */
58523 /*! @{ */
58524 
58525 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU)
58526 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U)
58527 /*! FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value
58528  */
58529 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
58530 
58531 #define IOMUXC_GPR_GPR18_DWP_MASK                (0x30000000U)
58532 #define IOMUXC_GPR_GPR18_DWP_SHIFT               (28U)
58533 /*! DWP - Domain write protection
58534  *  0b00..Both cores are allowed
58535  *  0b01..CM7 is forbidden
58536  *  0b10..CM4 is forbidden
58537  *  0b11..Both cores are forbidden
58538  */
58539 #define IOMUXC_GPR_GPR18_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
58540 
58541 #define IOMUXC_GPR_GPR18_DWP_LOCK_MASK           (0xC0000000U)
58542 #define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT          (30U)
58543 /*! DWP_LOCK - Domain write protection lock
58544  *  0b00..Neither of DWP bits is locked
58545  *  0b01..The lower DWP bit is locked
58546  *  0b10..The higher DWP bit is locked
58547  *  0b11..Both DWP bits are locked
58548  */
58549 #define IOMUXC_GPR_GPR18_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
58550 /*! @} */
58551 
58552 /*! @name GPR20 - GPR20 General Purpose Register */
58553 /*! @{ */
58554 
58555 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U)
58556 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U)
58557 /*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select
58558  */
58559 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
58560 
58561 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U)
58562 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U)
58563 /*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select
58564  */
58565 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
58566 
58567 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U)
58568 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U)
58569 /*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select
58570  */
58571 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
58572 
58573 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U)
58574 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U)
58575 /*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select
58576  */
58577 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
58578 
58579 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U)
58580 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U)
58581 /*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select
58582  */
58583 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
58584 
58585 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U)
58586 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U)
58587 /*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select
58588  */
58589 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
58590 
58591 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U)
58592 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U)
58593 /*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select
58594  */
58595 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
58596 
58597 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U)
58598 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U)
58599 /*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select
58600  */
58601 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
58602 
58603 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U)
58604 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U)
58605 /*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select
58606  */
58607 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
58608 
58609 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U)
58610 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U)
58611 /*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select
58612  */
58613 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
58614 
58615 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U)
58616 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U)
58617 /*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select
58618  */
58619 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
58620 
58621 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U)
58622 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U)
58623 /*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select
58624  */
58625 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
58626 
58627 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U)
58628 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U)
58629 /*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select
58630  */
58631 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
58632 
58633 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U)
58634 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U)
58635 /*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select
58636  */
58637 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
58638 
58639 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U)
58640 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U)
58641 /*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select
58642  */
58643 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
58644 
58645 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U)
58646 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U)
58647 /*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select
58648  */
58649 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
58650 
58651 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U)
58652 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U)
58653 /*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select
58654  */
58655 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
58656 
58657 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U)
58658 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U)
58659 /*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select
58660  */
58661 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
58662 
58663 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U)
58664 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U)
58665 /*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select
58666  */
58667 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
58668 
58669 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U)
58670 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U)
58671 /*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select
58672  */
58673 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
58674 
58675 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U)
58676 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U)
58677 /*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select
58678  */
58679 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
58680 
58681 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U)
58682 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U)
58683 /*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select
58684  */
58685 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
58686 
58687 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U)
58688 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U)
58689 /*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select
58690  */
58691 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
58692 
58693 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U)
58694 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U)
58695 /*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select
58696  */
58697 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
58698 
58699 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U)
58700 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U)
58701 /*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select
58702  */
58703 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
58704 
58705 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U)
58706 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U)
58707 /*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select
58708  */
58709 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
58710 
58711 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U)
58712 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U)
58713 /*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select
58714  */
58715 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
58716 
58717 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U)
58718 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U)
58719 /*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select
58720  */
58721 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
58722 
58723 #define IOMUXC_GPR_GPR20_DWP_MASK                (0x30000000U)
58724 #define IOMUXC_GPR_GPR20_DWP_SHIFT               (28U)
58725 /*! DWP - Domain write protection
58726  *  0b00..Both cores are allowed
58727  *  0b01..CM7 is forbidden
58728  *  0b10..CM4 is forbidden
58729  *  0b11..Both cores are forbidden
58730  */
58731 #define IOMUXC_GPR_GPR20_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
58732 
58733 #define IOMUXC_GPR_GPR20_DWP_LOCK_MASK           (0xC0000000U)
58734 #define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT          (30U)
58735 /*! DWP_LOCK - Domain write protection lock
58736  *  0b00..Neither of DWP bits is locked
58737  *  0b01..The lower DWP bit is locked
58738  *  0b10..The higher DWP bit is locked
58739  *  0b11..Both DWP bits are locked
58740  */
58741 #define IOMUXC_GPR_GPR20_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
58742 /*! @} */
58743 
58744 /*! @name GPR21 - GPR21 General Purpose Register */
58745 /*! @{ */
58746 
58747 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
58748 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
58749 /*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select
58750  */
58751 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
58752 
58753 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
58754 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
58755 /*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select
58756  */
58757 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
58758 
58759 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
58760 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
58761 /*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select
58762  */
58763 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
58764 
58765 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
58766 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
58767 /*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select
58768  */
58769 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
58770 
58771 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
58772 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
58773 /*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select
58774  */
58775 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
58776 
58777 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
58778 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
58779 /*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select
58780  */
58781 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
58782 
58783 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U)
58784 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U)
58785 /*! IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select
58786  */
58787 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
58788 
58789 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U)
58790 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U)
58791 /*! IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select
58792  */
58793 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
58794 
58795 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U)
58796 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U)
58797 /*! IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select
58798  */
58799 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
58800 
58801 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U)
58802 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U)
58803 /*! IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select
58804  */
58805 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
58806 
58807 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U)
58808 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U)
58809 /*! IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select
58810  */
58811 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
58812 
58813 #define IOMUXC_GPR_GPR21_DWP_MASK                (0x30000000U)
58814 #define IOMUXC_GPR_GPR21_DWP_SHIFT               (28U)
58815 /*! DWP - Domain write protection
58816  *  0b00..Both cores are allowed
58817  *  0b01..CM7 is forbidden
58818  *  0b10..CM4 is forbidden
58819  *  0b11..Both cores are forbidden
58820  */
58821 #define IOMUXC_GPR_GPR21_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
58822 
58823 #define IOMUXC_GPR_GPR21_DWP_LOCK_MASK           (0xC0000000U)
58824 #define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT          (30U)
58825 /*! DWP_LOCK - Domain write protection lock
58826  *  0b00..Neither of DWP bits is locked
58827  *  0b01..The lower DWP bit is locked
58828  *  0b10..The higher DWP bit is locked
58829  *  0b11..Both DWP bits are locked
58830  */
58831 #define IOMUXC_GPR_GPR21_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
58832 /*! @} */
58833 
58834 /*! @name GPR22 - GPR22 General Purpose Register */
58835 /*! @{ */
58836 
58837 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK    (0x1U)
58838 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
58839 /*! REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select
58840  */
58841 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
58842 
58843 #define IOMUXC_GPR_GPR22_DWP_MASK                (0x30000000U)
58844 #define IOMUXC_GPR_GPR22_DWP_SHIFT               (28U)
58845 /*! DWP - Domain write protection
58846  *  0b00..Both cores are allowed
58847  *  0b01..CM7 is forbidden
58848  *  0b10..CM4 is forbidden
58849  *  0b11..Both cores are forbidden
58850  */
58851 #define IOMUXC_GPR_GPR22_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
58852 
58853 #define IOMUXC_GPR_GPR22_DWP_LOCK_MASK           (0xC0000000U)
58854 #define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT          (30U)
58855 /*! DWP_LOCK - Domain write protection lock
58856  *  0b00..Neither of DWP bits is locked
58857  *  0b01..The lower DWP bit is locked
58858  *  0b10..The higher DWP bit is locked
58859  *  0b11..Both DWP bits are locked
58860  */
58861 #define IOMUXC_GPR_GPR22_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
58862 /*! @} */
58863 
58864 /*! @name GPR23 - GPR23 General Purpose Register */
58865 /*! @{ */
58866 
58867 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK    (0x1U)
58868 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
58869 /*! REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select
58870  */
58871 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
58872 
58873 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK    (0x2U)
58874 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
58875 /*! GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select
58876  */
58877 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
58878 
58879 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK    (0x4U)
58880 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
58881 /*! GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select
58882  */
58883 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
58884 
58885 #define IOMUXC_GPR_GPR23_DWP_MASK                (0x30000000U)
58886 #define IOMUXC_GPR_GPR23_DWP_SHIFT               (28U)
58887 /*! DWP - Domain write protection
58888  *  0b00..Both cores are allowed
58889  *  0b01..CM7 is forbidden
58890  *  0b10..CM4 is forbidden
58891  *  0b11..Both cores are forbidden
58892  */
58893 #define IOMUXC_GPR_GPR23_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
58894 
58895 #define IOMUXC_GPR_GPR23_DWP_LOCK_MASK           (0xC0000000U)
58896 #define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT          (30U)
58897 /*! DWP_LOCK - Domain write protection lock
58898  *  0b00..Neither of DWP bits is locked
58899  *  0b01..The lower DWP bit is locked
58900  *  0b10..The higher DWP bit is locked
58901  *  0b11..Both DWP bits are locked
58902  */
58903 #define IOMUXC_GPR_GPR23_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
58904 /*! @} */
58905 
58906 /*! @name GPR24 - GPR24 General Purpose Register */
58907 /*! @{ */
58908 
58909 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK    (0x1U)
58910 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
58911 /*! REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select
58912  */
58913 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
58914 
58915 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK    (0x2U)
58916 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
58917 /*! GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select
58918  */
58919 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
58920 
58921 #define IOMUXC_GPR_GPR24_DWP_MASK                (0x30000000U)
58922 #define IOMUXC_GPR_GPR24_DWP_SHIFT               (28U)
58923 /*! DWP - Domain write protection
58924  *  0b00..Both cores are allowed
58925  *  0b01..CM7 is forbidden
58926  *  0b10..CM4 is forbidden
58927  *  0b11..Both cores are forbidden
58928  */
58929 #define IOMUXC_GPR_GPR24_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
58930 
58931 #define IOMUXC_GPR_GPR24_DWP_LOCK_MASK           (0xC0000000U)
58932 #define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT          (30U)
58933 /*! DWP_LOCK - Domain write protection lock
58934  *  0b00..Neither of DWP bits is locked
58935  *  0b01..The lower DWP bit is locked
58936  *  0b10..The higher DWP bit is locked
58937  *  0b11..Both DWP bits are locked
58938  */
58939 #define IOMUXC_GPR_GPR24_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
58940 /*! @} */
58941 
58942 /*! @name GPR25 - GPR25 General Purpose Register */
58943 /*! @{ */
58944 
58945 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK    (0x1U)
58946 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
58947 /*! REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select
58948  */
58949 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
58950 
58951 #define IOMUXC_GPR_GPR25_DWP_MASK                (0x30000000U)
58952 #define IOMUXC_GPR_GPR25_DWP_SHIFT               (28U)
58953 /*! DWP - Domain write protection
58954  *  0b00..Both cores are allowed
58955  *  0b01..CM7 is forbidden
58956  *  0b10..CM4 is forbidden
58957  *  0b11..Both cores are forbidden
58958  */
58959 #define IOMUXC_GPR_GPR25_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
58960 
58961 #define IOMUXC_GPR_GPR25_DWP_LOCK_MASK           (0xC0000000U)
58962 #define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT          (30U)
58963 /*! DWP_LOCK - Domain write protection lock
58964  *  0b00..Neither of DWP bits is locked
58965  *  0b01..The lower DWP bit is locked
58966  *  0b10..The higher DWP bit is locked
58967  *  0b11..Both DWP bits are locked
58968  */
58969 #define IOMUXC_GPR_GPR25_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
58970 /*! @} */
58971 
58972 /*! @name GPR26 - GPR26 General Purpose Register */
58973 /*! @{ */
58974 
58975 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK    (0x1U)
58976 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
58977 /*! REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select
58978  */
58979 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
58980 
58981 #define IOMUXC_GPR_GPR26_DWP_MASK                (0x30000000U)
58982 #define IOMUXC_GPR_GPR26_DWP_SHIFT               (28U)
58983 /*! DWP - Domain write protection
58984  *  0b00..Both cores are allowed
58985  *  0b01..CM7 is forbidden
58986  *  0b10..CM4 is forbidden
58987  *  0b11..Both cores are forbidden
58988  */
58989 #define IOMUXC_GPR_GPR26_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
58990 
58991 #define IOMUXC_GPR_GPR26_DWP_LOCK_MASK           (0xC0000000U)
58992 #define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT          (30U)
58993 /*! DWP_LOCK - Domain write protection lock
58994  *  0b00..Neither of DWP bits is locked
58995  *  0b01..The lower DWP bit is locked
58996  *  0b10..The higher DWP bit is locked
58997  *  0b11..Both DWP bits are locked
58998  */
58999 #define IOMUXC_GPR_GPR26_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
59000 /*! @} */
59001 
59002 /*! @name GPR27 - GPR27 General Purpose Register */
59003 /*! @{ */
59004 
59005 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK    (0x1U)
59006 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
59007 /*! REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select
59008  */
59009 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
59010 
59011 #define IOMUXC_GPR_GPR27_DWP_MASK                (0x30000000U)
59012 #define IOMUXC_GPR_GPR27_DWP_SHIFT               (28U)
59013 /*! DWP - Domain write protection
59014  *  0b00..Both cores are allowed
59015  *  0b01..CM7 is forbidden
59016  *  0b10..CM4 is forbidden
59017  *  0b11..Both cores are forbidden
59018  */
59019 #define IOMUXC_GPR_GPR27_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
59020 
59021 #define IOMUXC_GPR_GPR27_DWP_LOCK_MASK           (0xC0000000U)
59022 #define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT          (30U)
59023 /*! DWP_LOCK - Domain write protection lock
59024  *  0b00..Neither of DWP bits is locked
59025  *  0b01..The lower DWP bit is locked
59026  *  0b10..The higher DWP bit is locked
59027  *  0b11..Both DWP bits are locked
59028  */
59029 #define IOMUXC_GPR_GPR27_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
59030 /*! @} */
59031 
59032 /*! @name GPR28 - GPR28 General Purpose Register */
59033 /*! @{ */
59034 
59035 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK      (0x1U)
59036 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT     (0U)
59037 /*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions
59038  */
59039 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
59040 
59041 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK      (0x2U)
59042 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT     (1U)
59043 /*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions
59044  */
59045 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
59046 
59047 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK       (0x20U)
59048 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT      (5U)
59049 #define IOMUXC_GPR_GPR28_CACHE_ENET1G(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
59050 
59051 #define IOMUXC_GPR_GPR28_CACHE_ENET_MASK         (0x80U)
59052 #define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT        (7U)
59053 /*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions
59054  */
59055 #define IOMUXC_GPR_GPR28_CACHE_ENET(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
59056 
59057 #define IOMUXC_GPR_GPR28_CACHE_USB_MASK          (0x2000U)
59058 #define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT         (13U)
59059 /*! CACHE_USB - USB block cacheable attribute value of AXI transactions
59060  */
59061 #define IOMUXC_GPR_GPR28_CACHE_USB(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
59062 
59063 #define IOMUXC_GPR_GPR28_DWP_MASK                (0x30000000U)
59064 #define IOMUXC_GPR_GPR28_DWP_SHIFT               (28U)
59065 /*! DWP - Domain write protection
59066  *  0b00..Both cores are allowed
59067  *  0b01..CM7 is forbidden
59068  *  0b10..CM4 is forbidden
59069  *  0b11..Both cores are forbidden
59070  */
59071 #define IOMUXC_GPR_GPR28_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
59072 
59073 #define IOMUXC_GPR_GPR28_DWP_LOCK_MASK           (0xC0000000U)
59074 #define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT          (30U)
59075 /*! DWP_LOCK - Domain write protection lock
59076  *  0b00..Neither of DWP bits is locked
59077  *  0b01..The lower DWP bit is locked
59078  *  0b10..The higher DWP bit is locked
59079  *  0b11..Both DWP bits are locked
59080  */
59081 #define IOMUXC_GPR_GPR28_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
59082 /*! @} */
59083 
59084 /*! @name GPR29 - GPR29 General Purpose Register */
59085 /*! @{ */
59086 
59087 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
59088 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
59089 /*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable
59090  */
59091 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
59092 
59093 #define IOMUXC_GPR_GPR29_DWP_MASK                (0x30000000U)
59094 #define IOMUXC_GPR_GPR29_DWP_SHIFT               (28U)
59095 /*! DWP - Domain write protection
59096  *  0b00..Both cores are allowed
59097  *  0b01..CM7 is forbidden
59098  *  0b10..CM4 is forbidden
59099  *  0b11..Both cores are forbidden
59100  */
59101 #define IOMUXC_GPR_GPR29_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
59102 
59103 #define IOMUXC_GPR_GPR29_DWP_LOCK_MASK           (0xC0000000U)
59104 #define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT          (30U)
59105 /*! DWP_LOCK - Domain write protection lock
59106  *  0b00..Neither of DWP bits is locked
59107  *  0b01..The lower DWP bit is locked
59108  *  0b10..The higher DWP bit is locked
59109  *  0b11..Both DWP bits are locked
59110  */
59111 #define IOMUXC_GPR_GPR29_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
59112 /*! @} */
59113 
59114 /*! @name GPR30 - GPR30 General Purpose Register */
59115 /*! @{ */
59116 
59117 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U)
59118 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U)
59119 /*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable
59120  */
59121 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
59122 
59123 #define IOMUXC_GPR_GPR30_DWP_MASK                (0x30000000U)
59124 #define IOMUXC_GPR_GPR30_DWP_SHIFT               (28U)
59125 /*! DWP - Domain write protection
59126  *  0b00..Both cores are allowed
59127  *  0b01..CM7 is forbidden
59128  *  0b10..CM4 is forbidden
59129  *  0b11..Both cores are forbidden
59130  */
59131 #define IOMUXC_GPR_GPR30_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
59132 
59133 #define IOMUXC_GPR_GPR30_DWP_LOCK_MASK           (0xC0000000U)
59134 #define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT          (30U)
59135 /*! DWP_LOCK - Domain write protection lock
59136  *  0b00..Neither of DWP bits is locked
59137  *  0b01..The lower DWP bit is locked
59138  *  0b10..The higher DWP bit is locked
59139  *  0b11..Both DWP bits are locked
59140  */
59141 #define IOMUXC_GPR_GPR30_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
59142 /*! @} */
59143 
59144 /*! @name GPR31 - GPR31 General Purpose Register */
59145 /*! @{ */
59146 
59147 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
59148 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
59149 /*! RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable
59150  */
59151 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
59152 
59153 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U)
59154 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U)
59155 /*! OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable
59156  */
59157 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
59158 
59159 #define IOMUXC_GPR_GPR31_DWP_MASK                (0x30000000U)
59160 #define IOMUXC_GPR_GPR31_DWP_SHIFT               (28U)
59161 /*! DWP - Domain write protection
59162  *  0b00..Both cores are allowed
59163  *  0b01..CM7 is forbidden
59164  *  0b10..CM4 is forbidden
59165  *  0b11..Both cores are forbidden
59166  */
59167 #define IOMUXC_GPR_GPR31_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
59168 
59169 #define IOMUXC_GPR_GPR31_DWP_LOCK_MASK           (0xC0000000U)
59170 #define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT          (30U)
59171 /*! DWP_LOCK - Domain write protection lock
59172  *  0b00..Neither of DWP bits is locked
59173  *  0b01..The lower DWP bit is locked
59174  *  0b10..The higher DWP bit is locked
59175  *  0b11..Both DWP bits are locked
59176  */
59177 #define IOMUXC_GPR_GPR31_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
59178 /*! @} */
59179 
59180 /*! @name GPR32 - GPR32 General Purpose Register */
59181 /*! @{ */
59182 
59183 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U)
59184 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U)
59185 /*! RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable
59186  */
59187 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
59188 
59189 #define IOMUXC_GPR_GPR32_DWP_MASK                (0x30000000U)
59190 #define IOMUXC_GPR_GPR32_DWP_SHIFT               (28U)
59191 /*! DWP - Domain write protection
59192  *  0b00..Both cores are allowed
59193  *  0b01..CM7 is forbidden
59194  *  0b10..CM4 is forbidden
59195  *  0b11..Both cores are forbidden
59196  */
59197 #define IOMUXC_GPR_GPR32_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
59198 
59199 #define IOMUXC_GPR_GPR32_DWP_LOCK_MASK           (0xC0000000U)
59200 #define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT          (30U)
59201 /*! DWP_LOCK - Domain write protection lock
59202  *  0b00..Neither of DWP bits is locked
59203  *  0b01..The lower DWP bit is locked
59204  *  0b10..The higher DWP bit is locked
59205  *  0b11..Both DWP bits are locked
59206  */
59207 #define IOMUXC_GPR_GPR32_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
59208 /*! @} */
59209 
59210 /*! @name GPR33 - GPR33 General Purpose Register */
59211 /*! @{ */
59212 
59213 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
59214 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
59215 /*! RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable
59216  */
59217 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
59218 
59219 #define IOMUXC_GPR_GPR33_DWP_MASK                (0x30000000U)
59220 #define IOMUXC_GPR_GPR33_DWP_SHIFT               (28U)
59221 /*! DWP - Domain write protection
59222  *  0b00..Both cores are allowed
59223  *  0b01..CM7 is forbidden
59224  *  0b10..CM4 is forbidden
59225  *  0b11..Both cores are forbidden
59226  */
59227 #define IOMUXC_GPR_GPR33_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
59228 
59229 #define IOMUXC_GPR_GPR33_DWP_LOCK_MASK           (0xC0000000U)
59230 #define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT          (30U)
59231 /*! DWP_LOCK - Domain write protection lock
59232  *  0b00..Neither of DWP bits is locked
59233  *  0b01..The lower DWP bit is locked
59234  *  0b10..The higher DWP bit is locked
59235  *  0b11..Both DWP bits are locked
59236  */
59237 #define IOMUXC_GPR_GPR33_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
59238 /*! @} */
59239 
59240 /*! @name GPR34 - GPR34 General Purpose Register */
59241 /*! @{ */
59242 
59243 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U)
59244 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U)
59245 /*! XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable
59246  */
59247 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
59248 
59249 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK  (0x2U)
59250 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U)
59251 /*! FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable
59252  */
59253 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
59254 
59255 #define IOMUXC_GPR_GPR34_DWP_MASK                (0x30000000U)
59256 #define IOMUXC_GPR_GPR34_DWP_SHIFT               (28U)
59257 /*! DWP - Domain write protection
59258  *  0b00..Both cores are allowed
59259  *  0b01..CM7 is forbidden
59260  *  0b10..CM4 is forbidden
59261  *  0b11..Both cores are forbidden
59262  */
59263 #define IOMUXC_GPR_GPR34_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
59264 
59265 #define IOMUXC_GPR_GPR34_DWP_LOCK_MASK           (0xC0000000U)
59266 #define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT          (30U)
59267 /*! DWP_LOCK - Domain write protection lock
59268  *  0b00..Neither of DWP bits is locked
59269  *  0b01..The lower DWP bit is locked
59270  *  0b10..The higher DWP bit is locked
59271  *  0b11..Both DWP bits are locked
59272  */
59273 #define IOMUXC_GPR_GPR34_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
59274 /*! @} */
59275 
59276 /*! @name GPR35 - GPR35 General Purpose Register */
59277 /*! @{ */
59278 
59279 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U)
59280 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U)
59281 /*! XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable
59282  */
59283 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
59284 
59285 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK  (0x2U)
59286 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U)
59287 /*! FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable
59288  */
59289 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
59290 
59291 #define IOMUXC_GPR_GPR35_DWP_MASK                (0x30000000U)
59292 #define IOMUXC_GPR_GPR35_DWP_SHIFT               (28U)
59293 /*! DWP - Domain write protection
59294  *  0b00..Both cores are allowed
59295  *  0b01..CM7 is forbidden
59296  *  0b10..CM4 is forbidden
59297  *  0b11..Both cores are forbidden
59298  */
59299 #define IOMUXC_GPR_GPR35_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
59300 
59301 #define IOMUXC_GPR_GPR35_DWP_LOCK_MASK           (0xC0000000U)
59302 #define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT          (30U)
59303 /*! DWP_LOCK - Domain write protection lock
59304  *  0b00..Neither of DWP bits is locked
59305  *  0b01..The lower DWP bit is locked
59306  *  0b10..The higher DWP bit is locked
59307  *  0b11..Both DWP bits are locked
59308  */
59309 #define IOMUXC_GPR_GPR35_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
59310 /*! @} */
59311 
59312 /*! @name GPR36 - GPR36 General Purpose Register */
59313 /*! @{ */
59314 
59315 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U)
59316 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U)
59317 /*! XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable
59318  */
59319 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
59320 
59321 #define IOMUXC_GPR_GPR36_DWP_MASK                (0x30000000U)
59322 #define IOMUXC_GPR_GPR36_DWP_SHIFT               (28U)
59323 /*! DWP - Domain write protection
59324  *  0b00..Both cores are allowed
59325  *  0b01..CM7 is forbidden
59326  *  0b10..CM4 is forbidden
59327  *  0b11..Both cores are forbidden
59328  */
59329 #define IOMUXC_GPR_GPR36_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
59330 
59331 #define IOMUXC_GPR_GPR36_DWP_LOCK_MASK           (0xC0000000U)
59332 #define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT          (30U)
59333 /*! DWP_LOCK - Domain write protection lock
59334  *  0b00..Neither of DWP bits is locked
59335  *  0b01..The lower DWP bit is locked
59336  *  0b10..The higher DWP bit is locked
59337  *  0b11..Both DWP bits are locked
59338  */
59339 #define IOMUXC_GPR_GPR36_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
59340 /*! @} */
59341 
59342 /*! @name GPR37 - GPR37 General Purpose Register */
59343 /*! @{ */
59344 
59345 #define IOMUXC_GPR_GPR37_NIDEN_MASK              (0x1U)
59346 #define IOMUXC_GPR_GPR37_NIDEN_SHIFT             (0U)
59347 /*! NIDEN - ARM non-secure (non-invasive) debug enable
59348  */
59349 #define IOMUXC_GPR_GPR37_NIDEN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
59350 
59351 #define IOMUXC_GPR_GPR37_DBG_EN_MASK             (0x2U)
59352 #define IOMUXC_GPR_GPR37_DBG_EN_SHIFT            (1U)
59353 /*! DBG_EN - ARM invasive debug enable
59354  */
59355 #define IOMUXC_GPR_GPR37_DBG_EN(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
59356 
59357 #define IOMUXC_GPR_GPR37_EXC_MON_MASK            (0x8U)
59358 #define IOMUXC_GPR_GPR37_EXC_MON_SHIFT           (3U)
59359 /*! EXC_MON - Exclusive monitor response select of illegal command
59360  */
59361 #define IOMUXC_GPR_GPR37_EXC_MON(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
59362 
59363 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK    (0x20U)
59364 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
59365 /*! M7_DBG_ACK_MASK - CM7 debug halt mask
59366  */
59367 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
59368 
59369 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK    (0x40U)
59370 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
59371 /*! M4_DBG_ACK_MASK - CM4 debug halt mask
59372  */
59373 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
59374 
59375 #define IOMUXC_GPR_GPR37_DWP_MASK                (0x30000000U)
59376 #define IOMUXC_GPR_GPR37_DWP_SHIFT               (28U)
59377 /*! DWP - Domain write protection
59378  *  0b00..Both cores are allowed
59379  *  0b01..CM7 is forbidden
59380  *  0b10..CM4 is forbidden
59381  *  0b11..Both cores are forbidden
59382  */
59383 #define IOMUXC_GPR_GPR37_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
59384 
59385 #define IOMUXC_GPR_GPR37_DWP_LOCK_MASK           (0xC0000000U)
59386 #define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT          (30U)
59387 /*! DWP_LOCK - Domain write protection lock
59388  *  0b00..Neither of DWP bits is locked
59389  *  0b01..The lower DWP bit is locked
59390  *  0b10..The higher DWP bit is locked
59391  *  0b11..Both DWP bits are locked
59392  */
59393 #define IOMUXC_GPR_GPR37_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
59394 /*! @} */
59395 
59396 /*! @name GPR38 - GPR38 General Purpose Register */
59397 /*! @{ */
59398 
59399 #define IOMUXC_GPR_GPR38_DWP_MASK                (0x30000000U)
59400 #define IOMUXC_GPR_GPR38_DWP_SHIFT               (28U)
59401 /*! DWP - Domain write protection
59402  *  0b00..Both cores are allowed
59403  *  0b01..CM7 is forbidden
59404  *  0b10..CM4 is forbidden
59405  *  0b11..Both cores are forbidden
59406  */
59407 #define IOMUXC_GPR_GPR38_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
59408 
59409 #define IOMUXC_GPR_GPR38_DWP_LOCK_MASK           (0xC0000000U)
59410 #define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT          (30U)
59411 /*! DWP_LOCK - Domain write protection lock
59412  *  0b00..Neither of DWP bits is locked
59413  *  0b01..The lower DWP bit is locked
59414  *  0b10..The higher DWP bit is locked
59415  *  0b11..Both DWP bits are locked
59416  */
59417 #define IOMUXC_GPR_GPR38_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
59418 /*! @} */
59419 
59420 /*! @name GPR39 - GPR39 General Purpose Register */
59421 /*! @{ */
59422 
59423 #define IOMUXC_GPR_GPR39_DWP_MASK                (0x30000000U)
59424 #define IOMUXC_GPR_GPR39_DWP_SHIFT               (28U)
59425 /*! DWP - Domain write protection
59426  *  0b00..Both cores are allowed
59427  *  0b01..CM7 is forbidden
59428  *  0b10..CM4 is forbidden
59429  *  0b11..Both cores are forbidden
59430  */
59431 #define IOMUXC_GPR_GPR39_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
59432 
59433 #define IOMUXC_GPR_GPR39_DWP_LOCK_MASK           (0xC0000000U)
59434 #define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT          (30U)
59435 /*! DWP_LOCK - Domain write protection lock
59436  *  0b00..Neither of DWP bits is locked
59437  *  0b01..The lower DWP bit is locked
59438  *  0b10..The higher DWP bit is locked
59439  *  0b11..Both DWP bits are locked
59440  */
59441 #define IOMUXC_GPR_GPR39_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
59442 /*! @} */
59443 
59444 /*! @name GPR40 - GPR40 General Purpose Register */
59445 /*! @{ */
59446 
59447 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU)
59448 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U)
59449 /*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
59450  */
59451 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
59452 
59453 #define IOMUXC_GPR_GPR40_DWP_MASK                (0x30000000U)
59454 #define IOMUXC_GPR_GPR40_DWP_SHIFT               (28U)
59455 /*! DWP - Domain write protection
59456  *  0b00..Both cores are allowed
59457  *  0b01..CM7 is forbidden
59458  *  0b10..CM4 is forbidden
59459  *  0b11..Both cores are forbidden
59460  */
59461 #define IOMUXC_GPR_GPR40_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
59462 
59463 #define IOMUXC_GPR_GPR40_DWP_LOCK_MASK           (0xC0000000U)
59464 #define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT          (30U)
59465 /*! DWP_LOCK - Domain write protection lock
59466  *  0b00..Neither of DWP bits is locked
59467  *  0b01..The lower DWP bit is locked
59468  *  0b10..The higher DWP bit is locked
59469  *  0b11..Both DWP bits are locked
59470  */
59471 #define IOMUXC_GPR_GPR40_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
59472 /*! @} */
59473 
59474 /*! @name GPR41 - GPR41 General Purpose Register */
59475 /*! @{ */
59476 
59477 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU)
59478 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U)
59479 /*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
59480  */
59481 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
59482 
59483 #define IOMUXC_GPR_GPR41_DWP_MASK                (0x30000000U)
59484 #define IOMUXC_GPR_GPR41_DWP_SHIFT               (28U)
59485 /*! DWP - Domain write protection
59486  *  0b00..Both cores are allowed
59487  *  0b01..CM7 is forbidden
59488  *  0b10..CM4 is forbidden
59489  *  0b11..Both cores are forbidden
59490  */
59491 #define IOMUXC_GPR_GPR41_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
59492 
59493 #define IOMUXC_GPR_GPR41_DWP_LOCK_MASK           (0xC0000000U)
59494 #define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT          (30U)
59495 /*! DWP_LOCK - Domain write protection lock
59496  *  0b00..Neither of DWP bits is locked
59497  *  0b01..The lower DWP bit is locked
59498  *  0b10..The higher DWP bit is locked
59499  *  0b11..Both DWP bits are locked
59500  */
59501 #define IOMUXC_GPR_GPR41_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
59502 /*! @} */
59503 
59504 /*! @name GPR42 - GPR42 General Purpose Register */
59505 /*! @{ */
59506 
59507 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU)
59508 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U)
59509 /*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
59510  */
59511 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
59512 
59513 #define IOMUXC_GPR_GPR42_DWP_MASK                (0x30000000U)
59514 #define IOMUXC_GPR_GPR42_DWP_SHIFT               (28U)
59515 /*! DWP - Domain write protection
59516  *  0b00..Both cores are allowed
59517  *  0b01..CM7 is forbidden
59518  *  0b10..CM4 is forbidden
59519  *  0b11..Both cores are forbidden
59520  */
59521 #define IOMUXC_GPR_GPR42_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
59522 
59523 #define IOMUXC_GPR_GPR42_DWP_LOCK_MASK           (0xC0000000U)
59524 #define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT          (30U)
59525 /*! DWP_LOCK - Domain write protection lock
59526  *  0b00..Neither of DWP bits is locked
59527  *  0b01..The lower DWP bit is locked
59528  *  0b10..The higher DWP bit is locked
59529  *  0b11..Both DWP bits are locked
59530  */
59531 #define IOMUXC_GPR_GPR42_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
59532 /*! @} */
59533 
59534 /*! @name GPR43 - GPR43 General Purpose Register */
59535 /*! @{ */
59536 
59537 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU)
59538 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U)
59539 /*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
59540  */
59541 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
59542 
59543 #define IOMUXC_GPR_GPR43_DWP_MASK                (0x30000000U)
59544 #define IOMUXC_GPR_GPR43_DWP_SHIFT               (28U)
59545 /*! DWP - Domain write protection
59546  *  0b00..Both cores are allowed
59547  *  0b01..CM7 is forbidden
59548  *  0b10..CM4 is forbidden
59549  *  0b11..Both cores are forbidden
59550  */
59551 #define IOMUXC_GPR_GPR43_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
59552 
59553 #define IOMUXC_GPR_GPR43_DWP_LOCK_MASK           (0xC0000000U)
59554 #define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT          (30U)
59555 /*! DWP_LOCK - Domain write protection lock
59556  *  0b00..Neither of DWP bits is locked
59557  *  0b01..The lower DWP bit is locked
59558  *  0b10..The higher DWP bit is locked
59559  *  0b11..Both DWP bits are locked
59560  */
59561 #define IOMUXC_GPR_GPR43_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
59562 /*! @} */
59563 
59564 /*! @name GPR44 - GPR44 General Purpose Register */
59565 /*! @{ */
59566 
59567 #define IOMUXC_GPR_GPR44_DWP_MASK                (0x30000000U)
59568 #define IOMUXC_GPR_GPR44_DWP_SHIFT               (28U)
59569 /*! DWP - Domain write protection
59570  *  0b00..Both cores are allowed
59571  *  0b01..CM7 is forbidden
59572  *  0b10..CM4 is forbidden
59573  *  0b11..Both cores are forbidden
59574  */
59575 #define IOMUXC_GPR_GPR44_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
59576 
59577 #define IOMUXC_GPR_GPR44_DWP_LOCK_MASK           (0xC0000000U)
59578 #define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT          (30U)
59579 /*! DWP_LOCK - Domain write protection lock
59580  *  0b00..Neither of DWP bits is locked
59581  *  0b01..The lower DWP bit is locked
59582  *  0b10..The higher DWP bit is locked
59583  *  0b11..Both DWP bits are locked
59584  */
59585 #define IOMUXC_GPR_GPR44_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
59586 /*! @} */
59587 
59588 /*! @name GPR45 - GPR45 General Purpose Register */
59589 /*! @{ */
59590 
59591 #define IOMUXC_GPR_GPR45_DWP_MASK                (0x30000000U)
59592 #define IOMUXC_GPR_GPR45_DWP_SHIFT               (28U)
59593 /*! DWP - Domain write protection
59594  *  0b00..Both cores are allowed
59595  *  0b01..CM7 is forbidden
59596  *  0b10..CM4 is forbidden
59597  *  0b11..Both cores are forbidden
59598  */
59599 #define IOMUXC_GPR_GPR45_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
59600 
59601 #define IOMUXC_GPR_GPR45_DWP_LOCK_MASK           (0xC0000000U)
59602 #define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT          (30U)
59603 /*! DWP_LOCK - Domain write protection lock
59604  *  0b00..Neither of DWP bits is locked
59605  *  0b01..The lower DWP bit is locked
59606  *  0b10..The higher DWP bit is locked
59607  *  0b11..Both DWP bits are locked
59608  */
59609 #define IOMUXC_GPR_GPR45_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
59610 /*! @} */
59611 
59612 /*! @name GPR46 - GPR46 General Purpose Register */
59613 /*! @{ */
59614 
59615 #define IOMUXC_GPR_GPR46_DWP_MASK                (0x30000000U)
59616 #define IOMUXC_GPR_GPR46_DWP_SHIFT               (28U)
59617 /*! DWP - Domain write protection
59618  *  0b00..Both cores are allowed
59619  *  0b01..CM7 is forbidden
59620  *  0b10..CM4 is forbidden
59621  *  0b11..Both cores are forbidden
59622  */
59623 #define IOMUXC_GPR_GPR46_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
59624 
59625 #define IOMUXC_GPR_GPR46_DWP_LOCK_MASK           (0xC0000000U)
59626 #define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT          (30U)
59627 /*! DWP_LOCK - Domain write protection lock
59628  *  0b00..Neither of DWP bits is locked
59629  *  0b01..The lower DWP bit is locked
59630  *  0b10..The higher DWP bit is locked
59631  *  0b11..Both DWP bits are locked
59632  */
59633 #define IOMUXC_GPR_GPR46_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
59634 /*! @} */
59635 
59636 /*! @name GPR47 - GPR47 General Purpose Register */
59637 /*! @{ */
59638 
59639 #define IOMUXC_GPR_GPR47_DWP_MASK                (0x30000000U)
59640 #define IOMUXC_GPR_GPR47_DWP_SHIFT               (28U)
59641 /*! DWP - Domain write protection
59642  *  0b00..Both cores are allowed
59643  *  0b01..CM7 is forbidden
59644  *  0b10..CM4 is forbidden
59645  *  0b11..Both cores are forbidden
59646  */
59647 #define IOMUXC_GPR_GPR47_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
59648 
59649 #define IOMUXC_GPR_GPR47_DWP_LOCK_MASK           (0xC0000000U)
59650 #define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT          (30U)
59651 /*! DWP_LOCK - Domain write protection lock
59652  *  0b00..Neither of DWP bits is locked
59653  *  0b01..The lower DWP bit is locked
59654  *  0b10..The higher DWP bit is locked
59655  *  0b11..Both DWP bits are locked
59656  */
59657 #define IOMUXC_GPR_GPR47_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
59658 /*! @} */
59659 
59660 /*! @name GPR48 - GPR48 General Purpose Register */
59661 /*! @{ */
59662 
59663 #define IOMUXC_GPR_GPR48_DWP_MASK                (0x30000000U)
59664 #define IOMUXC_GPR_GPR48_DWP_SHIFT               (28U)
59665 /*! DWP - Domain write protection
59666  *  0b00..Both cores are allowed
59667  *  0b01..CM7 is forbidden
59668  *  0b10..CM4 is forbidden
59669  *  0b11..Both cores are forbidden
59670  */
59671 #define IOMUXC_GPR_GPR48_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
59672 
59673 #define IOMUXC_GPR_GPR48_DWP_LOCK_MASK           (0xC0000000U)
59674 #define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT          (30U)
59675 /*! DWP_LOCK - Domain write protection lock
59676  *  0b00..Neither of DWP bits is locked
59677  *  0b01..The lower DWP bit is locked
59678  *  0b10..The higher DWP bit is locked
59679  *  0b11..Both DWP bits are locked
59680  */
59681 #define IOMUXC_GPR_GPR48_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
59682 /*! @} */
59683 
59684 /*! @name GPR49 - GPR49 General Purpose Register */
59685 /*! @{ */
59686 
59687 #define IOMUXC_GPR_GPR49_DWP_MASK                (0x30000000U)
59688 #define IOMUXC_GPR_GPR49_DWP_SHIFT               (28U)
59689 /*! DWP - Domain write protection
59690  *  0b00..Both cores are allowed
59691  *  0b01..CM7 is forbidden
59692  *  0b10..CM4 is forbidden
59693  *  0b11..Both cores are forbidden
59694  */
59695 #define IOMUXC_GPR_GPR49_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
59696 
59697 #define IOMUXC_GPR_GPR49_DWP_LOCK_MASK           (0xC0000000U)
59698 #define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT          (30U)
59699 /*! DWP_LOCK - Domain write protection lock
59700  *  0b00..Neither of DWP bits is locked
59701  *  0b01..The lower DWP bit is locked
59702  *  0b10..The higher DWP bit is locked
59703  *  0b11..Both DWP bits are locked
59704  */
59705 #define IOMUXC_GPR_GPR49_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
59706 /*! @} */
59707 
59708 /*! @name GPR50 - GPR50 General Purpose Register */
59709 /*! @{ */
59710 
59711 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK       (0x1FU)
59712 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT      (0U)
59713 /*! CAAM_IPS_MGR - CAAM manager processor identifier
59714  */
59715 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
59716 
59717 #define IOMUXC_GPR_GPR50_DWP_MASK                (0x30000000U)
59718 #define IOMUXC_GPR_GPR50_DWP_SHIFT               (28U)
59719 /*! DWP - Domain write protection
59720  *  0b00..Both cores are allowed
59721  *  0b01..CM7 is forbidden
59722  *  0b10..CM4 is forbidden
59723  *  0b11..Both cores are forbidden
59724  */
59725 #define IOMUXC_GPR_GPR50_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
59726 
59727 #define IOMUXC_GPR_GPR50_DWP_LOCK_MASK           (0xC0000000U)
59728 #define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT          (30U)
59729 /*! DWP_LOCK - Domain write protection lock
59730  *  0b00..Neither of DWP bits is locked
59731  *  0b01..The lower DWP bit is locked
59732  *  0b10..The higher DWP bit is locked
59733  *  0b11..Both DWP bits are locked
59734  */
59735 #define IOMUXC_GPR_GPR50_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
59736 /*! @} */
59737 
59738 /*! @name GPR51 - GPR51 General Purpose Register */
59739 /*! @{ */
59740 
59741 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK       (0x1U)
59742 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT      (0U)
59743 /*! M7_NMI_CLEAR - Clear CM7 NMI holding register
59744  */
59745 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
59746 
59747 #define IOMUXC_GPR_GPR51_DWP_MASK                (0x30000000U)
59748 #define IOMUXC_GPR_GPR51_DWP_SHIFT               (28U)
59749 /*! DWP - Domain write protection
59750  *  0b00..Both cores are allowed
59751  *  0b01..CM7 is forbidden
59752  *  0b10..CM4 is forbidden
59753  *  0b11..Both cores are forbidden
59754  */
59755 #define IOMUXC_GPR_GPR51_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
59756 
59757 #define IOMUXC_GPR_GPR51_DWP_LOCK_MASK           (0xC0000000U)
59758 #define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT          (30U)
59759 /*! DWP_LOCK - Domain write protection lock
59760  *  0b00..Neither of DWP bits is locked
59761  *  0b01..The lower DWP bit is locked
59762  *  0b10..The higher DWP bit is locked
59763  *  0b11..Both DWP bits are locked
59764  */
59765 #define IOMUXC_GPR_GPR51_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
59766 /*! @} */
59767 
59768 /*! @name GPR52 - GPR52 General Purpose Register */
59769 /*! @{ */
59770 
59771 #define IOMUXC_GPR_GPR52_DWP_MASK                (0x30000000U)
59772 #define IOMUXC_GPR_GPR52_DWP_SHIFT               (28U)
59773 /*! DWP - Domain write protection
59774  *  0b00..Both cores are allowed
59775  *  0b01..CM7 is forbidden
59776  *  0b10..CM4 is forbidden
59777  *  0b11..Both cores are forbidden
59778  */
59779 #define IOMUXC_GPR_GPR52_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
59780 
59781 #define IOMUXC_GPR_GPR52_DWP_LOCK_MASK           (0xC0000000U)
59782 #define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT          (30U)
59783 /*! DWP_LOCK - Domain write protection lock
59784  *  0b00..Neither of DWP bits is locked
59785  *  0b01..The lower DWP bit is locked
59786  *  0b10..The higher DWP bit is locked
59787  *  0b11..Both DWP bits are locked
59788  */
59789 #define IOMUXC_GPR_GPR52_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
59790 /*! @} */
59791 
59792 /*! @name GPR53 - GPR53 General Purpose Register */
59793 /*! @{ */
59794 
59795 #define IOMUXC_GPR_GPR53_DWP_MASK                (0x30000000U)
59796 #define IOMUXC_GPR_GPR53_DWP_SHIFT               (28U)
59797 /*! DWP - Domain write protection
59798  *  0b00..Both cores are allowed
59799  *  0b01..CM7 is forbidden
59800  *  0b10..CM4 is forbidden
59801  *  0b11..Both cores are forbidden
59802  */
59803 #define IOMUXC_GPR_GPR53_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
59804 
59805 #define IOMUXC_GPR_GPR53_DWP_LOCK_MASK           (0xC0000000U)
59806 #define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT          (30U)
59807 /*! DWP_LOCK - Domain write protection lock
59808  *  0b00..Neither of DWP bits is locked
59809  *  0b01..The lower DWP bit is locked
59810  *  0b10..The higher DWP bit is locked
59811  *  0b11..Both DWP bits are locked
59812  */
59813 #define IOMUXC_GPR_GPR53_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
59814 /*! @} */
59815 
59816 /*! @name GPR54 - GPR54 General Purpose Register */
59817 /*! @{ */
59818 
59819 #define IOMUXC_GPR_GPR54_DWP_MASK                (0x30000000U)
59820 #define IOMUXC_GPR_GPR54_DWP_SHIFT               (28U)
59821 /*! DWP - Domain write protection
59822  *  0b00..Both cores are allowed
59823  *  0b01..CM7 is forbidden
59824  *  0b10..CM4 is forbidden
59825  *  0b11..Both cores are forbidden
59826  */
59827 #define IOMUXC_GPR_GPR54_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
59828 
59829 #define IOMUXC_GPR_GPR54_DWP_LOCK_MASK           (0xC0000000U)
59830 #define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT          (30U)
59831 /*! DWP_LOCK - Domain write protection lock
59832  *  0b00..Neither of DWP bits is locked
59833  *  0b01..The lower DWP bit is locked
59834  *  0b10..The higher DWP bit is locked
59835  *  0b11..Both DWP bits are locked
59836  */
59837 #define IOMUXC_GPR_GPR54_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
59838 /*! @} */
59839 
59840 /*! @name GPR55 - GPR55 General Purpose Register */
59841 /*! @{ */
59842 
59843 #define IOMUXC_GPR_GPR55_DWP_MASK                (0x30000000U)
59844 #define IOMUXC_GPR_GPR55_DWP_SHIFT               (28U)
59845 /*! DWP - Domain write protection
59846  *  0b00..Both cores are allowed
59847  *  0b01..CM7 is forbidden
59848  *  0b10..CM4 is forbidden
59849  *  0b11..Both cores are forbidden
59850  */
59851 #define IOMUXC_GPR_GPR55_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
59852 
59853 #define IOMUXC_GPR_GPR55_DWP_LOCK_MASK           (0xC0000000U)
59854 #define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT          (30U)
59855 /*! DWP_LOCK - Domain write protection lock
59856  *  0b00..Neither of DWP bits is locked
59857  *  0b01..The lower DWP bit is locked
59858  *  0b10..The higher DWP bit is locked
59859  *  0b11..Both DWP bits are locked
59860  */
59861 #define IOMUXC_GPR_GPR55_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
59862 /*! @} */
59863 
59864 /*! @name GPR59 - GPR59 General Purpose Register */
59865 /*! @{ */
59866 
59867 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U)
59868 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U)
59869 /*! MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.
59870  */
59871 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
59872 
59873 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U)
59874 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U)
59875 /*! MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit
59876  *  0b0..Assert reset
59877  *  0b1..De-assert reset
59878  */
59879 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
59880 
59881 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U)
59882 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U)
59883 /*! MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state
59884  *    during continuous clock mode operation, despite line glitches.
59885  */
59886 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
59887 
59888 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U)
59889 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U)
59890 /*! MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS
59891  */
59892 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
59893 
59894 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK     (0x10U)
59895 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT    (4U)
59896 /*! MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY.
59897  */
59898 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
59899 
59900 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U)
59901 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U)
59902 /*! MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable
59903  */
59904 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
59905 
59906 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
59907 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT  (6U)
59908 /*! MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits
59909  */
59910 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
59911 
59912 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK    (0x300U)
59913 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
59914 /*! MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01
59915  *  0b00..344mV
59916  *  0b01..325mV (Default)
59917  *  0b10..307mV
59918  *  0b11..Invalid
59919  */
59920 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
59921 
59922 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK    (0xC00U)
59923 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
59924 /*! MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01
59925  */
59926 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
59927 
59928 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U)
59929 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U)
59930 /*! MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE.
59931  */
59932 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
59933 
59934 #define IOMUXC_GPR_GPR59_DWP_MASK                (0x30000000U)
59935 #define IOMUXC_GPR_GPR59_DWP_SHIFT               (28U)
59936 /*! DWP - Domain write protection
59937  *  0b00..Both cores are allowed
59938  *  0b01..CM7 is forbidden
59939  *  0b10..CM4 is forbidden
59940  *  0b11..Both cores are forbidden
59941  */
59942 #define IOMUXC_GPR_GPR59_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
59943 
59944 #define IOMUXC_GPR_GPR59_DWP_LOCK_MASK           (0xC0000000U)
59945 #define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT          (30U)
59946 /*! DWP_LOCK - Domain write protection lock
59947  *  0b00..Neither of DWP bits is locked
59948  *  0b01..The lower DWP bit is locked
59949  *  0b10..The higher DWP bit is locked
59950  *  0b11..Both DWP bits are locked
59951  */
59952 #define IOMUXC_GPR_GPR59_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
59953 /*! @} */
59954 
59955 /*! @name GPR62 - GPR62 General Purpose Register */
59956 /*! @{ */
59957 
59958 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK    (0x7U)
59959 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
59960 /*! MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits
59961  */
59962 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
59963 
59964 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK     (0x38U)
59965 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT    (3U)
59966 /*! MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits
59967  */
59968 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
59969 
59970 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK     (0x1C0U)
59971 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT    (6U)
59972 /*! MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits
59973  */
59974 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
59975 
59976 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
59977 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT  (9U)
59978 /*! MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits
59979  */
59980 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
59981 
59982 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U)
59983 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U)
59984 /*! MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable
59985  */
59986 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
59987 
59988 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U)
59989 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U)
59990 /*! MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit
59991  *  0b0..Assert reset
59992  *  0b1..De-assert reset
59993  */
59994 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
59995 
59996 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U)
59997 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U)
59998 /*! MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit
59999  *  0b0..Assert reset
60000  *  0b1..De-assert reset
60001  */
60002 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
60003 
60004 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U)
60005 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U)
60006 /*! MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit
60007  *  0b0..Assert reset
60008  *  0b1..De-assert reset
60009  */
60010 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
60011 
60012 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U)
60013 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U)
60014 /*! MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit
60015  *  0b0..Assert reset
60016  *  0b1..De-assert reset
60017  */
60018 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
60019 
60020 #define IOMUXC_GPR_GPR62_DWP_MASK                (0x30000000U)
60021 #define IOMUXC_GPR_GPR62_DWP_SHIFT               (28U)
60022 /*! DWP - Domain write protection
60023  *  0b00..Both cores are allowed
60024  *  0b01..CM7 is forbidden
60025  *  0b10..CM4 is forbidden
60026  *  0b11..Both cores are forbidden
60027  */
60028 #define IOMUXC_GPR_GPR62_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
60029 
60030 #define IOMUXC_GPR_GPR62_DWP_LOCK_MASK           (0xC0000000U)
60031 #define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT          (30U)
60032 /*! DWP_LOCK - Domain write protection lock
60033  *  0b00..Neither of DWP bits is locked
60034  *  0b01..The lower DWP bit is locked
60035  *  0b10..The higher DWP bit is locked
60036  *  0b11..Both DWP bits are locked
60037  */
60038 #define IOMUXC_GPR_GPR62_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
60039 /*! @} */
60040 
60041 /*! @name GPR63 - GPR63 General Purpose Register */
60042 /*! @{ */
60043 
60044 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U)
60045 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U)
60046 /*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag
60047  */
60048 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
60049 /*! @} */
60050 
60051 /*! @name GPR64 - GPR64 General Purpose Register */
60052 /*! @{ */
60053 
60054 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK  (0x1U)
60055 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U)
60056 /*! GPIO_DISP1_FREEZE - Compensation code freeze
60057  */
60058 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
60059 
60060 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK  (0x2U)
60061 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U)
60062 /*! GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60063  */
60064 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
60065 
60066 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK  (0x4U)
60067 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U)
60068 /*! GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60069  */
60070 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
60071 
60072 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U)
60073 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U)
60074 /*! GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze
60075  */
60076 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
60077 
60078 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK  (0xF0U)
60079 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U)
60080 /*! GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core
60081  */
60082 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
60083 
60084 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK  (0xF00U)
60085 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U)
60086 /*! GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core
60087  */
60088 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
60089 
60090 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U)
60091 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U)
60092 /*! GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection
60093  */
60094 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
60095 
60096 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U)
60097 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U)
60098 /*! GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable
60099  */
60100 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
60101 
60102 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U)
60103 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U)
60104 /*! GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable
60105  */
60106 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
60107 
60108 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK  (0x100000U)
60109 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U)
60110 /*! GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag
60111  */
60112 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
60113 
60114 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
60115 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT  (21U)
60116 /*! GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes
60117  */
60118 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
60119 
60120 #define IOMUXC_GPR_GPR64_DWP_MASK                (0x30000000U)
60121 #define IOMUXC_GPR_GPR64_DWP_SHIFT               (28U)
60122 /*! DWP - Domain write protection
60123  *  0b00..Both cores are allowed
60124  *  0b01..CM7 is forbidden
60125  *  0b10..CM4 is forbidden
60126  *  0b11..Both cores are forbidden
60127  */
60128 #define IOMUXC_GPR_GPR64_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
60129 
60130 #define IOMUXC_GPR_GPR64_DWP_LOCK_MASK           (0xC0000000U)
60131 #define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT          (30U)
60132 /*! DWP_LOCK - Domain write protection lock
60133  *  0b00..Neither of DWP bits is locked
60134  *  0b01..The lower DWP bit is locked
60135  *  0b10..The higher DWP bit is locked
60136  *  0b11..Both DWP bits are locked
60137  */
60138 #define IOMUXC_GPR_GPR64_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
60139 /*! @} */
60140 
60141 /*! @name GPR65 - GPR65 General Purpose Register */
60142 /*! @{ */
60143 
60144 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
60145 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT  (0U)
60146 /*! GPIO_EMC1_FREEZE - Compensation code freeze
60147  */
60148 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
60149 
60150 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
60151 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT  (1U)
60152 /*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60153  */
60154 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
60155 
60156 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
60157 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT  (2U)
60158 /*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60159  */
60160 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
60161 
60162 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
60163 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
60164 /*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze
60165  */
60166 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
60167 
60168 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
60169 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT  (4U)
60170 /*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core
60171  */
60172 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
60173 
60174 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
60175 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT  (8U)
60176 /*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core
60177  */
60178 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
60179 
60180 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
60181 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
60182 /*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection
60183  */
60184 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
60185 
60186 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
60187 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
60188 /*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable
60189  */
60190 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
60191 
60192 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
60193 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
60194 /*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable
60195  */
60196 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
60197 
60198 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
60199 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT  (20U)
60200 /*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag
60201  */
60202 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
60203 
60204 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK    (0x1E00000U)
60205 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
60206 /*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes
60207  */
60208 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
60209 
60210 #define IOMUXC_GPR_GPR65_DWP_MASK                (0x30000000U)
60211 #define IOMUXC_GPR_GPR65_DWP_SHIFT               (28U)
60212 /*! DWP - Domain write protection
60213  *  0b00..Both cores are allowed
60214  *  0b01..CM7 is forbidden
60215  *  0b10..CM4 is forbidden
60216  *  0b11..Both cores are forbidden
60217  */
60218 #define IOMUXC_GPR_GPR65_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
60219 
60220 #define IOMUXC_GPR_GPR65_DWP_LOCK_MASK           (0xC0000000U)
60221 #define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT          (30U)
60222 /*! DWP_LOCK - Domain write protection lock
60223  *  0b00..Neither of DWP bits is locked
60224  *  0b01..The lower DWP bit is locked
60225  *  0b10..The higher DWP bit is locked
60226  *  0b11..Both DWP bits are locked
60227  */
60228 #define IOMUXC_GPR_GPR65_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
60229 /*! @} */
60230 
60231 /*! @name GPR66 - GPR66 General Purpose Register */
60232 /*! @{ */
60233 
60234 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
60235 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT  (0U)
60236 /*! GPIO_EMC2_FREEZE - Compensation code freeze
60237  */
60238 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
60239 
60240 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
60241 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT  (1U)
60242 /*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60243  */
60244 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
60245 
60246 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
60247 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT  (2U)
60248 /*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60249  */
60250 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
60251 
60252 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
60253 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
60254 /*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze
60255  */
60256 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
60257 
60258 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
60259 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT  (4U)
60260 /*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core
60261  */
60262 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
60263 
60264 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
60265 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT  (8U)
60266 /*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core
60267  */
60268 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
60269 
60270 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
60271 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
60272 /*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection
60273  */
60274 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
60275 
60276 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
60277 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
60278 /*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable
60279  */
60280 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
60281 
60282 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
60283 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
60284 /*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable
60285  */
60286 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
60287 
60288 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
60289 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT  (20U)
60290 /*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag
60291  */
60292 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
60293 
60294 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK    (0x1E00000U)
60295 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
60296 /*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes
60297  */
60298 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
60299 
60300 #define IOMUXC_GPR_GPR66_DWP_MASK                (0x30000000U)
60301 #define IOMUXC_GPR_GPR66_DWP_SHIFT               (28U)
60302 /*! DWP - Domain write protection
60303  *  0b00..Both cores are allowed
60304  *  0b01..CM7 is forbidden
60305  *  0b10..CM4 is forbidden
60306  *  0b11..Both cores are forbidden
60307  */
60308 #define IOMUXC_GPR_GPR66_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
60309 
60310 #define IOMUXC_GPR_GPR66_DWP_LOCK_MASK           (0xC0000000U)
60311 #define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT          (30U)
60312 /*! DWP_LOCK - Domain write protection lock
60313  *  0b00..Neither of DWP bits is locked
60314  *  0b01..The lower DWP bit is locked
60315  *  0b10..The higher DWP bit is locked
60316  *  0b11..Both DWP bits are locked
60317  */
60318 #define IOMUXC_GPR_GPR66_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
60319 /*! @} */
60320 
60321 /*! @name GPR67 - GPR67 General Purpose Register */
60322 /*! @{ */
60323 
60324 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK    (0x1U)
60325 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
60326 /*! GPIO_SD1_FREEZE - Compensation code freeze
60327  */
60328 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
60329 
60330 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK    (0x2U)
60331 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
60332 /*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60333  */
60334 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
60335 
60336 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK    (0x4U)
60337 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
60338 /*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60339  */
60340 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
60341 
60342 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
60343 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
60344 /*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze
60345  */
60346 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
60347 
60348 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK    (0xF0U)
60349 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
60350 /*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core
60351  */
60352 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
60353 
60354 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK    (0xF00U)
60355 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
60356 /*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core
60357  */
60358 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
60359 
60360 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
60361 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
60362 /*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection
60363  */
60364 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
60365 
60366 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
60367 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
60368 /*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable
60369  */
60370 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
60371 
60372 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
60373 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
60374 /*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable
60375  */
60376 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
60377 
60378 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK    (0x100000U)
60379 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
60380 /*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag
60381  */
60382 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
60383 
60384 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK     (0x1E00000U)
60385 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT    (21U)
60386 /*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes
60387  */
60388 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
60389 
60390 #define IOMUXC_GPR_GPR67_DWP_MASK                (0x30000000U)
60391 #define IOMUXC_GPR_GPR67_DWP_SHIFT               (28U)
60392 /*! DWP - Domain write protection
60393  *  0b00..Both cores are allowed
60394  *  0b01..CM7 is forbidden
60395  *  0b10..CM4 is forbidden
60396  *  0b11..Both cores are forbidden
60397  */
60398 #define IOMUXC_GPR_GPR67_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
60399 
60400 #define IOMUXC_GPR_GPR67_DWP_LOCK_MASK           (0xC0000000U)
60401 #define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT          (30U)
60402 /*! DWP_LOCK - Domain write protection lock
60403  *  0b00..Neither of DWP bits is locked
60404  *  0b01..The lower DWP bit is locked
60405  *  0b10..The higher DWP bit is locked
60406  *  0b11..Both DWP bits are locked
60407  */
60408 #define IOMUXC_GPR_GPR67_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
60409 /*! @} */
60410 
60411 /*! @name GPR68 - GPR68 General Purpose Register */
60412 /*! @{ */
60413 
60414 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK    (0x1U)
60415 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
60416 /*! GPIO_SD2_FREEZE - Compensation code freeze
60417  */
60418 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
60419 
60420 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK    (0x2U)
60421 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
60422 /*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60423  */
60424 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
60425 
60426 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK    (0x4U)
60427 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
60428 /*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60429  */
60430 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
60431 
60432 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
60433 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
60434 /*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze
60435  */
60436 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
60437 
60438 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK    (0xF0U)
60439 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
60440 /*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core
60441  */
60442 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
60443 
60444 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK    (0xF00U)
60445 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
60446 /*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core
60447  */
60448 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
60449 
60450 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
60451 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
60452 /*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection
60453  */
60454 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
60455 
60456 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
60457 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
60458 /*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable
60459  */
60460 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
60461 
60462 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
60463 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
60464 /*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable
60465  */
60466 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
60467 
60468 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK    (0x100000U)
60469 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
60470 /*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag
60471  */
60472 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
60473 
60474 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK     (0x1E00000U)
60475 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT    (21U)
60476 /*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes
60477  */
60478 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
60479 
60480 #define IOMUXC_GPR_GPR68_DWP_MASK                (0x30000000U)
60481 #define IOMUXC_GPR_GPR68_DWP_SHIFT               (28U)
60482 /*! DWP - Domain write protection
60483  *  0b00..Both cores are allowed
60484  *  0b01..CM7 is forbidden
60485  *  0b10..CM4 is forbidden
60486  *  0b11..Both cores are forbidden
60487  */
60488 #define IOMUXC_GPR_GPR68_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
60489 
60490 #define IOMUXC_GPR_GPR68_DWP_LOCK_MASK           (0xC0000000U)
60491 #define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT          (30U)
60492 /*! DWP_LOCK - Domain write protection lock
60493  *  0b00..Neither of DWP bits is locked
60494  *  0b01..The lower DWP bit is locked
60495  *  0b10..The higher DWP bit is locked
60496  *  0b11..Both DWP bits are locked
60497  */
60498 #define IOMUXC_GPR_GPR68_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
60499 /*! @} */
60500 
60501 /*! @name GPR69 - GPR69 General Purpose Register */
60502 /*! @{ */
60503 
60504 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U)
60505 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U)
60506 /*! GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
60507  */
60508 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
60509 
60510 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U)
60511 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U)
60512 /*! GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
60513  */
60514 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
60515 
60516 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U)
60517 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U)
60518 /*! GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
60519  */
60520 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
60521 
60522 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U)
60523 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U)
60524 /*! GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
60525  */
60526 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
60527 
60528 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U)
60529 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U)
60530 /*! GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
60531  */
60532 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
60533 
60534 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U)
60535 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U)
60536 /*! GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
60537  */
60538 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
60539 
60540 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U)
60541 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U)
60542 /*! SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable
60543  */
60544 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
60545 
60546 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
60547 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
60548 /*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable
60549  */
60550 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
60551 
60552 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
60553 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
60554 /*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable
60555  */
60556 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
60557 
60558 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
60559 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U)
60560 /*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable
60561  */
60562 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
60563 
60564 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
60565 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U)
60566 /*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable
60567  */
60568 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
60569 
60570 #define IOMUXC_GPR_GPR69_DWP_MASK                (0x30000000U)
60571 #define IOMUXC_GPR_GPR69_DWP_SHIFT               (28U)
60572 /*! DWP - Domain write protection
60573  *  0b00..Both cores are allowed
60574  *  0b01..CM7 is forbidden
60575  *  0b10..CM4 is forbidden
60576  *  0b11..Both cores are forbidden
60577  */
60578 #define IOMUXC_GPR_GPR69_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
60579 
60580 #define IOMUXC_GPR_GPR69_DWP_LOCK_MASK           (0xC0000000U)
60581 #define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT          (30U)
60582 /*! DWP_LOCK - Domain write protection lock
60583  *  0b00..Neither of DWP bits is locked
60584  *  0b01..The lower DWP bit is locked
60585  *  0b10..The higher DWP bit is locked
60586  *  0b11..Both DWP bits are locked
60587  */
60588 #define IOMUXC_GPR_GPR69_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
60589 /*! @} */
60590 
60591 /*! @name GPR70 - GPR70 General Purpose Register */
60592 /*! @{ */
60593 
60594 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK      (0x1U)
60595 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT     (0U)
60596 /*! ADC1_IPG_DOZE - ADC1 doze mode
60597  */
60598 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
60599 
60600 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK      (0x2U)
60601 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT     (1U)
60602 /*! ADC1_STOP_REQ - ADC1 stop request
60603  */
60604 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
60605 
60606 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U)
60607 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U)
60608 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted.
60609  *  0b0..This module is functional in Stop Mode
60610  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60611  */
60612 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
60613 
60614 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK      (0x8U)
60615 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT     (3U)
60616 /*! ADC2_IPG_DOZE - ADC2 doze mode
60617  */
60618 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
60619 
60620 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK      (0x10U)
60621 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT     (4U)
60622 /*! ADC2_STOP_REQ - ADC2 stop request
60623  */
60624 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
60625 
60626 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U)
60627 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U)
60628 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted.
60629  *  0b0..This module is functional in Stop Mode
60630  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60631  */
60632 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
60633 
60634 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK      (0x40U)
60635 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT     (6U)
60636 /*! CAAM_IPG_DOZE - CAN3 doze mode
60637  */
60638 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
60639 
60640 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK      (0x80U)
60641 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT     (7U)
60642 /*! CAAM_STOP_REQ - CAAM stop request
60643  */
60644 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
60645 
60646 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK      (0x100U)
60647 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT     (8U)
60648 /*! CAN1_IPG_DOZE - CAN1 doze mode
60649  */
60650 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
60651 
60652 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK      (0x200U)
60653 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT     (9U)
60654 /*! CAN1_STOP_REQ - CAN1 stop request
60655  */
60656 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
60657 
60658 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK      (0x400U)
60659 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT     (10U)
60660 /*! CAN2_IPG_DOZE - CAN2 doze mode
60661  */
60662 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
60663 
60664 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK      (0x800U)
60665 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT     (11U)
60666 /*! CAN2_STOP_REQ - CAN2 stop request
60667  */
60668 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
60669 
60670 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK      (0x1000U)
60671 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT     (12U)
60672 /*! CAN3_IPG_DOZE - CAN3 doze mode
60673  */
60674 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
60675 
60676 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK      (0x2000U)
60677 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT     (13U)
60678 /*! CAN3_STOP_REQ - CAN3 stop request
60679  */
60680 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
60681 
60682 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK      (0x8000U)
60683 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT     (15U)
60684 /*! EDMA_STOP_REQ - EDMA stop request
60685  */
60686 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
60687 
60688 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
60689 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U)
60690 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
60691  */
60692 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
60693 
60694 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK      (0x20000U)
60695 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT     (17U)
60696 /*! ENET_IPG_DOZE - ENET doze mode
60697  */
60698 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
60699 
60700 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK      (0x40000U)
60701 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT     (18U)
60702 /*! ENET_STOP_REQ - ENET stop request
60703  */
60704 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
60705 
60706 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK    (0x80000U)
60707 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
60708 /*! ENET1G_IPG_DOZE - ENET1G doze mode
60709  */
60710 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
60711 
60712 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK    (0x100000U)
60713 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
60714 /*! ENET1G_STOP_REQ - ENET1G stop request
60715  */
60716 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
60717 
60718 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
60719 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT  (21U)
60720 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
60721  */
60722 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
60723 
60724 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
60725 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT  (22U)
60726 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
60727  */
60728 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
60729 
60730 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK  (0x800000U)
60731 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U)
60732 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
60733  */
60734 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
60735 
60736 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK  (0x1000000U)
60737 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U)
60738 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
60739  */
60740 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
60741 
60742 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK  (0x2000000U)
60743 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U)
60744 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
60745  */
60746 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
60747 
60748 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK  (0x4000000U)
60749 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U)
60750 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
60751  */
60752 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
60753 
60754 #define IOMUXC_GPR_GPR70_DWP_MASK                (0x30000000U)
60755 #define IOMUXC_GPR_GPR70_DWP_SHIFT               (28U)
60756 /*! DWP - Domain write protection
60757  *  0b00..Both cores are allowed
60758  *  0b01..CM7 is forbidden
60759  *  0b10..CM4 is forbidden
60760  *  0b11..Both cores are forbidden
60761  */
60762 #define IOMUXC_GPR_GPR70_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
60763 
60764 #define IOMUXC_GPR_GPR70_DWP_LOCK_MASK           (0xC0000000U)
60765 #define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT          (30U)
60766 /*! DWP_LOCK - Domain write protection lock
60767  *  0b00..Neither of DWP bits is locked
60768  *  0b01..The lower DWP bit is locked
60769  *  0b10..The higher DWP bit is locked
60770  *  0b11..Both DWP bits are locked
60771  */
60772 #define IOMUXC_GPR_GPR70_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
60773 /*! @} */
60774 
60775 /*! @name GPR71 - GPR71 General Purpose Register */
60776 /*! @{ */
60777 
60778 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK      (0x1U)
60779 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT     (0U)
60780 /*! GPT1_IPG_DOZE - GPT1 doze mode
60781  */
60782 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
60783 
60784 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK      (0x2U)
60785 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT     (1U)
60786 /*! GPT2_IPG_DOZE - GPT2 doze mode
60787  */
60788 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
60789 
60790 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK      (0x4U)
60791 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT     (2U)
60792 /*! GPT3_IPG_DOZE - GPT3 doze mode
60793  */
60794 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
60795 
60796 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK      (0x8U)
60797 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT     (3U)
60798 /*! GPT4_IPG_DOZE - GPT4 doze mode
60799  */
60800 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
60801 
60802 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK      (0x10U)
60803 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT     (4U)
60804 /*! GPT5_IPG_DOZE - GPT5 doze mode
60805  */
60806 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
60807 
60808 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK      (0x20U)
60809 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT     (5U)
60810 /*! GPT6_IPG_DOZE - GPT6 doze mode
60811  */
60812 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
60813 
60814 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK    (0x40U)
60815 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
60816 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
60817  */
60818 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
60819 
60820 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK    (0x80U)
60821 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
60822 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
60823  */
60824 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
60825 
60826 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
60827 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
60828 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted.
60829  *  0b0..This module is functional in Stop Mode
60830  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60831  */
60832 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
60833 
60834 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK    (0x200U)
60835 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
60836 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
60837  */
60838 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
60839 
60840 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK    (0x400U)
60841 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
60842 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
60843  */
60844 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
60845 
60846 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
60847 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
60848 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted.
60849  *  0b0..This module is functional in Stop Mode
60850  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60851  */
60852 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
60853 
60854 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK    (0x1000U)
60855 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
60856 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
60857  */
60858 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
60859 
60860 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK    (0x2000U)
60861 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
60862 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
60863  */
60864 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
60865 
60866 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
60867 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
60868 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted.
60869  *  0b0..This module is functional in Stop Mode
60870  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60871  */
60872 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
60873 
60874 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK    (0x8000U)
60875 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
60876 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
60877  */
60878 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
60879 
60880 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK    (0x10000U)
60881 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
60882 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
60883  */
60884 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
60885 
60886 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
60887 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
60888 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted.
60889  *  0b0..This module is functional in Stop Mode
60890  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60891  */
60892 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
60893 
60894 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK    (0x40000U)
60895 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
60896 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
60897  */
60898 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
60899 
60900 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK    (0x80000U)
60901 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
60902 /*! LPI2C5_STOP_REQ - LPI2C5 stop request
60903  */
60904 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
60905 
60906 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
60907 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
60908 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted.
60909  *  0b0..This module is functional in Stop Mode
60910  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60911  */
60912 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
60913 
60914 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK    (0x200000U)
60915 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
60916 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
60917  */
60918 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
60919 
60920 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK    (0x400000U)
60921 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
60922 /*! LPI2C6_STOP_REQ - LPI2C6 stop request
60923  */
60924 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
60925 
60926 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
60927 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
60928 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted.
60929  *  0b0..This module is functional in Stop Mode
60930  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60931  */
60932 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
60933 
60934 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK    (0x1000000U)
60935 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
60936 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
60937  */
60938 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
60939 
60940 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK    (0x2000000U)
60941 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
60942 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
60943  */
60944 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
60945 
60946 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
60947 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
60948 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted.
60949  *  0b0..This module is functional in Stop Mode
60950  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60951  */
60952 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
60953 
60954 #define IOMUXC_GPR_GPR71_DWP_MASK                (0x30000000U)
60955 #define IOMUXC_GPR_GPR71_DWP_SHIFT               (28U)
60956 /*! DWP - Domain write protection
60957  *  0b00..Both cores are allowed
60958  *  0b01..CM7 is forbidden
60959  *  0b10..CM4 is forbidden
60960  *  0b11..Both cores are forbidden
60961  */
60962 #define IOMUXC_GPR_GPR71_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
60963 
60964 #define IOMUXC_GPR_GPR71_DWP_LOCK_MASK           (0xC0000000U)
60965 #define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT          (30U)
60966 /*! DWP_LOCK - Domain write protection lock
60967  *  0b00..Neither of DWP bits is locked
60968  *  0b01..The lower DWP bit is locked
60969  *  0b10..The higher DWP bit is locked
60970  *  0b11..Both DWP bits are locked
60971  */
60972 #define IOMUXC_GPR_GPR71_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
60973 /*! @} */
60974 
60975 /*! @name GPR72 - GPR72 General Purpose Register */
60976 /*! @{ */
60977 
60978 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK    (0x1U)
60979 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
60980 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
60981  */
60982 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
60983 
60984 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK    (0x2U)
60985 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
60986 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
60987  */
60988 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
60989 
60990 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
60991 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
60992 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted.
60993  *  0b0..This module is functional in Stop Mode
60994  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
60995  */
60996 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
60997 
60998 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK    (0x8U)
60999 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
61000 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
61001  */
61002 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
61003 
61004 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK    (0x10U)
61005 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
61006 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
61007  */
61008 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
61009 
61010 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
61011 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
61012 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted.
61013  *  0b0..This module is functional in Stop Mode
61014  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61015  */
61016 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
61017 
61018 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK    (0x40U)
61019 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
61020 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
61021  */
61022 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
61023 
61024 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK    (0x80U)
61025 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
61026 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
61027  */
61028 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
61029 
61030 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
61031 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
61032 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted.
61033  *  0b0..This module is functional in Stop Mode
61034  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61035  */
61036 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
61037 
61038 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK    (0x200U)
61039 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
61040 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
61041  */
61042 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
61043 
61044 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK    (0x400U)
61045 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
61046 /*! LPSPI5_STOP_REQ - LPSPI5 stop request
61047  */
61048 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
61049 
61050 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
61051 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
61052 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted.
61053  *  0b0..This module is functional in Stop Mode
61054  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61055  */
61056 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
61057 
61058 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK    (0x1000U)
61059 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
61060 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
61061  */
61062 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
61063 
61064 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK    (0x2000U)
61065 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
61066 /*! LPSPI6_STOP_REQ - LPSPI6 stop request
61067  */
61068 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
61069 
61070 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
61071 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
61072 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted.
61073  *  0b0..This module is functional in Stop Mode
61074  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61075  */
61076 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
61077 
61078 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
61079 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT  (15U)
61080 /*! LPUART1_IPG_DOZE - LPUART1 doze mode
61081  */
61082 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
61083 
61084 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
61085 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT  (16U)
61086 /*! LPUART1_STOP_REQ - LPUART1 stop request
61087  */
61088 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
61089 
61090 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
61091 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U)
61092 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted.
61093  *  0b0..This module is functional in Stop Mode
61094  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61095  */
61096 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
61097 
61098 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
61099 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT  (18U)
61100 /*! LPUART2_IPG_DOZE - LPUART2 doze mode
61101  */
61102 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
61103 
61104 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
61105 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT  (19U)
61106 /*! LPUART2_STOP_REQ - LPUART2 stop request
61107  */
61108 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
61109 
61110 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
61111 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U)
61112 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted.
61113  *  0b0..This module is functional in Stop Mode
61114  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61115  */
61116 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
61117 
61118 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
61119 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT  (21U)
61120 /*! LPUART3_IPG_DOZE - LPUART3 doze mode
61121  */
61122 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
61123 
61124 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
61125 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT  (22U)
61126 /*! LPUART3_STOP_REQ - LPUART3 stop request
61127  */
61128 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
61129 
61130 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
61131 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U)
61132 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted.
61133  *  0b0..This module is functional in Stop Mode
61134  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61135  */
61136 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
61137 
61138 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
61139 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT  (24U)
61140 /*! LPUART4_IPG_DOZE - LPUART4 doze mode
61141  */
61142 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
61143 
61144 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
61145 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT  (25U)
61146 /*! LPUART4_STOP_REQ - LPUART4 stop request
61147  */
61148 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
61149 
61150 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
61151 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U)
61152 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted.
61153  *  0b0..This module is functional in Stop Mode
61154  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61155  */
61156 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
61157 
61158 #define IOMUXC_GPR_GPR72_DWP_MASK                (0x30000000U)
61159 #define IOMUXC_GPR_GPR72_DWP_SHIFT               (28U)
61160 /*! DWP - Domain write protection
61161  *  0b00..Both cores are allowed
61162  *  0b01..CM7 is forbidden
61163  *  0b10..CM4 is forbidden
61164  *  0b11..Both cores are forbidden
61165  */
61166 #define IOMUXC_GPR_GPR72_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
61167 
61168 #define IOMUXC_GPR_GPR72_DWP_LOCK_MASK           (0xC0000000U)
61169 #define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT          (30U)
61170 /*! DWP_LOCK - Domain write protection lock
61171  *  0b00..Neither of DWP bits is locked
61172  *  0b01..The lower DWP bit is locked
61173  *  0b10..The higher DWP bit is locked
61174  *  0b11..Both DWP bits are locked
61175  */
61176 #define IOMUXC_GPR_GPR72_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
61177 /*! @} */
61178 
61179 /*! @name GPR73 - GPR73 General Purpose Register */
61180 /*! @{ */
61181 
61182 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
61183 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT  (0U)
61184 /*! LPUART5_IPG_DOZE - LPUART5 doze mode
61185  */
61186 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
61187 
61188 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
61189 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT  (1U)
61190 /*! LPUART5_STOP_REQ - LPUART5 stop request
61191  */
61192 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
61193 
61194 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U)
61195 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U)
61196 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted.
61197  *  0b0..This module is functional in Stop Mode
61198  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61199  */
61200 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
61201 
61202 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
61203 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT  (3U)
61204 /*! LPUART6_IPG_DOZE - LPUART6 doze mode
61205  */
61206 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
61207 
61208 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
61209 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT  (4U)
61210 /*! LPUART6_STOP_REQ - LPUART6 stop request
61211  */
61212 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
61213 
61214 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U)
61215 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U)
61216 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted.
61217  *  0b0..This module is functional in Stop Mode
61218  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61219  */
61220 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
61221 
61222 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
61223 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT  (6U)
61224 /*! LPUART7_IPG_DOZE - LPUART7 doze mode
61225  */
61226 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
61227 
61228 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
61229 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT  (7U)
61230 /*! LPUART7_STOP_REQ - LPUART7 stop request
61231  */
61232 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
61233 
61234 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U)
61235 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U)
61236 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted.
61237  *  0b0..This module is functional in Stop Mode
61238  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61239  */
61240 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
61241 
61242 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
61243 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT  (9U)
61244 /*! LPUART8_IPG_DOZE - LPUART8 doze mode
61245  */
61246 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
61247 
61248 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
61249 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT  (10U)
61250 /*! LPUART8_STOP_REQ - LPUART8 stop request
61251  */
61252 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
61253 
61254 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U)
61255 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U)
61256 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted.
61257  *  0b0..This module is functional in Stop Mode
61258  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61259  */
61260 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
61261 
61262 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
61263 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT  (12U)
61264 /*! LPUART9_IPG_DOZE - LPUART9 doze mode
61265  */
61266 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
61267 
61268 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
61269 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT  (13U)
61270 /*! LPUART9_STOP_REQ - LPUART9 stop request
61271  */
61272 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
61273 
61274 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
61275 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U)
61276 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted.
61277  *  0b0..This module is functional in Stop Mode
61278  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61279  */
61280 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
61281 
61282 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK  (0x8000U)
61283 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U)
61284 /*! LPUART10_IPG_DOZE - LPUART10 doze mode
61285  */
61286 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
61287 
61288 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK  (0x10000U)
61289 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U)
61290 /*! LPUART10_STOP_REQ - LPUART10 stop request
61291  */
61292 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
61293 
61294 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
61295 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U)
61296 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted.
61297  *  0b0..This module is functional in Stop Mode
61298  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61299  */
61300 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
61301 
61302 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK  (0x40000U)
61303 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U)
61304 /*! LPUART11_IPG_DOZE - LPUART11 doze mode
61305  */
61306 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
61307 
61308 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK  (0x80000U)
61309 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U)
61310 /*! LPUART11_STOP_REQ - LPUART11 stop request
61311  */
61312 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
61313 
61314 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
61315 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U)
61316 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted.
61317  *  0b0..This module is functional in Stop Mode
61318  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61319  */
61320 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
61321 
61322 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK  (0x200000U)
61323 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U)
61324 /*! LPUART12_IPG_DOZE - LPUART12 doze mode
61325  */
61326 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
61327 
61328 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK  (0x400000U)
61329 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U)
61330 /*! LPUART12_STOP_REQ - LPUART12 stop request
61331  */
61332 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
61333 
61334 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
61335 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U)
61336 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted.
61337  *  0b0..This module is functional in Stop Mode
61338  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61339  */
61340 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
61341 
61342 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK       (0x1000000U)
61343 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT      (24U)
61344 /*! MIC_IPG_DOZE - MIC doze mode
61345  */
61346 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
61347 
61348 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK       (0x2000000U)
61349 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT      (25U)
61350 /*! MIC_STOP_REQ - MIC stop request
61351  */
61352 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
61353 
61354 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK  (0x4000000U)
61355 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U)
61356 /*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted.
61357  *  0b0..This module is functional in Stop Mode
61358  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61359  */
61360 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
61361 
61362 #define IOMUXC_GPR_GPR73_DWP_MASK                (0x30000000U)
61363 #define IOMUXC_GPR_GPR73_DWP_SHIFT               (28U)
61364 /*! DWP - Domain write protection
61365  *  0b00..Both cores are allowed
61366  *  0b01..CM7 is forbidden
61367  *  0b10..CM4 is forbidden
61368  *  0b11..Both cores are forbidden
61369  */
61370 #define IOMUXC_GPR_GPR73_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
61371 
61372 #define IOMUXC_GPR_GPR73_DWP_LOCK_MASK           (0xC0000000U)
61373 #define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT          (30U)
61374 /*! DWP_LOCK - Domain write protection lock
61375  *  0b00..Neither of DWP bits is locked
61376  *  0b01..The lower DWP bit is locked
61377  *  0b10..The higher DWP bit is locked
61378  *  0b11..Both DWP bits are locked
61379  */
61380 #define IOMUXC_GPR_GPR73_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
61381 /*! @} */
61382 
61383 /*! @name GPR74 - GPR74 General Purpose Register */
61384 /*! @{ */
61385 
61386 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK      (0x2U)
61387 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT     (1U)
61388 /*! PIT1_STOP_REQ - PIT1 stop request
61389  */
61390 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
61391 
61392 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK      (0x4U)
61393 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT     (2U)
61394 /*! PIT2_STOP_REQ - PIT2 stop request
61395  */
61396 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
61397 
61398 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK      (0x8U)
61399 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT     (3U)
61400 /*! SEMC_STOP_REQ - SEMC stop request
61401  */
61402 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
61403 
61404 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK      (0x10U)
61405 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT     (4U)
61406 /*! SIM1_IPG_DOZE - SIM1 doze mode
61407  */
61408 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
61409 
61410 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK      (0x20U)
61411 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT     (5U)
61412 /*! SIM2_IPG_DOZE - SIM2 doze mode
61413  */
61414 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
61415 
61416 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
61417 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT  (6U)
61418 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
61419  */
61420 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
61421 
61422 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
61423 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT  (7U)
61424 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request
61425  */
61426 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
61427 
61428 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK     (0x100U)
61429 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT    (8U)
61430 /*! WDOG1_IPG_DOZE - WDOG1 doze mode
61431  */
61432 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
61433 
61434 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK     (0x200U)
61435 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT    (9U)
61436 /*! WDOG2_IPG_DOZE - WDOG2 doze mode
61437  */
61438 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
61439 
61440 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK      (0x400U)
61441 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT     (10U)
61442 /*! SAI1_STOP_REQ - SAI1 stop request
61443  */
61444 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
61445 
61446 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK      (0x800U)
61447 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT     (11U)
61448 /*! SAI2_STOP_REQ - SAI2 stop request
61449  */
61450 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
61451 
61452 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK      (0x1000U)
61453 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT     (12U)
61454 /*! SAI3_STOP_REQ - SAI3 stop request
61455  */
61456 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
61457 
61458 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK      (0x2000U)
61459 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT     (13U)
61460 /*! SAI4_STOP_REQ - SAI4 stop request
61461  */
61462 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
61463 
61464 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
61465 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
61466 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
61467  */
61468 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
61469 
61470 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
61471 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
61472 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
61473  */
61474 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
61475 
61476 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
61477 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
61478 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
61479  */
61480 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
61481 
61482 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
61483 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
61484 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
61485  */
61486 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
61487 
61488 #define IOMUXC_GPR_GPR74_DWP_MASK                (0x30000000U)
61489 #define IOMUXC_GPR_GPR74_DWP_SHIFT               (28U)
61490 /*! DWP - Domain write protection
61491  *  0b00..Both cores are allowed
61492  *  0b01..CM7 is forbidden
61493  *  0b10..CM4 is forbidden
61494  *  0b11..Both cores are forbidden
61495  */
61496 #define IOMUXC_GPR_GPR74_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
61497 
61498 #define IOMUXC_GPR_GPR74_DWP_LOCK_MASK           (0xC0000000U)
61499 #define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT          (30U)
61500 /*! DWP_LOCK - Domain write protection lock
61501  *  0b00..Neither of DWP bits is locked
61502  *  0b01..The lower DWP bit is locked
61503  *  0b10..The higher DWP bit is locked
61504  *  0b11..Both DWP bits are locked
61505  */
61506 #define IOMUXC_GPR_GPR74_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
61507 /*! @} */
61508 
61509 /*! @name GPR75 - GPR75 General Purpose Register */
61510 /*! @{ */
61511 
61512 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK      (0x1U)
61513 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT     (0U)
61514 /*! ADC1_STOP_ACK - ADC1 stop acknowledge
61515  */
61516 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
61517 
61518 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK      (0x2U)
61519 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT     (1U)
61520 /*! ADC2_STOP_ACK - ADC2 stop acknowledge
61521  */
61522 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
61523 
61524 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK      (0x4U)
61525 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT     (2U)
61526 /*! CAAM_STOP_ACK - CAAM stop acknowledge
61527  */
61528 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
61529 
61530 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK      (0x8U)
61531 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT     (3U)
61532 /*! CAN1_STOP_ACK - CAN1 stop acknowledge
61533  */
61534 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
61535 
61536 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK      (0x10U)
61537 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT     (4U)
61538 /*! CAN2_STOP_ACK - CAN2 stop acknowledge
61539  */
61540 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
61541 
61542 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK      (0x20U)
61543 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT     (5U)
61544 /*! CAN3_STOP_ACK - CAN3 stop acknowledge
61545  */
61546 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
61547 
61548 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK      (0x40U)
61549 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT     (6U)
61550 /*! EDMA_STOP_ACK - EDMA stop acknowledge
61551  */
61552 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
61553 
61554 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U)
61555 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U)
61556 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
61557  */
61558 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
61559 
61560 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK      (0x100U)
61561 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT     (8U)
61562 /*! ENET_STOP_ACK - ENET stop acknowledge
61563  */
61564 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
61565 
61566 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK    (0x200U)
61567 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
61568 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge
61569  */
61570 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
61571 
61572 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK  (0x400U)
61573 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U)
61574 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
61575  */
61576 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
61577 
61578 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK  (0x800U)
61579 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U)
61580 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
61581  */
61582 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
61583 
61584 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK    (0x1000U)
61585 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
61586 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
61587  */
61588 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
61589 
61590 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK    (0x2000U)
61591 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
61592 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
61593  */
61594 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
61595 
61596 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK    (0x4000U)
61597 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
61598 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
61599  */
61600 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
61601 
61602 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK    (0x8000U)
61603 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
61604 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
61605  */
61606 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
61607 
61608 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK    (0x10000U)
61609 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
61610 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
61611  */
61612 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
61613 
61614 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK    (0x20000U)
61615 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
61616 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
61617  */
61618 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
61619 
61620 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK    (0x40000U)
61621 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
61622 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
61623  */
61624 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
61625 
61626 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK    (0x80000U)
61627 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
61628 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
61629  */
61630 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
61631 
61632 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK    (0x100000U)
61633 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
61634 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
61635  */
61636 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
61637 
61638 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK    (0x200000U)
61639 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
61640 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
61641  */
61642 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
61643 
61644 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK    (0x400000U)
61645 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
61646 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
61647  */
61648 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
61649 
61650 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK    (0x800000U)
61651 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
61652 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
61653  */
61654 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
61655 
61656 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
61657 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT  (24U)
61658 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
61659  */
61660 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
61661 
61662 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
61663 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT  (25U)
61664 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
61665  */
61666 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
61667 
61668 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
61669 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT  (26U)
61670 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
61671  */
61672 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
61673 
61674 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
61675 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT  (27U)
61676 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
61677  */
61678 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
61679 
61680 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
61681 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT  (28U)
61682 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
61683  */
61684 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
61685 
61686 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
61687 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT  (29U)
61688 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
61689  */
61690 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
61691 
61692 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
61693 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT  (30U)
61694 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
61695  */
61696 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
61697 
61698 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
61699 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT  (31U)
61700 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
61701  */
61702 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
61703 /*! @} */
61704 
61705 /*! @name GPR76 - GPR76 General Purpose Register */
61706 /*! @{ */
61707 
61708 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
61709 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT  (0U)
61710 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
61711  */
61712 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
61713 
61714 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK  (0x2U)
61715 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U)
61716 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
61717  */
61718 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
61719 
61720 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK  (0x4U)
61721 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U)
61722 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
61723  */
61724 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
61725 
61726 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK  (0x8U)
61727 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U)
61728 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
61729  */
61730 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
61731 
61732 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK       (0x10U)
61733 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT      (4U)
61734 /*! MIC_STOP_ACK - MIC stop acknowledge
61735  */
61736 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
61737 
61738 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK      (0x20U)
61739 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT     (5U)
61740 /*! PIT1_STOP_ACK - PIT1 stop acknowledge
61741  */
61742 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
61743 
61744 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK      (0x40U)
61745 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT     (6U)
61746 /*! PIT2_STOP_ACK - PIT2 stop acknowledge
61747  */
61748 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
61749 
61750 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK      (0x80U)
61751 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT     (7U)
61752 /*! SEMC_STOP_ACK - SEMC stop acknowledge
61753  */
61754 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
61755 
61756 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
61757 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT  (8U)
61758 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
61759  */
61760 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
61761 
61762 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK      (0x200U)
61763 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT     (9U)
61764 /*! SAI1_STOP_ACK - SAI1 stop acknowledge
61765  */
61766 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
61767 
61768 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK      (0x400U)
61769 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT     (10U)
61770 /*! SAI2_STOP_ACK - SAI2 stop acknowledge
61771  */
61772 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
61773 
61774 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK      (0x800U)
61775 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT     (11U)
61776 /*! SAI3_STOP_ACK - SAI3 stop acknowledge
61777  */
61778 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
61779 
61780 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK      (0x1000U)
61781 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT     (12U)
61782 /*! SAI4_STOP_ACK - SAI4 stop acknowledge
61783  */
61784 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
61785 
61786 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
61787 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
61788 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
61789  */
61790 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
61791 
61792 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
61793 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
61794 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
61795  */
61796 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
61797 
61798 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
61799 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
61800 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
61801  */
61802 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
61803 
61804 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
61805 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
61806 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
61807  */
61808 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
61809 /*! @} */
61810 
61811 
61812 /*!
61813  * @}
61814  */ /* end of group IOMUXC_GPR_Register_Masks */
61815 
61816 
61817 /* IOMUXC_GPR - Peripheral instance base addresses */
61818 /** Peripheral IOMUXC_GPR base address */
61819 #define IOMUXC_GPR_BASE                          (0x400E4000u)
61820 /** Peripheral IOMUXC_GPR base pointer */
61821 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
61822 /** Array initializer of IOMUXC_GPR peripheral base addresses */
61823 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
61824 /** Array initializer of IOMUXC_GPR peripheral base pointers */
61825 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
61826 
61827 /*!
61828  * @}
61829  */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
61830 
61831 
61832 /* ----------------------------------------------------------------------------
61833    -- IOMUXC_LPSR Peripheral Access Layer
61834    ---------------------------------------------------------------------------- */
61835 
61836 /*!
61837  * @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer
61838  * @{
61839  */
61840 
61841 /** IOMUXC_LPSR - Register Layout Typedef */
61842 typedef struct {
61843   __IO uint32_t SW_MUX_CTL_PAD[16];                /**< SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4 */
61844   __IO uint32_t SW_PAD_CTL_PAD[16];                /**< SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4 */
61845   __IO uint32_t SELECT_INPUT[24];                  /**< CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4 */
61846 } IOMUXC_LPSR_Type;
61847 
61848 /* ----------------------------------------------------------------------------
61849    -- IOMUXC_LPSR Register Masks
61850    ---------------------------------------------------------------------------- */
61851 
61852 /*!
61853  * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks
61854  * @{
61855  */
61856 
61857 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register */
61858 /*! @{ */
61859 
61860 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
61861 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
61862 /*! MUX_MODE - MUX Mode Select Field.
61863  *  0b0000..Select mux mode: ALT0 mux port: FLEXCAN3_TX of instance: FLEXCAN3
61864  *  0b0001..Select mux mode: ALT1 mux port: MIC_CLK of instance: MIC
61865  *  0b0010..Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS
61866  *  0b0011..Select mux mode: ALT3 mux port: ARM_CM4_EVENTO of instance: CM4
61867  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO00 of instance: GPIO_MUX6
61868  *  0b0110..Select mux mode: ALT6 mux port: LPUART12_TXD of instance: LPUART12
61869  *  0b0111..Select mux mode: ALT7 mux port: SAI4_MCLK of instance: SAI4
61870  *  0b1010..Select mux mode: ALT10 mux port: GPIO12_IO00 of instance: GPIO12
61871  */
61872 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)
61873 
61874 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK     (0x10U)
61875 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT    (4U)
61876 /*! SION - Software Input On Field.
61877  *  0b1..Force input path of pad GPIO_LPSR_00
61878  *  0b0..Input Path is determined by functionality
61879  */
61880 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)
61881 /*! @} */
61882 
61883 /* The count of IOMUXC_LPSR_SW_MUX_CTL_PAD */
61884 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT         (16U)
61885 
61886 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register */
61887 /*! @{ */
61888 
61889 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK      (0x1U)
61890 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT     (0U)
61891 /*! SRE - Slew Rate Field
61892  *  0b0..Slow Slew Rate
61893  *  0b1..Fast Slew Rate
61894  */
61895 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)
61896 
61897 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK      (0x2U)
61898 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT     (1U)
61899 /*! DSE - Drive Strength Field
61900  *  0b0..normal driver
61901  *  0b1..high driver
61902  */
61903 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)
61904 
61905 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK      (0x4U)
61906 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT     (2U)
61907 /*! PUE - Pull / Keep Select Field
61908  *  0b0..Pull Disable
61909  *  0b1..Pull Enable
61910  */
61911 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)
61912 
61913 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK      (0x8U)
61914 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT     (3U)
61915 /*! PUS - Pull Up / Down Config. Field
61916  *  0b0..Weak pull down
61917  *  0b1..Weak pull up
61918  */
61919 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)
61920 
61921 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)
61922 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)
61923 /*! ODE_LPSR - Open Drain LPSR Field
61924  *  0b0..Disabled
61925  *  0b1..Enabled
61926  */
61927 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)
61928 
61929 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK      (0x30000000U)
61930 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT     (28U)
61931 /*! DWP - Domain write protection
61932  *  0b00..Both cores are allowed
61933  *  0b01..CM7 is forbidden
61934  *  0b10..CM4 is forbidden
61935  *  0b11..Both cores are forbidden
61936  */
61937 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)
61938 
61939 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
61940 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
61941 /*! DWP_LOCK - Domain write protection lock
61942  *  0b00..Neither of DWP bits is locked
61943  *  0b01..The lower DWP bit is locked
61944  *  0b10..The higher DWP bit is locked
61945  *  0b11..Both DWP bits are locked
61946  */
61947 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
61948 /*! @} */
61949 
61950 /* The count of IOMUXC_LPSR_SW_PAD_CTL_PAD */
61951 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT         (16U)
61952 
61953 /*! @name SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */
61954 /*! @{ */
61955 
61956 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK      (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
61957 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT     (0U)
61958 /*! DAISY - Selecting Pads Involved in Daisy Chain.
61959  *  0b00..Selecting Pad: GPIO_LPSR_01 for Mode: ALT0
61960  *  0b01..Selecting Pad: GPIO_LPSR_07 for Mode: ALT6
61961  *  0b10..Selecting Pad: GPIO_LPSR_09 for Mode: ALT1
61962  */
61963 #define IOMUXC_LPSR_SELECT_INPUT_DAISY(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
61964 /*! @} */
61965 
61966 /* The count of IOMUXC_LPSR_SELECT_INPUT */
61967 #define IOMUXC_LPSR_SELECT_INPUT_COUNT           (24U)
61968 
61969 
61970 /*!
61971  * @}
61972  */ /* end of group IOMUXC_LPSR_Register_Masks */
61973 
61974 
61975 /* IOMUXC_LPSR - Peripheral instance base addresses */
61976 /** Peripheral IOMUXC_LPSR base address */
61977 #define IOMUXC_LPSR_BASE                         (0x40C08000u)
61978 /** Peripheral IOMUXC_LPSR base pointer */
61979 #define IOMUXC_LPSR                              ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
61980 /** Array initializer of IOMUXC_LPSR peripheral base addresses */
61981 #define IOMUXC_LPSR_BASE_ADDRS                   { IOMUXC_LPSR_BASE }
61982 /** Array initializer of IOMUXC_LPSR peripheral base pointers */
61983 #define IOMUXC_LPSR_BASE_PTRS                    { IOMUXC_LPSR }
61984 
61985 /*!
61986  * @}
61987  */ /* end of group IOMUXC_LPSR_Peripheral_Access_Layer */
61988 
61989 
61990 /* ----------------------------------------------------------------------------
61991    -- IOMUXC_LPSR_GPR Peripheral Access Layer
61992    ---------------------------------------------------------------------------- */
61993 
61994 /*!
61995  * @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer
61996  * @{
61997  */
61998 
61999 /** IOMUXC_LPSR_GPR - Register Layout Typedef */
62000 typedef struct {
62001   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
62002   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
62003   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
62004   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
62005   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
62006   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
62007   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
62008   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
62009   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
62010   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
62011   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
62012   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
62013   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
62014   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
62015   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
62016   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
62017   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
62018   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
62019   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
62020   __IO uint32_t GPR19;                             /**< GPR19 General Purpose Register, offset: 0x4C */
62021   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
62022   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
62023   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
62024   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
62025   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
62026   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
62027   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
62028        uint8_t RESERVED_0[24];
62029   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
62030   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
62031   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
62032   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
62033   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
62034   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
62035   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
62036   __I  uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
62037   __I  uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
62038 } IOMUXC_LPSR_GPR_Type;
62039 
62040 /* ----------------------------------------------------------------------------
62041    -- IOMUXC_LPSR_GPR Register Masks
62042    ---------------------------------------------------------------------------- */
62043 
62044 /*!
62045  * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks
62046  * @{
62047  */
62048 
62049 /*! @name GPR0 - GPR0 General Purpose Register */
62050 /*! @{ */
62051 
62052 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U)
62053 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U)
62054 /*! CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset
62055  */
62056 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
62057 
62058 #define IOMUXC_LPSR_GPR_GPR0_DWP_MASK            (0x30000000U)
62059 #define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT           (28U)
62060 /*! DWP - Domain write protection
62061  *  0b00..Both cores are allowed
62062  *  0b01..CM7 is forbidden
62063  *  0b10..CM4 is forbidden
62064  *  0b11..Both cores are forbidden
62065  */
62066 #define IOMUXC_LPSR_GPR_GPR0_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
62067 
62068 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK       (0xC0000000U)
62069 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT      (30U)
62070 /*! DWP_LOCK - Domain write protection lock
62071  *  0b00..Neither of DWP bits is locked
62072  *  0b01..The lower DWP bit is locked
62073  *  0b10..The higher DWP bit is locked
62074  *  0b11..Both DWP bits are locked
62075  */
62076 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
62077 /*! @} */
62078 
62079 /*! @name GPR1 - GPR1 General Purpose Register */
62080 /*! @{ */
62081 
62082 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU)
62083 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U)
62084 /*! CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset
62085  */
62086 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
62087 
62088 #define IOMUXC_LPSR_GPR_GPR1_DWP_MASK            (0x30000000U)
62089 #define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT           (28U)
62090 /*! DWP - Domain write protection
62091  *  0b00..Both cores are allowed
62092  *  0b01..CM7 is forbidden
62093  *  0b10..CM4 is forbidden
62094  *  0b11..Both cores are forbidden
62095  */
62096 #define IOMUXC_LPSR_GPR_GPR1_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
62097 
62098 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK       (0xC0000000U)
62099 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT      (30U)
62100 /*! DWP_LOCK - Domain write protection lock
62101  *  0b00..Neither of DWP bits is locked
62102  *  0b01..The lower DWP bit is locked
62103  *  0b10..The higher DWP bit is locked
62104  *  0b11..Both DWP bits are locked
62105  */
62106 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
62107 /*! @} */
62108 
62109 /*! @name GPR2 - GPR2 General Purpose Register */
62110 /*! @{ */
62111 
62112 #define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK           (0x1U)
62113 #define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT          (0U)
62114 /*! LOCK - Lock the write to bit 31:1
62115  *  0b1..Write access to bit 31:1 is blocked
62116  *  0b0..Write access to bit 31:1 is not blocked
62117  */
62118 #define IOMUXC_LPSR_GPR_GPR2_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
62119 
62120 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK  (0xFFFFFFF8U)
62121 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U)
62122 /*! APC_AC_R0_BOT - APC start address of memory region-0
62123  */
62124 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
62125 /*! @} */
62126 
62127 /*! @name GPR3 - GPR3 General Purpose Register */
62128 /*! @{ */
62129 
62130 #define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK           (0x1U)
62131 #define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT          (0U)
62132 /*! LOCK - Lock the write to bit 31:1
62133  *  0b1..Write access to bit 31:1 is blocked
62134  *  0b0..Write access to bit 31:1 is not blocked
62135  */
62136 #define IOMUXC_LPSR_GPR_GPR3_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
62137 
62138 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK  (0xFFFFFFF8U)
62139 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U)
62140 /*! APC_AC_R0_TOP - APC end address of memory region-0
62141  */
62142 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
62143 /*! @} */
62144 
62145 /*! @name GPR4 - GPR4 General Purpose Register */
62146 /*! @{ */
62147 
62148 #define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK           (0x1U)
62149 #define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT          (0U)
62150 /*! LOCK - Lock the write to bit 31:1
62151  *  0b1..Write access to bit 31:1 is blocked
62152  *  0b0..Write access to bit 31:1 is not blocked
62153  */
62154 #define IOMUXC_LPSR_GPR_GPR4_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
62155 
62156 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK  (0xFFFFFFF8U)
62157 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U)
62158 /*! APC_AC_R1_BOT - APC start address of memory region-1
62159  */
62160 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
62161 /*! @} */
62162 
62163 /*! @name GPR5 - GPR5 General Purpose Register */
62164 /*! @{ */
62165 
62166 #define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK           (0x1U)
62167 #define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT          (0U)
62168 /*! LOCK - Lock the write to bit 31:1
62169  *  0b1..Write access to bit 31:1 is blocked
62170  *  0b0..Write access to bit 31:1 is not blocked
62171  */
62172 #define IOMUXC_LPSR_GPR_GPR5_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
62173 
62174 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK  (0xFFFFFFF8U)
62175 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U)
62176 /*! APC_AC_R1_TOP - APC end address of memory region-1
62177  */
62178 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
62179 /*! @} */
62180 
62181 /*! @name GPR6 - GPR6 General Purpose Register */
62182 /*! @{ */
62183 
62184 #define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK           (0x1U)
62185 #define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT          (0U)
62186 /*! LOCK - Lock the write to bit 31:1
62187  *  0b1..Write access to bit 31:1 is blocked
62188  *  0b0..Write access to bit 31:1 is not blocked
62189  */
62190 #define IOMUXC_LPSR_GPR_GPR6_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK)
62191 
62192 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK  (0xFFFFFFF8U)
62193 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U)
62194 /*! APC_AC_R2_BOT - APC start address of memory region-2
62195  */
62196 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK)
62197 /*! @} */
62198 
62199 /*! @name GPR7 - GPR7 General Purpose Register */
62200 /*! @{ */
62201 
62202 #define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK           (0x1U)
62203 #define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT          (0U)
62204 /*! LOCK - Lock the write to bit 31:1
62205  *  0b1..Write access to bit 31:1 is blocked
62206  *  0b0..Write access to bit 31:1 is not blocked
62207  */
62208 #define IOMUXC_LPSR_GPR_GPR7_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
62209 
62210 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK  (0xFFFFFFF8U)
62211 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U)
62212 /*! APC_AC_R2_TOP - APC end address of memory region-2
62213  */
62214 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
62215 /*! @} */
62216 
62217 /*! @name GPR8 - GPR8 General Purpose Register */
62218 /*! @{ */
62219 
62220 #define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK           (0x1U)
62221 #define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT          (0U)
62222 /*! LOCK - Lock the write to bit 31:1
62223  *  0b1..Write access to bit 31:1 is blocked
62224  *  0b0..Write access to bit 31:1 is not blocked
62225  */
62226 #define IOMUXC_LPSR_GPR_GPR8_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
62227 
62228 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK  (0xFFFFFFF8U)
62229 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U)
62230 /*! APC_AC_R3_BOT - APC start address of memory region-3
62231  */
62232 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
62233 /*! @} */
62234 
62235 /*! @name GPR9 - GPR9 General Purpose Register */
62236 /*! @{ */
62237 
62238 #define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK           (0x1U)
62239 #define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT          (0U)
62240 /*! LOCK - Lock the write to bit 31:1
62241  *  0b1..Write access to bit 31:1 is blocked
62242  *  0b0..Write access to bit 31:1 is not blocked
62243  */
62244 #define IOMUXC_LPSR_GPR_GPR9_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
62245 
62246 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK  (0xFFFFFFF8U)
62247 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U)
62248 /*! APC_AC_R3_TOP - APC end address of memory region-3
62249  */
62250 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
62251 /*! @} */
62252 
62253 /*! @name GPR10 - GPR10 General Purpose Register */
62254 /*! @{ */
62255 
62256 #define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK          (0x1U)
62257 #define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT         (0U)
62258 /*! LOCK - Lock the write to bit 31:1
62259  *  0b1..Write access to bit 31:1 is blocked
62260  *  0b0..Write access to bit 31:1 is not blocked
62261  */
62262 #define IOMUXC_LPSR_GPR_GPR10_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
62263 
62264 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U)
62265 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U)
62266 /*! APC_AC_R4_BOT - APC start address of memory region-4
62267  */
62268 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
62269 /*! @} */
62270 
62271 /*! @name GPR11 - GPR11 General Purpose Register */
62272 /*! @{ */
62273 
62274 #define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK          (0x1U)
62275 #define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT         (0U)
62276 /*! LOCK - Lock the write to bit 31:1
62277  *  0b1..Write access to bit 31:1 is blocked
62278  *  0b0..Write access to bit 31:1 is not blocked
62279  */
62280 #define IOMUXC_LPSR_GPR_GPR11_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
62281 
62282 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U)
62283 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U)
62284 /*! APC_AC_R4_TOP - APC end address of memory region-4
62285  */
62286 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
62287 /*! @} */
62288 
62289 /*! @name GPR12 - GPR12 General Purpose Register */
62290 /*! @{ */
62291 
62292 #define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK          (0x1U)
62293 #define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT         (0U)
62294 /*! LOCK - Lock the write to bit 31:1
62295  *  0b1..Write access to bit 31:1 is blocked
62296  *  0b0..Write access to bit 31:1 is not blocked
62297  */
62298 #define IOMUXC_LPSR_GPR_GPR12_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
62299 
62300 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U)
62301 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U)
62302 /*! APC_AC_R5_BOT - APC start address of memory region-5
62303  */
62304 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
62305 /*! @} */
62306 
62307 /*! @name GPR13 - GPR13 General Purpose Register */
62308 /*! @{ */
62309 
62310 #define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK          (0x1U)
62311 #define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT         (0U)
62312 /*! LOCK - Lock the write to bit 31:1
62313  *  0b1..Write access to bit 31:1 is blocked
62314  *  0b0..Write access to bit 31:1 is not blocked
62315  */
62316 #define IOMUXC_LPSR_GPR_GPR13_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
62317 
62318 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U)
62319 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U)
62320 /*! APC_AC_R5_TOP - APC end address of memory region-5
62321  */
62322 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
62323 /*! @} */
62324 
62325 /*! @name GPR14 - GPR14 General Purpose Register */
62326 /*! @{ */
62327 
62328 #define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK          (0x1U)
62329 #define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT         (0U)
62330 /*! LOCK - Lock the write to bit 31:1
62331  *  0b1..Write access to bit 31:1 is blocked
62332  *  0b0..Write access to bit 31:1 is not blocked
62333  */
62334 #define IOMUXC_LPSR_GPR_GPR14_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
62335 
62336 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U)
62337 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U)
62338 /*! APC_AC_R6_BOT - APC start address of memory region-6
62339  */
62340 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
62341 /*! @} */
62342 
62343 /*! @name GPR15 - GPR15 General Purpose Register */
62344 /*! @{ */
62345 
62346 #define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK          (0x1U)
62347 #define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT         (0U)
62348 /*! LOCK - Lock the write to bit 31:1
62349  *  0b1..Write access to bit 31:1 is blocked
62350  *  0b0..Write access to bit 31:1 is not blocked
62351  */
62352 #define IOMUXC_LPSR_GPR_GPR15_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
62353 
62354 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U)
62355 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U)
62356 /*! APC_AC_R6_TOP - APC end address of memory region-6
62357  */
62358 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
62359 /*! @} */
62360 
62361 /*! @name GPR16 - GPR16 General Purpose Register */
62362 /*! @{ */
62363 
62364 #define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK          (0x1U)
62365 #define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT         (0U)
62366 /*! LOCK - Lock the write to bit 31:1
62367  *  0b1..Write access to bit 31:1 is blocked
62368  *  0b0..Write access to bit 31:1 is not blocked
62369  */
62370 #define IOMUXC_LPSR_GPR_GPR16_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
62371 
62372 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U)
62373 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U)
62374 /*! APC_AC_R7_BOT - APC start address of memory region-7
62375  */
62376 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
62377 /*! @} */
62378 
62379 /*! @name GPR17 - GPR17 General Purpose Register */
62380 /*! @{ */
62381 
62382 #define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK          (0x1U)
62383 #define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT         (0U)
62384 /*! LOCK - Lock the write to bit 31:1
62385  *  0b1..Write access to bit 31:1 is blocked
62386  *  0b0..Write access to bit 31:1 is not blocked
62387  */
62388 #define IOMUXC_LPSR_GPR_GPR17_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
62389 
62390 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U)
62391 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U)
62392 /*! APC_AC_R7_TOP - APC end address of memory region-7
62393  */
62394 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
62395 /*! @} */
62396 
62397 /*! @name GPR18 - GPR18 General Purpose Register */
62398 /*! @{ */
62399 
62400 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U)
62401 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U)
62402 /*! APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable
62403  *  0b1..Encryption enabled
62404  *  0b0..No effect
62405  */
62406 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
62407 
62408 #define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK          (0xFFFF0000U)
62409 #define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT         (16U)
62410 /*! LOCK - Lock the write to bit 15:0
62411  */
62412 #define IOMUXC_LPSR_GPR_GPR18_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
62413 /*! @} */
62414 
62415 /*! @name GPR19 - GPR19 General Purpose Register */
62416 /*! @{ */
62417 
62418 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U)
62419 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U)
62420 /*! APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable
62421  *  0b1..Encryption enabled
62422  *  0b0..No effect
62423  */
62424 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK)
62425 
62426 #define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK          (0xFFFF0000U)
62427 #define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT         (16U)
62428 /*! LOCK - Lock the write to bit 15:0
62429  */
62430 #define IOMUXC_LPSR_GPR_GPR19_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK)
62431 /*! @} */
62432 
62433 /*! @name GPR20 - GPR20 General Purpose Register */
62434 /*! @{ */
62435 
62436 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U)
62437 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U)
62438 /*! APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable
62439  *  0b1..Encryption enabled
62440  *  0b0..No effect
62441  */
62442 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
62443 
62444 #define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK          (0xFFFF0000U)
62445 #define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT         (16U)
62446 /*! LOCK - Lock the write to bit 15:0
62447  */
62448 #define IOMUXC_LPSR_GPR_GPR20_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
62449 /*! @} */
62450 
62451 /*! @name GPR21 - GPR21 General Purpose Register */
62452 /*! @{ */
62453 
62454 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U)
62455 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U)
62456 /*! APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable
62457  *  0b1..Encryption enabled
62458  *  0b0..No effect
62459  */
62460 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
62461 
62462 #define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK          (0xFFFF0000U)
62463 #define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT         (16U)
62464 /*! LOCK - Lock the write to bit 15:0
62465  */
62466 #define IOMUXC_LPSR_GPR_GPR21_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
62467 /*! @} */
62468 
62469 /*! @name GPR22 - GPR22 General Purpose Register */
62470 /*! @{ */
62471 
62472 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U)
62473 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U)
62474 /*! APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable
62475  *  0b1..Encryption enabled
62476  *  0b0..No effect
62477  */
62478 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
62479 
62480 #define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK          (0xFFFF0000U)
62481 #define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT         (16U)
62482 /*! LOCK - Lock the write to bit 15:0
62483  */
62484 #define IOMUXC_LPSR_GPR_GPR22_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
62485 /*! @} */
62486 
62487 /*! @name GPR23 - GPR23 General Purpose Register */
62488 /*! @{ */
62489 
62490 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U)
62491 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U)
62492 /*! APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable
62493  *  0b1..Encryption enabled
62494  *  0b0..No effect
62495  */
62496 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
62497 
62498 #define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK          (0xFFFF0000U)
62499 #define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT         (16U)
62500 /*! LOCK - Lock the write to bit 15:0
62501  */
62502 #define IOMUXC_LPSR_GPR_GPR23_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
62503 /*! @} */
62504 
62505 /*! @name GPR24 - GPR24 General Purpose Register */
62506 /*! @{ */
62507 
62508 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U)
62509 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U)
62510 /*! APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable
62511  *  0b1..Encryption enabled
62512  *  0b0..No effect
62513  */
62514 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
62515 
62516 #define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK          (0xFFFF0000U)
62517 #define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT         (16U)
62518 /*! LOCK - Lock the write to bit 15:0
62519  */
62520 #define IOMUXC_LPSR_GPR_GPR24_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
62521 /*! @} */
62522 
62523 /*! @name GPR25 - GPR25 General Purpose Register */
62524 /*! @{ */
62525 
62526 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U)
62527 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U)
62528 /*! APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable
62529  *  0b1..Encryption enabled
62530  *  0b0..No effect
62531  */
62532 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
62533 
62534 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK     (0x20U)
62535 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT    (5U)
62536 /*! APC_VALID - APC global enable bit
62537  *  0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25)
62538  *  0b0..No effect
62539  */
62540 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
62541 
62542 #define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK          (0xFFFF0000U)
62543 #define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT         (16U)
62544 /*! LOCK - Lock the write to bit 15:0
62545  */
62546 #define IOMUXC_LPSR_GPR_GPR25_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
62547 /*! @} */
62548 
62549 /*! @name GPR26 - GPR26 General Purpose Register */
62550 /*! @{ */
62551 
62552 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU)
62553 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U)
62554 /*! CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture
62555  *    Reference Manual for more information about the vector table offset register (VTOR).
62556  */
62557 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
62558 
62559 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK       (0xE000000U)
62560 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT      (25U)
62561 /*! FIELD_0 - General purpose bits
62562  */
62563 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
62564 
62565 #define IOMUXC_LPSR_GPR_GPR26_DWP_MASK           (0x30000000U)
62566 #define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT          (28U)
62567 /*! DWP - Domain write protection
62568  *  0b00..Both cores are allowed
62569  *  0b01..CM7 is forbidden
62570  *  0b10..CM4 is forbidden
62571  *  0b11..Both cores are forbidden
62572  */
62573 #define IOMUXC_LPSR_GPR_GPR26_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
62574 
62575 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK      (0xC0000000U)
62576 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT     (30U)
62577 /*! DWP_LOCK - Domain write protection lock
62578  *  0b00..Neither of DWP bits is locked
62579  *  0b01..The lower DWP bit is locked
62580  *  0b10..The higher DWP bit is locked
62581  *  0b11..Both DWP bits are locked
62582  */
62583 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
62584 /*! @} */
62585 
62586 /*! @name GPR33 - GPR33 General Purpose Register */
62587 /*! @{ */
62588 
62589 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK  (0x1U)
62590 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U)
62591 /*! M4_NMI_CLEAR - Clear CM4 NMI holding register
62592  */
62593 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
62594 
62595 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U)
62596 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U)
62597 /*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
62598  */
62599 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
62600 
62601 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U)
62602 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U)
62603 /*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
62604  */
62605 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
62606 
62607 #define IOMUXC_LPSR_GPR_GPR33_DWP_MASK           (0x30000000U)
62608 #define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT          (28U)
62609 /*! DWP - Domain write protection
62610  *  0b00..Both cores are allowed
62611  *  0b01..CM7 is forbidden
62612  *  0b10..CM4 is forbidden
62613  *  0b11..Both cores are forbidden
62614  */
62615 #define IOMUXC_LPSR_GPR_GPR33_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
62616 
62617 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK      (0xC0000000U)
62618 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT     (30U)
62619 /*! DWP_LOCK - Domain write protection lock
62620  *  0b00..Neither of DWP bits is locked
62621  *  0b01..The lower DWP bit is locked
62622  *  0b10..The higher DWP bit is locked
62623  *  0b11..Both DWP bits are locked
62624  */
62625 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
62626 /*! @} */
62627 
62628 /*! @name GPR34 - GPR34 General Purpose Register */
62629 /*! @{ */
62630 
62631 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U)
62632 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U)
62633 /*! GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection
62634  */
62635 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
62636 
62637 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U)
62638 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U)
62639 /*! GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection
62640  */
62641 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
62642 
62643 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
62644 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT  (3U)
62645 /*! M7_NMI_MASK - Mask CM7 NMI pin input
62646  *  0b0..NMI input from IO to CM7 is not blocked
62647  *  0b1..NMI input from IO to CM7 is blocked
62648  */
62649 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
62650 
62651 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
62652 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT  (4U)
62653 /*! M4_NMI_MASK - Mask CM4 NMI pin input
62654  *  0b0..NMI input from IO to CM4 is not blocked
62655  *  0b1..NMI input from IO to CM4 is blocked
62656  */
62657 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
62658 
62659 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U)
62660 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U)
62661 /*! M4_GPC_SLEEP_SEL - CM4 sleep request selection
62662  *  0b0..CM4 SLEEPDEEP is sent to GPC
62663  *  0b1..CM4 SLEEPING is sent to GPC
62664  */
62665 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
62666 
62667 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK  (0x800U)
62668 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U)
62669 /*! SEC_ERR_RESP - Security error response enable
62670  *  0b0..OKEY response
62671  *  0b1..SLVError (default)
62672  */
62673 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
62674 
62675 #define IOMUXC_LPSR_GPR_GPR34_DWP_MASK           (0x30000000U)
62676 #define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT          (28U)
62677 /*! DWP - Domain write protection
62678  *  0b00..Both cores are allowed
62679  *  0b01..CM7 is forbidden
62680  *  0b10..CM4 is forbidden
62681  *  0b11..Both cores are forbidden
62682  */
62683 #define IOMUXC_LPSR_GPR_GPR34_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
62684 
62685 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK      (0xC0000000U)
62686 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT     (30U)
62687 /*! DWP_LOCK - Domain write protection lock
62688  *  0b00..Neither of DWP bits is locked
62689  *  0b01..The lower DWP bit is locked
62690  *  0b10..The higher DWP bit is locked
62691  *  0b11..Both DWP bits are locked
62692  */
62693 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
62694 /*! @} */
62695 
62696 /*! @name GPR35 - GPR35 General Purpose Register */
62697 /*! @{ */
62698 
62699 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U)
62700 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U)
62701 /*! ADC1_IPG_DOZE - ADC1 doze mode
62702  *  0b0..Not in doze mode
62703  *  0b1..In doze mode
62704  */
62705 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
62706 
62707 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U)
62708 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U)
62709 /*! ADC1_STOP_REQ - ADC1 stop request
62710  *  0b0..Stop request off
62711  *  0b1..Stop request on
62712  */
62713 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
62714 
62715 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U)
62716 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U)
62717 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted.
62718  *  0b0..This module is functional in Stop Mode
62719  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
62720  */
62721 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
62722 
62723 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U)
62724 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U)
62725 /*! ADC2_IPG_DOZE - ADC2 doze mode
62726  *  0b0..Not in doze mode
62727  *  0b1..In doze mode
62728  */
62729 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
62730 
62731 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U)
62732 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U)
62733 /*! ADC2_STOP_REQ - ADC2 stop request
62734  *  0b0..Stop request off
62735  *  0b1..Stop request on
62736  */
62737 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
62738 
62739 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U)
62740 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U)
62741 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted.
62742  *  0b0..This module is functional in Stop Mode
62743  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
62744  */
62745 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
62746 
62747 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U)
62748 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U)
62749 /*! CAAM_IPG_DOZE - CAN3 doze mode
62750  *  0b0..Not in doze mode
62751  *  0b1..In doze mode
62752  */
62753 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
62754 
62755 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U)
62756 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U)
62757 /*! CAAM_STOP_REQ - CAAM stop request
62758  *  0b0..Stop request off
62759  *  0b1..Stop request on
62760  */
62761 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
62762 
62763 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U)
62764 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U)
62765 /*! CAN1_IPG_DOZE - CAN1 doze mode
62766  *  0b0..Not in doze mode
62767  *  0b1..In doze mode
62768  */
62769 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
62770 
62771 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U)
62772 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U)
62773 /*! CAN1_STOP_REQ - CAN1 stop request
62774  *  0b0..Stop request off
62775  *  0b1..Stop request on
62776  */
62777 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
62778 
62779 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U)
62780 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U)
62781 /*! CAN2_IPG_DOZE - CAN2 doze mode
62782  *  0b0..Not in doze mode
62783  *  0b1..In doze mode
62784  */
62785 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
62786 
62787 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U)
62788 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U)
62789 /*! CAN2_STOP_REQ - CAN2 stop request
62790  *  0b0..Stop request off
62791  *  0b1..Stop request on
62792  */
62793 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
62794 
62795 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U)
62796 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U)
62797 /*! CAN3_IPG_DOZE - CAN3 doze mode
62798  *  0b0..Not in doze mode
62799  *  0b1..In doze mode
62800  */
62801 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
62802 
62803 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U)
62804 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U)
62805 /*! CAN3_STOP_REQ - CAN3 stop request
62806  *  0b0..Stop request off
62807  *  0b1..Stop request on
62808  */
62809 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
62810 
62811 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U)
62812 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U)
62813 /*! EDMA_STOP_REQ - EDMA stop request
62814  *  0b0..Stop request off
62815  *  0b1..Stop request on
62816  */
62817 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
62818 
62819 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
62820 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U)
62821 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
62822  *  0b0..Stop request off
62823  *  0b1..Stop request on
62824  */
62825 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
62826 
62827 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U)
62828 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U)
62829 /*! ENET_IPG_DOZE - ENET doze mode
62830  *  0b0..Not in doze mode
62831  *  0b1..In doze mode
62832  */
62833 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
62834 
62835 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U)
62836 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U)
62837 /*! ENET_STOP_REQ - ENET stop request
62838  *  0b0..Stop request off
62839  *  0b1..Stop request on
62840  */
62841 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
62842 
62843 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U)
62844 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U)
62845 /*! ENET1G_IPG_DOZE - ENET1G doze mode
62846  *  0b0..Not in doze mode
62847  *  0b1..In doze mode
62848  */
62849 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
62850 
62851 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U)
62852 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U)
62853 /*! ENET1G_STOP_REQ - ENET1G stop request
62854  *  0b0..Stop request off
62855  *  0b1..Stop request on
62856  */
62857 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
62858 
62859 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U)
62860 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U)
62861 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
62862  *  0b0..Not in doze mode
62863  *  0b1..In doze mode
62864  */
62865 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
62866 
62867 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U)
62868 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U)
62869 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
62870  *  0b0..Not in doze mode
62871  *  0b1..In doze mode
62872  */
62873 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
62874 
62875 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
62876 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U)
62877 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
62878  *  0b0..Not in doze mode
62879  *  0b1..In doze mode
62880  */
62881 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
62882 
62883 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
62884 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U)
62885 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
62886  *  0b0..Stop request off
62887  *  0b1..Stop request on
62888  */
62889 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
62890 
62891 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
62892 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U)
62893 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
62894  *  0b0..Not in doze mode
62895  *  0b1..In doze mode
62896  */
62897 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
62898 
62899 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
62900 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U)
62901 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
62902  *  0b0..Stop request off
62903  *  0b1..Stop request on
62904  */
62905 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
62906 
62907 #define IOMUXC_LPSR_GPR_GPR35_DWP_MASK           (0x30000000U)
62908 #define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT          (28U)
62909 /*! DWP - Domain write protection
62910  *  0b00..Both cores are allowed
62911  *  0b01..CM7 is forbidden
62912  *  0b10..CM4 is forbidden
62913  *  0b11..Both cores are forbidden
62914  */
62915 #define IOMUXC_LPSR_GPR_GPR35_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
62916 
62917 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK      (0xC0000000U)
62918 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT     (30U)
62919 /*! DWP_LOCK - Domain write protection lock
62920  *  0b00..Neither of DWP bits is locked
62921  *  0b01..The lower DWP bit is locked
62922  *  0b10..The higher DWP bit is locked
62923  *  0b11..Both DWP bits are locked
62924  */
62925 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
62926 /*! @} */
62927 
62928 /*! @name GPR36 - GPR36 General Purpose Register */
62929 /*! @{ */
62930 
62931 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U)
62932 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U)
62933 /*! GPT1_IPG_DOZE - GPT1 doze mode
62934  *  0b0..Not in doze mode
62935  *  0b1..In doze mode
62936  */
62937 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
62938 
62939 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U)
62940 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U)
62941 /*! GPT2_IPG_DOZE - GPT2 doze mode
62942  *  0b0..Not in doze mode
62943  *  0b1..In doze mode
62944  */
62945 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
62946 
62947 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U)
62948 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U)
62949 /*! GPT3_IPG_DOZE - GPT3 doze mode
62950  *  0b0..Not in doze mode
62951  *  0b1..In doze mode
62952  */
62953 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
62954 
62955 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U)
62956 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U)
62957 /*! GPT4_IPG_DOZE - GPT4 doze mode
62958  *  0b0..Not in doze mode
62959  *  0b1..In doze mode
62960  */
62961 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
62962 
62963 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U)
62964 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U)
62965 /*! GPT5_IPG_DOZE - GPT5 doze mode
62966  *  0b0..Not in doze mode
62967  *  0b1..In doze mode
62968  */
62969 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
62970 
62971 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U)
62972 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U)
62973 /*! GPT6_IPG_DOZE - GPT6 doze mode
62974  *  0b0..Not in doze mode
62975  *  0b1..In doze mode
62976  */
62977 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
62978 
62979 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U)
62980 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U)
62981 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
62982  *  0b0..Not in doze mode
62983  *  0b1..In doze mode
62984  */
62985 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
62986 
62987 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U)
62988 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U)
62989 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
62990  *  0b0..Stop request off
62991  *  0b1..Stop request on
62992  */
62993 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
62994 
62995 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
62996 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
62997 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted.
62998  *  0b0..This module is functional in Stop Mode
62999  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63000  */
63001 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
63002 
63003 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U)
63004 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U)
63005 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
63006  *  0b0..Not in doze mode
63007  *  0b1..In doze mode
63008  */
63009 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
63010 
63011 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U)
63012 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U)
63013 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
63014  *  0b0..Stop request off
63015  *  0b1..Stop request on
63016  */
63017 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
63018 
63019 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
63020 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
63021 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted.
63022  *  0b0..This module is functional in Stop Mode
63023  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63024  */
63025 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
63026 
63027 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U)
63028 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U)
63029 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
63030  *  0b0..Not in doze mode
63031  *  0b1..In doze mode
63032  */
63033 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
63034 
63035 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U)
63036 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U)
63037 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
63038  *  0b0..Stop request off
63039  *  0b1..Stop request on
63040  */
63041 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
63042 
63043 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
63044 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
63045 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted.
63046  *  0b0..This module is functional in Stop Mode
63047  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63048  */
63049 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
63050 
63051 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U)
63052 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U)
63053 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
63054  *  0b0..Not in doze mode
63055  *  0b1..In doze mode
63056  */
63057 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
63058 
63059 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U)
63060 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U)
63061 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
63062  *  0b0..Stop request off
63063  *  0b1..Stop request on
63064  */
63065 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
63066 
63067 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
63068 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
63069 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted.
63070  *  0b0..This module is functional in Stop Mode
63071  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63072  */
63073 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
63074 
63075 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U)
63076 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U)
63077 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
63078  *  0b0..Not in doze mode
63079  *  0b1..In doze mode
63080  */
63081 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
63082 
63083 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U)
63084 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U)
63085 /*! LPI2C5_STOP_REQ - LPI2C5 stop request
63086  *  0b0..Stop request off
63087  *  0b1..Stop request on
63088  */
63089 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
63090 
63091 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
63092 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
63093 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted.
63094  *  0b0..This module is functional in Stop Mode
63095  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63096  */
63097 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
63098 
63099 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U)
63100 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U)
63101 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
63102  *  0b0..Not in doze mode
63103  *  0b1..In doze mode
63104  */
63105 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
63106 
63107 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U)
63108 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U)
63109 /*! LPI2C6_STOP_REQ - LPI2C6 stop request
63110  *  0b0..Stop request off
63111  *  0b1..Stop request on
63112  */
63113 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
63114 
63115 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
63116 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
63117 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted.
63118  *  0b0..This module is functional in Stop Mode
63119  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63120  */
63121 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
63122 
63123 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U)
63124 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U)
63125 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
63126  *  0b0..Not in doze mode
63127  *  0b1..In doze mode
63128  */
63129 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
63130 
63131 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U)
63132 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U)
63133 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
63134  *  0b0..Stop request off
63135  *  0b1..Stop request on
63136  */
63137 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
63138 
63139 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
63140 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
63141 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted.
63142  *  0b0..This module is functional in Stop Mode
63143  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63144  */
63145 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
63146 
63147 #define IOMUXC_LPSR_GPR_GPR36_DWP_MASK           (0x30000000U)
63148 #define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT          (28U)
63149 /*! DWP - Domain write protection
63150  *  0b00..Both cores are allowed
63151  *  0b01..CM7 is forbidden
63152  *  0b10..CM4 is forbidden
63153  *  0b11..Both cores are forbidden
63154  */
63155 #define IOMUXC_LPSR_GPR_GPR36_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
63156 
63157 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK      (0xC0000000U)
63158 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT     (30U)
63159 /*! DWP_LOCK - Domain write protection lock
63160  *  0b00..Neither of DWP bits is locked
63161  *  0b01..The lower DWP bit is locked
63162  *  0b10..The higher DWP bit is locked
63163  *  0b11..Both DWP bits are locked
63164  */
63165 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
63166 /*! @} */
63167 
63168 /*! @name GPR37 - GPR37 General Purpose Register */
63169 /*! @{ */
63170 
63171 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U)
63172 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U)
63173 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
63174  *  0b0..Not in doze mode
63175  *  0b1..In doze mode
63176  */
63177 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
63178 
63179 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U)
63180 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U)
63181 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
63182  *  0b0..Stop request off
63183  *  0b1..Stop request on
63184  */
63185 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
63186 
63187 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
63188 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
63189 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted.
63190  *  0b0..This module is functional in Stop Mode
63191  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63192  */
63193 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
63194 
63195 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U)
63196 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U)
63197 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
63198  *  0b0..Not in doze mode
63199  *  0b1..In doze mode
63200  */
63201 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
63202 
63203 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U)
63204 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U)
63205 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
63206  *  0b0..Stop request off
63207  *  0b1..Stop request on
63208  */
63209 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
63210 
63211 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
63212 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
63213 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted.
63214  *  0b0..This module is functional in Stop Mode
63215  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63216  */
63217 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
63218 
63219 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U)
63220 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U)
63221 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
63222  *  0b0..Not in doze mode
63223  *  0b1..In doze mode
63224  */
63225 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
63226 
63227 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U)
63228 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U)
63229 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
63230  *  0b0..Stop request off
63231  *  0b1..Stop request on
63232  */
63233 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
63234 
63235 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
63236 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
63237 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted.
63238  *  0b0..This module is functional in Stop Mode
63239  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63240  */
63241 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
63242 
63243 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U)
63244 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U)
63245 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
63246  *  0b0..Not in doze mode
63247  *  0b1..In doze mode
63248  */
63249 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
63250 
63251 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U)
63252 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U)
63253 /*! LPSPI5_STOP_REQ - LPSPI5 stop request
63254  *  0b0..Stop request off
63255  *  0b1..Stop request on
63256  */
63257 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
63258 
63259 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
63260 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
63261 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted.
63262  *  0b0..This module is functional in Stop Mode
63263  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63264  */
63265 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
63266 
63267 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U)
63268 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U)
63269 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
63270  *  0b0..Not in doze mode
63271  *  0b1..In doze mode
63272  */
63273 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
63274 
63275 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U)
63276 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U)
63277 /*! LPSPI6_STOP_REQ - LPSPI6 stop request
63278  *  0b0..Stop request off
63279  *  0b1..Stop request on
63280  */
63281 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
63282 
63283 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
63284 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
63285 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted.
63286  *  0b0..This module is functional in Stop Mode
63287  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63288  */
63289 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
63290 
63291 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U)
63292 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U)
63293 /*! LPUART1_IPG_DOZE - LPUART1 doze mode
63294  *  0b0..Not in doze mode
63295  *  0b1..In doze mode
63296  */
63297 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
63298 
63299 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U)
63300 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U)
63301 /*! LPUART1_STOP_REQ - LPUART1 stop request
63302  *  0b0..Stop request off
63303  *  0b1..Stop request on
63304  */
63305 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
63306 
63307 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
63308 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U)
63309 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted.
63310  *  0b0..This module is functional in Stop Mode
63311  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63312  */
63313 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
63314 
63315 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U)
63316 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U)
63317 /*! LPUART2_IPG_DOZE - LPUART2 doze mode
63318  *  0b0..Not in doze mode
63319  *  0b1..In doze mode
63320  */
63321 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
63322 
63323 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U)
63324 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U)
63325 /*! LPUART2_STOP_REQ - LPUART2 stop request
63326  *  0b0..Stop request off
63327  *  0b1..Stop request on
63328  */
63329 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
63330 
63331 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
63332 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U)
63333 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted.
63334  *  0b0..This module is functional in Stop Mode
63335  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63336  */
63337 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
63338 
63339 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U)
63340 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U)
63341 /*! LPUART3_IPG_DOZE - LPUART3 doze mode
63342  *  0b0..Not in doze mode
63343  *  0b1..In doze mode
63344  */
63345 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
63346 
63347 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U)
63348 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U)
63349 /*! LPUART3_STOP_REQ - LPUART3 stop request
63350  *  0b0..Stop request off
63351  *  0b1..Stop request on
63352  */
63353 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
63354 
63355 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
63356 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U)
63357 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted.
63358  *  0b0..This module is functional in Stop Mode
63359  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63360  */
63361 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
63362 
63363 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U)
63364 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U)
63365 /*! LPUART4_IPG_DOZE - LPUART4 doze mode
63366  *  0b0..Not in doze mode
63367  *  0b1..In doze mode
63368  */
63369 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
63370 
63371 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U)
63372 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U)
63373 /*! LPUART4_STOP_REQ - LPUART4 stop request
63374  *  0b0..Stop request off
63375  *  0b1..Stop request on
63376  */
63377 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
63378 
63379 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
63380 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U)
63381 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted.
63382  *  0b0..This module is functional in Stop Mode
63383  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63384  */
63385 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
63386 
63387 #define IOMUXC_LPSR_GPR_GPR37_DWP_MASK           (0x30000000U)
63388 #define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT          (28U)
63389 /*! DWP - Domain write protection
63390  *  0b00..Both cores are allowed
63391  *  0b01..CM7 is forbidden
63392  *  0b10..CM4 is forbidden
63393  *  0b11..Both cores are forbidden
63394  */
63395 #define IOMUXC_LPSR_GPR_GPR37_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
63396 
63397 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK      (0xC0000000U)
63398 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT     (30U)
63399 /*! DWP_LOCK - Domain write protection lock
63400  *  0b00..Neither of DWP bits is locked
63401  *  0b01..The lower DWP bit is locked
63402  *  0b10..The higher DWP bit is locked
63403  *  0b11..Both DWP bits are locked
63404  */
63405 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
63406 /*! @} */
63407 
63408 /*! @name GPR38 - GPR38 General Purpose Register */
63409 /*! @{ */
63410 
63411 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U)
63412 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U)
63413 /*! LPUART5_IPG_DOZE - LPUART5 doze mode
63414  *  0b0..Not in doze mode
63415  *  0b1..In doze mode
63416  */
63417 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
63418 
63419 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U)
63420 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U)
63421 /*! LPUART5_STOP_REQ - LPUART5 stop request
63422  *  0b0..Stop request off
63423  *  0b1..Stop request on
63424  */
63425 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
63426 
63427 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U)
63428 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U)
63429 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted.
63430  *  0b0..This module is functional in Stop Mode
63431  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63432  */
63433 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
63434 
63435 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U)
63436 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U)
63437 /*! LPUART6_IPG_DOZE - LPUART6 doze mode
63438  *  0b0..Not in doze mode
63439  *  0b1..In doze mode
63440  */
63441 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
63442 
63443 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U)
63444 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U)
63445 /*! LPUART6_STOP_REQ - LPUART6 stop request
63446  *  0b0..Stop request off
63447  *  0b1..Stop request on
63448  */
63449 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
63450 
63451 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U)
63452 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U)
63453 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted.
63454  *  0b0..This module is functional in Stop Mode
63455  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63456  */
63457 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
63458 
63459 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U)
63460 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U)
63461 /*! LPUART7_IPG_DOZE - LPUART7 doze mode
63462  *  0b0..Not in doze mode
63463  *  0b1..In doze mode
63464  */
63465 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
63466 
63467 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U)
63468 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U)
63469 /*! LPUART7_STOP_REQ - LPUART7 stop request
63470  *  0b0..Stop request off
63471  *  0b1..Stop request on
63472  */
63473 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
63474 
63475 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U)
63476 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U)
63477 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted.
63478  *  0b0..This module is functional in Stop Mode
63479  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63480  */
63481 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
63482 
63483 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U)
63484 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U)
63485 /*! LPUART8_IPG_DOZE - LPUART8 doze mode
63486  *  0b0..Not in doze mode
63487  *  0b1..In doze mode
63488  */
63489 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
63490 
63491 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U)
63492 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U)
63493 /*! LPUART8_STOP_REQ - LPUART8 stop request
63494  *  0b0..Stop request off
63495  *  0b1..Stop request on
63496  */
63497 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
63498 
63499 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U)
63500 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U)
63501 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted.
63502  *  0b0..This module is functional in Stop Mode
63503  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63504  */
63505 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
63506 
63507 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U)
63508 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U)
63509 /*! LPUART9_IPG_DOZE - LPUART9 doze mode
63510  *  0b0..Not in doze mode
63511  *  0b1..In doze mode
63512  */
63513 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
63514 
63515 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U)
63516 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U)
63517 /*! LPUART9_STOP_REQ - LPUART9 stop request
63518  *  0b0..Stop request off
63519  *  0b1..Stop request on
63520  */
63521 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
63522 
63523 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
63524 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U)
63525 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted.
63526  *  0b0..This module is functional in Stop Mode
63527  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63528  */
63529 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
63530 
63531 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U)
63532 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U)
63533 /*! LPUART10_IPG_DOZE - LPUART10 doze mode
63534  *  0b0..Not in doze mode
63535  *  0b1..In doze mode
63536  */
63537 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
63538 
63539 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U)
63540 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U)
63541 /*! LPUART10_STOP_REQ - LPUART10 stop request
63542  *  0b0..Stop request off
63543  *  0b1..Stop request on
63544  */
63545 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
63546 
63547 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
63548 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U)
63549 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted.
63550  *  0b0..This module is functional in Stop Mode
63551  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63552  */
63553 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
63554 
63555 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U)
63556 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U)
63557 /*! LPUART11_IPG_DOZE - LPUART11 doze mode
63558  *  0b0..Not in doze mode
63559  *  0b1..In doze mode
63560  */
63561 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
63562 
63563 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U)
63564 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U)
63565 /*! LPUART11_STOP_REQ - LPUART11 stop request
63566  *  0b0..Stop request off
63567  *  0b1..Stop request on
63568  */
63569 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
63570 
63571 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
63572 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U)
63573 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted.
63574  *  0b0..This module is functional in Stop Mode
63575  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63576  */
63577 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
63578 
63579 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U)
63580 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U)
63581 /*! LPUART12_IPG_DOZE - LPUART12 doze mode
63582  *  0b0..Not in doze mode
63583  *  0b1..In doze mode
63584  */
63585 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
63586 
63587 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U)
63588 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U)
63589 /*! LPUART12_STOP_REQ - LPUART12 stop request
63590  *  0b0..Stop request off
63591  *  0b1..Stop request on
63592  */
63593 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
63594 
63595 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
63596 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U)
63597 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted.
63598  *  0b0..This module is functional in Stop Mode
63599  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63600  */
63601 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
63602 
63603 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK  (0x1000000U)
63604 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U)
63605 /*! MIC_IPG_DOZE - MIC doze mode
63606  *  0b0..Not in doze mode
63607  *  0b1..In doze mode
63608  */
63609 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
63610 
63611 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK  (0x2000000U)
63612 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U)
63613 /*! MIC_STOP_REQ - MIC stop request
63614  *  0b0..Stop request off
63615  *  0b1..Stop request on
63616  */
63617 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
63618 
63619 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U)
63620 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U)
63621 /*! MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted.
63622  *  0b0..This module is functional in Stop Mode
63623  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63624  */
63625 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
63626 
63627 #define IOMUXC_LPSR_GPR_GPR38_DWP_MASK           (0x30000000U)
63628 #define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT          (28U)
63629 /*! DWP - Domain write protection
63630  *  0b00..Both cores are allowed
63631  *  0b01..CM7 is forbidden
63632  *  0b10..CM4 is forbidden
63633  *  0b11..Both cores are forbidden
63634  */
63635 #define IOMUXC_LPSR_GPR_GPR38_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
63636 
63637 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK      (0xC0000000U)
63638 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT     (30U)
63639 /*! DWP_LOCK - Domain write protection lock
63640  *  0b00..Neither of DWP bits is locked
63641  *  0b01..The lower DWP bit is locked
63642  *  0b10..The higher DWP bit is locked
63643  *  0b11..Both DWP bits are locked
63644  */
63645 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
63646 /*! @} */
63647 
63648 /*! @name GPR39 - GPR39 General Purpose Register */
63649 /*! @{ */
63650 
63651 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U)
63652 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U)
63653 /*! PIT1_STOP_REQ - PIT1 stop request
63654  *  0b0..Stop request off
63655  *  0b1..Stop request on
63656  */
63657 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
63658 
63659 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U)
63660 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U)
63661 /*! PIT2_STOP_REQ - PIT2 stop request
63662  *  0b0..Stop request off
63663  *  0b1..Stop request on
63664  */
63665 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
63666 
63667 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U)
63668 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U)
63669 /*! SEMC_STOP_REQ - SEMC stop request
63670  *  0b0..Stop request off
63671  *  0b1..Stop request on
63672  */
63673 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
63674 
63675 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U)
63676 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U)
63677 /*! SIM1_IPG_DOZE - SIM1 doze mode
63678  *  0b0..Not in doze mode
63679  *  0b1..In doze mode
63680  */
63681 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
63682 
63683 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U)
63684 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U)
63685 /*! SIM2_IPG_DOZE - SIM2 doze mode
63686  *  0b0..Not in doze mode
63687  *  0b1..In doze mode
63688  */
63689 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
63690 
63691 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U)
63692 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U)
63693 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
63694  *  0b0..Not in doze mode
63695  *  0b1..In doze mode
63696  */
63697 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
63698 
63699 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U)
63700 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U)
63701 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request
63702  *  0b0..Stop request off
63703  *  0b1..Stop request on
63704  */
63705 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
63706 
63707 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U)
63708 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U)
63709 /*! WDOG1_IPG_DOZE - WDOG1 doze mode
63710  *  0b0..Not in doze mode
63711  *  0b1..In doze mode
63712  */
63713 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
63714 
63715 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U)
63716 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U)
63717 /*! WDOG2_IPG_DOZE - WDOG2 doze mode
63718  *  0b0..Not in doze mode
63719  *  0b1..In doze mode
63720  */
63721 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
63722 
63723 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U)
63724 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U)
63725 /*! SAI1_STOP_REQ - SAI1 stop request
63726  *  0b0..Stop request off
63727  *  0b1..Stop request on
63728  */
63729 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
63730 
63731 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U)
63732 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U)
63733 /*! SAI2_STOP_REQ - SAI2 stop request
63734  *  0b0..Stop request off
63735  *  0b1..Stop request on
63736  */
63737 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
63738 
63739 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U)
63740 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U)
63741 /*! SAI3_STOP_REQ - SAI3 stop request
63742  *  0b0..Stop request off
63743  *  0b1..Stop request on
63744  */
63745 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
63746 
63747 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U)
63748 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U)
63749 /*! SAI4_STOP_REQ - SAI4 stop request
63750  *  0b0..Stop request off
63751  *  0b1..Stop request on
63752  */
63753 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
63754 
63755 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
63756 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
63757 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
63758  *  0b0..Stop request off
63759  *  0b1..Stop request on
63760  */
63761 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
63762 
63763 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
63764 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
63765 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
63766  *  0b0..Stop request off
63767  *  0b1..Stop request on
63768  */
63769 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
63770 
63771 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
63772 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
63773 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
63774  *  0b0..Stop request off
63775  *  0b1..Stop request on
63776  */
63777 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
63778 
63779 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
63780 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
63781 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
63782  *  0b0..Stop request off
63783  *  0b1..Stop request on
63784  */
63785 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
63786 
63787 #define IOMUXC_LPSR_GPR_GPR39_DWP_MASK           (0x30000000U)
63788 #define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT          (28U)
63789 /*! DWP - Domain write protection
63790  *  0b00..Both cores are allowed
63791  *  0b01..CM7 is forbidden
63792  *  0b10..CM4 is forbidden
63793  *  0b11..Both cores are forbidden
63794  */
63795 #define IOMUXC_LPSR_GPR_GPR39_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
63796 
63797 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK      (0xC0000000U)
63798 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT     (30U)
63799 /*! DWP_LOCK - Domain write protection lock
63800  *  0b00..Neither of DWP bits is locked
63801  *  0b01..The lower DWP bit is locked
63802  *  0b10..The higher DWP bit is locked
63803  *  0b11..Both DWP bits are locked
63804  */
63805 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
63806 /*! @} */
63807 
63808 /*! @name GPR40 - GPR40 General Purpose Register */
63809 /*! @{ */
63810 
63811 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U)
63812 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U)
63813 /*! ADC1_STOP_ACK - ADC1 stop acknowledge
63814  */
63815 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
63816 
63817 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U)
63818 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U)
63819 /*! ADC2_STOP_ACK - ADC2 stop acknowledge
63820  */
63821 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
63822 
63823 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U)
63824 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U)
63825 /*! CAAM_STOP_ACK - CAAM stop acknowledge
63826  */
63827 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
63828 
63829 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U)
63830 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U)
63831 /*! CAN1_STOP_ACK - CAN1 stop acknowledge
63832  */
63833 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
63834 
63835 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U)
63836 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U)
63837 /*! CAN2_STOP_ACK - CAN2 stop acknowledge
63838  */
63839 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
63840 
63841 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U)
63842 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U)
63843 /*! CAN3_STOP_ACK - CAN3 stop acknowledge
63844  */
63845 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
63846 
63847 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U)
63848 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U)
63849 /*! EDMA_STOP_ACK - EDMA stop acknowledge
63850  */
63851 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
63852 
63853 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U)
63854 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U)
63855 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
63856  */
63857 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
63858 
63859 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U)
63860 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U)
63861 /*! ENET_STOP_ACK - ENET stop acknowledge
63862  */
63863 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
63864 
63865 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U)
63866 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U)
63867 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge
63868  */
63869 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
63870 
63871 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U)
63872 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U)
63873 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
63874  */
63875 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
63876 
63877 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U)
63878 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U)
63879 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
63880  */
63881 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
63882 
63883 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U)
63884 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U)
63885 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
63886  */
63887 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
63888 
63889 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U)
63890 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U)
63891 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
63892  */
63893 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
63894 
63895 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U)
63896 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U)
63897 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
63898  */
63899 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
63900 
63901 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U)
63902 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U)
63903 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
63904  */
63905 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
63906 
63907 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U)
63908 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U)
63909 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
63910  */
63911 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
63912 
63913 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U)
63914 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U)
63915 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
63916  */
63917 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
63918 
63919 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U)
63920 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U)
63921 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
63922  */
63923 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
63924 
63925 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U)
63926 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U)
63927 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
63928  */
63929 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
63930 
63931 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U)
63932 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U)
63933 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
63934  */
63935 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
63936 
63937 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U)
63938 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U)
63939 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
63940  */
63941 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
63942 
63943 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U)
63944 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U)
63945 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
63946  */
63947 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
63948 
63949 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U)
63950 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U)
63951 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
63952  */
63953 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
63954 
63955 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U)
63956 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U)
63957 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
63958  */
63959 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
63960 
63961 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U)
63962 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U)
63963 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
63964  */
63965 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
63966 
63967 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U)
63968 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U)
63969 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
63970  */
63971 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
63972 
63973 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U)
63974 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U)
63975 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
63976  */
63977 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
63978 
63979 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U)
63980 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U)
63981 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
63982  */
63983 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
63984 
63985 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U)
63986 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U)
63987 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
63988  */
63989 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
63990 
63991 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U)
63992 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U)
63993 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
63994  */
63995 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
63996 
63997 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U)
63998 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U)
63999 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
64000  */
64001 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
64002 /*! @} */
64003 
64004 /*! @name GPR41 - GPR41 General Purpose Register */
64005 /*! @{ */
64006 
64007 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U)
64008 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U)
64009 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
64010  */
64011 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
64012 
64013 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U)
64014 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U)
64015 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
64016  */
64017 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
64018 
64019 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U)
64020 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U)
64021 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
64022  */
64023 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
64024 
64025 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U)
64026 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U)
64027 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
64028  */
64029 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
64030 
64031 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK  (0x10U)
64032 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U)
64033 /*! MIC_STOP_ACK - MIC stop acknowledge
64034  */
64035 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
64036 
64037 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U)
64038 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U)
64039 /*! PIT1_STOP_ACK - PIT1 stop acknowledge
64040  */
64041 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
64042 
64043 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U)
64044 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U)
64045 /*! PIT2_STOP_ACK - PIT2 stop acknowledge
64046  */
64047 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
64048 
64049 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U)
64050 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U)
64051 /*! SEMC_STOP_ACK - SEMC stop acknowledge
64052  */
64053 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
64054 
64055 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U)
64056 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U)
64057 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
64058  */
64059 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
64060 
64061 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U)
64062 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U)
64063 /*! SAI1_STOP_ACK - SAI1 stop acknowledge
64064  */
64065 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
64066 
64067 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U)
64068 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U)
64069 /*! SAI2_STOP_ACK - SAI2 stop acknowledge
64070  */
64071 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
64072 
64073 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U)
64074 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U)
64075 /*! SAI3_STOP_ACK - SAI3 stop acknowledge
64076  */
64077 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
64078 
64079 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U)
64080 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U)
64081 /*! SAI4_STOP_ACK - SAI4 stop acknowledge
64082  */
64083 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
64084 
64085 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
64086 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
64087 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
64088  */
64089 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
64090 
64091 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
64092 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
64093 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
64094  */
64095 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
64096 
64097 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
64098 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
64099 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
64100  */
64101 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
64102 
64103 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
64104 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
64105 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
64106  */
64107 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
64108 
64109 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U)
64110 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U)
64111 /*! ROM_READ_LOCKED - ROM read lock status bit
64112  */
64113 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
64114 /*! @} */
64115 
64116 
64117 /*!
64118  * @}
64119  */ /* end of group IOMUXC_LPSR_GPR_Register_Masks */
64120 
64121 
64122 /* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
64123 /** Peripheral IOMUXC_LPSR_GPR base address */
64124 #define IOMUXC_LPSR_GPR_BASE                     (0x40C0C000u)
64125 /** Peripheral IOMUXC_LPSR_GPR base pointer */
64126 #define IOMUXC_LPSR_GPR                          ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
64127 /** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */
64128 #define IOMUXC_LPSR_GPR_BASE_ADDRS               { IOMUXC_LPSR_GPR_BASE }
64129 /** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */
64130 #define IOMUXC_LPSR_GPR_BASE_PTRS                { IOMUXC_LPSR_GPR }
64131 
64132 /*!
64133  * @}
64134  */ /* end of group IOMUXC_LPSR_GPR_Peripheral_Access_Layer */
64135 
64136 
64137 /* ----------------------------------------------------------------------------
64138    -- IOMUXC_SNVS Peripheral Access Layer
64139    ---------------------------------------------------------------------------- */
64140 
64141 /*!
64142  * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
64143  * @{
64144  */
64145 
64146 /** IOMUXC_SNVS - Register Layout Typedef */
64147 typedef struct {
64148   __IO uint32_t SW_MUX_CTL_PAD_WAKEUP_DIG;         /**< SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0 */
64149   __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4 */
64150   __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8 */
64151   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC */
64152   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10 */
64153   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14 */
64154   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18 */
64155   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C */
64156   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20 */
64157   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24 */
64158   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28 */
64159   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C */
64160   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30 */
64161   __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE_DIG;      /**< SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34 */
64162   __IO uint32_t SW_PAD_CTL_PAD_POR_B_DIG;          /**< SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38 */
64163   __IO uint32_t SW_PAD_CTL_PAD_ONOFF_DIG;          /**< SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C */
64164   __IO uint32_t SW_PAD_CTL_PAD_WAKEUP_DIG;         /**< SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40 */
64165   __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44 */
64166   __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48 */
64167   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C */
64168   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50 */
64169   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54 */
64170   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58 */
64171   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C */
64172   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60 */
64173   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64 */
64174   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68 */
64175   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C */
64176   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70 */
64177 } IOMUXC_SNVS_Type;
64178 
64179 /* ----------------------------------------------------------------------------
64180    -- IOMUXC_SNVS Register Masks
64181    ---------------------------------------------------------------------------- */
64182 
64183 /*!
64184  * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
64185  * @{
64186  */
64187 
64188 /*! @name SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register */
64189 /*! @{ */
64190 
64191 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)
64192 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)
64193 /*! MUX_MODE - MUX Mode Select Field.
64194  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13
64195  *  0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE
64196  */
64197 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)
64198 
64199 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)
64200 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)
64201 /*! SION - Software Input On Field.
64202  *  0b1..Force input path of pad WAKEUP_DIG
64203  *  0b0..Input Path is determined by functionality
64204  */
64205 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)
64206 /*! @} */
64207 
64208 /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register */
64209 /*! @{ */
64210 
64211 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)
64212 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)
64213 /*! MUX_MODE - MUX Mode Select Field.
64214  *  0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP
64215  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13
64216  */
64217 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)
64218 
64219 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)
64220 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)
64221 /*! SION - Software Input On Field.
64222  *  0b1..Force input path of pad PMIC_ON_REQ_DIG
64223  *  0b0..Input Path is determined by functionality
64224  */
64225 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)
64226 /*! @} */
64227 
64228 /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register */
64229 /*! @{ */
64230 
64231 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)
64232 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)
64233 /*! MUX_MODE - MUX Mode Select Field.
64234  *  0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM
64235  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13
64236  */
64237 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)
64238 
64239 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)
64240 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)
64241 /*! SION - Software Input On Field.
64242  *  0b1..Force input path of pad PMIC_STBY_REQ_DIG
64243  *  0b0..Input Path is determined by functionality
64244  */
64245 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)
64246 /*! @} */
64247 
64248 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register */
64249 /*! @{ */
64250 
64251 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)
64252 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)
64253 /*! MUX_MODE - MUX Mode Select Field.
64254  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP
64255  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13
64256  */
64257 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)
64258 
64259 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)
64260 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)
64261 /*! SION - Software Input On Field.
64262  *  0b1..Force input path of pad GPIO_SNVS_00_DIG
64263  *  0b0..Input Path is determined by functionality
64264  */
64265 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)
64266 /*! @} */
64267 
64268 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register */
64269 /*! @{ */
64270 
64271 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)
64272 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)
64273 /*! MUX_MODE - MUX Mode Select Field.
64274  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP
64275  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13
64276  */
64277 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)
64278 
64279 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)
64280 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)
64281 /*! SION - Software Input On Field.
64282  *  0b1..Force input path of pad GPIO_SNVS_01_DIG
64283  *  0b0..Input Path is determined by functionality
64284  */
64285 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)
64286 /*! @} */
64287 
64288 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register */
64289 /*! @{ */
64290 
64291 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)
64292 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)
64293 /*! MUX_MODE - MUX Mode Select Field.
64294  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP
64295  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13
64296  */
64297 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)
64298 
64299 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)
64300 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)
64301 /*! SION - Software Input On Field.
64302  *  0b1..Force input path of pad GPIO_SNVS_02_DIG
64303  *  0b0..Input Path is determined by functionality
64304  */
64305 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)
64306 /*! @} */
64307 
64308 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register */
64309 /*! @{ */
64310 
64311 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)
64312 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)
64313 /*! MUX_MODE - MUX Mode Select Field.
64314  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP
64315  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13
64316  */
64317 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)
64318 
64319 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)
64320 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)
64321 /*! SION - Software Input On Field.
64322  *  0b1..Force input path of pad GPIO_SNVS_03_DIG
64323  *  0b0..Input Path is determined by functionality
64324  */
64325 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)
64326 /*! @} */
64327 
64328 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register */
64329 /*! @{ */
64330 
64331 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)
64332 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)
64333 /*! MUX_MODE - MUX Mode Select Field.
64334  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP
64335  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13
64336  */
64337 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)
64338 
64339 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)
64340 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)
64341 /*! SION - Software Input On Field.
64342  *  0b1..Force input path of pad GPIO_SNVS_04_DIG
64343  *  0b0..Input Path is determined by functionality
64344  */
64345 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)
64346 /*! @} */
64347 
64348 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register */
64349 /*! @{ */
64350 
64351 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)
64352 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)
64353 /*! MUX_MODE - MUX Mode Select Field.
64354  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP
64355  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13
64356  */
64357 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)
64358 
64359 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)
64360 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)
64361 /*! SION - Software Input On Field.
64362  *  0b1..Force input path of pad GPIO_SNVS_05_DIG
64363  *  0b0..Input Path is determined by functionality
64364  */
64365 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)
64366 /*! @} */
64367 
64368 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register */
64369 /*! @{ */
64370 
64371 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)
64372 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)
64373 /*! MUX_MODE - MUX Mode Select Field.
64374  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP
64375  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13
64376  */
64377 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)
64378 
64379 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)
64380 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)
64381 /*! SION - Software Input On Field.
64382  *  0b1..Force input path of pad GPIO_SNVS_06_DIG
64383  *  0b0..Input Path is determined by functionality
64384  */
64385 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)
64386 /*! @} */
64387 
64388 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register */
64389 /*! @{ */
64390 
64391 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)
64392 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)
64393 /*! MUX_MODE - MUX Mode Select Field.
64394  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP
64395  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13
64396  */
64397 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)
64398 
64399 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)
64400 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)
64401 /*! SION - Software Input On Field.
64402  *  0b1..Force input path of pad GPIO_SNVS_07_DIG
64403  *  0b0..Input Path is determined by functionality
64404  */
64405 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)
64406 /*! @} */
64407 
64408 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register */
64409 /*! @{ */
64410 
64411 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)
64412 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)
64413 /*! MUX_MODE - MUX Mode Select Field.
64414  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP
64415  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13
64416  */
64417 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)
64418 
64419 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)
64420 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)
64421 /*! SION - Software Input On Field.
64422  *  0b1..Force input path of pad GPIO_SNVS_08_DIG
64423  *  0b0..Input Path is determined by functionality
64424  */
64425 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)
64426 /*! @} */
64427 
64428 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register */
64429 /*! @{ */
64430 
64431 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)
64432 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)
64433 /*! MUX_MODE - MUX Mode Select Field.
64434  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP
64435  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13
64436  */
64437 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)
64438 
64439 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)
64440 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)
64441 /*! SION - Software Input On Field.
64442  *  0b1..Force input path of pad GPIO_SNVS_09_DIG
64443  *  0b0..Input Path is determined by functionality
64444  */
64445 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)
64446 /*! @} */
64447 
64448 /*! @name SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register */
64449 /*! @{ */
64450 
64451 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)
64452 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)
64453 /*! SRE - Slew Rate Field
64454  *  0b0..Slow Slew Rate
64455  *  0b1..Fast Slew Rate
64456  */
64457 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)
64458 
64459 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)
64460 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)
64461 /*! DSE - Drive Strength Field
64462  *  0b0..normal driver
64463  *  0b1..high driver
64464  */
64465 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)
64466 
64467 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)
64468 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)
64469 /*! PUE - Pull / Keep Select Field
64470  *  0b0..Pull Disable
64471  *  0b1..Pull Enable
64472  */
64473 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)
64474 
64475 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)
64476 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)
64477 /*! PUS - Pull Up / Down Config. Field
64478  *  0b0..Weak pull down
64479  *  0b1..Weak pull up
64480  */
64481 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)
64482 
64483 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)
64484 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)
64485 /*! DWP - Domain write protection
64486  *  0b00..Both cores are allowed
64487  *  0b01..CM7 is forbidden
64488  *  0b10..CM4 is forbidden
64489  *  0b11..Both cores are forbidden
64490  */
64491 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)
64492 
64493 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)
64494 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)
64495 /*! DWP_LOCK - Domain write protection lock
64496  *  0b00..Neither of DWP bits is locked
64497  *  0b01..The lower DWP bit is locked
64498  *  0b10..The higher DWP bit is locked
64499  *  0b11..Both DWP bits are locked
64500  */
64501 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)
64502 /*! @} */
64503 
64504 /*! @name SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register */
64505 /*! @{ */
64506 
64507 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)
64508 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)
64509 /*! SRE - Slew Rate Field
64510  *  0b0..Slow Slew Rate
64511  *  0b1..Fast Slew Rate
64512  */
64513 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)
64514 
64515 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)
64516 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)
64517 /*! DSE - Drive Strength Field
64518  *  0b0..normal driver
64519  *  0b1..high driver
64520  */
64521 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)
64522 
64523 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)
64524 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)
64525 /*! PUE - Pull / Keep Select Field
64526  *  0b0..Pull Disable
64527  *  0b1..Pull Enable
64528  */
64529 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)
64530 
64531 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)
64532 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)
64533 /*! PUS - Pull Up / Down Config. Field
64534  *  0b0..Weak pull down
64535  *  0b1..Weak pull up
64536  */
64537 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)
64538 
64539 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)
64540 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)
64541 /*! DWP - Domain write protection
64542  *  0b00..Both cores are allowed
64543  *  0b01..CM7 is forbidden
64544  *  0b10..CM4 is forbidden
64545  *  0b11..Both cores are forbidden
64546  */
64547 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)
64548 
64549 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)
64550 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)
64551 /*! DWP_LOCK - Domain write protection lock
64552  *  0b00..Neither of DWP bits is locked
64553  *  0b01..The lower DWP bit is locked
64554  *  0b10..The higher DWP bit is locked
64555  *  0b11..Both DWP bits are locked
64556  */
64557 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)
64558 /*! @} */
64559 
64560 /*! @name SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register */
64561 /*! @{ */
64562 
64563 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)
64564 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)
64565 /*! SRE - Slew Rate Field
64566  *  0b0..Slow Slew Rate
64567  *  0b1..Fast Slew Rate
64568  */
64569 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)
64570 
64571 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)
64572 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)
64573 /*! DSE - Drive Strength Field
64574  *  0b0..normal driver
64575  *  0b1..high driver
64576  */
64577 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)
64578 
64579 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)
64580 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)
64581 /*! PUE - Pull / Keep Select Field
64582  *  0b0..Pull Disable
64583  *  0b1..Pull Enable
64584  */
64585 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)
64586 
64587 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)
64588 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)
64589 /*! PUS - Pull Up / Down Config. Field
64590  *  0b0..Weak pull down
64591  *  0b1..Weak pull up
64592  */
64593 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)
64594 
64595 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)
64596 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)
64597 /*! DWP - Domain write protection
64598  *  0b00..Both cores are allowed
64599  *  0b01..CM7 is forbidden
64600  *  0b10..CM4 is forbidden
64601  *  0b11..Both cores are forbidden
64602  */
64603 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)
64604 
64605 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)
64606 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)
64607 /*! DWP_LOCK - Domain write protection lock
64608  *  0b00..Neither of DWP bits is locked
64609  *  0b01..The lower DWP bit is locked
64610  *  0b10..The higher DWP bit is locked
64611  *  0b11..Both DWP bits are locked
64612  */
64613 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)
64614 /*! @} */
64615 
64616 /*! @name SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register */
64617 /*! @{ */
64618 
64619 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)
64620 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)
64621 /*! SRE - Slew Rate Field
64622  *  0b0..Slow Slew Rate
64623  *  0b1..Fast Slew Rate
64624  */
64625 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)
64626 
64627 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)
64628 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)
64629 /*! DSE - Drive Strength Field
64630  *  0b0..normal driver
64631  *  0b1..high driver
64632  */
64633 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)
64634 
64635 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)
64636 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)
64637 /*! PUE - Pull / Keep Select Field
64638  *  0b0..Pull Disable
64639  *  0b1..Pull Enable
64640  */
64641 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)
64642 
64643 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)
64644 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)
64645 /*! PUS - Pull Up / Down Config. Field
64646  *  0b0..Weak pull down
64647  *  0b1..Weak pull up
64648  */
64649 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)
64650 
64651 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)
64652 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)
64653 /*! ODE_SNVS - Open Drain SNVS Field
64654  *  0b0..Disabled
64655  *  0b1..Enabled
64656  */
64657 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)
64658 
64659 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)
64660 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)
64661 /*! DWP - Domain write protection
64662  *  0b00..Both cores are allowed
64663  *  0b01..CM7 is forbidden
64664  *  0b10..CM4 is forbidden
64665  *  0b11..Both cores are forbidden
64666  */
64667 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)
64668 
64669 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)
64670 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)
64671 /*! DWP_LOCK - Domain write protection lock
64672  *  0b00..Neither of DWP bits is locked
64673  *  0b01..The lower DWP bit is locked
64674  *  0b10..The higher DWP bit is locked
64675  *  0b11..Both DWP bits are locked
64676  */
64677 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)
64678 /*! @} */
64679 
64680 /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register */
64681 /*! @{ */
64682 
64683 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)
64684 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)
64685 /*! SRE - Slew Rate Field
64686  *  0b0..Slow Slew Rate
64687  *  0b1..Fast Slew Rate
64688  */
64689 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)
64690 
64691 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)
64692 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)
64693 /*! DSE - Drive Strength Field
64694  *  0b0..normal driver
64695  *  0b1..high driver
64696  */
64697 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)
64698 
64699 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)
64700 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)
64701 /*! PUE - Pull / Keep Select Field
64702  *  0b0..Pull Disable
64703  *  0b1..Pull Enable
64704  */
64705 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)
64706 
64707 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)
64708 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)
64709 /*! PUS - Pull Up / Down Config. Field
64710  *  0b0..Weak pull down
64711  *  0b1..Weak pull up
64712  */
64713 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)
64714 
64715 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)
64716 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)
64717 /*! ODE_SNVS - Open Drain SNVS Field
64718  *  0b0..Disabled
64719  *  0b1..Enabled
64720  */
64721 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)
64722 
64723 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)
64724 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)
64725 /*! DWP - Domain write protection
64726  *  0b00..Both cores are allowed
64727  *  0b01..CM7 is forbidden
64728  *  0b10..CM4 is forbidden
64729  *  0b11..Both cores are forbidden
64730  */
64731 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)
64732 
64733 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
64734 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)
64735 /*! DWP_LOCK - Domain write protection lock
64736  *  0b00..Neither of DWP bits is locked
64737  *  0b01..The lower DWP bit is locked
64738  *  0b10..The higher DWP bit is locked
64739  *  0b11..Both DWP bits are locked
64740  */
64741 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)
64742 /*! @} */
64743 
64744 /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register */
64745 /*! @{ */
64746 
64747 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)
64748 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)
64749 /*! SRE - Slew Rate Field
64750  *  0b0..Slow Slew Rate
64751  *  0b1..Fast Slew Rate
64752  */
64753 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)
64754 
64755 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)
64756 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)
64757 /*! DSE - Drive Strength Field
64758  *  0b0..normal driver
64759  *  0b1..high driver
64760  */
64761 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)
64762 
64763 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)
64764 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)
64765 /*! PUE - Pull / Keep Select Field
64766  *  0b0..Pull Disable
64767  *  0b1..Pull Enable
64768  */
64769 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)
64770 
64771 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)
64772 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)
64773 /*! PUS - Pull Up / Down Config. Field
64774  *  0b0..Weak pull down
64775  *  0b1..Weak pull up
64776  */
64777 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)
64778 
64779 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)
64780 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)
64781 /*! ODE_SNVS - Open Drain SNVS Field
64782  *  0b0..Disabled
64783  *  0b1..Enabled
64784  */
64785 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)
64786 
64787 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)
64788 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)
64789 /*! DWP - Domain write protection
64790  *  0b00..Both cores are allowed
64791  *  0b01..CM7 is forbidden
64792  *  0b10..CM4 is forbidden
64793  *  0b11..Both cores are forbidden
64794  */
64795 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)
64796 
64797 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
64798 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)
64799 /*! DWP_LOCK - Domain write protection lock
64800  *  0b00..Neither of DWP bits is locked
64801  *  0b01..The lower DWP bit is locked
64802  *  0b10..The higher DWP bit is locked
64803  *  0b11..Both DWP bits are locked
64804  */
64805 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)
64806 /*! @} */
64807 
64808 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register */
64809 /*! @{ */
64810 
64811 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)
64812 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)
64813 /*! SRE - Slew Rate Field
64814  *  0b0..Slow Slew Rate
64815  *  0b1..Fast Slew Rate
64816  */
64817 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)
64818 
64819 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)
64820 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)
64821 /*! DSE - Drive Strength Field
64822  *  0b0..normal driver
64823  *  0b1..high driver
64824  */
64825 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)
64826 
64827 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)
64828 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)
64829 /*! PUE - Pull / Keep Select Field
64830  *  0b0..Pull Disable
64831  *  0b1..Pull Enable
64832  */
64833 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)
64834 
64835 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)
64836 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)
64837 /*! PUS - Pull Up / Down Config. Field
64838  *  0b0..Weak pull down
64839  *  0b1..Weak pull up
64840  */
64841 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)
64842 
64843 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)
64844 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)
64845 /*! ODE_SNVS - Open Drain SNVS Field
64846  *  0b0..Disabled
64847  *  0b1..Enabled
64848  */
64849 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)
64850 
64851 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)
64852 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)
64853 /*! DWP - Domain write protection
64854  *  0b00..Both cores are allowed
64855  *  0b01..CM7 is forbidden
64856  *  0b10..CM4 is forbidden
64857  *  0b11..Both cores are forbidden
64858  */
64859 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)
64860 
64861 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)
64862 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)
64863 /*! DWP_LOCK - Domain write protection lock
64864  *  0b00..Neither of DWP bits is locked
64865  *  0b01..The lower DWP bit is locked
64866  *  0b10..The higher DWP bit is locked
64867  *  0b11..Both DWP bits are locked
64868  */
64869 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)
64870 /*! @} */
64871 
64872 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register */
64873 /*! @{ */
64874 
64875 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)
64876 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)
64877 /*! SRE - Slew Rate Field
64878  *  0b0..Slow Slew Rate
64879  *  0b1..Fast Slew Rate
64880  */
64881 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)
64882 
64883 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)
64884 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)
64885 /*! DSE - Drive Strength Field
64886  *  0b0..normal driver
64887  *  0b1..high driver
64888  */
64889 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)
64890 
64891 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)
64892 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)
64893 /*! PUE - Pull / Keep Select Field
64894  *  0b0..Pull Disable
64895  *  0b1..Pull Enable
64896  */
64897 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)
64898 
64899 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)
64900 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)
64901 /*! PUS - Pull Up / Down Config. Field
64902  *  0b0..Weak pull down
64903  *  0b1..Weak pull up
64904  */
64905 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)
64906 
64907 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)
64908 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)
64909 /*! ODE_SNVS - Open Drain SNVS Field
64910  *  0b0..Disabled
64911  *  0b1..Enabled
64912  */
64913 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)
64914 
64915 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)
64916 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)
64917 /*! DWP - Domain write protection
64918  *  0b00..Both cores are allowed
64919  *  0b01..CM7 is forbidden
64920  *  0b10..CM4 is forbidden
64921  *  0b11..Both cores are forbidden
64922  */
64923 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)
64924 
64925 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)
64926 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)
64927 /*! DWP_LOCK - Domain write protection lock
64928  *  0b00..Neither of DWP bits is locked
64929  *  0b01..The lower DWP bit is locked
64930  *  0b10..The higher DWP bit is locked
64931  *  0b11..Both DWP bits are locked
64932  */
64933 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)
64934 /*! @} */
64935 
64936 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register */
64937 /*! @{ */
64938 
64939 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)
64940 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)
64941 /*! SRE - Slew Rate Field
64942  *  0b0..Slow Slew Rate
64943  *  0b1..Fast Slew Rate
64944  */
64945 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)
64946 
64947 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)
64948 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)
64949 /*! DSE - Drive Strength Field
64950  *  0b0..normal driver
64951  *  0b1..high driver
64952  */
64953 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)
64954 
64955 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)
64956 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)
64957 /*! PUE - Pull / Keep Select Field
64958  *  0b0..Pull Disable
64959  *  0b1..Pull Enable
64960  */
64961 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)
64962 
64963 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)
64964 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)
64965 /*! PUS - Pull Up / Down Config. Field
64966  *  0b0..Weak pull down
64967  *  0b1..Weak pull up
64968  */
64969 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)
64970 
64971 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)
64972 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)
64973 /*! ODE_SNVS - Open Drain SNVS Field
64974  *  0b0..Disabled
64975  *  0b1..Enabled
64976  */
64977 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)
64978 
64979 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)
64980 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)
64981 /*! DWP - Domain write protection
64982  *  0b00..Both cores are allowed
64983  *  0b01..CM7 is forbidden
64984  *  0b10..CM4 is forbidden
64985  *  0b11..Both cores are forbidden
64986  */
64987 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)
64988 
64989 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)
64990 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)
64991 /*! DWP_LOCK - Domain write protection lock
64992  *  0b00..Neither of DWP bits is locked
64993  *  0b01..The lower DWP bit is locked
64994  *  0b10..The higher DWP bit is locked
64995  *  0b11..Both DWP bits are locked
64996  */
64997 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)
64998 /*! @} */
64999 
65000 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register */
65001 /*! @{ */
65002 
65003 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)
65004 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)
65005 /*! SRE - Slew Rate Field
65006  *  0b0..Slow Slew Rate
65007  *  0b1..Fast Slew Rate
65008  */
65009 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)
65010 
65011 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)
65012 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)
65013 /*! DSE - Drive Strength Field
65014  *  0b0..normal driver
65015  *  0b1..high driver
65016  */
65017 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)
65018 
65019 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)
65020 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)
65021 /*! PUE - Pull / Keep Select Field
65022  *  0b0..Pull Disable
65023  *  0b1..Pull Enable
65024  */
65025 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)
65026 
65027 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)
65028 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)
65029 /*! PUS - Pull Up / Down Config. Field
65030  *  0b0..Weak pull down
65031  *  0b1..Weak pull up
65032  */
65033 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)
65034 
65035 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)
65036 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)
65037 /*! ODE_SNVS - Open Drain SNVS Field
65038  *  0b0..Disabled
65039  *  0b1..Enabled
65040  */
65041 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)
65042 
65043 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)
65044 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)
65045 /*! DWP - Domain write protection
65046  *  0b00..Both cores are allowed
65047  *  0b01..CM7 is forbidden
65048  *  0b10..CM4 is forbidden
65049  *  0b11..Both cores are forbidden
65050  */
65051 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)
65052 
65053 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)
65054 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)
65055 /*! DWP_LOCK - Domain write protection lock
65056  *  0b00..Neither of DWP bits is locked
65057  *  0b01..The lower DWP bit is locked
65058  *  0b10..The higher DWP bit is locked
65059  *  0b11..Both DWP bits are locked
65060  */
65061 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)
65062 /*! @} */
65063 
65064 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register */
65065 /*! @{ */
65066 
65067 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)
65068 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)
65069 /*! SRE - Slew Rate Field
65070  *  0b0..Slow Slew Rate
65071  *  0b1..Fast Slew Rate
65072  */
65073 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)
65074 
65075 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)
65076 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)
65077 /*! DSE - Drive Strength Field
65078  *  0b0..normal driver
65079  *  0b1..high driver
65080  */
65081 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)
65082 
65083 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)
65084 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)
65085 /*! PUE - Pull / Keep Select Field
65086  *  0b0..Pull Disable
65087  *  0b1..Pull Enable
65088  */
65089 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)
65090 
65091 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)
65092 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)
65093 /*! PUS - Pull Up / Down Config. Field
65094  *  0b0..Weak pull down
65095  *  0b1..Weak pull up
65096  */
65097 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)
65098 
65099 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)
65100 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)
65101 /*! ODE_SNVS - Open Drain SNVS Field
65102  *  0b0..Disabled
65103  *  0b1..Enabled
65104  */
65105 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)
65106 
65107 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)
65108 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)
65109 /*! DWP - Domain write protection
65110  *  0b00..Both cores are allowed
65111  *  0b01..CM7 is forbidden
65112  *  0b10..CM4 is forbidden
65113  *  0b11..Both cores are forbidden
65114  */
65115 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)
65116 
65117 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)
65118 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)
65119 /*! DWP_LOCK - Domain write protection lock
65120  *  0b00..Neither of DWP bits is locked
65121  *  0b01..The lower DWP bit is locked
65122  *  0b10..The higher DWP bit is locked
65123  *  0b11..Both DWP bits are locked
65124  */
65125 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)
65126 /*! @} */
65127 
65128 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register */
65129 /*! @{ */
65130 
65131 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)
65132 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)
65133 /*! SRE - Slew Rate Field
65134  *  0b0..Slow Slew Rate
65135  *  0b1..Fast Slew Rate
65136  */
65137 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)
65138 
65139 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)
65140 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)
65141 /*! DSE - Drive Strength Field
65142  *  0b0..normal driver
65143  *  0b1..high driver
65144  */
65145 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)
65146 
65147 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)
65148 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)
65149 /*! PUE - Pull / Keep Select Field
65150  *  0b0..Pull Disable
65151  *  0b1..Pull Enable
65152  */
65153 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)
65154 
65155 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)
65156 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)
65157 /*! PUS - Pull Up / Down Config. Field
65158  *  0b0..Weak pull down
65159  *  0b1..Weak pull up
65160  */
65161 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)
65162 
65163 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)
65164 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)
65165 /*! ODE_SNVS - Open Drain SNVS Field
65166  *  0b0..Disabled
65167  *  0b1..Enabled
65168  */
65169 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)
65170 
65171 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)
65172 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)
65173 /*! DWP - Domain write protection
65174  *  0b00..Both cores are allowed
65175  *  0b01..CM7 is forbidden
65176  *  0b10..CM4 is forbidden
65177  *  0b11..Both cores are forbidden
65178  */
65179 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)
65180 
65181 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)
65182 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)
65183 /*! DWP_LOCK - Domain write protection lock
65184  *  0b00..Neither of DWP bits is locked
65185  *  0b01..The lower DWP bit is locked
65186  *  0b10..The higher DWP bit is locked
65187  *  0b11..Both DWP bits are locked
65188  */
65189 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)
65190 /*! @} */
65191 
65192 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register */
65193 /*! @{ */
65194 
65195 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)
65196 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)
65197 /*! SRE - Slew Rate Field
65198  *  0b0..Slow Slew Rate
65199  *  0b1..Fast Slew Rate
65200  */
65201 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)
65202 
65203 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)
65204 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)
65205 /*! DSE - Drive Strength Field
65206  *  0b0..normal driver
65207  *  0b1..high driver
65208  */
65209 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)
65210 
65211 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)
65212 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)
65213 /*! PUE - Pull / Keep Select Field
65214  *  0b0..Pull Disable
65215  *  0b1..Pull Enable
65216  */
65217 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)
65218 
65219 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)
65220 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)
65221 /*! PUS - Pull Up / Down Config. Field
65222  *  0b0..Weak pull down
65223  *  0b1..Weak pull up
65224  */
65225 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)
65226 
65227 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)
65228 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)
65229 /*! ODE_SNVS - Open Drain SNVS Field
65230  *  0b0..Disabled
65231  *  0b1..Enabled
65232  */
65233 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)
65234 
65235 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)
65236 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)
65237 /*! DWP - Domain write protection
65238  *  0b00..Both cores are allowed
65239  *  0b01..CM7 is forbidden
65240  *  0b10..CM4 is forbidden
65241  *  0b11..Both cores are forbidden
65242  */
65243 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)
65244 
65245 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)
65246 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)
65247 /*! DWP_LOCK - Domain write protection lock
65248  *  0b00..Neither of DWP bits is locked
65249  *  0b01..The lower DWP bit is locked
65250  *  0b10..The higher DWP bit is locked
65251  *  0b11..Both DWP bits are locked
65252  */
65253 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)
65254 /*! @} */
65255 
65256 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register */
65257 /*! @{ */
65258 
65259 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)
65260 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)
65261 /*! SRE - Slew Rate Field
65262  *  0b0..Slow Slew Rate
65263  *  0b1..Fast Slew Rate
65264  */
65265 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)
65266 
65267 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)
65268 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)
65269 /*! DSE - Drive Strength Field
65270  *  0b0..normal driver
65271  *  0b1..high driver
65272  */
65273 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)
65274 
65275 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)
65276 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)
65277 /*! PUE - Pull / Keep Select Field
65278  *  0b0..Pull Disable
65279  *  0b1..Pull Enable
65280  */
65281 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)
65282 
65283 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)
65284 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)
65285 /*! PUS - Pull Up / Down Config. Field
65286  *  0b0..Weak pull down
65287  *  0b1..Weak pull up
65288  */
65289 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)
65290 
65291 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)
65292 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)
65293 /*! ODE_SNVS - Open Drain SNVS Field
65294  *  0b0..Disabled
65295  *  0b1..Enabled
65296  */
65297 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)
65298 
65299 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)
65300 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)
65301 /*! DWP - Domain write protection
65302  *  0b00..Both cores are allowed
65303  *  0b01..CM7 is forbidden
65304  *  0b10..CM4 is forbidden
65305  *  0b11..Both cores are forbidden
65306  */
65307 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)
65308 
65309 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)
65310 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)
65311 /*! DWP_LOCK - Domain write protection lock
65312  *  0b00..Neither of DWP bits is locked
65313  *  0b01..The lower DWP bit is locked
65314  *  0b10..The higher DWP bit is locked
65315  *  0b11..Both DWP bits are locked
65316  */
65317 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)
65318 /*! @} */
65319 
65320 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register */
65321 /*! @{ */
65322 
65323 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)
65324 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)
65325 /*! SRE - Slew Rate Field
65326  *  0b0..Slow Slew Rate
65327  *  0b1..Fast Slew Rate
65328  */
65329 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)
65330 
65331 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)
65332 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)
65333 /*! DSE - Drive Strength Field
65334  *  0b0..normal driver
65335  *  0b1..high driver
65336  */
65337 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)
65338 
65339 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)
65340 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)
65341 /*! PUE - Pull / Keep Select Field
65342  *  0b0..Pull Disable
65343  *  0b1..Pull Enable
65344  */
65345 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)
65346 
65347 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)
65348 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)
65349 /*! PUS - Pull Up / Down Config. Field
65350  *  0b0..Weak pull down
65351  *  0b1..Weak pull up
65352  */
65353 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)
65354 
65355 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)
65356 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)
65357 /*! ODE_SNVS - Open Drain SNVS Field
65358  *  0b0..Disabled
65359  *  0b1..Enabled
65360  */
65361 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)
65362 
65363 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)
65364 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)
65365 /*! DWP - Domain write protection
65366  *  0b00..Both cores are allowed
65367  *  0b01..CM7 is forbidden
65368  *  0b10..CM4 is forbidden
65369  *  0b11..Both cores are forbidden
65370  */
65371 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)
65372 
65373 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)
65374 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)
65375 /*! DWP_LOCK - Domain write protection lock
65376  *  0b00..Neither of DWP bits is locked
65377  *  0b01..The lower DWP bit is locked
65378  *  0b10..The higher DWP bit is locked
65379  *  0b11..Both DWP bits are locked
65380  */
65381 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)
65382 /*! @} */
65383 
65384 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register */
65385 /*! @{ */
65386 
65387 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)
65388 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)
65389 /*! SRE - Slew Rate Field
65390  *  0b0..Slow Slew Rate
65391  *  0b1..Fast Slew Rate
65392  */
65393 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)
65394 
65395 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)
65396 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)
65397 /*! DSE - Drive Strength Field
65398  *  0b0..normal driver
65399  *  0b1..high driver
65400  */
65401 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)
65402 
65403 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)
65404 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)
65405 /*! PUE - Pull / Keep Select Field
65406  *  0b0..Pull Disable
65407  *  0b1..Pull Enable
65408  */
65409 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)
65410 
65411 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)
65412 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)
65413 /*! PUS - Pull Up / Down Config. Field
65414  *  0b0..Weak pull down
65415  *  0b1..Weak pull up
65416  */
65417 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)
65418 
65419 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)
65420 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)
65421 /*! ODE_SNVS - Open Drain SNVS Field
65422  *  0b0..Disabled
65423  *  0b1..Enabled
65424  */
65425 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)
65426 
65427 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)
65428 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)
65429 /*! DWP - Domain write protection
65430  *  0b00..Both cores are allowed
65431  *  0b01..CM7 is forbidden
65432  *  0b10..CM4 is forbidden
65433  *  0b11..Both cores are forbidden
65434  */
65435 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)
65436 
65437 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)
65438 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)
65439 /*! DWP_LOCK - Domain write protection lock
65440  *  0b00..Neither of DWP bits is locked
65441  *  0b01..The lower DWP bit is locked
65442  *  0b10..The higher DWP bit is locked
65443  *  0b11..Both DWP bits are locked
65444  */
65445 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)
65446 /*! @} */
65447 
65448 
65449 /*!
65450  * @}
65451  */ /* end of group IOMUXC_SNVS_Register_Masks */
65452 
65453 
65454 /* IOMUXC_SNVS - Peripheral instance base addresses */
65455 /** Peripheral IOMUXC_SNVS base address */
65456 #define IOMUXC_SNVS_BASE                         (0x40C94000u)
65457 /** Peripheral IOMUXC_SNVS base pointer */
65458 #define IOMUXC_SNVS                              ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
65459 /** Array initializer of IOMUXC_SNVS peripheral base addresses */
65460 #define IOMUXC_SNVS_BASE_ADDRS                   { IOMUXC_SNVS_BASE }
65461 /** Array initializer of IOMUXC_SNVS peripheral base pointers */
65462 #define IOMUXC_SNVS_BASE_PTRS                    { IOMUXC_SNVS }
65463 
65464 /*!
65465  * @}
65466  */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
65467 
65468 
65469 /* ----------------------------------------------------------------------------
65470    -- IOMUXC_SNVS_GPR Peripheral Access Layer
65471    ---------------------------------------------------------------------------- */
65472 
65473 /*!
65474  * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
65475  * @{
65476  */
65477 
65478 /** IOMUXC_SNVS_GPR - Register Layout Typedef */
65479 typedef struct {
65480   __IO uint32_t GPR[32];                           /**< GPR0 General Purpose Register, array offset: 0x0, array step: 0x4 */
65481   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
65482   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
65483   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
65484   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
65485   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
65486   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
65487 } IOMUXC_SNVS_GPR_Type;
65488 
65489 /* ----------------------------------------------------------------------------
65490    -- IOMUXC_SNVS_GPR Register Masks
65491    ---------------------------------------------------------------------------- */
65492 
65493 /*!
65494  * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
65495  * @{
65496  */
65497 
65498 /*! @name GPR - GPR0 General Purpose Register */
65499 /*! @{ */
65500 
65501 #define IOMUXC_SNVS_GPR_GPR_GPR_MASK             (0xFFFFFFFFU)
65502 #define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT            (0U)
65503 /*! GPR - General purpose bits
65504  */
65505 #define IOMUXC_SNVS_GPR_GPR_GPR(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK)
65506 /*! @} */
65507 
65508 /* The count of IOMUXC_SNVS_GPR_GPR */
65509 #define IOMUXC_SNVS_GPR_GPR_COUNT                (32U)
65510 
65511 /*! @name GPR32 - GPR32 General Purpose Register */
65512 /*! @{ */
65513 
65514 #define IOMUXC_SNVS_GPR_GPR32_GPR_MASK           (0xFFFEU)
65515 #define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT          (1U)
65516 /*! GPR - General purpose bits
65517  */
65518 #define IOMUXC_SNVS_GPR_GPR32_GPR(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
65519 
65520 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK          (0xFFFF0000U)
65521 #define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT         (16U)
65522 /*! LOCK - Lock the write to bit 15:0
65523  */
65524 #define IOMUXC_SNVS_GPR_GPR32_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
65525 /*! @} */
65526 
65527 /*! @name GPR33 - GPR33 General Purpose Register */
65528 /*! @{ */
65529 
65530 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
65531 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
65532 /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
65533  *  0b0..No change
65534  *  0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
65535  */
65536 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
65537 
65538 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U)
65539 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U)
65540 /*! SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable
65541  *  0b1..Enable bypass
65542  *  0b0..Disable bypass
65543  */
65544 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
65545 
65546 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U)
65547 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U)
65548 /*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect
65549  *  0b1..Voltage on DCDC_IN is lower than 2.6V
65550  *  0b0..Voltage on DCDC_IN is higher than 2.6V
65551  */
65552 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
65553 
65554 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U)
65555 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U)
65556 /*! DCDC_OVER_CUR - DCDC output over current alert
65557  *  0b1..Overcurrent on DCDC output
65558  *  0b0..No Overcurrent on DCDC output
65559  */
65560 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
65561 
65562 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U)
65563 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U)
65564 /*! DCDC_OVER_VOL - DCDC output over voltage alert
65565  *  0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output
65566  *  0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
65567  */
65568 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
65569 
65570 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U)
65571 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U)
65572 /*! DCDC_STS_DC_OK - DCDC status OK
65573  *  0b0..DCDC is settling
65574  *  0b1..DCDC already settled
65575  */
65576 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
65577 
65578 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U)
65579 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U)
65580 /*! SNVS_XTAL_CLK_OK - 32K OSC ok flag
65581  *  0b1..32K oscillator is stable into normal operation
65582  *  0b0..32K oscillator is NOT stable into normal operation
65583  */
65584 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
65585 /*! @} */
65586 
65587 /*! @name GPR34 - GPR34 General Purpose Register */
65588 /*! @{ */
65589 
65590 #define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK          (0x1U)
65591 #define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT         (0U)
65592 /*! LOCK - Lock the write to bit 31:1
65593  *  0b0..Write access is not blocked
65594  *  0b1..Write access is blocked
65595  */
65596 #define IOMUXC_SNVS_GPR_GPR34_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
65597 
65598 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
65599 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
65600 /*! SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select
65601  *  0b0..The trimming codes are selected from eFuse
65602  *  0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
65603  */
65604 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
65605 
65606 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU)
65607 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U)
65608 /*! SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim
65609  */
65610 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
65611 
65612 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U)
65613 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U)
65614 /*! SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select
65615  *  0b0..The trimming codes are selected from eFuse
65616  *  0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
65617  */
65618 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
65619 
65620 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U)
65621 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U)
65622 /*! SNVS_CLK_DET_TRIM - SNVS clock detect trim bits
65623  */
65624 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
65625 
65626 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U)
65627 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U)
65628 /*! SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency
65629  *  0b00..No change (Default)
65630  *  0b01..Add +5 to the Trim
65631  *  0b10..Add +10 to the trim
65632  *  0b11..Add -5 to the Trim
65633  */
65634 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
65635 
65636 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U)
65637 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U)
65638 /*! SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency
65639  *  0b00..No change (Default)
65640  *  0b01..Add +5 to the Trim
65641  *  0b10..Add +10 to the trim
65642  *  0b11..Add -5 to the Trim
65643  */
65644 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
65645 
65646 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U)
65647 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U)
65648 /*! SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select
65649  *  0b0..The trimming codes are selected from eFuse
65650  *  0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
65651  */
65652 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
65653 
65654 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U)
65655 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U)
65656 /*! SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim
65657  */
65658 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
65659 /*! @} */
65660 
65661 /*! @name GPR35 - GPR35 General Purpose Register */
65662 /*! @{ */
65663 
65664 #define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK          (0x1U)
65665 #define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT         (0U)
65666 /*! LOCK - Lock the write to bit 31:1
65667  *  0b0..Write access is not blocked
65668  *  0b1..Write access is blocked
65669  */
65670 #define IOMUXC_SNVS_GPR_GPR35_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
65671 
65672 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U)
65673 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U)
65674 /*! SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select
65675  *  0b0..The trimming codes are selected from eFuse
65676  *  0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
65677  */
65678 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
65679 
65680 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U)
65681 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U)
65682 /*! SNVS_VOLT_DET_TRIM - SNVS voltage detect trim
65683  */
65684 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
65685 
65686 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U)
65687 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U)
65688 /*! SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select
65689  *  0b0..The trimming codes are selected from eFuse
65690  *  0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
65691  */
65692 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
65693 
65694 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U)
65695 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U)
65696 /*! SNVS_TEMP_DET_TRIM - SNVS temperature detect trim
65697  */
65698 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
65699 
65700 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U)
65701 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U)
65702 /*! SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary
65703  *  0b00..No change (Default)
65704  *  0b01..Add +5 to the Trim
65705  *  0b10..Add +10 to the trim
65706  *  0b11..Add -5 to the Trim
65707  */
65708 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
65709 
65710 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U)
65711 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U)
65712 /*! SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary
65713  *  0b00..No change (Default)
65714  *  0b01..Add +5 to the Trim
65715  *  0b10..Add +10 to the trim
65716  *  0b11..Add -5 to the Trim
65717  */
65718 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
65719 /*! @} */
65720 
65721 /*! @name GPR36 - GPR36 General Purpose Register */
65722 /*! @{ */
65723 
65724 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U)
65725 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U)
65726 /*! SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit
65727  *  0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off
65728  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
65729  */
65730 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
65731 
65732 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U)
65733 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U)
65734 /*! SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit
65735  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled)
65736  *  0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit
65737  *       ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so
65738  *       this bit is default high.
65739  */
65740 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
65741 
65742 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U)
65743 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U)
65744 /*! SNVS_SRAM_STDBY - SNVS SRAM standby enable bit
65745  *  0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF
65746  *  0b0..SNVS SRAM does not enter low leakage state
65747  */
65748 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
65749 
65750 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U)
65751 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U)
65752 /*! SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral
65753  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
65754  *  0b0..Switch on SNVS SRAM power for peripheral
65755  */
65756 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
65757 
65758 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U)
65759 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U)
65760 /*! SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit
65761  *  0b1..Switch off SNVS SRAM power for peripheral and array
65762  *  0b0..Switch on SNVS SRAM power for peripheral and array
65763  */
65764 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
65765 
65766 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U)
65767 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U)
65768 /*! SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral
65769  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
65770  *  0b0..Switch on SNVS SRAM power for peripheral
65771  */
65772 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
65773 
65774 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U)
65775 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U)
65776 /*! SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit
65777  *  0b1..Switch off SNVS SRAM power for peripheral and array
65778  *  0b0..Switch on SNVS SRAM power for peripheral and array
65779  */
65780 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
65781 /*! @} */
65782 
65783 /*! @name GPR37 - GPR37 General Purpose Register */
65784 /*! @{ */
65785 
65786 #define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK          (0x1U)
65787 #define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT         (0U)
65788 /*! LOCK - Lock the write to bit 31:1
65789  *  0b0..Write access is not blocked
65790  *  0b1..Write access is blocked
65791  */
65792 #define IOMUXC_SNVS_GPR_GPR37_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
65793 
65794 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU)
65795 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U)
65796 /*! SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit
65797  */
65798 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
65799 
65800 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U)
65801 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U)
65802 /*! SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit
65803  */
65804 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
65805 /*! @} */
65806 
65807 
65808 /*!
65809  * @}
65810  */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
65811 
65812 
65813 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
65814 /** Peripheral IOMUXC_SNVS_GPR base address */
65815 #define IOMUXC_SNVS_GPR_BASE                     (0x40C98000u)
65816 /** Peripheral IOMUXC_SNVS_GPR base pointer */
65817 #define IOMUXC_SNVS_GPR                          ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
65818 /** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
65819 #define IOMUXC_SNVS_GPR_BASE_ADDRS               { IOMUXC_SNVS_GPR_BASE }
65820 /** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
65821 #define IOMUXC_SNVS_GPR_BASE_PTRS                { IOMUXC_SNVS_GPR }
65822 
65823 /*!
65824  * @}
65825  */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
65826 
65827 
65828 /* ----------------------------------------------------------------------------
65829    -- IPS_DOMAIN Peripheral Access Layer
65830    ---------------------------------------------------------------------------- */
65831 
65832 /*!
65833  * @addtogroup IPS_DOMAIN_Peripheral_Access_Layer IPS_DOMAIN Peripheral Access Layer
65834  * @{
65835  */
65836 
65837 /** IPS_DOMAIN - Register Layout Typedef */
65838 typedef struct {
65839   struct {                                         /* offset: 0x0, array step: 0x10 */
65840     __IO uint32_t SLOT_CTRL;                         /**< Slot Control Register, array offset: 0x0, array step: 0x10 */
65841          uint8_t RESERVED_0[12];
65842   } SLOT_CTRL[38];
65843 } IPS_DOMAIN_Type;
65844 
65845 /* ----------------------------------------------------------------------------
65846    -- IPS_DOMAIN Register Masks
65847    ---------------------------------------------------------------------------- */
65848 
65849 /*!
65850  * @addtogroup IPS_DOMAIN_Register_Masks IPS_DOMAIN Register Masks
65851  * @{
65852  */
65853 
65854 /*! @name SLOT_CTRL - Slot Control Register */
65855 /*! @{ */
65856 
65857 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU)
65858 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U)
65859 /*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked
65860  */
65861 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
65862 
65863 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK    (0x8000U)
65864 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT   (15U)
65865 /*! DOMAIN_LOCK - Lock domain ID of this slot
65866  *  0b0..Do not lock the domain ID
65867  *  0b1..Lock the domain ID
65868  */
65869 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK)
65870 
65871 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U)
65872 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U)
65873 /*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register
65874  *  0b0..Do not allow non-secure write access
65875  *  0b1..Allow non-secure write access
65876  */
65877 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x)  (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK)
65878 
65879 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK     (0x20000U)
65880 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT    (17U)
65881 /*! ALLOW_USER - Allow user write access to this domain control register or domain register
65882  *  0b0..Do not allow user write access
65883  *  0b1..Allow user write access
65884  */
65885 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x)       (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK)
65886 
65887 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
65888 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT  (31U)
65889 /*! LOCK_CONTROL - Lock control of this slot
65890  *  0b0..Do not lock the control register of this slot
65891  *  0b1..Lock the control register of this slot
65892  */
65893 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x)     (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK)
65894 /*! @} */
65895 
65896 /* The count of IPS_DOMAIN_SLOT_CTRL */
65897 #define IPS_DOMAIN_SLOT_CTRL_COUNT               (38U)
65898 
65899 
65900 /*!
65901  * @}
65902  */ /* end of group IPS_DOMAIN_Register_Masks */
65903 
65904 
65905 /* IPS_DOMAIN - Peripheral instance base addresses */
65906 /** Peripheral IPS_DOMAIN base address */
65907 #define IPS_DOMAIN_BASE                          (0x40C87C00u)
65908 /** Peripheral IPS_DOMAIN base pointer */
65909 #define IPS_DOMAIN                               ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
65910 /** Array initializer of IPS_DOMAIN peripheral base addresses */
65911 #define IPS_DOMAIN_BASE_ADDRS                    { IPS_DOMAIN_BASE }
65912 /** Array initializer of IPS_DOMAIN peripheral base pointers */
65913 #define IPS_DOMAIN_BASE_PTRS                     { IPS_DOMAIN }
65914 
65915 /*!
65916  * @}
65917  */ /* end of group IPS_DOMAIN_Peripheral_Access_Layer */
65918 
65919 
65920 /* ----------------------------------------------------------------------------
65921    -- KEY_MANAGER Peripheral Access Layer
65922    ---------------------------------------------------------------------------- */
65923 
65924 /*!
65925  * @addtogroup KEY_MANAGER_Peripheral_Access_Layer KEY_MANAGER Peripheral Access Layer
65926  * @{
65927  */
65928 
65929 /** KEY_MANAGER - Register Layout Typedef */
65930 typedef struct {
65931   __IO uint32_t MASTER_KEY_CTRL;                   /**< CSR Master Key Control Register, offset: 0x0 */
65932        uint8_t RESERVED_0[12];
65933   __IO uint32_t OTFAD1_KEY_CTRL;                   /**< CSR OTFAD-1 Key Control, offset: 0x10 */
65934        uint8_t RESERVED_1[4];
65935   __IO uint32_t OTFAD2_KEY_CTRL;                   /**< CSR OTFAD-2 Key Control, offset: 0x18 */
65936        uint8_t RESERVED_2[4];
65937   __IO uint32_t IEE_KEY_CTRL;                      /**< CSR IEE Key Control, offset: 0x20 */
65938        uint8_t RESERVED_3[12];
65939   __IO uint32_t PUF_KEY_CTRL;                      /**< CSR PUF Key Control, offset: 0x30 */
65940        uint8_t RESERVED_4[972];
65941   __IO uint32_t SLOT0_CTRL;                        /**< Slot 0 Control, offset: 0x400 */
65942   __IO uint32_t SLOT1_CTRL;                        /**< Slot1 Control, offset: 0x404 */
65943   __IO uint32_t SLOT2_CTRL;                        /**< Slot2 Control, offset: 0x408 */
65944   __IO uint32_t SLOT3_CTRL;                        /**< Slot3 Control, offset: 0x40C */
65945   __IO uint32_t SLOT4_CTRL;                        /**< Slot 4 Control, offset: 0x410 */
65946 } KEY_MANAGER_Type;
65947 
65948 /* ----------------------------------------------------------------------------
65949    -- KEY_MANAGER Register Masks
65950    ---------------------------------------------------------------------------- */
65951 
65952 /*!
65953  * @addtogroup KEY_MANAGER_Register_Masks KEY_MANAGER Register Masks
65954  * @{
65955  */
65956 
65957 /*! @name MASTER_KEY_CTRL - CSR Master Key Control Register */
65958 /*! @{ */
65959 
65960 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK  (0x1U)
65961 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U)
65962 /*! SELECT - Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL.
65963  *  0b0..select key from UDF
65964  *  0b1..If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS)
65965  */
65966 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK)
65967 
65968 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK    (0x10000U)
65969 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT   (16U)
65970 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK.
65971  *  0b0..not locked
65972  *  0b1..locked
65973  */
65974 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK)
65975 /*! @} */
65976 
65977 /*! @name OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */
65978 /*! @{ */
65979 
65980 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK  (0x1U)
65981 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U)
65982 /*! SELECT - key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL.
65983  *  0b0..Select key from OCOTP USER_KEY5
65984  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
65985  */
65986 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK)
65987 
65988 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK    (0x10000U)
65989 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT   (16U)
65990 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK.
65991  *  0b0..not locked
65992  *  0b1..locked
65993  */
65994 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK)
65995 /*! @} */
65996 
65997 /*! @name OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */
65998 /*! @{ */
65999 
66000 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK  (0x1U)
66001 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U)
66002 /*! SELECT - key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL.
66003  *  0b0..select key from OCOTP USER_KEY5
66004  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
66005  */
66006 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK)
66007 
66008 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK    (0x10000U)
66009 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT   (16U)
66010 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK.
66011  *  0b0..not locked
66012  *  0b1..locked
66013  */
66014 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK)
66015 /*! @} */
66016 
66017 /*! @name IEE_KEY_CTRL - CSR IEE Key Control */
66018 /*! @{ */
66019 
66020 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK     (0x1U)
66021 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT    (0U)
66022 /*! RELOAD - Restart load key signal for IEE
66023  *  0b0..Do nothing
66024  *  0b1..Restart IEE key load flow
66025  */
66026 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK)
66027 /*! @} */
66028 
66029 /*! @name PUF_KEY_CTRL - CSR PUF Key Control */
66030 /*! @{ */
66031 
66032 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK       (0x1U)
66033 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT      (0U)
66034 /*! LOCK - Lock signal for key select
66035  *  0b0..Do not lock the key select
66036  *  0b1..Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has
66037  *       been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done.
66038  */
66039 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK)
66040 /*! @} */
66041 
66042 /*! @name SLOT0_CTRL - Slot 0 Control */
66043 /*! @{ */
66044 
66045 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK   (0xFU)
66046 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT  (0U)
66047 /*! WHITE_LIST - Whitelist
66048  */
66049 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK)
66050 
66051 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK    (0x8000U)
66052 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT   (15U)
66053 /*! LOCK_LIST - Lock whitelist
66054  *  0b0..Whitelist is not locked
66055  *  0b1..Whitelist is locked
66056  */
66057 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK)
66058 
66059 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK        (0x10000U)
66060 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT       (16U)
66061 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66062  *  0b0..Do not allow non-secure write access
66063  *  0b1..Allow non-secure write access
66064  */
66065 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK)
66066 
66067 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK      (0x20000U)
66068 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT     (17U)
66069 /*! TZ_USER - Allow user write access to this register and the slot it controls
66070  *  0b0..Do not allow user write access
66071  *  0b1..Allow user write access
66072  */
66073 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK)
66074 
66075 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66076 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U)
66077 /*! LOCK_CONTROL - Lock control of this slot
66078  *  0b0..Do not lock the control register of this slot
66079  *  0b1..Lock the control register of this slot
66080  */
66081 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK)
66082 /*! @} */
66083 
66084 /*! @name SLOT1_CTRL - Slot1 Control */
66085 /*! @{ */
66086 
66087 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK   (0xFU)
66088 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT  (0U)
66089 /*! WHITE_LIST - Whitelist
66090  */
66091 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK)
66092 
66093 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK    (0x8000U)
66094 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT   (15U)
66095 /*! LOCK_LIST - Lock whitelist
66096  *  0b0..Whitelist is not locked
66097  *  0b1..Whitelist is locked
66098  */
66099 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK)
66100 
66101 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK        (0x10000U)
66102 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT       (16U)
66103 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66104  *  0b0..Do not allow non-secure write access
66105  *  0b1..Allow non-secure write access
66106  */
66107 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK)
66108 
66109 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK      (0x20000U)
66110 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT     (17U)
66111 /*! TZ_USER - Allow user write access to this register and the slot it controls
66112  *  0b0..Do not allow user write access
66113  *  0b1..Allow user write access
66114  */
66115 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK)
66116 
66117 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66118 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U)
66119 /*! LOCK_CONTROL - Lock control of this slot
66120  *  0b0..Do not lock the control register of this slot
66121  *  0b1..Lock the control register of this slot
66122  */
66123 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK)
66124 /*! @} */
66125 
66126 /*! @name SLOT2_CTRL - Slot2 Control */
66127 /*! @{ */
66128 
66129 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK   (0xFU)
66130 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT  (0U)
66131 /*! WHITE_LIST - Whitelist
66132  */
66133 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK)
66134 
66135 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK    (0x8000U)
66136 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT   (15U)
66137 /*! LOCK_LIST - Lock whitelist
66138  *  0b0..Whitelist is not locked
66139  *  0b1..Whitelist is locked
66140  */
66141 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK)
66142 
66143 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK        (0x10000U)
66144 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT       (16U)
66145 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66146  *  0b0..Do not allow non-secure write access
66147  *  0b1..Allow non-secure write access
66148  */
66149 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK)
66150 
66151 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK      (0x20000U)
66152 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT     (17U)
66153 /*! TZ_USER - Allow user write access to this register and the slot it controls
66154  *  0b0..Do not allow user write access
66155  *  0b1..Allow user write access
66156  */
66157 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK)
66158 
66159 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66160 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U)
66161 /*! LOCK_CONTROL - Lock control of this slot
66162  *  0b0..Do not lock the control register of this slot
66163  *  0b1..Lock the control register of this slot
66164  */
66165 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK)
66166 /*! @} */
66167 
66168 /*! @name SLOT3_CTRL - Slot3 Control */
66169 /*! @{ */
66170 
66171 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK   (0xFU)
66172 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT  (0U)
66173 /*! WHITE_LIST - Whitelist
66174  */
66175 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK)
66176 
66177 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK    (0x8000U)
66178 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT   (15U)
66179 /*! LOCK_LIST - Lock whitelist
66180  *  0b0..Whitelist is not locked
66181  *  0b1..Whitelist is locked
66182  */
66183 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK)
66184 
66185 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK        (0x10000U)
66186 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT       (16U)
66187 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66188  *  0b0..Do not allow non-secure write access
66189  *  0b1..Allow non-secure write access
66190  */
66191 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK)
66192 
66193 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK      (0x20000U)
66194 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT     (17U)
66195 /*! TZ_USER - Allow user write access to this register and the slot it controls
66196  *  0b0..Do not allow user write access
66197  *  0b1..Allow user write access
66198  */
66199 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK)
66200 
66201 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66202 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U)
66203 /*! LOCK_CONTROL - Lock control of this slot
66204  *  0b0..Do not lock the control register of this slot
66205  *  0b1..Lock the control register of this slot
66206  */
66207 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK)
66208 /*! @} */
66209 
66210 /*! @name SLOT4_CTRL - Slot 4 Control */
66211 /*! @{ */
66212 
66213 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK   (0xFU)
66214 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT  (0U)
66215 /*! WHITE_LIST - Whitelist
66216  */
66217 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK)
66218 
66219 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK    (0x8000U)
66220 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT   (15U)
66221 /*! LOCK_LIST - Lock whitelist
66222  *  0b0..Whitelist is not locked
66223  *  0b1..Whitelist is locked
66224  */
66225 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK)
66226 
66227 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK        (0x10000U)
66228 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT       (16U)
66229 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66230  *  0b0..Do not allow non-secure write access
66231  *  0b1..Allow non-secure write access
66232  */
66233 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK)
66234 
66235 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK      (0x20000U)
66236 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT     (17U)
66237 /*! TZ_USER - Allow user write access to this register and the slot it controls
66238  *  0b0..Do not allow user write access
66239  *  0b1..Allow user write access
66240  */
66241 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK)
66242 
66243 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66244 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U)
66245 /*! LOCK_CONTROL - Lock control of this slot
66246  *  0b0..Do not lock the control register of this slot
66247  *  0b1..Lock the control register of this slot
66248  */
66249 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK)
66250 /*! @} */
66251 
66252 
66253 /*!
66254  * @}
66255  */ /* end of group KEY_MANAGER_Register_Masks */
66256 
66257 
66258 /* KEY_MANAGER - Peripheral instance base addresses */
66259 /** Peripheral KEY_MANAGER base address */
66260 #define KEY_MANAGER_BASE                         (0x40C80000u)
66261 /** Peripheral KEY_MANAGER base pointer */
66262 #define KEY_MANAGER                              ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
66263 /** Array initializer of KEY_MANAGER peripheral base addresses */
66264 #define KEY_MANAGER_BASE_ADDRS                   { KEY_MANAGER_BASE }
66265 /** Array initializer of KEY_MANAGER peripheral base pointers */
66266 #define KEY_MANAGER_BASE_PTRS                    { KEY_MANAGER }
66267 
66268 /*!
66269  * @}
66270  */ /* end of group KEY_MANAGER_Peripheral_Access_Layer */
66271 
66272 
66273 /* ----------------------------------------------------------------------------
66274    -- KPP Peripheral Access Layer
66275    ---------------------------------------------------------------------------- */
66276 
66277 /*!
66278  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
66279  * @{
66280  */
66281 
66282 /** KPP - Register Layout Typedef */
66283 typedef struct {
66284   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
66285   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
66286   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
66287   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
66288 } KPP_Type;
66289 
66290 /* ----------------------------------------------------------------------------
66291    -- KPP Register Masks
66292    ---------------------------------------------------------------------------- */
66293 
66294 /*!
66295  * @addtogroup KPP_Register_Masks KPP Register Masks
66296  * @{
66297  */
66298 
66299 /*! @name KPCR - Keypad Control Register */
66300 /*! @{ */
66301 
66302 #define KPP_KPCR_KRE_MASK                        (0xFFU)
66303 #define KPP_KPCR_KRE_SHIFT                       (0U)
66304 /*! KRE - KRE
66305  *  0b00000000..Row is not included in the keypad key press detect.
66306  *  0b00000001..Row is included in the keypad key press detect.
66307  */
66308 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
66309 
66310 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
66311 #define KPP_KPCR_KCO_SHIFT                       (8U)
66312 /*! KCO - KCO
66313  *  0b00000000..Column strobe output is totem pole drive.
66314  *  0b00000001..Column strobe output is open drain.
66315  */
66316 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
66317 /*! @} */
66318 
66319 /*! @name KPSR - Keypad Status Register */
66320 /*! @{ */
66321 
66322 #define KPP_KPSR_KPKD_MASK                       (0x1U)
66323 #define KPP_KPSR_KPKD_SHIFT                      (0U)
66324 /*! KPKD - KPKD
66325  *  0b0..No key presses detected
66326  *  0b1..A key has been depressed
66327  */
66328 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
66329 
66330 #define KPP_KPSR_KPKR_MASK                       (0x2U)
66331 #define KPP_KPSR_KPKR_SHIFT                      (1U)
66332 /*! KPKR - KPKR
66333  *  0b0..No key release detected
66334  *  0b1..All keys have been released
66335  */
66336 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
66337 
66338 #define KPP_KPSR_KDSC_MASK                       (0x4U)
66339 #define KPP_KPSR_KDSC_SHIFT                      (2U)
66340 /*! KDSC - KDSC
66341  *  0b0..No effect
66342  *  0b1..Set bits that clear the keypad depress synchronizer chain
66343  */
66344 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
66345 
66346 #define KPP_KPSR_KRSS_MASK                       (0x8U)
66347 #define KPP_KPSR_KRSS_SHIFT                      (3U)
66348 /*! KRSS - KRSS
66349  *  0b0..No effect
66350  *  0b1..Set bits which sets keypad release synchronizer chain
66351  */
66352 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
66353 
66354 #define KPP_KPSR_KDIE_MASK                       (0x100U)
66355 #define KPP_KPSR_KDIE_SHIFT                      (8U)
66356 /*! KDIE - KDIE
66357  *  0b0..No interrupt request is generated when KPKD is set.
66358  *  0b1..An interrupt request is generated when KPKD is set.
66359  */
66360 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
66361 
66362 #define KPP_KPSR_KRIE_MASK                       (0x200U)
66363 #define KPP_KPSR_KRIE_SHIFT                      (9U)
66364 /*! KRIE - KRIE
66365  *  0b0..No interrupt request is generated when KPKR is set.
66366  *  0b1..An interrupt request is generated when KPKR is set.
66367  */
66368 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
66369 /*! @} */
66370 
66371 /*! @name KDDR - Keypad Data Direction Register */
66372 /*! @{ */
66373 
66374 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
66375 #define KPP_KDDR_KRDD_SHIFT                      (0U)
66376 /*! KRDD - KRDD
66377  *  0b00000000..ROWn pin configured as an input.
66378  *  0b00000001..ROWn pin configured as an output.
66379  */
66380 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
66381 
66382 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
66383 #define KPP_KDDR_KCDD_SHIFT                      (8U)
66384 /*! KCDD - KCDD
66385  *  0b00000000..COLn pin is configured as an input.
66386  *  0b00000001..COLn pin is configured as an output.
66387  */
66388 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
66389 /*! @} */
66390 
66391 /*! @name KPDR - Keypad Data Register */
66392 /*! @{ */
66393 
66394 #define KPP_KPDR_KRD_MASK                        (0xFFU)
66395 #define KPP_KPDR_KRD_SHIFT                       (0U)
66396 /*! KRD - KRD
66397  */
66398 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
66399 
66400 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
66401 #define KPP_KPDR_KCD_SHIFT                       (8U)
66402 /*! KCD - KCD
66403  */
66404 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
66405 /*! @} */
66406 
66407 
66408 /*!
66409  * @}
66410  */ /* end of group KPP_Register_Masks */
66411 
66412 
66413 /* KPP - Peripheral instance base addresses */
66414 /** Peripheral KPP base address */
66415 #define KPP_BASE                                 (0x400E0000u)
66416 /** Peripheral KPP base pointer */
66417 #define KPP                                      ((KPP_Type *)KPP_BASE)
66418 /** Array initializer of KPP peripheral base addresses */
66419 #define KPP_BASE_ADDRS                           { KPP_BASE }
66420 /** Array initializer of KPP peripheral base pointers */
66421 #define KPP_BASE_PTRS                            { KPP }
66422 /** Interrupt vectors for the KPP peripheral type */
66423 #define KPP_IRQS                                 { KPP_IRQn }
66424 
66425 /*!
66426  * @}
66427  */ /* end of group KPP_Peripheral_Access_Layer */
66428 
66429 
66430 /* ----------------------------------------------------------------------------
66431    -- LCDIF Peripheral Access Layer
66432    ---------------------------------------------------------------------------- */
66433 
66434 /*!
66435  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
66436  * @{
66437  */
66438 
66439 /** LCDIF - Register Layout Typedef */
66440 typedef struct {
66441   __IO uint32_t CTRL;                              /**< LCDIF General Control Register, offset: 0x0 */
66442   __IO uint32_t CTRL_SET;                          /**< LCDIF General Control Register, offset: 0x4 */
66443   __IO uint32_t CTRL_CLR;                          /**< LCDIF General Control Register, offset: 0x8 */
66444   __IO uint32_t CTRL_TOG;                          /**< LCDIF General Control Register, offset: 0xC */
66445   __IO uint32_t CTRL1;                             /**< LCDIF General Control1 Register, offset: 0x10 */
66446   __IO uint32_t CTRL1_SET;                         /**< LCDIF General Control1 Register, offset: 0x14 */
66447   __IO uint32_t CTRL1_CLR;                         /**< LCDIF General Control1 Register, offset: 0x18 */
66448   __IO uint32_t CTRL1_TOG;                         /**< LCDIF General Control1 Register, offset: 0x1C */
66449   __IO uint32_t CTRL2;                             /**< LCDIF General Control2 Register, offset: 0x20 */
66450   __IO uint32_t CTRL2_SET;                         /**< LCDIF General Control2 Register, offset: 0x24 */
66451   __IO uint32_t CTRL2_CLR;                         /**< LCDIF General Control2 Register, offset: 0x28 */
66452   __IO uint32_t CTRL2_TOG;                         /**< LCDIF General Control2 Register, offset: 0x2C */
66453   __IO uint32_t TRANSFER_COUNT;                    /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
66454        uint8_t RESERVED_0[12];
66455   __IO uint32_t CUR_BUF;                           /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
66456        uint8_t RESERVED_1[12];
66457   __IO uint32_t NEXT_BUF;                          /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
66458        uint8_t RESERVED_2[28];
66459   __IO uint32_t VDCTRL0;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
66460   __IO uint32_t VDCTRL0_SET;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
66461   __IO uint32_t VDCTRL0_CLR;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
66462   __IO uint32_t VDCTRL0_TOG;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
66463   __IO uint32_t VDCTRL1;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
66464        uint8_t RESERVED_3[12];
66465   __IO uint32_t VDCTRL2;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
66466        uint8_t RESERVED_4[12];
66467   __IO uint32_t VDCTRL3;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
66468        uint8_t RESERVED_5[12];
66469   __IO uint32_t VDCTRL4;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
66470        uint8_t RESERVED_6[220];
66471   __IO uint32_t BM_ERROR_STAT;                     /**< Bus Master Error Status Register, offset: 0x190 */
66472        uint8_t RESERVED_7[12];
66473   __IO uint32_t CRC_STAT;                          /**< CRC Status Register, offset: 0x1A0 */
66474        uint8_t RESERVED_8[12];
66475   __I  uint32_t STAT;                              /**< LCD Interface Status Register, offset: 0x1B0 */
66476        uint8_t RESERVED_9[76];
66477   __IO uint32_t THRES;                             /**< LCDIF Threshold Register, offset: 0x200 */
66478        uint8_t RESERVED_10[380];
66479   __IO uint32_t PIGEONCTRL0;                       /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
66480   __IO uint32_t PIGEONCTRL0_SET;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
66481   __IO uint32_t PIGEONCTRL0_CLR;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
66482   __IO uint32_t PIGEONCTRL0_TOG;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
66483   __IO uint32_t PIGEONCTRL1;                       /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
66484   __IO uint32_t PIGEONCTRL1_SET;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
66485   __IO uint32_t PIGEONCTRL1_CLR;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
66486   __IO uint32_t PIGEONCTRL1_TOG;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
66487   __IO uint32_t PIGEONCTRL2;                       /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
66488   __IO uint32_t PIGEONCTRL2_SET;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
66489   __IO uint32_t PIGEONCTRL2_CLR;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
66490   __IO uint32_t PIGEONCTRL2_TOG;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
66491        uint8_t RESERVED_11[1104];
66492   struct {                                         /* offset: 0x800, array step: 0x40 */
66493     __IO uint32_t PIGEON_0;                          /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
66494          uint8_t RESERVED_0[12];
66495     __IO uint32_t PIGEON_1;                          /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
66496          uint8_t RESERVED_1[12];
66497     __IO uint32_t PIGEON_2;                          /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
66498          uint8_t RESERVED_2[28];
66499   } PIGEON[12];
66500   __IO uint32_t LUT_CTRL;                          /**< Look Up Table Control Register, offset: 0xB00 */
66501        uint8_t RESERVED_12[12];
66502   __IO uint32_t LUT0_ADDR;                         /**< Lookup Table 0 Index Register, offset: 0xB10 */
66503        uint8_t RESERVED_13[12];
66504   __IO uint32_t LUT0_DATA;                         /**< Lookup Table 0 Data Register, offset: 0xB20 */
66505        uint8_t RESERVED_14[12];
66506   __IO uint32_t LUT1_ADDR;                         /**< Lookup Table 1 Index Register, offset: 0xB30 */
66507        uint8_t RESERVED_15[12];
66508   __IO uint32_t LUT1_DATA;                         /**< Lookup Table 1 Data Register, offset: 0xB40 */
66509 } LCDIF_Type;
66510 
66511 /* ----------------------------------------------------------------------------
66512    -- LCDIF Register Masks
66513    ---------------------------------------------------------------------------- */
66514 
66515 /*!
66516  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
66517  * @{
66518  */
66519 
66520 /*! @name CTRL - LCDIF General Control Register */
66521 /*! @{ */
66522 
66523 #define LCDIF_CTRL_RUN_MASK                      (0x1U)
66524 #define LCDIF_CTRL_RUN_SHIFT                     (0U)
66525 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
66526 
66527 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
66528 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
66529 /*! DATA_FORMAT_24_BIT
66530  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
66531  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
66532  *       each byte do not contain any useful data, and should be dropped.
66533  */
66534 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
66535 
66536 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
66537 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
66538 /*! DATA_FORMAT_18_BIT
66539  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
66540  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
66541  */
66542 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
66543 
66544 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
66545 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
66546 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
66547 
66548 #define LCDIF_CTRL_RSRVD0_MASK                   (0x10U)
66549 #define LCDIF_CTRL_RSRVD0_SHIFT                  (4U)
66550 #define LCDIF_CTRL_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
66551 
66552 #define LCDIF_CTRL_MASTER_MASK                   (0x20U)
66553 #define LCDIF_CTRL_MASTER_SHIFT                  (5U)
66554 #define LCDIF_CTRL_MASTER(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
66555 
66556 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK     (0x40U)
66557 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT    (6U)
66558 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
66559 
66560 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
66561 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
66562 /*! WORD_LENGTH
66563  *  0b00..Input data is 16 bits per pixel.
66564  *  0b01..Input data is 8 bits wide.
66565  *  0b10..Input data is 18 bits per pixel.
66566  *  0b11..Input data is 24 bits per pixel.
66567  */
66568 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
66569 
66570 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
66571 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
66572 /*! LCD_DATABUS_WIDTH
66573  *  0b00..16-bit data bus mode.
66574  *  0b01..8-bit data bus mode.
66575  *  0b10..18-bit data bus mode.
66576  *  0b11..24-bit data bus mode.
66577  */
66578 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
66579 
66580 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
66581 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
66582 /*! CSC_DATA_SWIZZLE
66583  *  0b00..No byte swapping.(Little endian)
66584  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66585  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66586  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66587  *  0b10..Swap half-words.
66588  *  0b11..Swap bytes within each half-word.
66589  */
66590 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
66591 
66592 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
66593 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
66594 /*! INPUT_DATA_SWIZZLE
66595  *  0b00..No byte swapping.(Little endian)
66596  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66597  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66598  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66599  *  0b10..Swap half-words.
66600  *  0b11..Swap bytes within each half-word.
66601  */
66602 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
66603 
66604 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
66605 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
66606 #define LCDIF_CTRL_DOTCLK_MODE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
66607 
66608 #define LCDIF_CTRL_BYPASS_COUNT_MASK             (0x80000U)
66609 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT            (19U)
66610 #define LCDIF_CTRL_BYPASS_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
66611 
66612 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK           (0x3E00000U)
66613 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT          (21U)
66614 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
66615 
66616 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
66617 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
66618 /*! DATA_SHIFT_DIR
66619  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
66620  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
66621  */
66622 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
66623 
66624 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
66625 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
66626 #define LCDIF_CTRL_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
66627 
66628 #define LCDIF_CTRL_SFTRST_MASK                   (0x80000000U)
66629 #define LCDIF_CTRL_SFTRST_SHIFT                  (31U)
66630 #define LCDIF_CTRL_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
66631 /*! @} */
66632 
66633 /*! @name CTRL_SET - LCDIF General Control Register */
66634 /*! @{ */
66635 
66636 #define LCDIF_CTRL_SET_RUN_MASK                  (0x1U)
66637 #define LCDIF_CTRL_SET_RUN_SHIFT                 (0U)
66638 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
66639 
66640 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
66641 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
66642 /*! DATA_FORMAT_24_BIT
66643  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
66644  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
66645  *       each byte do not contain any useful data, and should be dropped.
66646  */
66647 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
66648 
66649 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
66650 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
66651 /*! DATA_FORMAT_18_BIT
66652  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
66653  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
66654  */
66655 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
66656 
66657 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
66658 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
66659 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
66660 
66661 #define LCDIF_CTRL_SET_RSRVD0_MASK               (0x10U)
66662 #define LCDIF_CTRL_SET_RSRVD0_SHIFT              (4U)
66663 #define LCDIF_CTRL_SET_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
66664 
66665 #define LCDIF_CTRL_SET_MASTER_MASK               (0x20U)
66666 #define LCDIF_CTRL_SET_MASTER_SHIFT              (5U)
66667 #define LCDIF_CTRL_SET_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
66668 
66669 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
66670 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
66671 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
66672 
66673 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
66674 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
66675 /*! WORD_LENGTH
66676  *  0b00..Input data is 16 bits per pixel.
66677  *  0b01..Input data is 8 bits wide.
66678  *  0b10..Input data is 18 bits per pixel.
66679  *  0b11..Input data is 24 bits per pixel.
66680  */
66681 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
66682 
66683 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
66684 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
66685 /*! LCD_DATABUS_WIDTH
66686  *  0b00..16-bit data bus mode.
66687  *  0b01..8-bit data bus mode.
66688  *  0b10..18-bit data bus mode.
66689  *  0b11..24-bit data bus mode.
66690  */
66691 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
66692 
66693 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
66694 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
66695 /*! CSC_DATA_SWIZZLE
66696  *  0b00..No byte swapping.(Little endian)
66697  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66698  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66699  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66700  *  0b10..Swap half-words.
66701  *  0b11..Swap bytes within each half-word.
66702  */
66703 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
66704 
66705 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
66706 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
66707 /*! INPUT_DATA_SWIZZLE
66708  *  0b00..No byte swapping.(Little endian)
66709  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66710  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66711  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66712  *  0b10..Swap half-words.
66713  *  0b11..Swap bytes within each half-word.
66714  */
66715 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
66716 
66717 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
66718 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
66719 #define LCDIF_CTRL_SET_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
66720 
66721 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK         (0x80000U)
66722 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT        (19U)
66723 #define LCDIF_CTRL_SET_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
66724 
66725 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK       (0x3E00000U)
66726 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT      (21U)
66727 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
66728 
66729 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
66730 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
66731 /*! DATA_SHIFT_DIR
66732  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
66733  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
66734  */
66735 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
66736 
66737 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
66738 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
66739 #define LCDIF_CTRL_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
66740 
66741 #define LCDIF_CTRL_SET_SFTRST_MASK               (0x80000000U)
66742 #define LCDIF_CTRL_SET_SFTRST_SHIFT              (31U)
66743 #define LCDIF_CTRL_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
66744 /*! @} */
66745 
66746 /*! @name CTRL_CLR - LCDIF General Control Register */
66747 /*! @{ */
66748 
66749 #define LCDIF_CTRL_CLR_RUN_MASK                  (0x1U)
66750 #define LCDIF_CTRL_CLR_RUN_SHIFT                 (0U)
66751 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
66752 
66753 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
66754 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
66755 /*! DATA_FORMAT_24_BIT
66756  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
66757  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
66758  *       each byte do not contain any useful data, and should be dropped.
66759  */
66760 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
66761 
66762 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
66763 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
66764 /*! DATA_FORMAT_18_BIT
66765  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
66766  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
66767  */
66768 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
66769 
66770 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
66771 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
66772 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
66773 
66774 #define LCDIF_CTRL_CLR_RSRVD0_MASK               (0x10U)
66775 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT              (4U)
66776 #define LCDIF_CTRL_CLR_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
66777 
66778 #define LCDIF_CTRL_CLR_MASTER_MASK               (0x20U)
66779 #define LCDIF_CTRL_CLR_MASTER_SHIFT              (5U)
66780 #define LCDIF_CTRL_CLR_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
66781 
66782 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
66783 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
66784 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
66785 
66786 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
66787 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
66788 /*! WORD_LENGTH
66789  *  0b00..Input data is 16 bits per pixel.
66790  *  0b01..Input data is 8 bits wide.
66791  *  0b10..Input data is 18 bits per pixel.
66792  *  0b11..Input data is 24 bits per pixel.
66793  */
66794 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
66795 
66796 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
66797 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
66798 /*! LCD_DATABUS_WIDTH
66799  *  0b00..16-bit data bus mode.
66800  *  0b01..8-bit data bus mode.
66801  *  0b10..18-bit data bus mode.
66802  *  0b11..24-bit data bus mode.
66803  */
66804 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
66805 
66806 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
66807 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
66808 /*! CSC_DATA_SWIZZLE
66809  *  0b00..No byte swapping.(Little endian)
66810  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66811  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66812  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66813  *  0b10..Swap half-words.
66814  *  0b11..Swap bytes within each half-word.
66815  */
66816 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
66817 
66818 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
66819 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
66820 /*! INPUT_DATA_SWIZZLE
66821  *  0b00..No byte swapping.(Little endian)
66822  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66823  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66824  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66825  *  0b10..Swap half-words.
66826  *  0b11..Swap bytes within each half-word.
66827  */
66828 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
66829 
66830 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
66831 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
66832 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
66833 
66834 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK         (0x80000U)
66835 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT        (19U)
66836 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
66837 
66838 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK       (0x3E00000U)
66839 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT      (21U)
66840 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
66841 
66842 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
66843 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
66844 /*! DATA_SHIFT_DIR
66845  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
66846  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
66847  */
66848 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
66849 
66850 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
66851 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
66852 #define LCDIF_CTRL_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
66853 
66854 #define LCDIF_CTRL_CLR_SFTRST_MASK               (0x80000000U)
66855 #define LCDIF_CTRL_CLR_SFTRST_SHIFT              (31U)
66856 #define LCDIF_CTRL_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
66857 /*! @} */
66858 
66859 /*! @name CTRL_TOG - LCDIF General Control Register */
66860 /*! @{ */
66861 
66862 #define LCDIF_CTRL_TOG_RUN_MASK                  (0x1U)
66863 #define LCDIF_CTRL_TOG_RUN_SHIFT                 (0U)
66864 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
66865 
66866 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
66867 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
66868 /*! DATA_FORMAT_24_BIT
66869  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
66870  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
66871  *       each byte do not contain any useful data, and should be dropped.
66872  */
66873 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
66874 
66875 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
66876 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
66877 /*! DATA_FORMAT_18_BIT
66878  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
66879  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
66880  */
66881 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
66882 
66883 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
66884 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
66885 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
66886 
66887 #define LCDIF_CTRL_TOG_RSRVD0_MASK               (0x10U)
66888 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT              (4U)
66889 #define LCDIF_CTRL_TOG_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
66890 
66891 #define LCDIF_CTRL_TOG_MASTER_MASK               (0x20U)
66892 #define LCDIF_CTRL_TOG_MASTER_SHIFT              (5U)
66893 #define LCDIF_CTRL_TOG_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
66894 
66895 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
66896 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
66897 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
66898 
66899 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
66900 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
66901 /*! WORD_LENGTH
66902  *  0b00..Input data is 16 bits per pixel.
66903  *  0b01..Input data is 8 bits wide.
66904  *  0b10..Input data is 18 bits per pixel.
66905  *  0b11..Input data is 24 bits per pixel.
66906  */
66907 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
66908 
66909 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
66910 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
66911 /*! LCD_DATABUS_WIDTH
66912  *  0b00..16-bit data bus mode.
66913  *  0b01..8-bit data bus mode.
66914  *  0b10..18-bit data bus mode.
66915  *  0b11..24-bit data bus mode.
66916  */
66917 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
66918 
66919 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
66920 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
66921 /*! CSC_DATA_SWIZZLE
66922  *  0b00..No byte swapping.(Little endian)
66923  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66924  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66925  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66926  *  0b10..Swap half-words.
66927  *  0b11..Swap bytes within each half-word.
66928  */
66929 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
66930 
66931 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
66932 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
66933 /*! INPUT_DATA_SWIZZLE
66934  *  0b00..No byte swapping.(Little endian)
66935  *  0b00..Little Endian byte ordering (same as NO_SWAP).
66936  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
66937  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
66938  *  0b10..Swap half-words.
66939  *  0b11..Swap bytes within each half-word.
66940  */
66941 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
66942 
66943 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
66944 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
66945 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
66946 
66947 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK         (0x80000U)
66948 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT        (19U)
66949 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
66950 
66951 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK       (0x3E00000U)
66952 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT      (21U)
66953 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
66954 
66955 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
66956 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
66957 /*! DATA_SHIFT_DIR
66958  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
66959  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
66960  */
66961 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
66962 
66963 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
66964 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
66965 #define LCDIF_CTRL_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
66966 
66967 #define LCDIF_CTRL_TOG_SFTRST_MASK               (0x80000000U)
66968 #define LCDIF_CTRL_TOG_SFTRST_SHIFT              (31U)
66969 #define LCDIF_CTRL_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
66970 /*! @} */
66971 
66972 /*! @name CTRL1 - LCDIF General Control1 Register */
66973 /*! @{ */
66974 
66975 #define LCDIF_CTRL1_RSRVD0_MASK                  (0xF8U)
66976 #define LCDIF_CTRL1_RSRVD0_SHIFT                 (3U)
66977 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
66978 
66979 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
66980 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
66981 /*! VSYNC_EDGE_IRQ
66982  *  0b0..No Interrupt Request Pending.
66983  *  0b1..Interrupt Request Pending.
66984  */
66985 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
66986 
66987 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
66988 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
66989 /*! CUR_FRAME_DONE_IRQ
66990  *  0b0..No Interrupt Request Pending.
66991  *  0b1..Interrupt Request Pending.
66992  */
66993 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
66994 
66995 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
66996 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
66997 /*! UNDERFLOW_IRQ
66998  *  0b0..No Interrupt Request Pending.
66999  *  0b1..Interrupt Request Pending.
67000  */
67001 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
67002 
67003 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
67004 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
67005 /*! OVERFLOW_IRQ
67006  *  0b0..No Interrupt Request Pending.
67007  *  0b1..Interrupt Request Pending.
67008  */
67009 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
67010 
67011 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
67012 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
67013 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
67014 
67015 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
67016 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  (13U)
67017 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
67018 
67019 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        (0x4000U)
67020 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       (14U)
67021 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
67022 
67023 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         (0x8000U)
67024 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        (15U)
67025 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
67026 
67027 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     (0xF0000U)
67028 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    (16U)
67029 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
67030 
67031 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67032 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67033 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
67034 
67035 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              (0x200000U)
67036 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             (21U)
67037 #define LCDIF_CTRL1_FIFO_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
67038 
67039 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67040 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67041 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67042 
67043 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        (0x800000U)
67044 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       (23U)
67045 #define LCDIF_CTRL1_INTERLACE_FIELDS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
67046 
67047 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    (0x1000000U)
67048 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
67049 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
67050 
67051 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
67052 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
67053 /*! BM_ERROR_IRQ
67054  *  0b0..No Interrupt Request Pending.
67055  *  0b1..Interrupt Request Pending.
67056  */
67057 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
67058 
67059 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
67060 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
67061 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
67062 
67063 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK           (0x40000000U)
67064 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT          (30U)
67065 #define LCDIF_CTRL1_CS_OUT_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
67066 
67067 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK       (0x80000000U)
67068 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT      (31U)
67069 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
67070 /*! @} */
67071 
67072 /*! @name CTRL1_SET - LCDIF General Control1 Register */
67073 /*! @{ */
67074 
67075 #define LCDIF_CTRL1_SET_RSRVD0_MASK              (0xF8U)
67076 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             (3U)
67077 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
67078 
67079 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
67080 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
67081 /*! VSYNC_EDGE_IRQ
67082  *  0b0..No Interrupt Request Pending.
67083  *  0b1..Interrupt Request Pending.
67084  */
67085 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
67086 
67087 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67088 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67089 /*! CUR_FRAME_DONE_IRQ
67090  *  0b0..No Interrupt Request Pending.
67091  *  0b1..Interrupt Request Pending.
67092  */
67093 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
67094 
67095 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
67096 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
67097 /*! UNDERFLOW_IRQ
67098  *  0b0..No Interrupt Request Pending.
67099  *  0b1..Interrupt Request Pending.
67100  */
67101 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
67102 
67103 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
67104 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
67105 /*! OVERFLOW_IRQ
67106  *  0b0..No Interrupt Request Pending.
67107  *  0b1..Interrupt Request Pending.
67108  */
67109 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
67110 
67111 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67112 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67113 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
67114 
67115 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67116 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67117 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
67118 
67119 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67120 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67121 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
67122 
67123 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67124 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    (15U)
67125 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
67126 
67127 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67128 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
67129 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
67130 
67131 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67132 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67133 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
67134 
67135 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          (0x200000U)
67136 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         (21U)
67137 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
67138 
67139 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67140 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67141 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67142 
67143 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    (0x800000U)
67144 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
67145 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
67146 
67147 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67148 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67149 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
67150 
67151 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
67152 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
67153 /*! BM_ERROR_IRQ
67154  *  0b0..No Interrupt Request Pending.
67155  *  0b1..Interrupt Request Pending.
67156  */
67157 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
67158 
67159 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67160 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
67161 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
67162 
67163 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK       (0x40000000U)
67164 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT      (30U)
67165 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
67166 
67167 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67168 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT  (31U)
67169 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
67170 /*! @} */
67171 
67172 /*! @name CTRL1_CLR - LCDIF General Control1 Register */
67173 /*! @{ */
67174 
67175 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              (0xF8U)
67176 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             (3U)
67177 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
67178 
67179 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
67180 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
67181 /*! VSYNC_EDGE_IRQ
67182  *  0b0..No Interrupt Request Pending.
67183  *  0b1..Interrupt Request Pending.
67184  */
67185 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
67186 
67187 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67188 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67189 /*! CUR_FRAME_DONE_IRQ
67190  *  0b0..No Interrupt Request Pending.
67191  *  0b1..Interrupt Request Pending.
67192  */
67193 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
67194 
67195 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
67196 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
67197 /*! UNDERFLOW_IRQ
67198  *  0b0..No Interrupt Request Pending.
67199  *  0b1..Interrupt Request Pending.
67200  */
67201 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
67202 
67203 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
67204 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
67205 /*! OVERFLOW_IRQ
67206  *  0b0..No Interrupt Request Pending.
67207  *  0b1..Interrupt Request Pending.
67208  */
67209 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
67210 
67211 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67212 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67213 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
67214 
67215 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67216 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67217 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
67218 
67219 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67220 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67221 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
67222 
67223 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67224 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    (15U)
67225 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
67226 
67227 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67228 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
67229 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
67230 
67231 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67232 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67233 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
67234 
67235 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          (0x200000U)
67236 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         (21U)
67237 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
67238 
67239 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67240 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67241 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67242 
67243 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    (0x800000U)
67244 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
67245 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
67246 
67247 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67248 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67249 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
67250 
67251 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
67252 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
67253 /*! BM_ERROR_IRQ
67254  *  0b0..No Interrupt Request Pending.
67255  *  0b1..Interrupt Request Pending.
67256  */
67257 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
67258 
67259 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67260 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
67261 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
67262 
67263 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK       (0x40000000U)
67264 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT      (30U)
67265 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
67266 
67267 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67268 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT  (31U)
67269 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
67270 /*! @} */
67271 
67272 /*! @name CTRL1_TOG - LCDIF General Control1 Register */
67273 /*! @{ */
67274 
67275 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              (0xF8U)
67276 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             (3U)
67277 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
67278 
67279 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
67280 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
67281 /*! VSYNC_EDGE_IRQ
67282  *  0b0..No Interrupt Request Pending.
67283  *  0b1..Interrupt Request Pending.
67284  */
67285 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
67286 
67287 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67288 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67289 /*! CUR_FRAME_DONE_IRQ
67290  *  0b0..No Interrupt Request Pending.
67291  *  0b1..Interrupt Request Pending.
67292  */
67293 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
67294 
67295 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
67296 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
67297 /*! UNDERFLOW_IRQ
67298  *  0b0..No Interrupt Request Pending.
67299  *  0b1..Interrupt Request Pending.
67300  */
67301 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
67302 
67303 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
67304 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
67305 /*! OVERFLOW_IRQ
67306  *  0b0..No Interrupt Request Pending.
67307  *  0b1..Interrupt Request Pending.
67308  */
67309 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
67310 
67311 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67312 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67313 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
67314 
67315 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67316 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67317 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
67318 
67319 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67320 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67321 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
67322 
67323 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67324 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    (15U)
67325 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
67326 
67327 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67328 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
67329 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
67330 
67331 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67332 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67333 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
67334 
67335 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          (0x200000U)
67336 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         (21U)
67337 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
67338 
67339 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67340 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67341 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67342 
67343 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    (0x800000U)
67344 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
67345 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
67346 
67347 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67348 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67349 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
67350 
67351 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
67352 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
67353 /*! BM_ERROR_IRQ
67354  *  0b0..No Interrupt Request Pending.
67355  *  0b1..Interrupt Request Pending.
67356  */
67357 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
67358 
67359 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67360 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
67361 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
67362 
67363 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK       (0x40000000U)
67364 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT      (30U)
67365 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
67366 
67367 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67368 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT  (31U)
67369 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
67370 /*! @} */
67371 
67372 /*! @name CTRL2 - LCDIF General Control2 Register */
67373 /*! @{ */
67374 
67375 #define LCDIF_CTRL2_RSRVD0_MASK                  (0xFFFU)
67376 #define LCDIF_CTRL2_RSRVD0_SHIFT                 (0U)
67377 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
67378 
67379 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
67380 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
67381 /*! EVEN_LINE_PATTERN
67382  *  0b000..RGB
67383  *  0b001..RBG
67384  *  0b010..GBR
67385  *  0b011..GRB
67386  *  0b100..BRG
67387  *  0b101..BGR
67388  */
67389 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
67390 
67391 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
67392 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
67393 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
67394 
67395 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
67396 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
67397 /*! ODD_LINE_PATTERN
67398  *  0b000..RGB
67399  *  0b001..RBG
67400  *  0b010..GBR
67401  *  0b011..GRB
67402  *  0b100..BRG
67403  *  0b101..BGR
67404  */
67405 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
67406 
67407 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
67408 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
67409 #define LCDIF_CTRL2_RSRVD4(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
67410 
67411 #define LCDIF_CTRL2_BURST_LEN_8_MASK             (0x100000U)
67412 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            (20U)
67413 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
67414 
67415 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
67416 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
67417 /*! OUTSTANDING_REQS
67418  *  0b000..REQ_1
67419  *  0b001..REQ_2
67420  *  0b010..REQ_4
67421  *  0b011..REQ_8
67422  *  0b100..REQ_16
67423  */
67424 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
67425 
67426 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
67427 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
67428 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
67429 /*! @} */
67430 
67431 /*! @name CTRL2_SET - LCDIF General Control2 Register */
67432 /*! @{ */
67433 
67434 #define LCDIF_CTRL2_SET_RSRVD0_MASK              (0xFFFU)
67435 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             (0U)
67436 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
67437 
67438 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
67439 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
67440 /*! EVEN_LINE_PATTERN
67441  *  0b000..RGB
67442  *  0b001..RBG
67443  *  0b010..GBR
67444  *  0b011..GRB
67445  *  0b100..BRG
67446  *  0b101..BGR
67447  */
67448 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
67449 
67450 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
67451 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
67452 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
67453 
67454 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
67455 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
67456 /*! ODD_LINE_PATTERN
67457  *  0b000..RGB
67458  *  0b001..RBG
67459  *  0b010..GBR
67460  *  0b011..GRB
67461  *  0b100..BRG
67462  *  0b101..BGR
67463  */
67464 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
67465 
67466 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
67467 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
67468 #define LCDIF_CTRL2_SET_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
67469 
67470 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         (0x100000U)
67471 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        (20U)
67472 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
67473 
67474 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
67475 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
67476 /*! OUTSTANDING_REQS
67477  *  0b000..REQ_1
67478  *  0b001..REQ_2
67479  *  0b010..REQ_4
67480  *  0b011..REQ_8
67481  *  0b100..REQ_16
67482  */
67483 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
67484 
67485 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
67486 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
67487 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
67488 /*! @} */
67489 
67490 /*! @name CTRL2_CLR - LCDIF General Control2 Register */
67491 /*! @{ */
67492 
67493 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              (0xFFFU)
67494 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             (0U)
67495 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
67496 
67497 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
67498 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
67499 /*! EVEN_LINE_PATTERN
67500  *  0b000..RGB
67501  *  0b001..RBG
67502  *  0b010..GBR
67503  *  0b011..GRB
67504  *  0b100..BRG
67505  *  0b101..BGR
67506  */
67507 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
67508 
67509 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
67510 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
67511 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
67512 
67513 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
67514 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
67515 /*! ODD_LINE_PATTERN
67516  *  0b000..RGB
67517  *  0b001..RBG
67518  *  0b010..GBR
67519  *  0b011..GRB
67520  *  0b100..BRG
67521  *  0b101..BGR
67522  */
67523 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
67524 
67525 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
67526 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
67527 #define LCDIF_CTRL2_CLR_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
67528 
67529 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         (0x100000U)
67530 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        (20U)
67531 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
67532 
67533 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
67534 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
67535 /*! OUTSTANDING_REQS
67536  *  0b000..REQ_1
67537  *  0b001..REQ_2
67538  *  0b010..REQ_4
67539  *  0b011..REQ_8
67540  *  0b100..REQ_16
67541  */
67542 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
67543 
67544 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
67545 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
67546 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
67547 /*! @} */
67548 
67549 /*! @name CTRL2_TOG - LCDIF General Control2 Register */
67550 /*! @{ */
67551 
67552 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              (0xFFFU)
67553 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             (0U)
67554 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
67555 
67556 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
67557 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
67558 /*! EVEN_LINE_PATTERN
67559  *  0b000..RGB
67560  *  0b001..RBG
67561  *  0b010..GBR
67562  *  0b011..GRB
67563  *  0b100..BRG
67564  *  0b101..BGR
67565  */
67566 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
67567 
67568 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
67569 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
67570 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
67571 
67572 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
67573 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
67574 /*! ODD_LINE_PATTERN
67575  *  0b000..RGB
67576  *  0b001..RBG
67577  *  0b010..GBR
67578  *  0b011..GRB
67579  *  0b100..BRG
67580  *  0b101..BGR
67581  */
67582 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
67583 
67584 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
67585 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
67586 #define LCDIF_CTRL2_TOG_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
67587 
67588 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         (0x100000U)
67589 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        (20U)
67590 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
67591 
67592 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
67593 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
67594 /*! OUTSTANDING_REQS
67595  *  0b000..REQ_1
67596  *  0b001..REQ_2
67597  *  0b010..REQ_4
67598  *  0b011..REQ_8
67599  *  0b100..REQ_16
67600  */
67601 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
67602 
67603 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
67604 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
67605 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
67606 /*! @} */
67607 
67608 /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
67609 /*! @{ */
67610 
67611 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        (0xFFFFU)
67612 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       (0U)
67613 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
67614 
67615 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        (0xFFFF0000U)
67616 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       (16U)
67617 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
67618 /*! @} */
67619 
67620 /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
67621 /*! @{ */
67622 
67623 #define LCDIF_CUR_BUF_ADDR_MASK                  (0xFFFFFFFFU)
67624 #define LCDIF_CUR_BUF_ADDR_SHIFT                 (0U)
67625 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
67626 /*! @} */
67627 
67628 /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
67629 /*! @{ */
67630 
67631 #define LCDIF_NEXT_BUF_ADDR_MASK                 (0xFFFFFFFFU)
67632 #define LCDIF_NEXT_BUF_ADDR_SHIFT                (0U)
67633 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
67634 /*! @} */
67635 
67636 /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
67637 /*! @{ */
67638 
67639 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     (0x3FFFFU)
67640 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    (0U)
67641 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
67642 
67643 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        (0x40000U)
67644 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       (18U)
67645 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
67646 
67647 #define LCDIF_VDCTRL0_HALF_LINE_MASK             (0x80000U)
67648 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            (19U)
67649 #define LCDIF_VDCTRL0_HALF_LINE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
67650 
67651 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
67652 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
67653 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
67654 
67655 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     (0x200000U)
67656 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    (21U)
67657 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
67658 
67659 #define LCDIF_VDCTRL0_RSRVD1_MASK                (0xC00000U)
67660 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               (22U)
67661 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
67662 
67663 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            (0x1000000U)
67664 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           (24U)
67665 #define LCDIF_VDCTRL0_ENABLE_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
67666 
67667 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            (0x2000000U)
67668 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           (25U)
67669 #define LCDIF_VDCTRL0_DOTCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
67670 
67671 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             (0x4000000U)
67672 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            (26U)
67673 #define LCDIF_VDCTRL0_HSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
67674 
67675 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             (0x8000000U)
67676 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            (27U)
67677 #define LCDIF_VDCTRL0_VSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
67678 
67679 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        (0x10000000U)
67680 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       (28U)
67681 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
67682 
67683 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             (0x20000000U)
67684 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            (29U)
67685 /*! VSYNC_OEB
67686  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
67687  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
67688  */
67689 #define LCDIF_VDCTRL0_VSYNC_OEB(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
67690 
67691 #define LCDIF_VDCTRL0_RSRVD2_MASK                (0xC0000000U)
67692 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               (30U)
67693 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
67694 /*! @} */
67695 
67696 /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
67697 /*! @{ */
67698 
67699 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
67700 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
67701 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
67702 
67703 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    (0x40000U)
67704 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
67705 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
67706 
67707 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         (0x80000U)
67708 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        (19U)
67709 #define LCDIF_VDCTRL0_SET_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
67710 
67711 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
67712 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
67713 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
67714 
67715 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
67716 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
67717 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
67718 
67719 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            (0xC00000U)
67720 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           (22U)
67721 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
67722 
67723 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        (0x1000000U)
67724 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       (24U)
67725 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
67726 
67727 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        (0x2000000U)
67728 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       (25U)
67729 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
67730 
67731 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         (0x4000000U)
67732 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        (26U)
67733 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
67734 
67735 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         (0x8000000U)
67736 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        (27U)
67737 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
67738 
67739 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    (0x10000000U)
67740 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
67741 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
67742 
67743 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         (0x20000000U)
67744 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        (29U)
67745 /*! VSYNC_OEB
67746  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
67747  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
67748  */
67749 #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
67750 
67751 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            (0xC0000000U)
67752 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           (30U)
67753 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
67754 /*! @} */
67755 
67756 /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
67757 /*! @{ */
67758 
67759 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
67760 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
67761 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
67762 
67763 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    (0x40000U)
67764 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
67765 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
67766 
67767 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         (0x80000U)
67768 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        (19U)
67769 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
67770 
67771 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
67772 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
67773 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
67774 
67775 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
67776 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
67777 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
67778 
67779 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            (0xC00000U)
67780 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           (22U)
67781 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
67782 
67783 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        (0x1000000U)
67784 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       (24U)
67785 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
67786 
67787 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        (0x2000000U)
67788 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       (25U)
67789 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
67790 
67791 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         (0x4000000U)
67792 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        (26U)
67793 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
67794 
67795 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         (0x8000000U)
67796 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        (27U)
67797 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
67798 
67799 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    (0x10000000U)
67800 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
67801 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
67802 
67803 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         (0x20000000U)
67804 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        (29U)
67805 /*! VSYNC_OEB
67806  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
67807  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
67808  */
67809 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
67810 
67811 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            (0xC0000000U)
67812 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           (30U)
67813 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
67814 /*! @} */
67815 
67816 /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
67817 /*! @{ */
67818 
67819 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
67820 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
67821 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
67822 
67823 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    (0x40000U)
67824 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
67825 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
67826 
67827 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         (0x80000U)
67828 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        (19U)
67829 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
67830 
67831 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
67832 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
67833 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
67834 
67835 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
67836 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
67837 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
67838 
67839 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            (0xC00000U)
67840 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           (22U)
67841 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
67842 
67843 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        (0x1000000U)
67844 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       (24U)
67845 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
67846 
67847 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        (0x2000000U)
67848 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       (25U)
67849 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
67850 
67851 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         (0x4000000U)
67852 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        (26U)
67853 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
67854 
67855 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         (0x8000000U)
67856 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        (27U)
67857 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
67858 
67859 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    (0x10000000U)
67860 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
67861 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
67862 
67863 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         (0x20000000U)
67864 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        (29U)
67865 /*! VSYNC_OEB
67866  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
67867  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
67868  */
67869 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
67870 
67871 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            (0xC0000000U)
67872 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           (30U)
67873 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
67874 /*! @} */
67875 
67876 /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
67877 /*! @{ */
67878 
67879 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          (0xFFFFFFFFU)
67880 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         (0U)
67881 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
67882 /*! @} */
67883 
67884 /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
67885 /*! @{ */
67886 
67887 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          (0x3FFFFU)
67888 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         (0U)
67889 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
67890 
67891 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     (0xFFFC0000U)
67892 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    (18U)
67893 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
67894 /*! @} */
67895 
67896 /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
67897 /*! @{ */
67898 
67899 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     (0xFFFFU)
67900 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    (0U)
67901 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
67902 
67903 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
67904 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  (16U)
67905 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
67906 
67907 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            (0x10000000U)
67908 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           (28U)
67909 #define LCDIF_VDCTRL3_VSYNC_ONLY(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
67910 
67911 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      (0x20000000U)
67912 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     (29U)
67913 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
67914 
67915 #define LCDIF_VDCTRL3_RSRVD0_MASK                (0xC0000000U)
67916 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               (30U)
67917 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
67918 /*! @} */
67919 
67920 /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
67921 /*! @{ */
67922 
67923 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
67924 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
67925 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
67926 
67927 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       (0x40000U)
67928 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      (18U)
67929 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
67930 
67931 #define LCDIF_VDCTRL4_RSRVD0_MASK                (0x1FF80000U)
67932 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               (19U)
67933 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
67934 
67935 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        (0xE0000000U)
67936 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       (29U)
67937 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
67938 /*! @} */
67939 
67940 /*! @name BM_ERROR_STAT - Bus Master Error Status Register */
67941 /*! @{ */
67942 
67943 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            (0xFFFFFFFFU)
67944 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           (0U)
67945 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
67946 /*! @} */
67947 
67948 /*! @name CRC_STAT - CRC Status Register */
67949 /*! @{ */
67950 
67951 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            (0xFFFFFFFFU)
67952 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           (0U)
67953 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
67954 /*! @} */
67955 
67956 /*! @name STAT - LCD Interface Status Register */
67957 /*! @{ */
67958 
67959 #define LCDIF_STAT_LFIFO_COUNT_MASK              (0x1FFU)
67960 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             (0U)
67961 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
67962 
67963 #define LCDIF_STAT_RSRVD0_MASK                   (0x1FFFE00U)
67964 #define LCDIF_STAT_RSRVD0_SHIFT                  (9U)
67965 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
67966 
67967 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             (0x4000000U)
67968 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            (26U)
67969 #define LCDIF_STAT_TXFIFO_EMPTY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
67970 
67971 #define LCDIF_STAT_TXFIFO_FULL_MASK              (0x8000000U)
67972 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             (27U)
67973 #define LCDIF_STAT_TXFIFO_FULL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
67974 
67975 #define LCDIF_STAT_LFIFO_EMPTY_MASK              (0x10000000U)
67976 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             (28U)
67977 #define LCDIF_STAT_LFIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
67978 
67979 #define LCDIF_STAT_LFIFO_FULL_MASK               (0x20000000U)
67980 #define LCDIF_STAT_LFIFO_FULL_SHIFT              (29U)
67981 #define LCDIF_STAT_LFIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
67982 
67983 #define LCDIF_STAT_DMA_REQ_MASK                  (0x40000000U)
67984 #define LCDIF_STAT_DMA_REQ_SHIFT                 (30U)
67985 #define LCDIF_STAT_DMA_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
67986 
67987 #define LCDIF_STAT_PRESENT_MASK                  (0x80000000U)
67988 #define LCDIF_STAT_PRESENT_SHIFT                 (31U)
67989 #define LCDIF_STAT_PRESENT(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
67990 /*! @} */
67991 
67992 /*! @name THRES - LCDIF Threshold Register */
67993 /*! @{ */
67994 
67995 #define LCDIF_THRES_RSRVD_MASK                   (0x1FFU)
67996 #define LCDIF_THRES_RSRVD_SHIFT                  (0U)
67997 #define LCDIF_THRES_RSRVD(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)
67998 
67999 #define LCDIF_THRES_RSRVD1_MASK                  (0xFE00U)
68000 #define LCDIF_THRES_RSRVD1_SHIFT                 (9U)
68001 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
68002 
68003 #define LCDIF_THRES_FASTCLOCK_MASK               (0x1FF0000U)
68004 #define LCDIF_THRES_FASTCLOCK_SHIFT              (16U)
68005 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
68006 
68007 #define LCDIF_THRES_RSRVD2_MASK                  (0xFE000000U)
68008 #define LCDIF_THRES_RSRVD2_SHIFT                 (25U)
68009 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
68010 /*! @} */
68011 
68012 /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
68013 /*! @{ */
68014 
68015 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK         (0xFFFU)
68016 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT        (0U)
68017 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
68018 
68019 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK         (0xFFF0000U)
68020 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT        (16U)
68021 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
68022 /*! @} */
68023 
68024 /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
68025 /*! @{ */
68026 
68027 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK     (0xFFFU)
68028 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT    (0U)
68029 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
68030 
68031 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK     (0xFFF0000U)
68032 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT    (16U)
68033 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
68034 /*! @} */
68035 
68036 /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
68037 /*! @{ */
68038 
68039 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK     (0xFFFU)
68040 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT    (0U)
68041 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
68042 
68043 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK     (0xFFF0000U)
68044 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT    (16U)
68045 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
68046 /*! @} */
68047 
68048 /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
68049 /*! @{ */
68050 
68051 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK     (0xFFFU)
68052 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT    (0U)
68053 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
68054 
68055 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK     (0xFFF0000U)
68056 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT    (16U)
68057 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
68058 /*! @} */
68059 
68060 /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
68061 /*! @{ */
68062 
68063 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK  (0xFFFU)
68064 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
68065 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
68066 
68067 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK  (0xFFF0000U)
68068 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
68069 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
68070 /*! @} */
68071 
68072 /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
68073 /*! @{ */
68074 
68075 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
68076 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
68077 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
68078 
68079 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68080 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
68081 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
68082 /*! @} */
68083 
68084 /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
68085 /*! @{ */
68086 
68087 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
68088 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
68089 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
68090 
68091 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68092 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
68093 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
68094 /*! @} */
68095 
68096 /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
68097 /*! @{ */
68098 
68099 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
68100 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
68101 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
68102 
68103 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68104 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
68105 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
68106 /*! @} */
68107 
68108 /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
68109 /*! @{ */
68110 
68111 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK    (0x1U)
68112 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT   (0U)
68113 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
68114 
68115 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK   (0x2U)
68116 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT  (1U)
68117 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
68118 /*! @} */
68119 
68120 /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
68121 /*! @{ */
68122 
68123 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
68124 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
68125 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
68126 
68127 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
68128 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
68129 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
68130 /*! @} */
68131 
68132 /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
68133 /*! @{ */
68134 
68135 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
68136 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
68137 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
68138 
68139 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
68140 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
68141 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
68142 /*! @} */
68143 
68144 /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
68145 /*! @{ */
68146 
68147 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
68148 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
68149 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
68150 
68151 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
68152 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
68153 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
68154 /*! @} */
68155 
68156 /*! @name PIGEON_0 - Panel Interface Signal Generator Register */
68157 /*! @{ */
68158 
68159 #define LCDIF_PIGEON_0_EN_MASK                   (0x1U)
68160 #define LCDIF_PIGEON_0_EN_SHIFT                  (0U)
68161 #define LCDIF_PIGEON_0_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
68162 
68163 #define LCDIF_PIGEON_0_POL_MASK                  (0x2U)
68164 #define LCDIF_PIGEON_0_POL_SHIFT                 (1U)
68165 /*! POL
68166  *  0b0..Normal Signal (Active high)
68167  *  0b1..Inverted signal (Active low)
68168  */
68169 #define LCDIF_PIGEON_0_POL(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
68170 
68171 #define LCDIF_PIGEON_0_INC_SEL_MASK              (0xCU)
68172 #define LCDIF_PIGEON_0_INC_SEL_SHIFT             (2U)
68173 /*! INC_SEL
68174  *  0b00..pclk
68175  *  0b01..Line start pulse
68176  *  0b10..Frame start pulse
68177  *  0b11..Use another signal as tick event
68178  */
68179 #define LCDIF_PIGEON_0_INC_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
68180 
68181 #define LCDIF_PIGEON_0_OFFSET_MASK               (0xF0U)
68182 #define LCDIF_PIGEON_0_OFFSET_SHIFT              (4U)
68183 #define LCDIF_PIGEON_0_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
68184 
68185 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK         (0xF00U)
68186 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT        (8U)
68187 /*! MASK_CNT_SEL
68188  *  0b0000..pclk counter within one hscan state
68189  *  0b0001..pclk cycle within one hscan state
68190  *  0b0010..line counter within one vscan state
68191  *  0b0011..line cycle within one vscan state
68192  *  0b0100..frame counter
68193  *  0b0101..frame cycle
68194  *  0b0110..horizontal counter (pclk counter within one line )
68195  *  0b0111..vertical counter (line counter within one frame)
68196  */
68197 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
68198 
68199 #define LCDIF_PIGEON_0_MASK_CNT_MASK             (0xFFF000U)
68200 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT            (12U)
68201 #define LCDIF_PIGEON_0_MASK_CNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
68202 
68203 #define LCDIF_PIGEON_0_STATE_MASK_MASK           (0xFF000000U)
68204 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT          (24U)
68205 /*! STATE_MASK
68206  *  0b00000001..FRAME SYNC
68207  *  0b00000010..FRAME BEGIN
68208  *  0b00000100..FRAME DATA
68209  *  0b00001000..FRAME END
68210  *  0b00010000..LINE SYNC
68211  *  0b00100000..LINE BEGIN
68212  *  0b01000000..LINE DATA
68213  *  0b10000000..LINE END
68214  */
68215 #define LCDIF_PIGEON_0_STATE_MASK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
68216 /*! @} */
68217 
68218 /* The count of LCDIF_PIGEON_0 */
68219 #define LCDIF_PIGEON_0_COUNT                     (12U)
68220 
68221 /*! @name PIGEON_1 - Panel Interface Signal Generator Register */
68222 /*! @{ */
68223 
68224 #define LCDIF_PIGEON_1_SET_CNT_MASK              (0xFFFFU)
68225 #define LCDIF_PIGEON_1_SET_CNT_SHIFT             (0U)
68226 /*! SET_CNT
68227  *  0b0000000000000000..Start as active
68228  */
68229 #define LCDIF_PIGEON_1_SET_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
68230 
68231 #define LCDIF_PIGEON_1_CLR_CNT_MASK              (0xFFFF0000U)
68232 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT             (16U)
68233 /*! CLR_CNT
68234  *  0b0000000000000000..Keep active until mask off
68235  */
68236 #define LCDIF_PIGEON_1_CLR_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
68237 /*! @} */
68238 
68239 /* The count of LCDIF_PIGEON_1 */
68240 #define LCDIF_PIGEON_1_COUNT                     (12U)
68241 
68242 /*! @name PIGEON_2 - Panel Interface Signal Generator Register */
68243 /*! @{ */
68244 
68245 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK            (0xFU)
68246 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT           (0U)
68247 /*! SIG_LOGIC
68248  *  0b0000..No logic operation
68249  *  0b0001..sigout = sig_another AND this_sig
68250  *  0b0010..sigout = sig_another OR this_sig
68251  *  0b0011..mask = sig_another AND other_masks
68252  */
68253 #define LCDIF_PIGEON_2_SIG_LOGIC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
68254 
68255 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK          (0x1F0U)
68256 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT         (4U)
68257 /*! SIG_ANOTHER
68258  *  0b00000..Keep active until mask off
68259  */
68260 #define LCDIF_PIGEON_2_SIG_ANOTHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
68261 
68262 #define LCDIF_PIGEON_2_RSVD_MASK                 (0xFFFFFE00U)
68263 #define LCDIF_PIGEON_2_RSVD_SHIFT                (9U)
68264 #define LCDIF_PIGEON_2_RSVD(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
68265 /*! @} */
68266 
68267 /* The count of LCDIF_PIGEON_2 */
68268 #define LCDIF_PIGEON_2_COUNT                     (12U)
68269 
68270 /*! @name LUT_CTRL - Look Up Table Control Register */
68271 /*! @{ */
68272 
68273 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK           (0x1U)
68274 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT          (0U)
68275 #define LCDIF_LUT_CTRL_LUT_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
68276 /*! @} */
68277 
68278 /*! @name LUT0_ADDR - Lookup Table 0 Index Register */
68279 /*! @{ */
68280 
68281 #define LCDIF_LUT0_ADDR_ADDR_MASK                (0xFFU)
68282 #define LCDIF_LUT0_ADDR_ADDR_SHIFT               (0U)
68283 #define LCDIF_LUT0_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
68284 /*! @} */
68285 
68286 /*! @name LUT0_DATA - Lookup Table 0 Data Register */
68287 /*! @{ */
68288 
68289 #define LCDIF_LUT0_DATA_DATA_MASK                (0xFFFFFFFFU)
68290 #define LCDIF_LUT0_DATA_DATA_SHIFT               (0U)
68291 #define LCDIF_LUT0_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
68292 /*! @} */
68293 
68294 /*! @name LUT1_ADDR - Lookup Table 1 Index Register */
68295 /*! @{ */
68296 
68297 #define LCDIF_LUT1_ADDR_ADDR_MASK                (0xFFU)
68298 #define LCDIF_LUT1_ADDR_ADDR_SHIFT               (0U)
68299 #define LCDIF_LUT1_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
68300 /*! @} */
68301 
68302 /*! @name LUT1_DATA - Lookup Table 1 Data Register */
68303 /*! @{ */
68304 
68305 #define LCDIF_LUT1_DATA_DATA_MASK                (0xFFFFFFFFU)
68306 #define LCDIF_LUT1_DATA_DATA_SHIFT               (0U)
68307 #define LCDIF_LUT1_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
68308 /*! @} */
68309 
68310 
68311 /*!
68312  * @}
68313  */ /* end of group LCDIF_Register_Masks */
68314 
68315 
68316 /* LCDIF - Peripheral instance base addresses */
68317 /** Peripheral LCDIF base address */
68318 #define LCDIF_BASE                               (0x40804000u)
68319 /** Peripheral LCDIF base pointer */
68320 #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
68321 /** Array initializer of LCDIF peripheral base addresses */
68322 #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
68323 /** Array initializer of LCDIF peripheral base pointers */
68324 #define LCDIF_BASE_PTRS                          { LCDIF }
68325 /** Interrupt vectors for the LCDIF peripheral type */
68326 #define LCDIF_IRQ0_IRQS                          { eLCDIF_IRQn }
68327 
68328 /*!
68329  * @}
68330  */ /* end of group LCDIF_Peripheral_Access_Layer */
68331 
68332 
68333 /* ----------------------------------------------------------------------------
68334    -- LCDIFV2 Peripheral Access Layer
68335    ---------------------------------------------------------------------------- */
68336 
68337 /*!
68338  * @addtogroup LCDIFV2_Peripheral_Access_Layer LCDIFV2 Peripheral Access Layer
68339  * @{
68340  */
68341 
68342 /** LCDIFV2 - Register Layout Typedef */
68343 typedef struct {
68344   __IO uint32_t CTRL;                              /**< LCDIFv2 display control Register, offset: 0x0 */
68345   __IO uint32_t CTRL_SET;                          /**< LCDIFv2 display control Register, offset: 0x4 */
68346   __IO uint32_t CTRL_CLR;                          /**< LCDIFv2 display control Register, offset: 0x8 */
68347   __IO uint32_t CTRL_TOG;                          /**< LCDIFv2 display control Register, offset: 0xC */
68348   __IO uint32_t DISP_PARA;                         /**< Display Parameter Register, offset: 0x10 */
68349   __IO uint32_t DISP_SIZE;                         /**< Display Size Register, offset: 0x14 */
68350   __IO uint32_t HSYN_PARA;                         /**< Horizontal Sync Parameter Register, offset: 0x18 */
68351   __IO uint32_t VSYN_PARA;                         /**< Vertical Sync Parameter Register, offset: 0x1C */
68352   struct {                                         /* offset: 0x20, array step: 0x10 */
68353     __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10 */
68354     __IO uint32_t INT_ENABLE;                        /**< Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10 */
68355          uint8_t RESERVED_0[8];
68356   } INT[2];
68357   __IO uint32_t PDI_PARA;                          /**< Parallel Data Interface Parameter Register, offset: 0x40 */
68358        uint8_t RESERVED_0[444];
68359   struct {                                         /* offset: 0x200, array step: 0x40 */
68360     __IO uint32_t CTRLDESCL1;                        /**< Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40 */
68361     __IO uint32_t CTRLDESCL2;                        /**< Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40 */
68362     __IO uint32_t CTRLDESCL3;                        /**< Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40 */
68363     __IO uint32_t CTRLDESCL4;                        /**< Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40 */
68364     __IO uint32_t CTRLDESCL5;                        /**< Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40 */
68365     __IO uint32_t CTRLDESCL6;                        /**< Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40 */
68366     __IO uint32_t CSC_COEF0;                         /**< Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances */
68367     __IO uint32_t CSC_COEF1;                         /**< Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances */
68368     __IO uint32_t CSC_COEF2;                         /**< Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances */
68369          uint8_t RESERVED_0[28];
68370   } LAYER[8];
68371   __IO uint32_t CLUT_LOAD;                         /**< LCDIFv2 CLUT load Register, offset: 0x400 */
68372 } LCDIFV2_Type;
68373 
68374 /* ----------------------------------------------------------------------------
68375    -- LCDIFV2 Register Masks
68376    ---------------------------------------------------------------------------- */
68377 
68378 /*!
68379  * @addtogroup LCDIFV2_Register_Masks LCDIFV2 Register Masks
68380  * @{
68381  */
68382 
68383 /*! @name CTRL - LCDIFv2 display control Register */
68384 /*! @{ */
68385 
68386 #define LCDIFV2_CTRL_INV_HS_MASK                 (0x1U)
68387 #define LCDIFV2_CTRL_INV_HS_SHIFT                (0U)
68388 /*! INV_HS - Invert Horizontal synchronization signal
68389  *  0b0..HSYNC signal not inverted (active HIGH)
68390  *  0b1..Invert HSYNC signal (active LOW)
68391  */
68392 #define LCDIFV2_CTRL_INV_HS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
68393 
68394 #define LCDIFV2_CTRL_INV_VS_MASK                 (0x2U)
68395 #define LCDIFV2_CTRL_INV_VS_SHIFT                (1U)
68396 /*! INV_VS - Invert Vertical synchronization signal
68397  *  0b0..VSYNC signal not inverted (active HIGH)
68398  *  0b1..Invert VSYNC signal (active LOW)
68399  */
68400 #define LCDIFV2_CTRL_INV_VS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
68401 
68402 #define LCDIFV2_CTRL_INV_DE_MASK                 (0x4U)
68403 #define LCDIFV2_CTRL_INV_DE_SHIFT                (2U)
68404 /*! INV_DE - Invert Data Enable polarity
68405  *  0b0..Data enable is active high
68406  *  0b1..Data enable is active low
68407  */
68408 #define LCDIFV2_CTRL_INV_DE(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
68409 
68410 #define LCDIFV2_CTRL_INV_PXCK_MASK               (0x8U)
68411 #define LCDIFV2_CTRL_INV_PXCK_SHIFT              (3U)
68412 /*! INV_PXCK - Polarity change of Pixel Clock
68413  *  0b0..Display samples data on the falling edge
68414  *  0b1..Display samples data on the rising edge
68415  */
68416 #define LCDIFV2_CTRL_INV_PXCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
68417 
68418 #define LCDIFV2_CTRL_NEG_MASK                    (0x10U)
68419 #define LCDIFV2_CTRL_NEG_SHIFT                   (4U)
68420 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
68421  *  0b0..Output is to remain same
68422  *  0b1..Output to be negated
68423  */
68424 #define LCDIFV2_CTRL_NEG(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
68425 
68426 #define LCDIFV2_CTRL_SW_RESET_MASK               (0x80000000U)
68427 #define LCDIFV2_CTRL_SW_RESET_SHIFT              (31U)
68428 /*! SW_RESET - Software Reset
68429  *  0b0..No action
68430  *  0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected
68431  */
68432 #define LCDIFV2_CTRL_SW_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)
68433 /*! @} */
68434 
68435 /*! @name CTRL_SET - LCDIFv2 display control Register */
68436 /*! @{ */
68437 
68438 #define LCDIFV2_CTRL_SET_INV_HS_MASK             (0x1U)
68439 #define LCDIFV2_CTRL_SET_INV_HS_SHIFT            (0U)
68440 /*! INV_HS - Invert Horizontal synchronization signal
68441  */
68442 #define LCDIFV2_CTRL_SET_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
68443 
68444 #define LCDIFV2_CTRL_SET_INV_VS_MASK             (0x2U)
68445 #define LCDIFV2_CTRL_SET_INV_VS_SHIFT            (1U)
68446 /*! INV_VS - Invert Vertical synchronization signal
68447  */
68448 #define LCDIFV2_CTRL_SET_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
68449 
68450 #define LCDIFV2_CTRL_SET_INV_DE_MASK             (0x4U)
68451 #define LCDIFV2_CTRL_SET_INV_DE_SHIFT            (2U)
68452 /*! INV_DE - Invert Data Enable polarity
68453  */
68454 #define LCDIFV2_CTRL_SET_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
68455 
68456 #define LCDIFV2_CTRL_SET_INV_PXCK_MASK           (0x8U)
68457 #define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT          (3U)
68458 /*! INV_PXCK - Polarity change of Pixel Clock
68459  */
68460 #define LCDIFV2_CTRL_SET_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
68461 
68462 #define LCDIFV2_CTRL_SET_NEG_MASK                (0x10U)
68463 #define LCDIFV2_CTRL_SET_NEG_SHIFT               (4U)
68464 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
68465  */
68466 #define LCDIFV2_CTRL_SET_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
68467 
68468 #define LCDIFV2_CTRL_SET_SW_RESET_MASK           (0x80000000U)
68469 #define LCDIFV2_CTRL_SET_SW_RESET_SHIFT          (31U)
68470 /*! SW_RESET - Software Reset
68471  */
68472 #define LCDIFV2_CTRL_SET_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)
68473 /*! @} */
68474 
68475 /*! @name CTRL_CLR - LCDIFv2 display control Register */
68476 /*! @{ */
68477 
68478 #define LCDIFV2_CTRL_CLR_INV_HS_MASK             (0x1U)
68479 #define LCDIFV2_CTRL_CLR_INV_HS_SHIFT            (0U)
68480 /*! INV_HS - Invert Horizontal synchronization signal
68481  */
68482 #define LCDIFV2_CTRL_CLR_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
68483 
68484 #define LCDIFV2_CTRL_CLR_INV_VS_MASK             (0x2U)
68485 #define LCDIFV2_CTRL_CLR_INV_VS_SHIFT            (1U)
68486 /*! INV_VS - Invert Vertical synchronization signal
68487  */
68488 #define LCDIFV2_CTRL_CLR_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
68489 
68490 #define LCDIFV2_CTRL_CLR_INV_DE_MASK             (0x4U)
68491 #define LCDIFV2_CTRL_CLR_INV_DE_SHIFT            (2U)
68492 /*! INV_DE - Invert Data Enable polarity
68493  */
68494 #define LCDIFV2_CTRL_CLR_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
68495 
68496 #define LCDIFV2_CTRL_CLR_INV_PXCK_MASK           (0x8U)
68497 #define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT          (3U)
68498 /*! INV_PXCK - Polarity change of Pixel Clock
68499  */
68500 #define LCDIFV2_CTRL_CLR_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
68501 
68502 #define LCDIFV2_CTRL_CLR_NEG_MASK                (0x10U)
68503 #define LCDIFV2_CTRL_CLR_NEG_SHIFT               (4U)
68504 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
68505  */
68506 #define LCDIFV2_CTRL_CLR_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
68507 
68508 #define LCDIFV2_CTRL_CLR_SW_RESET_MASK           (0x80000000U)
68509 #define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT          (31U)
68510 /*! SW_RESET - Software Reset
68511  */
68512 #define LCDIFV2_CTRL_CLR_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)
68513 /*! @} */
68514 
68515 /*! @name CTRL_TOG - LCDIFv2 display control Register */
68516 /*! @{ */
68517 
68518 #define LCDIFV2_CTRL_TOG_INV_HS_MASK             (0x1U)
68519 #define LCDIFV2_CTRL_TOG_INV_HS_SHIFT            (0U)
68520 /*! INV_HS - Invert Horizontal synchronization signal
68521  */
68522 #define LCDIFV2_CTRL_TOG_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
68523 
68524 #define LCDIFV2_CTRL_TOG_INV_VS_MASK             (0x2U)
68525 #define LCDIFV2_CTRL_TOG_INV_VS_SHIFT            (1U)
68526 /*! INV_VS - Invert Vertical synchronization signal
68527  */
68528 #define LCDIFV2_CTRL_TOG_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
68529 
68530 #define LCDIFV2_CTRL_TOG_INV_DE_MASK             (0x4U)
68531 #define LCDIFV2_CTRL_TOG_INV_DE_SHIFT            (2U)
68532 /*! INV_DE - Invert Data Enable polarity
68533  */
68534 #define LCDIFV2_CTRL_TOG_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
68535 
68536 #define LCDIFV2_CTRL_TOG_INV_PXCK_MASK           (0x8U)
68537 #define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT          (3U)
68538 /*! INV_PXCK - Polarity change of Pixel Clock
68539  */
68540 #define LCDIFV2_CTRL_TOG_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
68541 
68542 #define LCDIFV2_CTRL_TOG_NEG_MASK                (0x10U)
68543 #define LCDIFV2_CTRL_TOG_NEG_SHIFT               (4U)
68544 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
68545  */
68546 #define LCDIFV2_CTRL_TOG_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
68547 
68548 #define LCDIFV2_CTRL_TOG_SW_RESET_MASK           (0x80000000U)
68549 #define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT          (31U)
68550 /*! SW_RESET - Software Reset
68551  */
68552 #define LCDIFV2_CTRL_TOG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)
68553 /*! @} */
68554 
68555 /*! @name DISP_PARA - Display Parameter Register */
68556 /*! @{ */
68557 
68558 #define LCDIFV2_DISP_PARA_BGND_B_MASK            (0xFFU)
68559 #define LCDIFV2_DISP_PARA_BGND_B_SHIFT           (0U)
68560 /*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active
68561  */
68562 #define LCDIFV2_DISP_PARA_BGND_B(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
68563 
68564 #define LCDIFV2_DISP_PARA_BGND_G_MASK            (0xFF00U)
68565 #define LCDIFV2_DISP_PARA_BGND_G_SHIFT           (8U)
68566 /*! BGND_G - Green component of the default color displayed in the sectors where no layer is active
68567  */
68568 #define LCDIFV2_DISP_PARA_BGND_G(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
68569 
68570 #define LCDIFV2_DISP_PARA_BGND_R_MASK            (0xFF0000U)
68571 #define LCDIFV2_DISP_PARA_BGND_R_SHIFT           (16U)
68572 /*! BGND_R - Red component of the default color displayed in the sectors where no layer is active
68573  */
68574 #define LCDIFV2_DISP_PARA_BGND_R(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
68575 
68576 #define LCDIFV2_DISP_PARA_DISP_MODE_MASK         (0x3000000U)
68577 #define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT        (24U)
68578 /*! DISP_MODE - LCDIFv2 operating mode
68579  *  0b00..Normal mode. Panel content controlled by layer configuration
68580  *  0b01..Test Mode1(BGND Color Display)
68581  *  0b10..Test Mode2(Column Color Bar)
68582  *  0b11..Test Mode3(Row Color Bar)
68583  */
68584 #define LCDIFV2_DISP_PARA_DISP_MODE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
68585 
68586 #define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK      (0x1C000000U)
68587 #define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT     (26U)
68588 /*! LINE_PATTERN - LCDIFv2 line output order
68589  *  0b000..RGB
68590  *  0b001..RBG
68591  *  0b010..GBR
68592  *  0b011..GRB
68593  *  0b100..BRG
68594  *  0b101..BGR
68595  */
68596 #define LCDIFV2_DISP_PARA_LINE_PATTERN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
68597 
68598 #define LCDIFV2_DISP_PARA_DISP_ON_MASK           (0x80000000U)
68599 #define LCDIFV2_DISP_PARA_DISP_ON_SHIFT          (31U)
68600 /*! DISP_ON - Display panel On/Off mode
68601  *  0b0..Display Off
68602  *  0b1..Display On
68603  */
68604 #define LCDIFV2_DISP_PARA_DISP_ON(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)
68605 /*! @} */
68606 
68607 /*! @name DISP_SIZE - Display Size Register */
68608 /*! @{ */
68609 
68610 #define LCDIFV2_DISP_SIZE_DELTA_X_MASK           (0xFFFU)
68611 #define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT          (0U)
68612 /*! DELTA_X - Sets the display size horizontal resolution in pixels
68613  */
68614 #define LCDIFV2_DISP_SIZE_DELTA_X(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
68615 
68616 #define LCDIFV2_DISP_SIZE_DELTA_Y_MASK           (0xFFF0000U)
68617 #define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT          (16U)
68618 /*! DELTA_Y - Sets the display size vertical resolution in pixels
68619  */
68620 #define LCDIFV2_DISP_SIZE_DELTA_Y(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)
68621 /*! @} */
68622 
68623 /*! @name HSYN_PARA - Horizontal Sync Parameter Register */
68624 /*! @{ */
68625 
68626 #define LCDIFV2_HSYN_PARA_FP_H_MASK              (0x1FFU)
68627 #define LCDIFV2_HSYN_PARA_FP_H_SHIFT             (0U)
68628 /*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
68629  */
68630 #define LCDIFV2_HSYN_PARA_FP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
68631 
68632 #define LCDIFV2_HSYN_PARA_PW_H_MASK              (0xFF800U)
68633 #define LCDIFV2_HSYN_PARA_PW_H_SHIFT             (11U)
68634 /*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
68635  */
68636 #define LCDIFV2_HSYN_PARA_PW_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
68637 
68638 #define LCDIFV2_HSYN_PARA_BP_H_MASK              (0x7FC00000U)
68639 #define LCDIFV2_HSYN_PARA_BP_H_SHIFT             (22U)
68640 /*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
68641  */
68642 #define LCDIFV2_HSYN_PARA_BP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)
68643 /*! @} */
68644 
68645 /*! @name VSYN_PARA - Vertical Sync Parameter Register */
68646 /*! @{ */
68647 
68648 #define LCDIFV2_VSYN_PARA_FP_V_MASK              (0x1FFU)
68649 #define LCDIFV2_VSYN_PARA_FP_V_SHIFT             (0U)
68650 /*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
68651  */
68652 #define LCDIFV2_VSYN_PARA_FP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
68653 
68654 #define LCDIFV2_VSYN_PARA_PW_V_MASK              (0xFF800U)
68655 #define LCDIFV2_VSYN_PARA_PW_V_SHIFT             (11U)
68656 /*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
68657  */
68658 #define LCDIFV2_VSYN_PARA_PW_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
68659 
68660 #define LCDIFV2_VSYN_PARA_BP_V_MASK              (0x7FC00000U)
68661 #define LCDIFV2_VSYN_PARA_BP_V_SHIFT             (22U)
68662 /*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
68663  */
68664 #define LCDIFV2_VSYN_PARA_BP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)
68665 /*! @} */
68666 
68667 /*! @name INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 */
68668 /*! @{ */
68669 
68670 #define LCDIFV2_INT_STATUS_VSYNC_MASK            (0x1U)
68671 #define LCDIFV2_INT_STATUS_VSYNC_SHIFT           (0U)
68672 /*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
68673  *  0b0..VSYNC has not started
68674  *  0b1..VSYNC has started
68675  */
68676 #define LCDIFV2_INT_STATUS_VSYNC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
68677 
68678 #define LCDIFV2_INT_STATUS_UNDERRUN_MASK         (0x2U)
68679 #define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT        (1U)
68680 /*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition
68681  *  0b0..Output buffer not underrun
68682  *  0b1..Output buffer underrun
68683  */
68684 #define LCDIFV2_INT_STATUS_UNDERRUN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
68685 
68686 #define LCDIFV2_INT_STATUS_VS_BLANK_MASK         (0x4U)
68687 #define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT        (2U)
68688 /*! VS_BLANK - Interrupt flag to indicate vertical blanking period
68689  *  0b0..Vertical blanking period has not started
68690  *  0b1..Vertical blanking period has started
68691  */
68692 #define LCDIFV2_INT_STATUS_VS_BLANK(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
68693 
68694 #define LCDIFV2_INT_STATUS_DMA_ERR_MASK          (0xFF00U)
68695 #define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT         (8U)
68696 /*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
68697  */
68698 #define LCDIFV2_INT_STATUS_DMA_ERR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
68699 
68700 #define LCDIFV2_INT_STATUS_DMA_DONE_MASK         (0xFF0000U)
68701 #define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT        (16U)
68702 /*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
68703  */
68704 #define LCDIFV2_INT_STATUS_DMA_DONE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
68705 
68706 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK       (0xFF000000U)
68707 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT      (24U)
68708 /*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed
68709  */
68710 #define LCDIFV2_INT_STATUS_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)
68711 /*! @} */
68712 
68713 /* The count of LCDIFV2_INT_STATUS */
68714 #define LCDIFV2_INT_STATUS_COUNT                 (2U)
68715 
68716 /*! @name INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 */
68717 /*! @{ */
68718 
68719 #define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK         (0x1U)
68720 #define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT        (0U)
68721 /*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
68722  *  0b0..VSYNC interrupt disable
68723  *  0b1..VSYNC interrupt enable
68724  */
68725 #define LCDIFV2_INT_ENABLE_VSYNC_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
68726 
68727 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK      (0x2U)
68728 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT     (1U)
68729 /*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition
68730  *  0b0..Output buffer underrun disable
68731  *  0b1..Output buffer underrun enable
68732  */
68733 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
68734 
68735 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK      (0x4U)
68736 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT     (2U)
68737 /*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period
68738  *  0b0..Vertical blanking start interrupt disable
68739  *  0b1..Vertical blanking start interrupt enable
68740  */
68741 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
68742 
68743 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK       (0xFF00U)
68744 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT      (8U)
68745 /*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
68746  */
68747 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
68748 
68749 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK      (0xFF0000U)
68750 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT     (16U)
68751 /*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
68752  */
68753 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
68754 
68755 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK    (0xFF000000U)
68756 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
68757 /*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed
68758  */
68759 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)
68760 /*! @} */
68761 
68762 /* The count of LCDIFV2_INT_ENABLE */
68763 #define LCDIFV2_INT_ENABLE_COUNT                 (2U)
68764 
68765 /*! @name PDI_PARA - Parallel Data Interface Parameter Register */
68766 /*! @{ */
68767 
68768 #define LCDIFV2_PDI_PARA_INV_PDI_HS_MASK         (0x1U)
68769 #define LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT        (0U)
68770 /*! INV_PDI_HS - Polarity of PDI input HSYNC
68771  *  0b0..HSYNC is active HIGH
68772  *  0b1..HSYNC is active LOW
68773  */
68774 #define LCDIFV2_PDI_PARA_INV_PDI_HS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
68775 
68776 #define LCDIFV2_PDI_PARA_INV_PDI_VS_MASK         (0x2U)
68777 #define LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT        (1U)
68778 /*! INV_PDI_VS - Polarity of PDI input VSYNC
68779  *  0b0..VSYNC is active HIGH
68780  *  0b1..VSYNC is active LOW
68781  */
68782 #define LCDIFV2_PDI_PARA_INV_PDI_VS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
68783 
68784 #define LCDIFV2_PDI_PARA_INV_PDI_DE_MASK         (0x4U)
68785 #define LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT        (2U)
68786 /*! INV_PDI_DE - Polarity of PDI input Data Enable
68787  *  0b0..Data enable is active HIGH
68788  *  0b1..Data enable is active LOW
68789  */
68790 #define LCDIFV2_PDI_PARA_INV_PDI_DE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
68791 
68792 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK       (0x8U)
68793 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT      (3U)
68794 /*! INV_PDI_PXCK - Polarity of PDI input Pixel Clock
68795  *  0b0..Samples data on the falling edge
68796  *  0b1..Samples data on the rising edge
68797  */
68798 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
68799 
68800 #define LCDIFV2_PDI_PARA_MODE_MASK               (0xF0U)
68801 #define LCDIFV2_PDI_PARA_MODE_SHIFT              (4U)
68802 /*! MODE - The PDI mode for input data format
68803  *  0b0000..32 bpp (ARGB8888)
68804  *  0b0001..24 bpp (RGB888)
68805  *  0b0010..24 bpp (RGB666)
68806  *  0b0011..16 bpp (RGB565)
68807  *  0b0100..16 bpp (RGB444)
68808  *  0b0101..16 bpp (RGB555)
68809  *  0b0110..16 bpp (YCbCr422)
68810  */
68811 #define LCDIFV2_PDI_PARA_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
68812 
68813 #define LCDIFV2_PDI_PARA_PDI_SEL_MASK            (0x40000000U)
68814 #define LCDIFV2_PDI_PARA_PDI_SEL_SHIFT           (30U)
68815 /*! PDI_SEL - PDI selected on LCDIFv2 plane number
68816  *  0b0..PDI selected on LCDIFv2 plane 0
68817  *  0b1..PDI selected on LCDIFv2 plane 1
68818  */
68819 #define LCDIFV2_PDI_PARA_PDI_SEL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
68820 
68821 #define LCDIFV2_PDI_PARA_PDI_EN_MASK             (0x80000000U)
68822 #define LCDIFV2_PDI_PARA_PDI_EN_SHIFT            (31U)
68823 /*! PDI_EN - Enable PDI input data to LCDIFv2 display
68824  *  0b0..Disable PDI input data
68825  *  0b1..Enable PDI input data
68826  */
68827 #define LCDIFV2_PDI_PARA_PDI_EN(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)
68828 /*! @} */
68829 
68830 /*! @name CTRLDESCL1 - Control Descriptor Layer 1 Register */
68831 /*! @{ */
68832 
68833 #define LCDIFV2_CTRLDESCL1_WIDTH_MASK            (0xFFFU)
68834 #define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT           (0U)
68835 /*! WIDTH - Width of the layer in pixels
68836  */
68837 #define LCDIFV2_CTRLDESCL1_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
68838 
68839 #define LCDIFV2_CTRLDESCL1_HEIGHT_MASK           (0xFFF0000U)
68840 #define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT          (16U)
68841 /*! HEIGHT - Height of the layer in pixels
68842  */
68843 #define LCDIFV2_CTRLDESCL1_HEIGHT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)
68844 /*! @} */
68845 
68846 /* The count of LCDIFV2_CTRLDESCL1 */
68847 #define LCDIFV2_CTRLDESCL1_COUNT                 (8U)
68848 
68849 /*! @name CTRLDESCL2 - Control Descriptor Layer 2 Register */
68850 /*! @{ */
68851 
68852 #define LCDIFV2_CTRLDESCL2_POSX_MASK             (0xFFFU)
68853 #define LCDIFV2_CTRLDESCL2_POSX_SHIFT            (0U)
68854 /*! POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column
68855  *    of the panel, only positive values are to the right the left-hand column of the panel
68856  */
68857 #define LCDIFV2_CTRLDESCL2_POSX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
68858 
68859 #define LCDIFV2_CTRLDESCL2_POSY_MASK             (0xFFF0000U)
68860 #define LCDIFV2_CTRLDESCL2_POSY_SHIFT            (16U)
68861 /*! POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only
68862  *    positive values are below the top row of the panel
68863  */
68864 #define LCDIFV2_CTRLDESCL2_POSY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)
68865 /*! @} */
68866 
68867 /* The count of LCDIFV2_CTRLDESCL2 */
68868 #define LCDIFV2_CTRLDESCL2_COUNT                 (8U)
68869 
68870 /*! @name CTRLDESCL3 - Control Descriptor Layer 3 Register */
68871 /*! @{ */
68872 
68873 #define LCDIFV2_CTRLDESCL3_PITCH_MASK            (0xFFFFU)
68874 #define LCDIFV2_CTRLDESCL3_PITCH_SHIFT           (0U)
68875 /*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
68876  *    is supported, but SW should align to 64B boundry
68877  */
68878 #define LCDIFV2_CTRLDESCL3_PITCH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)
68879 /*! @} */
68880 
68881 /* The count of LCDIFV2_CTRLDESCL3 */
68882 #define LCDIFV2_CTRLDESCL3_COUNT                 (8U)
68883 
68884 /*! @name CTRLDESCL4 - Control Descriptor Layer 4 Register */
68885 /*! @{ */
68886 
68887 #define LCDIFV2_CTRLDESCL4_ADDR_MASK             (0xFFFFFFFFU)
68888 #define LCDIFV2_CTRLDESCL4_ADDR_SHIFT            (0U)
68889 /*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned
68890  */
68891 #define LCDIFV2_CTRLDESCL4_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)
68892 /*! @} */
68893 
68894 /* The count of LCDIFV2_CTRLDESCL4 */
68895 #define LCDIFV2_CTRLDESCL4_COUNT                 (8U)
68896 
68897 /*! @name CTRLDESCL5 - Control Descriptor Layer 5 Register */
68898 /*! @{ */
68899 
68900 #define LCDIFV2_CTRLDESCL5_AB_MODE_MASK          (0x3U)
68901 #define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT         (0U)
68902 /*! AB_MODE - Alpha Blending Mode
68903  *  0b00..No alpha Blending (The SAFETY_EN bit need set to 1)
68904  *  0b01..Blend with global ALPHA
68905  *  0b10..Blend with embedded ALPHA
68906  *  0b11..Blend with PoterDuff enable
68907  */
68908 #define LCDIFV2_CTRLDESCL5_AB_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
68909 
68910 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
68911 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT  (4U)
68912 /*! PD_FACTOR_MODE - PoterDuff factor mode
68913  *  0b00..Using 1
68914  *  0b01..Using 0
68915  *  0b10..Using straight alpha
68916  *  0b11..Using inverse alpha
68917  */
68918 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
68919 
68920 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U)
68921 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U)
68922 /*! PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode
68923  *  0b00..Using global alpha
68924  *  0b01..Using local alpha
68925  *  0b10..Using scaled alpha
68926  *  0b11..Using scaled alpha
68927  */
68928 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
68929 
68930 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK    (0x100U)
68931 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
68932 /*! PD_ALPHA_MODE - PoterDuff alpha mode
68933  *  0b0..Straight mode for Porter Duff alpha
68934  *  0b1..Inversed mode for Porter Duff alpha
68935  */
68936 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
68937 
68938 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK    (0x200U)
68939 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
68940 /*! PD_COLOR_MODE - PoterDuff alpha mode
68941  *  0b0..Straight mode for Porter Duff color
68942  *  0b1..Inversed mode for Porter Duff color
68943  */
68944 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
68945 
68946 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK       (0xC000U)
68947 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT      (14U)
68948 /*! YUV_FORMAT - The YUV422 input format selection
68949  *  0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2
68950  *  0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2
68951  *  0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1
68952  *  0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1
68953  */
68954 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
68955 
68956 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK     (0xFF0000U)
68957 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT    (16U)
68958 /*! GLOBAL_ALPHA - Global Alpha
68959  */
68960 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)       (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
68961 
68962 #define LCDIFV2_CTRLDESCL5_BPP_MASK              (0xF000000U)
68963 #define LCDIFV2_CTRLDESCL5_BPP_SHIFT             (24U)
68964 /*! BPP - Layer encoding format (bit per pixel)
68965  *  0b0000..1 bpp
68966  *  0b0001..2 bpp
68967  *  0b0010..4 bpp
68968  *  0b0011..8 bpp
68969  *  0b0100..16 bpp (RGB565)
68970  *  0b0101..16 bpp (ARGB1555)
68971  *  0b0110..16 bpp (ARGB4444)
68972  *  0b0111..YCbCr422 (Only layer 0/1 can support this format)
68973  *  0b1000..24 bpp (RGB888)
68974  *  0b1001..32 bpp (ARGB8888)
68975  *  0b1010..32 bpp (ABGR8888)
68976  */
68977 #define LCDIFV2_CTRLDESCL5_BPP(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
68978 
68979 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK        (0x10000000U)
68980 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT       (28U)
68981 /*! SAFETY_EN - Safety Mode Enable Bit
68982  *  0b0..Safety Mode is disabled
68983  *  0b1..Safety Mode is enabled for this layer
68984  */
68985 #define LCDIFV2_CTRLDESCL5_SAFETY_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
68986 
68987 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
68988 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT  (30U)
68989 /*! SHADOW_LOAD_EN - Shadow Load Enable
68990  */
68991 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
68992 
68993 #define LCDIFV2_CTRLDESCL5_EN_MASK               (0x80000000U)
68994 #define LCDIFV2_CTRLDESCL5_EN_SHIFT              (31U)
68995 /*! EN - Enable the layer for DMA
68996  *  0b0..OFF
68997  *  0b1..ON
68998  */
68999 #define LCDIFV2_CTRLDESCL5_EN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)
69000 /*! @} */
69001 
69002 /* The count of LCDIFV2_CTRLDESCL5 */
69003 #define LCDIFV2_CTRLDESCL5_COUNT                 (8U)
69004 
69005 /*! @name CTRLDESCL6 - Control Descriptor Layer 6 Register */
69006 /*! @{ */
69007 
69008 #define LCDIFV2_CTRLDESCL6_BCLR_B_MASK           (0xFFU)
69009 #define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT          (0U)
69010 /*! BCLR_B - Background B component value
69011  */
69012 #define LCDIFV2_CTRLDESCL6_BCLR_B(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
69013 
69014 #define LCDIFV2_CTRLDESCL6_BCLR_G_MASK           (0xFF00U)
69015 #define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT          (8U)
69016 /*! BCLR_G - Background G component value
69017  */
69018 #define LCDIFV2_CTRLDESCL6_BCLR_G(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
69019 
69020 #define LCDIFV2_CTRLDESCL6_BCLR_R_MASK           (0xFF0000U)
69021 #define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT          (16U)
69022 /*! BCLR_R - Background R component value
69023  */
69024 #define LCDIFV2_CTRLDESCL6_BCLR_R(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)
69025 /*! @} */
69026 
69027 /* The count of LCDIFV2_CTRLDESCL6 */
69028 #define LCDIFV2_CTRLDESCL6_COUNT                 (8U)
69029 
69030 /*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */
69031 /*! @{ */
69032 
69033 #define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK          (0x1FFU)
69034 #define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT         (0U)
69035 /*! Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically
69036  *    0 and for YCbCr, this is typically -16 (0x1F0)
69037  */
69038 #define LCDIFV2_CSC_COEF0_Y_OFFSET(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
69039 
69040 #define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK         (0x3FE00U)
69041 #define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT        (9U)
69042 /*! UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to
69043  *    RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to
69044  *    0.5 range)
69045  */
69046 #define LCDIFV2_CSC_COEF0_UV_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
69047 
69048 #define LCDIFV2_CSC_COEF0_C0_MASK                (0x1FFC0000U)
69049 #define LCDIFV2_CSC_COEF0_C0_SHIFT               (18U)
69050 /*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)
69051  */
69052 #define LCDIFV2_CSC_COEF0_C0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
69053 
69054 #define LCDIFV2_CSC_COEF0_ENABLE_MASK            (0x40000000U)
69055 #define LCDIFV2_CSC_COEF0_ENABLE_SHIFT           (30U)
69056 /*! ENABLE - Enable the CSC unit in the LCDIFv2 plane data path
69057  *  0b0..The CSC is bypassed and the input pixels are RGB data already
69058  *  0b1..The CSC is enabled and the pixels will be converted to RGB data
69059  */
69060 #define LCDIFV2_CSC_COEF0_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
69061 
69062 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK        (0x80000000U)
69063 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT       (31U)
69064 /*! YCBCR_MODE - This bit changes the behavior when performing U/V converting
69065  *  0b0..Converting YUV to RGB data
69066  *  0b1..Converting YCbCr to RGB data
69067  */
69068 #define LCDIFV2_CSC_COEF0_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)
69069 /*! @} */
69070 
69071 /* The count of LCDIFV2_CSC_COEF0 */
69072 #define LCDIFV2_CSC_COEF0_COUNT                  (8U)
69073 
69074 /*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */
69075 /*! @{ */
69076 
69077 #define LCDIFV2_CSC_COEF1_C4_MASK                (0x7FFU)
69078 #define LCDIFV2_CSC_COEF1_C4_SHIFT               (0U)
69079 /*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)
69080  */
69081 #define LCDIFV2_CSC_COEF1_C4(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
69082 
69083 #define LCDIFV2_CSC_COEF1_C1_MASK                (0x7FF0000U)
69084 #define LCDIFV2_CSC_COEF1_C1_SHIFT               (16U)
69085 /*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)
69086  */
69087 #define LCDIFV2_CSC_COEF1_C1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)
69088 /*! @} */
69089 
69090 /* The count of LCDIFV2_CSC_COEF1 */
69091 #define LCDIFV2_CSC_COEF1_COUNT                  (8U)
69092 
69093 /*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */
69094 /*! @{ */
69095 
69096 #define LCDIFV2_CSC_COEF2_C3_MASK                (0x7FFU)
69097 #define LCDIFV2_CSC_COEF2_C3_SHIFT               (0U)
69098 /*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)
69099  */
69100 #define LCDIFV2_CSC_COEF2_C3(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
69101 
69102 #define LCDIFV2_CSC_COEF2_C2_MASK                (0x7FF0000U)
69103 #define LCDIFV2_CSC_COEF2_C2_SHIFT               (16U)
69104 /*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)
69105  */
69106 #define LCDIFV2_CSC_COEF2_C2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)
69107 /*! @} */
69108 
69109 /* The count of LCDIFV2_CSC_COEF2 */
69110 #define LCDIFV2_CSC_COEF2_COUNT                  (8U)
69111 
69112 /*! @name CLUT_LOAD - LCDIFv2 CLUT load Register */
69113 /*! @{ */
69114 
69115 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK    (0x1U)
69116 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
69117 /*! CLUT_UPDATE_EN - CLUT Update Enable
69118  */
69119 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
69120 
69121 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK      (0x70U)
69122 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT     (4U)
69123 /*! SEL_CLUT_NUM - Selected CLUT Number
69124  */
69125 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)
69126 /*! @} */
69127 
69128 
69129 /*!
69130  * @}
69131  */ /* end of group LCDIFV2_Register_Masks */
69132 
69133 
69134 /* LCDIFV2 - Peripheral instance base addresses */
69135 /** Peripheral LCDIFV2 base address */
69136 #define LCDIFV2_BASE                             (0x40808000u)
69137 /** Peripheral LCDIFV2 base pointer */
69138 #define LCDIFV2                                  ((LCDIFV2_Type *)LCDIFV2_BASE)
69139 /** Array initializer of LCDIFV2 peripheral base addresses */
69140 #define LCDIFV2_BASE_ADDRS                       { LCDIFV2_BASE }
69141 /** Array initializer of LCDIFV2 peripheral base pointers */
69142 #define LCDIFV2_BASE_PTRS                        { LCDIFV2 }
69143 
69144 /*!
69145  * @}
69146  */ /* end of group LCDIFV2_Peripheral_Access_Layer */
69147 
69148 
69149 /* ----------------------------------------------------------------------------
69150    -- LMEM Peripheral Access Layer
69151    ---------------------------------------------------------------------------- */
69152 
69153 /*!
69154  * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
69155  * @{
69156  */
69157 
69158 /** LMEM - Register Layout Typedef */
69159 typedef struct {
69160   __IO uint32_t PCCCR;                             /**< PC bus Cache control register, offset: 0x0 */
69161   __IO uint32_t PCCLCR;                            /**< PC bus Cache line control register, offset: 0x4 */
69162   __IO uint32_t PCCSAR;                            /**< PC bus Cache search address register, offset: 0x8 */
69163   __IO uint32_t PCCCVR;                            /**< PC bus Cache read/write value register, offset: 0xC */
69164        uint8_t RESERVED_0[2032];
69165   __IO uint32_t PSCCR;                             /**< PS bus Cache control register, offset: 0x800 */
69166   __IO uint32_t PSCLCR;                            /**< PS bus Cache line control register, offset: 0x804 */
69167   __IO uint32_t PSCSAR;                            /**< PS bus Cache search address register, offset: 0x808 */
69168   __IO uint32_t PSCCVR;                            /**< PS bus Cache read/write value register, offset: 0x80C */
69169 } LMEM_Type;
69170 
69171 /* ----------------------------------------------------------------------------
69172    -- LMEM Register Masks
69173    ---------------------------------------------------------------------------- */
69174 
69175 /*!
69176  * @addtogroup LMEM_Register_Masks LMEM Register Masks
69177  * @{
69178  */
69179 
69180 /*! @name PCCCR - PC bus Cache control register */
69181 /*! @{ */
69182 
69183 #define LMEM_PCCCR_ENCACHE_MASK                  (0x1U)
69184 #define LMEM_PCCCR_ENCACHE_SHIFT                 (0U)
69185 /*! ENCACHE - Cache enable
69186  *  0b0..Cache disabled
69187  *  0b1..Cache enabled
69188  */
69189 #define LMEM_PCCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
69190 
69191 #define LMEM_PCCCR_ENWRBUF_MASK                  (0x2U)
69192 #define LMEM_PCCCR_ENWRBUF_SHIFT                 (1U)
69193 /*! ENWRBUF - Enable Write Buffer
69194  *  0b0..Write buffer disabled
69195  *  0b1..Write buffer enabled
69196  */
69197 #define LMEM_PCCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
69198 
69199 #define LMEM_PCCCR_PCCR2_MASK                    (0x4U)
69200 #define LMEM_PCCCR_PCCR2_SHIFT                   (2U)
69201 /*! PCCR2 - Forces all cacheable spaces to write through
69202  *  0b0..Does NOT force all cacheable spaces to write through
69203  *  0b1..Forces all cacheable spaces to write through
69204  */
69205 #define LMEM_PCCCR_PCCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
69206 
69207 #define LMEM_PCCCR_PCCR3_MASK                    (0x8U)
69208 #define LMEM_PCCCR_PCCR3_SHIFT                   (3U)
69209 /*! PCCR3 - Forces no allocation on cache misses
69210  *  0b0..Allocation on cache misses
69211  *  0b1..Forces no allocation on cache misses (must also have PCCR2 asserted)
69212  */
69213 #define LMEM_PCCCR_PCCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
69214 
69215 #define LMEM_PCCCR_INVW0_MASK                    (0x1000000U)
69216 #define LMEM_PCCCR_INVW0_SHIFT                   (24U)
69217 /*! INVW0 - Invalidate Way 0
69218  *  0b0..No operation
69219  *  0b1..When setting the GO bit, invalidate all lines in way 0.
69220  */
69221 #define LMEM_PCCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
69222 
69223 #define LMEM_PCCCR_PUSHW0_MASK                   (0x2000000U)
69224 #define LMEM_PCCCR_PUSHW0_SHIFT                  (25U)
69225 /*! PUSHW0 - Push Way 0
69226  *  0b0..No operation
69227  *  0b1..When setting the GO bit, push all modified lines in way 0
69228  */
69229 #define LMEM_PCCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
69230 
69231 #define LMEM_PCCCR_INVW1_MASK                    (0x4000000U)
69232 #define LMEM_PCCCR_INVW1_SHIFT                   (26U)
69233 /*! INVW1 - Invalidate Way 1
69234  *  0b0..No operation
69235  *  0b1..When setting the GO bit, invalidate all lines in way 1
69236  */
69237 #define LMEM_PCCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
69238 
69239 #define LMEM_PCCCR_PUSHW1_MASK                   (0x8000000U)
69240 #define LMEM_PCCCR_PUSHW1_SHIFT                  (27U)
69241 /*! PUSHW1 - Push Way 1
69242  *  0b0..No operation
69243  *  0b1..When setting the GO bit, push all modified lines in way 1
69244  */
69245 #define LMEM_PCCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
69246 
69247 #define LMEM_PCCCR_GO_MASK                       (0x80000000U)
69248 #define LMEM_PCCCR_GO_SHIFT                      (31U)
69249 /*! GO - Initiate Cache Command
69250  *  0b0..Write: no effect. Read: no cache command active.
69251  *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
69252  */
69253 #define LMEM_PCCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
69254 /*! @} */
69255 
69256 /*! @name PCCLCR - PC bus Cache line control register */
69257 /*! @{ */
69258 
69259 #define LMEM_PCCLCR_LGO_MASK                     (0x1U)
69260 #define LMEM_PCCLCR_LGO_SHIFT                    (0U)
69261 /*! LGO - Initiate Cache Line Command
69262  *  0b0..Write: no effect. Read: no line command active.
69263  *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
69264  */
69265 #define LMEM_PCCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
69266 
69267 #define LMEM_PCCLCR_CACHEADDR_MASK               (0x3FFCU)
69268 #define LMEM_PCCLCR_CACHEADDR_SHIFT              (2U)
69269 /*! CACHEADDR - Cache address
69270  */
69271 #define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
69272 
69273 #define LMEM_PCCLCR_WSEL_MASK                    (0x4000U)
69274 #define LMEM_PCCLCR_WSEL_SHIFT                   (14U)
69275 /*! WSEL - Way select
69276  *  0b0..Way 0
69277  *  0b1..Way 1
69278  */
69279 #define LMEM_PCCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
69280 
69281 #define LMEM_PCCLCR_TDSEL_MASK                   (0x10000U)
69282 #define LMEM_PCCLCR_TDSEL_SHIFT                  (16U)
69283 /*! TDSEL - Tag/Data Select
69284  *  0b0..Data
69285  *  0b1..Tag
69286  */
69287 #define LMEM_PCCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
69288 
69289 #define LMEM_PCCLCR_LCIVB_MASK                   (0x100000U)
69290 #define LMEM_PCCLCR_LCIVB_SHIFT                  (20U)
69291 /*! LCIVB - Line Command Initial Valid Bit
69292  */
69293 #define LMEM_PCCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
69294 
69295 #define LMEM_PCCLCR_LCIMB_MASK                   (0x200000U)
69296 #define LMEM_PCCLCR_LCIMB_SHIFT                  (21U)
69297 /*! LCIMB - Line Command Initial Modified Bit
69298  */
69299 #define LMEM_PCCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
69300 
69301 #define LMEM_PCCLCR_LCWAY_MASK                   (0x400000U)
69302 #define LMEM_PCCLCR_LCWAY_SHIFT                  (22U)
69303 /*! LCWAY - Line Command Way
69304  */
69305 #define LMEM_PCCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
69306 
69307 #define LMEM_PCCLCR_LCMD_MASK                    (0x3000000U)
69308 #define LMEM_PCCLCR_LCMD_SHIFT                   (24U)
69309 /*! LCMD - Line Command
69310  *  0b00..Search and read or write
69311  *  0b01..Invalidate
69312  *  0b10..Push
69313  *  0b11..Clear
69314  */
69315 #define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
69316 
69317 #define LMEM_PCCLCR_LADSEL_MASK                  (0x4000000U)
69318 #define LMEM_PCCLCR_LADSEL_SHIFT                 (26U)
69319 /*! LADSEL - Line Address Select
69320  *  0b0..Cache address
69321  *  0b1..Physical address
69322  */
69323 #define LMEM_PCCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
69324 
69325 #define LMEM_PCCLCR_LACC_MASK                    (0x8000000U)
69326 #define LMEM_PCCLCR_LACC_SHIFT                   (27U)
69327 /*! LACC - Line access type
69328  *  0b0..Read
69329  *  0b1..Write
69330  */
69331 #define LMEM_PCCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
69332 /*! @} */
69333 
69334 /*! @name PCCSAR - PC bus Cache search address register */
69335 /*! @{ */
69336 
69337 #define LMEM_PCCSAR_LGO_MASK                     (0x1U)
69338 #define LMEM_PCCSAR_LGO_SHIFT                    (0U)
69339 /*! LGO - Initiate Cache Line Command
69340  *  0b0..Write: no effect. Read: no line command active.
69341  *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
69342  */
69343 #define LMEM_PCCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
69344 
69345 #define LMEM_PCCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
69346 #define LMEM_PCCSAR_PHYADDR_SHIFT                (1U)
69347 /*! PHYADDR - Physical Address
69348  */
69349 #define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
69350 /*! @} */
69351 
69352 /*! @name PCCCVR - PC bus Cache read/write value register */
69353 /*! @{ */
69354 
69355 #define LMEM_PCCCVR_DATA_MASK                    (0xFFFFFFFFU)
69356 #define LMEM_PCCCVR_DATA_SHIFT                   (0U)
69357 /*! DATA - Cache read/write Data
69358  */
69359 #define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
69360 /*! @} */
69361 
69362 /*! @name PSCCR - PS bus Cache control register */
69363 /*! @{ */
69364 
69365 #define LMEM_PSCCR_ENCACHE_MASK                  (0x1U)
69366 #define LMEM_PSCCR_ENCACHE_SHIFT                 (0U)
69367 /*! ENCACHE - Cache enable
69368  *  0b0..Cache disabled
69369  *  0b1..Cache enabled
69370  */
69371 #define LMEM_PSCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
69372 
69373 #define LMEM_PSCCR_ENWRBUF_MASK                  (0x2U)
69374 #define LMEM_PSCCR_ENWRBUF_SHIFT                 (1U)
69375 /*! ENWRBUF - Enable Write Buffer
69376  *  0b0..Write buffer disabled
69377  *  0b1..Write buffer enabled
69378  */
69379 #define LMEM_PSCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
69380 
69381 #define LMEM_PSCCR_PSCR2_MASK                    (0x4U)
69382 #define LMEM_PSCCR_PSCR2_SHIFT                   (2U)
69383 /*! PSCR2 - Forces all cacheable spaces to write through
69384  *  0b0..Does NOT force all cacheable spaces to write through
69385  *  0b1..Forces all cacheable spaces to write through
69386  */
69387 #define LMEM_PSCCR_PSCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR2_SHIFT)) & LMEM_PSCCR_PSCR2_MASK)
69388 
69389 #define LMEM_PSCCR_PSCR3_MASK                    (0x8U)
69390 #define LMEM_PSCCR_PSCR3_SHIFT                   (3U)
69391 /*! PSCR3 - Forces no allocation on cache misses
69392  *  0b0..Allocation on cache misses
69393  *  0b1..Forces no allocation on cache misses (must also have PSCR2 asserted)
69394  */
69395 #define LMEM_PSCCR_PSCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR3_SHIFT)) & LMEM_PSCCR_PSCR3_MASK)
69396 
69397 #define LMEM_PSCCR_INVW0_MASK                    (0x1000000U)
69398 #define LMEM_PSCCR_INVW0_SHIFT                   (24U)
69399 /*! INVW0 - Invalidate Way 0
69400  *  0b0..No operation
69401  *  0b1..When setting the GO bit, invalidate all lines in way 0.
69402  */
69403 #define LMEM_PSCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
69404 
69405 #define LMEM_PSCCR_PUSHW0_MASK                   (0x2000000U)
69406 #define LMEM_PSCCR_PUSHW0_SHIFT                  (25U)
69407 /*! PUSHW0 - Push Way 0
69408  *  0b0..No operation
69409  *  0b1..When setting the GO bit, push all modified lines in way 0
69410  */
69411 #define LMEM_PSCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
69412 
69413 #define LMEM_PSCCR_INVW1_MASK                    (0x4000000U)
69414 #define LMEM_PSCCR_INVW1_SHIFT                   (26U)
69415 /*! INVW1 - Invalidate Way 1
69416  *  0b0..No operation
69417  *  0b1..When setting the GO bit, invalidate all lines in way 1
69418  */
69419 #define LMEM_PSCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
69420 
69421 #define LMEM_PSCCR_PUSHW1_MASK                   (0x8000000U)
69422 #define LMEM_PSCCR_PUSHW1_SHIFT                  (27U)
69423 /*! PUSHW1 - Push Way 1
69424  *  0b0..No operation
69425  *  0b1..When setting the GO bit, push all modified lines in way 1
69426  */
69427 #define LMEM_PSCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
69428 
69429 #define LMEM_PSCCR_GO_MASK                       (0x80000000U)
69430 #define LMEM_PSCCR_GO_SHIFT                      (31U)
69431 /*! GO - Initiate Cache Command
69432  *  0b0..Write: no effect. Read: no cache command active.
69433  *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
69434  */
69435 #define LMEM_PSCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
69436 /*! @} */
69437 
69438 /*! @name PSCLCR - PS bus Cache line control register */
69439 /*! @{ */
69440 
69441 #define LMEM_PSCLCR_LGO_MASK                     (0x1U)
69442 #define LMEM_PSCLCR_LGO_SHIFT                    (0U)
69443 /*! LGO - Initiate Cache Line Command
69444  *  0b0..Write: no effect. Read: no line command active.
69445  *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
69446  */
69447 #define LMEM_PSCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
69448 
69449 #define LMEM_PSCLCR_CACHEADDR_MASK               (0x3FFCU)
69450 #define LMEM_PSCLCR_CACHEADDR_SHIFT              (2U)
69451 /*! CACHEADDR - Cache address
69452  */
69453 #define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
69454 
69455 #define LMEM_PSCLCR_WSEL_MASK                    (0x4000U)
69456 #define LMEM_PSCLCR_WSEL_SHIFT                   (14U)
69457 /*! WSEL - Way select
69458  *  0b0..Way 0
69459  *  0b1..Way 1
69460  */
69461 #define LMEM_PSCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
69462 
69463 #define LMEM_PSCLCR_TDSEL_MASK                   (0x10000U)
69464 #define LMEM_PSCLCR_TDSEL_SHIFT                  (16U)
69465 /*! TDSEL - Tag/Data Select
69466  *  0b0..Data
69467  *  0b1..Tag
69468  */
69469 #define LMEM_PSCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
69470 
69471 #define LMEM_PSCLCR_LCIVB_MASK                   (0x100000U)
69472 #define LMEM_PSCLCR_LCIVB_SHIFT                  (20U)
69473 /*! LCIVB - Line Command Initial Valid Bit
69474  */
69475 #define LMEM_PSCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
69476 
69477 #define LMEM_PSCLCR_LCIMB_MASK                   (0x200000U)
69478 #define LMEM_PSCLCR_LCIMB_SHIFT                  (21U)
69479 /*! LCIMB - Line Command Initial Modified Bit
69480  */
69481 #define LMEM_PSCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
69482 
69483 #define LMEM_PSCLCR_LCWAY_MASK                   (0x400000U)
69484 #define LMEM_PSCLCR_LCWAY_SHIFT                  (22U)
69485 /*! LCWAY - Line Command Way
69486  */
69487 #define LMEM_PSCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
69488 
69489 #define LMEM_PSCLCR_LCMD_MASK                    (0x3000000U)
69490 #define LMEM_PSCLCR_LCMD_SHIFT                   (24U)
69491 /*! LCMD - Line Command
69492  *  0b00..Search and read or write
69493  *  0b01..Invalidate
69494  *  0b10..Push
69495  *  0b11..Clear
69496  */
69497 #define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
69498 
69499 #define LMEM_PSCLCR_LADSEL_MASK                  (0x4000000U)
69500 #define LMEM_PSCLCR_LADSEL_SHIFT                 (26U)
69501 /*! LADSEL - Line Address Select
69502  *  0b0..Cache address
69503  *  0b1..Physical address
69504  */
69505 #define LMEM_PSCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
69506 
69507 #define LMEM_PSCLCR_LACC_MASK                    (0x8000000U)
69508 #define LMEM_PSCLCR_LACC_SHIFT                   (27U)
69509 /*! LACC - Line access type
69510  *  0b0..Read
69511  *  0b1..Write
69512  */
69513 #define LMEM_PSCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
69514 /*! @} */
69515 
69516 /*! @name PSCSAR - PS bus Cache search address register */
69517 /*! @{ */
69518 
69519 #define LMEM_PSCSAR_LGO_MASK                     (0x1U)
69520 #define LMEM_PSCSAR_LGO_SHIFT                    (0U)
69521 /*! LGO - Initiate Cache Line Command
69522  *  0b0..Write: no effect. Read: no line command active.
69523  *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
69524  */
69525 #define LMEM_PSCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
69526 
69527 #define LMEM_PSCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
69528 #define LMEM_PSCSAR_PHYADDR_SHIFT                (1U)
69529 /*! PHYADDR - Physical Address
69530  */
69531 #define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
69532 /*! @} */
69533 
69534 /*! @name PSCCVR - PS bus Cache read/write value register */
69535 /*! @{ */
69536 
69537 #define LMEM_PSCCVR_DATA_MASK                    (0xFFFFFFFFU)
69538 #define LMEM_PSCCVR_DATA_SHIFT                   (0U)
69539 /*! DATA - Cache read/write Data
69540  */
69541 #define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
69542 /*! @} */
69543 
69544 
69545 /*!
69546  * @}
69547  */ /* end of group LMEM_Register_Masks */
69548 
69549 
69550 /* LMEM - Peripheral instance base addresses */
69551 /** Peripheral LMEM base address */
69552 #define LMEM_BASE                                (0xE0082000u)
69553 /** Peripheral LMEM base pointer */
69554 #define LMEM                                     ((LMEM_Type *)LMEM_BASE)
69555 /** Array initializer of LMEM peripheral base addresses */
69556 #define LMEM_BASE_ADDRS                          { LMEM_BASE }
69557 /** Array initializer of LMEM peripheral base pointers */
69558 #define LMEM_BASE_PTRS                           { LMEM }
69559 
69560 /*!
69561  * @}
69562  */ /* end of group LMEM_Peripheral_Access_Layer */
69563 
69564 
69565 /* ----------------------------------------------------------------------------
69566    -- LPI2C Peripheral Access Layer
69567    ---------------------------------------------------------------------------- */
69568 
69569 /*!
69570  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
69571  * @{
69572  */
69573 
69574 /** LPI2C - Register Layout Typedef */
69575 typedef struct {
69576   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
69577   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
69578        uint8_t RESERVED_0[8];
69579   __IO uint32_t MCR;                               /**< Master Control, offset: 0x10 */
69580   __IO uint32_t MSR;                               /**< Master Status, offset: 0x14 */
69581   __IO uint32_t MIER;                              /**< Master Interrupt Enable, offset: 0x18 */
69582   __IO uint32_t MDER;                              /**< Master DMA Enable, offset: 0x1C */
69583   __IO uint32_t MCFGR0;                            /**< Master Configuration 0, offset: 0x20 */
69584   __IO uint32_t MCFGR1;                            /**< Master Configuration 1, offset: 0x24 */
69585   __IO uint32_t MCFGR2;                            /**< Master Configuration 2, offset: 0x28 */
69586   __IO uint32_t MCFGR3;                            /**< Master Configuration 3, offset: 0x2C */
69587        uint8_t RESERVED_1[16];
69588   __IO uint32_t MDMR;                              /**< Master Data Match, offset: 0x40 */
69589        uint8_t RESERVED_2[4];
69590   __IO uint32_t MCCR0;                             /**< Master Clock Configuration 0, offset: 0x48 */
69591        uint8_t RESERVED_3[4];
69592   __IO uint32_t MCCR1;                             /**< Master Clock Configuration 1, offset: 0x50 */
69593        uint8_t RESERVED_4[4];
69594   __IO uint32_t MFCR;                              /**< Master FIFO Control, offset: 0x58 */
69595   __I  uint32_t MFSR;                              /**< Master FIFO Status, offset: 0x5C */
69596   __O  uint32_t MTDR;                              /**< Master Transmit Data, offset: 0x60 */
69597        uint8_t RESERVED_5[12];
69598   __I  uint32_t MRDR;                              /**< Master Receive Data, offset: 0x70 */
69599        uint8_t RESERVED_6[156];
69600   __IO uint32_t SCR;                               /**< Slave Control, offset: 0x110 */
69601   __IO uint32_t SSR;                               /**< Slave Status, offset: 0x114 */
69602   __IO uint32_t SIER;                              /**< Slave Interrupt Enable, offset: 0x118 */
69603   __IO uint32_t SDER;                              /**< Slave DMA Enable, offset: 0x11C */
69604        uint8_t RESERVED_7[4];
69605   __IO uint32_t SCFGR1;                            /**< Slave Configuration 1, offset: 0x124 */
69606   __IO uint32_t SCFGR2;                            /**< Slave Configuration 2, offset: 0x128 */
69607        uint8_t RESERVED_8[20];
69608   __IO uint32_t SAMR;                              /**< Slave Address Match, offset: 0x140 */
69609        uint8_t RESERVED_9[12];
69610   __I  uint32_t SASR;                              /**< Slave Address Status, offset: 0x150 */
69611   __IO uint32_t STAR;                              /**< Slave Transmit ACK, offset: 0x154 */
69612        uint8_t RESERVED_10[8];
69613   __O  uint32_t STDR;                              /**< Slave Transmit Data, offset: 0x160 */
69614        uint8_t RESERVED_11[12];
69615   __I  uint32_t SRDR;                              /**< Slave Receive Data, offset: 0x170 */
69616 } LPI2C_Type;
69617 
69618 /* ----------------------------------------------------------------------------
69619    -- LPI2C Register Masks
69620    ---------------------------------------------------------------------------- */
69621 
69622 /*!
69623  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
69624  * @{
69625  */
69626 
69627 /*! @name VERID - Version ID */
69628 /*! @{ */
69629 
69630 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
69631 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
69632 /*! FEATURE - Feature Specification Number
69633  *  0b0000000000000010..Master only, with standard feature set
69634  *  0b0000000000000011..Master and slave, with standard feature set
69635  */
69636 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
69637 
69638 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
69639 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
69640 /*! MINOR - Minor Version Number
69641  */
69642 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
69643 
69644 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
69645 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
69646 /*! MAJOR - Major Version Number
69647  */
69648 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
69649 /*! @} */
69650 
69651 /*! @name PARAM - Parameter */
69652 /*! @{ */
69653 
69654 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
69655 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
69656 /*! MTXFIFO - Master Transmit FIFO Size
69657  */
69658 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
69659 
69660 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
69661 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
69662 /*! MRXFIFO - Master Receive FIFO Size
69663  */
69664 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
69665 /*! @} */
69666 
69667 /*! @name MCR - Master Control */
69668 /*! @{ */
69669 
69670 #define LPI2C_MCR_MEN_MASK                       (0x1U)
69671 #define LPI2C_MCR_MEN_SHIFT                      (0U)
69672 /*! MEN - Master Enable
69673  *  0b0..Master logic is disabled
69674  *  0b1..Master logic is enabled
69675  */
69676 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
69677 
69678 #define LPI2C_MCR_RST_MASK                       (0x2U)
69679 #define LPI2C_MCR_RST_SHIFT                      (1U)
69680 /*! RST - Software Reset
69681  *  0b0..Master logic is not reset
69682  *  0b1..Master logic is reset
69683  */
69684 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
69685 
69686 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
69687 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
69688 /*! DOZEN - Doze mode enable
69689  *  0b0..Master is enabled in Doze mode
69690  *  0b1..Master is disabled in Doze mode
69691  */
69692 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
69693 
69694 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
69695 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
69696 /*! DBGEN - Debug Enable
69697  *  0b0..Master is disabled in debug mode
69698  *  0b1..Master is enabled in debug mode
69699  */
69700 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
69701 
69702 #define LPI2C_MCR_RTF_MASK                       (0x100U)
69703 #define LPI2C_MCR_RTF_SHIFT                      (8U)
69704 /*! RTF - Reset Transmit FIFO
69705  *  0b0..No effect
69706  *  0b1..Transmit FIFO is reset
69707  */
69708 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
69709 
69710 #define LPI2C_MCR_RRF_MASK                       (0x200U)
69711 #define LPI2C_MCR_RRF_SHIFT                      (9U)
69712 /*! RRF - Reset Receive FIFO
69713  *  0b0..No effect
69714  *  0b1..Receive FIFO is reset
69715  */
69716 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
69717 /*! @} */
69718 
69719 /*! @name MSR - Master Status */
69720 /*! @{ */
69721 
69722 #define LPI2C_MSR_TDF_MASK                       (0x1U)
69723 #define LPI2C_MSR_TDF_SHIFT                      (0U)
69724 /*! TDF - Transmit Data Flag
69725  *  0b0..Transmit data is not requested
69726  *  0b1..Transmit data is requested
69727  */
69728 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
69729 
69730 #define LPI2C_MSR_RDF_MASK                       (0x2U)
69731 #define LPI2C_MSR_RDF_SHIFT                      (1U)
69732 /*! RDF - Receive Data Flag
69733  *  0b0..Receive Data is not ready
69734  *  0b1..Receive data is ready
69735  */
69736 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
69737 
69738 #define LPI2C_MSR_EPF_MASK                       (0x100U)
69739 #define LPI2C_MSR_EPF_SHIFT                      (8U)
69740 /*! EPF - End Packet Flag
69741  *  0b0..Master has not generated a STOP or Repeated START condition
69742  *  0b1..Master has generated a STOP or Repeated START condition
69743  */
69744 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
69745 
69746 #define LPI2C_MSR_SDF_MASK                       (0x200U)
69747 #define LPI2C_MSR_SDF_SHIFT                      (9U)
69748 /*! SDF - STOP Detect Flag
69749  *  0b0..Master has not generated a STOP condition
69750  *  0b1..Master has generated a STOP condition
69751  */
69752 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
69753 
69754 #define LPI2C_MSR_NDF_MASK                       (0x400U)
69755 #define LPI2C_MSR_NDF_SHIFT                      (10U)
69756 /*! NDF - NACK Detect Flag
69757  *  0b0..Unexpected NACK was not detected
69758  *  0b1..Unexpected NACK was detected
69759  */
69760 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
69761 
69762 #define LPI2C_MSR_ALF_MASK                       (0x800U)
69763 #define LPI2C_MSR_ALF_SHIFT                      (11U)
69764 /*! ALF - Arbitration Lost Flag
69765  *  0b0..Master has not lost arbitration
69766  *  0b1..Master has lost arbitration
69767  */
69768 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
69769 
69770 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
69771 #define LPI2C_MSR_FEF_SHIFT                      (12U)
69772 /*! FEF - FIFO Error Flag
69773  *  0b0..No error
69774  *  0b1..Master sending or receiving data without a START condition
69775  */
69776 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
69777 
69778 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
69779 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
69780 /*! PLTF - Pin Low Timeout Flag
69781  *  0b0..Pin low timeout has not occurred or is disabled
69782  *  0b1..Pin low timeout has occurred
69783  */
69784 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
69785 
69786 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
69787 #define LPI2C_MSR_DMF_SHIFT                      (14U)
69788 /*! DMF - Data Match Flag
69789  *  0b0..Have not received matching data
69790  *  0b1..Have received matching data
69791  */
69792 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
69793 
69794 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
69795 #define LPI2C_MSR_MBF_SHIFT                      (24U)
69796 /*! MBF - Master Busy Flag
69797  *  0b0..I2C Master is idle
69798  *  0b1..I2C Master is busy
69799  */
69800 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
69801 
69802 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
69803 #define LPI2C_MSR_BBF_SHIFT                      (25U)
69804 /*! BBF - Bus Busy Flag
69805  *  0b0..I2C Bus is idle
69806  *  0b1..I2C Bus is busy
69807  */
69808 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
69809 /*! @} */
69810 
69811 /*! @name MIER - Master Interrupt Enable */
69812 /*! @{ */
69813 
69814 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
69815 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
69816 /*! TDIE - Transmit Data Interrupt Enable
69817  *  0b0..Disabled
69818  *  0b1..Enabled
69819  */
69820 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
69821 
69822 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
69823 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
69824 /*! RDIE - Receive Data Interrupt Enable
69825  *  0b0..Disabled
69826  *  0b1..Enabled
69827  */
69828 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
69829 
69830 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
69831 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
69832 /*! EPIE - End Packet Interrupt Enable
69833  *  0b0..Disabled
69834  *  0b1..Enabled
69835  */
69836 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
69837 
69838 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
69839 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
69840 /*! SDIE - STOP Detect Interrupt Enable
69841  *  0b0..Disabled
69842  *  0b1..Enabled
69843  */
69844 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
69845 
69846 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
69847 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
69848 /*! NDIE - NACK Detect Interrupt Enable
69849  *  0b0..Disabled
69850  *  0b1..Enabled
69851  */
69852 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
69853 
69854 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
69855 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
69856 /*! ALIE - Arbitration Lost Interrupt Enable
69857  *  0b0..Disabled
69858  *  0b1..Enabled
69859  */
69860 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
69861 
69862 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
69863 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
69864 /*! FEIE - FIFO Error Interrupt Enable
69865  *  0b0..Enabled
69866  *  0b1..Disabled
69867  */
69868 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
69869 
69870 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
69871 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
69872 /*! PLTIE - Pin Low Timeout Interrupt Enable
69873  *  0b0..Disabled
69874  *  0b1..Enabled
69875  */
69876 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
69877 
69878 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
69879 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
69880 /*! DMIE - Data Match Interrupt Enable
69881  *  0b0..Disabled
69882  *  0b1..Enabled
69883  */
69884 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
69885 /*! @} */
69886 
69887 /*! @name MDER - Master DMA Enable */
69888 /*! @{ */
69889 
69890 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
69891 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
69892 /*! TDDE - Transmit Data DMA Enable
69893  *  0b0..DMA request is disabled
69894  *  0b1..DMA request is enabled
69895  */
69896 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
69897 
69898 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
69899 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
69900 /*! RDDE - Receive Data DMA Enable
69901  *  0b0..DMA request is disabled
69902  *  0b1..DMA request is enabled
69903  */
69904 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
69905 /*! @} */
69906 
69907 /*! @name MCFGR0 - Master Configuration 0 */
69908 /*! @{ */
69909 
69910 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
69911 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
69912 /*! HREN - Host Request Enable
69913  *  0b0..Host request input is disabled
69914  *  0b1..Host request input is enabled
69915  */
69916 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
69917 
69918 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
69919 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
69920 /*! HRPOL - Host Request Polarity
69921  *  0b0..Active low
69922  *  0b1..Active high
69923  */
69924 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
69925 
69926 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
69927 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
69928 /*! HRSEL - Host Request Select
69929  *  0b0..Host request input is pin HREQ
69930  *  0b1..Host request input is input trigger
69931  */
69932 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
69933 
69934 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
69935 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
69936 /*! CIRFIFO - Circular FIFO Enable
69937  *  0b0..Circular FIFO is disabled
69938  *  0b1..Circular FIFO is enabled
69939  */
69940 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
69941 
69942 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
69943 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
69944 /*! RDMO - Receive Data Match Only
69945  *  0b0..Received data is stored in the receive FIFO
69946  *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
69947  */
69948 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
69949 /*! @} */
69950 
69951 /*! @name MCFGR1 - Master Configuration 1 */
69952 /*! @{ */
69953 
69954 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
69955 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
69956 /*! PRESCALE - Prescaler
69957  *  0b000..Divide by 1
69958  *  0b001..Divide by 2
69959  *  0b010..Divide by 4
69960  *  0b011..Divide by 8
69961  *  0b100..Divide by 16
69962  *  0b101..Divide by 32
69963  *  0b110..Divide by 64
69964  *  0b111..Divide by 128
69965  */
69966 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
69967 
69968 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
69969 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
69970 /*! AUTOSTOP - Automatic STOP Generation
69971  *  0b0..No effect
69972  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
69973  */
69974 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
69975 
69976 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
69977 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
69978 /*! IGNACK - IGNACK
69979  *  0b0..LPI2C Master receives ACK and NACK normally
69980  *  0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK
69981  */
69982 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
69983 
69984 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
69985 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
69986 /*! TIMECFG - Timeout Configuration
69987  *  0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
69988  *  0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
69989  */
69990 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
69991 
69992 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
69993 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
69994 /*! MATCFG - Match Configuration
69995  *  0b000..Match is disabled
69996  *  0b001..Reserved
69997  *  0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
69998  *  0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
69999  *  0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
70000  *  0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
70001  *  0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
70002  *  0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
70003  */
70004 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
70005 
70006 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
70007 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
70008 /*! PINCFG - Pin Configuration
70009  *  0b000..2-pin open drain mode
70010  *  0b001..2-pin output only mode (ultra-fast mode)
70011  *  0b010..2-pin push-pull mode
70012  *  0b011..4-pin push-pull mode
70013  *  0b100..2-pin open drain mode with separate LPI2C slave
70014  *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
70015  *  0b110..2-pin push-pull mode with separate LPI2C slave
70016  *  0b111..4-pin push-pull mode (inverted outputs)
70017  */
70018 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
70019 /*! @} */
70020 
70021 /*! @name MCFGR2 - Master Configuration 2 */
70022 /*! @{ */
70023 
70024 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
70025 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
70026 /*! BUSIDLE - Bus Idle Timeout
70027  */
70028 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
70029 
70030 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
70031 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
70032 /*! FILTSCL - Glitch Filter SCL
70033  */
70034 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
70035 
70036 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
70037 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
70038 /*! FILTSDA - Glitch Filter SDA
70039  */
70040 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
70041 /*! @} */
70042 
70043 /*! @name MCFGR3 - Master Configuration 3 */
70044 /*! @{ */
70045 
70046 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
70047 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
70048 /*! PINLOW - Pin Low Timeout
70049  */
70050 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
70051 /*! @} */
70052 
70053 /*! @name MDMR - Master Data Match */
70054 /*! @{ */
70055 
70056 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
70057 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
70058 /*! MATCH0 - Match 0 Value
70059  */
70060 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
70061 
70062 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
70063 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
70064 /*! MATCH1 - Match 1 Value
70065  */
70066 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
70067 /*! @} */
70068 
70069 /*! @name MCCR0 - Master Clock Configuration 0 */
70070 /*! @{ */
70071 
70072 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
70073 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
70074 /*! CLKLO - Clock Low Period
70075  */
70076 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
70077 
70078 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
70079 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
70080 /*! CLKHI - Clock High Period
70081  */
70082 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
70083 
70084 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
70085 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
70086 /*! SETHOLD - Setup Hold Delay
70087  */
70088 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
70089 
70090 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
70091 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
70092 /*! DATAVD - Data Valid Delay
70093  */
70094 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
70095 /*! @} */
70096 
70097 /*! @name MCCR1 - Master Clock Configuration 1 */
70098 /*! @{ */
70099 
70100 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
70101 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
70102 /*! CLKLO - Clock Low Period
70103  */
70104 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
70105 
70106 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
70107 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
70108 /*! CLKHI - Clock High Period
70109  */
70110 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
70111 
70112 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
70113 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
70114 /*! SETHOLD - Setup Hold Delay
70115  */
70116 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
70117 
70118 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
70119 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
70120 /*! DATAVD - Data Valid Delay
70121  */
70122 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
70123 /*! @} */
70124 
70125 /*! @name MFCR - Master FIFO Control */
70126 /*! @{ */
70127 
70128 #define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
70129 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
70130 /*! TXWATER - Transmit FIFO Watermark
70131  */
70132 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
70133 
70134 #define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
70135 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
70136 /*! RXWATER - Receive FIFO Watermark
70137  */
70138 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
70139 /*! @} */
70140 
70141 /*! @name MFSR - Master FIFO Status */
70142 /*! @{ */
70143 
70144 #define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
70145 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
70146 /*! TXCOUNT - Transmit FIFO Count
70147  */
70148 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
70149 
70150 #define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
70151 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
70152 /*! RXCOUNT - Receive FIFO Count
70153  */
70154 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
70155 /*! @} */
70156 
70157 /*! @name MTDR - Master Transmit Data */
70158 /*! @{ */
70159 
70160 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
70161 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
70162 /*! DATA - Transmit Data
70163  */
70164 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
70165 
70166 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
70167 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
70168 /*! CMD - Command Data
70169  *  0b000..Transmit DATA[7:0]
70170  *  0b001..Receive (DATA[7:0] + 1) bytes
70171  *  0b010..Generate STOP condition
70172  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
70173  *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
70174  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
70175  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
70176  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
70177  */
70178 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
70179 /*! @} */
70180 
70181 /*! @name MRDR - Master Receive Data */
70182 /*! @{ */
70183 
70184 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
70185 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
70186 /*! DATA - Receive Data
70187  */
70188 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
70189 
70190 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
70191 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
70192 /*! RXEMPTY - RX Empty
70193  *  0b0..Receive FIFO is not empty
70194  *  0b1..Receive FIFO is empty
70195  */
70196 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
70197 /*! @} */
70198 
70199 /*! @name SCR - Slave Control */
70200 /*! @{ */
70201 
70202 #define LPI2C_SCR_SEN_MASK                       (0x1U)
70203 #define LPI2C_SCR_SEN_SHIFT                      (0U)
70204 /*! SEN - Slave Enable
70205  *  0b0..I2C Slave mode is disabled
70206  *  0b1..I2C Slave mode is enabled
70207  */
70208 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
70209 
70210 #define LPI2C_SCR_RST_MASK                       (0x2U)
70211 #define LPI2C_SCR_RST_SHIFT                      (1U)
70212 /*! RST - Software Reset
70213  *  0b0..Slave mode logic is not reset
70214  *  0b1..Slave mode logic is reset
70215  */
70216 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
70217 
70218 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
70219 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
70220 /*! FILTEN - Filter Enable
70221  *  0b0..Disable digital filter and output delay counter for slave mode
70222  *  0b1..Enable digital filter and output delay counter for slave mode
70223  */
70224 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
70225 
70226 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
70227 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
70228 /*! FILTDZ - Filter Doze Enable
70229  *  0b0..Filter remains enabled in Doze mode
70230  *  0b1..Filter is disabled in Doze mode
70231  */
70232 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
70233 
70234 #define LPI2C_SCR_RTF_MASK                       (0x100U)
70235 #define LPI2C_SCR_RTF_SHIFT                      (8U)
70236 /*! RTF - Reset Transmit FIFO
70237  *  0b0..No effect
70238  *  0b1..Transmit Data Register is now empty
70239  */
70240 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
70241 
70242 #define LPI2C_SCR_RRF_MASK                       (0x200U)
70243 #define LPI2C_SCR_RRF_SHIFT                      (9U)
70244 /*! RRF - Reset Receive FIFO
70245  *  0b0..No effect
70246  *  0b1..Receive Data Register is now empty
70247  */
70248 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
70249 /*! @} */
70250 
70251 /*! @name SSR - Slave Status */
70252 /*! @{ */
70253 
70254 #define LPI2C_SSR_TDF_MASK                       (0x1U)
70255 #define LPI2C_SSR_TDF_SHIFT                      (0U)
70256 /*! TDF - Transmit Data Flag
70257  *  0b0..Transmit data not requested
70258  *  0b1..Transmit data is requested
70259  */
70260 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
70261 
70262 #define LPI2C_SSR_RDF_MASK                       (0x2U)
70263 #define LPI2C_SSR_RDF_SHIFT                      (1U)
70264 /*! RDF - Receive Data Flag
70265  *  0b0..Receive data is not ready
70266  *  0b1..Receive data is ready
70267  */
70268 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
70269 
70270 #define LPI2C_SSR_AVF_MASK                       (0x4U)
70271 #define LPI2C_SSR_AVF_SHIFT                      (2U)
70272 /*! AVF - Address Valid Flag
70273  *  0b0..Address Status Register is not valid
70274  *  0b1..Address Status Register is valid
70275  */
70276 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
70277 
70278 #define LPI2C_SSR_TAF_MASK                       (0x8U)
70279 #define LPI2C_SSR_TAF_SHIFT                      (3U)
70280 /*! TAF - Transmit ACK Flag
70281  *  0b0..Transmit ACK/NACK is not required
70282  *  0b1..Transmit ACK/NACK is required
70283  */
70284 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
70285 
70286 #define LPI2C_SSR_RSF_MASK                       (0x100U)
70287 #define LPI2C_SSR_RSF_SHIFT                      (8U)
70288 /*! RSF - Repeated Start Flag
70289  *  0b0..Slave has not detected a Repeated START condition
70290  *  0b1..Slave has detected a Repeated START condition
70291  */
70292 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
70293 
70294 #define LPI2C_SSR_SDF_MASK                       (0x200U)
70295 #define LPI2C_SSR_SDF_SHIFT                      (9U)
70296 /*! SDF - STOP Detect Flag
70297  *  0b0..Slave has not detected a STOP condition
70298  *  0b1..Slave has detected a STOP condition
70299  */
70300 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
70301 
70302 #define LPI2C_SSR_BEF_MASK                       (0x400U)
70303 #define LPI2C_SSR_BEF_SHIFT                      (10U)
70304 /*! BEF - Bit Error Flag
70305  *  0b0..Slave has not detected a bit error
70306  *  0b1..Slave has detected a bit error
70307  */
70308 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
70309 
70310 #define LPI2C_SSR_FEF_MASK                       (0x800U)
70311 #define LPI2C_SSR_FEF_SHIFT                      (11U)
70312 /*! FEF - FIFO Error Flag
70313  *  0b0..FIFO underflow or overflow was not detected
70314  *  0b1..FIFO underflow or overflow was detected
70315  */
70316 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
70317 
70318 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
70319 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
70320 /*! AM0F - Address Match 0 Flag
70321  *  0b0..Have not received an ADDR0 matching address
70322  *  0b1..Have received an ADDR0 matching address
70323  */
70324 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
70325 
70326 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
70327 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
70328 /*! AM1F - Address Match 1 Flag
70329  *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
70330  *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
70331  */
70332 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
70333 
70334 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
70335 #define LPI2C_SSR_GCF_SHIFT                      (14U)
70336 /*! GCF - General Call Flag
70337  *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
70338  *  0b1..Slave has detected the General Call Address
70339  */
70340 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
70341 
70342 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
70343 #define LPI2C_SSR_SARF_SHIFT                     (15U)
70344 /*! SARF - SMBus Alert Response Flag
70345  *  0b0..SMBus Alert Response is disabled or not detected
70346  *  0b1..SMBus Alert Response is enabled and detected
70347  */
70348 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
70349 
70350 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
70351 #define LPI2C_SSR_SBF_SHIFT                      (24U)
70352 /*! SBF - Slave Busy Flag
70353  *  0b0..I2C Slave is idle
70354  *  0b1..I2C Slave is busy
70355  */
70356 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
70357 
70358 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
70359 #define LPI2C_SSR_BBF_SHIFT                      (25U)
70360 /*! BBF - Bus Busy Flag
70361  *  0b0..I2C Bus is idle
70362  *  0b1..I2C Bus is busy
70363  */
70364 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
70365 /*! @} */
70366 
70367 /*! @name SIER - Slave Interrupt Enable */
70368 /*! @{ */
70369 
70370 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
70371 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
70372 /*! TDIE - Transmit Data Interrupt Enable
70373  *  0b0..Disabled
70374  *  0b1..Enabled
70375  */
70376 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
70377 
70378 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
70379 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
70380 /*! RDIE - Receive Data Interrupt Enable
70381  *  0b0..Disabled
70382  *  0b1..Enabled
70383  */
70384 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
70385 
70386 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
70387 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
70388 /*! AVIE - Address Valid Interrupt Enable
70389  *  0b0..Disabled
70390  *  0b1..Enabled
70391  */
70392 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
70393 
70394 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
70395 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
70396 /*! TAIE - Transmit ACK Interrupt Enable
70397  *  0b0..Disabled
70398  *  0b1..Enabled
70399  */
70400 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
70401 
70402 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
70403 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
70404 /*! RSIE - Repeated Start Interrupt Enable
70405  *  0b0..Disabled
70406  *  0b1..Enabled
70407  */
70408 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
70409 
70410 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
70411 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
70412 /*! SDIE - STOP Detect Interrupt Enable
70413  *  0b0..Disabled
70414  *  0b1..Enabled
70415  */
70416 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
70417 
70418 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
70419 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
70420 /*! BEIE - Bit Error Interrupt Enable
70421  *  0b0..Disabled
70422  *  0b1..Enabled
70423  */
70424 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
70425 
70426 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
70427 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
70428 /*! FEIE - FIFO Error Interrupt Enable
70429  *  0b0..Disabled
70430  *  0b1..Enabled
70431  */
70432 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
70433 
70434 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
70435 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
70436 /*! AM0IE - Address Match 0 Interrupt Enable
70437  *  0b0..Disabled
70438  *  0b1..Enabled
70439  */
70440 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
70441 
70442 #define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
70443 #define LPI2C_SIER_AM1IE_SHIFT                   (13U)
70444 /*! AM1IE - Address Match 1 Interrupt Enable
70445  *  0b0..Disabled
70446  *  0b1..Enabled
70447  */
70448 #define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
70449 
70450 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
70451 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
70452 /*! GCIE - General Call Interrupt Enable
70453  *  0b0..Disabled
70454  *  0b1..Enabled
70455  */
70456 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
70457 
70458 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
70459 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
70460 /*! SARIE - SMBus Alert Response Interrupt Enable
70461  *  0b0..Disabled
70462  *  0b1..Enabled
70463  */
70464 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
70465 /*! @} */
70466 
70467 /*! @name SDER - Slave DMA Enable */
70468 /*! @{ */
70469 
70470 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
70471 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
70472 /*! TDDE - Transmit Data DMA Enable
70473  *  0b0..DMA request is disabled
70474  *  0b1..DMA request is enabled
70475  */
70476 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
70477 
70478 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
70479 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
70480 /*! RDDE - Receive Data DMA Enable
70481  *  0b0..DMA request is disabled
70482  *  0b1..DMA request is enabled
70483  */
70484 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
70485 
70486 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
70487 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
70488 /*! AVDE - Address Valid DMA Enable
70489  *  0b0..DMA request is disabled
70490  *  0b1..DMA request is enabled
70491  */
70492 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
70493 /*! @} */
70494 
70495 /*! @name SCFGR1 - Slave Configuration 1 */
70496 /*! @{ */
70497 
70498 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
70499 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
70500 /*! ADRSTALL - Address SCL Stall
70501  *  0b0..Clock stretching is disabled
70502  *  0b1..Clock stretching is enabled
70503  */
70504 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
70505 
70506 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
70507 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
70508 /*! RXSTALL - RX SCL Stall
70509  *  0b0..Clock stretching is disabled
70510  *  0b1..Clock stretching is enabled
70511  */
70512 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
70513 
70514 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
70515 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
70516 /*! TXDSTALL - TX Data SCL Stall
70517  *  0b0..Clock stretching is disabled
70518  *  0b1..Clock stretching is enabled
70519  */
70520 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
70521 
70522 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
70523 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
70524 /*! ACKSTALL - ACK SCL Stall
70525  *  0b0..Clock stretching is disabled
70526  *  0b1..Clock stretching is enabled
70527  */
70528 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
70529 
70530 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
70531 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
70532 /*! GCEN - General Call Enable
70533  *  0b0..General Call address is disabled
70534  *  0b1..General Call address is enabled
70535  */
70536 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
70537 
70538 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
70539 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
70540 /*! SAEN - SMBus Alert Enable
70541  *  0b0..Disables match on SMBus Alert
70542  *  0b1..Enables match on SMBus Alert
70543  */
70544 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
70545 
70546 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
70547 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
70548 /*! TXCFG - Transmit Flag Configuration
70549  *  0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
70550  *  0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
70551  */
70552 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
70553 
70554 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
70555 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
70556 /*! RXCFG - Receive Data Configuration
70557  *  0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]).
70558  *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address
70559  *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag
70560  *       is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
70561  */
70562 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
70563 
70564 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
70565 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
70566 /*! IGNACK - Ignore NACK
70567  *  0b0..Slave ends transfer when NACK is detected
70568  *  0b1..Slave does not end transfer when NACK detected
70569  */
70570 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
70571 
70572 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
70573 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
70574 /*! HSMEN - High Speed Mode Enable
70575  *  0b0..Disables detection of HS-mode master code
70576  *  0b1..Enables detection of HS-mode master code
70577  */
70578 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
70579 
70580 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
70581 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
70582 /*! ADDRCFG - Address Configuration
70583  *  0b000..Address match 0 (7-bit)
70584  *  0b001..Address match 0 (10-bit)
70585  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
70586  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
70587  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
70588  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
70589  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
70590  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
70591  */
70592 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
70593 /*! @} */
70594 
70595 /*! @name SCFGR2 - Slave Configuration 2 */
70596 /*! @{ */
70597 
70598 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
70599 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
70600 /*! CLKHOLD - Clock Hold Time
70601  */
70602 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
70603 
70604 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
70605 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
70606 /*! DATAVD - Data Valid Delay
70607  */
70608 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
70609 
70610 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
70611 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
70612 /*! FILTSCL - Glitch Filter SCL
70613  */
70614 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
70615 
70616 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
70617 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
70618 /*! FILTSDA - Glitch Filter SDA
70619  */
70620 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
70621 /*! @} */
70622 
70623 /*! @name SAMR - Slave Address Match */
70624 /*! @{ */
70625 
70626 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
70627 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
70628 /*! ADDR0 - Address 0 Value
70629  */
70630 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
70631 
70632 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
70633 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
70634 /*! ADDR1 - Address 1 Value
70635  */
70636 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
70637 /*! @} */
70638 
70639 /*! @name SASR - Slave Address Status */
70640 /*! @{ */
70641 
70642 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
70643 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
70644 /*! RADDR - Received Address
70645  */
70646 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
70647 
70648 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
70649 #define LPI2C_SASR_ANV_SHIFT                     (14U)
70650 /*! ANV - Address Not Valid
70651  *  0b0..Received Address (RADDR) is valid
70652  *  0b1..Received Address (RADDR) is not valid
70653  */
70654 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
70655 /*! @} */
70656 
70657 /*! @name STAR - Slave Transmit ACK */
70658 /*! @{ */
70659 
70660 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
70661 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
70662 /*! TXNACK - Transmit NACK
70663  *  0b0..Write a Transmit ACK for each received word
70664  *  0b1..Write a Transmit NACK for each received word
70665  */
70666 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
70667 /*! @} */
70668 
70669 /*! @name STDR - Slave Transmit Data */
70670 /*! @{ */
70671 
70672 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
70673 #define LPI2C_STDR_DATA_SHIFT                    (0U)
70674 /*! DATA - Transmit Data
70675  */
70676 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
70677 /*! @} */
70678 
70679 /*! @name SRDR - Slave Receive Data */
70680 /*! @{ */
70681 
70682 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
70683 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
70684 /*! DATA - Receive Data
70685  */
70686 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
70687 
70688 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
70689 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
70690 /*! RXEMPTY - RX Empty
70691  *  0b0..The Receive Data Register is not empty
70692  *  0b1..The Receive Data Register is empty
70693  */
70694 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
70695 
70696 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
70697 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
70698 /*! SOF - Start Of Frame
70699  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
70700  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
70701  */
70702 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
70703 /*! @} */
70704 
70705 
70706 /*!
70707  * @}
70708  */ /* end of group LPI2C_Register_Masks */
70709 
70710 
70711 /* LPI2C - Peripheral instance base addresses */
70712 /** Peripheral LPI2C1 base address */
70713 #define LPI2C1_BASE                              (0x40104000u)
70714 /** Peripheral LPI2C1 base pointer */
70715 #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
70716 /** Peripheral LPI2C2 base address */
70717 #define LPI2C2_BASE                              (0x40108000u)
70718 /** Peripheral LPI2C2 base pointer */
70719 #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
70720 /** Peripheral LPI2C3 base address */
70721 #define LPI2C3_BASE                              (0x4010C000u)
70722 /** Peripheral LPI2C3 base pointer */
70723 #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
70724 /** Peripheral LPI2C4 base address */
70725 #define LPI2C4_BASE                              (0x40110000u)
70726 /** Peripheral LPI2C4 base pointer */
70727 #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
70728 /** Peripheral LPI2C5 base address */
70729 #define LPI2C5_BASE                              (0x40C34000u)
70730 /** Peripheral LPI2C5 base pointer */
70731 #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
70732 /** Peripheral LPI2C6 base address */
70733 #define LPI2C6_BASE                              (0x40C38000u)
70734 /** Peripheral LPI2C6 base pointer */
70735 #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
70736 /** Array initializer of LPI2C peripheral base addresses */
70737 #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
70738 /** Array initializer of LPI2C peripheral base pointers */
70739 #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
70740 /** Interrupt vectors for the LPI2C peripheral type */
70741 #define LPI2C_IRQS                               { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
70742 
70743 /*!
70744  * @}
70745  */ /* end of group LPI2C_Peripheral_Access_Layer */
70746 
70747 
70748 /* ----------------------------------------------------------------------------
70749    -- LPSPI Peripheral Access Layer
70750    ---------------------------------------------------------------------------- */
70751 
70752 /*!
70753  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
70754  * @{
70755  */
70756 
70757 /** LPSPI - Register Layout Typedef */
70758 typedef struct {
70759   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
70760   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
70761        uint8_t RESERVED_0[8];
70762   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
70763   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
70764   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
70765   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
70766   __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
70767   __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
70768        uint8_t RESERVED_1[8];
70769   __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
70770   __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
70771        uint8_t RESERVED_2[8];
70772   __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
70773        uint8_t RESERVED_3[20];
70774   __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
70775   __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
70776   __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
70777   __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
70778        uint8_t RESERVED_4[8];
70779   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
70780   __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
70781 } LPSPI_Type;
70782 
70783 /* ----------------------------------------------------------------------------
70784    -- LPSPI Register Masks
70785    ---------------------------------------------------------------------------- */
70786 
70787 /*!
70788  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
70789  * @{
70790  */
70791 
70792 /*! @name VERID - Version ID */
70793 /*! @{ */
70794 
70795 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
70796 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
70797 /*! FEATURE - Module Identification Number
70798  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
70799  */
70800 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
70801 
70802 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
70803 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
70804 /*! MINOR - Minor Version Number
70805  */
70806 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
70807 
70808 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
70809 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
70810 /*! MAJOR - Major Version Number
70811  */
70812 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
70813 /*! @} */
70814 
70815 /*! @name PARAM - Parameter */
70816 /*! @{ */
70817 
70818 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
70819 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
70820 /*! TXFIFO - Transmit FIFO Size
70821  */
70822 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
70823 
70824 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
70825 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
70826 /*! RXFIFO - Receive FIFO Size
70827  */
70828 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
70829 
70830 #define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
70831 #define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
70832 /*! PCSNUM - PCS Number
70833  */
70834 #define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
70835 /*! @} */
70836 
70837 /*! @name CR - Control */
70838 /*! @{ */
70839 
70840 #define LPSPI_CR_MEN_MASK                        (0x1U)
70841 #define LPSPI_CR_MEN_SHIFT                       (0U)
70842 /*! MEN - Module Enable
70843  *  0b0..Module is disabled
70844  *  0b1..Module is enabled
70845  */
70846 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
70847 
70848 #define LPSPI_CR_RST_MASK                        (0x2U)
70849 #define LPSPI_CR_RST_SHIFT                       (1U)
70850 /*! RST - Software Reset
70851  *  0b0..Module is not reset
70852  *  0b1..Module is reset
70853  */
70854 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
70855 
70856 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
70857 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
70858 /*! DOZEN - Doze Mode Enable
70859  *  0b0..LPSPI module is enabled in Doze mode
70860  *  0b1..LPSPI module is disabled in Doze mode
70861  */
70862 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
70863 
70864 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
70865 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
70866 /*! DBGEN - Debug Enable
70867  *  0b0..LPSPI module is disabled in debug mode
70868  *  0b1..LPSPI module is enabled in debug mode
70869  */
70870 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
70871 
70872 #define LPSPI_CR_RTF_MASK                        (0x100U)
70873 #define LPSPI_CR_RTF_SHIFT                       (8U)
70874 /*! RTF - Reset Transmit FIFO
70875  *  0b0..No effect
70876  *  0b1..Reset the Transmit FIFO. The register bit always reads zero.
70877  */
70878 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
70879 
70880 #define LPSPI_CR_RRF_MASK                        (0x200U)
70881 #define LPSPI_CR_RRF_SHIFT                       (9U)
70882 /*! RRF - Reset Receive FIFO
70883  *  0b0..No effect
70884  *  0b1..Reset the Receive FIFO. The register bit always reads zero.
70885  */
70886 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
70887 /*! @} */
70888 
70889 /*! @name SR - Status */
70890 /*! @{ */
70891 
70892 #define LPSPI_SR_TDF_MASK                        (0x1U)
70893 #define LPSPI_SR_TDF_SHIFT                       (0U)
70894 /*! TDF - Transmit Data Flag
70895  *  0b0..Transmit data not requested
70896  *  0b1..Transmit data is requested
70897  */
70898 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
70899 
70900 #define LPSPI_SR_RDF_MASK                        (0x2U)
70901 #define LPSPI_SR_RDF_SHIFT                       (1U)
70902 /*! RDF - Receive Data Flag
70903  *  0b0..Receive Data is not ready
70904  *  0b1..Receive data is ready
70905  */
70906 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
70907 
70908 #define LPSPI_SR_WCF_MASK                        (0x100U)
70909 #define LPSPI_SR_WCF_SHIFT                       (8U)
70910 /*! WCF - Word Complete Flag
70911  *  0b0..Transfer of a received word has not yet completed
70912  *  0b1..Transfer of a received word has completed
70913  */
70914 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
70915 
70916 #define LPSPI_SR_FCF_MASK                        (0x200U)
70917 #define LPSPI_SR_FCF_SHIFT                       (9U)
70918 /*! FCF - Frame Complete Flag
70919  *  0b0..Frame transfer has not completed
70920  *  0b1..Frame transfer has completed
70921  */
70922 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
70923 
70924 #define LPSPI_SR_TCF_MASK                        (0x400U)
70925 #define LPSPI_SR_TCF_SHIFT                       (10U)
70926 /*! TCF - Transfer Complete Flag
70927  *  0b0..All transfers have not completed
70928  *  0b1..All transfers have completed
70929  */
70930 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
70931 
70932 #define LPSPI_SR_TEF_MASK                        (0x800U)
70933 #define LPSPI_SR_TEF_SHIFT                       (11U)
70934 /*! TEF - Transmit Error Flag
70935  *  0b0..Transmit FIFO underrun has not occurred
70936  *  0b1..Transmit FIFO underrun has occurred
70937  */
70938 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
70939 
70940 #define LPSPI_SR_REF_MASK                        (0x1000U)
70941 #define LPSPI_SR_REF_SHIFT                       (12U)
70942 /*! REF - Receive Error Flag
70943  *  0b0..Receive FIFO has not overflowed
70944  *  0b1..Receive FIFO has overflowed
70945  */
70946 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
70947 
70948 #define LPSPI_SR_DMF_MASK                        (0x2000U)
70949 #define LPSPI_SR_DMF_SHIFT                       (13U)
70950 /*! DMF - Data Match Flag
70951  *  0b0..Have not received matching data
70952  *  0b1..Have received matching data
70953  */
70954 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
70955 
70956 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
70957 #define LPSPI_SR_MBF_SHIFT                       (24U)
70958 /*! MBF - Module Busy Flag
70959  *  0b0..LPSPI is idle
70960  *  0b1..LPSPI is busy
70961  */
70962 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
70963 /*! @} */
70964 
70965 /*! @name IER - Interrupt Enable */
70966 /*! @{ */
70967 
70968 #define LPSPI_IER_TDIE_MASK                      (0x1U)
70969 #define LPSPI_IER_TDIE_SHIFT                     (0U)
70970 /*! TDIE - Transmit Data Interrupt Enable
70971  *  0b0..Disabled
70972  *  0b1..Enabled
70973  */
70974 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
70975 
70976 #define LPSPI_IER_RDIE_MASK                      (0x2U)
70977 #define LPSPI_IER_RDIE_SHIFT                     (1U)
70978 /*! RDIE - Receive Data Interrupt Enable
70979  *  0b0..Disabled
70980  *  0b1..Enabled
70981  */
70982 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
70983 
70984 #define LPSPI_IER_WCIE_MASK                      (0x100U)
70985 #define LPSPI_IER_WCIE_SHIFT                     (8U)
70986 /*! WCIE - Word Complete Interrupt Enable
70987  *  0b0..Disabled
70988  *  0b1..Enabled
70989  */
70990 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
70991 
70992 #define LPSPI_IER_FCIE_MASK                      (0x200U)
70993 #define LPSPI_IER_FCIE_SHIFT                     (9U)
70994 /*! FCIE - Frame Complete Interrupt Enable
70995  *  0b0..Disabled
70996  *  0b1..Enabled
70997  */
70998 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
70999 
71000 #define LPSPI_IER_TCIE_MASK                      (0x400U)
71001 #define LPSPI_IER_TCIE_SHIFT                     (10U)
71002 /*! TCIE - Transfer Complete Interrupt Enable
71003  *  0b0..Disabled
71004  *  0b1..Enabled
71005  */
71006 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
71007 
71008 #define LPSPI_IER_TEIE_MASK                      (0x800U)
71009 #define LPSPI_IER_TEIE_SHIFT                     (11U)
71010 /*! TEIE - Transmit Error Interrupt Enable
71011  *  0b0..Disabled
71012  *  0b1..Enabled
71013  */
71014 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
71015 
71016 #define LPSPI_IER_REIE_MASK                      (0x1000U)
71017 #define LPSPI_IER_REIE_SHIFT                     (12U)
71018 /*! REIE - Receive Error Interrupt Enable
71019  *  0b0..Disabled
71020  *  0b1..Enabled
71021  */
71022 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
71023 
71024 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
71025 #define LPSPI_IER_DMIE_SHIFT                     (13U)
71026 /*! DMIE - Data Match Interrupt Enable
71027  *  0b0..Disabled
71028  *  0b1..Enabled
71029  */
71030 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
71031 /*! @} */
71032 
71033 /*! @name DER - DMA Enable */
71034 /*! @{ */
71035 
71036 #define LPSPI_DER_TDDE_MASK                      (0x1U)
71037 #define LPSPI_DER_TDDE_SHIFT                     (0U)
71038 /*! TDDE - Transmit Data DMA Enable
71039  *  0b0..DMA request is disabled
71040  *  0b1..DMA request is enabled
71041  */
71042 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
71043 
71044 #define LPSPI_DER_RDDE_MASK                      (0x2U)
71045 #define LPSPI_DER_RDDE_SHIFT                     (1U)
71046 /*! RDDE - Receive Data DMA Enable
71047  *  0b0..DMA request is disabled
71048  *  0b1..DMA request is enabled
71049  */
71050 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
71051 /*! @} */
71052 
71053 /*! @name CFGR0 - Configuration 0 */
71054 /*! @{ */
71055 
71056 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
71057 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
71058 /*! CIRFIFO - Circular FIFO Enable
71059  *  0b0..Circular FIFO is disabled
71060  *  0b1..Circular FIFO is enabled
71061  */
71062 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
71063 
71064 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
71065 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
71066 /*! RDMO - Receive Data Match Only
71067  *  0b0..Received data is stored in the receive FIFO as in normal operations
71068  *  0b1..Received data is discarded unless the SR[DMF] = 1
71069  */
71070 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
71071 /*! @} */
71072 
71073 /*! @name CFGR1 - Configuration 1 */
71074 /*! @{ */
71075 
71076 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
71077 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
71078 /*! MASTER - Master Mode
71079  *  0b0..Slave mode
71080  *  0b1..Master mode
71081  */
71082 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
71083 
71084 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
71085 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
71086 /*! SAMPLE - Sample Point
71087  *  0b0..Input data is sampled on SCK edge
71088  *  0b1..Input data is sampled on delayed SCK edge
71089  */
71090 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
71091 
71092 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
71093 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
71094 /*! AUTOPCS - Automatic PCS
71095  *  0b0..Automatic PCS generation is disabled
71096  *  0b1..Automatic PCS generation is enabled
71097  */
71098 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
71099 
71100 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
71101 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
71102 /*! NOSTALL - No Stall
71103  *  0b0..Transfers stall when the transmit FIFO is empty
71104  *  0b1..Transfers do not stall, allowing transmit FIFO underruns to occur
71105  */
71106 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
71107 
71108 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
71109 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
71110 /*! PCSPOL - Peripheral Chip Select Polarity
71111  */
71112 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
71113 
71114 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
71115 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
71116 /*! MATCFG - Match Configuration
71117  *  0b000..Match is disabled
71118  *  0b001..Reserved
71119  *  0b010..Match is enabled is 1st data word is MATCH0 or MATCH1
71120  *  0b011..Match is enabled on any data word equal MATCH0 or MATCH1
71121  *  0b100..Match is enabled on data match sequence
71122  *  0b101..Match is enabled on data match sequence
71123  *  0b110..Match is enabled
71124  *  0b111..Match is enabled
71125  */
71126 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
71127 
71128 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
71129 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
71130 /*! PINCFG - Pin Configuration
71131  *  0b00..SIN is used for input data and SOUT is used for output data
71132  *  0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
71133  *  0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
71134  *  0b11..SOUT is used for input data and SIN is used for output data
71135  */
71136 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
71137 
71138 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
71139 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
71140 /*! OUTCFG - Output Configuration
71141  *  0b0..Output data retains last value when chip select is negated
71142  *  0b1..Output data is tristated when chip select is negated
71143  */
71144 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
71145 
71146 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
71147 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
71148 /*! PCSCFG - Peripheral Chip Select Configuration
71149  *  0b0..PCS[3:2] are configured for chip select function
71150  *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
71151  */
71152 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
71153 /*! @} */
71154 
71155 /*! @name DMR0 - Data Match 0 */
71156 /*! @{ */
71157 
71158 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
71159 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
71160 /*! MATCH0 - Match 0 Value
71161  */
71162 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
71163 /*! @} */
71164 
71165 /*! @name DMR1 - Data Match 1 */
71166 /*! @{ */
71167 
71168 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
71169 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
71170 /*! MATCH1 - Match 1 Value
71171  */
71172 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
71173 /*! @} */
71174 
71175 /*! @name CCR - Clock Configuration */
71176 /*! @{ */
71177 
71178 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
71179 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
71180 /*! SCKDIV - SCK Divider
71181  */
71182 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
71183 
71184 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
71185 #define LPSPI_CCR_DBT_SHIFT                      (8U)
71186 /*! DBT - Delay Between Transfers
71187  */
71188 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
71189 
71190 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
71191 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
71192 /*! PCSSCK - PCS-to-SCK Delay
71193  */
71194 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
71195 
71196 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
71197 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
71198 /*! SCKPCS - SCK-to-PCS Delay
71199  */
71200 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
71201 /*! @} */
71202 
71203 /*! @name FCR - FIFO Control */
71204 /*! @{ */
71205 
71206 #define LPSPI_FCR_TXWATER_MASK                   (0xFU)
71207 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
71208 /*! TXWATER - Transmit FIFO Watermark
71209  */
71210 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
71211 
71212 #define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)
71213 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
71214 /*! RXWATER - Receive FIFO Watermark
71215  */
71216 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
71217 /*! @} */
71218 
71219 /*! @name FSR - FIFO Status */
71220 /*! @{ */
71221 
71222 #define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)
71223 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
71224 /*! TXCOUNT - Transmit FIFO Count
71225  */
71226 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
71227 
71228 #define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)
71229 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
71230 /*! RXCOUNT - Receive FIFO Count
71231  */
71232 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
71233 /*! @} */
71234 
71235 /*! @name TCR - Transmit Command */
71236 /*! @{ */
71237 
71238 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
71239 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
71240 /*! FRAMESZ - Frame Size
71241  */
71242 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
71243 
71244 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
71245 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
71246 /*! WIDTH - Transfer Width
71247  *  0b00..1 bit transfer
71248  *  0b01..2 bit transfer
71249  *  0b10..4 bit transfer
71250  *  0b11..Reserved
71251  */
71252 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
71253 
71254 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
71255 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
71256 /*! TXMSK - Transmit Data Mask
71257  *  0b0..Normal transfer
71258  *  0b1..Mask transmit data
71259  */
71260 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
71261 
71262 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
71263 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
71264 /*! RXMSK - Receive Data Mask
71265  *  0b0..Normal transfer
71266  *  0b1..Receive data is masked
71267  */
71268 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
71269 
71270 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
71271 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
71272 /*! CONTC - Continuing Command
71273  *  0b0..Command word for start of new transfer
71274  *  0b1..Command word for continuing transfer
71275  */
71276 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
71277 
71278 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
71279 #define LPSPI_TCR_CONT_SHIFT                     (21U)
71280 /*! CONT - Continuous Transfer
71281  *  0b0..Continuous transfer is disabled
71282  *  0b1..Continuous transfer is enabled
71283  */
71284 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
71285 
71286 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
71287 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
71288 /*! BYSW - Byte Swap
71289  *  0b0..Byte swap is disabled
71290  *  0b1..Byte swap is enabled
71291  */
71292 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
71293 
71294 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
71295 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
71296 /*! LSBF - LSB First
71297  *  0b0..Data is transferred MSB first
71298  *  0b1..Data is transferred LSB first
71299  */
71300 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
71301 
71302 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
71303 #define LPSPI_TCR_PCS_SHIFT                      (24U)
71304 /*! PCS - Peripheral Chip Select
71305  *  0b00..Transfer using PCS[0]
71306  *  0b01..Transfer using PCS[1]
71307  *  0b10..Transfer using PCS[2]
71308  *  0b11..Transfer using PCS[3]
71309  */
71310 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
71311 
71312 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
71313 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
71314 /*! PRESCALE - Prescaler Value
71315  *  0b000..Divide by 1
71316  *  0b001..Divide by 2
71317  *  0b010..Divide by 4
71318  *  0b011..Divide by 8
71319  *  0b100..Divide by 16
71320  *  0b101..Divide by 32
71321  *  0b110..Divide by 64
71322  *  0b111..Divide by 128
71323  */
71324 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
71325 
71326 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
71327 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
71328 /*! CPHA - Clock Phase
71329  *  0b0..Captured
71330  *  0b1..Changed
71331  */
71332 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
71333 
71334 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
71335 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
71336 /*! CPOL - Clock Polarity
71337  *  0b0..The inactive state value of SCK is low
71338  *  0b1..The inactive state value of SCK is high
71339  */
71340 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
71341 /*! @} */
71342 
71343 /*! @name TDR - Transmit Data */
71344 /*! @{ */
71345 
71346 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
71347 #define LPSPI_TDR_DATA_SHIFT                     (0U)
71348 /*! DATA - Transmit Data
71349  */
71350 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
71351 /*! @} */
71352 
71353 /*! @name RSR - Receive Status */
71354 /*! @{ */
71355 
71356 #define LPSPI_RSR_SOF_MASK                       (0x1U)
71357 #define LPSPI_RSR_SOF_SHIFT                      (0U)
71358 /*! SOF - Start Of Frame
71359  *  0b0..Subsequent data word received after PCS assertion
71360  *  0b1..First data word received after PCS assertion
71361  */
71362 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
71363 
71364 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
71365 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
71366 /*! RXEMPTY - RX FIFO Empty
71367  *  0b0..RX FIFO is not empty
71368  *  0b1..RX FIFO is empty
71369  */
71370 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
71371 /*! @} */
71372 
71373 /*! @name RDR - Receive Data */
71374 /*! @{ */
71375 
71376 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
71377 #define LPSPI_RDR_DATA_SHIFT                     (0U)
71378 /*! DATA - Receive Data
71379  */
71380 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
71381 /*! @} */
71382 
71383 
71384 /*!
71385  * @}
71386  */ /* end of group LPSPI_Register_Masks */
71387 
71388 
71389 /* LPSPI - Peripheral instance base addresses */
71390 /** Peripheral LPSPI1 base address */
71391 #define LPSPI1_BASE                              (0x40114000u)
71392 /** Peripheral LPSPI1 base pointer */
71393 #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
71394 /** Peripheral LPSPI2 base address */
71395 #define LPSPI2_BASE                              (0x40118000u)
71396 /** Peripheral LPSPI2 base pointer */
71397 #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
71398 /** Peripheral LPSPI3 base address */
71399 #define LPSPI3_BASE                              (0x4011C000u)
71400 /** Peripheral LPSPI3 base pointer */
71401 #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
71402 /** Peripheral LPSPI4 base address */
71403 #define LPSPI4_BASE                              (0x40120000u)
71404 /** Peripheral LPSPI4 base pointer */
71405 #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
71406 /** Peripheral LPSPI5 base address */
71407 #define LPSPI5_BASE                              (0x40C2C000u)
71408 /** Peripheral LPSPI5 base pointer */
71409 #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
71410 /** Peripheral LPSPI6 base address */
71411 #define LPSPI6_BASE                              (0x40C30000u)
71412 /** Peripheral LPSPI6 base pointer */
71413 #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
71414 /** Array initializer of LPSPI peripheral base addresses */
71415 #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
71416 /** Array initializer of LPSPI peripheral base pointers */
71417 #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
71418 /** Interrupt vectors for the LPSPI peripheral type */
71419 #define LPSPI_IRQS                               { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
71420 
71421 /*!
71422  * @}
71423  */ /* end of group LPSPI_Peripheral_Access_Layer */
71424 
71425 
71426 /* ----------------------------------------------------------------------------
71427    -- LPUART Peripheral Access Layer
71428    ---------------------------------------------------------------------------- */
71429 
71430 /*!
71431  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
71432  * @{
71433  */
71434 
71435 /** LPUART - Register Layout Typedef */
71436 typedef struct {
71437   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
71438   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
71439   __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
71440   __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
71441   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
71442   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
71443   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
71444   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
71445   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
71446   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
71447   __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
71448   __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
71449 } LPUART_Type;
71450 
71451 /* ----------------------------------------------------------------------------
71452    -- LPUART Register Masks
71453    ---------------------------------------------------------------------------- */
71454 
71455 /*!
71456  * @addtogroup LPUART_Register_Masks LPUART Register Masks
71457  * @{
71458  */
71459 
71460 /*! @name VERID - Version ID Register */
71461 /*! @{ */
71462 
71463 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
71464 #define LPUART_VERID_FEATURE_SHIFT               (0U)
71465 /*! FEATURE - Feature Identification Number
71466  *  0b0000000000000001..Standard feature set.
71467  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
71468  */
71469 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
71470 
71471 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
71472 #define LPUART_VERID_MINOR_SHIFT                 (16U)
71473 /*! MINOR - Minor Version Number
71474  */
71475 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
71476 
71477 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
71478 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
71479 /*! MAJOR - Major Version Number
71480  */
71481 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
71482 /*! @} */
71483 
71484 /*! @name PARAM - Parameter Register */
71485 /*! @{ */
71486 
71487 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
71488 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
71489 /*! TXFIFO - Transmit FIFO Size
71490  */
71491 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
71492 
71493 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
71494 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
71495 /*! RXFIFO - Receive FIFO Size
71496  */
71497 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
71498 /*! @} */
71499 
71500 /*! @name GLOBAL - LPUART Global Register */
71501 /*! @{ */
71502 
71503 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
71504 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
71505 /*! RST - Software Reset
71506  *  0b0..Module is not reset.
71507  *  0b1..Module is reset.
71508  */
71509 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
71510 /*! @} */
71511 
71512 /*! @name PINCFG - LPUART Pin Configuration Register */
71513 /*! @{ */
71514 
71515 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
71516 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
71517 /*! TRGSEL - Trigger Select
71518  *  0b00..Input trigger is disabled.
71519  *  0b01..Input trigger is used instead of RXD pin input.
71520  *  0b10..Input trigger is used instead of CTS_B pin input.
71521  *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
71522  *        internally ANDed with the input trigger.
71523  */
71524 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
71525 /*! @} */
71526 
71527 /*! @name BAUD - LPUART Baud Rate Register */
71528 /*! @{ */
71529 
71530 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
71531 #define LPUART_BAUD_SBR_SHIFT                    (0U)
71532 /*! SBR - Baud Rate Modulo Divisor.
71533  */
71534 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
71535 
71536 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
71537 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
71538 /*! SBNS - Stop Bit Number Select
71539  *  0b0..One stop bit.
71540  *  0b1..Two stop bits.
71541  */
71542 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
71543 
71544 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
71545 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
71546 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
71547  *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
71548  *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
71549  */
71550 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
71551 
71552 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
71553 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
71554 /*! LBKDIE - LIN Break Detect Interrupt Enable
71555  *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
71556  *  0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
71557  */
71558 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
71559 
71560 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
71561 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
71562 /*! RESYNCDIS - Resynchronization Disable
71563  *  0b0..Resynchronization during received data word is supported.
71564  *  0b1..Resynchronization during received data word is disabled.
71565  */
71566 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
71567 
71568 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
71569 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
71570 /*! BOTHEDGE - Both Edge Sampling
71571  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
71572  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
71573  */
71574 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
71575 
71576 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
71577 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
71578 /*! MATCFG - Match Configuration
71579  *  0b00..Address Match Wakeup
71580  *  0b01..Idle Match Wakeup
71581  *  0b10..Match On and Match Off
71582  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
71583  */
71584 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
71585 
71586 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
71587 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
71588 /*! RDMAE - Receiver Full DMA Enable
71589  *  0b0..DMA request disabled.
71590  *  0b1..DMA request enabled.
71591  */
71592 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
71593 
71594 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
71595 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
71596 /*! TDMAE - Transmitter DMA Enable
71597  *  0b0..DMA request disabled.
71598  *  0b1..DMA request enabled.
71599  */
71600 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
71601 
71602 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
71603 #define LPUART_BAUD_OSR_SHIFT                    (24U)
71604 /*! OSR - Oversampling Ratio
71605  *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
71606  *  0b00001..Reserved
71607  *  0b00010..Reserved
71608  *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
71609  *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
71610  *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
71611  *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
71612  *  0b00111..Oversampling ratio of 8.
71613  *  0b01000..Oversampling ratio of 9.
71614  *  0b01001..Oversampling ratio of 10.
71615  *  0b01010..Oversampling ratio of 11.
71616  *  0b01011..Oversampling ratio of 12.
71617  *  0b01100..Oversampling ratio of 13.
71618  *  0b01101..Oversampling ratio of 14.
71619  *  0b01110..Oversampling ratio of 15.
71620  *  0b01111..Oversampling ratio of 16.
71621  *  0b10000..Oversampling ratio of 17.
71622  *  0b10001..Oversampling ratio of 18.
71623  *  0b10010..Oversampling ratio of 19.
71624  *  0b10011..Oversampling ratio of 20.
71625  *  0b10100..Oversampling ratio of 21.
71626  *  0b10101..Oversampling ratio of 22.
71627  *  0b10110..Oversampling ratio of 23.
71628  *  0b10111..Oversampling ratio of 24.
71629  *  0b11000..Oversampling ratio of 25.
71630  *  0b11001..Oversampling ratio of 26.
71631  *  0b11010..Oversampling ratio of 27.
71632  *  0b11011..Oversampling ratio of 28.
71633  *  0b11100..Oversampling ratio of 29.
71634  *  0b11101..Oversampling ratio of 30.
71635  *  0b11110..Oversampling ratio of 31.
71636  *  0b11111..Oversampling ratio of 32.
71637  */
71638 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
71639 
71640 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
71641 #define LPUART_BAUD_M10_SHIFT                    (29U)
71642 /*! M10 - 10-bit Mode select
71643  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
71644  *  0b1..Receiver and transmitter use 10-bit data characters.
71645  */
71646 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
71647 
71648 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
71649 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
71650 /*! MAEN2 - Match Address Mode Enable 2
71651  *  0b0..Normal operation.
71652  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
71653  */
71654 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
71655 
71656 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
71657 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
71658 /*! MAEN1 - Match Address Mode Enable 1
71659  *  0b0..Normal operation.
71660  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
71661  */
71662 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
71663 /*! @} */
71664 
71665 /*! @name STAT - LPUART Status Register */
71666 /*! @{ */
71667 
71668 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
71669 #define LPUART_STAT_MA2F_SHIFT                   (14U)
71670 /*! MA2F - Match 2 Flag
71671  *  0b0..Received data is not equal to MA2
71672  *  0b1..Received data is equal to MA2
71673  */
71674 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
71675 
71676 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
71677 #define LPUART_STAT_MA1F_SHIFT                   (15U)
71678 /*! MA1F - Match 1 Flag
71679  *  0b0..Received data is not equal to MA1
71680  *  0b1..Received data is equal to MA1
71681  */
71682 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
71683 
71684 #define LPUART_STAT_PF_MASK                      (0x10000U)
71685 #define LPUART_STAT_PF_SHIFT                     (16U)
71686 /*! PF - Parity Error Flag
71687  *  0b0..No parity error.
71688  *  0b1..Parity error.
71689  */
71690 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
71691 
71692 #define LPUART_STAT_FE_MASK                      (0x20000U)
71693 #define LPUART_STAT_FE_SHIFT                     (17U)
71694 /*! FE - Framing Error Flag
71695  *  0b0..No framing error detected. This does not guarantee the framing is correct.
71696  *  0b1..Framing error.
71697  */
71698 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
71699 
71700 #define LPUART_STAT_NF_MASK                      (0x40000U)
71701 #define LPUART_STAT_NF_SHIFT                     (18U)
71702 /*! NF - Noise Flag
71703  *  0b0..No noise detected.
71704  *  0b1..Noise detected in the received character in the DATA register.
71705  */
71706 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
71707 
71708 #define LPUART_STAT_OR_MASK                      (0x80000U)
71709 #define LPUART_STAT_OR_SHIFT                     (19U)
71710 /*! OR - Receiver Overrun Flag
71711  *  0b0..No overrun.
71712  *  0b1..Receive overrun (new LPUART data lost).
71713  */
71714 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
71715 
71716 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
71717 #define LPUART_STAT_IDLE_SHIFT                   (20U)
71718 /*! IDLE - Idle Line Flag
71719  *  0b0..No idle line detected.
71720  *  0b1..Idle line is detected.
71721  */
71722 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
71723 
71724 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
71725 #define LPUART_STAT_RDRF_SHIFT                   (21U)
71726 /*! RDRF - Receive Data Register Full Flag
71727  *  0b0..Receive FIFO level is less than watermark.
71728  *  0b1..Receive FIFO level is equal or greater than watermark.
71729  */
71730 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
71731 
71732 #define LPUART_STAT_TC_MASK                      (0x400000U)
71733 #define LPUART_STAT_TC_SHIFT                     (22U)
71734 /*! TC - Transmission Complete Flag
71735  *  0b0..Transmitter active (sending data, a preamble, or a break).
71736  *  0b1..Transmitter idle (transmission activity complete).
71737  */
71738 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
71739 
71740 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
71741 #define LPUART_STAT_TDRE_SHIFT                   (23U)
71742 /*! TDRE - Transmit Data Register Empty Flag
71743  *  0b0..Transmit FIFO level is greater than watermark.
71744  *  0b1..Transmit FIFO level is equal or less than watermark.
71745  */
71746 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
71747 
71748 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
71749 #define LPUART_STAT_RAF_SHIFT                    (24U)
71750 /*! RAF - Receiver Active Flag
71751  *  0b0..LPUART receiver idle waiting for a start bit.
71752  *  0b1..LPUART receiver active (RXD input not idle).
71753  */
71754 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
71755 
71756 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
71757 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
71758 /*! LBKDE - LIN Break Detection Enable
71759  *  0b0..LIN break detect is disabled, normal break character can be detected.
71760  *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
71761  */
71762 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
71763 
71764 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
71765 #define LPUART_STAT_BRK13_SHIFT                  (26U)
71766 /*! BRK13 - Break Character Generation Length
71767  *  0b0..Break character is transmitted with length of 9 to 13 bit times.
71768  *  0b1..Break character is transmitted with length of 12 to 15 bit times.
71769  */
71770 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
71771 
71772 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
71773 #define LPUART_STAT_RWUID_SHIFT                  (27U)
71774 /*! RWUID - Receive Wake Up Idle Detect
71775  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
71776  *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
71777  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
71778  *       address match wakeup, the IDLE bit does set when an address does not match.
71779  */
71780 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
71781 
71782 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
71783 #define LPUART_STAT_RXINV_SHIFT                  (28U)
71784 /*! RXINV - Receive Data Inversion
71785  *  0b0..Receive data not inverted.
71786  *  0b1..Receive data inverted.
71787  */
71788 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
71789 
71790 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
71791 #define LPUART_STAT_MSBF_SHIFT                   (29U)
71792 /*! MSBF - MSB First
71793  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
71794  *       after the start bit is identified as bit0.
71795  *  0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
71796  *       depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
71797  */
71798 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
71799 
71800 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
71801 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
71802 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
71803  *  0b0..No active edge on the receive pin has occurred.
71804  *  0b1..An active edge on the receive pin has occurred.
71805  */
71806 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
71807 
71808 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
71809 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
71810 /*! LBKDIF - LIN Break Detect Interrupt Flag
71811  *  0b0..No LIN break character has been detected.
71812  *  0b1..LIN break character has been detected.
71813  */
71814 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
71815 /*! @} */
71816 
71817 /*! @name CTRL - LPUART Control Register */
71818 /*! @{ */
71819 
71820 #define LPUART_CTRL_PT_MASK                      (0x1U)
71821 #define LPUART_CTRL_PT_SHIFT                     (0U)
71822 /*! PT - Parity Type
71823  *  0b0..Even parity.
71824  *  0b1..Odd parity.
71825  */
71826 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
71827 
71828 #define LPUART_CTRL_PE_MASK                      (0x2U)
71829 #define LPUART_CTRL_PE_SHIFT                     (1U)
71830 /*! PE - Parity Enable
71831  *  0b0..No hardware parity generation or checking.
71832  *  0b1..Parity enabled.
71833  */
71834 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
71835 
71836 #define LPUART_CTRL_ILT_MASK                     (0x4U)
71837 #define LPUART_CTRL_ILT_SHIFT                    (2U)
71838 /*! ILT - Idle Line Type Select
71839  *  0b0..Idle character bit count starts after start bit.
71840  *  0b1..Idle character bit count starts after stop bit.
71841  */
71842 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
71843 
71844 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
71845 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
71846 /*! WAKE - Receiver Wakeup Method Select
71847  *  0b0..Configures RWU for idle-line wakeup.
71848  *  0b1..Configures RWU with address-mark wakeup.
71849  */
71850 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
71851 
71852 #define LPUART_CTRL_M_MASK                       (0x10U)
71853 #define LPUART_CTRL_M_SHIFT                      (4U)
71854 /*! M - 9-Bit or 8-Bit Mode Select
71855  *  0b0..Receiver and transmitter use 8-bit data characters.
71856  *  0b1..Receiver and transmitter use 9-bit data characters.
71857  */
71858 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
71859 
71860 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
71861 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
71862 /*! RSRC - Receiver Source Select
71863  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
71864  *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
71865  */
71866 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
71867 
71868 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
71869 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
71870 /*! DOZEEN - Doze Enable
71871  *  0b0..LPUART is enabled in Doze mode.
71872  *  0b1..LPUART is disabled in Doze mode .
71873  */
71874 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
71875 
71876 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
71877 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
71878 /*! LOOPS - Loop Mode Select
71879  *  0b0..Normal operation - RXD and TXD use separate pins.
71880  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
71881  */
71882 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
71883 
71884 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
71885 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
71886 /*! IDLECFG - Idle Configuration
71887  *  0b000..1 idle character
71888  *  0b001..2 idle characters
71889  *  0b010..4 idle characters
71890  *  0b011..8 idle characters
71891  *  0b100..16 idle characters
71892  *  0b101..32 idle characters
71893  *  0b110..64 idle characters
71894  *  0b111..128 idle characters
71895  */
71896 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
71897 
71898 #define LPUART_CTRL_M7_MASK                      (0x800U)
71899 #define LPUART_CTRL_M7_SHIFT                     (11U)
71900 /*! M7 - 7-Bit Mode Select
71901  *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
71902  *  0b1..Receiver and transmitter use 7-bit data characters.
71903  */
71904 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
71905 
71906 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
71907 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
71908 /*! MA2IE - Match 2 Interrupt Enable
71909  *  0b0..MA2F interrupt disabled
71910  *  0b1..MA2F interrupt enabled
71911  */
71912 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
71913 
71914 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
71915 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
71916 /*! MA1IE - Match 1 Interrupt Enable
71917  *  0b0..MA1F interrupt disabled
71918  *  0b1..MA1F interrupt enabled
71919  */
71920 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
71921 
71922 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
71923 #define LPUART_CTRL_SBK_SHIFT                    (16U)
71924 /*! SBK - Send Break
71925  *  0b0..Normal transmitter operation.
71926  *  0b1..Queue break character(s) to be sent.
71927  */
71928 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
71929 
71930 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
71931 #define LPUART_CTRL_RWU_SHIFT                    (17U)
71932 /*! RWU - Receiver Wakeup Control
71933  *  0b0..Normal receiver operation.
71934  *  0b1..LPUART receiver in standby waiting for wakeup condition.
71935  */
71936 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
71937 
71938 #define LPUART_CTRL_RE_MASK                      (0x40000U)
71939 #define LPUART_CTRL_RE_SHIFT                     (18U)
71940 /*! RE - Receiver Enable
71941  *  0b0..Receiver disabled.
71942  *  0b1..Receiver enabled.
71943  */
71944 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
71945 
71946 #define LPUART_CTRL_TE_MASK                      (0x80000U)
71947 #define LPUART_CTRL_TE_SHIFT                     (19U)
71948 /*! TE - Transmitter Enable
71949  *  0b0..Transmitter disabled.
71950  *  0b1..Transmitter enabled.
71951  */
71952 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
71953 
71954 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
71955 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
71956 /*! ILIE - Idle Line Interrupt Enable
71957  *  0b0..Hardware interrupts from IDLE disabled; use polling.
71958  *  0b1..Hardware interrupt is requested when IDLE flag is 1.
71959  */
71960 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
71961 
71962 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
71963 #define LPUART_CTRL_RIE_SHIFT                    (21U)
71964 /*! RIE - Receiver Interrupt Enable
71965  *  0b0..Hardware interrupts from RDRF disabled.
71966  *  0b1..Hardware interrupt is requested when RDRF flag is 1.
71967  */
71968 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
71969 
71970 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
71971 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
71972 /*! TCIE - Transmission Complete Interrupt Enable for
71973  *  0b0..Hardware interrupts from TC disabled.
71974  *  0b1..Hardware interrupt is requested when TC flag is 1.
71975  */
71976 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
71977 
71978 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
71979 #define LPUART_CTRL_TIE_SHIFT                    (23U)
71980 /*! TIE - Transmit Interrupt Enable
71981  *  0b0..Hardware interrupts from TDRE disabled.
71982  *  0b1..Hardware interrupt is requested when TDRE flag is 1.
71983  */
71984 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
71985 
71986 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
71987 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
71988 /*! PEIE - Parity Error Interrupt Enable
71989  *  0b0..PF interrupts disabled; use polling).
71990  *  0b1..Hardware interrupt is requested when PF is set.
71991  */
71992 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
71993 
71994 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
71995 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
71996 /*! FEIE - Framing Error Interrupt Enable
71997  *  0b0..FE interrupts disabled; use polling.
71998  *  0b1..Hardware interrupt is requested when FE is set.
71999  */
72000 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
72001 
72002 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
72003 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
72004 /*! NEIE - Noise Error Interrupt Enable
72005  *  0b0..NF interrupts disabled; use polling.
72006  *  0b1..Hardware interrupt is requested when NF is set.
72007  */
72008 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
72009 
72010 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
72011 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
72012 /*! ORIE - Overrun Interrupt Enable
72013  *  0b0..OR interrupts disabled; use polling.
72014  *  0b1..Hardware interrupt is requested when OR is set.
72015  */
72016 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
72017 
72018 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
72019 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
72020 /*! TXINV - Transmit Data Inversion
72021  *  0b0..Transmit data not inverted.
72022  *  0b1..Transmit data inverted.
72023  */
72024 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
72025 
72026 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
72027 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
72028 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
72029  *  0b0..TXD pin is an input in single-wire mode.
72030  *  0b1..TXD pin is an output in single-wire mode.
72031  */
72032 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
72033 
72034 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
72035 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
72036 /*! R9T8 - Receive Bit 9 / Transmit Bit 8
72037  */
72038 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
72039 
72040 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
72041 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
72042 /*! R8T9 - Receive Bit 8 / Transmit Bit 9
72043  */
72044 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
72045 /*! @} */
72046 
72047 /*! @name DATA - LPUART Data Register */
72048 /*! @{ */
72049 
72050 #define LPUART_DATA_R0T0_MASK                    (0x1U)
72051 #define LPUART_DATA_R0T0_SHIFT                   (0U)
72052 /*! R0T0 - R0T0
72053  */
72054 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
72055 
72056 #define LPUART_DATA_R1T1_MASK                    (0x2U)
72057 #define LPUART_DATA_R1T1_SHIFT                   (1U)
72058 /*! R1T1 - R1T1
72059  */
72060 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
72061 
72062 #define LPUART_DATA_R2T2_MASK                    (0x4U)
72063 #define LPUART_DATA_R2T2_SHIFT                   (2U)
72064 /*! R2T2 - R2T2
72065  */
72066 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
72067 
72068 #define LPUART_DATA_R3T3_MASK                    (0x8U)
72069 #define LPUART_DATA_R3T3_SHIFT                   (3U)
72070 /*! R3T3 - R3T3
72071  */
72072 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
72073 
72074 #define LPUART_DATA_R4T4_MASK                    (0x10U)
72075 #define LPUART_DATA_R4T4_SHIFT                   (4U)
72076 /*! R4T4 - R4T4
72077  */
72078 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
72079 
72080 #define LPUART_DATA_R5T5_MASK                    (0x20U)
72081 #define LPUART_DATA_R5T5_SHIFT                   (5U)
72082 /*! R5T5 - R5T5
72083  */
72084 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
72085 
72086 #define LPUART_DATA_R6T6_MASK                    (0x40U)
72087 #define LPUART_DATA_R6T6_SHIFT                   (6U)
72088 /*! R6T6 - R6T6
72089  */
72090 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
72091 
72092 #define LPUART_DATA_R7T7_MASK                    (0x80U)
72093 #define LPUART_DATA_R7T7_SHIFT                   (7U)
72094 /*! R7T7 - R7T7
72095  */
72096 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
72097 
72098 #define LPUART_DATA_R8T8_MASK                    (0x100U)
72099 #define LPUART_DATA_R8T8_SHIFT                   (8U)
72100 /*! R8T8 - R8T8
72101  */
72102 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
72103 
72104 #define LPUART_DATA_R9T9_MASK                    (0x200U)
72105 #define LPUART_DATA_R9T9_SHIFT                   (9U)
72106 /*! R9T9 - R9T9
72107  */
72108 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
72109 
72110 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
72111 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
72112 /*! IDLINE - Idle Line
72113  *  0b0..Receiver was not idle before receiving this character.
72114  *  0b1..Receiver was idle before receiving this character.
72115  */
72116 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
72117 
72118 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
72119 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
72120 /*! RXEMPT - Receive Buffer Empty
72121  *  0b0..Receive buffer contains valid data.
72122  *  0b1..Receive buffer is empty, data returned on read is not valid.
72123  */
72124 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
72125 
72126 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
72127 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
72128 /*! FRETSC - Frame Error / Transmit Special Character
72129  *  0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
72130  *  0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
72131  */
72132 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
72133 
72134 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
72135 #define LPUART_DATA_PARITYE_SHIFT                (14U)
72136 /*! PARITYE - Parity Error
72137  *  0b0..The dataword is received without a parity error.
72138  *  0b1..The dataword is received with a parity error.
72139  */
72140 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
72141 
72142 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
72143 #define LPUART_DATA_NOISY_SHIFT                  (15U)
72144 /*! NOISY - Noisy Data Received
72145  *  0b0..The dataword is received without noise.
72146  *  0b1..The data is received with noise.
72147  */
72148 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
72149 /*! @} */
72150 
72151 /*! @name MATCH - LPUART Match Address Register */
72152 /*! @{ */
72153 
72154 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
72155 #define LPUART_MATCH_MA1_SHIFT                   (0U)
72156 /*! MA1 - Match Address 1
72157  */
72158 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
72159 
72160 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
72161 #define LPUART_MATCH_MA2_SHIFT                   (16U)
72162 /*! MA2 - Match Address 2
72163  */
72164 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
72165 /*! @} */
72166 
72167 /*! @name MODIR - LPUART Modem IrDA Register */
72168 /*! @{ */
72169 
72170 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
72171 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
72172 /*! TXCTSE - Transmitter clear-to-send enable
72173  *  0b0..CTS has no effect on the transmitter.
72174  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
72175  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
72176  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
72177  *       do not affect its transmission.
72178  */
72179 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
72180 
72181 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
72182 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
72183 /*! TXRTSE - Transmitter request-to-send enable
72184  *  0b0..The transmitter has no effect on RTS.
72185  *  0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
72186  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
72187  *       register are completely sent, including the last stop bit.
72188  */
72189 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
72190 
72191 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
72192 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
72193 /*! TXRTSPOL - Transmitter request-to-send polarity
72194  *  0b0..Transmitter RTS is active low.
72195  *  0b1..Transmitter RTS is active high.
72196  */
72197 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
72198 
72199 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
72200 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
72201 /*! RXRTSE - Receiver request-to-send enable
72202  *  0b0..The receiver has no effect on RTS.
72203  *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
72204  *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
72205  *       has not detected a start bit that would cause the receiver data register to become full.
72206  */
72207 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
72208 
72209 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
72210 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
72211 /*! TXCTSC - Transmit CTS Configuration
72212  *  0b0..CTS input is sampled at the start of each character.
72213  *  0b1..CTS input is sampled when the transmitter is idle.
72214  */
72215 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
72216 
72217 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
72218 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
72219 /*! TXCTSSRC - Transmit CTS Source
72220  *  0b0..CTS input is the CTS_B pin.
72221  *  0b1..CTS input is an internal connection to the receiver address match result.
72222  */
72223 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
72224 
72225 #define LPUART_MODIR_RTSWATER_MASK               (0x300U)
72226 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
72227 /*! RTSWATER - Receive RTS Configuration
72228  */
72229 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
72230 
72231 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
72232 #define LPUART_MODIR_TNP_SHIFT                   (16U)
72233 /*! TNP - Transmitter narrow pulse
72234  *  0b00..1/OSR.
72235  *  0b01..2/OSR.
72236  *  0b10..3/OSR.
72237  *  0b11..4/OSR.
72238  */
72239 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
72240 
72241 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
72242 #define LPUART_MODIR_IREN_SHIFT                  (18U)
72243 /*! IREN - Infrared enable
72244  *  0b0..IR disabled.
72245  *  0b1..IR enabled.
72246  */
72247 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
72248 /*! @} */
72249 
72250 /*! @name FIFO - LPUART FIFO Register */
72251 /*! @{ */
72252 
72253 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
72254 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
72255 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
72256  *  0b000..Receive FIFO/Buffer depth = 1 dataword.
72257  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
72258  *  0b010..Receive FIFO/Buffer depth = 8 datawords.
72259  *  0b011..Receive FIFO/Buffer depth = 16 datawords.
72260  *  0b100..Receive FIFO/Buffer depth = 32 datawords.
72261  *  0b101..Receive FIFO/Buffer depth = 64 datawords.
72262  *  0b110..Receive FIFO/Buffer depth = 128 datawords.
72263  *  0b111..Receive FIFO/Buffer depth = 256 datawords.
72264  */
72265 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
72266 
72267 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
72268 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
72269 /*! RXFE - Receive FIFO Enable
72270  *  0b0..Receive FIFO is not enabled. Buffer depth is 1.
72271  *  0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
72272  */
72273 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
72274 
72275 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
72276 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
72277 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
72278  *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
72279  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
72280  *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
72281  *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
72282  *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
72283  *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
72284  *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
72285  *  0b111..Transmit FIFO/Buffer depth = 256 datawords
72286  */
72287 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
72288 
72289 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
72290 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
72291 /*! TXFE - Transmit FIFO Enable
72292  *  0b0..Transmit FIFO is not enabled. Buffer depth is 1.
72293  *  0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
72294  */
72295 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
72296 
72297 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
72298 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
72299 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
72300  *  0b0..RXUF flag does not generate an interrupt to the host.
72301  *  0b1..RXUF flag generates an interrupt to the host.
72302  */
72303 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
72304 
72305 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
72306 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
72307 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
72308  *  0b0..TXOF flag does not generate an interrupt to the host.
72309  *  0b1..TXOF flag generates an interrupt to the host.
72310  */
72311 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
72312 
72313 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
72314 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
72315 /*! RXIDEN - Receiver Idle Empty Enable
72316  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
72317  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
72318  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
72319  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
72320  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
72321  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
72322  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
72323  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
72324  */
72325 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
72326 
72327 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
72328 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
72329 /*! RXFLUSH - Receive FIFO Flush
72330  *  0b0..No flush operation occurs.
72331  *  0b1..All data in the receive FIFO/buffer is cleared out.
72332  */
72333 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
72334 
72335 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
72336 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
72337 /*! TXFLUSH - Transmit FIFO Flush
72338  *  0b0..No flush operation occurs.
72339  *  0b1..All data in the transmit FIFO is cleared out.
72340  */
72341 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
72342 
72343 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
72344 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
72345 /*! RXUF - Receiver FIFO Underflow Flag
72346  *  0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
72347  *  0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
72348  */
72349 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
72350 
72351 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
72352 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
72353 /*! TXOF - Transmitter FIFO Overflow Flag
72354  *  0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
72355  *  0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
72356  */
72357 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
72358 
72359 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
72360 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
72361 /*! RXEMPT - Receive FIFO/Buffer Empty
72362  *  0b0..Receive buffer is not empty.
72363  *  0b1..Receive buffer is empty.
72364  */
72365 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
72366 
72367 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
72368 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
72369 /*! TXEMPT - Transmit FIFO/Buffer Empty
72370  *  0b0..Transmit buffer is not empty.
72371  *  0b1..Transmit buffer is empty.
72372  */
72373 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
72374 /*! @} */
72375 
72376 /*! @name WATER - LPUART Watermark Register */
72377 /*! @{ */
72378 
72379 #define LPUART_WATER_TXWATER_MASK                (0x3U)
72380 #define LPUART_WATER_TXWATER_SHIFT               (0U)
72381 /*! TXWATER - Transmit Watermark
72382  */
72383 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
72384 
72385 #define LPUART_WATER_TXCOUNT_MASK                (0x700U)
72386 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
72387 /*! TXCOUNT - Transmit Counter
72388  */
72389 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
72390 
72391 #define LPUART_WATER_RXWATER_MASK                (0x30000U)
72392 #define LPUART_WATER_RXWATER_SHIFT               (16U)
72393 /*! RXWATER - Receive Watermark
72394  */
72395 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
72396 
72397 #define LPUART_WATER_RXCOUNT_MASK                (0x7000000U)
72398 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
72399 /*! RXCOUNT - Receive Counter
72400  */
72401 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
72402 /*! @} */
72403 
72404 
72405 /*!
72406  * @}
72407  */ /* end of group LPUART_Register_Masks */
72408 
72409 
72410 /* LPUART - Peripheral instance base addresses */
72411 /** Peripheral LPUART1 base address */
72412 #define LPUART1_BASE                             (0x4007C000u)
72413 /** Peripheral LPUART1 base pointer */
72414 #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
72415 /** Peripheral LPUART2 base address */
72416 #define LPUART2_BASE                             (0x40080000u)
72417 /** Peripheral LPUART2 base pointer */
72418 #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
72419 /** Peripheral LPUART3 base address */
72420 #define LPUART3_BASE                             (0x40084000u)
72421 /** Peripheral LPUART3 base pointer */
72422 #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
72423 /** Peripheral LPUART4 base address */
72424 #define LPUART4_BASE                             (0x40088000u)
72425 /** Peripheral LPUART4 base pointer */
72426 #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
72427 /** Peripheral LPUART5 base address */
72428 #define LPUART5_BASE                             (0x4008C000u)
72429 /** Peripheral LPUART5 base pointer */
72430 #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
72431 /** Peripheral LPUART6 base address */
72432 #define LPUART6_BASE                             (0x40090000u)
72433 /** Peripheral LPUART6 base pointer */
72434 #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
72435 /** Peripheral LPUART7 base address */
72436 #define LPUART7_BASE                             (0x40094000u)
72437 /** Peripheral LPUART7 base pointer */
72438 #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
72439 /** Peripheral LPUART8 base address */
72440 #define LPUART8_BASE                             (0x40098000u)
72441 /** Peripheral LPUART8 base pointer */
72442 #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
72443 /** Peripheral LPUART9 base address */
72444 #define LPUART9_BASE                             (0x4009C000u)
72445 /** Peripheral LPUART9 base pointer */
72446 #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
72447 /** Peripheral LPUART10 base address */
72448 #define LPUART10_BASE                            (0x400A0000u)
72449 /** Peripheral LPUART10 base pointer */
72450 #define LPUART10                                 ((LPUART_Type *)LPUART10_BASE)
72451 /** Peripheral LPUART11 base address */
72452 #define LPUART11_BASE                            (0x40C24000u)
72453 /** Peripheral LPUART11 base pointer */
72454 #define LPUART11                                 ((LPUART_Type *)LPUART11_BASE)
72455 /** Peripheral LPUART12 base address */
72456 #define LPUART12_BASE                            (0x40C28000u)
72457 /** Peripheral LPUART12 base pointer */
72458 #define LPUART12                                 ((LPUART_Type *)LPUART12_BASE)
72459 /** Array initializer of LPUART peripheral base addresses */
72460 #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
72461 /** Array initializer of LPUART peripheral base pointers */
72462 #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
72463 /** Interrupt vectors for the LPUART peripheral type */
72464 #define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
72465 
72466 /*!
72467  * @}
72468  */ /* end of group LPUART_Peripheral_Access_Layer */
72469 
72470 
72471 /* ----------------------------------------------------------------------------
72472    -- MCM Peripheral Access Layer
72473    ---------------------------------------------------------------------------- */
72474 
72475 /*!
72476  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
72477  * @{
72478  */
72479 
72480 /** MCM - Register Layout Typedef */
72481 typedef struct {
72482   __I  uint16_t PLREV;                             /**< SoC-defined platform revision, offset: 0x0 */
72483   __I  uint16_t PCT;                               /**< Processor core type, offset: 0x2 */
72484   __I  uint32_t MEMCFG;                            /**< Memory configuration, offset: 0x4 */
72485   __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
72486   __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
72487   __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
72488   __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
72489        uint8_t RESERVED_0[12];
72490   __I  uint32_t FADR;                              /**< Fault address register, offset: 0x20 */
72491   __I  uint32_t FATR;                              /**< Fault attributes register, offset: 0x24 */
72492   __I  uint32_t FDR;                               /**< Fault data register, offset: 0x28 */
72493        uint8_t RESERVED_1[980];
72494   __IO uint32_t LMDR[4];                           /**< Local Memory Descriptor Register, array offset: 0x400, array step: 0x4 */
72495        uint8_t RESERVED_2[112];
72496   __IO uint32_t LMPECR;                            /**< LMEM Parity & ECC Control Register, offset: 0x480 */
72497        uint8_t RESERVED_3[4];
72498   __IO uint32_t LMPEIR;                            /**< LMEM Parity & ECC Interrupt Register, offset: 0x488 */
72499        uint8_t RESERVED_4[4];
72500   __I  uint32_t LMFAR;                             /**< LMEM Fault Address Register, offset: 0x490 */
72501   __IO uint32_t LMFATR;                            /**< LMEM Fault Attribute Register, offset: 0x494 */
72502        uint8_t RESERVED_5[8];
72503   __I  uint32_t LMFDHR;                            /**< LMEM Fault Data High Register, offset: 0x4A0 */
72504   __I  uint32_t LMFDLR;                            /**< LMEM Fault Data Low Register, offset: 0x4A4 */
72505 } MCM_Type;
72506 
72507 /* ----------------------------------------------------------------------------
72508    -- MCM Register Masks
72509    ---------------------------------------------------------------------------- */
72510 
72511 /*!
72512  * @addtogroup MCM_Register_Masks MCM Register Masks
72513  * @{
72514  */
72515 
72516 /*! @name PLREV - SoC-defined platform revision */
72517 /*! @{ */
72518 
72519 #define MCM_PLREV_PLREV_MASK                     (0xFFFFU)
72520 #define MCM_PLREV_PLREV_SHIFT                    (0U)
72521 /*! PLREV - The PLREV[15:0] field is specified by an platform input signal to define a software-visible revision number.
72522  */
72523 #define MCM_PLREV_PLREV(x)                       (((uint16_t)(((uint16_t)(x)) << MCM_PLREV_PLREV_SHIFT)) & MCM_PLREV_PLREV_MASK)
72524 /*! @} */
72525 
72526 /*! @name PCT - Processor core type */
72527 /*! @{ */
72528 
72529 #define MCM_PCT_PCT_MASK                         (0xFFFFU)
72530 #define MCM_PCT_PCT_SHIFT                        (0U)
72531 /*! PCT - This MCM design supports the ARM Cortex M4 core. The following value identifies this core complex.
72532  *  0b1010110001000000..ARM Cortex M4
72533  */
72534 #define MCM_PCT_PCT(x)                           (((uint16_t)(((uint16_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK)
72535 /*! @} */
72536 
72537 /*! @name MEMCFG - Memory configuration */
72538 /*! @{ */
72539 
72540 #define MCM_MEMCFG_TCRAMUSZ_MASK                 (0x3CU)
72541 #define MCM_MEMCFG_TCRAMUSZ_SHIFT                (2U)
72542 /*! TCRAMUSZ - TCRAMU size
72543  */
72544 #define MCM_MEMCFG_TCRAMUSZ(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMUSZ_SHIFT)) & MCM_MEMCFG_TCRAMUSZ_MASK)
72545 
72546 #define MCM_MEMCFG_TCRAMLSZ_MASK                 (0xF00U)
72547 #define MCM_MEMCFG_TCRAMLSZ_SHIFT                (8U)
72548 /*! TCRAMLSZ - TCRAML size
72549  */
72550 #define MCM_MEMCFG_TCRAMLSZ(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMLSZ_SHIFT)) & MCM_MEMCFG_TCRAMLSZ_MASK)
72551 /*! @} */
72552 
72553 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
72554 /*! @{ */
72555 
72556 #define MCM_PLASC_ASC_MASK                       (0xFFU)
72557 #define MCM_PLASC_ASC_SHIFT                      (0U)
72558 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the
72559  *    crossbar switch's slave input port.
72560  *  0b00000000..A bus slave connection to AXBS input port n is absent
72561  *  0b00000001..A bus slave connection to AXBS input port n is present
72562  */
72563 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
72564 /*! @} */
72565 
72566 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
72567 /*! @{ */
72568 
72569 #define MCM_PLAMC_AMC_MASK                       (0xFFU)
72570 #define MCM_PLAMC_AMC_SHIFT                      (0U)
72571 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
72572  *  0b00000000..A bus master connection to AXBS input port n is absent
72573  *  0b00000001..A bus master connection to AXBS input port n is present
72574  */
72575 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
72576 /*! @} */
72577 
72578 /*! @name CR - Control Register */
72579 /*! @{ */
72580 
72581 #define MCM_CR_STATUS_MASK                       (0x1FFU)
72582 #define MCM_CR_STATUS_SHIFT                      (0U)
72583 /*! STATUS - Status bits
72584  */
72585 #define MCM_CR_STATUS(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CR_STATUS_SHIFT)) & MCM_CR_STATUS_MASK)
72586 
72587 #define MCM_CR_CBRR_MASK                         (0x200U)
72588 #define MCM_CR_CBRR_SHIFT                        (9U)
72589 /*! CBRR - Crossbar round-robin arbitration enable
72590  *  0b0..Fixed-priority arbitration
72591  *  0b1..Round-robin arbitration
72592  */
72593 #define MCM_CR_CBRR(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_CR_CBRR_SHIFT)) & MCM_CR_CBRR_MASK)
72594 
72595 #define MCM_CR_STCMAP_MASK                       (0x3000000U)
72596 #define MCM_CR_STCMAP_SHIFT                      (24U)
72597 /*! STCMAP - System TCM arbitration priority
72598  *  0b00..Round robin
72599  *  0b01..Special round robin (favors TCM backoor accesses over the processor)
72600  *  0b10..Fixed priority. Processor has highest, backdoor has lowest
72601  *  0b11..Fixed priority. Backdoor has highest, processor has lowest
72602  */
72603 #define MCM_CR_STCMAP(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMAP_SHIFT)) & MCM_CR_STCMAP_MASK)
72604 
72605 #define MCM_CR_STCMWP_MASK                       (0x4000000U)
72606 #define MCM_CR_STCMWP_SHIFT                      (26U)
72607 /*! STCMWP - System TCM write protect
72608  */
72609 #define MCM_CR_STCMWP(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMWP_SHIFT)) & MCM_CR_STCMWP_MASK)
72610 
72611 #define MCM_CR_CTCMAP_MASK                       (0x30000000U)
72612 #define MCM_CR_CTCMAP_SHIFT                      (28U)
72613 /*! CTCMAP - Code TCM arbitration priority
72614  *  0b00..Round robin
72615  *  0b01..Special round robin (favors TCM backoor accesses over the processor)
72616  *  0b10..Fixed priority. Processor has highest, backdoor has lowest
72617  *  0b11..Fixed priority. Backdoor has highest, processor has lowest
72618  */
72619 #define MCM_CR_CTCMAP(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMAP_SHIFT)) & MCM_CR_CTCMAP_MASK)
72620 
72621 #define MCM_CR_CTCMWP_MASK                       (0x40000000U)
72622 #define MCM_CR_CTCMWP_SHIFT                      (30U)
72623 /*! CTCMWP - Code TCM Write Protect
72624  */
72625 #define MCM_CR_CTCMWP(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMWP_SHIFT)) & MCM_CR_CTCMWP_MASK)
72626 /*! @} */
72627 
72628 /*! @name ISCR - Interrupt Status and Control Register */
72629 /*! @{ */
72630 
72631 #define MCM_ISCR_CWBER_MASK                      (0x10U)
72632 #define MCM_ISCR_CWBER_SHIFT                     (4U)
72633 /*! CWBER - Cache write buffer error status
72634  *  0b0..No error
72635  *  0b1..Error occurred
72636  */
72637 #define MCM_ISCR_CWBER(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK)
72638 
72639 #define MCM_ISCR_FIOC_MASK                       (0x100U)
72640 #define MCM_ISCR_FIOC_SHIFT                      (8U)
72641 /*! FIOC - FPU invalid operation interrupt status
72642  *  0b0..No interrupt
72643  *  0b1..Interrupt occurred
72644  */
72645 #define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
72646 
72647 #define MCM_ISCR_FDZC_MASK                       (0x200U)
72648 #define MCM_ISCR_FDZC_SHIFT                      (9U)
72649 /*! FDZC - FPU divide-by-zero interrupt status
72650  *  0b0..No interrupt
72651  *  0b1..Interrupt occurred
72652  */
72653 #define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
72654 
72655 #define MCM_ISCR_FOFC_MASK                       (0x400U)
72656 #define MCM_ISCR_FOFC_SHIFT                      (10U)
72657 /*! FOFC - FPU overflow interrupt status
72658  *  0b0..No interrupt
72659  *  0b1..Interrupt occurred
72660  */
72661 #define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
72662 
72663 #define MCM_ISCR_FUFC_MASK                       (0x800U)
72664 #define MCM_ISCR_FUFC_SHIFT                      (11U)
72665 /*! FUFC - FPU underflow interrupt status
72666  *  0b0..No interrupt
72667  *  0b1..Interrupt occurred
72668  */
72669 #define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
72670 
72671 #define MCM_ISCR_FIXC_MASK                       (0x1000U)
72672 #define MCM_ISCR_FIXC_SHIFT                      (12U)
72673 /*! FIXC - FPU inexact interrupt status
72674  *  0b0..No interrupt
72675  *  0b1..Interrupt occurred
72676  */
72677 #define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
72678 
72679 #define MCM_ISCR_FIDC_MASK                       (0x8000U)
72680 #define MCM_ISCR_FIDC_SHIFT                      (15U)
72681 /*! FIDC - FPU input denormal interrupt status
72682  *  0b0..No interrupt
72683  *  0b1..Interrupt occurred
72684  */
72685 #define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
72686 
72687 #define MCM_ISCR_CWBEE_MASK                      (0x100000U)
72688 #define MCM_ISCR_CWBEE_SHIFT                     (20U)
72689 /*! CWBEE - Cache write buffer error enable
72690  *  0b0..Disable error interrupt
72691  *  0b1..Enable error interrupt
72692  */
72693 #define MCM_ISCR_CWBEE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK)
72694 
72695 #define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
72696 #define MCM_ISCR_FIOCE_SHIFT                     (24U)
72697 /*! FIOCE - FPU invalid operation interrupt enable
72698  *  0b0..Disable interrupt
72699  *  0b1..Enable interrupt
72700  */
72701 #define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
72702 
72703 #define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
72704 #define MCM_ISCR_FDZCE_SHIFT                     (25U)
72705 /*! FDZCE - FPU divide-by-zero interrupt enable
72706  *  0b0..Disable interrupt
72707  *  0b1..Enable interrupt
72708  */
72709 #define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
72710 
72711 #define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
72712 #define MCM_ISCR_FOFCE_SHIFT                     (26U)
72713 /*! FOFCE - FPU overflow interrupt enable
72714  *  0b0..Disable interrupt
72715  *  0b1..Enable interrupt
72716  */
72717 #define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
72718 
72719 #define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
72720 #define MCM_ISCR_FUFCE_SHIFT                     (27U)
72721 /*! FUFCE - FPU underflow interrupt enable
72722  *  0b0..Disable interrupt
72723  *  0b1..Enable interrupt
72724  */
72725 #define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
72726 
72727 #define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
72728 #define MCM_ISCR_FIXCE_SHIFT                     (28U)
72729 /*! FIXCE - FPU inexact interrupt enable
72730  *  0b0..Disable interrupt
72731  *  0b1..Enable interrupt
72732  */
72733 #define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
72734 
72735 #define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
72736 #define MCM_ISCR_FIDCE_SHIFT                     (31U)
72737 /*! FIDCE - FPU input denormal interrupt enable
72738  *  0b0..Disable interrupt
72739  *  0b1..Enable interrupt
72740  */
72741 #define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
72742 /*! @} */
72743 
72744 /*! @name FADR - Fault address register */
72745 /*! @{ */
72746 
72747 #define MCM_FADR_ADDRESS_MASK                    (0xFFFFFFFFU)
72748 #define MCM_FADR_ADDRESS_SHIFT                   (0U)
72749 /*! ADDRESS - Fault address
72750  */
72751 #define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
72752 /*! @} */
72753 
72754 /*! @name FATR - Fault attributes register */
72755 /*! @{ */
72756 
72757 #define MCM_FATR_BEDA_MASK                       (0x1U)
72758 #define MCM_FATR_BEDA_SHIFT                      (0U)
72759 /*! BEDA - Bus error access type
72760  *  0b0..Instruction
72761  *  0b1..Data
72762  */
72763 #define MCM_FATR_BEDA(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
72764 
72765 #define MCM_FATR_BEMD_MASK                       (0x2U)
72766 #define MCM_FATR_BEMD_SHIFT                      (1U)
72767 /*! BEMD - Bus error privilege level
72768  *  0b0..User mode
72769  *  0b1..Supervisor/privileged mode
72770  */
72771 #define MCM_FATR_BEMD(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
72772 
72773 #define MCM_FATR_BESZ_MASK                       (0x30U)
72774 #define MCM_FATR_BESZ_SHIFT                      (4U)
72775 /*! BESZ - Bus error size
72776  *  0b00..8-bit access
72777  *  0b01..16-bit access
72778  *  0b10..32-bit access
72779  *  0b11..Reserved
72780  */
72781 #define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
72782 
72783 #define MCM_FATR_BEWT_MASK                       (0x80U)
72784 #define MCM_FATR_BEWT_SHIFT                      (7U)
72785 /*! BEWT - Bus error write
72786  *  0b0..Read access
72787  *  0b1..Write access
72788  */
72789 #define MCM_FATR_BEWT(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
72790 
72791 #define MCM_FATR_BEMN_MASK                       (0xF00U)
72792 #define MCM_FATR_BEMN_SHIFT                      (8U)
72793 /*! BEMN - Bus error master number
72794  */
72795 #define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
72796 
72797 #define MCM_FATR_BEOVR_MASK                      (0x80000000U)
72798 #define MCM_FATR_BEOVR_SHIFT                     (31U)
72799 /*! BEOVR - Bus error overrun
72800  *  0b0..No bus error overrun
72801  *  0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
72802  */
72803 #define MCM_FATR_BEOVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
72804 /*! @} */
72805 
72806 /*! @name FDR - Fault data register */
72807 /*! @{ */
72808 
72809 #define MCM_FDR_DATA_MASK                        (0xFFFFFFFFU)
72810 #define MCM_FDR_DATA_SHIFT                       (0U)
72811 /*! DATA - Fault data
72812  */
72813 #define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
72814 /*! @} */
72815 
72816 /*! @name LMDR - Local Memory Descriptor Register */
72817 /*! @{ */
72818 
72819 #define MCM_LMDR_CF0_MASK                        (0xFU)
72820 #define MCM_LMDR_CF0_SHIFT                       (0U)
72821 /*! CF0 - Control Field 0
72822  */
72823 #define MCM_LMDR_CF0(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK)
72824 
72825 #define MCM_LMDR_CF1_MASK                        (0xF0U)
72826 #define MCM_LMDR_CF1_SHIFT                       (4U)
72827 /*! CF1 - Control Field 1 - for Cache Parity control functions
72828  */
72829 #define MCM_LMDR_CF1(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF1_SHIFT)) & MCM_LMDR_CF1_MASK)
72830 
72831 #define MCM_LMDR_MT_MASK                         (0xE000U)
72832 #define MCM_LMDR_MT_SHIFT                        (13U)
72833 /*! MT - Memory Type
72834  *  0b000..code TCM
72835  *  0b001..system TCM
72836  *  0b010..PC Cache
72837  *  0b011..PS Cache
72838  */
72839 #define MCM_LMDR_MT(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK)
72840 
72841 #define MCM_LMDR_RO_MASK                         (0x10000U)
72842 #define MCM_LMDR_RO_SHIFT                        (16U)
72843 /*! RO
72844  *  0b0..Writes to the LMDRn[7:0] are allowed.
72845  *  0b1..Writes to the LMDRn[7:0] are ignored.
72846  */
72847 #define MCM_LMDR_RO(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_RO_SHIFT)) & MCM_LMDR_RO_MASK)
72848 
72849 #define MCM_LMDR_DPW_MASK                        (0xE0000U)
72850 #define MCM_LMDR_DPW_SHIFT                       (17U)
72851 /*! DPW
72852  *  0b010..LMEMn 32-bits wide
72853  *  0b011..LMEMn 64-bits wide
72854  */
72855 #define MCM_LMDR_DPW(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK)
72856 
72857 #define MCM_LMDR_WY_MASK                         (0xF00000U)
72858 #define MCM_LMDR_WY_SHIFT                        (20U)
72859 /*! WY - Level 1 Cache Ways
72860  *  0b0000..No Cache
72861  *  0b0010..2-Way Set Associative
72862  *  0b0100..4-Way Set Associative
72863  */
72864 #define MCM_LMDR_WY(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK)
72865 
72866 #define MCM_LMDR_LMSZ_MASK                       (0xF000000U)
72867 #define MCM_LMDR_LMSZ_SHIFT                      (24U)
72868 /*! LMSZ
72869  *  0b0000..no LMEMn (0 KB)
72870  *  0b0001..1 KB LMEMn
72871  *  0b0010..2 KB LMEMn
72872  *  0b0011..4 KB LMEMn
72873  *  0b0100..8 KB LMEMn
72874  *  0b0101..16 KB LMEMn
72875  *  0b0110..32 KB LMEMn
72876  *  0b0111..64 KB LMEMn
72877  *  0b1000..128 KB LMEMn
72878  *  0b1001..256 KB LMEMn
72879  *  0b1010..512 KB LMEMn
72880  *  0b1011..1024 KB LMEMn
72881  *  0b1100..2048 KB LMEMn
72882  *  0b1101..4096 KB LMEMn
72883  *  0b1110..8192 KB LMEMn
72884  *  0b1111..16384 KB LMEMn
72885  */
72886 #define MCM_LMDR_LMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK)
72887 
72888 #define MCM_LMDR_LMSZH_MASK                      (0x10000000U)
72889 #define MCM_LMDR_LMSZH_SHIFT                     (28U)
72890 /*! LMSZH
72891  *  0b0..LMEMn is a power-of-2 capacity.
72892  *  0b1..LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ.
72893  */
72894 #define MCM_LMDR_LMSZH(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK)
72895 
72896 #define MCM_LMDR_V_MASK                          (0x80000000U)
72897 #define MCM_LMDR_V_SHIFT                         (31U)
72898 /*! V
72899  *  0b0..LMEMn is not present.
72900  *  0b1..LMEMn is present.
72901  */
72902 #define MCM_LMDR_V(x)                            (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK)
72903 /*! @} */
72904 
72905 /* The count of MCM_LMDR */
72906 #define MCM_LMDR_COUNT                           (4U)
72907 
72908 /*! @name LMPECR - LMEM Parity & ECC Control Register */
72909 /*! @{ */
72910 
72911 #define MCM_LMPECR_ERNCR_MASK                    (0x1U)
72912 #define MCM_LMPECR_ERNCR_SHIFT                   (0U)
72913 /*! ERNCR - Enable RAM ECC Non-correctable Reporting
72914  *  0b0..reporting enabled
72915  *  0b1..reporting disabled
72916  */
72917 #define MCM_LMPECR_ERNCR(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCR_SHIFT)) & MCM_LMPECR_ERNCR_MASK)
72918 
72919 #define MCM_LMPECR_ERNCI_MASK                    (0x2U)
72920 #define MCM_LMPECR_ERNCI_SHIFT                   (1U)
72921 /*! ERNCI
72922  *  0b0..Interrupt is disabled
72923  *  0b1..Interrupt is enabled
72924  */
72925 #define MCM_LMPECR_ERNCI(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCI_SHIFT)) & MCM_LMPECR_ERNCI_MASK)
72926 
72927 #define MCM_LMPECR_ER1BR_MASK                    (0x100U)
72928 #define MCM_LMPECR_ER1BR_SHIFT                   (8U)
72929 /*! ER1BR - Enable RAM ECC 1-bit Reporting
72930  *  0b0..reporting enabled
72931  *  0b1..reporting disabled
72932  */
72933 #define MCM_LMPECR_ER1BR(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BR_SHIFT)) & MCM_LMPECR_ER1BR_MASK)
72934 
72935 #define MCM_LMPECR_ER1BI_MASK                    (0x200U)
72936 #define MCM_LMPECR_ER1BI_SHIFT                   (9U)
72937 /*! ER1BI - Enable RAM ECC 1-bit Interrupt
72938  *  0b0..Interrupt is disabled
72939  *  0b1..Interrupt is enabled
72940  */
72941 #define MCM_LMPECR_ER1BI(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BI_SHIFT)) & MCM_LMPECR_ER1BI_MASK)
72942 
72943 #define MCM_LMPECR_ECPR_MASK                     (0x100000U)
72944 #define MCM_LMPECR_ECPR_SHIFT                    (20U)
72945 /*! ECPR - Enable Cache Parity Reporting
72946  *  0b0..reporting enabled
72947  *  0b1..reporting disabled
72948  */
72949 #define MCM_LMPECR_ECPR(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK)
72950 
72951 #define MCM_LMPECR_ECPI_MASK                     (0x200000U)
72952 #define MCM_LMPECR_ECPI_SHIFT                    (21U)
72953 /*! ECPI - Enable Cache Parity IRQ
72954  *  0b0..enabled
72955  *  0b1..disabled
72956  */
72957 #define MCM_LMPECR_ECPI(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPI_SHIFT)) & MCM_LMPECR_ECPI_MASK)
72958 /*! @} */
72959 
72960 /*! @name LMPEIR - LMEM Parity & ECC Interrupt Register */
72961 /*! @{ */
72962 
72963 #define MCM_LMPEIR_ENC_MASK                      (0xFFU)
72964 #define MCM_LMPEIR_ENC_SHIFT                     (0U)
72965 /*! ENC - ENCn = ECC Non-correctable Error n
72966  */
72967 #define MCM_LMPEIR_ENC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK)
72968 
72969 #define MCM_LMPEIR_E1B_MASK                      (0xFF00U)
72970 #define MCM_LMPEIR_E1B_SHIFT                     (8U)
72971 /*! E1B - E1Bn = ECC 1-bit Error n
72972  */
72973 #define MCM_LMPEIR_E1B(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK)
72974 
72975 #define MCM_LMPEIR_PE_MASK                       (0xFF0000U)
72976 #define MCM_LMPEIR_PE_SHIFT                      (16U)
72977 /*! PE - Parity Error
72978  */
72979 #define MCM_LMPEIR_PE(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK)
72980 
72981 #define MCM_LMPEIR_PEELOC_MASK                   (0x1F000000U)
72982 #define MCM_LMPEIR_PEELOC_SHIFT                  (24U)
72983 #define MCM_LMPEIR_PEELOC(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK)
72984 
72985 #define MCM_LMPEIR_V_MASK                        (0x80000000U)
72986 #define MCM_LMPEIR_V_SHIFT                       (31U)
72987 /*! V - Valid bit
72988  */
72989 #define MCM_LMPEIR_V(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK)
72990 /*! @} */
72991 
72992 /*! @name LMFAR - LMEM Fault Address Register */
72993 /*! @{ */
72994 
72995 #define MCM_LMFAR_EFADD_MASK                     (0xFFFFFFFFU)
72996 #define MCM_LMFAR_EFADD_SHIFT                    (0U)
72997 /*! EFADD - ECC Fault Address
72998  */
72999 #define MCM_LMFAR_EFADD(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK)
73000 /*! @} */
73001 
73002 /*! @name LMFATR - LMEM Fault Attribute Register */
73003 /*! @{ */
73004 
73005 #define MCM_LMFATR_PEFPRT_MASK                   (0xFU)
73006 #define MCM_LMFATR_PEFPRT_SHIFT                  (0U)
73007 #define MCM_LMFATR_PEFPRT(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK)
73008 
73009 #define MCM_LMFATR_PEFSIZE_MASK                  (0x70U)
73010 #define MCM_LMFATR_PEFSIZE_SHIFT                 (4U)
73011 #define MCM_LMFATR_PEFSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK)
73012 
73013 #define MCM_LMFATR_PEFW_MASK                     (0x80U)
73014 #define MCM_LMFATR_PEFW_SHIFT                    (7U)
73015 #define MCM_LMFATR_PEFW(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK)
73016 
73017 #define MCM_LMFATR_PEFMST_MASK                   (0xFF00U)
73018 #define MCM_LMFATR_PEFMST_SHIFT                  (8U)
73019 #define MCM_LMFATR_PEFMST(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFMST_SHIFT)) & MCM_LMFATR_PEFMST_MASK)
73020 
73021 #define MCM_LMFATR_WORDID_MASK                   (0x1000000U)
73022 #define MCM_LMFATR_WORDID_SHIFT                  (24U)
73023 #define MCM_LMFATR_WORDID(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_WORDID_SHIFT)) & MCM_LMFATR_WORDID_MASK)
73024 
73025 #define MCM_LMFATR_OVR_MASK                      (0x80000000U)
73026 #define MCM_LMFATR_OVR_SHIFT                     (31U)
73027 /*! OVR - Overrun
73028  */
73029 #define MCM_LMFATR_OVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK)
73030 /*! @} */
73031 
73032 /*! @name LMFDHR - LMEM Fault Data High Register */
73033 /*! @{ */
73034 
73035 #define MCM_LMFDHR_PEFDH_MASK                    (0xFFFFFFFFU)
73036 #define MCM_LMFDHR_PEFDH_SHIFT                   (0U)
73037 #define MCM_LMFDHR_PEFDH(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK)
73038 /*! @} */
73039 
73040 /*! @name LMFDLR - LMEM Fault Data Low Register */
73041 /*! @{ */
73042 
73043 #define MCM_LMFDLR_PEFDL_MASK                    (0xFFFFFFFFU)
73044 #define MCM_LMFDLR_PEFDL_SHIFT                   (0U)
73045 #define MCM_LMFDLR_PEFDL(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK)
73046 /*! @} */
73047 
73048 
73049 /*!
73050  * @}
73051  */ /* end of group MCM_Register_Masks */
73052 
73053 
73054 /* MCM - Peripheral instance base addresses */
73055 /** Peripheral MCM base address */
73056 #define MCM_BASE                                 (0xE0080000u)
73057 /** Peripheral MCM base pointer */
73058 #define MCM                                      ((MCM_Type *)MCM_BASE)
73059 /** Array initializer of MCM peripheral base addresses */
73060 #define MCM_BASE_ADDRS                           { MCM_BASE }
73061 /** Array initializer of MCM peripheral base pointers */
73062 #define MCM_BASE_PTRS                            { MCM }
73063 
73064 /*!
73065  * @}
73066  */ /* end of group MCM_Peripheral_Access_Layer */
73067 
73068 
73069 /* ----------------------------------------------------------------------------
73070    -- MECC Peripheral Access Layer
73071    ---------------------------------------------------------------------------- */
73072 
73073 /*!
73074  * @addtogroup MECC_Peripheral_Access_Layer MECC Peripheral Access Layer
73075  * @{
73076  */
73077 
73078 /** MECC - Register Layout Typedef */
73079 typedef struct {
73080   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x0 */
73081   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x4 */
73082   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0x8 */
73083   __IO uint32_t ERR_DATA_INJ_LOW0;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */
73084   __IO uint32_t ERR_DATA_INJ_HIGH0;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */
73085   __IO uint32_t ERR_ECC_INJ0;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */
73086   __IO uint32_t ERR_DATA_INJ_LOW1;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */
73087   __IO uint32_t ERR_DATA_INJ_HIGH1;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */
73088   __IO uint32_t ERR_ECC_INJ1;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */
73089   __IO uint32_t ERR_DATA_INJ_LOW2;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */
73090   __IO uint32_t ERR_DATA_INJ_HIGH2;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */
73091   __IO uint32_t ERR_ECC_INJ2;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */
73092   __IO uint32_t ERR_DATA_INJ_LOW3;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */
73093   __IO uint32_t ERR_DATA_INJ_HIGH3;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */
73094   __IO uint32_t ERR_ECC_INJ3;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */
73095   __I  uint32_t SINGLE_ERR_ADDR_ECC0;              /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */
73096   __I  uint32_t SINGLE_ERR_DATA_LOW0;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */
73097   __I  uint32_t SINGLE_ERR_DATA_HIGH0;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */
73098   __I  uint32_t SINGLE_ERR_POS_LOW0;               /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */
73099   __I  uint32_t SINGLE_ERR_POS_HIGH0;              /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */
73100   __I  uint32_t SINGLE_ERR_ADDR_ECC1;              /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */
73101   __I  uint32_t SINGLE_ERR_DATA_LOW1;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */
73102   __I  uint32_t SINGLE_ERR_DATA_HIGH1;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */
73103   __I  uint32_t SINGLE_ERR_POS_LOW1;               /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */
73104   __I  uint32_t SINGLE_ERR_POS_HIGH1;              /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */
73105   __I  uint32_t SINGLE_ERR_ADDR_ECC2;              /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */
73106   __I  uint32_t SINGLE_ERR_DATA_LOW2;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */
73107   __I  uint32_t SINGLE_ERR_DATA_HIGH2;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */
73108   __I  uint32_t SINGLE_ERR_POS_LOW2;               /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */
73109   __I  uint32_t SINGLE_ERR_POS_HIGH2;              /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */
73110   __I  uint32_t SINGLE_ERR_ADDR_ECC3;              /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */
73111   __I  uint32_t SINGLE_ERR_DATA_LOW3;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */
73112   __I  uint32_t SINGLE_ERR_DATA_HIGH3;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */
73113   __I  uint32_t SINGLE_ERR_POS_LOW3;               /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */
73114   __I  uint32_t SINGLE_ERR_POS_HIGH3;              /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */
73115   __I  uint32_t MULTI_ERR_ADDR_ECC0;               /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */
73116   __I  uint32_t MULTI_ERR_DATA_LOW0;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */
73117   __I  uint32_t MULTI_ERR_DATA_HIGH0;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */
73118   __I  uint32_t MULTI_ERR_ADDR_ECC1;               /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */
73119   __I  uint32_t MULTI_ERR_DATA_LOW1;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */
73120   __I  uint32_t MULTI_ERR_DATA_HIGH1;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */
73121   __I  uint32_t MULTI_ERR_ADDR_ECC2;               /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */
73122   __I  uint32_t MULTI_ERR_DATA_LOW2;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */
73123   __I  uint32_t MULTI_ERR_DATA_HIGH2;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */
73124   __I  uint32_t MULTI_ERR_ADDR_ECC3;               /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */
73125   __I  uint32_t MULTI_ERR_DATA_LOW3;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */
73126   __I  uint32_t MULTI_ERR_DATA_HIGH3;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */
73127        uint8_t RESERVED_0[68];
73128   __IO uint32_t PIPE_ECC_EN;                       /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */
73129   __I  uint32_t PENDING_STAT;                      /**< Pending Status, offset: 0x104 */
73130 } MECC_Type;
73131 
73132 /* ----------------------------------------------------------------------------
73133    -- MECC Register Masks
73134    ---------------------------------------------------------------------------- */
73135 
73136 /*!
73137  * @addtogroup MECC_Register_Masks MECC Register Masks
73138  * @{
73139  */
73140 
73141 /*! @name ERR_STATUS - Error Interrupt Status Register */
73142 /*! @{ */
73143 
73144 #define MECC_ERR_STATUS_SINGLE_ERR0_MASK         (0x1U)
73145 #define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT        (0U)
73146 /*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0
73147  *  0b0..Single bit error does not happen on OCRAM bank0.
73148  *  0b1..Single bit error happens on OCRAM bank0.
73149  */
73150 #define MECC_ERR_STATUS_SINGLE_ERR0(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
73151 
73152 #define MECC_ERR_STATUS_SINGLE_ERR1_MASK         (0x2U)
73153 #define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT        (1U)
73154 /*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1
73155  *  0b0..Single bit error does not happen on OCRAM bank1.
73156  *  0b1..Single bit error happens on OCRAM bank1.
73157  */
73158 #define MECC_ERR_STATUS_SINGLE_ERR1(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
73159 
73160 #define MECC_ERR_STATUS_SINGLE_ERR2_MASK         (0x4U)
73161 #define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT        (2U)
73162 /*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2
73163  *  0b0..Single bit error does not happen on OCRAM bank2.
73164  *  0b1..Single bit error happens on OCRAM bank2.
73165  */
73166 #define MECC_ERR_STATUS_SINGLE_ERR2(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
73167 
73168 #define MECC_ERR_STATUS_SINGLE_ERR3_MASK         (0x8U)
73169 #define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT        (3U)
73170 /*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3
73171  *  0b0..Single bit error does not happen on OCRAM bank3.
73172  *  0b1..Single bit error happens on OCRAM bank3.
73173  */
73174 #define MECC_ERR_STATUS_SINGLE_ERR3(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
73175 
73176 #define MECC_ERR_STATUS_MULTI_ERR0_MASK          (0x10U)
73177 #define MECC_ERR_STATUS_MULTI_ERR0_SHIFT         (4U)
73178 /*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0
73179  *  0b0..Multiple bits error does not happen on OCRAM bank0.
73180  *  0b1..Multiple bits error happens on OCRAM bank0.
73181  */
73182 #define MECC_ERR_STATUS_MULTI_ERR0(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
73183 
73184 #define MECC_ERR_STATUS_MULTI_ERR1_MASK          (0x20U)
73185 #define MECC_ERR_STATUS_MULTI_ERR1_SHIFT         (5U)
73186 /*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1
73187  *  0b0..Multiple bits error does not happen on OCRAM bank1.
73188  *  0b1..Multiple bits error happens on OCRAM bank1.
73189  */
73190 #define MECC_ERR_STATUS_MULTI_ERR1(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
73191 
73192 #define MECC_ERR_STATUS_MULTI_ERR2_MASK          (0x40U)
73193 #define MECC_ERR_STATUS_MULTI_ERR2_SHIFT         (6U)
73194 /*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2
73195  *  0b0..Multiple bits error does not happen on OCRAM bank2.
73196  *  0b1..Multiple bits error happens on OCRAM bank2.
73197  */
73198 #define MECC_ERR_STATUS_MULTI_ERR2(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
73199 
73200 #define MECC_ERR_STATUS_MULTI_ERR3_MASK          (0x80U)
73201 #define MECC_ERR_STATUS_MULTI_ERR3_SHIFT         (7U)
73202 /*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3
73203  *  0b0..Multiple bits error does not happen on OCRAM bank3.
73204  *  0b1..Multiple bits error happens on OCRAM bank3.
73205  */
73206 #define MECC_ERR_STATUS_MULTI_ERR3(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
73207 
73208 #define MECC_ERR_STATUS_STRB_ERR0_MASK           (0x100U)
73209 #define MECC_ERR_STATUS_STRB_ERR0_SHIFT          (8U)
73210 /*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0
73211  *  0b0..AXI strobe error does not happen on OCRAM bank0.
73212  *  0b1..AXI strobe error happens on OCRAM bank0.
73213  */
73214 #define MECC_ERR_STATUS_STRB_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
73215 
73216 #define MECC_ERR_STATUS_STRB_ERR1_MASK           (0x200U)
73217 #define MECC_ERR_STATUS_STRB_ERR1_SHIFT          (9U)
73218 /*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1
73219  *  0b0..AXI strobe error does not happen on OCRAM bank1.
73220  *  0b1..AXI strobe error happens on OCRAM bank1.
73221  */
73222 #define MECC_ERR_STATUS_STRB_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
73223 
73224 #define MECC_ERR_STATUS_STRB_ERR2_MASK           (0x400U)
73225 #define MECC_ERR_STATUS_STRB_ERR2_SHIFT          (10U)
73226 /*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2
73227  *  0b0..AXI strobe error does not happen on OCRAM bank2.
73228  *  0b1..AXI strobe error happens on OCRAM bank2.
73229  */
73230 #define MECC_ERR_STATUS_STRB_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
73231 
73232 #define MECC_ERR_STATUS_STRB_ERR3_MASK           (0x800U)
73233 #define MECC_ERR_STATUS_STRB_ERR3_SHIFT          (11U)
73234 /*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3
73235  *  0b0..AXI strobe error does not happen on OCRAM bank3.
73236  *  0b1..AXI strobe error happens on OCRAM bank3.
73237  */
73238 #define MECC_ERR_STATUS_STRB_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
73239 
73240 #define MECC_ERR_STATUS_ADDR_ERR0_MASK           (0x1000U)
73241 #define MECC_ERR_STATUS_ADDR_ERR0_SHIFT          (12U)
73242 /*! ADDR_ERR0 - OCRAM Access Error On Bank0
73243  *  0b0..OCRAM access error does not happen on OCRAM bank0.
73244  *  0b1..OCRAM access error happens on OCRAM bank0.
73245  */
73246 #define MECC_ERR_STATUS_ADDR_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
73247 
73248 #define MECC_ERR_STATUS_ADDR_ERR1_MASK           (0x2000U)
73249 #define MECC_ERR_STATUS_ADDR_ERR1_SHIFT          (13U)
73250 /*! ADDR_ERR1 - OCRAM Access Error On Bank1
73251  *  0b0..OCRAM access error does not happen on OCRAM bank1.
73252  *  0b1..OCRAM access error happens on OCRAM bank1.
73253  */
73254 #define MECC_ERR_STATUS_ADDR_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
73255 
73256 #define MECC_ERR_STATUS_ADDR_ERR2_MASK           (0x4000U)
73257 #define MECC_ERR_STATUS_ADDR_ERR2_SHIFT          (14U)
73258 /*! ADDR_ERR2 - OCRAM Access Error On Bank2
73259  *  0b0..OCRAM access error does not happen on OCRAM bank2.
73260  *  0b1..OCRAM access error happens on OCRAM bank2.
73261  */
73262 #define MECC_ERR_STATUS_ADDR_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
73263 
73264 #define MECC_ERR_STATUS_ADDR_ERR3_MASK           (0x8000U)
73265 #define MECC_ERR_STATUS_ADDR_ERR3_SHIFT          (15U)
73266 /*! ADDR_ERR3 - OCRAM Access Error On Bank3
73267  *  0b0..OCRAM access error does not happen on OCRAM bank3.
73268  *  0b1..OCRAM access error happens on OCRAM bank3.
73269  */
73270 #define MECC_ERR_STATUS_ADDR_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
73271 /*! @} */
73272 
73273 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
73274 /*! @{ */
73275 
73276 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
73277 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
73278 /*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0
73279  *  0b0..Disabled
73280  *  0b1..Enabled
73281  */
73282 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
73283 
73284 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
73285 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
73286 /*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1
73287  *  0b0..Disabled
73288  *  0b1..Enabled
73289  */
73290 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
73291 
73292 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
73293 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
73294 /*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2
73295  *  0b0..Disabled
73296  *  0b1..Enabled
73297  */
73298 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
73299 
73300 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
73301 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
73302 /*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3
73303  *  0b0..Disabled
73304  *  0b1..Enabled
73305  */
73306 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
73307 
73308 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
73309 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
73310 /*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0
73311  *  0b0..Disabled
73312  *  0b1..Enabled
73313  */
73314 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
73315 
73316 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
73317 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
73318 /*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1
73319  *  0b0..Disabled
73320  *  0b1..Enabled
73321  */
73322 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
73323 
73324 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
73325 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
73326 /*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2
73327  *  0b0..Disabled
73328  *  0b1..Enabled
73329  */
73330 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
73331 
73332 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
73333 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
73334 /*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3
73335  *  0b0..Disabled
73336  *  0b1..Enabled
73337  */
73338 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
73339 
73340 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK  (0x100U)
73341 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
73342 /*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0
73343  *  0b0..Disabled
73344  *  0b1..Enabled
73345  */
73346 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
73347 
73348 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK  (0x200U)
73349 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
73350 /*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1
73351  *  0b0..Disabled
73352  *  0b1..Enabled
73353  */
73354 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
73355 
73356 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK  (0x400U)
73357 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
73358 /*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2
73359  *  0b0..Disabled
73360  *  0b1..Enabled
73361  */
73362 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
73363 
73364 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK  (0x800U)
73365 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
73366 /*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3
73367  *  0b0..Disabled
73368  *  0b1..Enabled
73369  */
73370 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
73371 
73372 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK  (0x1000U)
73373 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
73374 /*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0
73375  *  0b0..Disabled
73376  *  0b1..Enabled
73377  */
73378 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
73379 
73380 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK  (0x2000U)
73381 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
73382 /*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1
73383  *  0b0..Disabled
73384  *  0b1..Enabled
73385  */
73386 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
73387 
73388 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK  (0x4000U)
73389 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
73390 /*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2
73391  *  0b0..Disabled
73392  *  0b1..Enabled
73393  */
73394 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
73395 
73396 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK  (0x8000U)
73397 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
73398 /*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3
73399  *  0b0..Disabled
73400  *  0b1..Enabled
73401  */
73402 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
73403 /*! @} */
73404 
73405 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
73406 /*! @{ */
73407 
73408 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK  (0x1U)
73409 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
73410 /*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0
73411  *  0b0..Disabled
73412  *  0b1..Enabled
73413  */
73414 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
73415 
73416 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK  (0x2U)
73417 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
73418 /*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1
73419  *  0b0..Disabled
73420  *  0b1..Enabled
73421  */
73422 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
73423 
73424 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK  (0x4U)
73425 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
73426 /*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2
73427  *  0b0..Disabled
73428  *  0b1..Enabled
73429  */
73430 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
73431 
73432 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK  (0x8U)
73433 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
73434 /*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3
73435  *  0b0..Disabled
73436  *  0b1..Enabled
73437  */
73438 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
73439 
73440 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK   (0x10U)
73441 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT  (4U)
73442 /*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0
73443  *  0b0..Disabled
73444  *  0b1..Enabled
73445  */
73446 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
73447 
73448 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK   (0x20U)
73449 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT  (5U)
73450 /*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1
73451  *  0b0..Disabled
73452  *  0b1..Enabled
73453  */
73454 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
73455 
73456 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK   (0x40U)
73457 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT  (6U)
73458 /*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2
73459  *  0b0..Disabled
73460  *  0b1..Enabled
73461  */
73462 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
73463 
73464 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK   (0x80U)
73465 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT  (7U)
73466 /*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3
73467  *  0b0..Disabled
73468  *  0b1..Enabled
73469  */
73470 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
73471 
73472 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK    (0x100U)
73473 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT   (8U)
73474 /*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0
73475  *  0b0..Disabled
73476  *  0b1..Enabled
73477  */
73478 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
73479 
73480 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK    (0x200U)
73481 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT   (9U)
73482 /*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1
73483  *  0b0..Disabled
73484  *  0b1..Enabled
73485  */
73486 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
73487 
73488 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK    (0x400U)
73489 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT   (10U)
73490 /*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2
73491  *  0b0..Disabled
73492  *  0b1..Enabled
73493  */
73494 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
73495 
73496 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK    (0x800U)
73497 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT   (11U)
73498 /*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3
73499  *  0b0..Disabled
73500  *  0b1..Enabled
73501  */
73502 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
73503 
73504 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK    (0x1000U)
73505 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT   (12U)
73506 /*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0
73507  *  0b0..Disabled
73508  *  0b1..Enabled
73509  */
73510 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
73511 
73512 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK    (0x2000U)
73513 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT   (13U)
73514 /*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1
73515  *  0b0..Disabled
73516  *  0b1..Enabled
73517  */
73518 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
73519 
73520 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK    (0x4000U)
73521 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT   (14U)
73522 /*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2
73523  *  0b0..Disabled
73524  *  0b1..Enabled
73525  */
73526 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
73527 
73528 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK    (0x8000U)
73529 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT   (15U)
73530 /*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3
73531  *  0b0..Disabled
73532  *  0b1..Enabled
73533  */
73534 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
73535 /*! @} */
73536 
73537 /*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
73538 /*! @{ */
73539 
73540 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73541 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
73542 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
73543  */
73544 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
73545 /*! @} */
73546 
73547 /*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
73548 /*! @{ */
73549 
73550 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73551 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
73552 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
73553  */
73554 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
73555 /*! @} */
73556 
73557 /*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
73558 /*! @{ */
73559 
73560 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK       (0xFFU)
73561 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT      (0U)
73562 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
73563  */
73564 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
73565 /*! @} */
73566 
73567 /*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
73568 /*! @{ */
73569 
73570 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73571 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
73572 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
73573  */
73574 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
73575 /*! @} */
73576 
73577 /*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
73578 /*! @{ */
73579 
73580 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73581 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
73582 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
73583  */
73584 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
73585 /*! @} */
73586 
73587 /*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
73588 /*! @{ */
73589 
73590 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK       (0xFFU)
73591 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT      (0U)
73592 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
73593  */
73594 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
73595 /*! @} */
73596 
73597 /*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
73598 /*! @{ */
73599 
73600 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73601 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
73602 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
73603  */
73604 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
73605 /*! @} */
73606 
73607 /*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
73608 /*! @{ */
73609 
73610 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73611 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
73612 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
73613  */
73614 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
73615 /*! @} */
73616 
73617 /*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
73618 /*! @{ */
73619 
73620 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK       (0xFFU)
73621 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT      (0U)
73622 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
73623  */
73624 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
73625 /*! @} */
73626 
73627 /*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
73628 /*! @{ */
73629 
73630 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73631 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
73632 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
73633  */
73634 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
73635 /*! @} */
73636 
73637 /*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
73638 /*! @{ */
73639 
73640 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73641 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
73642 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
73643  */
73644 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
73645 /*! @} */
73646 
73647 /*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
73648 /*! @{ */
73649 
73650 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK       (0xFFU)
73651 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT      (0U)
73652 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
73653  */
73654 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
73655 /*! @} */
73656 
73657 /*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */
73658 /*! @{ */
73659 
73660 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
73661 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
73662 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0
73663  */
73664 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
73665 
73666 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73667 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
73668 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0
73669  */
73670 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)
73671 /*! @} */
73672 
73673 /*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
73674 /*! @{ */
73675 
73676 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73677 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
73678 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0
73679  */
73680 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
73681 /*! @} */
73682 
73683 /*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
73684 /*! @{ */
73685 
73686 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73687 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
73688 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
73689  */
73690 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
73691 /*! @} */
73692 
73693 /*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */
73694 /*! @{ */
73695 
73696 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73697 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
73698 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0
73699  */
73700 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
73701 /*! @} */
73702 
73703 /*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */
73704 /*! @{ */
73705 
73706 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73707 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
73708 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0
73709  */
73710 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
73711 /*! @} */
73712 
73713 /*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */
73714 /*! @{ */
73715 
73716 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
73717 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
73718 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1
73719  */
73720 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
73721 
73722 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73723 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
73724 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1
73725  */
73726 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)
73727 /*! @} */
73728 
73729 /*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
73730 /*! @{ */
73731 
73732 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73733 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
73734 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1
73735  */
73736 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
73737 /*! @} */
73738 
73739 /*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
73740 /*! @{ */
73741 
73742 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73743 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
73744 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
73745  */
73746 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
73747 /*! @} */
73748 
73749 /*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */
73750 /*! @{ */
73751 
73752 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73753 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
73754 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1
73755  */
73756 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
73757 /*! @} */
73758 
73759 /*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */
73760 /*! @{ */
73761 
73762 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73763 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
73764 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1
73765  */
73766 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
73767 /*! @} */
73768 
73769 /*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */
73770 /*! @{ */
73771 
73772 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
73773 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
73774 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2
73775  */
73776 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
73777 
73778 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73779 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
73780 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2
73781  */
73782 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)
73783 /*! @} */
73784 
73785 /*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
73786 /*! @{ */
73787 
73788 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73789 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
73790 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2
73791  */
73792 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
73793 /*! @} */
73794 
73795 /*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
73796 /*! @{ */
73797 
73798 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73799 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
73800 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
73801  */
73802 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
73803 /*! @} */
73804 
73805 /*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */
73806 /*! @{ */
73807 
73808 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73809 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
73810 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2
73811  */
73812 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
73813 /*! @} */
73814 
73815 /*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */
73816 /*! @{ */
73817 
73818 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73819 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
73820 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2
73821  */
73822 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
73823 /*! @} */
73824 
73825 /*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */
73826 /*! @{ */
73827 
73828 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
73829 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
73830 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3
73831  */
73832 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
73833 
73834 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73835 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
73836 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3
73837  */
73838 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)
73839 /*! @} */
73840 
73841 /*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
73842 /*! @{ */
73843 
73844 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73845 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
73846 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3
73847  */
73848 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
73849 /*! @} */
73850 
73851 /*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
73852 /*! @{ */
73853 
73854 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73855 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
73856 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
73857  */
73858 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
73859 /*! @} */
73860 
73861 /*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */
73862 /*! @{ */
73863 
73864 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73865 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
73866 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3
73867  */
73868 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
73869 /*! @} */
73870 
73871 /*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */
73872 /*! @{ */
73873 
73874 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73875 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
73876 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3
73877  */
73878 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
73879 /*! @} */
73880 
73881 /*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */
73882 /*! @{ */
73883 
73884 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
73885 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
73886 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0
73887  */
73888 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
73889 
73890 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73891 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
73892 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0
73893  */
73894 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)
73895 /*! @} */
73896 
73897 /*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
73898 /*! @{ */
73899 
73900 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73901 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
73902 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
73903  */
73904 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
73905 /*! @} */
73906 
73907 /*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
73908 /*! @{ */
73909 
73910 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73911 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
73912 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
73913  */
73914 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
73915 /*! @} */
73916 
73917 /*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */
73918 /*! @{ */
73919 
73920 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
73921 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
73922 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1
73923  */
73924 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
73925 
73926 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73927 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
73928 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1
73929  */
73930 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)
73931 /*! @} */
73932 
73933 /*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
73934 /*! @{ */
73935 
73936 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73937 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
73938 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
73939  */
73940 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
73941 /*! @} */
73942 
73943 /*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
73944 /*! @{ */
73945 
73946 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73947 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
73948 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
73949  */
73950 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
73951 /*! @} */
73952 
73953 /*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */
73954 /*! @{ */
73955 
73956 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
73957 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
73958 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2
73959  */
73960 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
73961 
73962 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73963 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
73964 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2
73965  */
73966 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)
73967 /*! @} */
73968 
73969 /*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
73970 /*! @{ */
73971 
73972 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73973 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
73974 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
73975  */
73976 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
73977 /*! @} */
73978 
73979 /*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
73980 /*! @{ */
73981 
73982 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73983 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
73984 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
73985  */
73986 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
73987 /*! @} */
73988 
73989 /*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */
73990 /*! @{ */
73991 
73992 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
73993 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
73994 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3
73995  */
73996 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
73997 
73998 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73999 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
74000 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3
74001  */
74002 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)
74003 /*! @} */
74004 
74005 /*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
74006 /*! @{ */
74007 
74008 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
74009 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
74010 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
74011  */
74012 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
74013 /*! @} */
74014 
74015 /*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
74016 /*! @{ */
74017 
74018 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
74019 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
74020 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
74021  */
74022 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
74023 /*! @} */
74024 
74025 /*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */
74026 /*! @{ */
74027 
74028 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK  (0x1U)
74029 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
74030 /*! READ_DATA_WAIT_EN - Read Data Wait Enable
74031  *  0b0..Disable.
74032  *  0b1..Enable.
74033  */
74034 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
74035 
74036 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK  (0x2U)
74037 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
74038 /*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable
74039  *  0b0..Disable.
74040  *  0b1..Enable.
74041  */
74042 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
74043 
74044 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
74045 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
74046 /*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable
74047  *  0b0..Disable.
74048  *  0b1..Enable.
74049  */
74050 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
74051 
74052 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
74053 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
74054 /*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable
74055  *  0b0..Disable.
74056  *  0b1..Enable.
74057  */
74058 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
74059 
74060 #define MECC_PIPE_ECC_EN_ECC_EN_MASK             (0x10U)
74061 #define MECC_PIPE_ECC_EN_ECC_EN_SHIFT            (4U)
74062 /*! ECC_EN - ECC Function Enable
74063  *  0b0..Disable.
74064  *  0b1..Enable.
74065  */
74066 #define MECC_PIPE_ECC_EN_ECC_EN(x)               (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
74067 /*! @} */
74068 
74069 /*! @name PENDING_STAT - Pending Status */
74070 /*! @{ */
74071 
74072 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
74073 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
74074 /*! READ_DATA_WAIT_PENDING - Read Data Wait Pending
74075  *  0b0..No update pending status for READ_DATA_WAIT_EN.
74076  *  0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
74077  */
74078 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
74079 
74080 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
74081 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
74082 /*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending
74083  *  0b0..No update pending status for READ_ADDR_PIPE_EN.
74084  *  0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
74085  */
74086 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
74087 
74088 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
74089 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
74090 /*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending
74091  *  0b0..No update pending status for WRITE_DATA_PIPE_EN.
74092  *  0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
74093  */
74094 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
74095 
74096 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
74097 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
74098 /*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending
74099  *  0b0..No update pending status for WRITE_ADDR_PIPE_EN.
74100  *  0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
74101  */
74102 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)
74103 /*! @} */
74104 
74105 
74106 /*!
74107  * @}
74108  */ /* end of group MECC_Register_Masks */
74109 
74110 
74111 /* MECC - Peripheral instance base addresses */
74112 /** Peripheral MECC1 base address */
74113 #define MECC1_BASE                               (0x40014000u)
74114 /** Peripheral MECC1 base pointer */
74115 #define MECC1                                    ((MECC_Type *)MECC1_BASE)
74116 /** Peripheral MECC2 base address */
74117 #define MECC2_BASE                               (0x40018000u)
74118 /** Peripheral MECC2 base pointer */
74119 #define MECC2                                    ((MECC_Type *)MECC2_BASE)
74120 /** Array initializer of MECC peripheral base addresses */
74121 #define MECC_BASE_ADDRS                          { 0u, MECC1_BASE, MECC2_BASE }
74122 /** Array initializer of MECC peripheral base pointers */
74123 #define MECC_BASE_PTRS                           { (MECC_Type *)0u, MECC1, MECC2 }
74124 
74125 /*!
74126  * @}
74127  */ /* end of group MECC_Peripheral_Access_Layer */
74128 
74129 
74130 /* ----------------------------------------------------------------------------
74131    -- MIPI_CSI2RX Peripheral Access Layer
74132    ---------------------------------------------------------------------------- */
74133 
74134 /*!
74135  * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
74136  * @{
74137  */
74138 
74139 /** MIPI_CSI2RX - Register Layout Typedef */
74140 typedef struct {
74141        uint8_t RESERVED_0[256];
74142   __IO uint32_t CFG_NUM_LANES;                     /**< Lane Configuration Register, offset: 0x100 */
74143   __IO uint32_t CFG_DISABLE_DATA_LANES;            /**< Disable Data Lane Register, offset: 0x104 */
74144   __I  uint32_t BIT_ERR;                           /**< ECC and CRC Error Status Register, offset: 0x108 */
74145   __I  uint32_t IRQ_STATUS;                        /**< IRQ Status Register, offset: 0x10C */
74146   __IO uint32_t IRQ_MASK;                          /**< IRQ Mask Setting Register, offset: 0x110 */
74147   __I  uint32_t ULPS_STATUS;                       /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */
74148   __I  uint32_t PPI_ERRSOT_HS;                     /**< ERRSot HS Status Register, offset: 0x118 */
74149   __I  uint32_t PPI_ERRSOTSYNC_HS;                 /**< ErrSotSync HS Status Register, offset: 0x11C */
74150   __I  uint32_t PPI_ERRESC;                        /**< ErrEsc Status Register, offset: 0x120 */
74151   __I  uint32_t PPI_ERRSYNCESC;                    /**< ErrSyncEsc Status Register, offset: 0x124 */
74152   __I  uint32_t PPI_ERRCONTROL;                    /**< ErrControl Status Register, offset: 0x128 */
74153   __IO uint32_t CFG_DISABLE_PAYLOAD_0;             /**< Disable Payload 0 Register, offset: 0x12C */
74154   __IO uint32_t CFG_DISABLE_PAYLOAD_1;             /**< Disable Payload 1 Register, offset: 0x130 */
74155        uint8_t RESERVED_1[76];
74156   __IO uint32_t CFG_IGNORE_VC;                     /**< Ignore Virtual Channel Register, offset: 0x180 */
74157   __IO uint32_t CFG_VID_VC;                        /**< Virtual Channel value Register, offset: 0x184 */
74158   __IO uint32_t CFG_VID_P_FIFO_SEND_LEVEL;         /**< FIFO Send Level Configuration Register, offset: 0x188 */
74159   __IO uint32_t CFG_VID_VSYNC;                     /**< VSYNC Configuration Register, offset: 0x18C */
74160   __IO uint32_t CFG_VID_HSYNC_FP;                  /**< Start of HSYNC Delay control Register, offset: 0x190 */
74161   __IO uint32_t CFG_VID_HSYNC;                     /**< HSYNC Configuration Register, offset: 0x194 */
74162   __IO uint32_t CFG_VID_HSYNC_BP;                  /**< End of HSYNC Delay Control Register, offset: 0x198 */
74163 } MIPI_CSI2RX_Type;
74164 
74165 /* ----------------------------------------------------------------------------
74166    -- MIPI_CSI2RX Register Masks
74167    ---------------------------------------------------------------------------- */
74168 
74169 /*!
74170  * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
74171  * @{
74172  */
74173 
74174 /*! @name CFG_NUM_LANES - Lane Configuration Register */
74175 /*! @{ */
74176 
74177 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
74178 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
74179 /*! CFG_NUM_LANES - This field is used to set the number of active lanes for receiving data.
74180  *  0b00..1 Lane
74181  *  0b01..2 Lane
74182  *  0b10-0b11..Reserved
74183  */
74184 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
74185 /*! @} */
74186 
74187 /*! @name CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
74188 /*! @{ */
74189 
74190 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
74191 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
74192 /*! CFG_DISABLE_DATA_LANES - This field is used to disable data lanes.
74193  */
74194 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
74195 /*! @} */
74196 
74197 /*! @name BIT_ERR - ECC and CRC Error Status Register */
74198 /*! @{ */
74199 
74200 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK         (0x3FFU)
74201 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT        (0U)
74202 /*! BIT_ERR - This field shows the error status of ECC and CRC
74203  */
74204 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK)
74205 /*! @} */
74206 
74207 /*! @name IRQ_STATUS - IRQ Status Register */
74208 /*! @{ */
74209 
74210 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK   (0x1FFU)
74211 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT  (0U)
74212 /*! IRQ_STATUS - This field shows the IRQ status
74213  */
74214 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
74215 /*! @} */
74216 
74217 /*! @name IRQ_MASK - IRQ Mask Setting Register */
74218 /*! @{ */
74219 
74220 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK       (0x1FFU)
74221 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT      (0U)
74222 /*! IRQ_MASK - This field shows the IRQ Mask setting
74223  */
74224 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
74225 /*! @} */
74226 
74227 /*! @name ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */
74228 /*! @{ */
74229 
74230 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK      (0x3FFU)
74231 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT     (0U)
74232 /*! STATUS - This field shows the status of Rx D-PHY ULPS state
74233  */
74234 #define MIPI_CSI2RX_ULPS_STATUS_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK)
74235 /*! @} */
74236 
74237 /*! @name PPI_ERRSOT_HS - ERRSot HS Status Register */
74238 /*! @{ */
74239 
74240 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK    (0xFU)
74241 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT   (0U)
74242 /*! STATUS - This field indicates PPI ErrSotHS captured status from D-PHY
74243  */
74244 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
74245 /*! @} */
74246 
74247 /*! @name PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
74248 /*! @{ */
74249 
74250 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
74251 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
74252 /*! STATUS - This field indicates PPI ErrSotSync_HS captured status from D-PHY
74253  */
74254 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
74255 /*! @} */
74256 
74257 /*! @name PPI_ERRESC - ErrEsc Status Register */
74258 /*! @{ */
74259 
74260 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK       (0xFU)
74261 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT      (0U)
74262 /*! STATUS - This field indicates PPI ErrEsc captured status from D-PHY
74263  */
74264 #define MIPI_CSI2RX_PPI_ERRESC_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK)
74265 /*! @} */
74266 
74267 /*! @name PPI_ERRSYNCESC - ErrSyncEsc Status Register */
74268 /*! @{ */
74269 
74270 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK   (0xFU)
74271 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT  (0U)
74272 /*! STATUS - This field indicates PPI ErrSyncEsc captured status from D-PHY
74273  */
74274 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
74275 /*! @} */
74276 
74277 /*! @name PPI_ERRCONTROL - ErrControl Status Register */
74278 /*! @{ */
74279 
74280 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK   (0xFU)
74281 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT  (0U)
74282 /*! STATUS - This field indicates PPI ErrControl captured status from D-PHY
74283  */
74284 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
74285 /*! @} */
74286 
74287 /*! @name CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
74288 /*! @{ */
74289 
74290 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
74291 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
74292 /*! DIS_PAYLOAD_NULL - Null
74293  */
74294 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
74295 
74296 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
74297 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
74298 /*! DIS_PAYLOAD_BLANK - Blank
74299  */
74300 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
74301 
74302 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
74303 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
74304 /*! DIS_PAYLOAD_EMBEDDED - Embedded
74305  */
74306 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
74307 
74308 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
74309 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
74310 /*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit
74311  */
74312 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
74313 
74314 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
74315 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
74316 /*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit
74317  */
74318 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
74319 
74320 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
74321 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
74322 /*! DIS_PAYLOAD_RGB444 - RGB444
74323  */
74324 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
74325 
74326 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
74327 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
74328 /*! DIS_PAYLOAD_RGB555 - RGB555
74329  */
74330 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
74331 
74332 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
74333 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
74334 /*! DIS_PAYLOAD_RGB565 - RGB565
74335  */
74336 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
74337 
74338 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
74339 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
74340 /*! DIS_PAYLOAD_RGB666 - RGB666
74341  */
74342 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
74343 
74344 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
74345 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
74346 /*! DIS_PAYLOAD_RGB888 - RGB888
74347  */
74348 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
74349 /*! @} */
74350 
74351 /*! @name CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
74352 /*! @{ */
74353 
74354 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
74355 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
74356 /*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31
74357  */
74358 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
74359 
74360 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
74361 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
74362 /*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32
74363  */
74364 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
74365 
74366 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
74367 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
74368 /*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33
74369  */
74370 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
74371 
74372 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
74373 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
74374 /*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34
74375  */
74376 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
74377 
74378 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
74379 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
74380 /*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35
74381  */
74382 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
74383 
74384 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
74385 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
74386 /*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35
74387  */
74388 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
74389 
74390 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
74391 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
74392 /*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36
74393  */
74394 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
74395 
74396 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
74397 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
74398 /*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37
74399  */
74400 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
74401 
74402 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
74403 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
74404 /*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types
74405  */
74406 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
74407 /*! @} */
74408 
74409 /*! @name CFG_IGNORE_VC - Ignore Virtual Channel Register */
74410 /*! @{ */
74411 
74412 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U)
74413 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U)
74414 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK)
74415 /*! @} */
74416 
74417 /*! @name CFG_VID_VC - Virtual Channel value Register */
74418 /*! @{ */
74419 
74420 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK       (0x3U)
74421 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT      (0U)
74422 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK)
74423 /*! @} */
74424 
74425 /*! @name CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */
74426 /*! @{ */
74427 
74428 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU)
74429 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U)
74430 /*! SEND_LEVEL - FIFO Send Level field
74431  */
74432 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK)
74433 /*! @} */
74434 
74435 /*! @name CFG_VID_VSYNC - VSYNC Configuration Register */
74436 /*! @{ */
74437 
74438 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK     (0xFFU)
74439 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT    (0U)
74440 /*! WIDTH - Width of VSYNC
74441  */
74442 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK)
74443 /*! @} */
74444 
74445 /*! @name CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */
74446 /*! @{ */
74447 
74448 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU)
74449 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U)
74450 /*! DELAY_CTL - Delay control for beginning of HSYNC pulse
74451  */
74452 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK)
74453 /*! @} */
74454 
74455 /*! @name CFG_VID_HSYNC - HSYNC Configuration Register */
74456 /*! @{ */
74457 
74458 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK     (0xFFU)
74459 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT    (0U)
74460 /*! WIDTH - Width of HSYNC
74461  */
74462 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK)
74463 /*! @} */
74464 
74465 /*! @name CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */
74466 /*! @{ */
74467 
74468 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU)
74469 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U)
74470 /*! DELAY_CTL - Delay Control for end of HSYNC pulse
74471  */
74472 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK)
74473 /*! @} */
74474 
74475 
74476 /*!
74477  * @}
74478  */ /* end of group MIPI_CSI2RX_Register_Masks */
74479 
74480 
74481 /* MIPI_CSI2RX - Peripheral instance base addresses */
74482 /** Peripheral MIPI_CSI2RX base address */
74483 #define MIPI_CSI2RX_BASE                         (0x40810000u)
74484 /** Peripheral MIPI_CSI2RX base pointer */
74485 #define MIPI_CSI2RX                              ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
74486 /** Array initializer of MIPI_CSI2RX peripheral base addresses */
74487 #define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI2RX_BASE }
74488 /** Array initializer of MIPI_CSI2RX peripheral base pointers */
74489 #define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI2RX }
74490 
74491 /*!
74492  * @}
74493  */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
74494 
74495 
74496 /* ----------------------------------------------------------------------------
74497    -- MMCAU Peripheral Access Layer
74498    ---------------------------------------------------------------------------- */
74499 
74500 /*!
74501  * @addtogroup MMCAU_Peripheral_Access_Layer MMCAU Peripheral Access Layer
74502  * @{
74503  */
74504 
74505 /** MMCAU - Register Layout Typedef */
74506 typedef struct {
74507   __IO uint32_t CASR;                              /**< Status Register, offset: 0x0 */
74508   __IO uint32_t CAA;                               /**< Accumulator, offset: 0x4 */
74509   __IO uint32_t CA[9];                             /**< General Purpose Register, array offset: 0x8, array step: 0x4 */
74510 } MMCAU_Type;
74511 
74512 /* ----------------------------------------------------------------------------
74513    -- MMCAU Register Masks
74514    ---------------------------------------------------------------------------- */
74515 
74516 /*!
74517  * @addtogroup MMCAU_Register_Masks MMCAU Register Masks
74518  * @{
74519  */
74520 
74521 /*! @name CASR - Status Register */
74522 /*! @{ */
74523 
74524 #define MMCAU_CASR_IC_MASK                       (0x1U)
74525 #define MMCAU_CASR_IC_SHIFT                      (0U)
74526 /*! IC - Illegal Command
74527  *  0b0..No illegal commands issued.
74528  *  0b1..Illegal command issued.
74529  */
74530 #define MMCAU_CASR_IC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK)
74531 
74532 #define MMCAU_CASR_DPE_MASK                      (0x2U)
74533 #define MMCAU_CASR_DPE_SHIFT                     (1U)
74534 /*! DPE - DES Parity Error
74535  *  0b0..No error detected.
74536  *  0b1..DES key parity error detected.
74537  */
74538 #define MMCAU_CASR_DPE(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK)
74539 
74540 #define MMCAU_CASR_VER_MASK                      (0xF0000000U)
74541 #define MMCAU_CASR_VER_SHIFT                     (28U)
74542 /*! VER - CAU Version
74543  *  0b0001..Initial CAU version.
74544  *  0b0010..Second version, added support for SHA-256 algorithm (This is the value on this device).
74545  */
74546 #define MMCAU_CASR_VER(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK)
74547 /*! @} */
74548 
74549 /*! @name CAA - Accumulator */
74550 /*! @{ */
74551 
74552 #define MMCAU_CAA_ACC_MASK                       (0xFFFFFFFFU)
74553 #define MMCAU_CAA_ACC_SHIFT                      (0U)
74554 /*! ACC - Accumulator
74555  */
74556 #define MMCAU_CAA_ACC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK)
74557 /*! @} */
74558 
74559 /*! @name CA - General Purpose Register */
74560 /*! @{ */
74561 
74562 #define MMCAU_CA_CAn_MASK                        (0xFFFFFFFFU)
74563 #define MMCAU_CA_CAn_SHIFT                       (0U)
74564 /*! CAn - General Purpose Registers
74565  */
74566 #define MMCAU_CA_CAn(x)                          (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK)
74567 /*! @} */
74568 
74569 /* The count of MMCAU_CA */
74570 #define MMCAU_CA_COUNT                           (9U)
74571 
74572 
74573 /*!
74574  * @}
74575  */ /* end of group MMCAU_Register_Masks */
74576 
74577 
74578 /* MMCAU - Peripheral instance base addresses */
74579 /** Peripheral MMCAU base address */
74580 #define MMCAU_BASE                               (0xE0081000u)
74581 /** Peripheral MMCAU base pointer */
74582 #define MMCAU                                    ((MMCAU_Type *)MMCAU_BASE)
74583 /** Array initializer of MMCAU peripheral base addresses */
74584 #define MMCAU_BASE_ADDRS                         { MMCAU_BASE }
74585 /** Array initializer of MMCAU peripheral base pointers */
74586 #define MMCAU_BASE_PTRS                          { MMCAU }
74587 
74588 /*!
74589  * @}
74590  */ /* end of group MMCAU_Peripheral_Access_Layer */
74591 
74592 
74593 /* ----------------------------------------------------------------------------
74594    -- MU Peripheral Access Layer
74595    ---------------------------------------------------------------------------- */
74596 
74597 /*!
74598  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
74599  * @{
74600  */
74601 
74602 /** MU - Register Layout Typedef */
74603 typedef struct {
74604   __IO uint32_t TR[4];                             /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */
74605   __I  uint32_t RR[4];                             /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */
74606   __IO uint32_t SR;                                /**< Processor B Status Register, offset: 0x20 */
74607   __IO uint32_t CR;                                /**< Processor B Control Register, offset: 0x24 */
74608 } MU_Type;
74609 
74610 /* ----------------------------------------------------------------------------
74611    -- MU Register Masks
74612    ---------------------------------------------------------------------------- */
74613 
74614 /*!
74615  * @addtogroup MU_Register_Masks MU Register Masks
74616  * @{
74617  */
74618 
74619 /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
74620 /*! @{ */
74621 
74622 #define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
74623 #define MU_TR_DATA_SHIFT                         (0U)
74624 /*! DATA - TR3
74625  */
74626 #define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
74627 /*! @} */
74628 
74629 /* The count of MU_TR */
74630 #define MU_TR_COUNT                              (4U)
74631 
74632 /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
74633 /*! @{ */
74634 
74635 #define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
74636 #define MU_RR_DATA_SHIFT                         (0U)
74637 /*! DATA - RR3
74638  */
74639 #define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
74640 /*! @} */
74641 
74642 /* The count of MU_RR */
74643 #define MU_RR_COUNT                              (4U)
74644 
74645 /*! @name SR - Processor B Status Register */
74646 /*! @{ */
74647 
74648 #define MU_SR_Fn_MASK                            (0x7U)
74649 #define MU_SR_Fn_SHIFT                           (0U)
74650 /*! Fn - Fn
74651  *  0b000..ABFn bit in MUA.CR register is written 0 (default).
74652  *  0b001..ABFn bit in MUA.CR register is written 1.
74653  */
74654 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
74655 
74656 #define MU_SR_EP_MASK                            (0x10U)
74657 #define MU_SR_EP_SHIFT                           (4U)
74658 /*! EP - EP
74659  *  0b0..The Processor B-side event is not pending (default).
74660  *  0b1..The Processor B-side event is pending.
74661  */
74662 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
74663 
74664 #define MU_SR_RS_MASK                            (0x80U)
74665 #define MU_SR_RS_SHIFT                           (7U)
74666 /*! RS - RS
74667  *  0b0..The Processor A or the Processor A-side of the MU is not in reset.
74668  *  0b1..The Processor A or the Processor A-side of the MU is in reset.
74669  */
74670 #define MU_SR_RS(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
74671 
74672 #define MU_SR_FUP_MASK                           (0x100U)
74673 #define MU_SR_FUP_SHIFT                          (8U)
74674 /*! FUP - FUP
74675  *  0b0..No flags updated, initiated by the Processor B, in progress (default)
74676  *  0b1..Processor B initiated flags update, processing
74677  */
74678 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
74679 
74680 #define MU_SR_TEn_MASK                           (0xF00000U)
74681 #define MU_SR_TEn_SHIFT                          (20U)
74682 /*! TEn - TEn
74683  *  0b0000..MUB.TRn register is not empty.
74684  *  0b0001..MUB.TRn register is empty (default).
74685  */
74686 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
74687 
74688 #define MU_SR_RFn_MASK                           (0xF000000U)
74689 #define MU_SR_RFn_SHIFT                          (24U)
74690 /*! RFn - RFn
74691  *  0b0000..MUB.RRn register is not full (default).
74692  *  0b0001..MUB.RRn register has received data from MUA.TRn register and is ready to be read by the Processor B.
74693  */
74694 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
74695 
74696 #define MU_SR_GIPn_MASK                          (0xF0000000U)
74697 #define MU_SR_GIPn_SHIFT                         (28U)
74698 /*! GIPn - GIPn
74699  *  0b0000..Processor B general purpose interrupt n is not pending. (default)
74700  *  0b0001..Processor B general purpose interrupt n is pending.
74701  */
74702 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
74703 /*! @} */
74704 
74705 /*! @name CR - Processor B Control Register */
74706 /*! @{ */
74707 
74708 #define MU_CR_Fn_MASK                            (0x7U)
74709 #define MU_CR_Fn_SHIFT                           (0U)
74710 /*! Fn - Fn
74711  *  0b000..Clears the Fn bit in the MUA.SR register.
74712  *  0b001..Sets the Fn bit in the MUA.SR register.
74713  */
74714 #define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
74715 
74716 #define MU_CR_GIRn_MASK                          (0xF0000U)
74717 #define MU_CR_GIRn_SHIFT                         (16U)
74718 /*! GIRn - GIRn
74719  *  0b0000..Processor B General Interrupt n is not requested to the Processor A (default).
74720  *  0b0001..Processor B General Interrupt n is requested to the Processor A.
74721  */
74722 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
74723 
74724 #define MU_CR_TIEn_MASK                          (0xF00000U)
74725 #define MU_CR_TIEn_SHIFT                         (20U)
74726 /*! TIEn - TIEn
74727  *  0b0000..Disables Processor B Transmit Interrupt n. (default)
74728  *  0b0001..Enables Processor B Transmit Interrupt n.
74729  */
74730 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
74731 
74732 #define MU_CR_RIEn_MASK                          (0xF000000U)
74733 #define MU_CR_RIEn_SHIFT                         (24U)
74734 /*! RIEn - RIEn
74735  *  0b0000..Disables Processor B Receive Interrupt n. (default)
74736  *  0b0001..Enables Processor B Receive Interrupt n.
74737  */
74738 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
74739 
74740 #define MU_CR_GIEn_MASK                          (0xF0000000U)
74741 #define MU_CR_GIEn_SHIFT                         (28U)
74742 /*! GIEn - GIEn
74743  *  0b0000..Disables Processor B General Interrupt n. (default)
74744  *  0b0001..Enables Processor B General Interrupt n.
74745  */
74746 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
74747 /*! @} */
74748 
74749 
74750 /*!
74751  * @}
74752  */ /* end of group MU_Register_Masks */
74753 
74754 
74755 /* MU - Peripheral instance base addresses */
74756 /** Peripheral MUB base address */
74757 #define MUB_BASE                                 (0x40C4C000u)
74758 /** Peripheral MUB base pointer */
74759 #define MUB                                      ((MU_Type *)MUB_BASE)
74760 /** Array initializer of MU peripheral base addresses */
74761 #define MU_BASE_ADDRS                            { MUB_BASE }
74762 /** Array initializer of MU peripheral base pointers */
74763 #define MU_BASE_PTRS                             { MUB }
74764 /** Interrupt vectors for the MU peripheral type */
74765 #define MU_IRQS                                  { MUB_IRQn }
74766 
74767 /*!
74768  * @}
74769  */ /* end of group MU_Peripheral_Access_Layer */
74770 
74771 
74772 /* ----------------------------------------------------------------------------
74773    -- OCOTP Peripheral Access Layer
74774    ---------------------------------------------------------------------------- */
74775 
74776 /*!
74777  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
74778  * @{
74779  */
74780 
74781 /** OCOTP - Register Layout Typedef */
74782 typedef struct {
74783   __IO uint32_t CTRL;                              /**< OTP Controller Control and Status Register, offset: 0x0 */
74784   __IO uint32_t CTRL_SET;                          /**< OTP Controller Control and Status Register, offset: 0x4 */
74785   __IO uint32_t CTRL_CLR;                          /**< OTP Controller Control and Status Register, offset: 0x8 */
74786   __IO uint32_t CTRL_TOG;                          /**< OTP Controller Control and Status Register, offset: 0xC */
74787   __IO uint32_t PDN;                               /**< OTP Controller PDN Register, offset: 0x10 */
74788        uint8_t RESERVED_0[12];
74789   __IO uint32_t DATA;                              /**< OTP Controller Write Data Register, offset: 0x20 */
74790        uint8_t RESERVED_1[12];
74791   __IO uint32_t READ_CTRL;                         /**< OTP Controller Read Control Register, offset: 0x30 */
74792        uint8_t RESERVED_2[92];
74793   __IO uint32_t OUT_STATUS;                        /**< 8K OTP Memory STATUS Register, offset: 0x90 */
74794   __IO uint32_t OUT_STATUS_SET;                    /**< 8K OTP Memory STATUS Register, offset: 0x94 */
74795   __IO uint32_t OUT_STATUS_CLR;                    /**< 8K OTP Memory STATUS Register, offset: 0x98 */
74796   __IO uint32_t OUT_STATUS_TOG;                    /**< 8K OTP Memory STATUS Register, offset: 0x9C */
74797        uint8_t RESERVED_3[16];
74798   __I  uint32_t VERSION;                           /**< OTP Controller Version Register, offset: 0xB0 */
74799        uint8_t RESERVED_4[76];
74800   struct {                                         /* offset: 0x100, array step: 0x10 */
74801     __IO uint32_t READ_FUSE_DATA;                    /**< OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10 */
74802          uint8_t RESERVED_0[12];
74803   } READ_FUSE_DATAS[4];
74804   __IO uint32_t SW_LOCK;                           /**< SW_LOCK Register, offset: 0x140 */
74805        uint8_t RESERVED_5[12];
74806   __IO uint32_t BIT_LOCK;                          /**< BIT_LOCK Register, offset: 0x150 */
74807        uint8_t RESERVED_6[1196];
74808   __I  uint32_t LOCKED0;                           /**< OTP Controller Program Locked Status 0 Register, offset: 0x600 */
74809        uint8_t RESERVED_7[12];
74810   __I  uint32_t LOCKED1;                           /**< OTP Controller Program Locked Status 1 Register, offset: 0x610 */
74811        uint8_t RESERVED_8[12];
74812   __I  uint32_t LOCKED2;                           /**< OTP Controller Program Locked Status 2 Register, offset: 0x620 */
74813        uint8_t RESERVED_9[12];
74814   __I  uint32_t LOCKED3;                           /**< OTP Controller Program Locked Status 3 Register, offset: 0x630 */
74815        uint8_t RESERVED_10[12];
74816   __I  uint32_t LOCKED4;                           /**< OTP Controller Program Locked Status 4 Register, offset: 0x640 */
74817        uint8_t RESERVED_11[444];
74818   struct {                                         /* offset: 0x800, array step: 0x10 */
74819     __I  uint32_t FUSE;                              /**< Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10 */
74820          uint8_t RESERVED_0[12];
74821   } FUSEN[144];
74822 } OCOTP_Type;
74823 
74824 /* ----------------------------------------------------------------------------
74825    -- OCOTP Register Masks
74826    ---------------------------------------------------------------------------- */
74827 
74828 /*!
74829  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
74830  * @{
74831  */
74832 
74833 /*! @name CTRL - OTP Controller Control and Status Register */
74834 /*! @{ */
74835 
74836 #define OCOTP_CTRL_ADDR_MASK                     (0x3FFU)
74837 #define OCOTP_CTRL_ADDR_SHIFT                    (0U)
74838 /*! ADDR - OTP write and read access address register
74839  *  0b0000000000-0b0000001111..Address of one of the 16 supplementary fuse words in OTP memory.
74840  *  0b0000010000-0b0100001111..Address of one of the 256 user fuse words in OTP memory.
74841  */
74842 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
74843 
74844 #define OCOTP_CTRL_BUSY_MASK                     (0x400U)
74845 #define OCOTP_CTRL_BUSY_SHIFT                    (10U)
74846 /*! BUSY - OTP controller status bit
74847  *  0b0..No write or read access to OTP started.
74848  *  0b1..Write or read access to OTP started.
74849  */
74850 #define OCOTP_CTRL_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
74851 
74852 #define OCOTP_CTRL_ERROR_MASK                    (0x800U)
74853 #define OCOTP_CTRL_ERROR_SHIFT                   (11U)
74854 /*! ERROR - Locked Region Access Error
74855  *  0b0..No error.
74856  *  0b1..Error - access to a locked region requested.
74857  */
74858 #define OCOTP_CTRL_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
74859 
74860 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           (0x1000U)
74861 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          (12U)
74862 /*! RELOAD_SHADOWS - Reload Shadow Registers
74863  *  0b0..Do not force shadow register re-load.
74864  *  0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded.
74865  */
74866 #define OCOTP_CTRL_RELOAD_SHADOWS(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
74867 
74868 #define OCOTP_CTRL_WORDLOCK_MASK                 (0x8000U)
74869 #define OCOTP_CTRL_WORDLOCK_SHIFT                (15U)
74870 /*! WORDLOCK - Lock fuse word
74871  *  0b0..No change to LOCK bit when programming a word using redundancy
74872  *  0b1..LOCK bit for fuse word will be set after successfully programming a word using redundancy
74873  */
74874 #define OCOTP_CTRL_WORDLOCK(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK)
74875 
74876 #define OCOTP_CTRL_WR_UNLOCK_MASK                (0xFFFF0000U)
74877 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               (16U)
74878 /*! WR_UNLOCK - Write unlock
74879  *  0b0000000000000000..OTP write access is locked.
74880  *  0b0011111001110111..OTP write access is unlocked.
74881  */
74882 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
74883 /*! @} */
74884 
74885 /*! @name CTRL_SET - OTP Controller Control and Status Register */
74886 /*! @{ */
74887 
74888 #define OCOTP_CTRL_SET_ADDR_MASK                 (0x3FFU)
74889 #define OCOTP_CTRL_SET_ADDR_SHIFT                (0U)
74890 /*! ADDR - OTP write and read access address register
74891  */
74892 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
74893 
74894 #define OCOTP_CTRL_SET_BUSY_MASK                 (0x400U)
74895 #define OCOTP_CTRL_SET_BUSY_SHIFT                (10U)
74896 /*! BUSY - OTP controller status bit
74897  */
74898 #define OCOTP_CTRL_SET_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
74899 
74900 #define OCOTP_CTRL_SET_ERROR_MASK                (0x800U)
74901 #define OCOTP_CTRL_SET_ERROR_SHIFT               (11U)
74902 /*! ERROR - Locked Region Access Error
74903  */
74904 #define OCOTP_CTRL_SET_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
74905 
74906 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       (0x1000U)
74907 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      (12U)
74908 /*! RELOAD_SHADOWS - Reload Shadow Registers
74909  */
74910 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
74911 
74912 #define OCOTP_CTRL_SET_WORDLOCK_MASK             (0x8000U)
74913 #define OCOTP_CTRL_SET_WORDLOCK_SHIFT            (15U)
74914 /*! WORDLOCK - Lock fuse word
74915  */
74916 #define OCOTP_CTRL_SET_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK)
74917 
74918 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            (0xFFFF0000U)
74919 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           (16U)
74920 /*! WR_UNLOCK - Write unlock
74921  */
74922 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
74923 /*! @} */
74924 
74925 /*! @name CTRL_CLR - OTP Controller Control and Status Register */
74926 /*! @{ */
74927 
74928 #define OCOTP_CTRL_CLR_ADDR_MASK                 (0x3FFU)
74929 #define OCOTP_CTRL_CLR_ADDR_SHIFT                (0U)
74930 /*! ADDR - OTP write and read access address register
74931  */
74932 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
74933 
74934 #define OCOTP_CTRL_CLR_BUSY_MASK                 (0x400U)
74935 #define OCOTP_CTRL_CLR_BUSY_SHIFT                (10U)
74936 /*! BUSY - OTP controller status bit
74937  */
74938 #define OCOTP_CTRL_CLR_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
74939 
74940 #define OCOTP_CTRL_CLR_ERROR_MASK                (0x800U)
74941 #define OCOTP_CTRL_CLR_ERROR_SHIFT               (11U)
74942 /*! ERROR - Locked Region Access Error
74943  */
74944 #define OCOTP_CTRL_CLR_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
74945 
74946 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       (0x1000U)
74947 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      (12U)
74948 /*! RELOAD_SHADOWS - Reload Shadow Registers
74949  */
74950 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
74951 
74952 #define OCOTP_CTRL_CLR_WORDLOCK_MASK             (0x8000U)
74953 #define OCOTP_CTRL_CLR_WORDLOCK_SHIFT            (15U)
74954 /*! WORDLOCK - Lock fuse word
74955  */
74956 #define OCOTP_CTRL_CLR_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK)
74957 
74958 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            (0xFFFF0000U)
74959 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           (16U)
74960 /*! WR_UNLOCK - Write unlock
74961  */
74962 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
74963 /*! @} */
74964 
74965 /*! @name CTRL_TOG - OTP Controller Control and Status Register */
74966 /*! @{ */
74967 
74968 #define OCOTP_CTRL_TOG_ADDR_MASK                 (0x3FFU)
74969 #define OCOTP_CTRL_TOG_ADDR_SHIFT                (0U)
74970 /*! ADDR - OTP write and read access address register
74971  */
74972 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
74973 
74974 #define OCOTP_CTRL_TOG_BUSY_MASK                 (0x400U)
74975 #define OCOTP_CTRL_TOG_BUSY_SHIFT                (10U)
74976 /*! BUSY - OTP controller status bit
74977  */
74978 #define OCOTP_CTRL_TOG_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
74979 
74980 #define OCOTP_CTRL_TOG_ERROR_MASK                (0x800U)
74981 #define OCOTP_CTRL_TOG_ERROR_SHIFT               (11U)
74982 /*! ERROR - Locked Region Access Error
74983  */
74984 #define OCOTP_CTRL_TOG_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
74985 
74986 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       (0x1000U)
74987 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      (12U)
74988 /*! RELOAD_SHADOWS - Reload Shadow Registers
74989  */
74990 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
74991 
74992 #define OCOTP_CTRL_TOG_WORDLOCK_MASK             (0x8000U)
74993 #define OCOTP_CTRL_TOG_WORDLOCK_SHIFT            (15U)
74994 /*! WORDLOCK - Lock fuse word
74995  */
74996 #define OCOTP_CTRL_TOG_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK)
74997 
74998 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            (0xFFFF0000U)
74999 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           (16U)
75000 /*! WR_UNLOCK - Write unlock
75001  */
75002 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
75003 /*! @} */
75004 
75005 /*! @name PDN - OTP Controller PDN Register */
75006 /*! @{ */
75007 
75008 #define OCOTP_PDN_PDN_MASK                       (0x1U)
75009 #define OCOTP_PDN_PDN_SHIFT                      (0U)
75010 /*! PDN - PDN value
75011  *  0b0..OTP memory is not powered
75012  *  0b1..OTP memory is powered
75013  */
75014 #define OCOTP_PDN_PDN(x)                         (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK)
75015 /*! @} */
75016 
75017 /*! @name DATA - OTP Controller Write Data Register */
75018 /*! @{ */
75019 
75020 #define OCOTP_DATA_DATA_MASK                     (0xFFFFFFFFU)
75021 #define OCOTP_DATA_DATA_SHIFT                    (0U)
75022 /*! DATA - Data
75023  */
75024 #define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
75025 /*! @} */
75026 
75027 /*! @name READ_CTRL - OTP Controller Read Control Register */
75028 /*! @{ */
75029 
75030 #define OCOTP_READ_CTRL_READ_FUSE_MASK           (0x1U)
75031 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          (0U)
75032 /*! READ_FUSE - Read Fuse
75033  *  0b0..Do not initiate a read from OTP
75034  *  0b1..Initiate a read from OTP
75035  */
75036 #define OCOTP_READ_CTRL_READ_FUSE(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
75037 
75038 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK      (0x6U)
75039 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT     (1U)
75040 /*! READ_FUSE_CNTR - Number of words to read.
75041  *  0b00..1 word
75042  *  0b01..2 words
75043  *  0b10..3 words
75044  *  0b11..4 words
75045  */
75046 #define OCOTP_READ_CTRL_READ_FUSE_CNTR(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK)
75047 
75048 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U)
75049 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U)
75050 /*! READ_FUSE_DONE_INTR_ENA - Enable read-done interrupt
75051  *  0b0..Disable
75052  *  0b1..Enable
75053  */
75054 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK)
75055 
75056 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U)
75057 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U)
75058 /*! READ_FUSE_ERROR_INTR_ENA - Enable read-error interrupt
75059  *  0b0..Disable
75060  *  0b1..Enable
75061  */
75062 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK)
75063 /*! @} */
75064 
75065 /*! @name OUT_STATUS - 8K OTP Memory STATUS Register */
75066 /*! @{ */
75067 
75068 #define OCOTP_OUT_STATUS_SEC_MASK                (0x200U)
75069 #define OCOTP_OUT_STATUS_SEC_SHIFT               (9U)
75070 /*! SEC - Single Error Correct
75071  */
75072 #define OCOTP_OUT_STATUS_SEC(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK)
75073 
75074 #define OCOTP_OUT_STATUS_DED_MASK                (0x400U)
75075 #define OCOTP_OUT_STATUS_DED_SHIFT               (10U)
75076 /*! DED - Double error detect
75077  */
75078 #define OCOTP_OUT_STATUS_DED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK)
75079 
75080 #define OCOTP_OUT_STATUS_LOCKED_MASK             (0x800U)
75081 #define OCOTP_OUT_STATUS_LOCKED_SHIFT            (11U)
75082 /*! LOCKED - Word Locked
75083  */
75084 #define OCOTP_OUT_STATUS_LOCKED(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK)
75085 
75086 #define OCOTP_OUT_STATUS_PROGFAIL_MASK           (0x1000U)
75087 #define OCOTP_OUT_STATUS_PROGFAIL_SHIFT          (12U)
75088 /*! PROGFAIL - Programming failed
75089  */
75090 #define OCOTP_OUT_STATUS_PROGFAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK)
75091 
75092 #define OCOTP_OUT_STATUS_ACK_MASK                (0x2000U)
75093 #define OCOTP_OUT_STATUS_ACK_SHIFT               (13U)
75094 /*! ACK - Acknowledge
75095  */
75096 #define OCOTP_OUT_STATUS_ACK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK)
75097 
75098 #define OCOTP_OUT_STATUS_PWOK_MASK               (0x4000U)
75099 #define OCOTP_OUT_STATUS_PWOK_SHIFT              (14U)
75100 /*! PWOK - Power OK
75101  */
75102 #define OCOTP_OUT_STATUS_PWOK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK)
75103 
75104 #define OCOTP_OUT_STATUS_FLAGSTATE_MASK          (0x78000U)
75105 #define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT         (15U)
75106 /*! FLAGSTATE - Flag state
75107  */
75108 #define OCOTP_OUT_STATUS_FLAGSTATE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK)
75109 
75110 #define OCOTP_OUT_STATUS_SEC_RELOAD_MASK         (0x80000U)
75111 #define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT        (19U)
75112 /*! SEC_RELOAD - Indicates single error correction occured on reload
75113  */
75114 #define OCOTP_OUT_STATUS_SEC_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK)
75115 
75116 #define OCOTP_OUT_STATUS_DED_RELOAD_MASK         (0x100000U)
75117 #define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT        (20U)
75118 /*! DED_RELOAD - Indicates double error detection occured on reload
75119  */
75120 #define OCOTP_OUT_STATUS_DED_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK)
75121 
75122 #define OCOTP_OUT_STATUS_CALIBRATED_MASK         (0x200000U)
75123 #define OCOTP_OUT_STATUS_CALIBRATED_SHIFT        (21U)
75124 /*! CALIBRATED - Calibrated status
75125  */
75126 #define OCOTP_OUT_STATUS_CALIBRATED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK)
75127 
75128 #define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK     (0x400000U)
75129 #define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT    (22U)
75130 /*! READ_DONE_INTR - Read fuse done
75131  */
75132 #define OCOTP_OUT_STATUS_READ_DONE_INTR(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK)
75133 
75134 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK    (0x800000U)
75135 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT   (23U)
75136 /*! READ_ERROR_INTR - Fuse read error
75137  *  0b0..Read operation finished with out any error
75138  *  0b1..Read operation finished with an error
75139  */
75140 #define OCOTP_OUT_STATUS_READ_ERROR_INTR(x)      (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK)
75141 
75142 #define OCOTP_OUT_STATUS_DED0_MASK               (0x1000000U)
75143 #define OCOTP_OUT_STATUS_DED0_SHIFT              (24U)
75144 /*! DED0 - Double error detect
75145  */
75146 #define OCOTP_OUT_STATUS_DED0(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK)
75147 
75148 #define OCOTP_OUT_STATUS_DED1_MASK               (0x2000000U)
75149 #define OCOTP_OUT_STATUS_DED1_SHIFT              (25U)
75150 /*! DED1 - Double error detect
75151  */
75152 #define OCOTP_OUT_STATUS_DED1(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK)
75153 
75154 #define OCOTP_OUT_STATUS_DED2_MASK               (0x4000000U)
75155 #define OCOTP_OUT_STATUS_DED2_SHIFT              (26U)
75156 /*! DED2 - Double error detect
75157  */
75158 #define OCOTP_OUT_STATUS_DED2(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK)
75159 
75160 #define OCOTP_OUT_STATUS_DED3_MASK               (0x8000000U)
75161 #define OCOTP_OUT_STATUS_DED3_SHIFT              (27U)
75162 /*! DED3 - Double error detect
75163  */
75164 #define OCOTP_OUT_STATUS_DED3(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK)
75165 /*! @} */
75166 
75167 /*! @name OUT_STATUS_SET - 8K OTP Memory STATUS Register */
75168 /*! @{ */
75169 
75170 #define OCOTP_OUT_STATUS_SET_SEC_MASK            (0x200U)
75171 #define OCOTP_OUT_STATUS_SET_SEC_SHIFT           (9U)
75172 /*! SEC - Single Error Correct
75173  */
75174 #define OCOTP_OUT_STATUS_SET_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK)
75175 
75176 #define OCOTP_OUT_STATUS_SET_DED_MASK            (0x400U)
75177 #define OCOTP_OUT_STATUS_SET_DED_SHIFT           (10U)
75178 /*! DED - Double error detect
75179  */
75180 #define OCOTP_OUT_STATUS_SET_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK)
75181 
75182 #define OCOTP_OUT_STATUS_SET_LOCKED_MASK         (0x800U)
75183 #define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT        (11U)
75184 /*! LOCKED - Word Locked
75185  */
75186 #define OCOTP_OUT_STATUS_SET_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK)
75187 
75188 #define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK       (0x1000U)
75189 #define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT      (12U)
75190 /*! PROGFAIL - Programming failed
75191  */
75192 #define OCOTP_OUT_STATUS_SET_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK)
75193 
75194 #define OCOTP_OUT_STATUS_SET_ACK_MASK            (0x2000U)
75195 #define OCOTP_OUT_STATUS_SET_ACK_SHIFT           (13U)
75196 /*! ACK - Acknowledge
75197  */
75198 #define OCOTP_OUT_STATUS_SET_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK)
75199 
75200 #define OCOTP_OUT_STATUS_SET_PWOK_MASK           (0x4000U)
75201 #define OCOTP_OUT_STATUS_SET_PWOK_SHIFT          (14U)
75202 /*! PWOK - Power OK
75203  */
75204 #define OCOTP_OUT_STATUS_SET_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK)
75205 
75206 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK      (0x78000U)
75207 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT     (15U)
75208 /*! FLAGSTATE - Flag state
75209  */
75210 #define OCOTP_OUT_STATUS_SET_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK)
75211 
75212 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK     (0x80000U)
75213 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT    (19U)
75214 /*! SEC_RELOAD - Indicates single error correction occured on reload
75215  */
75216 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK)
75217 
75218 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK     (0x100000U)
75219 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT    (20U)
75220 /*! DED_RELOAD - Indicates double error detection occured on reload
75221  */
75222 #define OCOTP_OUT_STATUS_SET_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK)
75223 
75224 #define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK     (0x200000U)
75225 #define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT    (21U)
75226 /*! CALIBRATED - Calibrated status
75227  */
75228 #define OCOTP_OUT_STATUS_SET_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK)
75229 
75230 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U)
75231 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U)
75232 /*! READ_DONE_INTR - Read fuse done
75233  */
75234 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK)
75235 
75236 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U)
75237 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U)
75238 /*! READ_ERROR_INTR - Fuse read error
75239  */
75240 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK)
75241 
75242 #define OCOTP_OUT_STATUS_SET_DED0_MASK           (0x1000000U)
75243 #define OCOTP_OUT_STATUS_SET_DED0_SHIFT          (24U)
75244 /*! DED0 - Double error detect
75245  */
75246 #define OCOTP_OUT_STATUS_SET_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK)
75247 
75248 #define OCOTP_OUT_STATUS_SET_DED1_MASK           (0x2000000U)
75249 #define OCOTP_OUT_STATUS_SET_DED1_SHIFT          (25U)
75250 /*! DED1 - Double error detect
75251  */
75252 #define OCOTP_OUT_STATUS_SET_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK)
75253 
75254 #define OCOTP_OUT_STATUS_SET_DED2_MASK           (0x4000000U)
75255 #define OCOTP_OUT_STATUS_SET_DED2_SHIFT          (26U)
75256 /*! DED2 - Double error detect
75257  */
75258 #define OCOTP_OUT_STATUS_SET_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK)
75259 
75260 #define OCOTP_OUT_STATUS_SET_DED3_MASK           (0x8000000U)
75261 #define OCOTP_OUT_STATUS_SET_DED3_SHIFT          (27U)
75262 /*! DED3 - Double error detect
75263  */
75264 #define OCOTP_OUT_STATUS_SET_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK)
75265 /*! @} */
75266 
75267 /*! @name OUT_STATUS_CLR - 8K OTP Memory STATUS Register */
75268 /*! @{ */
75269 
75270 #define OCOTP_OUT_STATUS_CLR_SEC_MASK            (0x200U)
75271 #define OCOTP_OUT_STATUS_CLR_SEC_SHIFT           (9U)
75272 /*! SEC - Single Error Correct
75273  */
75274 #define OCOTP_OUT_STATUS_CLR_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK)
75275 
75276 #define OCOTP_OUT_STATUS_CLR_DED_MASK            (0x400U)
75277 #define OCOTP_OUT_STATUS_CLR_DED_SHIFT           (10U)
75278 /*! DED - Double error detect
75279  */
75280 #define OCOTP_OUT_STATUS_CLR_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK)
75281 
75282 #define OCOTP_OUT_STATUS_CLR_LOCKED_MASK         (0x800U)
75283 #define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT        (11U)
75284 /*! LOCKED - Word Locked
75285  */
75286 #define OCOTP_OUT_STATUS_CLR_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK)
75287 
75288 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK       (0x1000U)
75289 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT      (12U)
75290 /*! PROGFAIL - Programming failed
75291  */
75292 #define OCOTP_OUT_STATUS_CLR_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK)
75293 
75294 #define OCOTP_OUT_STATUS_CLR_ACK_MASK            (0x2000U)
75295 #define OCOTP_OUT_STATUS_CLR_ACK_SHIFT           (13U)
75296 /*! ACK - Acknowledge
75297  */
75298 #define OCOTP_OUT_STATUS_CLR_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK)
75299 
75300 #define OCOTP_OUT_STATUS_CLR_PWOK_MASK           (0x4000U)
75301 #define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT          (14U)
75302 /*! PWOK - Power OK
75303  */
75304 #define OCOTP_OUT_STATUS_CLR_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK)
75305 
75306 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK      (0x78000U)
75307 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT     (15U)
75308 /*! FLAGSTATE - Flag state
75309  */
75310 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK)
75311 
75312 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK     (0x80000U)
75313 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT    (19U)
75314 /*! SEC_RELOAD - Indicates single error correction occured on reload
75315  */
75316 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK)
75317 
75318 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK     (0x100000U)
75319 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT    (20U)
75320 /*! DED_RELOAD - Indicates double error detection occured on reload
75321  */
75322 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK)
75323 
75324 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK     (0x200000U)
75325 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT    (21U)
75326 /*! CALIBRATED - Calibrated status
75327  */
75328 #define OCOTP_OUT_STATUS_CLR_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK)
75329 
75330 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U)
75331 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U)
75332 /*! READ_DONE_INTR - Read fuse done
75333  */
75334 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK)
75335 
75336 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U)
75337 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U)
75338 /*! READ_ERROR_INTR - Fuse read error
75339  */
75340 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK)
75341 
75342 #define OCOTP_OUT_STATUS_CLR_DED0_MASK           (0x1000000U)
75343 #define OCOTP_OUT_STATUS_CLR_DED0_SHIFT          (24U)
75344 /*! DED0 - Double error detect
75345  */
75346 #define OCOTP_OUT_STATUS_CLR_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK)
75347 
75348 #define OCOTP_OUT_STATUS_CLR_DED1_MASK           (0x2000000U)
75349 #define OCOTP_OUT_STATUS_CLR_DED1_SHIFT          (25U)
75350 /*! DED1 - Double error detect
75351  */
75352 #define OCOTP_OUT_STATUS_CLR_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK)
75353 
75354 #define OCOTP_OUT_STATUS_CLR_DED2_MASK           (0x4000000U)
75355 #define OCOTP_OUT_STATUS_CLR_DED2_SHIFT          (26U)
75356 /*! DED2 - Double error detect
75357  */
75358 #define OCOTP_OUT_STATUS_CLR_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK)
75359 
75360 #define OCOTP_OUT_STATUS_CLR_DED3_MASK           (0x8000000U)
75361 #define OCOTP_OUT_STATUS_CLR_DED3_SHIFT          (27U)
75362 /*! DED3 - Double error detect
75363  */
75364 #define OCOTP_OUT_STATUS_CLR_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK)
75365 /*! @} */
75366 
75367 /*! @name OUT_STATUS_TOG - 8K OTP Memory STATUS Register */
75368 /*! @{ */
75369 
75370 #define OCOTP_OUT_STATUS_TOG_SEC_MASK            (0x200U)
75371 #define OCOTP_OUT_STATUS_TOG_SEC_SHIFT           (9U)
75372 /*! SEC - Single Error Correct
75373  */
75374 #define OCOTP_OUT_STATUS_TOG_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK)
75375 
75376 #define OCOTP_OUT_STATUS_TOG_DED_MASK            (0x400U)
75377 #define OCOTP_OUT_STATUS_TOG_DED_SHIFT           (10U)
75378 /*! DED - Double error detect
75379  */
75380 #define OCOTP_OUT_STATUS_TOG_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK)
75381 
75382 #define OCOTP_OUT_STATUS_TOG_LOCKED_MASK         (0x800U)
75383 #define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT        (11U)
75384 /*! LOCKED - Word Locked
75385  */
75386 #define OCOTP_OUT_STATUS_TOG_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK)
75387 
75388 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK       (0x1000U)
75389 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT      (12U)
75390 /*! PROGFAIL - Programming failed
75391  */
75392 #define OCOTP_OUT_STATUS_TOG_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK)
75393 
75394 #define OCOTP_OUT_STATUS_TOG_ACK_MASK            (0x2000U)
75395 #define OCOTP_OUT_STATUS_TOG_ACK_SHIFT           (13U)
75396 /*! ACK - Acknowledge
75397  */
75398 #define OCOTP_OUT_STATUS_TOG_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK)
75399 
75400 #define OCOTP_OUT_STATUS_TOG_PWOK_MASK           (0x4000U)
75401 #define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT          (14U)
75402 /*! PWOK - Power OK
75403  */
75404 #define OCOTP_OUT_STATUS_TOG_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK)
75405 
75406 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK      (0x78000U)
75407 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT     (15U)
75408 /*! FLAGSTATE - Flag state
75409  */
75410 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK)
75411 
75412 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK     (0x80000U)
75413 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT    (19U)
75414 /*! SEC_RELOAD - Indicates single error correction occured on reload
75415  */
75416 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK)
75417 
75418 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK     (0x100000U)
75419 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT    (20U)
75420 /*! DED_RELOAD - Indicates double error detection occured on reload
75421  */
75422 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK)
75423 
75424 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK     (0x200000U)
75425 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT    (21U)
75426 /*! CALIBRATED - Calibrated status
75427  */
75428 #define OCOTP_OUT_STATUS_TOG_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK)
75429 
75430 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U)
75431 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U)
75432 /*! READ_DONE_INTR - Read fuse done
75433  */
75434 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK)
75435 
75436 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U)
75437 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U)
75438 /*! READ_ERROR_INTR - Fuse read error
75439  */
75440 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK)
75441 
75442 #define OCOTP_OUT_STATUS_TOG_DED0_MASK           (0x1000000U)
75443 #define OCOTP_OUT_STATUS_TOG_DED0_SHIFT          (24U)
75444 /*! DED0 - Double error detect
75445  */
75446 #define OCOTP_OUT_STATUS_TOG_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK)
75447 
75448 #define OCOTP_OUT_STATUS_TOG_DED1_MASK           (0x2000000U)
75449 #define OCOTP_OUT_STATUS_TOG_DED1_SHIFT          (25U)
75450 /*! DED1 - Double error detect
75451  */
75452 #define OCOTP_OUT_STATUS_TOG_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK)
75453 
75454 #define OCOTP_OUT_STATUS_TOG_DED2_MASK           (0x4000000U)
75455 #define OCOTP_OUT_STATUS_TOG_DED2_SHIFT          (26U)
75456 /*! DED2 - Double error detect
75457  */
75458 #define OCOTP_OUT_STATUS_TOG_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK)
75459 
75460 #define OCOTP_OUT_STATUS_TOG_DED3_MASK           (0x8000000U)
75461 #define OCOTP_OUT_STATUS_TOG_DED3_SHIFT          (27U)
75462 /*! DED3 - Double error detect
75463  */
75464 #define OCOTP_OUT_STATUS_TOG_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK)
75465 /*! @} */
75466 
75467 /*! @name VERSION - OTP Controller Version Register */
75468 /*! @{ */
75469 
75470 #define OCOTP_VERSION_STEP_MASK                  (0xFFFFU)
75471 #define OCOTP_VERSION_STEP_SHIFT                 (0U)
75472 /*! STEP - RTL Version Stepping
75473  */
75474 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
75475 
75476 #define OCOTP_VERSION_MINOR_MASK                 (0xFF0000U)
75477 #define OCOTP_VERSION_MINOR_SHIFT                (16U)
75478 /*! MINOR - Minor RTL Version
75479  */
75480 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
75481 
75482 #define OCOTP_VERSION_MAJOR_MASK                 (0xFF000000U)
75483 #define OCOTP_VERSION_MAJOR_SHIFT                (24U)
75484 /*! MAJOR - Major RTL Version
75485  */
75486 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
75487 /*! @} */
75488 
75489 /*! @name READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register */
75490 /*! @{ */
75491 
75492 #define OCOTP_READ_FUSE_DATA_DATA_MASK           (0xFFFFFFFFU)
75493 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT          (0U)
75494 /*! DATA - Data
75495  */
75496 #define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
75497 /*! @} */
75498 
75499 /* The count of OCOTP_READ_FUSE_DATA */
75500 #define OCOTP_READ_FUSE_DATA_COUNT               (4U)
75501 
75502 /*! @name SW_LOCK - SW_LOCK Register */
75503 /*! @{ */
75504 
75505 #define OCOTP_SW_LOCK_SW_LOCK_MASK               (0xFFFFFFFFU)
75506 #define OCOTP_SW_LOCK_SW_LOCK_SHIFT              (0U)
75507 #define OCOTP_SW_LOCK_SW_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK)
75508 /*! @} */
75509 
75510 /*! @name BIT_LOCK - BIT_LOCK Register */
75511 /*! @{ */
75512 
75513 #define OCOTP_BIT_LOCK_BIT_LOCK_MASK             (0xFFFFFFFFU)
75514 #define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT            (0U)
75515 #define OCOTP_BIT_LOCK_BIT_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK)
75516 /*! @} */
75517 
75518 /*! @name LOCKED0 - OTP Controller Program Locked Status 0 Register */
75519 /*! @{ */
75520 
75521 #define OCOTP_LOCKED0_LOCKED_MASK                (0xFFFFU)
75522 #define OCOTP_LOCKED0_LOCKED_SHIFT               (0U)
75523 #define OCOTP_LOCKED0_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK)
75524 /*! @} */
75525 
75526 /*! @name LOCKED1 - OTP Controller Program Locked Status 1 Register */
75527 /*! @{ */
75528 
75529 #define OCOTP_LOCKED1_LOCKED_MASK                (0xFFFFFFFFU)
75530 #define OCOTP_LOCKED1_LOCKED_SHIFT               (0U)
75531 #define OCOTP_LOCKED1_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK)
75532 /*! @} */
75533 
75534 /*! @name LOCKED2 - OTP Controller Program Locked Status 2 Register */
75535 /*! @{ */
75536 
75537 #define OCOTP_LOCKED2_LOCKED_MASK                (0xFFFFFFFFU)
75538 #define OCOTP_LOCKED2_LOCKED_SHIFT               (0U)
75539 #define OCOTP_LOCKED2_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK)
75540 /*! @} */
75541 
75542 /*! @name LOCKED3 - OTP Controller Program Locked Status 3 Register */
75543 /*! @{ */
75544 
75545 #define OCOTP_LOCKED3_LOCKED_MASK                (0xFFFFFFFFU)
75546 #define OCOTP_LOCKED3_LOCKED_SHIFT               (0U)
75547 #define OCOTP_LOCKED3_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK)
75548 /*! @} */
75549 
75550 /*! @name LOCKED4 - OTP Controller Program Locked Status 4 Register */
75551 /*! @{ */
75552 
75553 #define OCOTP_LOCKED4_LOCKED_MASK                (0xFFFFFFFFU)
75554 #define OCOTP_LOCKED4_LOCKED_SHIFT               (0U)
75555 #define OCOTP_LOCKED4_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK)
75556 /*! @} */
75557 
75558 /*! @name FUSE - Value of fuse word 0..Value of fuse word 143 */
75559 /*! @{ */
75560 
75561 #define OCOTP_FUSE_BITS_MASK                     (0xFFFFFFFFU)
75562 #define OCOTP_FUSE_BITS_SHIFT                    (0U)
75563 /*! BITS - Reflects value of the fuse word
75564  */
75565 #define OCOTP_FUSE_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK)
75566 /*! @} */
75567 
75568 /* The count of OCOTP_FUSE */
75569 #define OCOTP_FUSE_COUNT                         (144U)
75570 
75571 
75572 /*!
75573  * @}
75574  */ /* end of group OCOTP_Register_Masks */
75575 
75576 
75577 /* OCOTP - Peripheral instance base addresses */
75578 /** Peripheral OCOTP base address */
75579 #define OCOTP_BASE                               (0x40CAC000u)
75580 /** Peripheral OCOTP base pointer */
75581 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
75582 /** Array initializer of OCOTP peripheral base addresses */
75583 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
75584 /** Array initializer of OCOTP peripheral base pointers */
75585 #define OCOTP_BASE_PTRS                          { OCOTP }
75586 
75587 /*!
75588  * @}
75589  */ /* end of group OCOTP_Peripheral_Access_Layer */
75590 
75591 
75592 /* ----------------------------------------------------------------------------
75593    -- OSC_RC_400M Peripheral Access Layer
75594    ---------------------------------------------------------------------------- */
75595 
75596 /*!
75597  * @addtogroup OSC_RC_400M_Peripheral_Access_Layer OSC_RC_400M Peripheral Access Layer
75598  * @{
75599  */
75600 
75601 /** OSC_RC_400M - Register Layout Typedef */
75602 typedef struct {
75603   struct {                                         /* offset: 0x0 */
75604     __IO uint32_t RW;                                /**< Control Register 0, offset: 0x0 */
75605     __IO uint32_t SET;                               /**< Control Register 0, offset: 0x4 */
75606     __IO uint32_t CLR;                               /**< Control Register 0, offset: 0x8 */
75607     __IO uint32_t TOG;                               /**< Control Register 0, offset: 0xC */
75608   } CTRL0;
75609   struct {                                         /* offset: 0x10 */
75610     __IO uint32_t RW;                                /**< Control Register 1, offset: 0x10 */
75611     __IO uint32_t SET;                               /**< Control Register 1, offset: 0x14 */
75612     __IO uint32_t CLR;                               /**< Control Register 1, offset: 0x18 */
75613     __IO uint32_t TOG;                               /**< Control Register 1, offset: 0x1C */
75614   } CTRL1;
75615   struct {                                         /* offset: 0x20 */
75616     __IO uint32_t RW;                                /**< Control Register 2, offset: 0x20 */
75617     __IO uint32_t SET;                               /**< Control Register 2, offset: 0x24 */
75618     __IO uint32_t CLR;                               /**< Control Register 2, offset: 0x28 */
75619     __IO uint32_t TOG;                               /**< Control Register 2, offset: 0x2C */
75620   } CTRL2;
75621   struct {                                         /* offset: 0x30 */
75622     __IO uint32_t RW;                                /**< Control Register 3, offset: 0x30 */
75623     __IO uint32_t SET;                               /**< Control Register 3, offset: 0x34 */
75624     __IO uint32_t CLR;                               /**< Control Register 3, offset: 0x38 */
75625     __IO uint32_t TOG;                               /**< Control Register 3, offset: 0x3C */
75626   } CTRL3;
75627        uint8_t RESERVED_0[16];
75628   struct {                                         /* offset: 0x50 */
75629     __I  uint32_t RW;                                /**< Status Register 0, offset: 0x50 */
75630     __I  uint32_t SET;                               /**< Status Register 0, offset: 0x54 */
75631     __I  uint32_t CLR;                               /**< Status Register 0, offset: 0x58 */
75632     __I  uint32_t TOG;                               /**< Status Register 0, offset: 0x5C */
75633   } STAT0;
75634   struct {                                         /* offset: 0x60 */
75635     __I  uint32_t RW;                                /**< Status Register 1, offset: 0x60 */
75636     __I  uint32_t SET;                               /**< Status Register 1, offset: 0x64 */
75637     __I  uint32_t CLR;                               /**< Status Register 1, offset: 0x68 */
75638     __I  uint32_t TOG;                               /**< Status Register 1, offset: 0x6C */
75639   } STAT1;
75640   struct {                                         /* offset: 0x70 */
75641     __I  uint32_t RW;                                /**< Status Register 2, offset: 0x70 */
75642     __I  uint32_t SET;                               /**< Status Register 2, offset: 0x74 */
75643     __I  uint32_t CLR;                               /**< Status Register 2, offset: 0x78 */
75644     __I  uint32_t TOG;                               /**< Status Register 2, offset: 0x7C */
75645   } STAT2;
75646 } OSC_RC_400M_Type;
75647 
75648 /* ----------------------------------------------------------------------------
75649    -- OSC_RC_400M Register Masks
75650    ---------------------------------------------------------------------------- */
75651 
75652 /*!
75653  * @addtogroup OSC_RC_400M_Register_Masks OSC_RC_400M Register Masks
75654  * @{
75655  */
75656 
75657 /*! @name CTRL0 - Control Register 0 */
75658 /*! @{ */
75659 
75660 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK       (0x3F000000U)
75661 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT      (24U)
75662 /*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP)
75663  */
75664 #define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)         (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
75665 /*! @} */
75666 
75667 /*! @name CTRL1 - Control Register 1 */
75668 /*! @{ */
75669 
75670 #define OSC_RC_400M_CTRL1_HYST_MINUS_MASK        (0xFU)
75671 #define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT       (0U)
75672 /*! HYST_MINUS - Negative hysteresis value for the tuned clock
75673  */
75674 #define OSC_RC_400M_CTRL1_HYST_MINUS(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
75675 
75676 #define OSC_RC_400M_CTRL1_HYST_PLUS_MASK         (0xF00U)
75677 #define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT        (8U)
75678 /*! HYST_PLUS - Positive hysteresis value for the tuned clock
75679  */
75680 #define OSC_RC_400M_CTRL1_HYST_PLUS(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
75681 
75682 #define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK      (0xFFFF0000U)
75683 #define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT     (16U)
75684 /*! TARGET_COUNT - Target count for the fast clock
75685  */
75686 #define OSC_RC_400M_CTRL1_TARGET_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
75687 /*! @} */
75688 
75689 /*! @name CTRL2 - Control Register 2 */
75690 /*! @{ */
75691 
75692 #define OSC_RC_400M_CTRL2_TUNE_BYP_MASK          (0x400U)
75693 #define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT         (10U)
75694 /*! TUNE_BYP - Bypass the tuning logic
75695  *  0b0..Use the output of tuning logic to run the oscillator
75696  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
75697  */
75698 #define OSC_RC_400M_CTRL2_TUNE_BYP(x)            (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
75699 
75700 #define OSC_RC_400M_CTRL2_TUNE_EN_MASK           (0x1000U)
75701 #define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT          (12U)
75702 /*! TUNE_EN - Freeze/Unfreeze the tuning value
75703  *  0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value
75704  *  0b1..Unfreezes and continues the tuning operation
75705  */
75706 #define OSC_RC_400M_CTRL2_TUNE_EN(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
75707 
75708 #define OSC_RC_400M_CTRL2_TUNE_START_MASK        (0x4000U)
75709 #define OSC_RC_400M_CTRL2_TUNE_START_SHIFT       (14U)
75710 /*! TUNE_START - Start/Stop tuning
75711  *  0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL
75712  *  0b1..Start tuning
75713  */
75714 #define OSC_RC_400M_CTRL2_TUNE_START(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
75715 
75716 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK      (0xFF000000U)
75717 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT     (24U)
75718 /*! OSC_TUNE_VAL - Program the oscillator frequency
75719  */
75720 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
75721 /*! @} */
75722 
75723 /*! @name CTRL3 - Control Register 3 */
75724 /*! @{ */
75725 
75726 #define OSC_RC_400M_CTRL3_CLR_ERR_MASK           (0x1U)
75727 #define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT          (0U)
75728 /*! CLR_ERR - Clear the error flag CLK1M_ERR
75729  *  0b0..No effect
75730  *  0b1..Clears the error flag CLK1M_ERR in status register STAT0
75731  */
75732 #define OSC_RC_400M_CTRL3_CLR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
75733 
75734 #define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK         (0x100U)
75735 #define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT        (8U)
75736 /*! EN_1M_CLK - Enable 1MHz output Clock
75737  *  0b0..Enable the output (clk_1m_out)
75738  *  0b1..Disable the output (clk_1m_out)
75739  */
75740 #define OSC_RC_400M_CTRL3_EN_1M_CLK(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
75741 
75742 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK        (0x400U)
75743 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT       (10U)
75744 /*! MUX_1M_CLK - Select free/locked 1MHz output
75745  *  0b0..Select free-running 1MHz to be put out on clk_1m_out
75746  *  0b1..Select locked 1MHz to be put out on clk_1m_out
75747  */
75748 #define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
75749 
75750 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK      (0xFFFF0000U)
75751 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT     (16U)
75752 /*! COUNT_1M_CLK - Count for the locked clk_1m_out
75753  */
75754 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
75755 /*! @} */
75756 
75757 /*! @name STAT0 - Status Register 0 */
75758 /*! @{ */
75759 
75760 #define OSC_RC_400M_STAT0_CLK1M_ERR_MASK         (0x1U)
75761 #define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT        (0U)
75762 /*! CLK1M_ERR - Error flag for clk_1m_locked
75763  *  0b0..No effect
75764  *  0b1..The count value has been reached within one divided ref_clk period
75765  */
75766 #define OSC_RC_400M_STAT0_CLK1M_ERR(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
75767 /*! @} */
75768 
75769 /*! @name STAT1 - Status Register 1 */
75770 /*! @{ */
75771 
75772 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK    (0xFFFF0000U)
75773 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
75774 /*! CURR_COUNT_VAL - Current count for the fast clock
75775  */
75776 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)      (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
75777 /*! @} */
75778 
75779 /*! @name STAT2 - Status Register 2 */
75780 /*! @{ */
75781 
75782 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
75783 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
75784 /*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator
75785  */
75786 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
75787 /*! @} */
75788 
75789 
75790 /*!
75791  * @}
75792  */ /* end of group OSC_RC_400M_Register_Masks */
75793 
75794 
75795 /* OSC_RC_400M - Peripheral instance base addresses */
75796 /** Peripheral OSC_RC_400M base address */
75797 #define OSC_RC_400M_BASE                         (0u)
75798 /** Peripheral OSC_RC_400M base pointer */
75799 #define OSC_RC_400M                              ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
75800 /** Array initializer of OSC_RC_400M peripheral base addresses */
75801 #define OSC_RC_400M_BASE_ADDRS                   { OSC_RC_400M_BASE }
75802 /** Array initializer of OSC_RC_400M peripheral base pointers */
75803 #define OSC_RC_400M_BASE_PTRS                    { OSC_RC_400M }
75804 
75805 /*!
75806  * @}
75807  */ /* end of group OSC_RC_400M_Peripheral_Access_Layer */
75808 
75809 
75810 /* ----------------------------------------------------------------------------
75811    -- OTFAD Peripheral Access Layer
75812    ---------------------------------------------------------------------------- */
75813 
75814 /*!
75815  * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
75816  * @{
75817  */
75818 
75819 /** OTFAD - Register Layout Typedef */
75820 typedef struct {
75821        uint8_t RESERVED_0[3072];
75822   __IO uint32_t CR;                                /**< Control Register, offset: 0xC00 */
75823   __IO uint32_t SR;                                /**< Status Register, offset: 0xC04 */
75824        uint8_t RESERVED_1[248];
75825   struct {                                         /* offset: 0xD00, array step: 0x40 */
75826     __IO uint32_t KEY[4];                            /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
75827     __IO uint32_t CTR[2];                            /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
75828     __IO uint32_t RGD_W0;                            /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
75829     __IO uint32_t RGD_W1;                            /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
75830          uint8_t RESERVED_0[32];
75831   } CTX[4];
75832 } OTFAD_Type;
75833 
75834 /* ----------------------------------------------------------------------------
75835    -- OTFAD Register Masks
75836    ---------------------------------------------------------------------------- */
75837 
75838 /*!
75839  * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
75840  * @{
75841  */
75842 
75843 /*! @name CR - Control Register */
75844 /*! @{ */
75845 
75846 #define OTFAD_CR_FERR_MASK                       (0x2U)
75847 #define OTFAD_CR_FERR_SHIFT                      (1U)
75848 /*! FERR - Force Error
75849  *  0b0..No effect on the SR[KBERE] indicator.
75850  *  0b1..SR[KBERR] is immediately set after a write with this data bit set.
75851  */
75852 #define OTFAD_CR_FERR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
75853 
75854 #define OTFAD_CR_FLDM_MASK                       (0x8U)
75855 #define OTFAD_CR_FLDM_SHIFT                      (3U)
75856 /*! FLDM - Force Logically Disabled Mode
75857  *  0b0..No effect on the operating mode.
75858  *  0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
75859  */
75860 #define OTFAD_CR_FLDM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
75861 
75862 #define OTFAD_CR_KBSE_MASK                       (0x10U)
75863 #define OTFAD_CR_KBSE_SHIFT                      (4U)
75864 /*! KBSE - Key Blob Scramble Enable
75865  *  0b0..Key blob KEK scrambling is disabled.
75866  *  0b1..Key blob KEK scrambling is enabled.
75867  */
75868 #define OTFAD_CR_KBSE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
75869 
75870 #define OTFAD_CR_KBPE_MASK                       (0x20U)
75871 #define OTFAD_CR_KBPE_SHIFT                      (5U)
75872 /*! KBPE - Key Blob Processing Enable
75873  *  0b0..Key blob processing is disabled.
75874  *  0b1..Key blob processing is enabled.
75875  */
75876 #define OTFAD_CR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
75877 
75878 #define OTFAD_CR_RRAE_MASK                       (0x80U)
75879 #define OTFAD_CR_RRAE_SHIFT                      (7U)
75880 /*! RRAE - Restricted Register Access Enable
75881  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
75882  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
75883  */
75884 #define OTFAD_CR_RRAE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
75885 
75886 #define OTFAD_CR_SKBP_MASK                       (0x40000000U)
75887 #define OTFAD_CR_SKBP_SHIFT                      (30U)
75888 /*! SKBP - Start key blob processing
75889  *  0b0..Key blob processing is not initiated.
75890  *  0b1..Properly-enabled key blob processing is initiated.
75891  */
75892 #define OTFAD_CR_SKBP(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
75893 
75894 #define OTFAD_CR_GE_MASK                         (0x80000000U)
75895 #define OTFAD_CR_GE_SHIFT                        (31U)
75896 /*! GE - Global OTFAD Enable
75897  *  0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
75898  *  0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
75899  */
75900 #define OTFAD_CR_GE(x)                           (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
75901 /*! @} */
75902 
75903 /*! @name SR - Status Register */
75904 /*! @{ */
75905 
75906 #define OTFAD_SR_KBERR_MASK                      (0x1U)
75907 #define OTFAD_SR_KBERR_SHIFT                     (0U)
75908 /*! KBERR - Key Blob Error
75909  *  0b0..No key blob error detected.
75910  *  0b1..One or more key blob errors has been detected.
75911  */
75912 #define OTFAD_SR_KBERR(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
75913 
75914 #define OTFAD_SR_MDPCP_MASK                      (0x2U)
75915 #define OTFAD_SR_MDPCP_SHIFT                     (1U)
75916 /*! MDPCP - MDPC Present
75917  */
75918 #define OTFAD_SR_MDPCP(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
75919 
75920 #define OTFAD_SR_MODE_MASK                       (0xCU)
75921 #define OTFAD_SR_MODE_SHIFT                      (2U)
75922 /*! MODE - Operating Mode
75923  *  0b00..Operating in Normal mode (NRM)
75924  *  0b01..Unused (reserved)
75925  *  0b10..Unused (reserved)
75926  *  0b11..Operating in Logically Disabled Mode (LDM)
75927  */
75928 #define OTFAD_SR_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
75929 
75930 #define OTFAD_SR_NCTX_MASK                       (0xF0U)
75931 #define OTFAD_SR_NCTX_SHIFT                      (4U)
75932 /*! NCTX - Number of Contexts
75933  */
75934 #define OTFAD_SR_NCTX(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
75935 
75936 #define OTFAD_SR_CTXER0_MASK                     (0x100U)
75937 #define OTFAD_SR_CTXER0_SHIFT                    (8U)
75938 /*! CTXER0 - Context Error
75939  *  0b0..No key blob error was detected for context "n".
75940  *  0b1..A key blob integrity error might have been detected in context "n".
75941  */
75942 #define OTFAD_SR_CTXER0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
75943 
75944 #define OTFAD_SR_CTXER1_MASK                     (0x200U)
75945 #define OTFAD_SR_CTXER1_SHIFT                    (9U)
75946 /*! CTXER1 - Context Error
75947  *  0b0..No key blob error was detected for context "n".
75948  *  0b1..A key blob integrity error might have been detected in context "n".
75949  */
75950 #define OTFAD_SR_CTXER1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
75951 
75952 #define OTFAD_SR_CTXER2_MASK                     (0x400U)
75953 #define OTFAD_SR_CTXER2_SHIFT                    (10U)
75954 /*! CTXER2 - Context Error
75955  *  0b0..No key blob error was detected for context "n".
75956  *  0b1..A key blob integrity error might have been detected in context "n".
75957  */
75958 #define OTFAD_SR_CTXER2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
75959 
75960 #define OTFAD_SR_CTXER3_MASK                     (0x800U)
75961 #define OTFAD_SR_CTXER3_SHIFT                    (11U)
75962 /*! CTXER3 - Context Error
75963  *  0b0..No key blob error was detected for context "n".
75964  *  0b1..A key blob integrity error might have been detected in context "n".
75965  */
75966 #define OTFAD_SR_CTXER3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
75967 
75968 #define OTFAD_SR_CTXIE0_MASK                     (0x10000U)
75969 #define OTFAD_SR_CTXIE0_SHIFT                    (16U)
75970 /*! CTXIE0 - Context Integrity Error
75971  *  0b0..No key blob integrity error was detected for context "n".
75972  *  0b1..A key blob integrity error was detected in context "n".
75973  */
75974 #define OTFAD_SR_CTXIE0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
75975 
75976 #define OTFAD_SR_CTXIE1_MASK                     (0x20000U)
75977 #define OTFAD_SR_CTXIE1_SHIFT                    (17U)
75978 /*! CTXIE1 - Context Integrity Error
75979  *  0b0..No key blob integrity error was detected for context "n".
75980  *  0b1..A key blob integrity error was detected in context "n".
75981  */
75982 #define OTFAD_SR_CTXIE1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
75983 
75984 #define OTFAD_SR_CTXIE2_MASK                     (0x40000U)
75985 #define OTFAD_SR_CTXIE2_SHIFT                    (18U)
75986 /*! CTXIE2 - Context Integrity Error
75987  *  0b0..No key blob integrity error was detected for context "n".
75988  *  0b1..A key blob integrity error was detected in context "n".
75989  */
75990 #define OTFAD_SR_CTXIE2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
75991 
75992 #define OTFAD_SR_CTXIE3_MASK                     (0x80000U)
75993 #define OTFAD_SR_CTXIE3_SHIFT                    (19U)
75994 /*! CTXIE3 - Context Integrity Error
75995  *  0b0..No key blob integrity error was detected for context "n".
75996  *  0b1..A key blob integrity error was detected in context "n".
75997  */
75998 #define OTFAD_SR_CTXIE3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
75999 
76000 #define OTFAD_SR_HRL_MASK                        (0xF000000U)
76001 #define OTFAD_SR_HRL_SHIFT                       (24U)
76002 /*! HRL - Hardware Revision Level
76003  */
76004 #define OTFAD_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
76005 
76006 #define OTFAD_SR_RRAM_MASK                       (0x10000000U)
76007 #define OTFAD_SR_RRAM_SHIFT                      (28U)
76008 /*! RRAM - Restricted Register Access Mode
76009  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
76010  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
76011  */
76012 #define OTFAD_SR_RRAM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
76013 
76014 #define OTFAD_SR_GEM_MASK                        (0x20000000U)
76015 #define OTFAD_SR_GEM_SHIFT                       (29U)
76016 /*! GEM - Global Enable Mode
76017  *  0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
76018  *  0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
76019  */
76020 #define OTFAD_SR_GEM(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
76021 
76022 #define OTFAD_SR_KBPE_MASK                       (0x40000000U)
76023 #define OTFAD_SR_KBPE_SHIFT                      (30U)
76024 /*! KBPE - Key Blob Processing Enable
76025  *  0b0..Key blob processing is not enabled.
76026  *  0b1..Key blob processing is enabled.
76027  */
76028 #define OTFAD_SR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
76029 
76030 #define OTFAD_SR_KBD_MASK                        (0x80000000U)
76031 #define OTFAD_SR_KBD_SHIFT                       (31U)
76032 /*! KBD - Key Blob Processing Done
76033  *  0b0..Key blob processing was not enabled, or is not complete.
76034  *  0b1..Key blob processing was enabled and is complete.
76035  */
76036 #define OTFAD_SR_KBD(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
76037 /*! @} */
76038 
76039 /*! @name KEY - AES Key Word */
76040 /*! @{ */
76041 
76042 #define OTFAD_KEY_KEY_MASK                       (0xFFFFFFFFU)
76043 #define OTFAD_KEY_KEY_SHIFT                      (0U)
76044 /*! KEY - AES Key
76045  */
76046 #define OTFAD_KEY_KEY(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
76047 /*! @} */
76048 
76049 /* The count of OTFAD_KEY */
76050 #define OTFAD_KEY_COUNT                          (4U)
76051 
76052 /* The count of OTFAD_KEY */
76053 #define OTFAD_KEY_COUNT2                         (4U)
76054 
76055 /*! @name CTR - AES Counter Word */
76056 /*! @{ */
76057 
76058 #define OTFAD_CTR_CTR_MASK                       (0xFFFFFFFFU)
76059 #define OTFAD_CTR_CTR_SHIFT                      (0U)
76060 /*! CTR - AES Counter
76061  */
76062 #define OTFAD_CTR_CTR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
76063 /*! @} */
76064 
76065 /* The count of OTFAD_CTR */
76066 #define OTFAD_CTR_COUNT                          (4U)
76067 
76068 /* The count of OTFAD_CTR */
76069 #define OTFAD_CTR_COUNT2                         (2U)
76070 
76071 /*! @name RGD_W0 - AES Region Descriptor Word0 */
76072 /*! @{ */
76073 
76074 #define OTFAD_RGD_W0_SRTADDR_MASK                (0xFFFFFC00U)
76075 #define OTFAD_RGD_W0_SRTADDR_SHIFT               (10U)
76076 /*! SRTADDR - Start Address
76077  */
76078 #define OTFAD_RGD_W0_SRTADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
76079 /*! @} */
76080 
76081 /* The count of OTFAD_RGD_W0 */
76082 #define OTFAD_RGD_W0_COUNT                       (4U)
76083 
76084 /*! @name RGD_W1 - AES Region Descriptor Word1 */
76085 /*! @{ */
76086 
76087 #define OTFAD_RGD_W1_VLD_MASK                    (0x1U)
76088 #define OTFAD_RGD_W1_VLD_SHIFT                   (0U)
76089 /*! VLD - Valid
76090  *  0b0..Context is invalid.
76091  *  0b1..Context is valid.
76092  */
76093 #define OTFAD_RGD_W1_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
76094 
76095 #define OTFAD_RGD_W1_ADE_MASK                    (0x2U)
76096 #define OTFAD_RGD_W1_ADE_SHIFT                   (1U)
76097 /*! ADE - AES Decryption Enable.
76098  *  0b0..Bypass the fetched data.
76099  *  0b1..Perform the CTR-AES128 mode decryption on the fetched data.
76100  */
76101 #define OTFAD_RGD_W1_ADE(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
76102 
76103 #define OTFAD_RGD_W1_RO_MASK                     (0x4U)
76104 #define OTFAD_RGD_W1_RO_SHIFT                    (2U)
76105 /*! RO - Read-Only
76106  *  0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
76107  *  0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
76108  */
76109 #define OTFAD_RGD_W1_RO(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
76110 
76111 #define OTFAD_RGD_W1_ENDADDR_MASK                (0xFFFFFC00U)
76112 #define OTFAD_RGD_W1_ENDADDR_SHIFT               (10U)
76113 /*! ENDADDR - End Address
76114  */
76115 #define OTFAD_RGD_W1_ENDADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
76116 /*! @} */
76117 
76118 /* The count of OTFAD_RGD_W1 */
76119 #define OTFAD_RGD_W1_COUNT                       (4U)
76120 
76121 
76122 /*!
76123  * @}
76124  */ /* end of group OTFAD_Register_Masks */
76125 
76126 
76127 /* OTFAD - Peripheral instance base addresses */
76128 /** Peripheral OTFAD1 base address */
76129 #define OTFAD1_BASE                              (0x400CC000u)
76130 /** Peripheral OTFAD1 base pointer */
76131 #define OTFAD1                                   ((OTFAD_Type *)OTFAD1_BASE)
76132 /** Peripheral OTFAD2 base address */
76133 #define OTFAD2_BASE                              (0x400D0000u)
76134 /** Peripheral OTFAD2 base pointer */
76135 #define OTFAD2                                   ((OTFAD_Type *)OTFAD2_BASE)
76136 /** Array initializer of OTFAD peripheral base addresses */
76137 #define OTFAD_BASE_ADDRS                         { 0u, OTFAD1_BASE, OTFAD2_BASE }
76138 /** Array initializer of OTFAD peripheral base pointers */
76139 #define OTFAD_BASE_PTRS                          { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
76140 
76141 /*!
76142  * @}
76143  */ /* end of group OTFAD_Peripheral_Access_Layer */
76144 
76145 
76146 /* ----------------------------------------------------------------------------
76147    -- PDM Peripheral Access Layer
76148    ---------------------------------------------------------------------------- */
76149 
76150 /*!
76151  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
76152  * @{
76153  */
76154 
76155 /** PDM - Register Layout Typedef */
76156 typedef struct {
76157   __IO uint32_t CTRL_1;                            /**< PDM Control register 1, offset: 0x0 */
76158   __IO uint32_t CTRL_2;                            /**< PDM Control register 2, offset: 0x4 */
76159   __IO uint32_t STAT;                              /**< PDM Status register, offset: 0x8 */
76160        uint8_t RESERVED_0[4];
76161   __IO uint32_t FIFO_CTRL;                         /**< PDM FIFO Control register, offset: 0x10 */
76162   __IO uint32_t FIFO_STAT;                         /**< PDM FIFO Status register, offset: 0x14 */
76163        uint8_t RESERVED_1[12];
76164   __I  uint32_t DATACH[8];                         /**< PDM Output Result Register, array offset: 0x24, array step: 0x4 */
76165        uint8_t RESERVED_2[32];
76166   __IO uint32_t DC_CTRL;                           /**< PDM DC Remover Control register, offset: 0x64 */
76167        uint8_t RESERVED_3[12];
76168   __IO uint32_t RANGE_CTRL;                        /**< PDM Range Control register, offset: 0x74 */
76169        uint8_t RESERVED_4[4];
76170   __IO uint32_t RANGE_STAT;                        /**< PDM Range Status register, offset: 0x7C */
76171        uint8_t RESERVED_5[16];
76172   __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control register, offset: 0x90 */
76173   __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control register, offset: 0x94 */
76174   __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status register, offset: 0x98 */
76175   __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
76176   __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
76177   __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
76178   __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
76179 } PDM_Type;
76180 
76181 /* ----------------------------------------------------------------------------
76182    -- PDM Register Masks
76183    ---------------------------------------------------------------------------- */
76184 
76185 /*!
76186  * @addtogroup PDM_Register_Masks PDM Register Masks
76187  * @{
76188  */
76189 
76190 /*! @name CTRL_1 - PDM Control register 1 */
76191 /*! @{ */
76192 
76193 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
76194 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
76195 /*! CH0EN - Channel 0 Enable
76196  */
76197 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
76198 
76199 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
76200 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
76201 /*! CH1EN - Channel 1 Enable
76202  */
76203 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
76204 
76205 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
76206 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
76207 /*! CH2EN - Channel 2 Enable
76208  */
76209 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
76210 
76211 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
76212 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
76213 /*! CH3EN - Channel 3 Enable
76214  */
76215 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
76216 
76217 #define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
76218 #define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
76219 /*! CH4EN - Channel 4 Enable
76220  */
76221 #define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
76222 
76223 #define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
76224 #define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
76225 /*! CH5EN - Channel 5 Enable
76226  */
76227 #define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
76228 
76229 #define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
76230 #define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
76231 /*! CH6EN - Channel 6 Enable
76232  */
76233 #define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
76234 
76235 #define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
76236 #define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
76237 /*! CH7EN - Channel 7 Enable
76238  */
76239 #define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
76240 
76241 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
76242 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
76243 /*! ERREN - Error Interruption Enable
76244  *  0b0..Error Interrupts disabled
76245  *  0b1..Error Interrupts enabled
76246  */
76247 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
76248 
76249 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
76250 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
76251 /*! DISEL - DMA Interrupt Selection
76252  *  0b00..DMA and interrupt requests disabled
76253  *  0b01..DMA requests enabled
76254  *  0b10..Interrupt requests enabled
76255  *  0b11..Reserved
76256  */
76257 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
76258 
76259 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
76260 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
76261 /*! DBGE - Module Enable in Debug
76262  *  0b0..Disabled after completing the current frame
76263  *  0b1..Enabled
76264  */
76265 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
76266 
76267 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
76268 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
76269 /*! SRES - Software-reset bit
76270  *  0b0..No action
76271  *  0b1..Software reset
76272  */
76273 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
76274 
76275 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
76276 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
76277 /*! DBG - Debug Mode
76278  *  0b0..Normal Mode
76279  *  0b1..Debug Mode
76280  */
76281 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
76282 
76283 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
76284 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
76285 /*! PDMIEN - PDM Enable
76286  *  0b0..PDM stopped
76287  *  0b1..PDM operation started
76288  */
76289 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
76290 
76291 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
76292 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
76293 /*! DOZEN - DOZE enable
76294  */
76295 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
76296 
76297 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
76298 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
76299 /*! MDIS - Module Disable
76300  *  0b0..Normal Mode
76301  *  0b1..Disable/Low Leakage Mode
76302  */
76303 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
76304 /*! @} */
76305 
76306 /*! @name CTRL_2 - PDM Control register 2 */
76307 /*! @{ */
76308 
76309 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
76310 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
76311 /*! CLKDIV - Clock Divider
76312  */
76313 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
76314 
76315 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
76316 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
76317 /*! CICOSR - CIC Decimation Rate
76318  */
76319 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
76320 
76321 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
76322 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
76323 /*! QSEL - Quality Mode
76324  *  0b001..High quality mode
76325  *  0b000..Medium quality mode
76326  *  0b111..Low quality mode
76327  *  0b110..Very low quality 0 mode
76328  *  0b101..Very low quality 1 mode
76329  *  0b100..Very low quality 2 mode
76330  */
76331 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
76332 /*! @} */
76333 
76334 /*! @name STAT - PDM Status register */
76335 /*! @{ */
76336 
76337 #define PDM_STAT_CH0F_MASK                       (0x1U)
76338 #define PDM_STAT_CH0F_SHIFT                      (0U)
76339 /*! CH0F - Channel 0 Output Data Flag
76340  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76341  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76342  */
76343 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
76344 
76345 #define PDM_STAT_CH1F_MASK                       (0x2U)
76346 #define PDM_STAT_CH1F_SHIFT                      (1U)
76347 /*! CH1F - Channel 1 Output Data Flag
76348  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76349  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76350  */
76351 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
76352 
76353 #define PDM_STAT_CH2F_MASK                       (0x4U)
76354 #define PDM_STAT_CH2F_SHIFT                      (2U)
76355 /*! CH2F - Channel 2 Output Data Flag
76356  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76357  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76358  */
76359 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
76360 
76361 #define PDM_STAT_CH3F_MASK                       (0x8U)
76362 #define PDM_STAT_CH3F_SHIFT                      (3U)
76363 /*! CH3F - Channel 3 Output Data Flag
76364  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76365  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76366  */
76367 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
76368 
76369 #define PDM_STAT_CH4F_MASK                       (0x10U)
76370 #define PDM_STAT_CH4F_SHIFT                      (4U)
76371 /*! CH4F - Channel 4 Output Data Flag
76372  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76373  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76374  */
76375 #define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
76376 
76377 #define PDM_STAT_CH5F_MASK                       (0x20U)
76378 #define PDM_STAT_CH5F_SHIFT                      (5U)
76379 /*! CH5F - Channel 5 Output Data Flag
76380  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76381  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76382  */
76383 #define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
76384 
76385 #define PDM_STAT_CH6F_MASK                       (0x40U)
76386 #define PDM_STAT_CH6F_SHIFT                      (6U)
76387 /*! CH6F - Channel 6 Output Data Flag
76388  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76389  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76390  */
76391 #define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
76392 
76393 #define PDM_STAT_CH7F_MASK                       (0x80U)
76394 #define PDM_STAT_CH7F_SHIFT                      (7U)
76395 /*! CH7F - Channel 7 Output Data Flag
76396  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76397  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76398  */
76399 #define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
76400 
76401 #define PDM_STAT_LOWFREQF_MASK                   (0x20000000U)
76402 #define PDM_STAT_LOWFREQF_SHIFT                  (29U)
76403 /*! LOWFREQF - Low Frequency Flag
76404  *  0b0..CLKDIV value is OK
76405  *  0b1..CLKDIV value is too low
76406  */
76407 #define PDM_STAT_LOWFREQF(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
76408 
76409 #define PDM_STAT_FIR_RDY_MASK                    (0x40000000U)
76410 #define PDM_STAT_FIR_RDY_SHIFT                   (30U)
76411 /*! FIR_RDY - Filter Data Ready
76412  *  0b0..Filter data is not reliable
76413  *  0b1..Filter data is reliable
76414  */
76415 #define PDM_STAT_FIR_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
76416 
76417 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
76418 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
76419 /*! BSY_FIL - Busy Flag
76420  *  0b1..PDM is running
76421  *  0b0..PDM is stopped
76422  */
76423 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
76424 /*! @} */
76425 
76426 /*! @name FIFO_CTRL - PDM FIFO Control register */
76427 /*! @{ */
76428 
76429 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
76430 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
76431 /*! FIFOWMK - FIFO Watermark Control
76432  */
76433 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
76434 /*! @} */
76435 
76436 /*! @name FIFO_STAT - PDM FIFO Status register */
76437 /*! @{ */
76438 
76439 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
76440 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
76441 /*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
76442  *  0b0..No exception by FIFO overflow
76443  *  0b1..Exception by FIFO overflow
76444  */
76445 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
76446 
76447 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
76448 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
76449 /*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
76450  *  0b0..No exception by FIFO overflow
76451  *  0b1..Exception by FIFO overflow
76452  */
76453 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
76454 
76455 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
76456 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
76457 /*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
76458  *  0b0..No exception by FIFO overflow
76459  *  0b1..Exception by FIFO overflow
76460  */
76461 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
76462 
76463 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
76464 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
76465 /*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
76466  *  0b0..No exception by FIFO overflow
76467  *  0b1..Exception by FIFO overflow
76468  */
76469 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
76470 
76471 #define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
76472 #define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
76473 /*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
76474  *  0b0..No exception by FIFO overflow
76475  *  0b1..Exception by FIFO overflow
76476  */
76477 #define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
76478 
76479 #define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
76480 #define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
76481 /*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
76482  *  0b0..No exception by FIFO overflow
76483  *  0b1..Exception by FIFO overflow
76484  */
76485 #define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
76486 
76487 #define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
76488 #define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
76489 /*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
76490  *  0b0..No exception by FIFO overflow
76491  *  0b1..Exception by FIFO overflow
76492  */
76493 #define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
76494 
76495 #define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
76496 #define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
76497 /*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
76498  *  0b0..No exception by FIFO overflow
76499  *  0b1..Exception by FIFO overflow
76500  */
76501 #define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
76502 
76503 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
76504 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
76505 /*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
76506  *  0b0..No exception by FIFO Underflow
76507  *  0b1..Exception by FIFO underflow
76508  */
76509 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
76510 
76511 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
76512 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
76513 /*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
76514  *  0b0..No exception by FIFO Underflow
76515  *  0b1..Exception by FIFO underflow
76516  */
76517 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
76518 
76519 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
76520 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
76521 /*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
76522  *  0b0..No exception by FIFO Underflow
76523  *  0b1..Exception by FIFO underflow
76524  */
76525 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
76526 
76527 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
76528 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
76529 /*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
76530  *  0b0..No exception by FIFO Underflow
76531  *  0b1..Exception by FIFO underflow
76532  */
76533 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
76534 
76535 #define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
76536 #define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
76537 /*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
76538  *  0b0..No exception by FIFO Underflow
76539  *  0b1..Exception by FIFO underflow
76540  */
76541 #define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
76542 
76543 #define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
76544 #define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
76545 /*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
76546  *  0b0..No exception by FIFO Underflow
76547  *  0b1..Exception by FIFO underflow
76548  */
76549 #define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
76550 
76551 #define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
76552 #define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
76553 /*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
76554  *  0b0..No exception by FIFO Underflow
76555  *  0b1..Exception by FIFO underflow
76556  */
76557 #define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
76558 
76559 #define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
76560 #define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
76561 /*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
76562  *  0b0..No exception by FIFO Underflow
76563  *  0b1..Exception by FIFO underflow
76564  */
76565 #define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
76566 /*! @} */
76567 
76568 /*! @name DATACH - PDM Output Result Register */
76569 /*! @{ */
76570 
76571 #define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
76572 #define PDM_DATACH_DATA_SHIFT                    (0U)
76573 /*! DATA - Channel n Data
76574  */
76575 #define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
76576 /*! @} */
76577 
76578 /* The count of PDM_DATACH */
76579 #define PDM_DATACH_COUNT                         (8U)
76580 
76581 /*! @name DC_CTRL - PDM DC Remover Control register */
76582 /*! @{ */
76583 
76584 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
76585 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
76586 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
76587  *  0b11..DC Remover is bypassed
76588  *  0b00..DC Remover cut-off at 21Hz
76589  *  0b01..DC Remover cut-off at 83Hz
76590  *  0b10..DC Remover cut-off at 152Hz
76591  */
76592 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
76593 
76594 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
76595 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
76596 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
76597  *  0b11..DC Remover is bypassed
76598  *  0b00..DC Remover cut-off at 21Hz
76599  *  0b01..DC Remover cut-off at 83Hz
76600  *  0b10..DC Remover cut-off at 152Hz
76601  */
76602 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
76603 
76604 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
76605 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
76606 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
76607  *  0b11..DC Remover is bypassed
76608  *  0b00..DC Remover cut-off at 21Hz
76609  *  0b01..DC Remover cut-off at 83Hz
76610  *  0b10..DC Remover cut-off at 152Hz
76611  */
76612 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
76613 
76614 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
76615 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
76616 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
76617  *  0b11..DC Remover is bypassed
76618  *  0b00..DC Remover cut-off at 21Hz
76619  *  0b01..DC Remover cut-off at 83Hz
76620  *  0b10..DC Remover cut-off at 152Hz
76621  */
76622 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
76623 
76624 #define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
76625 #define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
76626 /*! DCCONFIG4 - Channel 4 DC Remover Configuration
76627  *  0b11..DC Remover is bypassed
76628  *  0b00..DC Remover cut-off at 21Hz
76629  *  0b01..DC Remover cut-off at 83Hz
76630  *  0b10..DC Remover cut-off at 152Hz
76631  */
76632 #define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
76633 
76634 #define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
76635 #define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
76636 /*! DCCONFIG5 - Channel 5 DC Remover Configuration
76637  *  0b11..DC Remover is bypassed
76638  *  0b00..DC Remover cut-off at 21Hz
76639  *  0b01..DC Remover cut-off at 83Hz
76640  *  0b10..DC Remover cut-off at 152Hz
76641  */
76642 #define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
76643 
76644 #define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
76645 #define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
76646 /*! DCCONFIG6 - Channel 6 DC Remover Configuration
76647  *  0b11..DC Remover is bypassed
76648  *  0b00..DC Remover cut-off at 21Hz
76649  *  0b01..DC Remover cut-off at 83Hz
76650  *  0b10..DC Remover cut-off at 152Hz
76651  */
76652 #define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
76653 
76654 #define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
76655 #define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
76656 /*! DCCONFIG7 - Channel 7 DC Remover Configuration
76657  *  0b11..DC Remover is bypassed
76658  *  0b00..DC Remover cut-off at 21Hz
76659  *  0b01..DC Remover cut-off at 83Hz
76660  *  0b10..DC Remover cut-off at 152Hz
76661  */
76662 #define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
76663 /*! @} */
76664 
76665 /*! @name RANGE_CTRL - PDM Range Control register */
76666 /*! @{ */
76667 
76668 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
76669 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
76670 /*! RANGEADJ0 - Channel 0 Range Adjustment
76671  */
76672 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
76673 
76674 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
76675 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
76676 /*! RANGEADJ1 - Channel 1 Range Adjustment
76677  */
76678 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
76679 
76680 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
76681 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
76682 /*! RANGEADJ2 - Channel 2 Range Adjustment
76683  */
76684 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
76685 
76686 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
76687 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
76688 /*! RANGEADJ3 - Channel 3 Range Adjustment
76689  */
76690 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
76691 
76692 #define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
76693 #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
76694 /*! RANGEADJ4 - Channel 4 Range Adjustment
76695  */
76696 #define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
76697 
76698 #define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
76699 #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
76700 /*! RANGEADJ5 - Channel 5 Range Adjustment
76701  */
76702 #define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
76703 
76704 #define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
76705 #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
76706 /*! RANGEADJ6 - Channel 6 Range Adjustment
76707  */
76708 #define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
76709 
76710 #define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
76711 #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
76712 /*! RANGEADJ7 - Channel 7 Range Adjustment
76713  */
76714 #define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
76715 /*! @} */
76716 
76717 /*! @name RANGE_STAT - PDM Range Status register */
76718 /*! @{ */
76719 
76720 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
76721 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
76722 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
76723  *  0b0..No exception by range overflow
76724  *  0b1..Exception by range overflow
76725  */
76726 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
76727 
76728 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
76729 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
76730 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
76731  *  0b0..No exception by range overflow
76732  *  0b1..Exception by range overflow
76733  */
76734 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
76735 
76736 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
76737 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
76738 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
76739  *  0b0..No exception by range overflow
76740  *  0b1..Exception by range overflow
76741  */
76742 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
76743 
76744 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
76745 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
76746 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
76747  *  0b0..No exception by range overflow
76748  *  0b1..Exception by range overflow
76749  */
76750 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
76751 
76752 #define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
76753 #define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
76754 /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
76755  *  0b0..No exception by range overflow
76756  *  0b1..Exception by range overflow
76757  */
76758 #define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
76759 
76760 #define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
76761 #define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
76762 /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
76763  *  0b0..No exception by range overflow
76764  *  0b1..Exception by range overflow
76765  */
76766 #define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
76767 
76768 #define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
76769 #define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
76770 /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
76771  *  0b0..No exception by range overflow
76772  *  0b1..Exception by range overflow
76773  */
76774 #define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
76775 
76776 #define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
76777 #define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
76778 /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
76779  *  0b0..No exception by range overflow
76780  *  0b1..Exception by range overflow
76781  */
76782 #define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
76783 
76784 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
76785 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
76786 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
76787  *  0b0..No exception by range underflow
76788  *  0b1..Exception by range underflow
76789  */
76790 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
76791 
76792 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
76793 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
76794 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
76795  *  0b0..No exception by range underflow
76796  *  0b1..Exception by range underflow
76797  */
76798 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
76799 
76800 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
76801 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
76802 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
76803  *  0b0..No exception by range underflow
76804  *  0b1..Exception by range underflow
76805  */
76806 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
76807 
76808 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
76809 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
76810 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
76811  *  0b0..No exception by range underflow
76812  *  0b1..Exception by range underflow
76813  */
76814 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
76815 
76816 #define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
76817 #define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
76818 /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
76819  *  0b0..No exception by range underflow
76820  *  0b1..Exception by range underflow
76821  */
76822 #define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
76823 
76824 #define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
76825 #define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
76826 /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
76827  *  0b0..No exception by range underflow
76828  *  0b1..Exception by range underflow
76829  */
76830 #define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
76831 
76832 #define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
76833 #define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
76834 /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
76835  *  0b0..No exception by range underflow
76836  *  0b1..Exception by range underflow
76837  */
76838 #define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
76839 
76840 #define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
76841 #define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
76842 /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
76843  *  0b0..No exception by range underflow
76844  *  0b1..Exception by range underflow
76845  */
76846 #define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
76847 /*! @} */
76848 
76849 /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
76850 /*! @{ */
76851 
76852 #define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
76853 #define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
76854 /*! VADEN - Voice Activity Detector Enable
76855  *  0b0..The HWVAD is disabled
76856  *  0b1..The HWVAD is enabled
76857  */
76858 #define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
76859 
76860 #define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
76861 #define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
76862 /*! VADRST - Voice Activity Detector Reset
76863  */
76864 #define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
76865 
76866 #define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
76867 #define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
76868 /*! VADIE - Voice Activity Detector Interruption Enable
76869  *  0b0..HWVAD Interrupts disabled
76870  *  0b1..HWVAD Interrupts enabled
76871  */
76872 #define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
76873 
76874 #define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
76875 #define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
76876 /*! VADERIE - Voice Activity Detector Error Interruption Enable
76877  *  0b0..HWVAD Error Interrupts disabled
76878  *  0b1..HWVAD Error Interrupts enabled
76879  */
76880 #define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
76881 
76882 #define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
76883 #define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
76884 /*! VADST10 - Voice Activity Detector Internal Filters Initialization
76885  *  0b0..Normal operation.
76886  *  0b1..Filters are initialized.
76887  */
76888 #define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
76889 
76890 #define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
76891 #define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
76892 /*! VADINITT - Voice Activity Detector Initialization Time
76893  */
76894 #define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
76895 
76896 #define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
76897 #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
76898 /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate
76899  */
76900 #define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
76901 
76902 #define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
76903 #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
76904 /*! VADCHSEL - Voice Activity Detector Channel Selector
76905  */
76906 #define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
76907 /*! @} */
76908 
76909 /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
76910 /*! @{ */
76911 
76912 #define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
76913 #define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
76914 /*! VADHPF - Voice Activity Detector High-Pass Filter
76915  *  0b00..Filter bypassed.
76916  *  0b01..Cut-off frequency at 1750Hz.
76917  *  0b10..Cut-off frequency at 215Hz.
76918  *  0b11..Cut-off frequency at 102Hz.
76919  */
76920 #define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
76921 
76922 #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
76923 #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
76924 /*! VADINPGAIN - Voice Activity Detector Input Gain
76925  */
76926 #define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
76927 
76928 #define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
76929 #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
76930 /*! VADFRAMET - Voice Activity Detector Frame Time
76931  */
76932 #define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
76933 
76934 #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
76935 #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
76936 /*! VADFOUTDIS - Voice Activity Detector Force Output Disable
76937  *  0b0..Output is enabled.
76938  *  0b1..Output is disabled.
76939  */
76940 #define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
76941 
76942 #define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
76943 #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
76944 /*! VADPREFEN - Voice Activity Detector Pre Filter Enable
76945  *  0b0..Pre-filter is bypassed.
76946  *  0b1..Pre-filter is enabled.
76947  */
76948 #define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
76949 
76950 #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
76951 #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
76952 /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
76953  *  0b1..Frame energy calculus disabled.
76954  *  0b0..Frame energy calculus enabled.
76955  */
76956 #define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
76957 /*! @} */
76958 
76959 /*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
76960 /*! @{ */
76961 
76962 #define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
76963 #define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
76964 /*! VADIF - Voice Activity Detector Interrupt Flag
76965  *  0b0..Voice activity not detected
76966  *  0b1..Voice activity detected
76967  */
76968 #define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
76969 
76970 #define PDM_VAD0_STAT_VADEF_MASK                 (0x8000U)
76971 #define PDM_VAD0_STAT_VADEF_SHIFT                (15U)
76972 /*! VADEF - Voice Activity Detector Event Flag
76973  *  0b0..Voice activity not detected
76974  *  0b1..Voice activity detected
76975  */
76976 #define PDM_VAD0_STAT_VADEF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
76977 
76978 #define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
76979 #define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
76980 /*! VADINSATF - Voice Activity Detector Input Saturation Flag
76981  *  0b0..No exception
76982  *  0b1..Exception
76983  */
76984 #define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
76985 
76986 #define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
76987 #define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
76988 /*! VADINITF - Voice Activity Detector Initialization Flag
76989  *  0b0..HWVAD is not being initialized.
76990  *  0b1..HWVAD is being initialized.
76991  */
76992 #define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
76993 /*! @} */
76994 
76995 /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
76996 /*! @{ */
76997 
76998 #define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
76999 #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
77000 /*! VADSGAIN - Voice Activity Detector Signal Gain
77001  */
77002 #define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
77003 
77004 #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
77005 #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
77006 /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
77007  *  0b0..Maximum block is bypassed.
77008  *  0b1..Maximum block is enabled.
77009  */
77010 #define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
77011 
77012 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
77013 #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
77014 /*! VADSFILEN - Voice Activity Detector Signal Filter Enable
77015  *  0b0..Signal filter is disabled.
77016  *  0b1..Signal filter is enabled.
77017  */
77018 #define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
77019 /*! @} */
77020 
77021 /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
77022 /*! @{ */
77023 
77024 #define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
77025 #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
77026 /*! VADNGAIN - Voice Activity Detector Noise Gain
77027  */
77028 #define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
77029 
77030 #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
77031 #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
77032 /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment
77033  */
77034 #define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
77035 
77036 #define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
77037 #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
77038 /*! VADNOREN - Voice Activity Detector Noise OR Enable
77039  *  0b0..Noise input is not decimated.
77040  *  0b1..Noise input is decimated.
77041  */
77042 #define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
77043 
77044 #define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
77045 #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
77046 /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
77047  *  0b0..Noise input is not decimated.
77048  *  0b1..Noise input is decimated.
77049  */
77050 #define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
77051 
77052 #define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
77053 #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
77054 /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
77055  *  0b0..Minimum block is bypassed.
77056  *  0b1..Minimum block is enabled.
77057  */
77058 #define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
77059 
77060 #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
77061 #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
77062 /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
77063  *  0b0..Noise filter is always enabled.
77064  *  0b1..Noise filter is enabled/disabled based on voice activity information.
77065  */
77066 #define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
77067 /*! @} */
77068 
77069 /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
77070 /*! @{ */
77071 
77072 #define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
77073 #define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
77074 /*! VADNDATA - Voice Activity Detector Noise Data
77075  */
77076 #define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
77077 /*! @} */
77078 
77079 /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
77080 /*! @{ */
77081 
77082 #define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
77083 #define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
77084 /*! VADZCDEN - Zero-Crossing Detector Enable
77085  *  0b0..The ZCD is disabled
77086  *  0b1..The ZCD is enabled
77087  */
77088 #define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
77089 
77090 #define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
77091 #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
77092 /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
77093  *  0b0..The ZCD threshold is not estimated automatically
77094  *  0b1..The ZCD threshold is estimated automatically
77095  */
77096 #define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
77097 
77098 #define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
77099 #define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
77100 /*! VADZCDAND - Zero-Crossing Detector AND Behavior
77101  *  0b0..The ZCD result is OR'ed with the energy-based detection.
77102  *  0b1..The ZCD result is AND'ed with the energy-based detection.
77103  */
77104 #define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
77105 
77106 #define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
77107 #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
77108 /*! VADZCDADJ - Zero-Crossing Detector Adjustment
77109  */
77110 #define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
77111 
77112 #define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
77113 #define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
77114 /*! VADZCDTH - Zero-Crossing Detector Threshold
77115  */
77116 #define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
77117 /*! @} */
77118 
77119 
77120 /*!
77121  * @}
77122  */ /* end of group PDM_Register_Masks */
77123 
77124 
77125 /* PDM - Peripheral instance base addresses */
77126 /** Peripheral PDM base address */
77127 #define PDM_BASE                                 (0x40C20000u)
77128 /** Peripheral PDM base pointer */
77129 #define PDM                                      ((PDM_Type *)PDM_BASE)
77130 /** Array initializer of PDM peripheral base addresses */
77131 #define PDM_BASE_ADDRS                           { PDM_BASE }
77132 /** Array initializer of PDM peripheral base pointers */
77133 #define PDM_BASE_PTRS                            { PDM }
77134 
77135 /*!
77136  * @}
77137  */ /* end of group PDM_Peripheral_Access_Layer */
77138 
77139 
77140 /* ----------------------------------------------------------------------------
77141    -- PGMC_BPC Peripheral Access Layer
77142    ---------------------------------------------------------------------------- */
77143 
77144 /*!
77145  * @addtogroup PGMC_BPC_Peripheral_Access_Layer PGMC_BPC Peripheral Access Layer
77146  * @{
77147  */
77148 
77149 /** PGMC_BPC - Register Layout Typedef */
77150 typedef struct {
77151        uint8_t RESERVED_0[4];
77152   __IO uint32_t BPC_AUTHEN_CTRL;                   /**< BPC Authentication Control, offset: 0x4 */
77153        uint8_t RESERVED_1[8];
77154   __IO uint32_t BPC_MODE;                          /**< BPC Mode, offset: 0x10 */
77155   __IO uint32_t BPC_POWER_CTRL;                    /**< BPC power control, offset: 0x14 */
77156        uint8_t RESERVED_2[20];
77157   __IO uint32_t BPC_FLAG;                          /**< BPC flag, offset: 0x2C */
77158        uint8_t RESERVED_3[16];
77159   __IO uint32_t BPC_SSAR_SAVE_CTRL;                /**< BPC SSAR save control, offset: 0x40 */
77160   __IO uint32_t BPC_SSAR_RESTORE_CTRL;             /**< BPC SSAR restore control, offset: 0x44 */
77161 } PGMC_BPC_Type;
77162 
77163 /* ----------------------------------------------------------------------------
77164    -- PGMC_BPC Register Masks
77165    ---------------------------------------------------------------------------- */
77166 
77167 /*!
77168  * @addtogroup PGMC_BPC_Register_Masks PGMC_BPC Register Masks
77169  * @{
77170  */
77171 
77172 /*! @name BPC_AUTHEN_CTRL - BPC Authentication Control */
77173 /*! @{ */
77174 
77175 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK       (0x1U)
77176 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT      (0U)
77177 /*! USER - Allow user mode access
77178  *  0b0..Allow only privilege mode to access basic power control registers
77179  *  0b1..Allow both privilege and user mode to access basic power control registers
77180  */
77181 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK)
77182 
77183 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
77184 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
77185 /*! NONSECURE - Allow non-secure mode access
77186  *  0b0..Allow only secure mode to access basic power control registers
77187  *  0b1..Allow both secure and non-secure mode to access basic power control registers
77188  */
77189 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK)
77190 
77191 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
77192 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
77193 /*! LOCK_SETTING - Lock NONSECURE and USER
77194  */
77195 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
77196 
77197 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
77198 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
77199 /*! WHITE_LIST - Domain ID white list
77200  */
77201 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)
77202 
77203 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
77204 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
77205 /*! LOCK_LIST - White list lock
77206  */
77207 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK)
77208 
77209 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77210 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77211 /*! LOCK_CFG - Configuration lock
77212  */
77213 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK)
77214 /*! @} */
77215 
77216 /*! @name BPC_MODE - BPC Mode */
77217 /*! @{ */
77218 
77219 #define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK         (0x3U)
77220 #define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT        (0U)
77221 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77222  *  0b00..Not affected by any low power mode
77223  *  0b01..Controlled by CPU power mode of the domain
77224  *  0b10..Controlled by Setpoint
77225  *  0b11..Reserved
77226  */
77227 #define PGMC_BPC_BPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK)
77228 
77229 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
77230 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
77231 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
77232  *  0b00..Domain 0
77233  *  0b01..Domain 1
77234  *  0b10..Domain 2
77235  *  0b11..Domain 3
77236  */
77237 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK)
77238 /*! @} */
77239 
77240 /*! @name BPC_POWER_CTRL - BPC power control */
77241 /*! @{ */
77242 
77243 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
77244 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
77245 /*! PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode
77246  */
77247 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
77248 
77249 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
77250 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
77251 /*! PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode
77252  */
77253 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
77254 
77255 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
77256 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
77257 /*! PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode
77258  */
77259 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
77260 
77261 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
77262 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
77263 /*! ISO_ON_SOFT - Software isolation on trigger
77264  */
77265 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK)
77266 
77267 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
77268 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
77269 /*! PSW_OFF_SOFT - Software power off trigger
77270  */
77271 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK)
77272 
77273 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
77274 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
77275 /*! PSW_ON_SOFT - Software power on trigger
77276  */
77277 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK)
77278 
77279 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
77280 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
77281 /*! ISO_OFF_SOFT - Software isolation off trigger
77282  */
77283 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK)
77284 
77285 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U)
77286 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U)
77287 /*! PWR_OFF_AT_SP - Power off when system enters Setpoint number
77288  */
77289 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK)
77290 /*! @} */
77291 
77292 /*! @name BPC_FLAG - BPC flag */
77293 /*! @{ */
77294 
77295 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK          (0x1U)
77296 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT         (0U)
77297 /*! PDN_FLAG - set to 1 after power switch off, cleared by writing 1
77298  */
77299 #define PGMC_BPC_BPC_FLAG_PDN_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK)
77300 /*! @} */
77301 
77302 /*! @name BPC_SSAR_SAVE_CTRL - BPC SSAR save control */
77303 /*! @{ */
77304 
77305 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U)
77306 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U)
77307 /*! SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process
77308  */
77309 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK)
77310 
77311 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U)
77312 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U)
77313 /*! SAVE_AT_WAIT - Save data when domain enters WAIT mode
77314  */
77315 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK)
77316 
77317 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U)
77318 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U)
77319 /*! SAVE_AT_STOP - Save data when domain enters STOP mode
77320  */
77321 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK)
77322 
77323 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U)
77324 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U)
77325 /*! SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode
77326  */
77327 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK)
77328 
77329 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U)
77330 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U)
77331 /*! SAVE_AT_SP - Save data when system enters a Setpoint.
77332  */
77333 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK)
77334 /*! @} */
77335 
77336 /*! @name BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control */
77337 /*! @{ */
77338 
77339 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U)
77340 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U)
77341 /*! RESTORE_AT_RUN - Restore data at RUN mode
77342  */
77343 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK)
77344 
77345 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U)
77346 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U)
77347 /*! RESTORE_AT_SP - Restore data when system enters a Setpoint.
77348  */
77349 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK)
77350 /*! @} */
77351 
77352 
77353 /*!
77354  * @}
77355  */ /* end of group PGMC_BPC_Register_Masks */
77356 
77357 
77358 /* PGMC_BPC - Peripheral instance base addresses */
77359 /** Peripheral PGMC_BPC0 base address */
77360 #define PGMC_BPC0_BASE                           (0x40C88000u)
77361 /** Peripheral PGMC_BPC0 base pointer */
77362 #define PGMC_BPC0                                ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
77363 /** Peripheral PGMC_BPC1 base address */
77364 #define PGMC_BPC1_BASE                           (0x40C88200u)
77365 /** Peripheral PGMC_BPC1 base pointer */
77366 #define PGMC_BPC1                                ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
77367 /** Peripheral PGMC_BPC2 base address */
77368 #define PGMC_BPC2_BASE                           (0x40C88400u)
77369 /** Peripheral PGMC_BPC2 base pointer */
77370 #define PGMC_BPC2                                ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
77371 /** Peripheral PGMC_BPC3 base address */
77372 #define PGMC_BPC3_BASE                           (0x40C88600u)
77373 /** Peripheral PGMC_BPC3 base pointer */
77374 #define PGMC_BPC3                                ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
77375 /** Peripheral PGMC_BPC4 base address */
77376 #define PGMC_BPC4_BASE                           (0x40C88800u)
77377 /** Peripheral PGMC_BPC4 base pointer */
77378 #define PGMC_BPC4                                ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
77379 /** Peripheral PGMC_BPC5 base address */
77380 #define PGMC_BPC5_BASE                           (0x40C88A00u)
77381 /** Peripheral PGMC_BPC5 base pointer */
77382 #define PGMC_BPC5                                ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
77383 /** Peripheral PGMC_BPC6 base address */
77384 #define PGMC_BPC6_BASE                           (0x40C88C00u)
77385 /** Peripheral PGMC_BPC6 base pointer */
77386 #define PGMC_BPC6                                ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
77387 /** Peripheral PGMC_BPC7 base address */
77388 #define PGMC_BPC7_BASE                           (0x40C88E00u)
77389 /** Peripheral PGMC_BPC7 base pointer */
77390 #define PGMC_BPC7                                ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
77391 /** Array initializer of PGMC_BPC peripheral base addresses */
77392 #define PGMC_BPC_BASE_ADDRS                      { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
77393 /** Array initializer of PGMC_BPC peripheral base pointers */
77394 #define PGMC_BPC_BASE_PTRS                       { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
77395 
77396 /*!
77397  * @}
77398  */ /* end of group PGMC_BPC_Peripheral_Access_Layer */
77399 
77400 
77401 /* ----------------------------------------------------------------------------
77402    -- PGMC_CPC Peripheral Access Layer
77403    ---------------------------------------------------------------------------- */
77404 
77405 /*!
77406  * @addtogroup PGMC_CPC_Peripheral_Access_Layer PGMC_CPC Peripheral Access Layer
77407  * @{
77408  */
77409 
77410 /** PGMC_CPC - Register Layout Typedef */
77411 typedef struct {
77412        uint8_t RESERVED_0[4];
77413   __IO uint32_t CPC_AUTHEN_CTRL;                   /**< CPC Authentication Control, offset: 0x4 */
77414        uint8_t RESERVED_1[8];
77415   __IO uint32_t CPC_CORE_MODE;                     /**< CPC Core Mode, offset: 0x10 */
77416   __IO uint32_t CPC_CORE_POWER_CTRL;               /**< CPC core power control, offset: 0x14 */
77417        uint8_t RESERVED_2[20];
77418   __IO uint32_t CPC_FLAG;                          /**< CPC flag, offset: 0x2C */
77419        uint8_t RESERVED_3[16];
77420   __IO uint32_t CPC_CACHE_MODE;                    /**< CPC Cache Mode, offset: 0x40 */
77421   __IO uint32_t CPC_CACHE_CM_CTRL;                 /**< CPC cache CPU mode control, offset: 0x44 */
77422   __IO uint32_t CPC_CACHE_SP_CTRL_0;               /**< CPC cache Setpoint control 0, offset: 0x48 */
77423   __IO uint32_t CPC_CACHE_SP_CTRL_1;               /**< CPC cache Setpoint control 1, offset: 0x4C */
77424        uint8_t RESERVED_4[112];
77425   __IO uint32_t CPC_LMEM_MODE;                     /**< CPC local memory Mode, offset: 0xC0 */
77426   __IO uint32_t CPC_LMEM_CM_CTRL;                  /**< CPC local memory CPU mode control, offset: 0xC4 */
77427   __IO uint32_t CPC_LMEM_SP_CTRL_0;                /**< CPC local memory Setpoint control 0, offset: 0xC8 */
77428   __IO uint32_t CPC_LMEM_SP_CTRL_1;                /**< CPC local memory Setpoint control 1, offset: 0xCC */
77429 } PGMC_CPC_Type;
77430 
77431 /* ----------------------------------------------------------------------------
77432    -- PGMC_CPC Register Masks
77433    ---------------------------------------------------------------------------- */
77434 
77435 /*!
77436  * @addtogroup PGMC_CPC_Register_Masks PGMC_CPC Register Masks
77437  * @{
77438  */
77439 
77440 /*! @name CPC_AUTHEN_CTRL - CPC Authentication Control */
77441 /*! @{ */
77442 
77443 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK       (0x1U)
77444 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT      (0U)
77445 /*! USER - Allow user mode access
77446  */
77447 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)
77448 
77449 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
77450 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
77451 /*! NONSECURE - Allow non-secure mode access
77452  */
77453 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)
77454 
77455 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
77456 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
77457 /*! LOCK_SETTING - Lock NONSECURE and USER
77458  */
77459 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
77460 
77461 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
77462 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
77463 /*! WHITE_LIST - Domain ID white list
77464  */
77465 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)
77466 
77467 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
77468 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
77469 /*! LOCK_LIST - White list lock
77470  */
77471 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)
77472 
77473 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77474 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77475 /*! LOCK_CFG - Configuration lock
77476  */
77477 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)
77478 /*! @} */
77479 
77480 /*! @name CPC_CORE_MODE - CPC Core Mode */
77481 /*! @{ */
77482 
77483 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK    (0x3U)
77484 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT   (0U)
77485 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77486  *  0b00..Not affected by any low power mode
77487  *  0b01..Controlled by CPU power mode of the domain
77488  *  0b10..Reserved
77489  *  0b11..Reserved
77490  */
77491 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)
77492 /*! @} */
77493 
77494 /*! @name CPC_CORE_POWER_CTRL - CPC core power control */
77495 /*! @{ */
77496 
77497 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
77498 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
77499 /*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode
77500  */
77501 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
77502 
77503 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
77504 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
77505 /*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode
77506  */
77507 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
77508 
77509 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
77510 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
77511 /*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode
77512  */
77513 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
77514 
77515 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
77516 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
77517 /*! ISO_ON_SOFT - Software isolation on trigger
77518  */
77519 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)
77520 
77521 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
77522 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
77523 /*! PSW_OFF_SOFT - Software power off trigger
77524  */
77525 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)
77526 
77527 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
77528 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
77529 /*! PSW_ON_SOFT - Software power on trigger
77530  */
77531 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)
77532 
77533 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
77534 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
77535 /*! ISO_OFF_SOFT - Software isolation off trigger
77536  */
77537 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)
77538 /*! @} */
77539 
77540 /*! @name CPC_FLAG - CPC flag */
77541 /*! @{ */
77542 
77543 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK     (0x1U)
77544 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT    (0U)
77545 /*! CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1
77546  */
77547 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)
77548 /*! @} */
77549 
77550 /*! @name CPC_CACHE_MODE - CPC Cache Mode */
77551 /*! @{ */
77552 
77553 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK   (0x3U)
77554 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT  (0U)
77555 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77556  *  0b00..Not affected by any low power mode
77557  *  0b01..Controlled by CPU power mode of the domain
77558  *  0b10..Controlled by Setpoint
77559  *  0b11..Reserved
77560  */
77561 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)
77562 /*! @} */
77563 
77564 /*! @name CPC_CACHE_CM_CTRL - CPC cache CPU mode control */
77565 /*! @{ */
77566 
77567 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
77568 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
77569 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
77570  */
77571 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)
77572 
77573 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
77574 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
77575 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77576  */
77577 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)
77578 
77579 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
77580 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
77581 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77582  */
77583 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)
77584 
77585 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
77586 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
77587 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77588  */
77589 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)
77590 
77591 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
77592 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)
77593 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
77594  */
77595 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)
77596 /*! @} */
77597 
77598 /*! @name CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 */
77599 /*! @{ */
77600 
77601 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
77602 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
77603 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77604  */
77605 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)
77606 
77607 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
77608 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
77609 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77610  */
77611 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)
77612 
77613 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
77614 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
77615 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77616  */
77617 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)
77618 
77619 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
77620 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
77621 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77622  */
77623 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)
77624 
77625 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
77626 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
77627 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77628  */
77629 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)
77630 
77631 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
77632 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
77633 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77634  */
77635 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)
77636 
77637 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
77638 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
77639 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77640  */
77641 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)
77642 
77643 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
77644 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
77645 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77646  */
77647 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)
77648 /*! @} */
77649 
77650 /*! @name CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 */
77651 /*! @{ */
77652 
77653 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
77654 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
77655 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77656  */
77657 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)
77658 
77659 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
77660 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
77661 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77662  */
77663 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)
77664 
77665 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
77666 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
77667 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77668  */
77669 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)
77670 
77671 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
77672 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
77673 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77674  */
77675 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)
77676 
77677 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
77678 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
77679 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77680  */
77681 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)
77682 
77683 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
77684 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
77685 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77686  */
77687 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)
77688 
77689 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
77690 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
77691 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77692  */
77693 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)
77694 
77695 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
77696 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
77697 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77698  */
77699 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)
77700 /*! @} */
77701 
77702 /*! @name CPC_LMEM_MODE - CPC local memory Mode */
77703 /*! @{ */
77704 
77705 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK    (0x3U)
77706 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT   (0U)
77707 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77708  *  0b00..Not affected by any low power mode
77709  *  0b01..Controlled by CPU power mode of the domain
77710  *  0b10..Controlled by Setpoint
77711  *  0b11..Reserved
77712  */
77713 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)
77714 /*! @} */
77715 
77716 /*! @name CPC_LMEM_CM_CTRL - CPC local memory CPU mode control */
77717 /*! @{ */
77718 
77719 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
77720 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
77721 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
77722  */
77723 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)
77724 
77725 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
77726 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
77727 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77728  */
77729 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)
77730 
77731 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
77732 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
77733 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77734  */
77735 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)
77736 
77737 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
77738 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
77739 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77740  */
77741 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)
77742 
77743 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
77744 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)
77745 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
77746  */
77747 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)
77748 /*! @} */
77749 
77750 /*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 */
77751 /*! @{ */
77752 
77753 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
77754 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
77755 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77756  */
77757 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)
77758 
77759 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
77760 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
77761 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77762  */
77763 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)
77764 
77765 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
77766 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
77767 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77768  */
77769 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)
77770 
77771 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
77772 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
77773 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77774  */
77775 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)
77776 
77777 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
77778 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
77779 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77780  */
77781 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)
77782 
77783 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
77784 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
77785 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77786  */
77787 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)
77788 
77789 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
77790 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
77791 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77792  */
77793 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)
77794 
77795 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
77796 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
77797 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77798  */
77799 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)
77800 /*! @} */
77801 
77802 /*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 */
77803 /*! @{ */
77804 
77805 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
77806 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
77807 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77808  */
77809 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)
77810 
77811 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
77812 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
77813 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77814  */
77815 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)
77816 
77817 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
77818 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
77819 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77820  */
77821 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)
77822 
77823 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
77824 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
77825 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77826  */
77827 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)
77828 
77829 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
77830 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
77831 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77832  */
77833 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)
77834 
77835 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
77836 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
77837 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77838  */
77839 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)
77840 
77841 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
77842 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
77843 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77844  */
77845 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)
77846 
77847 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
77848 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
77849 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77850  */
77851 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)
77852 /*! @} */
77853 
77854 
77855 /*!
77856  * @}
77857  */ /* end of group PGMC_CPC_Register_Masks */
77858 
77859 
77860 /* PGMC_CPC - Peripheral instance base addresses */
77861 /** Peripheral PGMC_CPC0 base address */
77862 #define PGMC_CPC0_BASE                           (0x40C89000u)
77863 /** Peripheral PGMC_CPC0 base pointer */
77864 #define PGMC_CPC0                                ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
77865 /** Peripheral PGMC_CPC1 base address */
77866 #define PGMC_CPC1_BASE                           (0x40C89400u)
77867 /** Peripheral PGMC_CPC1 base pointer */
77868 #define PGMC_CPC1                                ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
77869 /** Array initializer of PGMC_CPC peripheral base addresses */
77870 #define PGMC_CPC_BASE_ADDRS                      { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
77871 /** Array initializer of PGMC_CPC peripheral base pointers */
77872 #define PGMC_CPC_BASE_PTRS                       { PGMC_CPC0, PGMC_CPC1 }
77873 
77874 /*!
77875  * @}
77876  */ /* end of group PGMC_CPC_Peripheral_Access_Layer */
77877 
77878 
77879 /* ----------------------------------------------------------------------------
77880    -- PGMC_MIF Peripheral Access Layer
77881    ---------------------------------------------------------------------------- */
77882 
77883 /*!
77884  * @addtogroup PGMC_MIF_Peripheral_Access_Layer PGMC_MIF Peripheral Access Layer
77885  * @{
77886  */
77887 
77888 /** PGMC_MIF - Register Layout Typedef */
77889 typedef struct {
77890        uint8_t RESERVED_0[4];
77891   __IO uint32_t MIF_AUTHEN_CTRL;                   /**< MIF Authentication Control, offset: 0x4 */
77892        uint8_t RESERVED_1[8];
77893   __IO uint32_t MIF_MLPL_SLEEP;                    /**< MIF MLPL control of SLEEP, offset: 0x10 */
77894        uint8_t RESERVED_2[12];
77895   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of IG, offset: 0x20 */
77896        uint8_t RESERVED_3[12];
77897   __IO uint32_t MIF_MLPL_LS;                       /**< MIF MLPL control of LS, offset: 0x30 */
77898        uint8_t RESERVED_4[12];
77899   __IO uint32_t MIF_MLPL_HS;                       /**< MIF MLPL control of HS, offset: 0x40 */
77900        uint8_t RESERVED_5[12];
77901   __IO uint32_t MIF_MLPL_STDBY;                    /**< MIF MLPL control of STDBY, offset: 0x50 */
77902        uint8_t RESERVED_6[12];
77903   __IO uint32_t MIF_MLPL_ARR_PDN;                  /**< MIF MLPL control of array power down, offset: 0x60 */
77904        uint8_t RESERVED_7[12];
77905   __IO uint32_t MIF_MLPL_PER_PDN;                  /**< MIF MLPL control of peripheral power down, offset: 0x70 */
77906        uint8_t RESERVED_8[12];
77907   __IO uint32_t MIF_MLPL_INITN;                    /**< MIF MLPL control of INITN, offset: 0x80 */
77908        uint8_t RESERVED_9[44];
77909   __IO uint32_t MIF_MLPL_ISO;                      /**< MIF MLPL control of isolation enable, offset: 0xB0 */
77910 } PGMC_MIF_Type;
77911 
77912 /* ----------------------------------------------------------------------------
77913    -- PGMC_MIF Register Masks
77914    ---------------------------------------------------------------------------- */
77915 
77916 /*!
77917  * @addtogroup PGMC_MIF_Register_Masks PGMC_MIF Register Masks
77918  * @{
77919  */
77920 
77921 /*! @name MIF_AUTHEN_CTRL - MIF Authentication Control */
77922 /*! @{ */
77923 
77924 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77925 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77926 /*! LOCK_CFG - Configuration lock
77927  */
77928 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK)
77929 /*! @} */
77930 
77931 /*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */
77932 /*! @{ */
77933 
77934 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK   (0xFFFFU)
77935 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT  (0U)
77936 /*! MLPL_CTRL - Signal behavior at each MLPL
77937  */
77938 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
77939 /*! @} */
77940 
77941 /*! @name MIF_MLPL_IG - MIF MLPL control of IG */
77942 /*! @{ */
77943 
77944 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK      (0xFFFFU)
77945 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT     (0U)
77946 /*! MLPL_CTRL - Signal behavior at each MLPL
77947  */
77948 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK)
77949 /*! @} */
77950 
77951 /*! @name MIF_MLPL_LS - MIF MLPL control of LS */
77952 /*! @{ */
77953 
77954 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK      (0xFFFFU)
77955 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT     (0U)
77956 /*! MLPL_CTRL - Signal behavior at each MLPL
77957  */
77958 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK)
77959 /*! @} */
77960 
77961 /*! @name MIF_MLPL_HS - MIF MLPL control of HS */
77962 /*! @{ */
77963 
77964 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK      (0xFFFFU)
77965 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT     (0U)
77966 /*! MLPL_CTRL - Signal behavior at each MLPL
77967  */
77968 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK)
77969 /*! @} */
77970 
77971 /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
77972 /*! @{ */
77973 
77974 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK   (0xFFFFU)
77975 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT  (0U)
77976 /*! MLPL_CTRL - Signal behavior at each MLPL
77977  */
77978 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
77979 /*! @} */
77980 
77981 /*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */
77982 /*! @{ */
77983 
77984 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU)
77985 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
77986 /*! MLPL_CTRL - Signal behavior at each MLPL
77987  */
77988 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
77989 /*! @} */
77990 
77991 /*! @name MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down */
77992 /*! @{ */
77993 
77994 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU)
77995 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U)
77996 /*! MLPL_CTRL - Signal behavior at each MLPL
77997  */
77998 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK)
77999 /*! @} */
78000 
78001 /*! @name MIF_MLPL_INITN - MIF MLPL control of INITN */
78002 /*! @{ */
78003 
78004 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK   (0xFFFFU)
78005 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT  (0U)
78006 /*! MLPL_CTRL - Signal behavior at each MLPL
78007  */
78008 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK)
78009 
78010 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U)
78011 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U)
78012 /*! BYPASS_VDD_OK - Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78013  */
78014 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK)
78015 /*! @} */
78016 
78017 /*! @name MIF_MLPL_ISO - MIF MLPL control of isolation enable */
78018 /*! @{ */
78019 
78020 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK     (0xFFFFU)
78021 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT    (0U)
78022 /*! MLPL_CTRL - Signal behavior at each MLPL
78023  */
78024 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK)
78025 /*! @} */
78026 
78027 
78028 /*!
78029  * @}
78030  */ /* end of group PGMC_MIF_Register_Masks */
78031 
78032 
78033 /* PGMC_MIF - Peripheral instance base addresses */
78034 /** Peripheral PGMC_CPC0_MIF0 base address */
78035 #define PGMC_CPC0_MIF0_BASE                      (0x40C89100u)
78036 /** Peripheral PGMC_CPC0_MIF0 base pointer */
78037 #define PGMC_CPC0_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
78038 /** Peripheral PGMC_CPC0_MIF1 base address */
78039 #define PGMC_CPC0_MIF1_BASE                      (0x40C89200u)
78040 /** Peripheral PGMC_CPC0_MIF1 base pointer */
78041 #define PGMC_CPC0_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
78042 /** Peripheral PGMC_CPC1_MIF0 base address */
78043 #define PGMC_CPC1_MIF0_BASE                      (0x40C89500u)
78044 /** Peripheral PGMC_CPC1_MIF0 base pointer */
78045 #define PGMC_CPC1_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
78046 /** Peripheral PGMC_CPC1_MIF1 base address */
78047 #define PGMC_CPC1_MIF1_BASE                      (0x40C89600u)
78048 /** Peripheral PGMC_CPC1_MIF1 base pointer */
78049 #define PGMC_CPC1_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
78050 /** Array initializer of PGMC_MIF peripheral base addresses */
78051 #define PGMC_MIF_BASE_ADDRS                      { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
78052 /** Array initializer of PGMC_MIF peripheral base pointers */
78053 #define PGMC_MIF_BASE_PTRS                       { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
78054 
78055 /*!
78056  * @}
78057  */ /* end of group PGMC_MIF_Peripheral_Access_Layer */
78058 
78059 
78060 /* ----------------------------------------------------------------------------
78061    -- PGMC_PPC Peripheral Access Layer
78062    ---------------------------------------------------------------------------- */
78063 
78064 /*!
78065  * @addtogroup PGMC_PPC_Peripheral_Access_Layer PGMC_PPC Peripheral Access Layer
78066  * @{
78067  */
78068 
78069 /** PGMC_PPC - Register Layout Typedef */
78070 typedef struct {
78071        uint8_t RESERVED_0[4];
78072   __IO uint32_t PPC_AUTHEN_CTRL;                   /**< PPC Authentication Control, offset: 0x4 */
78073        uint8_t RESERVED_1[8];
78074   __IO uint32_t PPC_MODE;                          /**< PPC Mode, offset: 0x10 */
78075   __IO uint32_t PPC_STBY_CM_CTRL;                  /**< PPC standby CPU mode control, offset: 0x14 */
78076   __IO uint32_t PPC_STBY_SP_CTRL;                  /**< PPC standby Setpoint control, offset: 0x18 */
78077 } PGMC_PPC_Type;
78078 
78079 /* ----------------------------------------------------------------------------
78080    -- PGMC_PPC Register Masks
78081    ---------------------------------------------------------------------------- */
78082 
78083 /*!
78084  * @addtogroup PGMC_PPC_Register_Masks PGMC_PPC Register Masks
78085  * @{
78086  */
78087 
78088 /*! @name PPC_AUTHEN_CTRL - PPC Authentication Control */
78089 /*! @{ */
78090 
78091 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK       (0x1U)
78092 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT      (0U)
78093 /*! USER - Allow user mode access
78094  */
78095 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK)
78096 
78097 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
78098 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
78099 /*! NONSECURE - Allow non-secure mode access
78100  */
78101 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK)
78102 
78103 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
78104 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
78105 /*! LOCK_SETTING - Lock NONSECURE and USER
78106  */
78107 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
78108 
78109 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
78110 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
78111 /*! WHITE_LIST - Domain ID white list
78112  */
78113 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)
78114 
78115 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
78116 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
78117 /*! LOCK_LIST - White list lock
78118  */
78119 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK)
78120 
78121 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
78122 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
78123 /*! LOCK_CFG - Configuration lock
78124  */
78125 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK)
78126 /*! @} */
78127 
78128 /*! @name PPC_MODE - PPC Mode */
78129 /*! @{ */
78130 
78131 #define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK         (0x3U)
78132 #define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT        (0U)
78133 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78134  *  0b00..Not affected by any low power mode
78135  *  0b01..Controlled by CPU power mode of the domain
78136  *  0b10..Controlled by Setpoint and system standby
78137  *  0b11..Reserved
78138  */
78139 #define PGMC_PPC_PPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK)
78140 
78141 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
78142 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
78143 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
78144  *  0b00..Domain 0
78145  *  0b01..Domain 1
78146  *  0b10..Domain 2
78147  *  0b11..Domain 3
78148  */
78149 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK)
78150 /*! @} */
78151 
78152 /*! @name PPC_STBY_CM_CTRL - PPC standby CPU mode control */
78153 /*! @{ */
78154 
78155 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U)
78156 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U)
78157 /*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78158  */
78159 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK)
78160 
78161 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U)
78162 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U)
78163 /*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78164  */
78165 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK)
78166 
78167 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U)
78168 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U)
78169 /*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78170  */
78171 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK)
78172 
78173 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U)
78174 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U)
78175 /*! STBY_ON_SOFT - Software PMIC standby on trigger
78176  */
78177 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK)
78178 
78179 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U)
78180 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U)
78181 /*! STBY_OFF_SOFT - Software PMIC standby off trigger
78182  */
78183 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK)
78184 /*! @} */
78185 
78186 /*! @name PPC_STBY_SP_CTRL - PPC standby Setpoint control */
78187 /*! @{ */
78188 
78189 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU)
78190 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U)
78191 /*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78192  */
78193 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK)
78194 
78195 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U)
78196 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U)
78197 /*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters Setpoint number and system is in
78198  *    standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
78199  */
78200 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK)
78201 /*! @} */
78202 
78203 
78204 /*!
78205  * @}
78206  */ /* end of group PGMC_PPC_Register_Masks */
78207 
78208 
78209 /* PGMC_PPC - Peripheral instance base addresses */
78210 /** Peripheral PGMC_PPC0 base address */
78211 #define PGMC_PPC0_BASE                           (0x40C8B000u)
78212 /** Peripheral PGMC_PPC0 base pointer */
78213 #define PGMC_PPC0                                ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
78214 /** Array initializer of PGMC_PPC peripheral base addresses */
78215 #define PGMC_PPC_BASE_ADDRS                      { PGMC_PPC0_BASE }
78216 /** Array initializer of PGMC_PPC peripheral base pointers */
78217 #define PGMC_PPC_BASE_PTRS                       { PGMC_PPC0 }
78218 
78219 /*!
78220  * @}
78221  */ /* end of group PGMC_PPC_Peripheral_Access_Layer */
78222 
78223 
78224 /* ----------------------------------------------------------------------------
78225    -- PHY_LDO Peripheral Access Layer
78226    ---------------------------------------------------------------------------- */
78227 
78228 /*!
78229  * @addtogroup PHY_LDO_Peripheral_Access_Layer PHY_LDO Peripheral Access Layer
78230  * @{
78231  */
78232 
78233 /** PHY_LDO - Register Layout Typedef */
78234 typedef struct {
78235   struct {                                         /* offset: 0x0 */
78236     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
78237     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
78238     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
78239     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
78240   } CTRL0;
78241        uint8_t RESERVED_0[64];
78242   struct {                                         /* offset: 0x50 */
78243     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
78244     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
78245     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
78246     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
78247   } STAT0;
78248 } PHY_LDO_Type;
78249 
78250 /* ----------------------------------------------------------------------------
78251    -- PHY_LDO Register Masks
78252    ---------------------------------------------------------------------------- */
78253 
78254 /*!
78255  * @addtogroup PHY_LDO_Register_Masks PHY_LDO Register Masks
78256  * @{
78257  */
78258 
78259 /*! @name CTRL0 - Analog Control Register CTRL0 */
78260 /*! @{ */
78261 
78262 #define PHY_LDO_CTRL0_LINREG_EN_MASK             (0x1U)
78263 #define PHY_LDO_CTRL0_LINREG_EN_SHIFT            (0U)
78264 /*! LINREG_EN - LinrReg master enable
78265  */
78266 #define PHY_LDO_CTRL0_LINREG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
78267 
78268 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK  (0x2U)
78269 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
78270 /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
78271  *  0b0..Internal pull-down enabled
78272  *  0b1..Internal pull-down disabled
78273  */
78274 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x)    (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
78275 
78276 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK      (0x4U)
78277 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT     (2U)
78278 /*! LINREG_ILIMIT_EN - LinReg current-limit enable
78279  */
78280 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
78281 
78282 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK     (0x1F0U)
78283 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT    (4U)
78284 /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
78285  *  0b00000..Set output voltage to x.xV
78286  *  0b10000..Sets output voltage to 1.0V
78287  *  0b11111..Set output voltage to x.xV
78288  */
78289 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
78290 
78291 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK      (0x8000U)
78292 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT     (15U)
78293 /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load
78294  */
78295 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
78296 /*! @} */
78297 
78298 /*! @name STAT0 - Analog Status Register STAT0 */
78299 /*! @{ */
78300 
78301 #define PHY_LDO_STAT0_LINREG_STAT_MASK           (0xFU)
78302 #define PHY_LDO_STAT0_LINREG_STAT_SHIFT          (0U)
78303 /*! LINREG_STAT - LinReg Status Bits
78304  */
78305 #define PHY_LDO_STAT0_LINREG_STAT(x)             (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK)
78306 /*! @} */
78307 
78308 
78309 /*!
78310  * @}
78311  */ /* end of group PHY_LDO_Register_Masks */
78312 
78313 
78314 /* PHY_LDO - Peripheral instance base addresses */
78315 /** Peripheral PHY_LDO base address */
78316 #define PHY_LDO_BASE                             (0u)
78317 /** Peripheral PHY_LDO base pointer */
78318 #define PHY_LDO                                  ((PHY_LDO_Type *)PHY_LDO_BASE)
78319 /** Array initializer of PHY_LDO peripheral base addresses */
78320 #define PHY_LDO_BASE_ADDRS                       { PHY_LDO_BASE }
78321 /** Array initializer of PHY_LDO peripheral base pointers */
78322 #define PHY_LDO_BASE_PTRS                        { PHY_LDO }
78323 
78324 /*!
78325  * @}
78326  */ /* end of group PHY_LDO_Peripheral_Access_Layer */
78327 
78328 
78329 /* ----------------------------------------------------------------------------
78330    -- PIT Peripheral Access Layer
78331    ---------------------------------------------------------------------------- */
78332 
78333 /*!
78334  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
78335  * @{
78336  */
78337 
78338 /** PIT - Register Layout Typedef */
78339 typedef struct {
78340   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
78341        uint8_t RESERVED_0[220];
78342   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
78343   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
78344        uint8_t RESERVED_1[24];
78345   struct {                                         /* offset: 0x100, array step: 0x10 */
78346     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
78347     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
78348     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
78349     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
78350   } CHANNEL[4];
78351 } PIT_Type;
78352 
78353 /* ----------------------------------------------------------------------------
78354    -- PIT Register Masks
78355    ---------------------------------------------------------------------------- */
78356 
78357 /*!
78358  * @addtogroup PIT_Register_Masks PIT Register Masks
78359  * @{
78360  */
78361 
78362 /*! @name MCR - PIT Module Control Register */
78363 /*! @{ */
78364 
78365 #define PIT_MCR_FRZ_MASK                         (0x1U)
78366 #define PIT_MCR_FRZ_SHIFT                        (0U)
78367 /*! FRZ - Freeze
78368  *  0b0..Timers continue to run in Debug mode.
78369  *  0b1..Timers are stopped in Debug mode.
78370  */
78371 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
78372 
78373 #define PIT_MCR_MDIS_MASK                        (0x2U)
78374 #define PIT_MCR_MDIS_SHIFT                       (1U)
78375 /*! MDIS - Module Disable for PIT
78376  *  0b0..Clock for standard PIT timers is enabled.
78377  *  0b1..Clock for standard PIT timers is disabled.
78378  */
78379 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
78380 /*! @} */
78381 
78382 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
78383 /*! @{ */
78384 
78385 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
78386 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
78387 /*! LTH - Life Timer value
78388  */
78389 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
78390 /*! @} */
78391 
78392 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
78393 /*! @{ */
78394 
78395 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
78396 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
78397 /*! LTL - Life Timer value
78398  */
78399 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
78400 /*! @} */
78401 
78402 /*! @name LDVAL - Timer Load Value Register */
78403 /*! @{ */
78404 
78405 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
78406 #define PIT_LDVAL_TSV_SHIFT                      (0U)
78407 /*! TSV - Timer Start Value
78408  */
78409 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
78410 /*! @} */
78411 
78412 /* The count of PIT_LDVAL */
78413 #define PIT_LDVAL_COUNT                          (4U)
78414 
78415 /*! @name CVAL - Current Timer Value Register */
78416 /*! @{ */
78417 
78418 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
78419 #define PIT_CVAL_TVL_SHIFT                       (0U)
78420 /*! TVL - Current Timer Value
78421  */
78422 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
78423 /*! @} */
78424 
78425 /* The count of PIT_CVAL */
78426 #define PIT_CVAL_COUNT                           (4U)
78427 
78428 /*! @name TCTRL - Timer Control Register */
78429 /*! @{ */
78430 
78431 #define PIT_TCTRL_TEN_MASK                       (0x1U)
78432 #define PIT_TCTRL_TEN_SHIFT                      (0U)
78433 /*! TEN - Timer Enable
78434  *  0b0..Timer n is disabled.
78435  *  0b1..Timer n is enabled.
78436  */
78437 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
78438 
78439 #define PIT_TCTRL_TIE_MASK                       (0x2U)
78440 #define PIT_TCTRL_TIE_SHIFT                      (1U)
78441 /*! TIE - Timer Interrupt Enable
78442  *  0b0..Interrupt requests from Timer n are disabled.
78443  *  0b1..Interrupt is requested whenever TIF is set.
78444  */
78445 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
78446 
78447 #define PIT_TCTRL_CHN_MASK                       (0x4U)
78448 #define PIT_TCTRL_CHN_SHIFT                      (2U)
78449 /*! CHN - Chain Mode
78450  *  0b0..Timer is not chained.
78451  *  0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.
78452  */
78453 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
78454 /*! @} */
78455 
78456 /* The count of PIT_TCTRL */
78457 #define PIT_TCTRL_COUNT                          (4U)
78458 
78459 /*! @name TFLG - Timer Flag Register */
78460 /*! @{ */
78461 
78462 #define PIT_TFLG_TIF_MASK                        (0x1U)
78463 #define PIT_TFLG_TIF_SHIFT                       (0U)
78464 /*! TIF - Timer Interrupt Flag
78465  *  0b0..Timeout has not yet occurred.
78466  *  0b1..Timeout has occurred.
78467  */
78468 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
78469 /*! @} */
78470 
78471 /* The count of PIT_TFLG */
78472 #define PIT_TFLG_COUNT                           (4U)
78473 
78474 
78475 /*!
78476  * @}
78477  */ /* end of group PIT_Register_Masks */
78478 
78479 
78480 /* PIT - Peripheral instance base addresses */
78481 /** Peripheral PIT1 base address */
78482 #define PIT1_BASE                                (0x400D8000u)
78483 /** Peripheral PIT1 base pointer */
78484 #define PIT1                                     ((PIT_Type *)PIT1_BASE)
78485 /** Peripheral PIT2 base address */
78486 #define PIT2_BASE                                (0x40CB0000u)
78487 /** Peripheral PIT2 base pointer */
78488 #define PIT2                                     ((PIT_Type *)PIT2_BASE)
78489 /** Array initializer of PIT peripheral base addresses */
78490 #define PIT_BASE_ADDRS                           { 0u, PIT1_BASE, PIT2_BASE }
78491 /** Array initializer of PIT peripheral base pointers */
78492 #define PIT_BASE_PTRS                            { (PIT_Type *)0u, PIT1, PIT2 }
78493 /** Interrupt vectors for the PIT peripheral type */
78494 #define PIT_IRQS                                 { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
78495 
78496 /*!
78497  * @}
78498  */ /* end of group PIT_Peripheral_Access_Layer */
78499 
78500 
78501 /* ----------------------------------------------------------------------------
78502    -- PUF Peripheral Access Layer
78503    ---------------------------------------------------------------------------- */
78504 
78505 /*!
78506  * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
78507  * @{
78508  */
78509 
78510 /** PUF - Register Layout Typedef */
78511 typedef struct {
78512   __IO uint32_t CTRL;                              /**< PUF Control Register, offset: 0x0 */
78513   __IO uint32_t KEYINDEX;                          /**< PUF Key Index Register, offset: 0x4 */
78514   __IO uint32_t KEYSIZE;                           /**< PUF Key Size Register, offset: 0x8 */
78515        uint8_t RESERVED_0[20];
78516   __I  uint32_t STAT;                              /**< PUF Status Register, offset: 0x20 */
78517        uint8_t RESERVED_1[4];
78518   __I  uint32_t ALLOW;                             /**< PUF Allow Register, offset: 0x28 */
78519        uint8_t RESERVED_2[20];
78520   __O  uint32_t KEYINPUT;                          /**< PUF Key Input Register, offset: 0x40 */
78521   __O  uint32_t CODEINPUT;                         /**< PUF Code Input Register, offset: 0x44 */
78522   __I  uint32_t CODEOUTPUT;                        /**< PUF Code Output Register, offset: 0x48 */
78523        uint8_t RESERVED_3[20];
78524   __I  uint32_t KEYOUTINDEX;                       /**< PUF Key Output Index Register, offset: 0x60 */
78525   __I  uint32_t KEYOUTPUT;                         /**< PUF Key Output Register, offset: 0x64 */
78526        uint8_t RESERVED_4[116];
78527   __IO uint32_t IFSTAT;                            /**< PUF Interface Status Register, offset: 0xDC */
78528        uint8_t RESERVED_5[28];
78529   __I  uint32_t VERSION;                           /**< PUF Version Register, offset: 0xFC */
78530   __IO uint32_t INTEN;                             /**< PUF Interrupt Enable, offset: 0x100 */
78531   __IO uint32_t INTSTAT;                           /**< PUF Interrupt Status, offset: 0x104 */
78532   __IO uint32_t PWRCTRL;                           /**< PUF Power Control Of RAM, offset: 0x108 */
78533   __IO uint32_t CFG;                               /**< PUF Configuration Register, offset: 0x10C */
78534        uint8_t RESERVED_6[240];
78535   __IO uint32_t KEYLOCK;                           /**< PUF Key Manager Lock, offset: 0x200 */
78536   __IO uint32_t KEYENABLE;                         /**< PUF Key Manager Enable, offset: 0x204 */
78537   __IO uint32_t KEYRESET;                          /**< PUF Key Manager Reset, offset: 0x208 */
78538   __IO uint32_t IDXBLK;                            /**< PUF Index Block Key Output, offset: 0x20C */
78539   __IO uint32_t IDXBLK_DP;                         /**< PUF Index Block Key Output, offset: 0x210 */
78540   __IO uint32_t KEYMASK[2];                        /**< PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */
78541        uint8_t RESERVED_7[56];
78542   __I  uint32_t IDXBLK_STATUS;                     /**< PUF Index Block Setting Status Register, offset: 0x254 */
78543   __I  uint32_t IDXBLK_SHIFT;                      /**< PUF Key Manager Shift Status, offset: 0x258 */
78544 } PUF_Type;
78545 
78546 /* ----------------------------------------------------------------------------
78547    -- PUF Register Masks
78548    ---------------------------------------------------------------------------- */
78549 
78550 /*!
78551  * @addtogroup PUF_Register_Masks PUF Register Masks
78552  * @{
78553  */
78554 
78555 /*! @name CTRL - PUF Control Register */
78556 /*! @{ */
78557 
78558 #define PUF_CTRL_ZEROIZE_MASK                    (0x1U)
78559 #define PUF_CTRL_ZEROIZE_SHIFT                   (0U)
78560 /*! ZEROIZE - Begin Zeroize operation for PUF and go to Error state
78561  *  0b0..No Zeroize operation in progress
78562  *  0b1..Zeroize operation in progress
78563  */
78564 #define PUF_CTRL_ZEROIZE(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
78565 
78566 #define PUF_CTRL_ENROLL_MASK                     (0x2U)
78567 #define PUF_CTRL_ENROLL_SHIFT                    (1U)
78568 /*! ENROLL - Begin Enroll operation
78569  *  0b0..No Enroll operation in progress
78570  *  0b1..Enroll operation in progress
78571  */
78572 #define PUF_CTRL_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
78573 
78574 #define PUF_CTRL_START_MASK                      (0x4U)
78575 #define PUF_CTRL_START_SHIFT                     (2U)
78576 /*! START - Begin Start operation
78577  *  0b0..No Start operation in progress
78578  *  0b1..Start operation in progress
78579  */
78580 #define PUF_CTRL_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
78581 
78582 #define PUF_CTRL_GENERATEKEY_MASK                (0x8U)
78583 #define PUF_CTRL_GENERATEKEY_SHIFT               (3U)
78584 /*! GENERATEKEY - Begin Set Intrinsic Key operation
78585  *  0b0..No Set Intrinsic Key operation in progress
78586  *  0b1..Set Intrinsic Key operation in progress
78587  */
78588 #define PUF_CTRL_GENERATEKEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
78589 
78590 #define PUF_CTRL_SETKEY_MASK                     (0x10U)
78591 #define PUF_CTRL_SETKEY_SHIFT                    (4U)
78592 /*! SETKEY - Begin Set User Key operation
78593  *  0b0..No Set Key operation in progress
78594  *  0b1..Set Key operation in progress
78595  */
78596 #define PUF_CTRL_SETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
78597 
78598 #define PUF_CTRL_GETKEY_MASK                     (0x40U)
78599 #define PUF_CTRL_GETKEY_SHIFT                    (6U)
78600 /*! GETKEY - Begin Get Key operation
78601  *  0b0..No Get Key operation in progress
78602  *  0b1..Get Key operation in progress
78603  */
78604 #define PUF_CTRL_GETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
78605 /*! @} */
78606 
78607 /*! @name KEYINDEX - PUF Key Index Register */
78608 /*! @{ */
78609 
78610 #define PUF_KEYINDEX_KEYIDX_MASK                 (0xFU)
78611 #define PUF_KEYINDEX_KEYIDX_SHIFT                (0U)
78612 /*! KEYIDX - PUF Key Index
78613  *  0b0000..USE INDEX0
78614  *  0b0001..USE INDEX1
78615  *  0b0010..USE INDEX2
78616  *  0b0011..USE INDEX3
78617  *  0b0100..USE INDEX4
78618  *  0b0101..USE INDEX5
78619  *  0b0110..USE INDEX6
78620  *  0b0111..USE INDEX7
78621  *  0b1000..USE INDEX8
78622  *  0b1001..USE INDEX9
78623  *  0b1010..USE INDEX10
78624  *  0b1011..USE INDEX11
78625  *  0b1100..USE INDEX12
78626  *  0b1101..USE INDEX13
78627  *  0b1110..USE INDEX14
78628  *  0b1111..USE INDEX15
78629  */
78630 #define PUF_KEYINDEX_KEYIDX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
78631 /*! @} */
78632 
78633 /*! @name KEYSIZE - PUF Key Size Register */
78634 /*! @{ */
78635 
78636 #define PUF_KEYSIZE_KEYSIZE_MASK                 (0x3FU)
78637 #define PUF_KEYSIZE_KEYSIZE_SHIFT                (0U)
78638 /*! KEYSIZE - PUF Key Size
78639  *  0b000001..Key Size is 8 Bytes and KC Size is 52 Bytes
78640  *  0b000010..Key Size is 16 Bytes and KC Size is 52 Bytes
78641  *  0b000011..Key Size is 24 Bytes and KC Size is 52 Bytes
78642  *  0b000100..Key Size is 32 Bytes and KC Size is 52 Bytes
78643  *  0b000101..Key Size is 40 Bytes and KC Size is 84 Bytes
78644  *  0b000110..Key Size is 48 Bytes and KC Size is 84 Bytes
78645  *  0b000111..Key Size is 56 Bytes and KC Size is 84 Bytes
78646  *  0b001000..Key Size is 64 Bytes and KC Size is 84 Bytes
78647  *  0b001001..Key Size is 72 Bytes and KC Size is 116 Bytes
78648  *  0b001010..Key Size is 80 Bytes and KC Size is 116 Bytes
78649  *  0b001011..Key Size is 88 Bytes and KC Size is 116 Bytes
78650  *  0b001100..Key Size is 96 Bytes and KC Size is 116 Bytes
78651  *  0b001101..Key Size is 104 Bytes and KC Size is 148 Bytes
78652  *  0b001110..Key Size is 112 Bytes and KC Size is 148 Bytes
78653  *  0b001111..Key Size is 120 Bytes and KC Size is 148 Bytes
78654  *  0b010000..Key Size is 128 Bytes and KC Size is 148 Bytes
78655  *  0b010001..Key Size is 136 Bytes and KC Size is 180 Bytes
78656  *  0b010010..Key Size is 144 Bytes and KC Size is 180 Bytes
78657  *  0b010011..Key Size is 152 Bytes and KC Size is 180 Bytes
78658  *  0b010100..Key Size is 160 Bytes and KC Size is 180 Bytes
78659  *  0b010101..Key Size is 168 Bytes and KC Size is 212 Bytes
78660  *  0b010110..Key Size is 176 Bytes and KC Size is 212 Bytes
78661  *  0b010111..Key Size is 184 Bytes and KC Size is 212 Bytes
78662  *  0b011000..Key Size is 192 Bytes and KC Size is 212 Bytes
78663  *  0b011001..Key Size is 200 Bytes and KC Size is 244 Bytes
78664  *  0b011010..Key Size is 208 Bytes and KC Size is 244 Bytes
78665  *  0b011011..Key Size is 216 Bytes and KC Size is 244 Bytes
78666  *  0b011100..Key Size is 224 Bytes and KC Size is 244 Bytes
78667  *  0b011101..Key Size is 232 Bytes and KC Size is 276 Bytes
78668  *  0b011110..Key Size is 240 Bytes and KC Size is 276 Bytes
78669  *  0b011111..Key Size is 248 Bytes and KC Size is 276 Bytes
78670  *  0b100000..Key Size is 256 Bytes and KC Size is 276 Bytes
78671  *  0b100001..Key Size is 264 Bytes and KC Size is 308 Bytes
78672  *  0b100010..Key Size is 272 Bytes and KC Size is 308 Bytes
78673  *  0b100011..Key Size is 280 Bytes and KC Size is 308 Bytes
78674  *  0b100100..Key Size is 288 Bytes and KC Size is 308 Bytes
78675  *  0b100101..Key Size is 296 Bytes and KC Size is 340 Bytes
78676  *  0b100110..Key Size is 304 Bytes and KC Size is 340 Bytes
78677  *  0b100111..Key Size is 312 Bytes and KC Size is 340 Bytes
78678  *  0b101000..Key Size is 320 Bytes and KC Size is 340 Bytes
78679  *  0b101001..Key Size is 328 Bytes and KC Size is 372 Bytes
78680  *  0b101010..Key Size is 336 Bytes and KC Size is 372 Bytes
78681  *  0b101011..Key Size is 344 Bytes and KC Size is 372 Bytes
78682  *  0b101100..Key Size is 352 Bytes and KC Size is 372 Bytes
78683  *  0b101101..Key Size is 360 Bytes and KC Size is 404 Bytes
78684  *  0b101110..Key Size is 368 Bytes and KC Size is 404 Bytes
78685  *  0b101111..Key Size is 376 Bytes and KC Size is 404 Bytes
78686  *  0b110000..Key Size is 384 Bytes and KC Size is 404 Bytes
78687  *  0b110001..Key Size is 392 Bytes and KC Size is 436 Bytes
78688  *  0b110010..Key Size is 400 Bytes and KC Size is 436 Bytes
78689  *  0b110011..Key Size is 408 Bytes and KC Size is 436 Bytes
78690  *  0b110100..Key Size is 416 Bytes and KC Size is 436 Bytes
78691  *  0b110101..Key Size is 424 Bytes and KC Size is 468 Bytes
78692  *  0b110110..Key Size is 432 Bytes and KC Size is 468 Bytes
78693  *  0b110111..Key Size is 440 Bytes and KC Size is 468 Bytes
78694  *  0b111000..Key Size is 448 Bytes and KC Size is 468 Bytes
78695  *  0b111001..Key Size is 456 Bytes and KC Size is 500 Bytes
78696  *  0b111010..Key Size is 464 Bytes and KC Size is 500 Bytes
78697  *  0b111011..Key Size is 472 Bytes and KC Size is 500 Bytes
78698  *  0b111100..Key Size is 480 Bytes and KC Size is 500 Bytes
78699  *  0b111101..Key Size is 488 Bytes and KC Size is 532 Bytes
78700  *  0b111110..Key Size is 496 Bytes and KC Size is 532 Bytes
78701  *  0b111111..Key Size is 504 Bytes and KC Size is 532 Bytes
78702  *  0b000000..Key Size is 512 Bytes and KC Size is 532 Bytes
78703  */
78704 #define PUF_KEYSIZE_KEYSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
78705 /*! @} */
78706 
78707 /*! @name STAT - PUF Status Register */
78708 /*! @{ */
78709 
78710 #define PUF_STAT_BUSY_MASK                       (0x1U)
78711 #define PUF_STAT_BUSY_SHIFT                      (0U)
78712 /*! BUSY - puf_busy
78713  *  0b0..IDLE
78714  *  0b1..BUSY
78715  */
78716 #define PUF_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
78717 
78718 #define PUF_STAT_SUCCESS_MASK                    (0x2U)
78719 #define PUF_STAT_SUCCESS_SHIFT                   (1U)
78720 /*! SUCCESS - puf_ok
78721  *  0b0..Last operation was unsuccessful
78722  *  0b1..Last operation was successful
78723  */
78724 #define PUF_STAT_SUCCESS(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
78725 
78726 #define PUF_STAT_ERROR_MASK                      (0x4U)
78727 #define PUF_STAT_ERROR_SHIFT                     (2U)
78728 /*! ERROR - puf_error
78729  *  0b0..PUF is not in the Error state
78730  *  0b1..PUF is in the Error state
78731  */
78732 #define PUF_STAT_ERROR(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
78733 
78734 #define PUF_STAT_KEYINREQ_MASK                   (0x10U)
78735 #define PUF_STAT_KEYINREQ_SHIFT                  (4U)
78736 /*! KEYINREQ - KI_ir
78737  *  0b0..No request for next part of key
78738  *  0b1..Request for next part of key in KEYINPUT register
78739  */
78740 #define PUF_STAT_KEYINREQ(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
78741 
78742 #define PUF_STAT_KEYOUTAVAIL_MASK                (0x20U)
78743 #define PUF_STAT_KEYOUTAVAIL_SHIFT               (5U)
78744 /*! KEYOUTAVAIL - KO_or
78745  *  0b0..Next part of key is not available
78746  *  0b1..Next part of key is available in KEYOUTPUT register
78747  */
78748 #define PUF_STAT_KEYOUTAVAIL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
78749 
78750 #define PUF_STAT_CODEINREQ_MASK                  (0x40U)
78751 #define PUF_STAT_CODEINREQ_SHIFT                 (6U)
78752 /*! CODEINREQ - CI_ir
78753  *  0b0..No request for next part of Activation Code/Key Code
78754  *  0b1..request for next part of Activation Code/Key Code in CODEINPUT register
78755  */
78756 #define PUF_STAT_CODEINREQ(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
78757 
78758 #define PUF_STAT_CODEOUTAVAIL_MASK               (0x80U)
78759 #define PUF_STAT_CODEOUTAVAIL_SHIFT              (7U)
78760 /*! CODEOUTAVAIL - CO_or
78761  *  0b0..Next part of Activation Code/Key Code is not available
78762  *  0b1..Next part of Activation Code/Key Code is available in CODEOUTPUT register
78763  */
78764 #define PUF_STAT_CODEOUTAVAIL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
78765 /*! @} */
78766 
78767 /*! @name ALLOW - PUF Allow Register */
78768 /*! @{ */
78769 
78770 #define PUF_ALLOW_ALLOWENROLL_MASK               (0x1U)
78771 #define PUF_ALLOW_ALLOWENROLL_SHIFT              (0U)
78772 /*! ALLOWENROLL - Allow Enroll operation
78773  *  0b0..Specified operation is not currently allowed
78774  *  0b1..Specified operation is allowed
78775  */
78776 #define PUF_ALLOW_ALLOWENROLL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
78777 
78778 #define PUF_ALLOW_ALLOWSTART_MASK                (0x2U)
78779 #define PUF_ALLOW_ALLOWSTART_SHIFT               (1U)
78780 /*! ALLOWSTART - Allow Start operation
78781  *  0b0..Specified operation is not currently allowed
78782  *  0b1..Specified operation is allowed
78783  */
78784 #define PUF_ALLOW_ALLOWSTART(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
78785 
78786 #define PUF_ALLOW_ALLOWSETKEY_MASK               (0x4U)
78787 #define PUF_ALLOW_ALLOWSETKEY_SHIFT              (2U)
78788 /*! ALLOWSETKEY - Allow Set Key operations
78789  *  0b0..Specified operation is not currently allowed
78790  *  0b1..Specified operation is allowed
78791  */
78792 #define PUF_ALLOW_ALLOWSETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
78793 
78794 #define PUF_ALLOW_ALLOWGETKEY_MASK               (0x8U)
78795 #define PUF_ALLOW_ALLOWGETKEY_SHIFT              (3U)
78796 /*! ALLOWGETKEY - Allow Get Key operation
78797  *  0b0..Specified operation is not currently allowed
78798  *  0b1..Specified operation is allowed
78799  */
78800 #define PUF_ALLOW_ALLOWGETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
78801 /*! @} */
78802 
78803 /*! @name KEYINPUT - PUF Key Input Register */
78804 /*! @{ */
78805 
78806 #define PUF_KEYINPUT_KEYIN_MASK                  (0xFFFFFFFFU)
78807 #define PUF_KEYINPUT_KEYIN_SHIFT                 (0U)
78808 /*! KEYIN - Key input data
78809  */
78810 #define PUF_KEYINPUT_KEYIN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
78811 /*! @} */
78812 
78813 /*! @name CODEINPUT - PUF Code Input Register */
78814 /*! @{ */
78815 
78816 #define PUF_CODEINPUT_CODEIN_MASK                (0xFFFFFFFFU)
78817 #define PUF_CODEINPUT_CODEIN_SHIFT               (0U)
78818 /*! CODEIN - AC/KC input data
78819  */
78820 #define PUF_CODEINPUT_CODEIN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
78821 /*! @} */
78822 
78823 /*! @name CODEOUTPUT - PUF Code Output Register */
78824 /*! @{ */
78825 
78826 #define PUF_CODEOUTPUT_CODEOUT_MASK              (0xFFFFFFFFU)
78827 #define PUF_CODEOUTPUT_CODEOUT_SHIFT             (0U)
78828 /*! CODEOUT - AC/KC output data
78829  */
78830 #define PUF_CODEOUTPUT_CODEOUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
78831 /*! @} */
78832 
78833 /*! @name KEYOUTINDEX - PUF Key Output Index Register */
78834 /*! @{ */
78835 
78836 #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK           (0xFFFFFFFFU)
78837 #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT          (0U)
78838 /*! KEYOUTIDX - Output Key index
78839  */
78840 #define PUF_KEYOUTINDEX_KEYOUTIDX(x)             (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
78841 /*! @} */
78842 
78843 /*! @name KEYOUTPUT - PUF Key Output Register */
78844 /*! @{ */
78845 
78846 #define PUF_KEYOUTPUT_KEYOUT_MASK                (0xFFFFFFFFU)
78847 #define PUF_KEYOUTPUT_KEYOUT_SHIFT               (0U)
78848 /*! KEYOUT - Key output data from a Get Key operation
78849  */
78850 #define PUF_KEYOUTPUT_KEYOUT(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
78851 /*! @} */
78852 
78853 /*! @name IFSTAT - PUF Interface Status Register */
78854 /*! @{ */
78855 
78856 #define PUF_IFSTAT_ERROR_MASK                    (0x1U)
78857 #define PUF_IFSTAT_ERROR_SHIFT                   (0U)
78858 /*! ERROR - APB error has occurred
78859  *  0b0..NOERROR
78860  *  0b1..ERROR
78861  */
78862 #define PUF_IFSTAT_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
78863 /*! @} */
78864 
78865 /*! @name VERSION - PUF Version Register */
78866 /*! @{ */
78867 
78868 #define PUF_VERSION_VERSION_MASK                 (0xFFFFFFFFU)
78869 #define PUF_VERSION_VERSION_SHIFT                (0U)
78870 /*! VERSION - Version of PUF
78871  */
78872 #define PUF_VERSION_VERSION(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
78873 /*! @} */
78874 
78875 /*! @name INTEN - PUF Interrupt Enable */
78876 /*! @{ */
78877 
78878 #define PUF_INTEN_READYEN_MASK                   (0x1U)
78879 #define PUF_INTEN_READYEN_SHIFT                  (0U)
78880 /*! READYEN - PUF Ready Interrupt Enable
78881  *  0b0..PUF ready interrupt disabled
78882  *  0b1..PUF ready interrupt enabled
78883  */
78884 #define PUF_INTEN_READYEN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
78885 
78886 #define PUF_INTEN_SUCCESSEN_MASK                 (0x2U)
78887 #define PUF_INTEN_SUCCESSEN_SHIFT                (1U)
78888 /*! SUCCESSEN - PUF_OK Interrupt Enable
78889  *  0b0..PUF successful interrupt disabled
78890  *  0b1..PUF successful interrupt enabled
78891  */
78892 #define PUF_INTEN_SUCCESSEN(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK)
78893 
78894 #define PUF_INTEN_ERROREN_MASK                   (0x4U)
78895 #define PUF_INTEN_ERROREN_SHIFT                  (2U)
78896 /*! ERROREN - PUF Error Interrupt Enable
78897  *  0b0..PUF error interrupt disabled
78898  *  0b1..PUF error interrupt enabled
78899  */
78900 #define PUF_INTEN_ERROREN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
78901 
78902 #define PUF_INTEN_KEYINREQEN_MASK                (0x10U)
78903 #define PUF_INTEN_KEYINREQEN_SHIFT               (4U)
78904 /*! KEYINREQEN - PUF Key Input Register Interrupt Enable
78905  *  0b0..Key interrupt request disabled
78906  *  0b1..Key interrupt request enabled
78907  */
78908 #define PUF_INTEN_KEYINREQEN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
78909 
78910 #define PUF_INTEN_KEYOUTAVAILEN_MASK             (0x20U)
78911 #define PUF_INTEN_KEYOUTAVAILEN_SHIFT            (5U)
78912 /*! KEYOUTAVAILEN - PUF Key Output Register Interrupt Enable
78913  *  0b0..Key available interrupt disabled
78914  *  0b1..Key available interrupt enabled
78915  */
78916 #define PUF_INTEN_KEYOUTAVAILEN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
78917 
78918 #define PUF_INTEN_CODEINREQEN_MASK               (0x40U)
78919 #define PUF_INTEN_CODEINREQEN_SHIFT              (6U)
78920 /*! CODEINREQEN - PUF Code Input Register Interrupt Enable
78921  *  0b0..AC/KC interrupt request disabled
78922  *  0b1..AC/KC interrupt request enabled
78923  */
78924 #define PUF_INTEN_CODEINREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
78925 
78926 #define PUF_INTEN_CODEOUTAVAILEN_MASK            (0x80U)
78927 #define PUF_INTEN_CODEOUTAVAILEN_SHIFT           (7U)
78928 /*! CODEOUTAVAILEN - PUF Code Output Register Interrupt Enable
78929  *  0b0..AC/KC available interrupt disabled
78930  *  0b1..AC/KC available interrupt enabled
78931  */
78932 #define PUF_INTEN_CODEOUTAVAILEN(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
78933 /*! @} */
78934 
78935 /*! @name INTSTAT - PUF Interrupt Status */
78936 /*! @{ */
78937 
78938 #define PUF_INTSTAT_READY_MASK                   (0x1U)
78939 #define PUF_INTSTAT_READY_SHIFT                  (0U)
78940 /*! READY - PUF_FINISH Interrupt Status
78941  *  0b0..Indicates that last operation not finished
78942  *  0b1..Indicates that last operation is finished
78943  */
78944 #define PUF_INTSTAT_READY(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
78945 
78946 #define PUF_INTSTAT_SUCCESS_MASK                 (0x2U)
78947 #define PUF_INTSTAT_SUCCESS_SHIFT                (1U)
78948 /*! SUCCESS - PUF_OK Interrupt Status
78949  *  0b0..Indicates that last operation was not successful
78950  *  0b1..Indicates that last operation was successful
78951  */
78952 #define PUF_INTSTAT_SUCCESS(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
78953 
78954 #define PUF_INTSTAT_ERROR_MASK                   (0x4U)
78955 #define PUF_INTSTAT_ERROR_SHIFT                  (2U)
78956 /*! ERROR - PUF_ERROR Interrupt Status
78957  *  0b0..PUF is not in the Error state and operations can be performed
78958  *  0b1..PUF is in the Error state and no operations can be performed
78959  */
78960 #define PUF_INTSTAT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
78961 
78962 #define PUF_INTSTAT_KEYINREQ_MASK                (0x10U)
78963 #define PUF_INTSTAT_KEYINREQ_SHIFT               (4U)
78964 /*! KEYINREQ - PUF Key Input Register Interrupt Status
78965  *  0b0..No request for next part of key
78966  *  0b1..Request for next part of key
78967  */
78968 #define PUF_INTSTAT_KEYINREQ(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
78969 
78970 #define PUF_INTSTAT_KEYOUTAVAIL_MASK             (0x20U)
78971 #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT            (5U)
78972 /*! KEYOUTAVAIL - PUF Key Output Register Interrupt Status
78973  *  0b0..Next part of key is not available
78974  *  0b1..Next part of key is available
78975  */
78976 #define PUF_INTSTAT_KEYOUTAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
78977 
78978 #define PUF_INTSTAT_CODEINREQ_MASK               (0x40U)
78979 #define PUF_INTSTAT_CODEINREQ_SHIFT              (6U)
78980 /*! CODEINREQ - PUF Code Input Register Interrupt Status
78981  *  0b0..No request for next part of AC/KC
78982  *  0b1..Request for next part of AC/KC
78983  */
78984 #define PUF_INTSTAT_CODEINREQ(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
78985 
78986 #define PUF_INTSTAT_CODEOUTAVAIL_MASK            (0x80U)
78987 #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT           (7U)
78988 /*! CODEOUTAVAIL - PUF Code Output Register Interrupt Status
78989  *  0b0..Next part of AC/KC is not available
78990  *  0b1..Next part of AC/KC is available
78991  */
78992 #define PUF_INTSTAT_CODEOUTAVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
78993 /*! @} */
78994 
78995 /*! @name PWRCTRL - PUF Power Control Of RAM */
78996 /*! @{ */
78997 
78998 #define PUF_PWRCTRL_RAM_ON_MASK                  (0x1U)
78999 #define PUF_PWRCTRL_RAM_ON_SHIFT                 (0U)
79000 /*! RAM_ON - PUF RAM on
79001  *  0b0..PUF RAM is in sleep mode (PUF operation disabled)
79002  *  0b1..PUF RAM is awake (normal PUF operation enabled)
79003  */
79004 #define PUF_PWRCTRL_RAM_ON(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
79005 
79006 #define PUF_PWRCTRL_CK_DIS_MASK                  (0x4U)
79007 #define PUF_PWRCTRL_CK_DIS_SHIFT                 (2U)
79008 /*! CK_DIS - Clock disable
79009  *  0b0..PUF RAM is clocked (normal PUF operation enabled)
79010  *  0b1..PUF RAM clock is gated/disabled (PUF operation disabled)
79011  */
79012 #define PUF_PWRCTRL_CK_DIS(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
79013 
79014 #define PUF_PWRCTRL_RAM_INITN_MASK               (0x8U)
79015 #define PUF_PWRCTRL_RAM_INITN_SHIFT              (3U)
79016 /*! RAM_INITN - RAM initialization
79017  *  0b0..Reset the PUF RAM (PUF operation disabled)
79018  *  0b1..Do not reset the PUF RAM (normal PUF operation enabled)
79019  */
79020 #define PUF_PWRCTRL_RAM_INITN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK)
79021 
79022 #define PUF_PWRCTRL_RAM_PSW_MASK                 (0xF0U)
79023 #define PUF_PWRCTRL_RAM_PSW_SHIFT                (4U)
79024 /*! RAM_PSW - PUF RAM power switches
79025  */
79026 #define PUF_PWRCTRL_RAM_PSW(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK)
79027 /*! @} */
79028 
79029 /*! @name CFG - PUF Configuration Register */
79030 /*! @{ */
79031 
79032 #define PUF_CFG_PUF_BLOCK_SET_KEY_MASK           (0x1U)
79033 #define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT          (0U)
79034 /*! PUF_BLOCK_SET_KEY - PUF Block Set Key Disable
79035  *  0b0..Enable the Set Key state
79036  *  0b1..Disable the Set Key state
79037  */
79038 #define PUF_CFG_PUF_BLOCK_SET_KEY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK)
79039 
79040 #define PUF_CFG_PUF_BLOCK_ENROLL_MASK            (0x2U)
79041 #define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT           (1U)
79042 /*! PUF_BLOCK_ENROLL - PUF Block Enroll Disable
79043  *  0b0..Enable the Enrollment state
79044  *  0b1..Disable the Enrollment state
79045  */
79046 #define PUF_CFG_PUF_BLOCK_ENROLL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK)
79047 /*! @} */
79048 
79049 /*! @name KEYLOCK - PUF Key Manager Lock */
79050 /*! @{ */
79051 
79052 #define PUF_KEYLOCK_LOCK0_MASK                   (0x3U)
79053 #define PUF_KEYLOCK_LOCK0_SHIFT                  (0U)
79054 /*! LOCK0 - Lock Block 0
79055  *  0b11..SNVS Key block locked
79056  *  0b10..SNVS Key block unlocked
79057  *  0b01..SNVS Key block locked
79058  *  0b00..SNVS Key block locked
79059  */
79060 #define PUF_KEYLOCK_LOCK0(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK)
79061 
79062 #define PUF_KEYLOCK_LOCK1_MASK                   (0xCU)
79063 #define PUF_KEYLOCK_LOCK1_SHIFT                  (2U)
79064 /*! LOCK1 - Lock Block 1
79065  *  0b11..OTFAD Key block locked
79066  *  0b10..OTFAD Key block unlocked
79067  *  0b01..OTFAD Key block locked
79068  *  0b00..OTFAD Key block locked
79069  */
79070 #define PUF_KEYLOCK_LOCK1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK)
79071 /*! @} */
79072 
79073 /*! @name KEYENABLE - PUF Key Manager Enable */
79074 /*! @{ */
79075 
79076 #define PUF_KEYENABLE_ENABLE0_MASK               (0x3U)
79077 #define PUF_KEYENABLE_ENABLE0_SHIFT              (0U)
79078 /*! ENABLE0 - Enable Block 0
79079  *  0b11..Key block 0 disabled
79080  *  0b10..Key block 0 enabled
79081  *  0b01..Key block 0 disabled
79082  *  0b00..Key block 0 disabled
79083  */
79084 #define PUF_KEYENABLE_ENABLE0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK)
79085 
79086 #define PUF_KEYENABLE_ENABLE1_MASK               (0xCU)
79087 #define PUF_KEYENABLE_ENABLE1_SHIFT              (2U)
79088 /*! ENABLE1 - Enable Block 1
79089  *  0b11..Key block 1 disabled
79090  *  0b10..Key block 1 enabled
79091  *  0b01..Key block 1 disabled
79092  *  0b00..Key block 1 disabled
79093  */
79094 #define PUF_KEYENABLE_ENABLE1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK)
79095 /*! @} */
79096 
79097 /*! @name KEYRESET - PUF Key Manager Reset */
79098 /*! @{ */
79099 
79100 #define PUF_KEYRESET_RESET0_MASK                 (0x3U)
79101 #define PUF_KEYRESET_RESET0_SHIFT                (0U)
79102 /*! RESET0 - Reset Block 0
79103  *  0b11..Do not reset key block 0
79104  *  0b10..Reset key block 0
79105  *  0b01..Do not reset key block 0
79106  *  0b00..Do not reset key block 0
79107  */
79108 #define PUF_KEYRESET_RESET0(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK)
79109 
79110 #define PUF_KEYRESET_RESET1_MASK                 (0xCU)
79111 #define PUF_KEYRESET_RESET1_SHIFT                (2U)
79112 /*! RESET1 - Reset Block 1
79113  *  0b11..Do not reset key block 1
79114  *  0b10..Reset key block 1
79115  *  0b01..Do not reset key block 1
79116  *  0b00..Do not reset key block 1
79117  */
79118 #define PUF_KEYRESET_RESET1(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK)
79119 /*! @} */
79120 
79121 /*! @name IDXBLK - PUF Index Block Key Output */
79122 /*! @{ */
79123 
79124 #define PUF_IDXBLK_IDXBLK0_MASK                  (0x3U)
79125 #define PUF_IDXBLK_IDXBLK0_SHIFT                 (0U)
79126 /*! IDXBLK0 - idxblk0
79127  */
79128 #define PUF_IDXBLK_IDXBLK0(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK)
79129 
79130 #define PUF_IDXBLK_IDXBLK1_MASK                  (0xCU)
79131 #define PUF_IDXBLK_IDXBLK1_SHIFT                 (2U)
79132 /*! IDXBLK1 - idxblk1
79133  */
79134 #define PUF_IDXBLK_IDXBLK1(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK)
79135 
79136 #define PUF_IDXBLK_IDXBLK2_MASK                  (0x30U)
79137 #define PUF_IDXBLK_IDXBLK2_SHIFT                 (4U)
79138 /*! IDXBLK2 - idxblk2
79139  */
79140 #define PUF_IDXBLK_IDXBLK2(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK)
79141 
79142 #define PUF_IDXBLK_IDXBLK3_MASK                  (0xC0U)
79143 #define PUF_IDXBLK_IDXBLK3_SHIFT                 (6U)
79144 /*! IDXBLK3 - idxblk3
79145  */
79146 #define PUF_IDXBLK_IDXBLK3(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK)
79147 
79148 #define PUF_IDXBLK_IDXBLK4_MASK                  (0x300U)
79149 #define PUF_IDXBLK_IDXBLK4_SHIFT                 (8U)
79150 /*! IDXBLK4 - idxblk4
79151  */
79152 #define PUF_IDXBLK_IDXBLK4(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK)
79153 
79154 #define PUF_IDXBLK_IDXBLK5_MASK                  (0xC00U)
79155 #define PUF_IDXBLK_IDXBLK5_SHIFT                 (10U)
79156 /*! IDXBLK5 - idxblk5
79157  */
79158 #define PUF_IDXBLK_IDXBLK5(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK)
79159 
79160 #define PUF_IDXBLK_IDXBLK6_MASK                  (0x3000U)
79161 #define PUF_IDXBLK_IDXBLK6_SHIFT                 (12U)
79162 /*! IDXBLK6 - idxblk6
79163  */
79164 #define PUF_IDXBLK_IDXBLK6(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK)
79165 
79166 #define PUF_IDXBLK_IDXBLK7_MASK                  (0xC000U)
79167 #define PUF_IDXBLK_IDXBLK7_SHIFT                 (14U)
79168 /*! IDXBLK7 - idxblk7
79169  */
79170 #define PUF_IDXBLK_IDXBLK7(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK)
79171 
79172 #define PUF_IDXBLK_IDXBLK8_MASK                  (0x30000U)
79173 #define PUF_IDXBLK_IDXBLK8_SHIFT                 (16U)
79174 /*! IDXBLK8 - idxblk8
79175  */
79176 #define PUF_IDXBLK_IDXBLK8(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK)
79177 
79178 #define PUF_IDXBLK_IDXBLK9_MASK                  (0xC0000U)
79179 #define PUF_IDXBLK_IDXBLK9_SHIFT                 (18U)
79180 /*! IDXBLK9 - idxblk9
79181  */
79182 #define PUF_IDXBLK_IDXBLK9(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK)
79183 
79184 #define PUF_IDXBLK_IDXBLK10_MASK                 (0x300000U)
79185 #define PUF_IDXBLK_IDXBLK10_SHIFT                (20U)
79186 /*! IDXBLK10 - idxblk10
79187  */
79188 #define PUF_IDXBLK_IDXBLK10(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK)
79189 
79190 #define PUF_IDXBLK_IDXBLK11_MASK                 (0xC00000U)
79191 #define PUF_IDXBLK_IDXBLK11_SHIFT                (22U)
79192 /*! IDXBLK11 - idxblk11
79193  */
79194 #define PUF_IDXBLK_IDXBLK11(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK)
79195 
79196 #define PUF_IDXBLK_IDXBLK12_MASK                 (0x3000000U)
79197 #define PUF_IDXBLK_IDXBLK12_SHIFT                (24U)
79198 /*! IDXBLK12 - idxblk12
79199  */
79200 #define PUF_IDXBLK_IDXBLK12(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK)
79201 
79202 #define PUF_IDXBLK_IDXBLK13_MASK                 (0xC000000U)
79203 #define PUF_IDXBLK_IDXBLK13_SHIFT                (26U)
79204 /*! IDXBLK13 - idxblk13
79205  */
79206 #define PUF_IDXBLK_IDXBLK13(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK)
79207 
79208 #define PUF_IDXBLK_IDXBLK14_MASK                 (0x30000000U)
79209 #define PUF_IDXBLK_IDXBLK14_SHIFT                (28U)
79210 /*! IDXBLK14 - idxblk14
79211  */
79212 #define PUF_IDXBLK_IDXBLK14(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK)
79213 
79214 #define PUF_IDXBLK_IDXBLK15_MASK                 (0xC0000000U)
79215 #define PUF_IDXBLK_IDXBLK15_SHIFT                (30U)
79216 /*! IDXBLK15 - idxblk15
79217  */
79218 #define PUF_IDXBLK_IDXBLK15(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK)
79219 /*! @} */
79220 
79221 /*! @name IDXBLK_DP - PUF Index Block Key Output */
79222 /*! @{ */
79223 
79224 #define PUF_IDXBLK_DP_IDXBLK_DP0_MASK            (0x3U)
79225 #define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT           (0U)
79226 /*! IDXBLK_DP0 - idxblk_dp0
79227  */
79228 #define PUF_IDXBLK_DP_IDXBLK_DP0(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK)
79229 
79230 #define PUF_IDXBLK_DP_IDXBLK_DP1_MASK            (0xCU)
79231 #define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT           (2U)
79232 /*! IDXBLK_DP1 - idxblk_dp1
79233  */
79234 #define PUF_IDXBLK_DP_IDXBLK_DP1(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK)
79235 
79236 #define PUF_IDXBLK_DP_IDXBLK_DP2_MASK            (0x30U)
79237 #define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT           (4U)
79238 /*! IDXBLK_DP2 - idxblk_dp2
79239  */
79240 #define PUF_IDXBLK_DP_IDXBLK_DP2(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK)
79241 
79242 #define PUF_IDXBLK_DP_IDXBLK_DP3_MASK            (0xC0U)
79243 #define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT           (6U)
79244 /*! IDXBLK_DP3 - idxblk_dp3
79245  */
79246 #define PUF_IDXBLK_DP_IDXBLK_DP3(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK)
79247 
79248 #define PUF_IDXBLK_DP_IDXBLK_DP4_MASK            (0x300U)
79249 #define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT           (8U)
79250 /*! IDXBLK_DP4 - idxblk_dp4
79251  */
79252 #define PUF_IDXBLK_DP_IDXBLK_DP4(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK)
79253 
79254 #define PUF_IDXBLK_DP_IDXBLK_DP5_MASK            (0xC00U)
79255 #define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT           (10U)
79256 /*! IDXBLK_DP5 - idxblk_dp5
79257  */
79258 #define PUF_IDXBLK_DP_IDXBLK_DP5(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK)
79259 
79260 #define PUF_IDXBLK_DP_IDXBLK_DP6_MASK            (0x3000U)
79261 #define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT           (12U)
79262 /*! IDXBLK_DP6 - idxblk_dp6
79263  */
79264 #define PUF_IDXBLK_DP_IDXBLK_DP6(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK)
79265 
79266 #define PUF_IDXBLK_DP_IDXBLK_DP7_MASK            (0xC000U)
79267 #define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT           (14U)
79268 /*! IDXBLK_DP7 - idxblk_dp7
79269  */
79270 #define PUF_IDXBLK_DP_IDXBLK_DP7(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK)
79271 
79272 #define PUF_IDXBLK_DP_IDXBLK_DP8_MASK            (0x30000U)
79273 #define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT           (16U)
79274 /*! IDXBLK_DP8 - idxblk_dp8
79275  */
79276 #define PUF_IDXBLK_DP_IDXBLK_DP8(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK)
79277 
79278 #define PUF_IDXBLK_DP_IDXBLK_DP9_MASK            (0xC0000U)
79279 #define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT           (18U)
79280 /*! IDXBLK_DP9 - idxblk_dp9
79281  */
79282 #define PUF_IDXBLK_DP_IDXBLK_DP9(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK)
79283 
79284 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK           (0x300000U)
79285 #define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT          (20U)
79286 /*! IDXBLK_DP10 - idxblk_dp10
79287  */
79288 #define PUF_IDXBLK_DP_IDXBLK_DP10(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
79289 
79290 #define PUF_IDXBLK_DP_IDXBLK_DP11_MASK           (0xC00000U)
79291 #define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT          (22U)
79292 /*! IDXBLK_DP11 - idxblk_dp11
79293  */
79294 #define PUF_IDXBLK_DP_IDXBLK_DP11(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK)
79295 
79296 #define PUF_IDXBLK_DP_IDXBLK_DP12_MASK           (0x3000000U)
79297 #define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT          (24U)
79298 /*! IDXBLK_DP12 - idxblk_dp12
79299  */
79300 #define PUF_IDXBLK_DP_IDXBLK_DP12(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK)
79301 
79302 #define PUF_IDXBLK_DP_IDXBLK_DP13_MASK           (0xC000000U)
79303 #define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT          (26U)
79304 /*! IDXBLK_DP13 - idxblk_dp13
79305  */
79306 #define PUF_IDXBLK_DP_IDXBLK_DP13(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK)
79307 
79308 #define PUF_IDXBLK_DP_IDXBLK_DP14_MASK           (0x30000000U)
79309 #define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT          (28U)
79310 /*! IDXBLK_DP14 - idxblk_dp14
79311  */
79312 #define PUF_IDXBLK_DP_IDXBLK_DP14(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK)
79313 
79314 #define PUF_IDXBLK_DP_IDXBLK_DP15_MASK           (0xC0000000U)
79315 #define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT          (30U)
79316 /*! IDXBLK_DP15 - idxblk_dp15
79317  */
79318 #define PUF_IDXBLK_DP_IDXBLK_DP15(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK)
79319 /*! @} */
79320 
79321 /*! @name KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable */
79322 /*! @{ */
79323 
79324 #define PUF_KEYMASK_KEYMASK_MASK                 (0xFFFFFFFFU)
79325 #define PUF_KEYMASK_KEYMASK_SHIFT                (0U)
79326 /*! KEYMASK - KEYMASK1
79327  */
79328 #define PUF_KEYMASK_KEYMASK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
79329 /*! @} */
79330 
79331 /* The count of PUF_KEYMASK */
79332 #define PUF_KEYMASK_COUNT                        (2U)
79333 
79334 /*! @name IDXBLK_STATUS - PUF Index Block Setting Status Register */
79335 /*! @{ */
79336 
79337 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK    (0x3U)
79338 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT   (0U)
79339 /*! IDXBLK_STATUS0 - idxblk_status0
79340  */
79341 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK)
79342 
79343 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK    (0xCU)
79344 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT   (2U)
79345 /*! IDXBLK_STATUS1 - idxblk_status1
79346  */
79347 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
79348 
79349 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK    (0x30U)
79350 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT   (4U)
79351 /*! IDXBLK_STATUS2 - idxblk_status2
79352  */
79353 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK)
79354 
79355 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK    (0xC0U)
79356 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT   (6U)
79357 /*! IDXBLK_STATUS3 - idxblk_status3
79358  */
79359 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK)
79360 
79361 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK    (0x300U)
79362 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT   (8U)
79363 /*! IDXBLK_STATUS4 - idxblk_status4
79364  */
79365 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK)
79366 
79367 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK    (0xC00U)
79368 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT   (10U)
79369 /*! IDXBLK_STATUS5 - idxblk_status5
79370  */
79371 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK)
79372 
79373 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK    (0x3000U)
79374 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT   (12U)
79375 /*! IDXBLK_STATUS6 - idxblk_status6
79376  */
79377 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK)
79378 
79379 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK    (0xC000U)
79380 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT   (14U)
79381 /*! IDXBLK_STATUS7 - idxblk_status7
79382  */
79383 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK)
79384 
79385 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK    (0x30000U)
79386 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT   (16U)
79387 /*! IDXBLK_STATUS8 - idxblk_status8
79388  */
79389 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK)
79390 
79391 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK    (0xC0000U)
79392 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT   (18U)
79393 /*! IDXBLK_STATUS9 - idxblk_status9
79394  */
79395 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK)
79396 
79397 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK   (0x300000U)
79398 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT  (20U)
79399 /*! IDXBLK_STATUS10 - idxblk_status10
79400  */
79401 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK)
79402 
79403 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK   (0xC00000U)
79404 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT  (22U)
79405 /*! IDXBLK_STATUS11 - idxblk_status11
79406  */
79407 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK)
79408 
79409 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK   (0x3000000U)
79410 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT  (24U)
79411 /*! IDXBLK_STATUS12 - idxblk_status12
79412  */
79413 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK)
79414 
79415 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK   (0xC000000U)
79416 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT  (26U)
79417 /*! IDXBLK_STATUS13 - idxblk_status13
79418  */
79419 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK)
79420 
79421 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK   (0x30000000U)
79422 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT  (28U)
79423 /*! IDXBLK_STATUS14 - idxblk_status14
79424  */
79425 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK)
79426 
79427 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK   (0xC0000000U)
79428 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT  (30U)
79429 /*! IDXBLK_STATUS15 - idxblk_status15
79430  */
79431 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK)
79432 /*! @} */
79433 
79434 /*! @name IDXBLK_SHIFT - PUF Key Manager Shift Status */
79435 /*! @{ */
79436 
79437 #define PUF_IDXBLK_SHIFT_IND_KEY0_MASK           (0xFU)
79438 #define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT          (0U)
79439 /*! IND_KEY0 - Index of key space in block 0
79440  */
79441 #define PUF_IDXBLK_SHIFT_IND_KEY0(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK)
79442 
79443 #define PUF_IDXBLK_SHIFT_IND_KEY1_MASK           (0xF0U)
79444 #define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT          (4U)
79445 /*! IND_KEY1 - Index of key space in block 1
79446  */
79447 #define PUF_IDXBLK_SHIFT_IND_KEY1(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK)
79448 /*! @} */
79449 
79450 
79451 /*!
79452  * @}
79453  */ /* end of group PUF_Register_Masks */
79454 
79455 
79456 /* PUF - Peripheral instance base addresses */
79457 /** Peripheral KEY_MANAGER__PUF base address */
79458 #define KEY_MANAGER__PUF_BASE                    (0x40C82000u)
79459 /** Peripheral KEY_MANAGER__PUF base pointer */
79460 #define KEY_MANAGER__PUF                         ((PUF_Type *)KEY_MANAGER__PUF_BASE)
79461 /** Array initializer of PUF peripheral base addresses */
79462 #define PUF_BASE_ADDRS                           { KEY_MANAGER__PUF_BASE }
79463 /** Array initializer of PUF peripheral base pointers */
79464 #define PUF_BASE_PTRS                            { KEY_MANAGER__PUF }
79465 
79466 /*!
79467  * @}
79468  */ /* end of group PUF_Peripheral_Access_Layer */
79469 
79470 
79471 /* ----------------------------------------------------------------------------
79472    -- PWM Peripheral Access Layer
79473    ---------------------------------------------------------------------------- */
79474 
79475 /*!
79476  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
79477  * @{
79478  */
79479 
79480 /** PWM - Register Layout Typedef */
79481 typedef struct {
79482   struct {                                         /* offset: 0x0, array step: 0x60 */
79483     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
79484     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
79485     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
79486     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
79487          uint8_t RESERVED_0[2];
79488     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
79489     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
79490     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
79491     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
79492     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
79493     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
79494     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
79495     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
79496     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
79497     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
79498     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
79499     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
79500     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
79501     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
79502     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
79503     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
79504     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
79505     __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
79506          uint8_t RESERVED_1[2];
79507     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
79508     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
79509     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
79510     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
79511     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
79512     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
79513     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
79514     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
79515     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
79516     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
79517     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
79518     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
79519     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
79520     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
79521     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
79522     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
79523     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
79524     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
79525     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
79526     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
79527          uint8_t RESERVED_2[8];
79528   } SM[4];
79529   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
79530   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
79531   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
79532   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
79533   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
79534   __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
79535   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
79536   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
79537   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
79538   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
79539   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
79540 } PWM_Type;
79541 
79542 /* ----------------------------------------------------------------------------
79543    -- PWM Register Masks
79544    ---------------------------------------------------------------------------- */
79545 
79546 /*!
79547  * @addtogroup PWM_Register_Masks PWM Register Masks
79548  * @{
79549  */
79550 
79551 /*! @name CNT - Counter Register */
79552 /*! @{ */
79553 
79554 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
79555 #define PWM_CNT_CNT_SHIFT                        (0U)
79556 /*! CNT - Counter Register Bits
79557  */
79558 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
79559 /*! @} */
79560 
79561 /* The count of PWM_CNT */
79562 #define PWM_CNT_COUNT                            (4U)
79563 
79564 /*! @name INIT - Initial Count Register */
79565 /*! @{ */
79566 
79567 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
79568 #define PWM_INIT_INIT_SHIFT                      (0U)
79569 /*! INIT - Initial Count Register Bits
79570  */
79571 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
79572 /*! @} */
79573 
79574 /* The count of PWM_INIT */
79575 #define PWM_INIT_COUNT                           (4U)
79576 
79577 /*! @name CTRL2 - Control 2 Register */
79578 /*! @{ */
79579 
79580 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
79581 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
79582 /*! CLK_SEL - Clock Source Select
79583  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
79584  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
79585  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
79586  *        setting should not be used in submodule 0 as it will force the clock to logic 0.
79587  *  0b11..reserved
79588  */
79589 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
79590 
79591 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
79592 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
79593 /*! RELOAD_SEL - Reload Source Select
79594  *  0b0..The local RELOAD signal is used to reload registers.
79595  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
79596  *       in submodule 0 as it will force the RELOAD signal to logic 0.
79597  */
79598 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
79599 
79600 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
79601 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
79602 /*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
79603  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
79604  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
79605  *         submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
79606  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
79607  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
79608  *         not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
79609  *  0b100..The local sync signal from this submodule is used to force updates.
79610  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
79611  *         submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
79612  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
79613  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
79614  */
79615 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
79616 
79617 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
79618 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
79619 /*! FORCE - Force Initialization
79620  */
79621 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
79622 
79623 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
79624 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
79625 /*! FRCEN - FRCEN
79626  *  0b0..Initialization from a FORCE_OUT is disabled.
79627  *  0b1..Initialization from a FORCE_OUT is enabled.
79628  */
79629 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
79630 
79631 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
79632 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
79633 /*! INIT_SEL - Initialization Control Select
79634  *  0b00..Local sync (PWM_X) causes initialization.
79635  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
79636  *        it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
79637  *        reload occurs.
79638  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
79639  *        will force the INIT signal to logic 0.
79640  *  0b11..EXT_SYNC causes initialization.
79641  */
79642 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
79643 
79644 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
79645 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
79646 /*! PWMX_INIT - PWM_X Initial Value
79647  */
79648 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
79649 
79650 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
79651 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
79652 /*! PWM45_INIT - PWM45 Initial Value
79653  */
79654 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
79655 
79656 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
79657 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
79658 /*! PWM23_INIT - PWM23 Initial Value
79659  */
79660 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
79661 
79662 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
79663 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
79664 /*! INDEP - Independent or Complementary Pair Operation
79665  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
79666  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
79667  */
79668 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
79669 
79670 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
79671 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
79672 /*! WAITEN - WAIT Enable
79673  */
79674 #define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
79675 
79676 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
79677 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
79678 /*! DBGEN - Debug Enable
79679  */
79680 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
79681 /*! @} */
79682 
79683 /* The count of PWM_CTRL2 */
79684 #define PWM_CTRL2_COUNT                          (4U)
79685 
79686 /*! @name CTRL - Control Register */
79687 /*! @{ */
79688 
79689 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
79690 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
79691 /*! DBLEN - Double Switching Enable
79692  *  0b0..Double switching disabled.
79693  *  0b1..Double switching enabled.
79694  */
79695 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
79696 
79697 #define PWM_CTRL_DBLX_MASK                       (0x2U)
79698 #define PWM_CTRL_DBLX_SHIFT                      (1U)
79699 /*! DBLX - PWMX Double Switching Enable
79700  *  0b0..PWMX double pulse disabled.
79701  *  0b1..PWMX double pulse enabled.
79702  */
79703 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
79704 
79705 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
79706 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
79707 /*! LDMOD - Load Mode Select
79708  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
79709  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
79710  *       In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
79711  */
79712 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
79713 
79714 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
79715 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
79716 /*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
79717  *  0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
79718  *  0b1..DBLPWM is split to PWMA and PWMB.
79719  */
79720 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
79721 
79722 #define PWM_CTRL_PRSC_MASK                       (0x70U)
79723 #define PWM_CTRL_PRSC_SHIFT                      (4U)
79724 /*! PRSC - Prescaler
79725  *  0b000..Prescaler 1
79726  *  0b001..Prescaler 2
79727  *  0b010..Prescaler 4
79728  *  0b011..Prescaler 8
79729  *  0b100..Prescaler 16
79730  *  0b101..Prescaler 32
79731  *  0b110..Prescaler 64
79732  *  0b111..Prescaler 128
79733  */
79734 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
79735 
79736 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
79737 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
79738 /*! COMPMODE - Compare Mode
79739  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
79740  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
79741  *       output that is high at the end of a period will maintain this state until a match with VAL3 clears the
79742  *       output in the following period.
79743  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
79744  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
79745  *       values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
79746  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
79747  */
79748 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
79749 
79750 #define PWM_CTRL_DT_MASK                         (0x300U)
79751 #define PWM_CTRL_DT_SHIFT                        (8U)
79752 /*! DT - Deadtime
79753  */
79754 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
79755 
79756 #define PWM_CTRL_FULL_MASK                       (0x400U)
79757 #define PWM_CTRL_FULL_SHIFT                      (10U)
79758 /*! FULL - Full Cycle Reload
79759  *  0b0..Full-cycle reloads disabled.
79760  *  0b1..Full-cycle reloads enabled.
79761  */
79762 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
79763 
79764 #define PWM_CTRL_HALF_MASK                       (0x800U)
79765 #define PWM_CTRL_HALF_SHIFT                      (11U)
79766 /*! HALF - Half Cycle Reload
79767  *  0b0..Half-cycle reloads disabled.
79768  *  0b1..Half-cycle reloads enabled.
79769  */
79770 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
79771 
79772 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
79773 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
79774 /*! LDFQ - Load Frequency
79775  *  0b0000..Every PWM opportunity
79776  *  0b0001..Every 2 PWM opportunities
79777  *  0b0010..Every 3 PWM opportunities
79778  *  0b0011..Every 4 PWM opportunities
79779  *  0b0100..Every 5 PWM opportunities
79780  *  0b0101..Every 6 PWM opportunities
79781  *  0b0110..Every 7 PWM opportunities
79782  *  0b0111..Every 8 PWM opportunities
79783  *  0b1000..Every 9 PWM opportunities
79784  *  0b1001..Every 10 PWM opportunities
79785  *  0b1010..Every 11 PWM opportunities
79786  *  0b1011..Every 12 PWM opportunities
79787  *  0b1100..Every 13 PWM opportunities
79788  *  0b1101..Every 14 PWM opportunities
79789  *  0b1110..Every 15 PWM opportunities
79790  *  0b1111..Every 16 PWM opportunities
79791  */
79792 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
79793 /*! @} */
79794 
79795 /* The count of PWM_CTRL */
79796 #define PWM_CTRL_COUNT                           (4U)
79797 
79798 /*! @name VAL0 - Value Register 0 */
79799 /*! @{ */
79800 
79801 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
79802 #define PWM_VAL0_VAL0_SHIFT                      (0U)
79803 /*! VAL0 - Value Register 0
79804  */
79805 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
79806 /*! @} */
79807 
79808 /* The count of PWM_VAL0 */
79809 #define PWM_VAL0_COUNT                           (4U)
79810 
79811 /*! @name FRACVAL1 - Fractional Value Register 1 */
79812 /*! @{ */
79813 
79814 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
79815 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
79816 /*! FRACVAL1 - Fractional Value 1 Register
79817  */
79818 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
79819 /*! @} */
79820 
79821 /* The count of PWM_FRACVAL1 */
79822 #define PWM_FRACVAL1_COUNT                       (4U)
79823 
79824 /*! @name VAL1 - Value Register 1 */
79825 /*! @{ */
79826 
79827 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
79828 #define PWM_VAL1_VAL1_SHIFT                      (0U)
79829 /*! VAL1 - Value Register 1
79830  */
79831 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
79832 /*! @} */
79833 
79834 /* The count of PWM_VAL1 */
79835 #define PWM_VAL1_COUNT                           (4U)
79836 
79837 /*! @name FRACVAL2 - Fractional Value Register 2 */
79838 /*! @{ */
79839 
79840 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
79841 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
79842 /*! FRACVAL2 - Fractional Value 2
79843  */
79844 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
79845 /*! @} */
79846 
79847 /* The count of PWM_FRACVAL2 */
79848 #define PWM_FRACVAL2_COUNT                       (4U)
79849 
79850 /*! @name VAL2 - Value Register 2 */
79851 /*! @{ */
79852 
79853 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
79854 #define PWM_VAL2_VAL2_SHIFT                      (0U)
79855 /*! VAL2 - Value Register 2
79856  */
79857 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
79858 /*! @} */
79859 
79860 /* The count of PWM_VAL2 */
79861 #define PWM_VAL2_COUNT                           (4U)
79862 
79863 /*! @name FRACVAL3 - Fractional Value Register 3 */
79864 /*! @{ */
79865 
79866 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
79867 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
79868 /*! FRACVAL3 - Fractional Value 3
79869  */
79870 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
79871 /*! @} */
79872 
79873 /* The count of PWM_FRACVAL3 */
79874 #define PWM_FRACVAL3_COUNT                       (4U)
79875 
79876 /*! @name VAL3 - Value Register 3 */
79877 /*! @{ */
79878 
79879 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
79880 #define PWM_VAL3_VAL3_SHIFT                      (0U)
79881 /*! VAL3 - Value Register 3
79882  */
79883 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
79884 /*! @} */
79885 
79886 /* The count of PWM_VAL3 */
79887 #define PWM_VAL3_COUNT                           (4U)
79888 
79889 /*! @name FRACVAL4 - Fractional Value Register 4 */
79890 /*! @{ */
79891 
79892 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
79893 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
79894 /*! FRACVAL4 - Fractional Value 4
79895  */
79896 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
79897 /*! @} */
79898 
79899 /* The count of PWM_FRACVAL4 */
79900 #define PWM_FRACVAL4_COUNT                       (4U)
79901 
79902 /*! @name VAL4 - Value Register 4 */
79903 /*! @{ */
79904 
79905 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
79906 #define PWM_VAL4_VAL4_SHIFT                      (0U)
79907 /*! VAL4 - Value Register 4
79908  */
79909 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
79910 /*! @} */
79911 
79912 /* The count of PWM_VAL4 */
79913 #define PWM_VAL4_COUNT                           (4U)
79914 
79915 /*! @name FRACVAL5 - Fractional Value Register 5 */
79916 /*! @{ */
79917 
79918 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
79919 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
79920 /*! FRACVAL5 - Fractional Value 5
79921  */
79922 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
79923 /*! @} */
79924 
79925 /* The count of PWM_FRACVAL5 */
79926 #define PWM_FRACVAL5_COUNT                       (4U)
79927 
79928 /*! @name VAL5 - Value Register 5 */
79929 /*! @{ */
79930 
79931 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
79932 #define PWM_VAL5_VAL5_SHIFT                      (0U)
79933 /*! VAL5 - Value Register 5
79934  */
79935 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
79936 /*! @} */
79937 
79938 /* The count of PWM_VAL5 */
79939 #define PWM_VAL5_COUNT                           (4U)
79940 
79941 /*! @name FRCTRL - Fractional Control Register */
79942 /*! @{ */
79943 
79944 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
79945 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
79946 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
79947  *  0b0..Disable fractional cycle length for the PWM period.
79948  *  0b1..Enable fractional cycle length for the PWM period.
79949  */
79950 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
79951 
79952 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
79953 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
79954 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
79955  *  0b0..Disable fractional cycle placement for PWM_A.
79956  *  0b1..Enable fractional cycle placement for PWM_A.
79957  */
79958 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
79959 
79960 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
79961 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
79962 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
79963  *  0b0..Disable fractional cycle placement for PWM_B.
79964  *  0b1..Enable fractional cycle placement for PWM_B.
79965  */
79966 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
79967 
79968 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
79969 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
79970 /*! TEST - Test Status Bit
79971  */
79972 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
79973 /*! @} */
79974 
79975 /* The count of PWM_FRCTRL */
79976 #define PWM_FRCTRL_COUNT                         (4U)
79977 
79978 /*! @name OCTRL - Output Control Register */
79979 /*! @{ */
79980 
79981 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
79982 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
79983 /*! PWMXFS - PWM_X Fault State
79984  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
79985  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
79986  *  0b10, 0b11..Output is tristated.
79987  */
79988 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
79989 
79990 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
79991 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
79992 /*! PWMBFS - PWM_B Fault State
79993  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
79994  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
79995  *  0b10, 0b11..Output is tristated.
79996  */
79997 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
79998 
79999 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
80000 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
80001 /*! PWMAFS - PWM_A Fault State
80002  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
80003  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
80004  *  0b10, 0b11..Output is tristated.
80005  */
80006 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
80007 
80008 #define PWM_OCTRL_POLX_MASK                      (0x100U)
80009 #define PWM_OCTRL_POLX_SHIFT                     (8U)
80010 /*! POLX - PWM_X Output Polarity
80011  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
80012  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
80013  */
80014 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
80015 
80016 #define PWM_OCTRL_POLB_MASK                      (0x200U)
80017 #define PWM_OCTRL_POLB_SHIFT                     (9U)
80018 /*! POLB - PWM_B Output Polarity
80019  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
80020  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
80021  */
80022 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
80023 
80024 #define PWM_OCTRL_POLA_MASK                      (0x400U)
80025 #define PWM_OCTRL_POLA_SHIFT                     (10U)
80026 /*! POLA - PWM_A Output Polarity
80027  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
80028  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
80029  */
80030 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
80031 
80032 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
80033 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
80034 /*! PWMX_IN - PWM_X Input
80035  */
80036 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
80037 
80038 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
80039 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
80040 /*! PWMB_IN - PWM_B Input
80041  */
80042 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
80043 
80044 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
80045 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
80046 /*! PWMA_IN - PWM_A Input
80047  */
80048 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
80049 /*! @} */
80050 
80051 /* The count of PWM_OCTRL */
80052 #define PWM_OCTRL_COUNT                          (4U)
80053 
80054 /*! @name STS - Status Register */
80055 /*! @{ */
80056 
80057 #define PWM_STS_CMPF_MASK                        (0x3FU)
80058 #define PWM_STS_CMPF_SHIFT                       (0U)
80059 /*! CMPF - Compare Flags
80060  *  0b000000..No compare event has occurred for a particular VALx value.
80061  *  0b000001..A compare event has occurred for a particular VALx value.
80062  */
80063 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
80064 
80065 #define PWM_STS_CFX0_MASK                        (0x40U)
80066 #define PWM_STS_CFX0_SHIFT                       (6U)
80067 /*! CFX0 - Capture Flag X0
80068  */
80069 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
80070 
80071 #define PWM_STS_CFX1_MASK                        (0x80U)
80072 #define PWM_STS_CFX1_SHIFT                       (7U)
80073 /*! CFX1 - Capture Flag X1
80074  */
80075 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
80076 
80077 #define PWM_STS_CFB0_MASK                        (0x100U)
80078 #define PWM_STS_CFB0_SHIFT                       (8U)
80079 /*! CFB0 - Capture Flag B0
80080  */
80081 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
80082 
80083 #define PWM_STS_CFB1_MASK                        (0x200U)
80084 #define PWM_STS_CFB1_SHIFT                       (9U)
80085 /*! CFB1 - Capture Flag B1
80086  */
80087 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
80088 
80089 #define PWM_STS_CFA0_MASK                        (0x400U)
80090 #define PWM_STS_CFA0_SHIFT                       (10U)
80091 /*! CFA0 - Capture Flag A0
80092  */
80093 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
80094 
80095 #define PWM_STS_CFA1_MASK                        (0x800U)
80096 #define PWM_STS_CFA1_SHIFT                       (11U)
80097 /*! CFA1 - Capture Flag A1
80098  */
80099 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
80100 
80101 #define PWM_STS_RF_MASK                          (0x1000U)
80102 #define PWM_STS_RF_SHIFT                         (12U)
80103 /*! RF - Reload Flag
80104  *  0b0..No new reload cycle since last STS[RF] clearing
80105  *  0b1..New reload cycle since last STS[RF] clearing
80106  */
80107 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
80108 
80109 #define PWM_STS_REF_MASK                         (0x2000U)
80110 #define PWM_STS_REF_SHIFT                        (13U)
80111 /*! REF - Reload Error Flag
80112  *  0b0..No reload error occurred.
80113  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
80114  */
80115 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
80116 
80117 #define PWM_STS_RUF_MASK                         (0x4000U)
80118 #define PWM_STS_RUF_SHIFT                        (14U)
80119 /*! RUF - Registers Updated Flag
80120  *  0b0..No register update has occurred since last reload.
80121  *  0b1..At least one of the double buffered registers has been updated since the last reload.
80122  */
80123 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
80124 /*! @} */
80125 
80126 /* The count of PWM_STS */
80127 #define PWM_STS_COUNT                            (4U)
80128 
80129 /*! @name INTEN - Interrupt Enable Register */
80130 /*! @{ */
80131 
80132 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
80133 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
80134 /*! CMPIE - Compare Interrupt Enables
80135  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
80136  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
80137  */
80138 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
80139 
80140 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
80141 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
80142 /*! CX0IE - Capture X 0 Interrupt Enable
80143  *  0b0..Interrupt request disabled for STS[CFX0].
80144  *  0b1..Interrupt request enabled for STS[CFX0].
80145  */
80146 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
80147 
80148 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
80149 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
80150 /*! CX1IE - Capture X 1 Interrupt Enable
80151  *  0b0..Interrupt request disabled for STS[CFX1].
80152  *  0b1..Interrupt request enabled for STS[CFX1].
80153  */
80154 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
80155 
80156 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
80157 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
80158 /*! CB0IE - Capture B 0 Interrupt Enable
80159  *  0b0..Interrupt request disabled for STS[CFB0].
80160  *  0b1..Interrupt request enabled for STS[CFB0].
80161  */
80162 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
80163 
80164 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
80165 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
80166 /*! CB1IE - Capture B 1 Interrupt Enable
80167  *  0b0..Interrupt request disabled for STS[CFB1].
80168  *  0b1..Interrupt request enabled for STS[CFB1].
80169  */
80170 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
80171 
80172 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
80173 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
80174 /*! CA0IE - Capture A 0 Interrupt Enable
80175  *  0b0..Interrupt request disabled for STS[CFA0].
80176  *  0b1..Interrupt request enabled for STS[CFA0].
80177  */
80178 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
80179 
80180 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
80181 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
80182 /*! CA1IE - Capture A 1 Interrupt Enable
80183  *  0b0..Interrupt request disabled for STS[CFA1].
80184  *  0b1..Interrupt request enabled for STS[CFA1].
80185  */
80186 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
80187 
80188 #define PWM_INTEN_RIE_MASK                       (0x1000U)
80189 #define PWM_INTEN_RIE_SHIFT                      (12U)
80190 /*! RIE - Reload Interrupt Enable
80191  *  0b0..STS[RF] CPU interrupt requests disabled
80192  *  0b1..STS[RF] CPU interrupt requests enabled
80193  */
80194 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
80195 
80196 #define PWM_INTEN_REIE_MASK                      (0x2000U)
80197 #define PWM_INTEN_REIE_SHIFT                     (13U)
80198 /*! REIE - Reload Error Interrupt Enable
80199  *  0b0..STS[REF] CPU interrupt requests disabled
80200  *  0b1..STS[REF] CPU interrupt requests enabled
80201  */
80202 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
80203 /*! @} */
80204 
80205 /* The count of PWM_INTEN */
80206 #define PWM_INTEN_COUNT                          (4U)
80207 
80208 /*! @name DMAEN - DMA Enable Register */
80209 /*! @{ */
80210 
80211 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
80212 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
80213 /*! CX0DE - Capture X0 FIFO DMA Enable
80214  */
80215 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
80216 
80217 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
80218 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
80219 /*! CX1DE - Capture X1 FIFO DMA Enable
80220  */
80221 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
80222 
80223 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
80224 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
80225 /*! CB0DE - Capture B0 FIFO DMA Enable
80226  */
80227 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
80228 
80229 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
80230 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
80231 /*! CB1DE - Capture B1 FIFO DMA Enable
80232  */
80233 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
80234 
80235 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
80236 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
80237 /*! CA0DE - Capture A0 FIFO DMA Enable
80238  */
80239 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
80240 
80241 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
80242 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
80243 /*! CA1DE - Capture A1 FIFO DMA Enable
80244  */
80245 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
80246 
80247 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
80248 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
80249 /*! CAPTDE - Capture DMA Enable Source Select
80250  *  0b00..Read DMA requests disabled.
80251  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
80252  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
80253  *        which watermark(s) the DMA request is sensitive.
80254  *  0b10..A local sync (VAL1 matches counter) sets the read DMA request.
80255  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
80256  */
80257 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
80258 
80259 #define PWM_DMAEN_FAND_MASK                      (0x100U)
80260 #define PWM_DMAEN_FAND_SHIFT                     (8U)
80261 /*! FAND - FIFO Watermark AND Control
80262  *  0b0..Selected FIFO watermarks are OR'ed together.
80263  *  0b1..Selected FIFO watermarks are AND'ed together.
80264  */
80265 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
80266 
80267 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
80268 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
80269 /*! VALDE - Value Registers DMA Enable
80270  *  0b0..DMA write requests disabled
80271  *  0b1..Enabled
80272  */
80273 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
80274 /*! @} */
80275 
80276 /* The count of PWM_DMAEN */
80277 #define PWM_DMAEN_COUNT                          (4U)
80278 
80279 /*! @name TCTRL - Output Trigger Control Register */
80280 /*! @{ */
80281 
80282 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
80283 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
80284 /*! OUT_TRIG_EN - Output Trigger Enables
80285  *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
80286  *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
80287  *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
80288  *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
80289  *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
80290  *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
80291  */
80292 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
80293 
80294 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
80295 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
80296 /*! TRGFRQ - Trigger frequency
80297  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
80298  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
80299  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
80300  */
80301 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
80302 
80303 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
80304 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
80305 /*! PWBOT1 - Output Trigger 1 Source Select
80306  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
80307  *  0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
80308  */
80309 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
80310 
80311 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
80312 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
80313 /*! PWAOT0 - Output Trigger 0 Source Select
80314  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
80315  *  0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
80316  */
80317 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
80318 /*! @} */
80319 
80320 /* The count of PWM_TCTRL */
80321 #define PWM_TCTRL_COUNT                          (4U)
80322 
80323 /*! @name DISMAP - Fault Disable Mapping Register 0 */
80324 /*! @{ */
80325 
80326 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
80327 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
80328 /*! DIS0A - PWM_A Fault Disable Mask 0
80329  */
80330 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
80331 
80332 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
80333 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
80334 /*! DIS0B - PWM_B Fault Disable Mask 0
80335  */
80336 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
80337 
80338 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
80339 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
80340 /*! DIS0X - PWM_X Fault Disable Mask 0
80341  */
80342 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
80343 /*! @} */
80344 
80345 /* The count of PWM_DISMAP */
80346 #define PWM_DISMAP_COUNT                         (4U)
80347 
80348 /* The count of PWM_DISMAP */
80349 #define PWM_DISMAP_COUNT2                        (1U)
80350 
80351 /*! @name DTCNT0 - Deadtime Count Register 0 */
80352 /*! @{ */
80353 
80354 #define PWM_DTCNT0_DTCNT0_MASK                   (0xFFFFU)
80355 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
80356 /*! DTCNT0 - DTCNT0
80357  */
80358 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
80359 /*! @} */
80360 
80361 /* The count of PWM_DTCNT0 */
80362 #define PWM_DTCNT0_COUNT                         (4U)
80363 
80364 /*! @name DTCNT1 - Deadtime Count Register 1 */
80365 /*! @{ */
80366 
80367 #define PWM_DTCNT1_DTCNT1_MASK                   (0xFFFFU)
80368 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
80369 /*! DTCNT1 - DTCNT1
80370  */
80371 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
80372 /*! @} */
80373 
80374 /* The count of PWM_DTCNT1 */
80375 #define PWM_DTCNT1_COUNT                         (4U)
80376 
80377 /*! @name CAPTCTRLA - Capture Control A Register */
80378 /*! @{ */
80379 
80380 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
80381 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
80382 /*! ARMA - Arm A
80383  *  0b0..Input capture operation is disabled.
80384  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
80385  */
80386 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
80387 
80388 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
80389 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
80390 /*! ONESHOTA - One Shot Mode A
80391  *  0b0..Free Running
80392  *  0b1..One Shot
80393  */
80394 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
80395 
80396 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
80397 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
80398 /*! EDGA0 - Edge A 0
80399  *  0b00..Disabled
80400  *  0b01..Capture falling edges
80401  *  0b10..Capture rising edges
80402  *  0b11..Capture any edge
80403  */
80404 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
80405 
80406 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
80407 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
80408 /*! EDGA1 - Edge A 1
80409  *  0b00..Disabled
80410  *  0b01..Capture falling edges
80411  *  0b10..Capture rising edges
80412  *  0b11..Capture any edge
80413  */
80414 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
80415 
80416 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
80417 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
80418 /*! INP_SELA - Input Select A
80419  *  0b0..Raw PWM_A input signal selected as source.
80420  *  0b1..Edge Counter
80421  */
80422 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
80423 
80424 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
80425 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
80426 /*! EDGCNTA_EN - Edge Counter A Enable
80427  *  0b0..Edge counter disabled and held in reset
80428  *  0b1..Edge counter enabled
80429  */
80430 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
80431 
80432 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
80433 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
80434 /*! CFAWM - Capture A FIFOs Water Mark
80435  */
80436 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
80437 
80438 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
80439 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
80440 /*! CA0CNT - Capture A0 FIFO Word Count
80441  */
80442 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
80443 
80444 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
80445 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
80446 /*! CA1CNT - Capture A1 FIFO Word Count
80447  */
80448 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
80449 /*! @} */
80450 
80451 /* The count of PWM_CAPTCTRLA */
80452 #define PWM_CAPTCTRLA_COUNT                      (4U)
80453 
80454 /*! @name CAPTCOMPA - Capture Compare A Register */
80455 /*! @{ */
80456 
80457 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
80458 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
80459 /*! EDGCMPA - Edge Compare A
80460  */
80461 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
80462 
80463 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
80464 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
80465 /*! EDGCNTA - Edge Counter A
80466  */
80467 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
80468 /*! @} */
80469 
80470 /* The count of PWM_CAPTCOMPA */
80471 #define PWM_CAPTCOMPA_COUNT                      (4U)
80472 
80473 /*! @name CAPTCTRLB - Capture Control B Register */
80474 /*! @{ */
80475 
80476 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
80477 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
80478 /*! ARMB - Arm B
80479  *  0b0..Input capture operation is disabled.
80480  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
80481  */
80482 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
80483 
80484 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
80485 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
80486 /*! ONESHOTB - One Shot Mode B
80487  *  0b0..Free Running
80488  *  0b1..One Shot
80489  */
80490 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
80491 
80492 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
80493 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
80494 /*! EDGB0 - Edge B 0
80495  *  0b00..Disabled
80496  *  0b01..Capture falling edges
80497  *  0b10..Capture rising edges
80498  *  0b11..Capture any edge
80499  */
80500 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
80501 
80502 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
80503 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
80504 /*! EDGB1 - Edge B 1
80505  *  0b00..Disabled
80506  *  0b01..Capture falling edges
80507  *  0b10..Capture rising edges
80508  *  0b11..Capture any edge
80509  */
80510 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
80511 
80512 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
80513 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
80514 /*! INP_SELB - Input Select B
80515  *  0b0..Raw PWM_B input signal selected as source.
80516  *  0b1..Edge Counter
80517  */
80518 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
80519 
80520 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
80521 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
80522 /*! EDGCNTB_EN - Edge Counter B Enable
80523  *  0b0..Edge counter disabled and held in reset
80524  *  0b1..Edge counter enabled
80525  */
80526 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
80527 
80528 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
80529 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
80530 /*! CFBWM - Capture B FIFOs Water Mark
80531  */
80532 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
80533 
80534 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
80535 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
80536 /*! CB0CNT - Capture B0 FIFO Word Count
80537  */
80538 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
80539 
80540 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
80541 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
80542 /*! CB1CNT - Capture B1 FIFO Word Count
80543  */
80544 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
80545 /*! @} */
80546 
80547 /* The count of PWM_CAPTCTRLB */
80548 #define PWM_CAPTCTRLB_COUNT                      (4U)
80549 
80550 /*! @name CAPTCOMPB - Capture Compare B Register */
80551 /*! @{ */
80552 
80553 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
80554 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
80555 /*! EDGCMPB - Edge Compare B
80556  */
80557 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
80558 
80559 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
80560 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
80561 /*! EDGCNTB - Edge Counter B
80562  */
80563 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
80564 /*! @} */
80565 
80566 /* The count of PWM_CAPTCOMPB */
80567 #define PWM_CAPTCOMPB_COUNT                      (4U)
80568 
80569 /*! @name CAPTCTRLX - Capture Control X Register */
80570 /*! @{ */
80571 
80572 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
80573 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
80574 /*! ARMX - Arm X
80575  *  0b0..Input capture operation is disabled.
80576  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
80577  */
80578 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
80579 
80580 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
80581 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
80582 /*! ONESHOTX - One Shot Mode Aux
80583  *  0b0..Free Running
80584  *  0b1..One Shot
80585  */
80586 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
80587 
80588 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
80589 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
80590 /*! EDGX0 - Edge X 0
80591  *  0b00..Disabled
80592  *  0b01..Capture falling edges
80593  *  0b10..Capture rising edges
80594  *  0b11..Capture any edge
80595  */
80596 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
80597 
80598 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
80599 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
80600 /*! EDGX1 - Edge X 1
80601  *  0b00..Disabled
80602  *  0b01..Capture falling edges
80603  *  0b10..Capture rising edges
80604  *  0b11..Capture any edge
80605  */
80606 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
80607 
80608 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
80609 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
80610 /*! INP_SELX - Input Select X
80611  *  0b0..Raw PWM_X input signal selected as source.
80612  *  0b1..Edge Counter
80613  */
80614 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
80615 
80616 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
80617 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
80618 /*! EDGCNTX_EN - Edge Counter X Enable
80619  *  0b0..Edge counter disabled and held in reset
80620  *  0b1..Edge counter enabled
80621  */
80622 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
80623 
80624 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
80625 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
80626 /*! CFXWM - Capture X FIFOs Water Mark
80627  */
80628 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
80629 
80630 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
80631 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
80632 /*! CX0CNT - Capture X0 FIFO Word Count
80633  */
80634 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
80635 
80636 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
80637 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
80638 /*! CX1CNT - Capture X1 FIFO Word Count
80639  */
80640 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
80641 /*! @} */
80642 
80643 /* The count of PWM_CAPTCTRLX */
80644 #define PWM_CAPTCTRLX_COUNT                      (4U)
80645 
80646 /*! @name CAPTCOMPX - Capture Compare X Register */
80647 /*! @{ */
80648 
80649 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
80650 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
80651 /*! EDGCMPX - Edge Compare X
80652  */
80653 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
80654 
80655 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
80656 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
80657 /*! EDGCNTX - Edge Counter X
80658  */
80659 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
80660 /*! @} */
80661 
80662 /* The count of PWM_CAPTCOMPX */
80663 #define PWM_CAPTCOMPX_COUNT                      (4U)
80664 
80665 /*! @name CVAL0 - Capture Value 0 Register */
80666 /*! @{ */
80667 
80668 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
80669 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
80670 /*! CAPTVAL0 - CAPTVAL0
80671  */
80672 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
80673 /*! @} */
80674 
80675 /* The count of PWM_CVAL0 */
80676 #define PWM_CVAL0_COUNT                          (4U)
80677 
80678 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
80679 /*! @{ */
80680 
80681 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
80682 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
80683 /*! CVAL0CYC - CVAL0CYC
80684  */
80685 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
80686 /*! @} */
80687 
80688 /* The count of PWM_CVAL0CYC */
80689 #define PWM_CVAL0CYC_COUNT                       (4U)
80690 
80691 /*! @name CVAL1 - Capture Value 1 Register */
80692 /*! @{ */
80693 
80694 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
80695 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
80696 /*! CAPTVAL1 - CAPTVAL1
80697  */
80698 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
80699 /*! @} */
80700 
80701 /* The count of PWM_CVAL1 */
80702 #define PWM_CVAL1_COUNT                          (4U)
80703 
80704 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
80705 /*! @{ */
80706 
80707 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
80708 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
80709 /*! CVAL1CYC - CVAL1CYC
80710  */
80711 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
80712 /*! @} */
80713 
80714 /* The count of PWM_CVAL1CYC */
80715 #define PWM_CVAL1CYC_COUNT                       (4U)
80716 
80717 /*! @name CVAL2 - Capture Value 2 Register */
80718 /*! @{ */
80719 
80720 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
80721 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
80722 /*! CAPTVAL2 - CAPTVAL2
80723  */
80724 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
80725 /*! @} */
80726 
80727 /* The count of PWM_CVAL2 */
80728 #define PWM_CVAL2_COUNT                          (4U)
80729 
80730 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
80731 /*! @{ */
80732 
80733 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
80734 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
80735 /*! CVAL2CYC - CVAL2CYC
80736  */
80737 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
80738 /*! @} */
80739 
80740 /* The count of PWM_CVAL2CYC */
80741 #define PWM_CVAL2CYC_COUNT                       (4U)
80742 
80743 /*! @name CVAL3 - Capture Value 3 Register */
80744 /*! @{ */
80745 
80746 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
80747 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
80748 /*! CAPTVAL3 - CAPTVAL3
80749  */
80750 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
80751 /*! @} */
80752 
80753 /* The count of PWM_CVAL3 */
80754 #define PWM_CVAL3_COUNT                          (4U)
80755 
80756 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
80757 /*! @{ */
80758 
80759 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
80760 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
80761 /*! CVAL3CYC - CVAL3CYC
80762  */
80763 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
80764 /*! @} */
80765 
80766 /* The count of PWM_CVAL3CYC */
80767 #define PWM_CVAL3CYC_COUNT                       (4U)
80768 
80769 /*! @name CVAL4 - Capture Value 4 Register */
80770 /*! @{ */
80771 
80772 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
80773 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
80774 /*! CAPTVAL4 - CAPTVAL4
80775  */
80776 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
80777 /*! @} */
80778 
80779 /* The count of PWM_CVAL4 */
80780 #define PWM_CVAL4_COUNT                          (4U)
80781 
80782 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
80783 /*! @{ */
80784 
80785 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
80786 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
80787 /*! CVAL4CYC - CVAL4CYC
80788  */
80789 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
80790 /*! @} */
80791 
80792 /* The count of PWM_CVAL4CYC */
80793 #define PWM_CVAL4CYC_COUNT                       (4U)
80794 
80795 /*! @name CVAL5 - Capture Value 5 Register */
80796 /*! @{ */
80797 
80798 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
80799 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
80800 /*! CAPTVAL5 - CAPTVAL5
80801  */
80802 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
80803 /*! @} */
80804 
80805 /* The count of PWM_CVAL5 */
80806 #define PWM_CVAL5_COUNT                          (4U)
80807 
80808 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
80809 /*! @{ */
80810 
80811 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
80812 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
80813 /*! CVAL5CYC - CVAL5CYC
80814  */
80815 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
80816 /*! @} */
80817 
80818 /* The count of PWM_CVAL5CYC */
80819 #define PWM_CVAL5CYC_COUNT                       (4U)
80820 
80821 /*! @name OUTEN - Output Enable Register */
80822 /*! @{ */
80823 
80824 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
80825 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
80826 /*! PWMX_EN - PWM_X Output Enables
80827  *  0b0000..PWM_X output disabled.
80828  *  0b0001..PWM_X output enabled.
80829  */
80830 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
80831 
80832 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
80833 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
80834 /*! PWMB_EN - PWM_B Output Enables
80835  *  0b0000..PWM_B output disabled.
80836  *  0b0001..PWM_B output enabled.
80837  */
80838 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
80839 
80840 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
80841 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
80842 /*! PWMA_EN - PWM_A Output Enables
80843  *  0b0000..PWM_A output disabled.
80844  *  0b0001..PWM_A output enabled.
80845  */
80846 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
80847 /*! @} */
80848 
80849 /*! @name MASK - Mask Register */
80850 /*! @{ */
80851 
80852 #define PWM_MASK_MASKX_MASK                      (0xFU)
80853 #define PWM_MASK_MASKX_SHIFT                     (0U)
80854 /*! MASKX - PWM_X Masks
80855  *  0b0000..PWM_X output normal.
80856  *  0b0001..PWM_X output masked.
80857  */
80858 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
80859 
80860 #define PWM_MASK_MASKB_MASK                      (0xF0U)
80861 #define PWM_MASK_MASKB_SHIFT                     (4U)
80862 /*! MASKB - PWM_B Masks
80863  *  0b0000..PWM_B output normal.
80864  *  0b0001..PWM_B output masked.
80865  */
80866 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
80867 
80868 #define PWM_MASK_MASKA_MASK                      (0xF00U)
80869 #define PWM_MASK_MASKA_SHIFT                     (8U)
80870 /*! MASKA - PWM_A Masks
80871  *  0b0000..PWM_A output normal.
80872  *  0b0001..PWM_A output masked.
80873  */
80874 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
80875 /*! @} */
80876 
80877 /*! @name SWCOUT - Software Controlled Output Register */
80878 /*! @{ */
80879 
80880 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
80881 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
80882 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
80883  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
80884  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
80885  */
80886 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
80887 
80888 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
80889 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
80890 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
80891  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
80892  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
80893  */
80894 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
80895 
80896 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
80897 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
80898 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
80899  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
80900  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
80901  */
80902 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
80903 
80904 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
80905 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
80906 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
80907  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
80908  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
80909  */
80910 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
80911 
80912 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
80913 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
80914 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
80915  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
80916  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
80917  */
80918 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
80919 
80920 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
80921 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
80922 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
80923  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
80924  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
80925  */
80926 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
80927 
80928 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
80929 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
80930 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
80931  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
80932  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
80933  */
80934 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
80935 
80936 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
80937 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
80938 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
80939  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
80940  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
80941  */
80942 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
80943 /*! @} */
80944 
80945 /*! @name DTSRCSEL - PWM Source Select Register */
80946 /*! @{ */
80947 
80948 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
80949 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
80950 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
80951  *  0b00..Generated SM0PWM45 signal is used by the deadtime logic.
80952  *  0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
80953  *  0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
80954  *  0b11..PWM0_EXTB signal is used by the deadtime logic.
80955  */
80956 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
80957 
80958 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
80959 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
80960 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
80961  *  0b00..Generated SM0PWM23 signal is used by the deadtime logic.
80962  *  0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
80963  *  0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
80964  *  0b11..PWM0_EXTA signal is used by the deadtime logic.
80965  */
80966 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
80967 
80968 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
80969 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
80970 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
80971  *  0b00..Generated SM1PWM45 signal is used by the deadtime logic.
80972  *  0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
80973  *  0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
80974  *  0b11..PWM1_EXTB signal is used by the deadtime logic.
80975  */
80976 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
80977 
80978 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
80979 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
80980 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
80981  *  0b00..Generated SM1PWM23 signal is used by the deadtime logic.
80982  *  0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
80983  *  0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
80984  *  0b11..PWM1_EXTA signal is used by the deadtime logic.
80985  */
80986 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
80987 
80988 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
80989 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
80990 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
80991  *  0b00..Generated SM2PWM45 signal is used by the deadtime logic.
80992  *  0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
80993  *  0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
80994  *  0b11..PWM2_EXTB signal is used by the deadtime logic.
80995  */
80996 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
80997 
80998 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
80999 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
81000 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
81001  *  0b00..Generated SM2PWM23 signal is used by the deadtime logic.
81002  *  0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
81003  *  0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
81004  *  0b11..PWM2_EXTA signal is used by the deadtime logic.
81005  */
81006 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
81007 
81008 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
81009 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
81010 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
81011  *  0b00..Generated SM3PWM45 signal is used by the deadtime logic.
81012  *  0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
81013  *  0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
81014  *  0b11..PWM3_EXTB signal is used by the deadtime logic.
81015  */
81016 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
81017 
81018 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
81019 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
81020 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
81021  *  0b00..Generated SM3PWM23 signal is used by the deadtime logic.
81022  *  0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
81023  *  0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
81024  *  0b11..PWM3_EXTA signal is used by the deadtime logic.
81025  */
81026 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
81027 /*! @} */
81028 
81029 /*! @name MCTRL - Master Control Register */
81030 /*! @{ */
81031 
81032 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
81033 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
81034 /*! LDOK - Load Okay
81035  *  0b0000..Do not load new values.
81036  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
81037  */
81038 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
81039 
81040 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
81041 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
81042 /*! CLDOK - Clear Load Okay
81043  */
81044 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
81045 
81046 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
81047 #define PWM_MCTRL_RUN_SHIFT                      (8U)
81048 /*! RUN - Run
81049  *  0b0000..PWM counter is stopped, but PWM outputs will hold the current state.
81050  *  0b0001..PWM counter is started in the corresponding submodule.
81051  */
81052 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
81053 
81054 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
81055 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
81056 /*! IPOL - Current Polarity
81057  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
81058  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
81059  */
81060 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
81061 /*! @} */
81062 
81063 /*! @name MCTRL2 - Master Control 2 Register */
81064 /*! @{ */
81065 
81066 #define PWM_MCTRL2_MONPLL_MASK                   (0x3U)
81067 #define PWM_MCTRL2_MONPLL_SHIFT                  (0U)
81068 /*! MONPLL - Monitor PLL State
81069  *  0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
81070  *  0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
81071  *  0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
81072  *        will be controlled by software. These bits are write protected until the next reset.
81073  *  0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
81074  *        encounters problems. These bits are write protected until the next reset.
81075  */
81076 #define PWM_MCTRL2_MONPLL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
81077 /*! @} */
81078 
81079 /*! @name FCTRL - Fault Control Register */
81080 /*! @{ */
81081 
81082 #define PWM_FCTRL_FIE_MASK                       (0xFU)
81083 #define PWM_FCTRL_FIE_SHIFT                      (0U)
81084 /*! FIE - Fault Interrupt Enables
81085  *  0b0000..FAULTx CPU interrupt requests disabled.
81086  *  0b0001..FAULTx CPU interrupt requests enabled.
81087  */
81088 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
81089 
81090 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
81091 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
81092 /*! FSAFE - Fault Safety Mode
81093  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
81094  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
81095  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be
81096  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
81097  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
81098  *          DISMAPn).
81099  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
81100  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
81101  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
81102  */
81103 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
81104 
81105 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
81106 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
81107 /*! FAUTO - Automatic Fault Clearing
81108  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
81109  *          at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If
81110  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by
81111  *          FCTRL[FSAFE].
81112  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
81113  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
81114  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
81115  *          cannot be cleared.
81116  */
81117 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
81118 
81119 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
81120 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
81121 /*! FLVL - Fault Level
81122  *  0b0000..A logic 0 on the fault input indicates a fault condition.
81123  *  0b0001..A logic 1 on the fault input indicates a fault condition.
81124  */
81125 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
81126 /*! @} */
81127 
81128 /*! @name FSTS - Fault Status Register */
81129 /*! @{ */
81130 
81131 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
81132 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
81133 /*! FFLAG - Fault Flags
81134  *  0b0000..No fault on the FAULTx pin.
81135  *  0b0001..Fault on the FAULTx pin.
81136  */
81137 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
81138 
81139 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
81140 #define PWM_FSTS_FFULL_SHIFT                     (4U)
81141 /*! FFULL - Full Cycle
81142  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
81143  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
81144  */
81145 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
81146 
81147 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
81148 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
81149 /*! FFPIN - Filtered Fault Pins
81150  */
81151 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
81152 
81153 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
81154 #define PWM_FSTS_FHALF_SHIFT                     (12U)
81155 /*! FHALF - Half Cycle Fault Recovery
81156  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
81157  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
81158  */
81159 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
81160 /*! @} */
81161 
81162 /*! @name FFILT - Fault Filter Register */
81163 /*! @{ */
81164 
81165 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
81166 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
81167 /*! FILT_PER - Fault Filter Period
81168  */
81169 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
81170 
81171 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
81172 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
81173 /*! FILT_CNT - Fault Filter Count
81174  */
81175 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
81176 
81177 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
81178 #define PWM_FFILT_GSTR_SHIFT                     (15U)
81179 /*! GSTR - Fault Glitch Stretch Enable
81180  *  0b0..Fault input glitch stretching is disabled.
81181  *  0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
81182  */
81183 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
81184 /*! @} */
81185 
81186 /*! @name FTST - Fault Test Register */
81187 /*! @{ */
81188 
81189 #define PWM_FTST_FTEST_MASK                      (0x1U)
81190 #define PWM_FTST_FTEST_SHIFT                     (0U)
81191 /*! FTEST - Fault Test
81192  *  0b0..No fault
81193  *  0b1..Cause a simulated fault
81194  */
81195 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
81196 /*! @} */
81197 
81198 /*! @name FCTRL2 - Fault Control 2 Register */
81199 /*! @{ */
81200 
81201 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
81202 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
81203 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
81204  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
81205  *          with the filtered and latched fault signals to disable the PWM outputs.
81206  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
81207  *          and latched fault signals are used to disable the PWM outputs.
81208  */
81209 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
81210 /*! @} */
81211 
81212 
81213 /*!
81214  * @}
81215  */ /* end of group PWM_Register_Masks */
81216 
81217 
81218 /* PWM - Peripheral instance base addresses */
81219 /** Peripheral PWM1 base address */
81220 #define PWM1_BASE                                (0x4018C000u)
81221 /** Peripheral PWM1 base pointer */
81222 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
81223 /** Peripheral PWM2 base address */
81224 #define PWM2_BASE                                (0x40190000u)
81225 /** Peripheral PWM2 base pointer */
81226 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
81227 /** Peripheral PWM3 base address */
81228 #define PWM3_BASE                                (0x40194000u)
81229 /** Peripheral PWM3 base pointer */
81230 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
81231 /** Peripheral PWM4 base address */
81232 #define PWM4_BASE                                (0x40198000u)
81233 /** Peripheral PWM4 base pointer */
81234 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
81235 /** Array initializer of PWM peripheral base addresses */
81236 #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
81237 /** Array initializer of PWM peripheral base pointers */
81238 #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
81239 /** Interrupt vectors for the PWM peripheral type */
81240 #define PWM_CMP_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
81241 #define PWM_RELOAD_IRQS                          { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
81242 #define PWM_CAPTURE_IRQS                         { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
81243 #define PWM_FAULT_IRQS                           { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
81244 #define PWM_RELOAD_ERROR_IRQS                    { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
81245 
81246 /*!
81247  * @}
81248  */ /* end of group PWM_Peripheral_Access_Layer */
81249 
81250 
81251 /* ----------------------------------------------------------------------------
81252    -- PXP Peripheral Access Layer
81253    ---------------------------------------------------------------------------- */
81254 
81255 /*!
81256  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
81257  * @{
81258  */
81259 
81260 /** PXP - Register Layout Typedef */
81261 typedef struct {
81262   __IO uint32_t CTRL;                              /**< Control Register 0, offset: 0x0 */
81263   __IO uint32_t CTRL_SET;                          /**< Control Register 0, offset: 0x4 */
81264   __IO uint32_t CTRL_CLR;                          /**< Control Register 0, offset: 0x8 */
81265   __IO uint32_t CTRL_TOG;                          /**< Control Register 0, offset: 0xC */
81266   __IO uint32_t STAT;                              /**< Status Register, offset: 0x10 */
81267   __IO uint32_t STAT_SET;                          /**< Status Register, offset: 0x14 */
81268   __IO uint32_t STAT_CLR;                          /**< Status Register, offset: 0x18 */
81269   __IO uint32_t STAT_TOG;                          /**< Status Register, offset: 0x1C */
81270   __IO uint32_t OUT_CTRL;                          /**< Output Buffer Control Register, offset: 0x20 */
81271   __IO uint32_t OUT_CTRL_SET;                      /**< Output Buffer Control Register, offset: 0x24 */
81272   __IO uint32_t OUT_CTRL_CLR;                      /**< Output Buffer Control Register, offset: 0x28 */
81273   __IO uint32_t OUT_CTRL_TOG;                      /**< Output Buffer Control Register, offset: 0x2C */
81274   __IO uint32_t OUT_BUF;                           /**< Output Frame Buffer Pointer, offset: 0x30 */
81275        uint8_t RESERVED_0[12];
81276   __IO uint32_t OUT_BUF2;                          /**< Output Frame Buffer Pointer #2, offset: 0x40 */
81277        uint8_t RESERVED_1[12];
81278   __IO uint32_t OUT_PITCH;                         /**< Output Buffer Pitch, offset: 0x50 */
81279        uint8_t RESERVED_2[12];
81280   __IO uint32_t OUT_LRC;                           /**< Output Surface Lower Right Coordinate, offset: 0x60 */
81281        uint8_t RESERVED_3[12];
81282   __IO uint32_t OUT_PS_ULC;                        /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
81283        uint8_t RESERVED_4[12];
81284   __IO uint32_t OUT_PS_LRC;                        /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
81285        uint8_t RESERVED_5[12];
81286   __IO uint32_t OUT_AS_ULC;                        /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
81287        uint8_t RESERVED_6[12];
81288   __IO uint32_t OUT_AS_LRC;                        /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
81289        uint8_t RESERVED_7[12];
81290   __IO uint32_t PS_CTRL;                           /**< Processed Surface (PS) Control Register, offset: 0xB0 */
81291   __IO uint32_t PS_CTRL_SET;                       /**< Processed Surface (PS) Control Register, offset: 0xB4 */
81292   __IO uint32_t PS_CTRL_CLR;                       /**< Processed Surface (PS) Control Register, offset: 0xB8 */
81293   __IO uint32_t PS_CTRL_TOG;                       /**< Processed Surface (PS) Control Register, offset: 0xBC */
81294   __IO uint32_t PS_BUF;                            /**< PS Input Buffer Address, offset: 0xC0 */
81295        uint8_t RESERVED_8[12];
81296   __IO uint32_t PS_UBUF;                           /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
81297        uint8_t RESERVED_9[12];
81298   __IO uint32_t PS_VBUF;                           /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
81299        uint8_t RESERVED_10[12];
81300   __IO uint32_t PS_PITCH;                          /**< Processed Surface Pitch, offset: 0xF0 */
81301        uint8_t RESERVED_11[12];
81302   __IO uint32_t PS_BACKGROUND;                     /**< PS Background Color, offset: 0x100 */
81303        uint8_t RESERVED_12[12];
81304   __IO uint32_t PS_SCALE;                          /**< PS Scale Factor Register, offset: 0x110 */
81305        uint8_t RESERVED_13[12];
81306   __IO uint32_t PS_OFFSET;                         /**< PS Scale Offset Register, offset: 0x120 */
81307        uint8_t RESERVED_14[12];
81308   __IO uint32_t PS_CLRKEYLOW;                      /**< PS Color Key Low, offset: 0x130 */
81309        uint8_t RESERVED_15[12];
81310   __IO uint32_t PS_CLRKEYHIGH;                     /**< PS Color Key High, offset: 0x140 */
81311        uint8_t RESERVED_16[12];
81312   __IO uint32_t AS_CTRL;                           /**< Alpha Surface Control, offset: 0x150 */
81313        uint8_t RESERVED_17[12];
81314   __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x160 */
81315        uint8_t RESERVED_18[12];
81316   __IO uint32_t AS_PITCH;                          /**< Alpha Surface Pitch, offset: 0x170 */
81317        uint8_t RESERVED_19[12];
81318   __IO uint32_t AS_CLRKEYLOW;                      /**< Overlay Color Key Low, offset: 0x180 */
81319        uint8_t RESERVED_20[12];
81320   __IO uint32_t AS_CLRKEYHIGH;                     /**< Overlay Color Key High, offset: 0x190 */
81321        uint8_t RESERVED_21[12];
81322   __IO uint32_t CSC1_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
81323        uint8_t RESERVED_22[12];
81324   __IO uint32_t CSC1_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
81325        uint8_t RESERVED_23[12];
81326   __IO uint32_t CSC1_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
81327        uint8_t RESERVED_24[348];
81328   __IO uint32_t POWER;                             /**< PXP Power Control Register, offset: 0x320 */
81329        uint8_t RESERVED_25[220];
81330   __IO uint32_t NEXT;                              /**< Next Frame Pointer, offset: 0x400 */
81331        uint8_t RESERVED_26[60];
81332   __IO uint32_t PORTER_DUFF_CTRL;                  /**< PXP Alpha Engine A Control Register., offset: 0x440 */
81333 } PXP_Type;
81334 
81335 /* ----------------------------------------------------------------------------
81336    -- PXP Register Masks
81337    ---------------------------------------------------------------------------- */
81338 
81339 /*!
81340  * @addtogroup PXP_Register_Masks PXP Register Masks
81341  * @{
81342  */
81343 
81344 /*! @name CTRL - Control Register 0 */
81345 /*! @{ */
81346 
81347 #define PXP_CTRL_ENABLE_MASK                     (0x1U)
81348 #define PXP_CTRL_ENABLE_SHIFT                    (0U)
81349 /*! ENABLE
81350  *  0b1..PXP is enabled
81351  *  0b0..PXP is disabled
81352  */
81353 #define PXP_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
81354 
81355 #define PXP_CTRL_IRQ_ENABLE_MASK                 (0x2U)
81356 #define PXP_CTRL_IRQ_ENABLE_SHIFT                (1U)
81357 /*! IRQ_ENABLE
81358  *  0b1..PXP interrupt is enabled
81359  *  0b0..PXP interrupt is disabled
81360  */
81361 #define PXP_CTRL_IRQ_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
81362 
81363 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            (0x4U)
81364 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           (2U)
81365 /*! NEXT_IRQ_ENABLE
81366  *  0b0..Disabled
81367  *  0b1..Enabled
81368  */
81369 #define PXP_CTRL_NEXT_IRQ_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
81370 
81371 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK       (0x10U)
81372 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT      (4U)
81373 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
81374 
81375 #define PXP_CTRL_ROTATE_MASK                     (0x300U)
81376 #define PXP_CTRL_ROTATE_SHIFT                    (8U)
81377 /*! ROTATE
81378  *  0b00..ROT_0
81379  *  0b01..ROT_90
81380  *  0b10..ROT_180
81381  *  0b11..ROT_270
81382  */
81383 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
81384 
81385 #define PXP_CTRL_HFLIP_MASK                      (0x400U)
81386 #define PXP_CTRL_HFLIP_SHIFT                     (10U)
81387 /*! HFLIP
81388  *  0b0..Horizontal Flip is disabled
81389  *  0b1..Horizontal Flip is enabled
81390  */
81391 #define PXP_CTRL_HFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
81392 
81393 #define PXP_CTRL_VFLIP_MASK                      (0x800U)
81394 #define PXP_CTRL_VFLIP_SHIFT                     (11U)
81395 /*! VFLIP
81396  *  0b0..Vertical Flip is disabled
81397  *  0b1..Vertical Flip is enabled
81398  */
81399 #define PXP_CTRL_VFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
81400 
81401 #define PXP_CTRL_ROT_POS_MASK                    (0x400000U)
81402 #define PXP_CTRL_ROT_POS_SHIFT                   (22U)
81403 #define PXP_CTRL_ROT_POS(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
81404 
81405 #define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
81406 #define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
81407 /*! BLOCK_SIZE
81408  *  0b0..Process 8x8 pixel blocks.
81409  *  0b1..Process 16x16 pixel blocks.
81410  */
81411 #define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
81412 
81413 #define PXP_CTRL_EN_REPEAT_MASK                  (0x10000000U)
81414 #define PXP_CTRL_EN_REPEAT_SHIFT                 (28U)
81415 /*! EN_REPEAT
81416  *  0b1..PXP will repeat based on the current configuration register settings
81417  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81418  */
81419 #define PXP_CTRL_EN_REPEAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
81420 
81421 #define PXP_CTRL_CLKGATE_MASK                    (0x40000000U)
81422 #define PXP_CTRL_CLKGATE_SHIFT                   (30U)
81423 /*! CLKGATE
81424  *  0b0..Normal operation
81425  *  0b1..All clocks to PXP is gated-off
81426  */
81427 #define PXP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
81428 
81429 #define PXP_CTRL_SFTRST_MASK                     (0x80000000U)
81430 #define PXP_CTRL_SFTRST_SHIFT                    (31U)
81431 /*! SFTRST
81432  *  0b0..Normal PXP operation is enabled
81433  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81434  */
81435 #define PXP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
81436 /*! @} */
81437 
81438 /*! @name CTRL_SET - Control Register 0 */
81439 /*! @{ */
81440 
81441 #define PXP_CTRL_SET_ENABLE_MASK                 (0x1U)
81442 #define PXP_CTRL_SET_ENABLE_SHIFT                (0U)
81443 /*! ENABLE
81444  *  0b1..PXP is enabled
81445  *  0b0..PXP is disabled
81446  */
81447 #define PXP_CTRL_SET_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
81448 
81449 #define PXP_CTRL_SET_IRQ_ENABLE_MASK             (0x2U)
81450 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT            (1U)
81451 /*! IRQ_ENABLE
81452  *  0b1..PXP interrupt is enabled
81453  *  0b0..PXP interrupt is disabled
81454  */
81455 #define PXP_CTRL_SET_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
81456 
81457 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK        (0x4U)
81458 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT       (2U)
81459 /*! NEXT_IRQ_ENABLE
81460  *  0b0..Disabled
81461  *  0b1..Enabled
81462  */
81463 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
81464 
81465 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81466 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81467 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
81468 
81469 #define PXP_CTRL_SET_ROTATE_MASK                 (0x300U)
81470 #define PXP_CTRL_SET_ROTATE_SHIFT                (8U)
81471 /*! ROTATE
81472  *  0b00..ROT_0
81473  *  0b01..ROT_90
81474  *  0b10..ROT_180
81475  *  0b11..ROT_270
81476  */
81477 #define PXP_CTRL_SET_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
81478 
81479 #define PXP_CTRL_SET_HFLIP_MASK                  (0x400U)
81480 #define PXP_CTRL_SET_HFLIP_SHIFT                 (10U)
81481 /*! HFLIP
81482  *  0b0..Horizontal Flip is disabled
81483  *  0b1..Horizontal Flip is enabled
81484  */
81485 #define PXP_CTRL_SET_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
81486 
81487 #define PXP_CTRL_SET_VFLIP_MASK                  (0x800U)
81488 #define PXP_CTRL_SET_VFLIP_SHIFT                 (11U)
81489 /*! VFLIP
81490  *  0b0..Vertical Flip is disabled
81491  *  0b1..Vertical Flip is enabled
81492  */
81493 #define PXP_CTRL_SET_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
81494 
81495 #define PXP_CTRL_SET_ROT_POS_MASK                (0x400000U)
81496 #define PXP_CTRL_SET_ROT_POS_SHIFT               (22U)
81497 #define PXP_CTRL_SET_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
81498 
81499 #define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
81500 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
81501 /*! BLOCK_SIZE
81502  *  0b0..Process 8x8 pixel blocks.
81503  *  0b1..Process 16x16 pixel blocks.
81504  */
81505 #define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
81506 
81507 #define PXP_CTRL_SET_EN_REPEAT_MASK              (0x10000000U)
81508 #define PXP_CTRL_SET_EN_REPEAT_SHIFT             (28U)
81509 /*! EN_REPEAT
81510  *  0b1..PXP will repeat based on the current configuration register settings
81511  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81512  */
81513 #define PXP_CTRL_SET_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
81514 
81515 #define PXP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
81516 #define PXP_CTRL_SET_CLKGATE_SHIFT               (30U)
81517 /*! CLKGATE
81518  *  0b0..Normal operation
81519  *  0b1..All clocks to PXP is gated-off
81520  */
81521 #define PXP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
81522 
81523 #define PXP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
81524 #define PXP_CTRL_SET_SFTRST_SHIFT                (31U)
81525 /*! SFTRST
81526  *  0b0..Normal PXP operation is enabled
81527  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81528  */
81529 #define PXP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
81530 /*! @} */
81531 
81532 /*! @name CTRL_CLR - Control Register 0 */
81533 /*! @{ */
81534 
81535 #define PXP_CTRL_CLR_ENABLE_MASK                 (0x1U)
81536 #define PXP_CTRL_CLR_ENABLE_SHIFT                (0U)
81537 /*! ENABLE
81538  *  0b1..PXP is enabled
81539  *  0b0..PXP is disabled
81540  */
81541 #define PXP_CTRL_CLR_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
81542 
81543 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK             (0x2U)
81544 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT            (1U)
81545 /*! IRQ_ENABLE
81546  *  0b1..PXP interrupt is enabled
81547  *  0b0..PXP interrupt is disabled
81548  */
81549 #define PXP_CTRL_CLR_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
81550 
81551 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK        (0x4U)
81552 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT       (2U)
81553 /*! NEXT_IRQ_ENABLE
81554  *  0b0..Disabled
81555  *  0b1..Enabled
81556  */
81557 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
81558 
81559 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81560 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81561 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
81562 
81563 #define PXP_CTRL_CLR_ROTATE_MASK                 (0x300U)
81564 #define PXP_CTRL_CLR_ROTATE_SHIFT                (8U)
81565 /*! ROTATE
81566  *  0b00..ROT_0
81567  *  0b01..ROT_90
81568  *  0b10..ROT_180
81569  *  0b11..ROT_270
81570  */
81571 #define PXP_CTRL_CLR_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
81572 
81573 #define PXP_CTRL_CLR_HFLIP_MASK                  (0x400U)
81574 #define PXP_CTRL_CLR_HFLIP_SHIFT                 (10U)
81575 /*! HFLIP
81576  *  0b0..Horizontal Flip is disabled
81577  *  0b1..Horizontal Flip is enabled
81578  */
81579 #define PXP_CTRL_CLR_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
81580 
81581 #define PXP_CTRL_CLR_VFLIP_MASK                  (0x800U)
81582 #define PXP_CTRL_CLR_VFLIP_SHIFT                 (11U)
81583 /*! VFLIP
81584  *  0b0..Vertical Flip is disabled
81585  *  0b1..Vertical Flip is enabled
81586  */
81587 #define PXP_CTRL_CLR_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
81588 
81589 #define PXP_CTRL_CLR_ROT_POS_MASK                (0x400000U)
81590 #define PXP_CTRL_CLR_ROT_POS_SHIFT               (22U)
81591 #define PXP_CTRL_CLR_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
81592 
81593 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
81594 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
81595 /*! BLOCK_SIZE
81596  *  0b0..Process 8x8 pixel blocks.
81597  *  0b1..Process 16x16 pixel blocks.
81598  */
81599 #define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
81600 
81601 #define PXP_CTRL_CLR_EN_REPEAT_MASK              (0x10000000U)
81602 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT             (28U)
81603 /*! EN_REPEAT
81604  *  0b1..PXP will repeat based on the current configuration register settings
81605  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81606  */
81607 #define PXP_CTRL_CLR_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
81608 
81609 #define PXP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
81610 #define PXP_CTRL_CLR_CLKGATE_SHIFT               (30U)
81611 /*! CLKGATE
81612  *  0b0..Normal operation
81613  *  0b1..All clocks to PXP is gated-off
81614  */
81615 #define PXP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
81616 
81617 #define PXP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
81618 #define PXP_CTRL_CLR_SFTRST_SHIFT                (31U)
81619 /*! SFTRST
81620  *  0b0..Normal PXP operation is enabled
81621  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81622  */
81623 #define PXP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
81624 /*! @} */
81625 
81626 /*! @name CTRL_TOG - Control Register 0 */
81627 /*! @{ */
81628 
81629 #define PXP_CTRL_TOG_ENABLE_MASK                 (0x1U)
81630 #define PXP_CTRL_TOG_ENABLE_SHIFT                (0U)
81631 /*! ENABLE
81632  *  0b1..PXP is enabled
81633  *  0b0..PXP is disabled
81634  */
81635 #define PXP_CTRL_TOG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
81636 
81637 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK             (0x2U)
81638 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT            (1U)
81639 /*! IRQ_ENABLE
81640  *  0b1..PXP interrupt is enabled
81641  *  0b0..PXP interrupt is disabled
81642  */
81643 #define PXP_CTRL_TOG_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
81644 
81645 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK        (0x4U)
81646 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT       (2U)
81647 /*! NEXT_IRQ_ENABLE
81648  *  0b0..Disabled
81649  *  0b1..Enabled
81650  */
81651 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
81652 
81653 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81654 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81655 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
81656 
81657 #define PXP_CTRL_TOG_ROTATE_MASK                 (0x300U)
81658 #define PXP_CTRL_TOG_ROTATE_SHIFT                (8U)
81659 /*! ROTATE
81660  *  0b00..ROT_0
81661  *  0b01..ROT_90
81662  *  0b10..ROT_180
81663  *  0b11..ROT_270
81664  */
81665 #define PXP_CTRL_TOG_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
81666 
81667 #define PXP_CTRL_TOG_HFLIP_MASK                  (0x400U)
81668 #define PXP_CTRL_TOG_HFLIP_SHIFT                 (10U)
81669 /*! HFLIP
81670  *  0b0..Horizontal Flip is disabled
81671  *  0b1..Horizontal Flip is enabled
81672  */
81673 #define PXP_CTRL_TOG_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
81674 
81675 #define PXP_CTRL_TOG_VFLIP_MASK                  (0x800U)
81676 #define PXP_CTRL_TOG_VFLIP_SHIFT                 (11U)
81677 /*! VFLIP
81678  *  0b0..Vertical Flip is disabled
81679  *  0b1..Vertical Flip is enabled
81680  */
81681 #define PXP_CTRL_TOG_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
81682 
81683 #define PXP_CTRL_TOG_ROT_POS_MASK                (0x400000U)
81684 #define PXP_CTRL_TOG_ROT_POS_SHIFT               (22U)
81685 #define PXP_CTRL_TOG_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
81686 
81687 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
81688 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
81689 /*! BLOCK_SIZE
81690  *  0b0..Process 8x8 pixel blocks.
81691  *  0b1..Process 16x16 pixel blocks.
81692  */
81693 #define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
81694 
81695 #define PXP_CTRL_TOG_EN_REPEAT_MASK              (0x10000000U)
81696 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT             (28U)
81697 /*! EN_REPEAT
81698  *  0b1..PXP will repeat based on the current configuration register settings
81699  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81700  */
81701 #define PXP_CTRL_TOG_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
81702 
81703 #define PXP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
81704 #define PXP_CTRL_TOG_CLKGATE_SHIFT               (30U)
81705 /*! CLKGATE
81706  *  0b0..Normal operation
81707  *  0b1..All clocks to PXP is gated-off
81708  */
81709 #define PXP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
81710 
81711 #define PXP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
81712 #define PXP_CTRL_TOG_SFTRST_SHIFT                (31U)
81713 /*! SFTRST
81714  *  0b0..Normal PXP operation is enabled
81715  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81716  */
81717 #define PXP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
81718 /*! @} */
81719 
81720 /*! @name STAT - Status Register */
81721 /*! @{ */
81722 
81723 #define PXP_STAT_IRQ_MASK                        (0x1U)
81724 #define PXP_STAT_IRQ_SHIFT                       (0U)
81725 /*! IRQ
81726  *  0b0..No interrupt
81727  *  0b1..Interrupt generated
81728  */
81729 #define PXP_STAT_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
81730 
81731 #define PXP_STAT_AXI_WRITE_ERROR_MASK            (0x2U)
81732 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT           (1U)
81733 /*! AXI_WRITE_ERROR
81734  *  0b0..AXI write is normal
81735  *  0b1..AXI write error has occurred
81736  */
81737 #define PXP_STAT_AXI_WRITE_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
81738 
81739 #define PXP_STAT_AXI_READ_ERROR_MASK             (0x4U)
81740 #define PXP_STAT_AXI_READ_ERROR_SHIFT            (2U)
81741 /*! AXI_READ_ERROR
81742  *  0b0..AXI read is normal
81743  *  0b1..AXI read error has occurred
81744  */
81745 #define PXP_STAT_AXI_READ_ERROR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
81746 
81747 #define PXP_STAT_NEXT_IRQ_MASK                   (0x8U)
81748 #define PXP_STAT_NEXT_IRQ_SHIFT                  (3U)
81749 #define PXP_STAT_NEXT_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
81750 
81751 #define PXP_STAT_AXI_ERROR_ID_MASK               (0xF0U)
81752 #define PXP_STAT_AXI_ERROR_ID_SHIFT              (4U)
81753 #define PXP_STAT_AXI_ERROR_ID(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
81754 
81755 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      (0x100U)
81756 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     (8U)
81757 /*! LUT_DMA_LOAD_DONE_IRQ
81758  *  0b0..LUT DMA LOAD transfer is active
81759  *  0b1..LUT DMA LOAD transfer is complete
81760  */
81761 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
81762 
81763 #define PXP_STAT_BLOCKY_MASK                     (0xFF0000U)
81764 #define PXP_STAT_BLOCKY_SHIFT                    (16U)
81765 #define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
81766 
81767 #define PXP_STAT_BLOCKX_MASK                     (0xFF000000U)
81768 #define PXP_STAT_BLOCKX_SHIFT                    (24U)
81769 #define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
81770 /*! @} */
81771 
81772 /*! @name STAT_SET - Status Register */
81773 /*! @{ */
81774 
81775 #define PXP_STAT_SET_IRQ_MASK                    (0x1U)
81776 #define PXP_STAT_SET_IRQ_SHIFT                   (0U)
81777 /*! IRQ
81778  *  0b0..No interrupt
81779  *  0b1..Interrupt generated
81780  */
81781 #define PXP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
81782 
81783 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK        (0x2U)
81784 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT       (1U)
81785 /*! AXI_WRITE_ERROR
81786  *  0b0..AXI write is normal
81787  *  0b1..AXI write error has occurred
81788  */
81789 #define PXP_STAT_SET_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
81790 
81791 #define PXP_STAT_SET_AXI_READ_ERROR_MASK         (0x4U)
81792 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT        (2U)
81793 /*! AXI_READ_ERROR
81794  *  0b0..AXI read is normal
81795  *  0b1..AXI read error has occurred
81796  */
81797 #define PXP_STAT_SET_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
81798 
81799 #define PXP_STAT_SET_NEXT_IRQ_MASK               (0x8U)
81800 #define PXP_STAT_SET_NEXT_IRQ_SHIFT              (3U)
81801 #define PXP_STAT_SET_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
81802 
81803 #define PXP_STAT_SET_AXI_ERROR_ID_MASK           (0xF0U)
81804 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT          (4U)
81805 #define PXP_STAT_SET_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
81806 
81807 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81808 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81809 /*! LUT_DMA_LOAD_DONE_IRQ
81810  *  0b0..LUT DMA LOAD transfer is active
81811  *  0b1..LUT DMA LOAD transfer is complete
81812  */
81813 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
81814 
81815 #define PXP_STAT_SET_BLOCKY_MASK                 (0xFF0000U)
81816 #define PXP_STAT_SET_BLOCKY_SHIFT                (16U)
81817 #define PXP_STAT_SET_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
81818 
81819 #define PXP_STAT_SET_BLOCKX_MASK                 (0xFF000000U)
81820 #define PXP_STAT_SET_BLOCKX_SHIFT                (24U)
81821 #define PXP_STAT_SET_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
81822 /*! @} */
81823 
81824 /*! @name STAT_CLR - Status Register */
81825 /*! @{ */
81826 
81827 #define PXP_STAT_CLR_IRQ_MASK                    (0x1U)
81828 #define PXP_STAT_CLR_IRQ_SHIFT                   (0U)
81829 /*! IRQ
81830  *  0b0..No interrupt
81831  *  0b1..Interrupt generated
81832  */
81833 #define PXP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
81834 
81835 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK        (0x2U)
81836 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT       (1U)
81837 /*! AXI_WRITE_ERROR
81838  *  0b0..AXI write is normal
81839  *  0b1..AXI write error has occurred
81840  */
81841 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
81842 
81843 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK         (0x4U)
81844 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT        (2U)
81845 /*! AXI_READ_ERROR
81846  *  0b0..AXI read is normal
81847  *  0b1..AXI read error has occurred
81848  */
81849 #define PXP_STAT_CLR_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
81850 
81851 #define PXP_STAT_CLR_NEXT_IRQ_MASK               (0x8U)
81852 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT              (3U)
81853 #define PXP_STAT_CLR_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
81854 
81855 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK           (0xF0U)
81856 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT          (4U)
81857 #define PXP_STAT_CLR_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
81858 
81859 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81860 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81861 /*! LUT_DMA_LOAD_DONE_IRQ
81862  *  0b0..LUT DMA LOAD transfer is active
81863  *  0b1..LUT DMA LOAD transfer is complete
81864  */
81865 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
81866 
81867 #define PXP_STAT_CLR_BLOCKY_MASK                 (0xFF0000U)
81868 #define PXP_STAT_CLR_BLOCKY_SHIFT                (16U)
81869 #define PXP_STAT_CLR_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
81870 
81871 #define PXP_STAT_CLR_BLOCKX_MASK                 (0xFF000000U)
81872 #define PXP_STAT_CLR_BLOCKX_SHIFT                (24U)
81873 #define PXP_STAT_CLR_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
81874 /*! @} */
81875 
81876 /*! @name STAT_TOG - Status Register */
81877 /*! @{ */
81878 
81879 #define PXP_STAT_TOG_IRQ_MASK                    (0x1U)
81880 #define PXP_STAT_TOG_IRQ_SHIFT                   (0U)
81881 /*! IRQ
81882  *  0b0..No interrupt
81883  *  0b1..Interrupt generated
81884  */
81885 #define PXP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
81886 
81887 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK        (0x2U)
81888 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT       (1U)
81889 /*! AXI_WRITE_ERROR
81890  *  0b0..AXI write is normal
81891  *  0b1..AXI write error has occurred
81892  */
81893 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
81894 
81895 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK         (0x4U)
81896 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT        (2U)
81897 /*! AXI_READ_ERROR
81898  *  0b0..AXI read is normal
81899  *  0b1..AXI read error has occurred
81900  */
81901 #define PXP_STAT_TOG_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
81902 
81903 #define PXP_STAT_TOG_NEXT_IRQ_MASK               (0x8U)
81904 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT              (3U)
81905 #define PXP_STAT_TOG_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
81906 
81907 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK           (0xF0U)
81908 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT          (4U)
81909 #define PXP_STAT_TOG_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
81910 
81911 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81912 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81913 /*! LUT_DMA_LOAD_DONE_IRQ
81914  *  0b0..LUT DMA LOAD transfer is active
81915  *  0b1..LUT DMA LOAD transfer is complete
81916  */
81917 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
81918 
81919 #define PXP_STAT_TOG_BLOCKY_MASK                 (0xFF0000U)
81920 #define PXP_STAT_TOG_BLOCKY_SHIFT                (16U)
81921 #define PXP_STAT_TOG_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
81922 
81923 #define PXP_STAT_TOG_BLOCKX_MASK                 (0xFF000000U)
81924 #define PXP_STAT_TOG_BLOCKX_SHIFT                (24U)
81925 #define PXP_STAT_TOG_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
81926 /*! @} */
81927 
81928 /*! @name OUT_CTRL - Output Buffer Control Register */
81929 /*! @{ */
81930 
81931 #define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
81932 #define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
81933 /*! FORMAT
81934  *  0b00000..32-bit pixels
81935  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81936  *  0b00101..24-bit pixels (packed 24-bit format)
81937  *  0b01000..16-bit pixels
81938  *  0b01001..16-bit pixels
81939  *  0b01100..16-bit pixels
81940  *  0b01101..16-bit pixels
81941  *  0b01110..16-bit pixels
81942  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81943  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81944  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81945  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81946  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81947  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81948  *  0b11001..16-bit pixels (2-plane UV)
81949  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81950  *  0b11011..16-bit pixels (2-plane VU)
81951  */
81952 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
81953 
81954 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
81955 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
81956 /*! INTERLACED_OUTPUT
81957  *  0b00..All data written in progressive format to the OUTBUF Pointer.
81958  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
81959  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
81960  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
81961  */
81962 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
81963 
81964 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           (0x800000U)
81965 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          (23U)
81966 /*! ALPHA_OUTPUT
81967  *  0b0..Retain
81968  *  0b1..Overwritten
81969  */
81970 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
81971 
81972 #define PXP_OUT_CTRL_ALPHA_MASK                  (0xFF000000U)
81973 #define PXP_OUT_CTRL_ALPHA_SHIFT                 (24U)
81974 #define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
81975 /*! @} */
81976 
81977 /*! @name OUT_CTRL_SET - Output Buffer Control Register */
81978 /*! @{ */
81979 
81980 #define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
81981 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
81982 /*! FORMAT
81983  *  0b00000..32-bit pixels
81984  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81985  *  0b00101..24-bit pixels (packed 24-bit format)
81986  *  0b01000..16-bit pixels
81987  *  0b01001..16-bit pixels
81988  *  0b01100..16-bit pixels
81989  *  0b01101..16-bit pixels
81990  *  0b01110..16-bit pixels
81991  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81992  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81993  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81994  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81995  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81996  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81997  *  0b11001..16-bit pixels (2-plane UV)
81998  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81999  *  0b11011..16-bit pixels (2-plane VU)
82000  */
82001 #define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
82002 
82003 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
82004 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
82005 /*! INTERLACED_OUTPUT
82006  *  0b00..All data written in progressive format to the OUTBUF Pointer.
82007  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
82008  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
82009  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
82010  */
82011 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
82012 
82013 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK       (0x800000U)
82014 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT      (23U)
82015 /*! ALPHA_OUTPUT
82016  *  0b0..Retain
82017  *  0b1..Overwritten
82018  */
82019 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
82020 
82021 #define PXP_OUT_CTRL_SET_ALPHA_MASK              (0xFF000000U)
82022 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT             (24U)
82023 #define PXP_OUT_CTRL_SET_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
82024 /*! @} */
82025 
82026 /*! @name OUT_CTRL_CLR - Output Buffer Control Register */
82027 /*! @{ */
82028 
82029 #define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
82030 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
82031 /*! FORMAT
82032  *  0b00000..32-bit pixels
82033  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
82034  *  0b00101..24-bit pixels (packed 24-bit format)
82035  *  0b01000..16-bit pixels
82036  *  0b01001..16-bit pixels
82037  *  0b01100..16-bit pixels
82038  *  0b01101..16-bit pixels
82039  *  0b01110..16-bit pixels
82040  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
82041  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82042  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82043  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
82044  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82045  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
82046  *  0b11001..16-bit pixels (2-plane UV)
82047  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
82048  *  0b11011..16-bit pixels (2-plane VU)
82049  */
82050 #define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
82051 
82052 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
82053 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
82054 /*! INTERLACED_OUTPUT
82055  *  0b00..All data written in progressive format to the OUTBUF Pointer.
82056  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
82057  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
82058  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
82059  */
82060 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
82061 
82062 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK       (0x800000U)
82063 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT      (23U)
82064 /*! ALPHA_OUTPUT
82065  *  0b0..Retain
82066  *  0b1..Overwritten
82067  */
82068 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
82069 
82070 #define PXP_OUT_CTRL_CLR_ALPHA_MASK              (0xFF000000U)
82071 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT             (24U)
82072 #define PXP_OUT_CTRL_CLR_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
82073 /*! @} */
82074 
82075 /*! @name OUT_CTRL_TOG - Output Buffer Control Register */
82076 /*! @{ */
82077 
82078 #define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
82079 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
82080 /*! FORMAT
82081  *  0b00000..32-bit pixels
82082  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
82083  *  0b00101..24-bit pixels (packed 24-bit format)
82084  *  0b01000..16-bit pixels
82085  *  0b01001..16-bit pixels
82086  *  0b01100..16-bit pixels
82087  *  0b01101..16-bit pixels
82088  *  0b01110..16-bit pixels
82089  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
82090  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82091  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82092  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
82093  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82094  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
82095  *  0b11001..16-bit pixels (2-plane UV)
82096  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
82097  *  0b11011..16-bit pixels (2-plane VU)
82098  */
82099 #define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
82100 
82101 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
82102 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
82103 /*! INTERLACED_OUTPUT
82104  *  0b00..All data written in progressive format to the OUTBUF Pointer.
82105  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
82106  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
82107  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
82108  */
82109 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
82110 
82111 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK       (0x800000U)
82112 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT      (23U)
82113 /*! ALPHA_OUTPUT
82114  *  0b0..Retain
82115  *  0b1..Overwritten
82116  */
82117 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
82118 
82119 #define PXP_OUT_CTRL_TOG_ALPHA_MASK              (0xFF000000U)
82120 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT             (24U)
82121 #define PXP_OUT_CTRL_TOG_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
82122 /*! @} */
82123 
82124 /*! @name OUT_BUF - Output Frame Buffer Pointer */
82125 /*! @{ */
82126 
82127 #define PXP_OUT_BUF_ADDR_MASK                    (0xFFFFFFFFU)
82128 #define PXP_OUT_BUF_ADDR_SHIFT                   (0U)
82129 #define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
82130 /*! @} */
82131 
82132 /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
82133 /*! @{ */
82134 
82135 #define PXP_OUT_BUF2_ADDR_MASK                   (0xFFFFFFFFU)
82136 #define PXP_OUT_BUF2_ADDR_SHIFT                  (0U)
82137 #define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
82138 /*! @} */
82139 
82140 /*! @name OUT_PITCH - Output Buffer Pitch */
82141 /*! @{ */
82142 
82143 #define PXP_OUT_PITCH_PITCH_MASK                 (0xFFFFU)
82144 #define PXP_OUT_PITCH_PITCH_SHIFT                (0U)
82145 #define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
82146 /*! @} */
82147 
82148 /*! @name OUT_LRC - Output Surface Lower Right Coordinate */
82149 /*! @{ */
82150 
82151 #define PXP_OUT_LRC_Y_MASK                       (0x3FFFU)
82152 #define PXP_OUT_LRC_Y_SHIFT                      (0U)
82153 #define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
82154 
82155 #define PXP_OUT_LRC_X_MASK                       (0x3FFF0000U)
82156 #define PXP_OUT_LRC_X_SHIFT                      (16U)
82157 #define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
82158 /*! @} */
82159 
82160 /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
82161 /*! @{ */
82162 
82163 #define PXP_OUT_PS_ULC_Y_MASK                    (0x3FFFU)
82164 #define PXP_OUT_PS_ULC_Y_SHIFT                   (0U)
82165 #define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
82166 
82167 #define PXP_OUT_PS_ULC_X_MASK                    (0x3FFF0000U)
82168 #define PXP_OUT_PS_ULC_X_SHIFT                   (16U)
82169 #define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
82170 /*! @} */
82171 
82172 /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
82173 /*! @{ */
82174 
82175 #define PXP_OUT_PS_LRC_Y_MASK                    (0x3FFFU)
82176 #define PXP_OUT_PS_LRC_Y_SHIFT                   (0U)
82177 #define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
82178 
82179 #define PXP_OUT_PS_LRC_X_MASK                    (0x3FFF0000U)
82180 #define PXP_OUT_PS_LRC_X_SHIFT                   (16U)
82181 #define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
82182 /*! @} */
82183 
82184 /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
82185 /*! @{ */
82186 
82187 #define PXP_OUT_AS_ULC_Y_MASK                    (0x3FFFU)
82188 #define PXP_OUT_AS_ULC_Y_SHIFT                   (0U)
82189 #define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
82190 
82191 #define PXP_OUT_AS_ULC_X_MASK                    (0x3FFF0000U)
82192 #define PXP_OUT_AS_ULC_X_SHIFT                   (16U)
82193 #define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
82194 /*! @} */
82195 
82196 /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
82197 /*! @{ */
82198 
82199 #define PXP_OUT_AS_LRC_Y_MASK                    (0x3FFFU)
82200 #define PXP_OUT_AS_LRC_Y_SHIFT                   (0U)
82201 #define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
82202 
82203 #define PXP_OUT_AS_LRC_X_MASK                    (0x3FFF0000U)
82204 #define PXP_OUT_AS_LRC_X_SHIFT                   (16U)
82205 #define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
82206 /*! @} */
82207 
82208 /*! @name PS_CTRL - Processed Surface (PS) Control Register */
82209 /*! @{ */
82210 
82211 #define PXP_PS_CTRL_FORMAT_MASK                  (0x3FU)
82212 #define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
82213 /*! FORMAT
82214  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
82215  *  0b001100..16-bit pixels with/without alpha at high 1bit
82216  *  0b001101..16-bit pixels with/without alpha at high 4 bits
82217  *  0b001110..16-bit pixels
82218  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
82219  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82220  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82221  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
82222  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82223  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
82224  *  0b011001..16-bit pixels (2-plane UV)
82225  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
82226  *  0b011011..16-bit pixels (2-plane VU)
82227  *  0b011110..16-bit pixels (3-plane format)
82228  *  0b011111..16-bit pixels (3-plane format)
82229  *  0b100100..2-bit pixels with alpha at the low 8 bits
82230  *  0b101100..16-bit pixels with alpha at the low 1bits
82231  *  0b101101..16-bit pixels with alpha at the low 4 bits
82232  */
82233 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
82234 
82235 #define PXP_PS_CTRL_WB_SWAP_MASK                 (0x40U)
82236 #define PXP_PS_CTRL_WB_SWAP_SHIFT                (6U)
82237 /*! WB_SWAP
82238  *  0b0..Byte swap is disabled
82239  *  0b1..Byte swap is enabled
82240  */
82241 #define PXP_PS_CTRL_WB_SWAP(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
82242 
82243 #define PXP_PS_CTRL_DECY_MASK                    (0x300U)
82244 #define PXP_PS_CTRL_DECY_SHIFT                   (8U)
82245 /*! DECY
82246  *  0b00..Disable pre-decimation filter.
82247  *  0b01..Decimate PS by 2.
82248  *  0b10..Decimate PS by 4.
82249  *  0b11..Decimate PS by 8.
82250  */
82251 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
82252 
82253 #define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
82254 #define PXP_PS_CTRL_DECX_SHIFT                   (10U)
82255 /*! DECX
82256  *  0b00..Disable pre-decimation filter.
82257  *  0b01..Decimate PS by 2.
82258  *  0b10..Decimate PS by 4.
82259  *  0b11..Decimate PS by 8.
82260  */
82261 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
82262 /*! @} */
82263 
82264 /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
82265 /*! @{ */
82266 
82267 #define PXP_PS_CTRL_SET_FORMAT_MASK              (0x3FU)
82268 #define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
82269 /*! FORMAT
82270  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
82271  *  0b001100..16-bit pixels with/without alpha at high 1bit
82272  *  0b001101..16-bit pixels with/without alpha at high 4 bits
82273  *  0b001110..16-bit pixels
82274  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
82275  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82276  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82277  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
82278  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82279  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
82280  *  0b011001..16-bit pixels (2-plane UV)
82281  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
82282  *  0b011011..16-bit pixels (2-plane VU)
82283  *  0b011110..16-bit pixels (3-plane format)
82284  *  0b011111..16-bit pixels (3-plane format)
82285  *  0b100100..2-bit pixels with alpha at the low 8 bits
82286  *  0b101100..16-bit pixels with alpha at the low 1bits
82287  *  0b101101..16-bit pixels with alpha at the low 4 bits
82288  */
82289 #define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
82290 
82291 #define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x40U)
82292 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (6U)
82293 /*! WB_SWAP
82294  *  0b0..Byte swap is disabled
82295  *  0b1..Byte swap is enabled
82296  */
82297 #define PXP_PS_CTRL_SET_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
82298 
82299 #define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
82300 #define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
82301 /*! DECY
82302  *  0b00..Disable pre-decimation filter.
82303  *  0b01..Decimate PS by 2.
82304  *  0b10..Decimate PS by 4.
82305  *  0b11..Decimate PS by 8.
82306  */
82307 #define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
82308 
82309 #define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
82310 #define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
82311 /*! DECX
82312  *  0b00..Disable pre-decimation filter.
82313  *  0b01..Decimate PS by 2.
82314  *  0b10..Decimate PS by 4.
82315  *  0b11..Decimate PS by 8.
82316  */
82317 #define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
82318 /*! @} */
82319 
82320 /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
82321 /*! @{ */
82322 
82323 #define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x3FU)
82324 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
82325 /*! FORMAT
82326  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
82327  *  0b001100..16-bit pixels with/without alpha at high 1bit
82328  *  0b001101..16-bit pixels with/without alpha at high 4 bits
82329  *  0b001110..16-bit pixels
82330  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
82331  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82332  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82333  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
82334  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82335  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
82336  *  0b011001..16-bit pixels (2-plane UV)
82337  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
82338  *  0b011011..16-bit pixels (2-plane VU)
82339  *  0b011110..16-bit pixels (3-plane format)
82340  *  0b011111..16-bit pixels (3-plane format)
82341  *  0b100100..2-bit pixels with alpha at the low 8 bits
82342  *  0b101100..16-bit pixels with alpha at the low 1bits
82343  *  0b101101..16-bit pixels with alpha at the low 4 bits
82344  */
82345 #define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
82346 
82347 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x40U)
82348 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (6U)
82349 /*! WB_SWAP
82350  *  0b0..Byte swap is disabled
82351  *  0b1..Byte swap is enabled
82352  */
82353 #define PXP_PS_CTRL_CLR_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
82354 
82355 #define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
82356 #define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
82357 /*! DECY
82358  *  0b00..Disable pre-decimation filter.
82359  *  0b01..Decimate PS by 2.
82360  *  0b10..Decimate PS by 4.
82361  *  0b11..Decimate PS by 8.
82362  */
82363 #define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
82364 
82365 #define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
82366 #define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
82367 /*! DECX
82368  *  0b00..Disable pre-decimation filter.
82369  *  0b01..Decimate PS by 2.
82370  *  0b10..Decimate PS by 4.
82371  *  0b11..Decimate PS by 8.
82372  */
82373 #define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
82374 /*! @} */
82375 
82376 /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
82377 /*! @{ */
82378 
82379 #define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x3FU)
82380 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
82381 /*! FORMAT
82382  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
82383  *  0b001100..16-bit pixels with/without alpha at high 1bit
82384  *  0b001101..16-bit pixels with/without alpha at high 4 bits
82385  *  0b001110..16-bit pixels
82386  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
82387  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82388  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82389  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
82390  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82391  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
82392  *  0b011001..16-bit pixels (2-plane UV)
82393  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
82394  *  0b011011..16-bit pixels (2-plane VU)
82395  *  0b011110..16-bit pixels (3-plane format)
82396  *  0b011111..16-bit pixels (3-plane format)
82397  *  0b100100..2-bit pixels with alpha at the low 8 bits
82398  *  0b101100..16-bit pixels with alpha at the low 1bits
82399  *  0b101101..16-bit pixels with alpha at the low 4 bits
82400  */
82401 #define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
82402 
82403 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x40U)
82404 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (6U)
82405 /*! WB_SWAP
82406  *  0b0..Byte swap is disabled
82407  *  0b1..Byte swap is enabled
82408  */
82409 #define PXP_PS_CTRL_TOG_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
82410 
82411 #define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
82412 #define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
82413 /*! DECY
82414  *  0b00..Disable pre-decimation filter.
82415  *  0b01..Decimate PS by 2.
82416  *  0b10..Decimate PS by 4.
82417  *  0b11..Decimate PS by 8.
82418  */
82419 #define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
82420 
82421 #define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
82422 #define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
82423 /*! DECX
82424  *  0b00..Disable pre-decimation filter.
82425  *  0b01..Decimate PS by 2.
82426  *  0b10..Decimate PS by 4.
82427  *  0b11..Decimate PS by 8.
82428  */
82429 #define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
82430 /*! @} */
82431 
82432 /*! @name PS_BUF - PS Input Buffer Address */
82433 /*! @{ */
82434 
82435 #define PXP_PS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
82436 #define PXP_PS_BUF_ADDR_SHIFT                    (0U)
82437 #define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
82438 /*! @} */
82439 
82440 /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
82441 /*! @{ */
82442 
82443 #define PXP_PS_UBUF_ADDR_MASK                    (0xFFFFFFFFU)
82444 #define PXP_PS_UBUF_ADDR_SHIFT                   (0U)
82445 #define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
82446 /*! @} */
82447 
82448 /*! @name PS_VBUF - PS V/Cr Input Buffer Address */
82449 /*! @{ */
82450 
82451 #define PXP_PS_VBUF_ADDR_MASK                    (0xFFFFFFFFU)
82452 #define PXP_PS_VBUF_ADDR_SHIFT                   (0U)
82453 #define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
82454 /*! @} */
82455 
82456 /*! @name PS_PITCH - Processed Surface Pitch */
82457 /*! @{ */
82458 
82459 #define PXP_PS_PITCH_PITCH_MASK                  (0xFFFFU)
82460 #define PXP_PS_PITCH_PITCH_SHIFT                 (0U)
82461 #define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
82462 /*! @} */
82463 
82464 /*! @name PS_BACKGROUND - PS Background Color */
82465 /*! @{ */
82466 
82467 #define PXP_PS_BACKGROUND_COLOR_MASK             (0xFFFFFFU)
82468 #define PXP_PS_BACKGROUND_COLOR_SHIFT            (0U)
82469 #define PXP_PS_BACKGROUND_COLOR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
82470 /*! @} */
82471 
82472 /*! @name PS_SCALE - PS Scale Factor Register */
82473 /*! @{ */
82474 
82475 #define PXP_PS_SCALE_XSCALE_MASK                 (0x7FFFU)
82476 #define PXP_PS_SCALE_XSCALE_SHIFT                (0U)
82477 #define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
82478 
82479 #define PXP_PS_SCALE_YSCALE_MASK                 (0x7FFF0000U)
82480 #define PXP_PS_SCALE_YSCALE_SHIFT                (16U)
82481 #define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
82482 /*! @} */
82483 
82484 /*! @name PS_OFFSET - PS Scale Offset Register */
82485 /*! @{ */
82486 
82487 #define PXP_PS_OFFSET_XOFFSET_MASK               (0xFFFU)
82488 #define PXP_PS_OFFSET_XOFFSET_SHIFT              (0U)
82489 #define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
82490 
82491 #define PXP_PS_OFFSET_YOFFSET_MASK               (0xFFF0000U)
82492 #define PXP_PS_OFFSET_YOFFSET_SHIFT              (16U)
82493 #define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
82494 /*! @} */
82495 
82496 /*! @name PS_CLRKEYLOW - PS Color Key Low */
82497 /*! @{ */
82498 
82499 #define PXP_PS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
82500 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT             (0U)
82501 #define PXP_PS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
82502 /*! @} */
82503 
82504 /*! @name PS_CLRKEYHIGH - PS Color Key High */
82505 /*! @{ */
82506 
82507 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
82508 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
82509 #define PXP_PS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
82510 /*! @} */
82511 
82512 /*! @name AS_CTRL - Alpha Surface Control */
82513 /*! @{ */
82514 
82515 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
82516 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
82517 /*! ALPHA_CTRL
82518  *  0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
82519  *  0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
82520  *  0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
82521  *        alpha is multiplied by the value in the ALPHA field.
82522  *  0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
82523  */
82524 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
82525 
82526 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
82527 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
82528 /*! ENABLE_COLORKEY
82529  *  0b0..Disabled
82530  *  0b1..Enabled
82531  */
82532 #define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
82533 
82534 #define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
82535 #define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
82536 /*! FORMAT
82537  *  0b0000..32-bit pixels with alpha
82538  *  0b0001..2-bit pixel with alpha at low 8 bits
82539  *  0b0100..32-bit pixels without alpha (unpacked 24-bit format)
82540  *  0b1000..16-bit pixels with alpha
82541  *  0b1001..16-bit pixels with alpha
82542  *  0b1010..16-bit pixel with alpha at low 1 bit
82543  *  0b1011..16-bit pixel with alpha at low 4 bits
82544  *  0b1100..16-bit pixels without alpha
82545  *  0b1101..16-bit pixels without alpha
82546  *  0b1110..16-bit pixels without alpha
82547  */
82548 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
82549 
82550 #define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
82551 #define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
82552 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
82553 
82554 #define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
82555 #define PXP_AS_CTRL_ROP_SHIFT                    (16U)
82556 /*! ROP
82557  *  0b0000..AS AND PS
82558  *  0b0001..nAS AND PS
82559  *  0b0010..AS AND nPS
82560  *  0b0011..AS OR PS
82561  *  0b0100..nAS OR PS
82562  *  0b0101..AS OR nPS
82563  *  0b0110..nAS
82564  *  0b0111..nPS
82565  *  0b1000..AS NAND PS
82566  *  0b1001..AS NOR PS
82567  *  0b1010..AS XOR PS
82568  *  0b1011..AS XNOR PS
82569  */
82570 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
82571 
82572 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            (0x100000U)
82573 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           (20U)
82574 /*! ALPHA_INVERT
82575  *  0b0..Not inverted
82576  *  0b1..Inverted
82577  */
82578 #define PXP_AS_CTRL_ALPHA_INVERT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
82579 /*! @} */
82580 
82581 /*! @name AS_BUF - Alpha Surface Buffer Pointer */
82582 /*! @{ */
82583 
82584 #define PXP_AS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
82585 #define PXP_AS_BUF_ADDR_SHIFT                    (0U)
82586 #define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
82587 /*! @} */
82588 
82589 /*! @name AS_PITCH - Alpha Surface Pitch */
82590 /*! @{ */
82591 
82592 #define PXP_AS_PITCH_PITCH_MASK                  (0xFFFFU)
82593 #define PXP_AS_PITCH_PITCH_SHIFT                 (0U)
82594 #define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
82595 /*! @} */
82596 
82597 /*! @name AS_CLRKEYLOW - Overlay Color Key Low */
82598 /*! @{ */
82599 
82600 #define PXP_AS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
82601 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT             (0U)
82602 #define PXP_AS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
82603 /*! @} */
82604 
82605 /*! @name AS_CLRKEYHIGH - Overlay Color Key High */
82606 /*! @{ */
82607 
82608 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
82609 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
82610 #define PXP_AS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
82611 /*! @} */
82612 
82613 /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
82614 /*! @{ */
82615 
82616 #define PXP_CSC1_COEF0_Y_OFFSET_MASK             (0x1FFU)
82617 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            (0U)
82618 #define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
82619 
82620 #define PXP_CSC1_COEF0_UV_OFFSET_MASK            (0x3FE00U)
82621 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           (9U)
82622 #define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
82623 
82624 #define PXP_CSC1_COEF0_C0_MASK                   (0x1FFC0000U)
82625 #define PXP_CSC1_COEF0_C0_SHIFT                  (18U)
82626 #define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
82627 
82628 #define PXP_CSC1_COEF0_BYPASS_MASK               (0x40000000U)
82629 #define PXP_CSC1_COEF0_BYPASS_SHIFT              (30U)
82630 #define PXP_CSC1_COEF0_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
82631 
82632 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK           (0x80000000U)
82633 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          (31U)
82634 /*! YCBCR_MODE
82635  *  0b0..YUV to RGB
82636  *  0b1..YCbCr to RGB
82637  */
82638 #define PXP_CSC1_COEF0_YCBCR_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
82639 /*! @} */
82640 
82641 /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
82642 /*! @{ */
82643 
82644 #define PXP_CSC1_COEF1_C4_MASK                   (0x7FFU)
82645 #define PXP_CSC1_COEF1_C4_SHIFT                  (0U)
82646 #define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
82647 
82648 #define PXP_CSC1_COEF1_C1_MASK                   (0x7FF0000U)
82649 #define PXP_CSC1_COEF1_C1_SHIFT                  (16U)
82650 #define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
82651 /*! @} */
82652 
82653 /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
82654 /*! @{ */
82655 
82656 #define PXP_CSC1_COEF2_C3_MASK                   (0x7FFU)
82657 #define PXP_CSC1_COEF2_C3_SHIFT                  (0U)
82658 #define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
82659 
82660 #define PXP_CSC1_COEF2_C2_MASK                   (0x7FF0000U)
82661 #define PXP_CSC1_COEF2_C2_SHIFT                  (16U)
82662 #define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
82663 /*! @} */
82664 
82665 /*! @name POWER - PXP Power Control Register */
82666 /*! @{ */
82667 
82668 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          (0xE00U)
82669 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         (9U)
82670 /*! ROT_MEM_LP_STATE
82671  *  0b000..Memory is not in low power state.
82672  *  0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
82673  *  0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
82674  *  0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
82675  */
82676 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
82677 /*! @} */
82678 
82679 /*! @name NEXT - Next Frame Pointer */
82680 /*! @{ */
82681 
82682 #define PXP_NEXT_ENABLED_MASK                    (0x1U)
82683 #define PXP_NEXT_ENABLED_SHIFT                   (0U)
82684 #define PXP_NEXT_ENABLED(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
82685 
82686 #define PXP_NEXT_POINTER_MASK                    (0xFFFFFFFCU)
82687 #define PXP_NEXT_POINTER_SHIFT                   (2U)
82688 #define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
82689 /*! @} */
82690 
82691 /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
82692 /*! @{ */
82693 
82694 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
82695 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
82696 /*! PORTER_DUFF_ENABLE
82697  *  0b0..Disabled
82698  *  0b1..Enabled
82699  */
82700 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
82701 
82702 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
82703 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
82704 /*! S0_S1_FACTOR_MODE
82705  *  0b00..1
82706  *  0b01..0
82707  *  0b10..Straight alpha
82708  *  0b11..Inverse alpha
82709  */
82710 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
82711 
82712 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
82713 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
82714 /*! S0_GLOBAL_ALPHA_MODE
82715  *  0b00..Global alpha
82716  *  0b01..Local alpha
82717  *  0b10..Scaled alpha
82718  *  0b11..Scaled alpha
82719  */
82720 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
82721 
82722 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK  (0x20U)
82723 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
82724 /*! S0_ALPHA_MODE
82725  *  0b0..Straight mode
82726  *  0b1..Inverted mode
82727  */
82728 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
82729 
82730 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK  (0x40U)
82731 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
82732 /*! S0_COLOR_MODE
82733  *  0b0..Original pixel
82734  *  0b1..Scaled pixel
82735  */
82736 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
82737 
82738 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
82739 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
82740 /*! S1_S0_FACTOR_MODE
82741  *  0b00..1
82742  *  0b01..0
82743  *  0b10..Straight alpha
82744  *  0b11..Inverse alpha
82745  */
82746 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
82747 
82748 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
82749 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
82750 /*! S1_GLOBAL_ALPHA_MODE
82751  *  0b00..Global alpha
82752  *  0b01..Local alpha
82753  *  0b10..Scaled alpha
82754  *  0b11..Scaled alpha
82755  */
82756 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
82757 
82758 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK  (0x1000U)
82759 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
82760 /*! S1_ALPHA_MODE
82761  *  0b0..Straight mode
82762  *  0b1..Inverted mode
82763  */
82764 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
82765 
82766 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK  (0x2000U)
82767 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
82768 /*! S1_COLOR_MODE
82769  *  0b0..Original pixel
82770  *  0b1..Scaled pixel
82771  */
82772 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
82773 
82774 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
82775 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
82776 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
82777 
82778 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
82779 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
82780 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
82781 /*! @} */
82782 
82783 
82784 /*!
82785  * @}
82786  */ /* end of group PXP_Register_Masks */
82787 
82788 
82789 /* PXP - Peripheral instance base addresses */
82790 /** Peripheral PXP base address */
82791 #define PXP_BASE                                 (0x40814000u)
82792 /** Peripheral PXP base pointer */
82793 #define PXP                                      ((PXP_Type *)PXP_BASE)
82794 /** Array initializer of PXP peripheral base addresses */
82795 #define PXP_BASE_ADDRS                           { PXP_BASE }
82796 /** Array initializer of PXP peripheral base pointers */
82797 #define PXP_BASE_PTRS                            { PXP }
82798 /** Interrupt vectors for the PXP peripheral type */
82799 #define PXP_IRQ0_IRQS                            { PXP_IRQn }
82800 
82801 /*!
82802  * @}
82803  */ /* end of group PXP_Peripheral_Access_Layer */
82804 
82805 
82806 /* ----------------------------------------------------------------------------
82807    -- RDC Peripheral Access Layer
82808    ---------------------------------------------------------------------------- */
82809 
82810 /*!
82811  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
82812  * @{
82813  */
82814 
82815 /** RDC - Register Layout Typedef */
82816 typedef struct {
82817   __I  uint32_t VIR;                               /**< Version Information, offset: 0x0 */
82818        uint8_t RESERVED_0[32];
82819   __IO uint32_t STAT;                              /**< Status, offset: 0x24 */
82820   __IO uint32_t INTCTRL;                           /**< Interrupt and Control, offset: 0x28 */
82821   __IO uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x2C */
82822        uint8_t RESERVED_1[464];
82823   __IO uint32_t MDA[12];                           /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
82824        uint8_t RESERVED_2[464];
82825   __IO uint32_t PDAP[128];                         /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
82826        uint8_t RESERVED_3[512];
82827   struct {                                         /* offset: 0x800, array step: 0x10 */
82828     __IO uint32_t MRSA;                              /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
82829     __IO uint32_t MREA;                              /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
82830     __IO uint32_t MRC;                               /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
82831     __IO uint32_t MRVS;                              /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
82832   } MR[59];
82833 } RDC_Type;
82834 
82835 /* ----------------------------------------------------------------------------
82836    -- RDC Register Masks
82837    ---------------------------------------------------------------------------- */
82838 
82839 /*!
82840  * @addtogroup RDC_Register_Masks RDC Register Masks
82841  * @{
82842  */
82843 
82844 /*! @name VIR - Version Information */
82845 /*! @{ */
82846 
82847 #define RDC_VIR_NDID_MASK                        (0xFU)
82848 #define RDC_VIR_NDID_SHIFT                       (0U)
82849 /*! NDID - Number of Domains
82850  */
82851 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
82852 
82853 #define RDC_VIR_NMSTR_MASK                       (0xFF0U)
82854 #define RDC_VIR_NMSTR_SHIFT                      (4U)
82855 /*! NMSTR - Number of Masters
82856  */
82857 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
82858 
82859 #define RDC_VIR_NPER_MASK                        (0xFF000U)
82860 #define RDC_VIR_NPER_SHIFT                       (12U)
82861 /*! NPER - Number of Peripherals
82862  */
82863 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
82864 
82865 #define RDC_VIR_NRGN_MASK                        (0xFF00000U)
82866 #define RDC_VIR_NRGN_SHIFT                       (20U)
82867 /*! NRGN - Number of Memory Regions
82868  */
82869 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
82870 /*! @} */
82871 
82872 /*! @name STAT - Status */
82873 /*! @{ */
82874 
82875 #define RDC_STAT_DID_MASK                        (0xFU)
82876 #define RDC_STAT_DID_SHIFT                       (0U)
82877 /*! DID - Domain ID
82878  */
82879 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
82880 
82881 #define RDC_STAT_PDS_MASK                        (0x100U)
82882 #define RDC_STAT_PDS_SHIFT                       (8U)
82883 /*! PDS - Power Domain Status
82884  *  0b0..Power Down Domain is OFF
82885  *  0b1..Power Down Domain is ON
82886  */
82887 #define RDC_STAT_PDS(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
82888 /*! @} */
82889 
82890 /*! @name INTCTRL - Interrupt and Control */
82891 /*! @{ */
82892 
82893 #define RDC_INTCTRL_RCI_EN_MASK                  (0x1U)
82894 #define RDC_INTCTRL_RCI_EN_SHIFT                 (0U)
82895 /*! RCI_EN - Restoration Complete Interrupt
82896  *  0b0..Interrupt Disabled
82897  *  0b1..Interrupt Enabled
82898  */
82899 #define RDC_INTCTRL_RCI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
82900 /*! @} */
82901 
82902 /*! @name INTSTAT - Interrupt Status */
82903 /*! @{ */
82904 
82905 #define RDC_INTSTAT_INT_MASK                     (0x1U)
82906 #define RDC_INTSTAT_INT_SHIFT                    (0U)
82907 /*! INT - Interrupt Status
82908  *  0b0..No Interrupt Pending
82909  *  0b1..Interrupt Pending
82910  */
82911 #define RDC_INTSTAT_INT(x)                       (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
82912 /*! @} */
82913 
82914 /*! @name MDA - Master Domain Assignment */
82915 /*! @{ */
82916 
82917 #define RDC_MDA_DID_MASK                         (0x3U)
82918 #define RDC_MDA_DID_SHIFT                        (0U)
82919 /*! DID - Domain ID
82920  *  0b00..Master assigned to Processing Domain 0
82921  *  0b01..Master assigned to Processing Domain 1
82922  *  0b10..Reserved
82923  *  0b11..Reserved
82924  */
82925 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
82926 
82927 #define RDC_MDA_LCK_MASK                         (0x80000000U)
82928 #define RDC_MDA_LCK_SHIFT                        (31U)
82929 /*! LCK - Assignment Lock
82930  *  0b0..Not Locked
82931  *  0b1..Locked
82932  */
82933 #define RDC_MDA_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
82934 /*! @} */
82935 
82936 /* The count of RDC_MDA */
82937 #define RDC_MDA_COUNT                            (12U)
82938 
82939 /*! @name PDAP - Peripheral Domain Access Permissions */
82940 /*! @{ */
82941 
82942 #define RDC_PDAP_D0W_MASK                        (0x1U)
82943 #define RDC_PDAP_D0W_SHIFT                       (0U)
82944 /*! D0W - Domain 0 Write Access
82945  *  0b0..No Write Access
82946  *  0b1..Write Access Allowed
82947  */
82948 #define RDC_PDAP_D0W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
82949 
82950 #define RDC_PDAP_D0R_MASK                        (0x2U)
82951 #define RDC_PDAP_D0R_SHIFT                       (1U)
82952 /*! D0R - Domain 0 Read Access
82953  *  0b0..No Read Access
82954  *  0b1..Read Access Allowed
82955  */
82956 #define RDC_PDAP_D0R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
82957 
82958 #define RDC_PDAP_D1W_MASK                        (0x4U)
82959 #define RDC_PDAP_D1W_SHIFT                       (2U)
82960 /*! D1W - Domain 1 Write Access
82961  *  0b0..No Write Access
82962  *  0b1..Write Access Allowed
82963  */
82964 #define RDC_PDAP_D1W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
82965 
82966 #define RDC_PDAP_D1R_MASK                        (0x8U)
82967 #define RDC_PDAP_D1R_SHIFT                       (3U)
82968 /*! D1R - Domain 1 Read Access
82969  *  0b0..No Read Access
82970  *  0b1..Read Access Allowed
82971  */
82972 #define RDC_PDAP_D1R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
82973 
82974 #define RDC_PDAP_SREQ_MASK                       (0x40000000U)
82975 #define RDC_PDAP_SREQ_SHIFT                      (30U)
82976 /*! SREQ - Semaphore Required
82977  *  0b0..Semaphores have no effect
82978  *  0b1..Semaphores are enforced
82979  */
82980 #define RDC_PDAP_SREQ(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
82981 
82982 #define RDC_PDAP_LCK_MASK                        (0x80000000U)
82983 #define RDC_PDAP_LCK_SHIFT                       (31U)
82984 /*! LCK - Peripheral Permissions Lock
82985  *  0b0..Not Locked
82986  *  0b1..Locked
82987  */
82988 #define RDC_PDAP_LCK(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
82989 /*! @} */
82990 
82991 /* The count of RDC_PDAP */
82992 #define RDC_PDAP_COUNT                           (128U)
82993 
82994 /*! @name MRSA - Memory Region Start Address */
82995 /*! @{ */
82996 
82997 #define RDC_MRSA_SADR_MASK                       (0xFFFFFF80U)
82998 #define RDC_MRSA_SADR_SHIFT                      (7U)
82999 /*! SADR - Start address for memory region
83000  */
83001 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
83002 /*! @} */
83003 
83004 /* The count of RDC_MRSA */
83005 #define RDC_MRSA_COUNT                           (59U)
83006 
83007 /*! @name MREA - Memory Region End Address */
83008 /*! @{ */
83009 
83010 #define RDC_MREA_EADR_MASK                       (0xFFFFFF80U)
83011 #define RDC_MREA_EADR_SHIFT                      (7U)
83012 /*! EADR - Upper bound for memory region
83013  */
83014 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
83015 /*! @} */
83016 
83017 /* The count of RDC_MREA */
83018 #define RDC_MREA_COUNT                           (59U)
83019 
83020 /*! @name MRC - Memory Region Control */
83021 /*! @{ */
83022 
83023 #define RDC_MRC_D0W_MASK                         (0x1U)
83024 #define RDC_MRC_D0W_SHIFT                        (0U)
83025 /*! D0W - Domain 0 Write Access to Region
83026  *  0b0..Processing Domain 0 does not have Write access to the memory region
83027  *  0b1..Processing Domain 0 has Write access to the memory region
83028  */
83029 #define RDC_MRC_D0W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
83030 
83031 #define RDC_MRC_D0R_MASK                         (0x2U)
83032 #define RDC_MRC_D0R_SHIFT                        (1U)
83033 /*! D0R - Domain 0 Read Access to Region
83034  *  0b0..Processing Domain 0 does not have Read access to the memory region
83035  *  0b1..Processing Domain 0 has Read access to the memory region
83036  */
83037 #define RDC_MRC_D0R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
83038 
83039 #define RDC_MRC_D1W_MASK                         (0x4U)
83040 #define RDC_MRC_D1W_SHIFT                        (2U)
83041 /*! D1W - Domain 1 Write Access to Region
83042  *  0b0..Processing Domain 1 does not have Write access to the memory region
83043  *  0b1..Processing Domain 1 has Write access to the memory region
83044  */
83045 #define RDC_MRC_D1W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
83046 
83047 #define RDC_MRC_D1R_MASK                         (0x8U)
83048 #define RDC_MRC_D1R_SHIFT                        (3U)
83049 /*! D1R - Domain 1 Read Access to Region
83050  *  0b0..Processing Domain 1 does not have Read access to the memory region
83051  *  0b1..Processing Domain 1 has Read access to the memory region
83052  */
83053 #define RDC_MRC_D1R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
83054 
83055 #define RDC_MRC_ENA_MASK                         (0x40000000U)
83056 #define RDC_MRC_ENA_SHIFT                        (30U)
83057 /*! ENA - Region Enable
83058  *  0b0..Memory region is not defined or restricted.
83059  *  0b1..Memory boundaries, domain permissions and controls are in effect.
83060  */
83061 #define RDC_MRC_ENA(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
83062 
83063 #define RDC_MRC_LCK_MASK                         (0x80000000U)
83064 #define RDC_MRC_LCK_SHIFT                        (31U)
83065 /*! LCK - Region Lock
83066  *  0b0..No Lock. All fields in this register may be modified.
83067  *  0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
83068  */
83069 #define RDC_MRC_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
83070 /*! @} */
83071 
83072 /* The count of RDC_MRC */
83073 #define RDC_MRC_COUNT                            (59U)
83074 
83075 /*! @name MRVS - Memory Region Violation Status */
83076 /*! @{ */
83077 
83078 #define RDC_MRVS_VDID_MASK                       (0x3U)
83079 #define RDC_MRVS_VDID_SHIFT                      (0U)
83080 /*! VDID - Violating Domain ID
83081  *  0b00..Processing Domain 0
83082  *  0b01..Processing Domain 1
83083  *  0b10..Reserved
83084  *  0b11..Reserved
83085  */
83086 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
83087 
83088 #define RDC_MRVS_AD_MASK                         (0x10U)
83089 #define RDC_MRVS_AD_SHIFT                        (4U)
83090 /*! AD - Access Denied
83091  */
83092 #define RDC_MRVS_AD(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
83093 
83094 #define RDC_MRVS_VADR_MASK                       (0xFFFFFFE0U)
83095 #define RDC_MRVS_VADR_SHIFT                      (5U)
83096 /*! VADR - Violating Address
83097  */
83098 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
83099 /*! @} */
83100 
83101 /* The count of RDC_MRVS */
83102 #define RDC_MRVS_COUNT                           (59U)
83103 
83104 
83105 /*!
83106  * @}
83107  */ /* end of group RDC_Register_Masks */
83108 
83109 
83110 /* RDC - Peripheral instance base addresses */
83111 /** Peripheral RDC base address */
83112 #define RDC_BASE                                 (0x40C78000u)
83113 /** Peripheral RDC base pointer */
83114 #define RDC                                      ((RDC_Type *)RDC_BASE)
83115 /** Array initializer of RDC peripheral base addresses */
83116 #define RDC_BASE_ADDRS                           { RDC_BASE }
83117 /** Array initializer of RDC peripheral base pointers */
83118 #define RDC_BASE_PTRS                            { RDC }
83119 /** Interrupt vectors for the RDC peripheral type */
83120 #define RDC_IRQS                                 { RDC_IRQn }
83121 
83122 /*!
83123  * @}
83124  */ /* end of group RDC_Peripheral_Access_Layer */
83125 
83126 
83127 /* ----------------------------------------------------------------------------
83128    -- RDC_SEMAPHORE Peripheral Access Layer
83129    ---------------------------------------------------------------------------- */
83130 
83131 /*!
83132  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
83133  * @{
83134  */
83135 
83136 /** RDC_SEMAPHORE - Register Layout Typedef */
83137 typedef struct {
83138   __IO uint8_t GATE[64];                           /**< Gate Register, array offset: 0x0, array step: 0x1 */
83139        uint8_t RESERVED_0[2];
83140   union {                                          /* offset: 0x42 */
83141     __IO uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
83142     __IO uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
83143   };
83144 } RDC_SEMAPHORE_Type;
83145 
83146 /* ----------------------------------------------------------------------------
83147    -- RDC_SEMAPHORE Register Masks
83148    ---------------------------------------------------------------------------- */
83149 
83150 /*!
83151  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
83152  * @{
83153  */
83154 
83155 /*! @name GATE - Gate Register */
83156 /*! @{ */
83157 
83158 #define RDC_SEMAPHORE_GATE_GTFSM_MASK            (0xFU)
83159 #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT           (0U)
83160 /*! GTFSM - Gate Finite State Machine.
83161  *  0b0000..The gate is unlocked (free).
83162  *  0b0001..The gate has been locked by processor with master_index = 0.
83163  *  0b0010..The gate has been locked by processor with master_index = 1.
83164  *  0b0011..The gate has been locked by processor with master_index = 2.
83165  *  0b0100..The gate has been locked by processor with master_index = 3.
83166  *  0b0101..The gate has been locked by processor with master_index = 4.
83167  *  0b0110..The gate has been locked by processor with master_index = 5.
83168  *  0b0111..The gate has been locked by processor with master_index = 6.
83169  *  0b1000..The gate has been locked by processor with master_index = 7.
83170  *  0b1001..The gate has been locked by processor with master_index = 8.
83171  *  0b1010..The gate has been locked by processor with master_index = 9.
83172  *  0b1011..The gate has been locked by processor with master_index = 10.
83173  *  0b1100..The gate has been locked by processor with master_index = 11.
83174  *  0b1101..The gate has been locked by processor with master_index = 12.
83175  *  0b1110..The gate has been locked by processor with master_index = 13.
83176  *  0b1111..The gate has been locked by processor with master_index = 14.
83177  */
83178 #define RDC_SEMAPHORE_GATE_GTFSM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)
83179 
83180 #define RDC_SEMAPHORE_GATE_LDOM_MASK             (0x30U)
83181 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT            (4U)
83182 /*! LDOM
83183  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
83184  *  0b01..The gate has been locked by domain 1.
83185  *  0b10..Reserved
83186  *  0b11..Reserved
83187  */
83188 #define RDC_SEMAPHORE_GATE_LDOM(x)               (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)
83189 /*! @} */
83190 
83191 /* The count of RDC_SEMAPHORE_GATE */
83192 #define RDC_SEMAPHORE_GATE_COUNT                 (64U)
83193 
83194 /*! @name RSTGT_R - Reset Gate Read */
83195 /*! @{ */
83196 
83197 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        (0xFU)
83198 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       (0U)
83199 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
83200 
83201 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        (0x30U)
83202 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       (4U)
83203 /*! RSTGSM
83204  *  0b00..Idle, waiting for the first data pattern write.
83205  *  0b01..Waiting for the second data pattern write.
83206  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
83207  *        this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
83208  *        for only one clock cycle. Software will never be able to observe this state.
83209  *  0b11..This state encoding is never used and therefore reserved.
83210  */
83211 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
83212 
83213 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        (0xFF00U)
83214 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       (8U)
83215 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
83216 /*! @} */
83217 
83218 /*! @name RSTGT_W - Reset Gate Write */
83219 /*! @{ */
83220 
83221 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        (0xFFU)
83222 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       (0U)
83223 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
83224 
83225 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        (0xFF00U)
83226 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       (8U)
83227 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
83228 /*! @} */
83229 
83230 
83231 /*!
83232  * @}
83233  */ /* end of group RDC_SEMAPHORE_Register_Masks */
83234 
83235 
83236 /* RDC_SEMAPHORE - Peripheral instance base addresses */
83237 /** Peripheral RDC_SEMAPHORE1 base address */
83238 #define RDC_SEMAPHORE1_BASE                      (0x40C44000u)
83239 /** Peripheral RDC_SEMAPHORE1 base pointer */
83240 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
83241 /** Peripheral RDC_SEMAPHORE2 base address */
83242 #define RDC_SEMAPHORE2_BASE                      (0x40CCC000u)
83243 /** Peripheral RDC_SEMAPHORE2 base pointer */
83244 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
83245 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
83246 #define RDC_SEMAPHORE_BASE_ADDRS                 { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
83247 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
83248 #define RDC_SEMAPHORE_BASE_PTRS                  { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
83249 
83250 /*!
83251  * @}
83252  */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
83253 
83254 
83255 /* ----------------------------------------------------------------------------
83256    -- RTWDOG Peripheral Access Layer
83257    ---------------------------------------------------------------------------- */
83258 
83259 /*!
83260  * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
83261  * @{
83262  */
83263 
83264 /** RTWDOG - Register Layout Typedef */
83265 typedef struct {
83266   __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
83267   __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
83268   __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
83269   __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
83270 } RTWDOG_Type;
83271 
83272 /* ----------------------------------------------------------------------------
83273    -- RTWDOG Register Masks
83274    ---------------------------------------------------------------------------- */
83275 
83276 /*!
83277  * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
83278  * @{
83279  */
83280 
83281 /*! @name CS - Watchdog Control and Status Register */
83282 /*! @{ */
83283 
83284 #define RTWDOG_CS_STOP_MASK                      (0x1U)
83285 #define RTWDOG_CS_STOP_SHIFT                     (0U)
83286 /*! STOP - Stop Enable
83287  *  0b0..Watchdog disabled in chip stop mode.
83288  *  0b1..Watchdog enabled in chip stop mode.
83289  */
83290 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
83291 
83292 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
83293 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
83294 /*! WAIT - Wait Enable
83295  *  0b0..Watchdog disabled in chip wait mode.
83296  *  0b1..Watchdog enabled in chip wait mode.
83297  */
83298 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
83299 
83300 #define RTWDOG_CS_DBG_MASK                       (0x4U)
83301 #define RTWDOG_CS_DBG_SHIFT                      (2U)
83302 /*! DBG - Debug Enable
83303  *  0b0..Watchdog disabled in chip debug mode.
83304  *  0b1..Watchdog enabled in chip debug mode.
83305  */
83306 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
83307 
83308 #define RTWDOG_CS_TST_MASK                       (0x18U)
83309 #define RTWDOG_CS_TST_SHIFT                      (3U)
83310 /*! TST - Watchdog Test
83311  *  0b00..Watchdog test mode disabled.
83312  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
83313  *        use this setting to indicate that the watchdog is functioning normally in user mode.
83314  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
83315  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
83316  */
83317 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
83318 
83319 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
83320 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
83321 /*! UPDATE - Allow updates
83322  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
83323  *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
83324  */
83325 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
83326 
83327 #define RTWDOG_CS_INT_MASK                       (0x40U)
83328 #define RTWDOG_CS_INT_SHIFT                      (6U)
83329 /*! INT - Watchdog Interrupt
83330  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
83331  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
83332  */
83333 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
83334 
83335 #define RTWDOG_CS_EN_MASK                        (0x80U)
83336 #define RTWDOG_CS_EN_SHIFT                       (7U)
83337 /*! EN - Watchdog Enable
83338  *  0b0..Watchdog disabled.
83339  *  0b1..Watchdog enabled.
83340  */
83341 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
83342 
83343 #define RTWDOG_CS_CLK_MASK                       (0x300U)
83344 #define RTWDOG_CS_CLK_SHIFT                      (8U)
83345 /*! CLK - Watchdog Clock
83346  */
83347 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
83348 
83349 #define RTWDOG_CS_RCS_MASK                       (0x400U)
83350 #define RTWDOG_CS_RCS_SHIFT                      (10U)
83351 /*! RCS - Reconfiguration Success
83352  *  0b0..Reconfiguring WDOG.
83353  *  0b1..Reconfiguration is successful.
83354  */
83355 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
83356 
83357 #define RTWDOG_CS_ULK_MASK                       (0x800U)
83358 #define RTWDOG_CS_ULK_SHIFT                      (11U)
83359 /*! ULK - Unlock status
83360  *  0b0..WDOG is locked.
83361  *  0b1..WDOG is unlocked.
83362  */
83363 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
83364 
83365 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
83366 #define RTWDOG_CS_PRES_SHIFT                     (12U)
83367 /*! PRES - Watchdog prescaler
83368  *  0b0..256 prescaler disabled.
83369  *  0b1..256 prescaler enabled.
83370  */
83371 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
83372 
83373 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
83374 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
83375 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
83376  *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
83377  *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
83378  */
83379 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
83380 
83381 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
83382 #define RTWDOG_CS_FLG_SHIFT                      (14U)
83383 /*! FLG - Watchdog Interrupt Flag
83384  *  0b0..No interrupt occurred.
83385  *  0b1..An interrupt occurred.
83386  */
83387 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
83388 
83389 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
83390 #define RTWDOG_CS_WIN_SHIFT                      (15U)
83391 /*! WIN - Watchdog Window
83392  *  0b0..Window mode disabled.
83393  *  0b1..Window mode enabled.
83394  */
83395 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
83396 /*! @} */
83397 
83398 /*! @name CNT - Watchdog Counter Register */
83399 /*! @{ */
83400 
83401 #define RTWDOG_CNT_CNTLOW_MASK                   (0xFFU)
83402 #define RTWDOG_CNT_CNTLOW_SHIFT                  (0U)
83403 /*! CNTLOW - Low byte of the Watchdog Counter
83404  */
83405 #define RTWDOG_CNT_CNTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
83406 
83407 #define RTWDOG_CNT_CNTHIGH_MASK                  (0xFF00U)
83408 #define RTWDOG_CNT_CNTHIGH_SHIFT                 (8U)
83409 /*! CNTHIGH - High byte of the Watchdog Counter
83410  */
83411 #define RTWDOG_CNT_CNTHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
83412 /*! @} */
83413 
83414 /*! @name TOVAL - Watchdog Timeout Value Register */
83415 /*! @{ */
83416 
83417 #define RTWDOG_TOVAL_TOVALLOW_MASK               (0xFFU)
83418 #define RTWDOG_TOVAL_TOVALLOW_SHIFT              (0U)
83419 /*! TOVALLOW - Low byte of the timeout value
83420  */
83421 #define RTWDOG_TOVAL_TOVALLOW(x)                 (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
83422 
83423 #define RTWDOG_TOVAL_TOVALHIGH_MASK              (0xFF00U)
83424 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT             (8U)
83425 /*! TOVALHIGH - High byte of the timeout value
83426  */
83427 #define RTWDOG_TOVAL_TOVALHIGH(x)                (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
83428 /*! @} */
83429 
83430 /*! @name WIN - Watchdog Window Register */
83431 /*! @{ */
83432 
83433 #define RTWDOG_WIN_WINLOW_MASK                   (0xFFU)
83434 #define RTWDOG_WIN_WINLOW_SHIFT                  (0U)
83435 /*! WINLOW - Low byte of Watchdog Window
83436  */
83437 #define RTWDOG_WIN_WINLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
83438 
83439 #define RTWDOG_WIN_WINHIGH_MASK                  (0xFF00U)
83440 #define RTWDOG_WIN_WINHIGH_SHIFT                 (8U)
83441 /*! WINHIGH - High byte of Watchdog Window
83442  */
83443 #define RTWDOG_WIN_WINHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
83444 /*! @} */
83445 
83446 
83447 /*!
83448  * @}
83449  */ /* end of group RTWDOG_Register_Masks */
83450 
83451 
83452 /* RTWDOG - Peripheral instance base addresses */
83453 /** Peripheral RTWDOG3 base address */
83454 #define RTWDOG3_BASE                             (0x40038000u)
83455 /** Peripheral RTWDOG3 base pointer */
83456 #define RTWDOG3                                  ((RTWDOG_Type *)RTWDOG3_BASE)
83457 /** Peripheral RTWDOG4 base address */
83458 #define RTWDOG4_BASE                             (0x40C10000u)
83459 /** Peripheral RTWDOG4 base pointer */
83460 #define RTWDOG4                                  ((RTWDOG_Type *)RTWDOG4_BASE)
83461 /** Array initializer of RTWDOG peripheral base addresses */
83462 #define RTWDOG_BASE_ADDRS                        { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
83463 /** Array initializer of RTWDOG peripheral base pointers */
83464 #define RTWDOG_BASE_PTRS                         { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
83465 /** Interrupt vectors for the RTWDOG peripheral type */
83466 #define RTWDOG_IRQS                              { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn }
83467 /* Extra definition */
83468 #define RTWDOG_UPDATE_KEY                        (0xD928C520U)
83469 #define RTWDOG_REFRESH_KEY                       (0xB480A602U)
83470 
83471 
83472 /*!
83473  * @}
83474  */ /* end of group RTWDOG_Peripheral_Access_Layer */
83475 
83476 
83477 /* ----------------------------------------------------------------------------
83478    -- SEMA4 Peripheral Access Layer
83479    ---------------------------------------------------------------------------- */
83480 
83481 /*!
83482  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
83483  * @{
83484  */
83485 
83486 /** SEMA4 - Register Layout Typedef */
83487 typedef struct {
83488   __IO uint8_t GATE[16];                           /**< Semaphores Gate n Register, array offset: 0x0, array step: 0x1 */
83489        uint8_t RESERVED_0[48];
83490   struct {                                         /* offset: 0x40, array step: 0x8 */
83491     __IO uint16_t CPINE;                             /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
83492          uint8_t RESERVED_0[6];
83493   } CPINE[2];
83494        uint8_t RESERVED_1[48];
83495   struct {                                         /* offset: 0x80, array step: 0x8 */
83496     __I  uint16_t CPNTF;                             /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
83497          uint8_t RESERVED_0[6];
83498   } CPNTF[2];
83499        uint8_t RESERVED_2[112];
83500   __IO uint16_t RSTGT;                             /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
83501        uint8_t RESERVED_3[2];
83502   __IO uint16_t RSTNTF;                            /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
83503 } SEMA4_Type;
83504 
83505 /* ----------------------------------------------------------------------------
83506    -- SEMA4 Register Masks
83507    ---------------------------------------------------------------------------- */
83508 
83509 /*!
83510  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
83511  * @{
83512  */
83513 
83514 /*! @name GATE - Semaphores Gate n Register */
83515 /*! @{ */
83516 
83517 #define SEMA4_GATE_GTFSM_MASK                    (0x3U)
83518 #define SEMA4_GATE_GTFSM_SHIFT                   (0U)
83519 /*! GTFSM - Gate Finite State Machine.
83520  *  0b00..The gate is unlocked (free).
83521  *  0b01..The gate has been locked by processor 0.
83522  *  0b10..The gate has been locked by processor 1.
83523  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
83524  *        operation" and do not affect the gate state machine.
83525  */
83526 #define SEMA4_GATE_GTFSM(x)                      (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)
83527 /*! @} */
83528 
83529 /* The count of SEMA4_GATE */
83530 #define SEMA4_GATE_COUNT                         (16U)
83531 
83532 /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
83533 /*! @{ */
83534 
83535 #define SEMA4_CPINE_INE7_MASK                    (0x1U)
83536 #define SEMA4_CPINE_INE7_SHIFT                   (0U)
83537 /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
83538  *    of an interrupt notification from a failed attempt to lock gate 7.
83539  *  0b0..The generation of the notification interrupt is disabled.
83540  *  0b1..The generation of the notification interrupt is enabled.
83541  */
83542 #define SEMA4_CPINE_INE7(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
83543 
83544 #define SEMA4_CPINE_INE6_MASK                    (0x2U)
83545 #define SEMA4_CPINE_INE6_SHIFT                   (1U)
83546 /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
83547  *    of an interrupt notification from a failed attempt to lock gate 6.
83548  *  0b0..The generation of the notification interrupt is disabled.
83549  *  0b1..The generation of the notification interrupt is enabled.
83550  */
83551 #define SEMA4_CPINE_INE6(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
83552 
83553 #define SEMA4_CPINE_INE5_MASK                    (0x4U)
83554 #define SEMA4_CPINE_INE5_SHIFT                   (2U)
83555 /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
83556  *    of an interrupt notification from a failed attempt to lock gate 5.
83557  *  0b0..The generation of the notification interrupt is disabled.
83558  *  0b1..The generation of the notification interrupt is enabled.
83559  */
83560 #define SEMA4_CPINE_INE5(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
83561 
83562 #define SEMA4_CPINE_INE4_MASK                    (0x8U)
83563 #define SEMA4_CPINE_INE4_SHIFT                   (3U)
83564 /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
83565  *    of an interrupt notification from a failed attempt to lock gate 4.
83566  *  0b0..The generation of the notification interrupt is disabled.
83567  *  0b1..The generation of the notification interrupt is enabled.
83568  */
83569 #define SEMA4_CPINE_INE4(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
83570 
83571 #define SEMA4_CPINE_INE3_MASK                    (0x10U)
83572 #define SEMA4_CPINE_INE3_SHIFT                   (4U)
83573 /*! INE3
83574  *  0b0..The generation of the notification interrupt is disabled.
83575  *  0b1..The generation of the notification interrupt is enabled.
83576  */
83577 #define SEMA4_CPINE_INE3(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
83578 
83579 #define SEMA4_CPINE_INE2_MASK                    (0x20U)
83580 #define SEMA4_CPINE_INE2_SHIFT                   (5U)
83581 /*! INE2
83582  *  0b0..The generation of the notification interrupt is disabled.
83583  *  0b1..The generation of the notification interrupt is enabled.
83584  */
83585 #define SEMA4_CPINE_INE2(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
83586 
83587 #define SEMA4_CPINE_INE1_MASK                    (0x40U)
83588 #define SEMA4_CPINE_INE1_SHIFT                   (6U)
83589 /*! INE1
83590  *  0b0..The generation of the notification interrupt is disabled.
83591  *  0b1..The generation of the notification interrupt is enabled.
83592  */
83593 #define SEMA4_CPINE_INE1(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
83594 
83595 #define SEMA4_CPINE_INE0_MASK                    (0x80U)
83596 #define SEMA4_CPINE_INE0_SHIFT                   (7U)
83597 /*! INE0
83598  *  0b0..The generation of the notification interrupt is disabled.
83599  *  0b1..The generation of the notification interrupt is enabled.
83600  */
83601 #define SEMA4_CPINE_INE0(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
83602 
83603 #define SEMA4_CPINE_INE15_MASK                   (0x100U)
83604 #define SEMA4_CPINE_INE15_SHIFT                  (8U)
83605 /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
83606  *    generation of an interrupt notification from a failed attempt to lock gate 15.
83607  *  0b0..The generation of the notification interrupt is disabled.
83608  *  0b1..The generation of the notification interrupt is enabled.
83609  */
83610 #define SEMA4_CPINE_INE15(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
83611 
83612 #define SEMA4_CPINE_INE14_MASK                   (0x200U)
83613 #define SEMA4_CPINE_INE14_SHIFT                  (9U)
83614 /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
83615  *    generation of an interrupt notification from a failed attempt to lock gate 14.
83616  *  0b0..The generation of the notification interrupt is disabled.
83617  *  0b1..The generation of the notification interrupt is enabled.
83618  */
83619 #define SEMA4_CPINE_INE14(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
83620 
83621 #define SEMA4_CPINE_INE13_MASK                   (0x400U)
83622 #define SEMA4_CPINE_INE13_SHIFT                  (10U)
83623 /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
83624  *    generation of an interrupt notification from a failed attempt to lock gate 13.
83625  *  0b0..The generation of the notification interrupt is disabled.
83626  *  0b1..The generation of the notification interrupt is enabled.
83627  */
83628 #define SEMA4_CPINE_INE13(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
83629 
83630 #define SEMA4_CPINE_INE12_MASK                   (0x800U)
83631 #define SEMA4_CPINE_INE12_SHIFT                  (11U)
83632 /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
83633  *    generation of an interrupt notification from a failed attempt to lock gate 12.
83634  *  0b0..The generation of the notification interrupt is disabled.
83635  *  0b1..The generation of the notification interrupt is enabled.
83636  */
83637 #define SEMA4_CPINE_INE12(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
83638 
83639 #define SEMA4_CPINE_INE11_MASK                   (0x1000U)
83640 #define SEMA4_CPINE_INE11_SHIFT                  (12U)
83641 /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
83642  *    generation of an interrupt notification from a failed attempt to lock gate 11.
83643  *  0b0..The generation of the notification interrupt is disabled.
83644  *  0b1..The generation of the notification interrupt is enabled.
83645  */
83646 #define SEMA4_CPINE_INE11(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
83647 
83648 #define SEMA4_CPINE_INE10_MASK                   (0x2000U)
83649 #define SEMA4_CPINE_INE10_SHIFT                  (13U)
83650 /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
83651  *    generation of an interrupt notification from a failed attempt to lock gate 10.
83652  *  0b0..The generation of the notification interrupt is disabled.
83653  *  0b1..The generation of the notification interrupt is enabled.
83654  */
83655 #define SEMA4_CPINE_INE10(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
83656 
83657 #define SEMA4_CPINE_INE9_MASK                    (0x4000U)
83658 #define SEMA4_CPINE_INE9_SHIFT                   (14U)
83659 /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
83660  *    of an interrupt notification from a failed attempt to lock gate 9.
83661  *  0b0..The generation of the notification interrupt is disabled.
83662  *  0b1..The generation of the notification interrupt is enabled.
83663  */
83664 #define SEMA4_CPINE_INE9(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
83665 
83666 #define SEMA4_CPINE_INE8_MASK                    (0x8000U)
83667 #define SEMA4_CPINE_INE8_SHIFT                   (15U)
83668 /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
83669  *    of an interrupt notification from a failed attempt to lock gate 8.
83670  *  0b0..The generation of the notification interrupt is disabled.
83671  *  0b1..The generation of the notification interrupt is enabled.
83672  */
83673 #define SEMA4_CPINE_INE8(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
83674 /*! @} */
83675 
83676 /* The count of SEMA4_CPINE */
83677 #define SEMA4_CPINE_COUNT                        (2U)
83678 
83679 /*! @name CPNTF - Semaphores Processor n IRQ Notification */
83680 /*! @{ */
83681 
83682 #define SEMA4_CPNTF_GN7_MASK                     (0x1U)
83683 #define SEMA4_CPNTF_GN7_SHIFT                    (0U)
83684 #define SEMA4_CPNTF_GN7(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
83685 
83686 #define SEMA4_CPNTF_GN6_MASK                     (0x2U)
83687 #define SEMA4_CPNTF_GN6_SHIFT                    (1U)
83688 #define SEMA4_CPNTF_GN6(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
83689 
83690 #define SEMA4_CPNTF_GN5_MASK                     (0x4U)
83691 #define SEMA4_CPNTF_GN5_SHIFT                    (2U)
83692 #define SEMA4_CPNTF_GN5(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
83693 
83694 #define SEMA4_CPNTF_GN4_MASK                     (0x8U)
83695 #define SEMA4_CPNTF_GN4_SHIFT                    (3U)
83696 #define SEMA4_CPNTF_GN4(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
83697 
83698 #define SEMA4_CPNTF_GN3_MASK                     (0x10U)
83699 #define SEMA4_CPNTF_GN3_SHIFT                    (4U)
83700 #define SEMA4_CPNTF_GN3(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
83701 
83702 #define SEMA4_CPNTF_GN2_MASK                     (0x20U)
83703 #define SEMA4_CPNTF_GN2_SHIFT                    (5U)
83704 #define SEMA4_CPNTF_GN2(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
83705 
83706 #define SEMA4_CPNTF_GN1_MASK                     (0x40U)
83707 #define SEMA4_CPNTF_GN1_SHIFT                    (6U)
83708 #define SEMA4_CPNTF_GN1(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
83709 
83710 #define SEMA4_CPNTF_GN0_MASK                     (0x80U)
83711 #define SEMA4_CPNTF_GN0_SHIFT                    (7U)
83712 #define SEMA4_CPNTF_GN0(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
83713 
83714 #define SEMA4_CPNTF_GN15_MASK                    (0x100U)
83715 #define SEMA4_CPNTF_GN15_SHIFT                   (8U)
83716 #define SEMA4_CPNTF_GN15(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
83717 
83718 #define SEMA4_CPNTF_GN14_MASK                    (0x200U)
83719 #define SEMA4_CPNTF_GN14_SHIFT                   (9U)
83720 #define SEMA4_CPNTF_GN14(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
83721 
83722 #define SEMA4_CPNTF_GN13_MASK                    (0x400U)
83723 #define SEMA4_CPNTF_GN13_SHIFT                   (10U)
83724 #define SEMA4_CPNTF_GN13(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
83725 
83726 #define SEMA4_CPNTF_GN12_MASK                    (0x800U)
83727 #define SEMA4_CPNTF_GN12_SHIFT                   (11U)
83728 #define SEMA4_CPNTF_GN12(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
83729 
83730 #define SEMA4_CPNTF_GN11_MASK                    (0x1000U)
83731 #define SEMA4_CPNTF_GN11_SHIFT                   (12U)
83732 #define SEMA4_CPNTF_GN11(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
83733 
83734 #define SEMA4_CPNTF_GN10_MASK                    (0x2000U)
83735 #define SEMA4_CPNTF_GN10_SHIFT                   (13U)
83736 #define SEMA4_CPNTF_GN10(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
83737 
83738 #define SEMA4_CPNTF_GN9_MASK                     (0x4000U)
83739 #define SEMA4_CPNTF_GN9_SHIFT                    (14U)
83740 #define SEMA4_CPNTF_GN9(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
83741 
83742 #define SEMA4_CPNTF_GN8_MASK                     (0x8000U)
83743 #define SEMA4_CPNTF_GN8_SHIFT                    (15U)
83744 #define SEMA4_CPNTF_GN8(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
83745 /*! @} */
83746 
83747 /* The count of SEMA4_CPNTF */
83748 #define SEMA4_CPNTF_COUNT                        (2U)
83749 
83750 /*! @name RSTGT - Semaphores (Secure) Reset Gate n */
83751 /*! @{ */
83752 
83753 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    (0xFFU)
83754 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   (0U)
83755 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
83756 
83757 #define SEMA4_RSTGT_RSTGTN_MASK                  (0xFF00U)
83758 #define SEMA4_RSTGT_RSTGTN_SHIFT                 (8U)
83759 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
83760 /*! @} */
83761 
83762 /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
83763 /*! @{ */
83764 
83765 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   (0xFFU)
83766 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  (0U)
83767 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
83768 
83769 #define SEMA4_RSTNTF_RSTNTN_MASK                 (0xFF00U)
83770 #define SEMA4_RSTNTF_RSTNTN_SHIFT                (8U)
83771 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
83772 /*! @} */
83773 
83774 
83775 /*!
83776  * @}
83777  */ /* end of group SEMA4_Register_Masks */
83778 
83779 
83780 /* SEMA4 - Peripheral instance base addresses */
83781 /** Peripheral SEMA4 base address */
83782 #define SEMA4_BASE                               (0x40CC8000u)
83783 /** Peripheral SEMA4 base pointer */
83784 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
83785 /** Array initializer of SEMA4 peripheral base addresses */
83786 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
83787 /** Array initializer of SEMA4 peripheral base pointers */
83788 #define SEMA4_BASE_PTRS                          { SEMA4 }
83789 
83790 /*!
83791  * @}
83792  */ /* end of group SEMA4_Peripheral_Access_Layer */
83793 
83794 
83795 /* ----------------------------------------------------------------------------
83796    -- SEMC Peripheral Access Layer
83797    ---------------------------------------------------------------------------- */
83798 
83799 /*!
83800  * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
83801  * @{
83802  */
83803 
83804 /** SEMC - Register Layout Typedef */
83805 typedef struct {
83806   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
83807   __IO uint32_t IOCR;                              /**< IO MUX Control Register, offset: 0x4 */
83808   __IO uint32_t BMCR0;                             /**< Bus (AXI) Master Control Register 0, offset: 0x8 */
83809   __IO uint32_t BMCR1;                             /**< Bus (AXI) Master Control Register 1, offset: 0xC */
83810   __IO uint32_t BR[9];                             /**< Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4 */
83811   __IO uint32_t DLLCR;                             /**< DLL Control Register, offset: 0x34 */
83812   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x38 */
83813   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x3C */
83814   __IO uint32_t SDRAMCR0;                          /**< SDRAM Control Register 0, offset: 0x40 */
83815   __IO uint32_t SDRAMCR1;                          /**< SDRAM Control Register 1, offset: 0x44 */
83816   __IO uint32_t SDRAMCR2;                          /**< SDRAM Control Register 2, offset: 0x48 */
83817   __IO uint32_t SDRAMCR3;                          /**< SDRAM Control Register 3, offset: 0x4C */
83818   __IO uint32_t NANDCR0;                           /**< NAND Control Register 0, offset: 0x50 */
83819   __IO uint32_t NANDCR1;                           /**< NAND Control Register 1, offset: 0x54 */
83820   __IO uint32_t NANDCR2;                           /**< NAND Control Register 2, offset: 0x58 */
83821   __IO uint32_t NANDCR3;                           /**< NAND Control Register 3, offset: 0x5C */
83822   __IO uint32_t NORCR0;                            /**< NOR Control Register 0, offset: 0x60 */
83823   __IO uint32_t NORCR1;                            /**< NOR Control Register 1, offset: 0x64 */
83824   __IO uint32_t NORCR2;                            /**< NOR Control Register 2, offset: 0x68 */
83825   __IO uint32_t NORCR3;                            /**< NOR Control Register 3, offset: 0x6C */
83826   __IO uint32_t SRAMCR0;                           /**< SRAM Control Register 0, offset: 0x70 */
83827   __IO uint32_t SRAMCR1;                           /**< SRAM Control Register 1, offset: 0x74 */
83828   __IO uint32_t SRAMCR2;                           /**< SRAM Control Register 2, offset: 0x78 */
83829        uint32_t SRAMCR3;                           /**< SRAM Control Register 3, offset: 0x7C */
83830   __IO uint32_t DBICR0;                            /**< DBI-B Control Register 0, offset: 0x80 */
83831   __IO uint32_t DBICR1;                            /**< DBI-B Control Register 1, offset: 0x84 */
83832   __IO uint32_t DBICR2;                            /**< DBI-B Control Register 2, offset: 0x88 */
83833        uint8_t RESERVED_0[4];
83834   __IO uint32_t IPCR0;                             /**< IP Command Control Register 0, offset: 0x90 */
83835   __IO uint32_t IPCR1;                             /**< IP Command Control Register 1, offset: 0x94 */
83836   __IO uint32_t IPCR2;                             /**< IP Command Control Register 2, offset: 0x98 */
83837   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0x9C */
83838   __IO uint32_t IPTXDAT;                           /**< TX DATA Register, offset: 0xA0 */
83839        uint8_t RESERVED_1[12];
83840   __I  uint32_t IPRXDAT;                           /**< RX DATA Register, offset: 0xB0 */
83841        uint8_t RESERVED_2[12];
83842   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xC0 */
83843        uint32_t STS1;                              /**< Status Register 1, offset: 0xC4 */
83844   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xC8 */
83845        uint32_t STS3;                              /**< Status Register 3, offset: 0xCC */
83846        uint32_t STS4;                              /**< Status Register 4, offset: 0xD0 */
83847        uint32_t STS5;                              /**< Status Register 5, offset: 0xD4 */
83848        uint32_t STS6;                              /**< Status Register 6, offset: 0xD8 */
83849        uint32_t STS7;                              /**< Status Register 7, offset: 0xDC */
83850        uint32_t STS8;                              /**< Status Register 8, offset: 0xE0 */
83851        uint32_t STS9;                              /**< Status Register 9, offset: 0xE4 */
83852        uint32_t STS10;                             /**< Status Register 10, offset: 0xE8 */
83853        uint32_t STS11;                             /**< Status Register 11, offset: 0xEC */
83854   __I  uint32_t STS12;                             /**< Status Register 12, offset: 0xF0 */
83855   __I  uint32_t STS13;                             /**< Status Register 13, offset: 0xF4 */
83856        uint32_t STS14;                             /**< Status Register 14, offset: 0xF8 */
83857        uint32_t STS15;                             /**< Status Register 15, offset: 0xFC */
83858   __IO uint32_t BR9;                               /**< Base Register 9, offset: 0x100 */
83859   __IO uint32_t BR10;                              /**< Base Register 10, offset: 0x104 */
83860   __IO uint32_t BR11;                              /**< Base Register 11, offset: 0x108 */
83861        uint8_t RESERVED_3[20];
83862   __IO uint32_t SRAMCR4;                           /**< SRAM Control Register 4, offset: 0x120 */
83863   __IO uint32_t SRAMCR5;                           /**< SRAM Control Register 5, offset: 0x124 */
83864   __IO uint32_t SRAMCR6;                           /**< SRAM Control Register 6, offset: 0x128 */
83865        uint8_t RESERVED_4[36];
83866   __IO uint32_t DCCR;                              /**< Delay Chain Control Register, offset: 0x150 */
83867 } SEMC_Type;
83868 
83869 /* ----------------------------------------------------------------------------
83870    -- SEMC Register Masks
83871    ---------------------------------------------------------------------------- */
83872 
83873 /*!
83874  * @addtogroup SEMC_Register_Masks SEMC Register Masks
83875  * @{
83876  */
83877 
83878 /*! @name MCR - Module Control Register */
83879 /*! @{ */
83880 
83881 #define SEMC_MCR_SWRST_MASK                      (0x1U)
83882 #define SEMC_MCR_SWRST_SHIFT                     (0U)
83883 /*! SWRST - Software Reset
83884  *  0b0..No reset
83885  *  0b1..Reset
83886  */
83887 #define SEMC_MCR_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
83888 
83889 #define SEMC_MCR_MDIS_MASK                       (0x2U)
83890 #define SEMC_MCR_MDIS_SHIFT                      (1U)
83891 /*! MDIS - Module Disable
83892  *  0b0..Module enabled
83893  *  0b1..Module disabled
83894  */
83895 #define SEMC_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
83896 
83897 #define SEMC_MCR_DQSMD_MASK                      (0x4U)
83898 #define SEMC_MCR_DQSMD_SHIFT                     (2U)
83899 /*! DQSMD - DQS (read strobe) mode
83900  *  0b0..Dummy read strobe loopbacked internally
83901  *  0b1..Dummy read strobe loopbacked from DQS pad
83902  */
83903 #define SEMC_MCR_DQSMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
83904 
83905 #define SEMC_MCR_WPOL0_MASK                      (0x40U)
83906 #define SEMC_MCR_WPOL0_SHIFT                     (6U)
83907 /*! WPOL0 - WAIT/RDY polarity for SRAM/NOR
83908  *  0b0..WAIT/RDY polarity is not changed.
83909  *  0b1..WAIT/RDY polarity is inverted.
83910  */
83911 #define SEMC_MCR_WPOL0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
83912 
83913 #define SEMC_MCR_WPOL1_MASK                      (0x80U)
83914 #define SEMC_MCR_WPOL1_SHIFT                     (7U)
83915 /*! WPOL1 - R/B# polarity for NAND device
83916  *  0b0..R/B# polarity is not changed.
83917  *  0b1..R/B# polarity is inverted.
83918  */
83919 #define SEMC_MCR_WPOL1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
83920 
83921 #define SEMC_MCR_CTO_MASK                        (0xFF0000U)
83922 #define SEMC_MCR_CTO_SHIFT                       (16U)
83923 /*! CTO - Command Execution timeout cycles
83924  */
83925 #define SEMC_MCR_CTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
83926 
83927 #define SEMC_MCR_BTO_MASK                        (0x1F000000U)
83928 #define SEMC_MCR_BTO_SHIFT                       (24U)
83929 /*! BTO - Bus timeout cycles
83930  *  0b00000..255*1
83931  *  0b00001..255*2
83932  *  0b11111..255*231
83933  */
83934 #define SEMC_MCR_BTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
83935 /*! @} */
83936 
83937 /*! @name IOCR - IO MUX Control Register */
83938 /*! @{ */
83939 
83940 #define SEMC_IOCR_MUX_A8_MASK                    (0xFU)
83941 #define SEMC_IOCR_MUX_A8_SHIFT                   (0U)
83942 /*! MUX_A8 - SEMC_ADDR08 output selection
83943  *  0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
83944  *  0b0100..NAND CE#
83945  *  0b0101..NOR CE#
83946  *  0b0110..SRAM CE# 0
83947  *  0b0111..DBI CSX
83948  *  0b1000..SRAM CE# 1
83949  *  0b1001..SRAM CE# 2
83950  *  0b1010..SRAM CE# 3
83951  *  0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
83952  */
83953 #define SEMC_IOCR_MUX_A8(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
83954 
83955 #define SEMC_IOCR_MUX_CSX0_MASK                  (0xF0U)
83956 #define SEMC_IOCR_MUX_CSX0_SHIFT                 (4U)
83957 /*! MUX_CSX0 - SEMC_CSX0 output selection
83958  *  0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode
83959  *  0b0001..SDRAM CS1
83960  *  0b0010..SDRAM CS2
83961  *  0b0011..SDRAM CS3
83962  *  0b0100..NAND CE#
83963  *  0b0101..NOR CE#
83964  *  0b0110..SRAM CE# 0
83965  *  0b0111..DBI CSX
83966  *  0b1000..SRAM CE# 1
83967  *  0b1001..SRAM CE# 2
83968  *  0b1010..SRAM CE# 3
83969  *  0b1011-0b1111..NOR/SRAM Address bit 24 (A24)
83970  */
83971 #define SEMC_IOCR_MUX_CSX0(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
83972 
83973 #define SEMC_IOCR_MUX_CSX1_MASK                  (0xF00U)
83974 #define SEMC_IOCR_MUX_CSX1_SHIFT                 (8U)
83975 /*! MUX_CSX1 - SEMC_CSX1 output selection
83976  *  0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode
83977  *  0b0001..SDRAM CS1
83978  *  0b0010..SDRAM CS2
83979  *  0b0011..SDRAM CS3
83980  *  0b0100..NAND CE#
83981  *  0b0101..NOR CE#
83982  *  0b0110..SRAM CE# 0
83983  *  0b0111..DBI CSX
83984  *  0b1000..SRAM CE# 1
83985  *  0b1001..SRAM CE# 2
83986  *  0b1010..SRAM CE# 3
83987  *  0b1011-0b1111..NOR/SRAM Address bit 25 (A25)
83988  */
83989 #define SEMC_IOCR_MUX_CSX1(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
83990 
83991 #define SEMC_IOCR_MUX_CSX2_MASK                  (0xF000U)
83992 #define SEMC_IOCR_MUX_CSX2_SHIFT                 (12U)
83993 /*! MUX_CSX2 - SEMC_CSX2 output selection
83994  *  0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode
83995  *  0b0001..SDRAM CS1
83996  *  0b0010..SDRAM CS2
83997  *  0b0011..SDRAM CS3
83998  *  0b0100..NAND CE#
83999  *  0b0101..NOR CE#
84000  *  0b0110..SRAM CE# 0
84001  *  0b0111..DBI CSX
84002  *  0b1000..SRAM CE# 1
84003  *  0b1001..SRAM CE# 2
84004  *  0b1010..SRAM CE# 3
84005  *  0b1011-0b1111..NOR/SRAM Address bit 26 (A26)
84006  */
84007 #define SEMC_IOCR_MUX_CSX2(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
84008 
84009 #define SEMC_IOCR_MUX_CSX3_MASK                  (0xF0000U)
84010 #define SEMC_IOCR_MUX_CSX3_SHIFT                 (16U)
84011 /*! MUX_CSX3 - SEMC_CSX3 output selection
84012  *  0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
84013  *  0b0001..SDRAM CS1
84014  *  0b0010..SDRAM CS2
84015  *  0b0011..SDRAM CS3
84016  *  0b0100..NAND CE#
84017  *  0b0101..NOR CE#
84018  *  0b0110..SRAM CE# 0
84019  *  0b0111..DBI CSX
84020  *  0b1000..SRAM CE# 1
84021  *  0b1001..SRAM CE# 2
84022  *  0b1010..SRAM CE# 3
84023  *  0b1011-0b1111..NOR/SRAM Address bit 27 (A27)
84024  */
84025 #define SEMC_IOCR_MUX_CSX3(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
84026 
84027 #define SEMC_IOCR_MUX_RDY_MASK                   (0xF00000U)
84028 #define SEMC_IOCR_MUX_RDY_SHIFT                  (20U)
84029 /*! MUX_RDY - SEMC_RDY function selection
84030  *  0b0000..NAND R/B# input
84031  *  0b0001..SDRAM CS1
84032  *  0b0010..SDRAM CS2
84033  *  0b0011..SDRAM CS3
84034  *  0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
84035  *  0b0101..NOR CE#
84036  *  0b0110..SRAM CE# 0
84037  *  0b0111..DBI CSX
84038  *  0b1000..SRAM CE# 1
84039  *  0b1001..SRAM CE# 2
84040  *  0b1010..SRAM CE# 3
84041  *  0b1011-0b1111..NOR/SRAM Address bit 27
84042  */
84043 #define SEMC_IOCR_MUX_RDY(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
84044 
84045 #define SEMC_IOCR_MUX_CLKX0_MASK                 (0x3000000U)
84046 #define SEMC_IOCR_MUX_CLKX0_SHIFT                (24U)
84047 /*! MUX_CLKX0 - SEMC_CLKX0 function selection
84048  *  0b00..Keep low
84049  *  0b01..NOR clock
84050  *  0b10..SRAM clock
84051  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
84052  */
84053 #define SEMC_IOCR_MUX_CLKX0(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
84054 
84055 #define SEMC_IOCR_MUX_CLKX1_MASK                 (0xC000000U)
84056 #define SEMC_IOCR_MUX_CLKX1_SHIFT                (26U)
84057 /*! MUX_CLKX1 - SEMC_CLKX1 function selection
84058  *  0b00..Keep low
84059  *  0b01..NOR clock
84060  *  0b10..SRAM clock
84061  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
84062  */
84063 #define SEMC_IOCR_MUX_CLKX1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
84064 
84065 #define SEMC_IOCR_CLKX0_AO_MASK                  (0x10000000U)
84066 #define SEMC_IOCR_CLKX0_AO_SHIFT                 (28U)
84067 /*! CLKX0_AO - SEMC_CLKX0 Always On
84068  *  0b0..SEMC_CLKX0 is controlled by MUX_CLKX0
84069  *  0b1..SEMC_CLKX0 is always on
84070  */
84071 #define SEMC_IOCR_CLKX0_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK)
84072 
84073 #define SEMC_IOCR_CLKX1_AO_MASK                  (0x20000000U)
84074 #define SEMC_IOCR_CLKX1_AO_SHIFT                 (29U)
84075 /*! CLKX1_AO - SEMC_CLKX1 Always On
84076  *  0b0..SEMC_CLKX1 is controlled by MUX_CLKX1
84077  *  0b1..SEMC_CLKX1 is always on
84078  */
84079 #define SEMC_IOCR_CLKX1_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK)
84080 /*! @} */
84081 
84082 /*! @name BMCR0 - Bus (AXI) Master Control Register 0 */
84083 /*! @{ */
84084 
84085 #define SEMC_BMCR0_WQOS_MASK                     (0xFU)
84086 #define SEMC_BMCR0_WQOS_SHIFT                    (0U)
84087 /*! WQOS - Weight of QOS
84088  */
84089 #define SEMC_BMCR0_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
84090 
84091 #define SEMC_BMCR0_WAGE_MASK                     (0xF0U)
84092 #define SEMC_BMCR0_WAGE_SHIFT                    (4U)
84093 /*! WAGE - Weight of AGE
84094  */
84095 #define SEMC_BMCR0_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
84096 
84097 #define SEMC_BMCR0_WSH_MASK                      (0xFF00U)
84098 #define SEMC_BMCR0_WSH_SHIFT                     (8U)
84099 /*! WSH - Weight of Slave Hit without read/write switch
84100  */
84101 #define SEMC_BMCR0_WSH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
84102 
84103 #define SEMC_BMCR0_WRWS_MASK                     (0xFF0000U)
84104 #define SEMC_BMCR0_WRWS_SHIFT                    (16U)
84105 /*! WRWS - Weight of slave hit with Read/Write Switch
84106  */
84107 #define SEMC_BMCR0_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
84108 /*! @} */
84109 
84110 /*! @name BMCR1 - Bus (AXI) Master Control Register 1 */
84111 /*! @{ */
84112 
84113 #define SEMC_BMCR1_WQOS_MASK                     (0xFU)
84114 #define SEMC_BMCR1_WQOS_SHIFT                    (0U)
84115 /*! WQOS - Weight of QOS
84116  */
84117 #define SEMC_BMCR1_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
84118 
84119 #define SEMC_BMCR1_WAGE_MASK                     (0xF0U)
84120 #define SEMC_BMCR1_WAGE_SHIFT                    (4U)
84121 /*! WAGE - Weight of AGE
84122  */
84123 #define SEMC_BMCR1_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
84124 
84125 #define SEMC_BMCR1_WPH_MASK                      (0xFF00U)
84126 #define SEMC_BMCR1_WPH_SHIFT                     (8U)
84127 /*! WPH - Weight of Page Hit
84128  */
84129 #define SEMC_BMCR1_WPH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
84130 
84131 #define SEMC_BMCR1_WRWS_MASK                     (0xFF0000U)
84132 #define SEMC_BMCR1_WRWS_SHIFT                    (16U)
84133 /*! WRWS - Weight of slave hit without Read/Write Switch
84134  */
84135 #define SEMC_BMCR1_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
84136 
84137 #define SEMC_BMCR1_WBR_MASK                      (0xFF000000U)
84138 #define SEMC_BMCR1_WBR_SHIFT                     (24U)
84139 /*! WBR - Weight of Bank Rotation
84140  */
84141 #define SEMC_BMCR1_WBR(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
84142 /*! @} */
84143 
84144 /*! @name BR - Base Register 0..Base Register 8 */
84145 /*! @{ */
84146 
84147 #define SEMC_BR_VLD_MASK                         (0x1U)
84148 #define SEMC_BR_VLD_SHIFT                        (0U)
84149 /*! VLD - Valid
84150  *  0b0..The memory is invalid, can not be accessed.
84151  *  0b1..The memory is valid, can be accessed.
84152  */
84153 #define SEMC_BR_VLD(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
84154 
84155 #define SEMC_BR_MS_MASK                          (0x3EU)
84156 #define SEMC_BR_MS_SHIFT                         (1U)
84157 /*! MS - Memory size
84158  *  0b00000..4KB
84159  *  0b00001..8KB
84160  *  0b00010..16KB
84161  *  0b00011..32KB
84162  *  0b00100..64KB
84163  *  0b00101..128KB
84164  *  0b00110..256KB
84165  *  0b00111..512KB
84166  *  0b01000..1MB
84167  *  0b01001..2MB
84168  *  0b01010..4MB
84169  *  0b01011..8MB
84170  *  0b01100..16MB
84171  *  0b01101..32MB
84172  *  0b01110..64MB
84173  *  0b01111..128MB
84174  *  0b10000..256MB
84175  *  0b10001..512MB
84176  *  0b10010..1GB
84177  *  0b10011..2GB
84178  *  0b10100-0b11111..4GB
84179  */
84180 #define SEMC_BR_MS(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
84181 
84182 #define SEMC_BR_BA_MASK                          (0xFFFFF000U)
84183 #define SEMC_BR_BA_SHIFT                         (12U)
84184 /*! BA - Base Address
84185  */
84186 #define SEMC_BR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
84187 /*! @} */
84188 
84189 /* The count of SEMC_BR */
84190 #define SEMC_BR_COUNT                            (9U)
84191 
84192 /*! @name DLLCR - DLL Control Register */
84193 /*! @{ */
84194 
84195 #define SEMC_DLLCR_DLLEN_MASK                    (0x1U)
84196 #define SEMC_DLLCR_DLLEN_SHIFT                   (0U)
84197 /*! DLLEN - DLL calibration enable
84198  *  0b0..DLL calibration is disabled.
84199  *  0b1..DLL calibration is enabled.
84200  */
84201 #define SEMC_DLLCR_DLLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
84202 
84203 #define SEMC_DLLCR_DLLRESET_MASK                 (0x2U)
84204 #define SEMC_DLLCR_DLLRESET_SHIFT                (1U)
84205 /*! DLLRESET - DLL Reset
84206  *  0b0..DLL is not reset.
84207  *  0b1..DLL is reset.
84208  */
84209 #define SEMC_DLLCR_DLLRESET(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
84210 
84211 #define SEMC_DLLCR_SLVDLYTARGET_MASK             (0x78U)
84212 #define SEMC_DLLCR_SLVDLYTARGET_SHIFT            (3U)
84213 /*! SLVDLYTARGET - Delay Target for Slave
84214  */
84215 #define SEMC_DLLCR_SLVDLYTARGET(x)               (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
84216 
84217 #define SEMC_DLLCR_OVRDEN_MASK                   (0x100U)
84218 #define SEMC_DLLCR_OVRDEN_SHIFT                  (8U)
84219 /*! OVRDEN - Override Enable
84220  *  0b0..The delay cell number is not overridden.
84221  *  0b1..The delay cell number is overridden.
84222  */
84223 #define SEMC_DLLCR_OVRDEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
84224 
84225 #define SEMC_DLLCR_OVRDVAL_MASK                  (0x7E00U)
84226 #define SEMC_DLLCR_OVRDVAL_SHIFT                 (9U)
84227 /*! OVRDVAL - Override Value
84228  */
84229 #define SEMC_DLLCR_OVRDVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
84230 /*! @} */
84231 
84232 /*! @name INTEN - Interrupt Enable Register */
84233 /*! @{ */
84234 
84235 #define SEMC_INTEN_IPCMDDONEEN_MASK              (0x1U)
84236 #define SEMC_INTEN_IPCMDDONEEN_SHIFT             (0U)
84237 /*! IPCMDDONEEN - IP command done interrupt enable
84238  *  0b0..Interrupt is disabled
84239  *  0b1..Interrupt is enabled
84240  */
84241 #define SEMC_INTEN_IPCMDDONEEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
84242 
84243 #define SEMC_INTEN_IPCMDERREN_MASK               (0x2U)
84244 #define SEMC_INTEN_IPCMDERREN_SHIFT              (1U)
84245 /*! IPCMDERREN - IP command error interrupt enable
84246  *  0b0..Interrupt is disabled
84247  *  0b1..Interrupt is enabled
84248  */
84249 #define SEMC_INTEN_IPCMDERREN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
84250 
84251 #define SEMC_INTEN_AXICMDERREN_MASK              (0x4U)
84252 #define SEMC_INTEN_AXICMDERREN_SHIFT             (2U)
84253 /*! AXICMDERREN - AXI command error interrupt enable
84254  *  0b0..Interrupt is disabled
84255  *  0b1..Interrupt is enabled
84256  */
84257 #define SEMC_INTEN_AXICMDERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
84258 
84259 #define SEMC_INTEN_AXIBUSERREN_MASK              (0x8U)
84260 #define SEMC_INTEN_AXIBUSERREN_SHIFT             (3U)
84261 /*! AXIBUSERREN - AXI bus error interrupt enable
84262  *  0b0..Interrupt is disabled
84263  *  0b1..Interrupt is enabled
84264  */
84265 #define SEMC_INTEN_AXIBUSERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
84266 
84267 #define SEMC_INTEN_NDPAGEENDEN_MASK              (0x10U)
84268 #define SEMC_INTEN_NDPAGEENDEN_SHIFT             (4U)
84269 /*! NDPAGEENDEN - NAND page end interrupt enable
84270  *  0b0..Interrupt is disabled
84271  *  0b1..Interrupt is enabled
84272  */
84273 #define SEMC_INTEN_NDPAGEENDEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
84274 
84275 #define SEMC_INTEN_NDNOPENDEN_MASK               (0x20U)
84276 #define SEMC_INTEN_NDNOPENDEN_SHIFT              (5U)
84277 /*! NDNOPENDEN - NAND no pending AXI access interrupt enable
84278  *  0b0..Interrupt is disabled
84279  *  0b1..Interrupt is enabled
84280  */
84281 #define SEMC_INTEN_NDNOPENDEN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
84282 /*! @} */
84283 
84284 /*! @name INTR - Interrupt Register */
84285 /*! @{ */
84286 
84287 #define SEMC_INTR_IPCMDDONE_MASK                 (0x1U)
84288 #define SEMC_INTR_IPCMDDONE_SHIFT                (0U)
84289 /*! IPCMDDONE - IP command normal done interrupt
84290  *  0b0..IP command is not done.
84291  *  0b1..IP command is done.
84292  */
84293 #define SEMC_INTR_IPCMDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
84294 
84295 #define SEMC_INTR_IPCMDERR_MASK                  (0x2U)
84296 #define SEMC_INTR_IPCMDERR_SHIFT                 (1U)
84297 /*! IPCMDERR - IP command error done interrupt
84298  *  0b0..No IP command error.
84299  *  0b1..IP command error occurs.
84300  */
84301 #define SEMC_INTR_IPCMDERR(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
84302 
84303 #define SEMC_INTR_AXICMDERR_MASK                 (0x4U)
84304 #define SEMC_INTR_AXICMDERR_SHIFT                (2U)
84305 /*! AXICMDERR - AXI command error interrupt
84306  *  0b0..No AXI command error.
84307  *  0b1..AXI command error occurs.
84308  */
84309 #define SEMC_INTR_AXICMDERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
84310 
84311 #define SEMC_INTR_AXIBUSERR_MASK                 (0x8U)
84312 #define SEMC_INTR_AXIBUSERR_SHIFT                (3U)
84313 /*! AXIBUSERR - AXI bus error interrupt
84314  *  0b0..No AXI bus error.
84315  *  0b1..AXI bus error occurs.
84316  */
84317 #define SEMC_INTR_AXIBUSERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
84318 
84319 #define SEMC_INTR_NDPAGEEND_MASK                 (0x10U)
84320 #define SEMC_INTR_NDPAGEEND_SHIFT                (4U)
84321 /*! NDPAGEEND - NAND page end interrupt
84322  *  0b0..The last address of main space in the NAND is not written by AXI command.
84323  *  0b1..The last address of main space in the NAND is written by AXI command.
84324  */
84325 #define SEMC_INTR_NDPAGEEND(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
84326 
84327 #define SEMC_INTR_NDNOPEND_MASK                  (0x20U)
84328 #define SEMC_INTR_NDNOPEND_SHIFT                 (5U)
84329 /*! NDNOPEND - NAND no pending AXI write transaction interrupt
84330  *  0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue.
84331  *  0b1..All NAND AXI write pending transactions are finished.
84332  */
84333 #define SEMC_INTR_NDNOPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
84334 /*! @} */
84335 
84336 /*! @name SDRAMCR0 - SDRAM Control Register 0 */
84337 /*! @{ */
84338 
84339 #define SEMC_SDRAMCR0_PS_MASK                    (0x3U)
84340 #define SEMC_SDRAMCR0_PS_SHIFT                   (0U)
84341 /*! PS - Port Size
84342  *  0b00..8bit
84343  *  0b01..16bit
84344  *  0b10..32bit
84345  *  0b11..Reserved
84346  */
84347 #define SEMC_SDRAMCR0_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
84348 
84349 #define SEMC_SDRAMCR0_BL_MASK                    (0x70U)
84350 #define SEMC_SDRAMCR0_BL_SHIFT                   (4U)
84351 /*! BL - Burst Length
84352  *  0b000..1
84353  *  0b001..2
84354  *  0b010..4
84355  *  0b011..8
84356  *  0b100..8
84357  *  0b101..8
84358  *  0b110..8
84359  *  0b111..8
84360  */
84361 #define SEMC_SDRAMCR0_BL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
84362 
84363 #define SEMC_SDRAMCR0_COL8_MASK                  (0x80U)
84364 #define SEMC_SDRAMCR0_COL8_SHIFT                 (7U)
84365 /*! COL8 - Column 8 selection
84366  *  0b0..Column address bit number is decided by COL field.
84367  *  0b1..Column address bit number is 8. COL field is ignored.
84368  */
84369 #define SEMC_SDRAMCR0_COL8(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
84370 
84371 #define SEMC_SDRAMCR0_COL_MASK                   (0x300U)
84372 #define SEMC_SDRAMCR0_COL_SHIFT                  (8U)
84373 /*! COL - Column address bit number
84374  *  0b00..12
84375  *  0b01..11
84376  *  0b10..10
84377  *  0b11..9
84378  */
84379 #define SEMC_SDRAMCR0_COL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
84380 
84381 #define SEMC_SDRAMCR0_CL_MASK                    (0xC00U)
84382 #define SEMC_SDRAMCR0_CL_SHIFT                   (10U)
84383 /*! CL - CAS Latency
84384  *  0b00..1
84385  *  0b01..1
84386  *  0b10..2
84387  *  0b11..3
84388  */
84389 #define SEMC_SDRAMCR0_CL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
84390 
84391 #define SEMC_SDRAMCR0_BANK2_MASK                 (0x4000U)
84392 #define SEMC_SDRAMCR0_BANK2_SHIFT                (14U)
84393 /*! BANK2 - 2 Bank selection bit
84394  *  0b0..SDRAM device has 4 banks.
84395  *  0b1..SDRAM device has 2 banks.
84396  */
84397 #define SEMC_SDRAMCR0_BANK2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
84398 /*! @} */
84399 
84400 /*! @name SDRAMCR1 - SDRAM Control Register 1 */
84401 /*! @{ */
84402 
84403 #define SEMC_SDRAMCR1_PRE2ACT_MASK               (0xFU)
84404 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT              (0U)
84405 /*! PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time
84406  */
84407 #define SEMC_SDRAMCR1_PRE2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
84408 
84409 #define SEMC_SDRAMCR1_ACT2RW_MASK                (0xF0U)
84410 #define SEMC_SDRAMCR1_ACT2RW_SHIFT               (4U)
84411 /*! ACT2RW - ACTIVE to READ/WRITE delay
84412  */
84413 #define SEMC_SDRAMCR1_ACT2RW(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
84414 
84415 #define SEMC_SDRAMCR1_RFRC_MASK                  (0x1F00U)
84416 #define SEMC_SDRAMCR1_RFRC_SHIFT                 (8U)
84417 /*! RFRC - REFRESH recovery time
84418  */
84419 #define SEMC_SDRAMCR1_RFRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
84420 
84421 #define SEMC_SDRAMCR1_WRC_MASK                   (0xE000U)
84422 #define SEMC_SDRAMCR1_WRC_SHIFT                  (13U)
84423 /*! WRC - WRITE recovery time
84424  */
84425 #define SEMC_SDRAMCR1_WRC(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
84426 
84427 #define SEMC_SDRAMCR1_CKEOFF_MASK                (0xF0000U)
84428 #define SEMC_SDRAMCR1_CKEOFF_SHIFT               (16U)
84429 /*! CKEOFF - CKE off minimum time
84430  */
84431 #define SEMC_SDRAMCR1_CKEOFF(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
84432 
84433 #define SEMC_SDRAMCR1_ACT2PRE_MASK               (0xF00000U)
84434 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT              (20U)
84435 /*! ACT2PRE - ACTIVE to PRECHARGE minimum time
84436  */
84437 #define SEMC_SDRAMCR1_ACT2PRE(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
84438 /*! @} */
84439 
84440 /*! @name SDRAMCR2 - SDRAM Control Register 2 */
84441 /*! @{ */
84442 
84443 #define SEMC_SDRAMCR2_SRRC_MASK                  (0xFFU)
84444 #define SEMC_SDRAMCR2_SRRC_SHIFT                 (0U)
84445 /*! SRRC - SELF REFRESH recovery time
84446  */
84447 #define SEMC_SDRAMCR2_SRRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
84448 
84449 #define SEMC_SDRAMCR2_REF2REF_MASK               (0xFF00U)
84450 #define SEMC_SDRAMCR2_REF2REF_SHIFT              (8U)
84451 /*! REF2REF - REFRESH to REFRESH delay
84452  */
84453 #define SEMC_SDRAMCR2_REF2REF(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
84454 
84455 #define SEMC_SDRAMCR2_ACT2ACT_MASK               (0xFF0000U)
84456 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT              (16U)
84457 /*! ACT2ACT - ACTIVE to ACTIVE delay
84458  */
84459 #define SEMC_SDRAMCR2_ACT2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
84460 
84461 #define SEMC_SDRAMCR2_ITO_MASK                   (0xFF000000U)
84462 #define SEMC_SDRAMCR2_ITO_SHIFT                  (24U)
84463 /*! ITO - SDRAM idle timeout
84464  *  0b00000000..IDLE timeout period is 256*Prescale period.
84465  *  0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
84466  */
84467 #define SEMC_SDRAMCR2_ITO(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
84468 /*! @} */
84469 
84470 /*! @name SDRAMCR3 - SDRAM Control Register 3 */
84471 /*! @{ */
84472 
84473 #define SEMC_SDRAMCR3_REN_MASK                   (0x1U)
84474 #define SEMC_SDRAMCR3_REN_SHIFT                  (0U)
84475 /*! REN - Refresh enable
84476  *  0b0..The SEMC does not send AUTO REFRESH command automatically
84477  *  0b1..The SEMC sends AUTO REFRESH command automatically
84478  */
84479 #define SEMC_SDRAMCR3_REN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
84480 
84481 #define SEMC_SDRAMCR3_REBL_MASK                  (0xEU)
84482 #define SEMC_SDRAMCR3_REBL_SHIFT                 (1U)
84483 /*! REBL - Refresh burst length
84484  *  0b000..1
84485  *  0b001..2
84486  *  0b010..3
84487  *  0b011..4
84488  *  0b100..5
84489  *  0b101..6
84490  *  0b110..7
84491  *  0b111..8
84492  */
84493 #define SEMC_SDRAMCR3_REBL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
84494 
84495 #define SEMC_SDRAMCR3_PRESCALE_MASK              (0xFF00U)
84496 #define SEMC_SDRAMCR3_PRESCALE_SHIFT             (8U)
84497 /*! PRESCALE - Prescaler period
84498  *  0b00000000..(256*16+1) clock cycles
84499  *  0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
84500  */
84501 #define SEMC_SDRAMCR3_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
84502 
84503 #define SEMC_SDRAMCR3_RT_MASK                    (0xFF0000U)
84504 #define SEMC_SDRAMCR3_RT_SHIFT                   (16U)
84505 /*! RT - Refresh timer period
84506  *  0b00000000..(256+1)*(Prescaler period)
84507  *  0b00000001-0b11111111..(RT+1)*(Prescaler period)
84508  */
84509 #define SEMC_SDRAMCR3_RT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
84510 
84511 #define SEMC_SDRAMCR3_UT_MASK                    (0xFF000000U)
84512 #define SEMC_SDRAMCR3_UT_SHIFT                   (24U)
84513 /*! UT - Urgent refresh threshold
84514  *  0b00000000..256*(Prescaler period)
84515  *  0b00000001-0b11111111..UT*(Prescaler period)
84516  */
84517 #define SEMC_SDRAMCR3_UT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
84518 /*! @} */
84519 
84520 /*! @name NANDCR0 - NAND Control Register 0 */
84521 /*! @{ */
84522 
84523 #define SEMC_NANDCR0_PS_MASK                     (0x1U)
84524 #define SEMC_NANDCR0_PS_SHIFT                    (0U)
84525 /*! PS - Port Size
84526  *  0b0..8bit
84527  *  0b1..16bit
84528  */
84529 #define SEMC_NANDCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
84530 
84531 #define SEMC_NANDCR0_SYNCEN_MASK                 (0x2U)
84532 #define SEMC_NANDCR0_SYNCEN_SHIFT                (1U)
84533 /*! SYNCEN - Synchronous Mode Enable
84534  *  0b0..Asynchronous mode is enabled.
84535  *  0b1..Synchronous mode is enabled.
84536  */
84537 #define SEMC_NANDCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
84538 
84539 #define SEMC_NANDCR0_BL_MASK                     (0x70U)
84540 #define SEMC_NANDCR0_BL_SHIFT                    (4U)
84541 /*! BL - Burst Length
84542  *  0b000..1
84543  *  0b001..2
84544  *  0b010..4
84545  *  0b011..8
84546  *  0b100..16
84547  *  0b101..32
84548  *  0b110..64
84549  *  0b111..64
84550  */
84551 #define SEMC_NANDCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
84552 
84553 #define SEMC_NANDCR0_EDO_MASK                    (0x80U)
84554 #define SEMC_NANDCR0_EDO_SHIFT                   (7U)
84555 /*! EDO - EDO mode enabled
84556  *  0b0..EDO mode disabled
84557  *  0b1..EDO mode enabled
84558  */
84559 #define SEMC_NANDCR0_EDO(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
84560 
84561 #define SEMC_NANDCR0_COL_MASK                    (0x700U)
84562 #define SEMC_NANDCR0_COL_SHIFT                   (8U)
84563 /*! COL - Column address bit number
84564  *  0b000..16
84565  *  0b001..15
84566  *  0b010..14
84567  *  0b011..13
84568  *  0b100..12
84569  *  0b101..11
84570  *  0b110..10
84571  *  0b111..9
84572  */
84573 #define SEMC_NANDCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
84574 /*! @} */
84575 
84576 /*! @name NANDCR1 - NAND Control Register 1 */
84577 /*! @{ */
84578 
84579 #define SEMC_NANDCR1_CES_MASK                    (0xFU)
84580 #define SEMC_NANDCR1_CES_SHIFT                   (0U)
84581 /*! CES - CE# setup time
84582  */
84583 #define SEMC_NANDCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
84584 
84585 #define SEMC_NANDCR1_CEH_MASK                    (0xF0U)
84586 #define SEMC_NANDCR1_CEH_SHIFT                   (4U)
84587 /*! CEH - CE# hold time
84588  */
84589 #define SEMC_NANDCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
84590 
84591 #define SEMC_NANDCR1_WEL_MASK                    (0xF00U)
84592 #define SEMC_NANDCR1_WEL_SHIFT                   (8U)
84593 /*! WEL - WE# low time
84594  */
84595 #define SEMC_NANDCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
84596 
84597 #define SEMC_NANDCR1_WEH_MASK                    (0xF000U)
84598 #define SEMC_NANDCR1_WEH_SHIFT                   (12U)
84599 /*! WEH - WE# high time
84600  */
84601 #define SEMC_NANDCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
84602 
84603 #define SEMC_NANDCR1_REL_MASK                    (0xF0000U)
84604 #define SEMC_NANDCR1_REL_SHIFT                   (16U)
84605 /*! REL - RE# low time
84606  */
84607 #define SEMC_NANDCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
84608 
84609 #define SEMC_NANDCR1_REH_MASK                    (0xF00000U)
84610 #define SEMC_NANDCR1_REH_SHIFT                   (20U)
84611 /*! REH - RE# high time
84612  */
84613 #define SEMC_NANDCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
84614 
84615 #define SEMC_NANDCR1_TA_MASK                     (0xF000000U)
84616 #define SEMC_NANDCR1_TA_SHIFT                    (24U)
84617 /*! TA - Turnaround time
84618  */
84619 #define SEMC_NANDCR1_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
84620 
84621 #define SEMC_NANDCR1_CEITV_MASK                  (0xF0000000U)
84622 #define SEMC_NANDCR1_CEITV_SHIFT                 (28U)
84623 /*! CEITV - CE# interval time
84624  */
84625 #define SEMC_NANDCR1_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
84626 /*! @} */
84627 
84628 /*! @name NANDCR2 - NAND Control Register 2 */
84629 /*! @{ */
84630 
84631 #define SEMC_NANDCR2_TWHR_MASK                   (0x3FU)
84632 #define SEMC_NANDCR2_TWHR_SHIFT                  (0U)
84633 /*! TWHR - WE# high to RE# low time
84634  */
84635 #define SEMC_NANDCR2_TWHR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
84636 
84637 #define SEMC_NANDCR2_TRHW_MASK                   (0xFC0U)
84638 #define SEMC_NANDCR2_TRHW_SHIFT                  (6U)
84639 /*! TRHW - RE# high to WE# low time
84640  */
84641 #define SEMC_NANDCR2_TRHW(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
84642 
84643 #define SEMC_NANDCR2_TADL_MASK                   (0x3F000U)
84644 #define SEMC_NANDCR2_TADL_SHIFT                  (12U)
84645 /*! TADL - Address cycle to data loading time
84646  */
84647 #define SEMC_NANDCR2_TADL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
84648 
84649 #define SEMC_NANDCR2_TRR_MASK                    (0xFC0000U)
84650 #define SEMC_NANDCR2_TRR_SHIFT                   (18U)
84651 /*! TRR - Ready to RE# low time
84652  */
84653 #define SEMC_NANDCR2_TRR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
84654 
84655 #define SEMC_NANDCR2_TWB_MASK                    (0x3F000000U)
84656 #define SEMC_NANDCR2_TWB_SHIFT                   (24U)
84657 /*! TWB - WE# high to busy time
84658  */
84659 #define SEMC_NANDCR2_TWB(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
84660 /*! @} */
84661 
84662 /*! @name NANDCR3 - NAND Control Register 3 */
84663 /*! @{ */
84664 
84665 #define SEMC_NANDCR3_NDOPT1_MASK                 (0x1U)
84666 #define SEMC_NANDCR3_NDOPT1_SHIFT                (0U)
84667 /*! NDOPT1 - NAND option bit 1
84668  */
84669 #define SEMC_NANDCR3_NDOPT1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
84670 
84671 #define SEMC_NANDCR3_NDOPT2_MASK                 (0x2U)
84672 #define SEMC_NANDCR3_NDOPT2_SHIFT                (1U)
84673 /*! NDOPT2 - NAND option bit 2
84674  */
84675 #define SEMC_NANDCR3_NDOPT2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
84676 
84677 #define SEMC_NANDCR3_NDOPT3_MASK                 (0x4U)
84678 #define SEMC_NANDCR3_NDOPT3_SHIFT                (2U)
84679 /*! NDOPT3 - NAND option bit 3
84680  */
84681 #define SEMC_NANDCR3_NDOPT3(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
84682 
84683 #define SEMC_NANDCR3_CLE_MASK                    (0x8U)
84684 #define SEMC_NANDCR3_CLE_SHIFT                   (3U)
84685 /*! CLE - NAND CLE Option
84686  */
84687 #define SEMC_NANDCR3_CLE(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
84688 
84689 #define SEMC_NANDCR3_RDS_MASK                    (0xF0000U)
84690 #define SEMC_NANDCR3_RDS_SHIFT                   (16U)
84691 /*! RDS - Read Data Setup time
84692  */
84693 #define SEMC_NANDCR3_RDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
84694 
84695 #define SEMC_NANDCR3_RDH_MASK                    (0xF00000U)
84696 #define SEMC_NANDCR3_RDH_SHIFT                   (20U)
84697 /*! RDH - Read Data Hold time
84698  */
84699 #define SEMC_NANDCR3_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
84700 
84701 #define SEMC_NANDCR3_WDS_MASK                    (0xF000000U)
84702 #define SEMC_NANDCR3_WDS_SHIFT                   (24U)
84703 /*! WDS - Write Data Setup time
84704  */
84705 #define SEMC_NANDCR3_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
84706 
84707 #define SEMC_NANDCR3_WDH_MASK                    (0xF0000000U)
84708 #define SEMC_NANDCR3_WDH_SHIFT                   (28U)
84709 /*! WDH - Write Data Hold time
84710  */
84711 #define SEMC_NANDCR3_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
84712 /*! @} */
84713 
84714 /*! @name NORCR0 - NOR Control Register 0 */
84715 /*! @{ */
84716 
84717 #define SEMC_NORCR0_PS_MASK                      (0x1U)
84718 #define SEMC_NORCR0_PS_SHIFT                     (0U)
84719 /*! PS - Port Size
84720  *  0b0..8bit
84721  *  0b1..16bit
84722  */
84723 #define SEMC_NORCR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
84724 
84725 #define SEMC_NORCR0_SYNCEN_MASK                  (0x2U)
84726 #define SEMC_NORCR0_SYNCEN_SHIFT                 (1U)
84727 /*! SYNCEN - Synchronous Mode Enable
84728  *  0b0..Asynchronous mode is enabled.
84729  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
84730  */
84731 #define SEMC_NORCR0_SYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
84732 
84733 #define SEMC_NORCR0_BL_MASK                      (0x70U)
84734 #define SEMC_NORCR0_BL_SHIFT                     (4U)
84735 /*! BL - Burst Length
84736  *  0b000..1
84737  *  0b001..2
84738  *  0b010..4
84739  *  0b011..8
84740  *  0b100..16
84741  *  0b101..32
84742  *  0b110..64
84743  *  0b111..64
84744  */
84745 #define SEMC_NORCR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
84746 
84747 #define SEMC_NORCR0_AM_MASK                      (0x300U)
84748 #define SEMC_NORCR0_AM_SHIFT                     (8U)
84749 /*! AM - Address Mode
84750  *  0b00..Address/Data MUX mode (ADMUX)
84751  *  0b01..Advanced Address/Data MUX mode (AADM)
84752  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
84753  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
84754  */
84755 #define SEMC_NORCR0_AM(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
84756 
84757 #define SEMC_NORCR0_ADVP_MASK                    (0x400U)
84758 #define SEMC_NORCR0_ADVP_SHIFT                   (10U)
84759 /*! ADVP - ADV# Polarity
84760  *  0b0..ADV# is active low.
84761  *  0b1..ADV# is active high.
84762  */
84763 #define SEMC_NORCR0_ADVP(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
84764 
84765 #define SEMC_NORCR0_ADVH_MASK                    (0x800U)
84766 #define SEMC_NORCR0_ADVH_SHIFT                   (11U)
84767 /*! ADVH - ADV# level control during address hold state
84768  *  0b0..ADV# is high during address hold state.
84769  *  0b1..ADV# is low during address hold state.
84770  */
84771 #define SEMC_NORCR0_ADVH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
84772 
84773 #define SEMC_NORCR0_COL_MASK                     (0xF000U)
84774 #define SEMC_NORCR0_COL_SHIFT                    (12U)
84775 /*! COL - Column Address bit width
84776  *  0b0000..12 Bits
84777  *  0b0001..11 Bits
84778  *  0b0010..10 Bits
84779  *  0b0011..9 Bits
84780  *  0b0100..8 Bits
84781  *  0b0101..7 Bits
84782  *  0b0110..6 Bits
84783  *  0b0111..5 Bits
84784  *  0b1000..4 Bits
84785  *  0b1001..3 Bits
84786  *  0b1010..2 Bits
84787  *  0b1011..12 Bits
84788  *  0b1100..12 Bits
84789  *  0b1101..12 Bits
84790  *  0b1110..12 Bits
84791  *  0b1111..12 Bits
84792  */
84793 #define SEMC_NORCR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
84794 /*! @} */
84795 
84796 /*! @name NORCR1 - NOR Control Register 1 */
84797 /*! @{ */
84798 
84799 #define SEMC_NORCR1_CES_MASK                     (0xFU)
84800 #define SEMC_NORCR1_CES_SHIFT                    (0U)
84801 /*! CES - CE setup time
84802  */
84803 #define SEMC_NORCR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
84804 
84805 #define SEMC_NORCR1_CEH_MASK                     (0xF0U)
84806 #define SEMC_NORCR1_CEH_SHIFT                    (4U)
84807 /*! CEH - CE hold time
84808  */
84809 #define SEMC_NORCR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
84810 
84811 #define SEMC_NORCR1_AS_MASK                      (0xF00U)
84812 #define SEMC_NORCR1_AS_SHIFT                     (8U)
84813 /*! AS - Address setup time
84814  */
84815 #define SEMC_NORCR1_AS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
84816 
84817 #define SEMC_NORCR1_AH_MASK                      (0xF000U)
84818 #define SEMC_NORCR1_AH_SHIFT                     (12U)
84819 /*! AH - Address hold time
84820  */
84821 #define SEMC_NORCR1_AH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
84822 
84823 #define SEMC_NORCR1_WEL_MASK                     (0xF0000U)
84824 #define SEMC_NORCR1_WEL_SHIFT                    (16U)
84825 /*! WEL - WE low time
84826  */
84827 #define SEMC_NORCR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
84828 
84829 #define SEMC_NORCR1_WEH_MASK                     (0xF00000U)
84830 #define SEMC_NORCR1_WEH_SHIFT                    (20U)
84831 /*! WEH - WE high time
84832  */
84833 #define SEMC_NORCR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
84834 
84835 #define SEMC_NORCR1_REL_MASK                     (0xF000000U)
84836 #define SEMC_NORCR1_REL_SHIFT                    (24U)
84837 /*! REL - RE low time
84838  */
84839 #define SEMC_NORCR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
84840 
84841 #define SEMC_NORCR1_REH_MASK                     (0xF0000000U)
84842 #define SEMC_NORCR1_REH_SHIFT                    (28U)
84843 /*! REH - RE high time
84844  */
84845 #define SEMC_NORCR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
84846 /*! @} */
84847 
84848 /*! @name NORCR2 - NOR Control Register 2 */
84849 /*! @{ */
84850 
84851 #define SEMC_NORCR2_TA_MASK                      (0xF00U)
84852 #define SEMC_NORCR2_TA_SHIFT                     (8U)
84853 /*! TA - Turnaround time
84854  */
84855 #define SEMC_NORCR2_TA(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
84856 
84857 #define SEMC_NORCR2_AWDH_MASK                    (0xF000U)
84858 #define SEMC_NORCR2_AWDH_SHIFT                   (12U)
84859 /*! AWDH - Address to write data hold time
84860  */
84861 #define SEMC_NORCR2_AWDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
84862 
84863 #define SEMC_NORCR2_LC_MASK                      (0xF0000U)
84864 #define SEMC_NORCR2_LC_SHIFT                     (16U)
84865 /*! LC - Latency count
84866  */
84867 #define SEMC_NORCR2_LC(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
84868 
84869 #define SEMC_NORCR2_RD_MASK                      (0xF00000U)
84870 #define SEMC_NORCR2_RD_SHIFT                     (20U)
84871 /*! RD - Read time
84872  */
84873 #define SEMC_NORCR2_RD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
84874 
84875 #define SEMC_NORCR2_CEITV_MASK                   (0xF000000U)
84876 #define SEMC_NORCR2_CEITV_SHIFT                  (24U)
84877 /*! CEITV - CE# interval time
84878  */
84879 #define SEMC_NORCR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
84880 
84881 #define SEMC_NORCR2_RDH_MASK                     (0xF0000000U)
84882 #define SEMC_NORCR2_RDH_SHIFT                    (28U)
84883 /*! RDH - Read hold time
84884  */
84885 #define SEMC_NORCR2_RDH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
84886 /*! @} */
84887 
84888 /*! @name NORCR3 - NOR Control Register 3 */
84889 /*! @{ */
84890 
84891 #define SEMC_NORCR3_ASSR_MASK                    (0xFU)
84892 #define SEMC_NORCR3_ASSR_SHIFT                   (0U)
84893 /*! ASSR - Address setup time for SYNC read
84894  */
84895 #define SEMC_NORCR3_ASSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
84896 
84897 #define SEMC_NORCR3_AHSR_MASK                    (0xF0U)
84898 #define SEMC_NORCR3_AHSR_SHIFT                   (4U)
84899 /*! AHSR - Address hold time for SYNC read
84900  */
84901 #define SEMC_NORCR3_AHSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
84902 /*! @} */
84903 
84904 /*! @name SRAMCR0 - SRAM Control Register 0 */
84905 /*! @{ */
84906 
84907 #define SEMC_SRAMCR0_PS_MASK                     (0x1U)
84908 #define SEMC_SRAMCR0_PS_SHIFT                    (0U)
84909 /*! PS - Port Size
84910  *  0b0..8bit
84911  *  0b1..16bit
84912  */
84913 #define SEMC_SRAMCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
84914 
84915 #define SEMC_SRAMCR0_SYNCEN_MASK                 (0x2U)
84916 #define SEMC_SRAMCR0_SYNCEN_SHIFT                (1U)
84917 /*! SYNCEN - Synchronous Mode Enable
84918  *  0b0..Asynchronous mode is enabled.
84919  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
84920  */
84921 #define SEMC_SRAMCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
84922 
84923 #define SEMC_SRAMCR0_WAITEN_MASK                 (0x4U)
84924 #define SEMC_SRAMCR0_WAITEN_SHIFT                (2U)
84925 /*! WAITEN - Wait Enable
84926  *  0b0..The SEMC does not monitor wait pin.
84927  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
84928  */
84929 #define SEMC_SRAMCR0_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK)
84930 
84931 #define SEMC_SRAMCR0_WAITSP_MASK                 (0x8U)
84932 #define SEMC_SRAMCR0_WAITSP_SHIFT                (3U)
84933 /*! WAITSP - Wait Sample
84934  *  0b0..Wait pin is directly used by the SEMC.
84935  *  0b1..Wait pin is sampled by internal clock before it is used.
84936  */
84937 #define SEMC_SRAMCR0_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK)
84938 
84939 #define SEMC_SRAMCR0_BL_MASK                     (0x70U)
84940 #define SEMC_SRAMCR0_BL_SHIFT                    (4U)
84941 /*! BL - Burst Length
84942  *  0b000..1
84943  *  0b001..2
84944  *  0b010..4
84945  *  0b011..8
84946  *  0b100..16
84947  *  0b101..32
84948  *  0b110..64
84949  *  0b111..64
84950  */
84951 #define SEMC_SRAMCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
84952 
84953 #define SEMC_SRAMCR0_AM_MASK                     (0x300U)
84954 #define SEMC_SRAMCR0_AM_SHIFT                    (8U)
84955 /*! AM - Address Mode
84956  *  0b00..Address/Data MUX mode (ADMUX)
84957  *  0b01..Advanced Address/Data MUX mode (AADM)
84958  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
84959  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
84960  */
84961 #define SEMC_SRAMCR0_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
84962 
84963 #define SEMC_SRAMCR0_ADVP_MASK                   (0x400U)
84964 #define SEMC_SRAMCR0_ADVP_SHIFT                  (10U)
84965 /*! ADVP - ADV# polarity
84966  *  0b0..ADV# is active low.
84967  *  0b1..ADV# is active high.
84968  */
84969 #define SEMC_SRAMCR0_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
84970 
84971 #define SEMC_SRAMCR0_ADVH_MASK                   (0x800U)
84972 #define SEMC_SRAMCR0_ADVH_SHIFT                  (11U)
84973 /*! ADVH - ADV# level control during address hold state
84974  *  0b0..ADV# is high during address hold state.
84975  *  0b1..ADV# is low during address hold state.
84976  */
84977 #define SEMC_SRAMCR0_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
84978 
84979 #define SEMC_SRAMCR0_COL_MASK                    (0xF000U)
84980 #define SEMC_SRAMCR0_COL_SHIFT                   (12U)
84981 /*! COL - Column Address bit width
84982  *  0b0000..12 Bits
84983  *  0b0001..11 Bits
84984  *  0b0010..10 Bits
84985  *  0b0011..9 Bits
84986  *  0b0100..8 Bits
84987  *  0b0101..7 Bits
84988  *  0b0110..6 Bits
84989  *  0b0111..5 Bits
84990  *  0b1000..4 Bits
84991  *  0b1001..3 Bits
84992  *  0b1010..2 Bits
84993  *  0b1011..12 Bits
84994  *  0b1100..12 Bits
84995  *  0b1101..12 Bits
84996  *  0b1110..12 Bits
84997  *  0b1111..12 Bits
84998  */
84999 #define SEMC_SRAMCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
85000 /*! @} */
85001 
85002 /*! @name SRAMCR1 - SRAM Control Register 1 */
85003 /*! @{ */
85004 
85005 #define SEMC_SRAMCR1_CES_MASK                    (0xFU)
85006 #define SEMC_SRAMCR1_CES_SHIFT                   (0U)
85007 /*! CES - CE setup time
85008  */
85009 #define SEMC_SRAMCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
85010 
85011 #define SEMC_SRAMCR1_CEH_MASK                    (0xF0U)
85012 #define SEMC_SRAMCR1_CEH_SHIFT                   (4U)
85013 /*! CEH - CE hold time
85014  */
85015 #define SEMC_SRAMCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
85016 
85017 #define SEMC_SRAMCR1_AS_MASK                     (0xF00U)
85018 #define SEMC_SRAMCR1_AS_SHIFT                    (8U)
85019 /*! AS - Address setup time
85020  */
85021 #define SEMC_SRAMCR1_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
85022 
85023 #define SEMC_SRAMCR1_AH_MASK                     (0xF000U)
85024 #define SEMC_SRAMCR1_AH_SHIFT                    (12U)
85025 /*! AH - Address hold time
85026  */
85027 #define SEMC_SRAMCR1_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
85028 
85029 #define SEMC_SRAMCR1_WEL_MASK                    (0xF0000U)
85030 #define SEMC_SRAMCR1_WEL_SHIFT                   (16U)
85031 /*! WEL - WE low time
85032  */
85033 #define SEMC_SRAMCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
85034 
85035 #define SEMC_SRAMCR1_WEH_MASK                    (0xF00000U)
85036 #define SEMC_SRAMCR1_WEH_SHIFT                   (20U)
85037 /*! WEH - WE high time
85038  */
85039 #define SEMC_SRAMCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
85040 
85041 #define SEMC_SRAMCR1_REL_MASK                    (0xF000000U)
85042 #define SEMC_SRAMCR1_REL_SHIFT                   (24U)
85043 /*! REL - RE low time
85044  */
85045 #define SEMC_SRAMCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
85046 
85047 #define SEMC_SRAMCR1_REH_MASK                    (0xF0000000U)
85048 #define SEMC_SRAMCR1_REH_SHIFT                   (28U)
85049 /*! REH - RE high time
85050  */
85051 #define SEMC_SRAMCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
85052 /*! @} */
85053 
85054 /*! @name SRAMCR2 - SRAM Control Register 2 */
85055 /*! @{ */
85056 
85057 #define SEMC_SRAMCR2_WDS_MASK                    (0xFU)
85058 #define SEMC_SRAMCR2_WDS_SHIFT                   (0U)
85059 /*! WDS - Write Data setup time
85060  */
85061 #define SEMC_SRAMCR2_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
85062 
85063 #define SEMC_SRAMCR2_WDH_MASK                    (0xF0U)
85064 #define SEMC_SRAMCR2_WDH_SHIFT                   (4U)
85065 /*! WDH - Write Data hold time
85066  */
85067 #define SEMC_SRAMCR2_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
85068 
85069 #define SEMC_SRAMCR2_TA_MASK                     (0xF00U)
85070 #define SEMC_SRAMCR2_TA_SHIFT                    (8U)
85071 /*! TA - Turnaround time
85072  */
85073 #define SEMC_SRAMCR2_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
85074 
85075 #define SEMC_SRAMCR2_AWDH_MASK                   (0xF000U)
85076 #define SEMC_SRAMCR2_AWDH_SHIFT                  (12U)
85077 /*! AWDH - Address to write data hold time
85078  */
85079 #define SEMC_SRAMCR2_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
85080 
85081 #define SEMC_SRAMCR2_LC_MASK                     (0xF0000U)
85082 #define SEMC_SRAMCR2_LC_SHIFT                    (16U)
85083 /*! LC - Latency count
85084  */
85085 #define SEMC_SRAMCR2_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
85086 
85087 #define SEMC_SRAMCR2_RD_MASK                     (0xF00000U)
85088 #define SEMC_SRAMCR2_RD_SHIFT                    (20U)
85089 /*! RD - Read time
85090  */
85091 #define SEMC_SRAMCR2_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
85092 
85093 #define SEMC_SRAMCR2_CEITV_MASK                  (0xF000000U)
85094 #define SEMC_SRAMCR2_CEITV_SHIFT                 (24U)
85095 /*! CEITV - CE# interval time
85096  */
85097 #define SEMC_SRAMCR2_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
85098 
85099 #define SEMC_SRAMCR2_RDH_MASK                    (0xF0000000U)
85100 #define SEMC_SRAMCR2_RDH_SHIFT                   (28U)
85101 /*! RDH - Read hold time
85102  */
85103 #define SEMC_SRAMCR2_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
85104 /*! @} */
85105 
85106 /*! @name DBICR0 - DBI-B Control Register 0 */
85107 /*! @{ */
85108 
85109 #define SEMC_DBICR0_PS_MASK                      (0x1U)
85110 #define SEMC_DBICR0_PS_SHIFT                     (0U)
85111 /*! PS - Port Size
85112  *  0b0..8bit
85113  *  0b1..16bit
85114  */
85115 #define SEMC_DBICR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
85116 
85117 #define SEMC_DBICR0_BL_MASK                      (0x70U)
85118 #define SEMC_DBICR0_BL_SHIFT                     (4U)
85119 /*! BL - Burst Length
85120  *  0b000..1
85121  *  0b001..2
85122  *  0b010..4
85123  *  0b011..8
85124  *  0b100..16
85125  *  0b101..32
85126  *  0b110..64
85127  *  0b111..64
85128  */
85129 #define SEMC_DBICR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
85130 
85131 #define SEMC_DBICR0_COL_MASK                     (0xF000U)
85132 #define SEMC_DBICR0_COL_SHIFT                    (12U)
85133 /*! COL - Column Address bit width
85134  *  0b0000..12 Bits
85135  *  0b0001..11 Bits
85136  *  0b0010..10 Bits
85137  *  0b0011..9 Bits
85138  *  0b0100..8 Bits
85139  *  0b0101..7 Bits
85140  *  0b0110..6 Bits
85141  *  0b0111..5 Bits
85142  *  0b1000..4 Bits
85143  *  0b1001..3 Bits
85144  *  0b1010..2 Bits
85145  *  0b1011..12 Bits
85146  *  0b1100..12 Bits
85147  *  0b1101..12 Bits
85148  *  0b1110..12 Bits
85149  *  0b1111..12 Bits
85150  */
85151 #define SEMC_DBICR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
85152 /*! @} */
85153 
85154 /*! @name DBICR1 - DBI-B Control Register 1 */
85155 /*! @{ */
85156 
85157 #define SEMC_DBICR1_CES_MASK                     (0xFU)
85158 #define SEMC_DBICR1_CES_SHIFT                    (0U)
85159 /*! CES - CSX Setup Time
85160  */
85161 #define SEMC_DBICR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
85162 
85163 #define SEMC_DBICR1_CEH_MASK                     (0xF0U)
85164 #define SEMC_DBICR1_CEH_SHIFT                    (4U)
85165 /*! CEH - CSX Hold Time
85166  */
85167 #define SEMC_DBICR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
85168 
85169 #define SEMC_DBICR1_WEL_MASK                     (0xF00U)
85170 #define SEMC_DBICR1_WEL_SHIFT                    (8U)
85171 /*! WEL - WRX Low Time
85172  */
85173 #define SEMC_DBICR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
85174 
85175 #define SEMC_DBICR1_WEH_MASK                     (0xF000U)
85176 #define SEMC_DBICR1_WEH_SHIFT                    (12U)
85177 /*! WEH - WRX High Time
85178  */
85179 #define SEMC_DBICR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
85180 
85181 #define SEMC_DBICR1_REL_MASK                     (0x7F0000U)
85182 #define SEMC_DBICR1_REL_SHIFT                    (16U)
85183 /*! REL - RDX Low Time
85184  */
85185 #define SEMC_DBICR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
85186 
85187 #define SEMC_DBICR1_REH_MASK                     (0x7F000000U)
85188 #define SEMC_DBICR1_REH_SHIFT                    (24U)
85189 /*! REH - RDX High Time
85190  */
85191 #define SEMC_DBICR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
85192 /*! @} */
85193 
85194 /*! @name DBICR2 - DBI-B Control Register 2 */
85195 /*! @{ */
85196 
85197 #define SEMC_DBICR2_CEITV_MASK                   (0xFU)
85198 #define SEMC_DBICR2_CEITV_SHIFT                  (0U)
85199 /*! CEITV - CSX interval time
85200  */
85201 #define SEMC_DBICR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK)
85202 /*! @} */
85203 
85204 /*! @name IPCR0 - IP Command Control Register 0 */
85205 /*! @{ */
85206 
85207 #define SEMC_IPCR0_SA_MASK                       (0xFFFFFFFFU)
85208 #define SEMC_IPCR0_SA_SHIFT                      (0U)
85209 /*! SA - Slave address
85210  */
85211 #define SEMC_IPCR0_SA(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
85212 /*! @} */
85213 
85214 /*! @name IPCR1 - IP Command Control Register 1 */
85215 /*! @{ */
85216 
85217 #define SEMC_IPCR1_DATSZ_MASK                    (0x7U)
85218 #define SEMC_IPCR1_DATSZ_SHIFT                   (0U)
85219 /*! DATSZ - Data Size in Byte
85220  *  0b000..4
85221  *  0b001..1
85222  *  0b010..2
85223  *  0b011..3
85224  *  0b100..4
85225  *  0b101..4
85226  *  0b110..4
85227  *  0b111..4
85228  */
85229 #define SEMC_IPCR1_DATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
85230 
85231 #define SEMC_IPCR1_NAND_EXT_ADDR_MASK            (0xFF00U)
85232 #define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT           (8U)
85233 /*! NAND_EXT_ADDR - NAND Extended Address
85234  */
85235 #define SEMC_IPCR1_NAND_EXT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
85236 /*! @} */
85237 
85238 /*! @name IPCR2 - IP Command Control Register 2 */
85239 /*! @{ */
85240 
85241 #define SEMC_IPCR2_BM0_MASK                      (0x1U)
85242 #define SEMC_IPCR2_BM0_SHIFT                     (0U)
85243 /*! BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0)
85244  *  0b0..Byte is unmasked
85245  *  0b1..Byte is masked
85246  */
85247 #define SEMC_IPCR2_BM0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
85248 
85249 #define SEMC_IPCR2_BM1_MASK                      (0x2U)
85250 #define SEMC_IPCR2_BM1_SHIFT                     (1U)
85251 /*! BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8)
85252  *  0b0..Byte is unmasked
85253  *  0b1..Byte is masked
85254  */
85255 #define SEMC_IPCR2_BM1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
85256 
85257 #define SEMC_IPCR2_BM2_MASK                      (0x4U)
85258 #define SEMC_IPCR2_BM2_SHIFT                     (2U)
85259 /*! BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16)
85260  *  0b0..Byte is unmasked
85261  *  0b1..Byte is masked
85262  */
85263 #define SEMC_IPCR2_BM2(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
85264 
85265 #define SEMC_IPCR2_BM3_MASK                      (0x8U)
85266 #define SEMC_IPCR2_BM3_SHIFT                     (3U)
85267 /*! BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24)
85268  *  0b0..Byte is unmasked
85269  *  0b1..Byte is masked
85270  */
85271 #define SEMC_IPCR2_BM3(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
85272 /*! @} */
85273 
85274 /*! @name IPCMD - IP Command Register */
85275 /*! @{ */
85276 
85277 #define SEMC_IPCMD_CMD_MASK                      (0xFFFFU)
85278 #define SEMC_IPCMD_CMD_SHIFT                     (0U)
85279 #define SEMC_IPCMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
85280 
85281 #define SEMC_IPCMD_KEY_MASK                      (0xFFFF0000U)
85282 #define SEMC_IPCMD_KEY_SHIFT                     (16U)
85283 #define SEMC_IPCMD_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
85284 /*! @} */
85285 
85286 /*! @name IPTXDAT - TX DATA Register */
85287 /*! @{ */
85288 
85289 #define SEMC_IPTXDAT_DAT_MASK                    (0xFFFFFFFFU)
85290 #define SEMC_IPTXDAT_DAT_SHIFT                   (0U)
85291 #define SEMC_IPTXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
85292 /*! @} */
85293 
85294 /*! @name IPRXDAT - RX DATA Register */
85295 /*! @{ */
85296 
85297 #define SEMC_IPRXDAT_DAT_MASK                    (0xFFFFFFFFU)
85298 #define SEMC_IPRXDAT_DAT_SHIFT                   (0U)
85299 #define SEMC_IPRXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
85300 /*! @} */
85301 
85302 /*! @name STS0 - Status Register 0 */
85303 /*! @{ */
85304 
85305 #define SEMC_STS0_IDLE_MASK                      (0x1U)
85306 #define SEMC_STS0_IDLE_SHIFT                     (0U)
85307 /*! IDLE - Indicating whether the SEMC is in idle state.
85308  */
85309 #define SEMC_STS0_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
85310 
85311 #define SEMC_STS0_NARDY_MASK                     (0x2U)
85312 #define SEMC_STS0_NARDY_SHIFT                    (1U)
85313 /*! NARDY - Indicating NAND device Ready/WAIT# pin level.
85314  *  0b0..NAND device is not ready
85315  *  0b1..NAND device is ready
85316  */
85317 #define SEMC_STS0_NARDY(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
85318 /*! @} */
85319 
85320 /*! @name STS2 - Status Register 2 */
85321 /*! @{ */
85322 
85323 #define SEMC_STS2_NDWRPEND_MASK                  (0x8U)
85324 #define SEMC_STS2_NDWRPEND_SHIFT                 (3U)
85325 /*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
85326  *  0b0..No pending
85327  *  0b1..Pending
85328  */
85329 #define SEMC_STS2_NDWRPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
85330 /*! @} */
85331 
85332 /*! @name STS12 - Status Register 12 */
85333 /*! @{ */
85334 
85335 #define SEMC_STS12_NDADDR_MASK                   (0xFFFFFFFFU)
85336 #define SEMC_STS12_NDADDR_SHIFT                  (0U)
85337 /*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
85338  */
85339 #define SEMC_STS12_NDADDR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
85340 /*! @} */
85341 
85342 /*! @name STS13 - Status Register 13 */
85343 /*! @{ */
85344 
85345 #define SEMC_STS13_SLVLOCK_MASK                  (0x1U)
85346 #define SEMC_STS13_SLVLOCK_SHIFT                 (0U)
85347 /*! SLVLOCK - Sample clock slave delay line locked.
85348  *  0b0..Slave delay line is not locked.
85349  *  0b1..Slave delay line is locked.
85350  */
85351 #define SEMC_STS13_SLVLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
85352 
85353 #define SEMC_STS13_REFLOCK_MASK                  (0x2U)
85354 #define SEMC_STS13_REFLOCK_SHIFT                 (1U)
85355 /*! REFLOCK - Sample clock reference delay line locked.
85356  *  0b0..Reference delay line is not locked.
85357  *  0b1..Reference delay line is locked.
85358  */
85359 #define SEMC_STS13_REFLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
85360 
85361 #define SEMC_STS13_SLVSEL_MASK                   (0xFCU)
85362 #define SEMC_STS13_SLVSEL_SHIFT                  (2U)
85363 /*! SLVSEL - Sample clock slave delay line delay cell number selection.
85364  */
85365 #define SEMC_STS13_SLVSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
85366 
85367 #define SEMC_STS13_REFSEL_MASK                   (0x3F00U)
85368 #define SEMC_STS13_REFSEL_SHIFT                  (8U)
85369 /*! REFSEL - Sample clock reference delay line delay cell number selection.
85370  */
85371 #define SEMC_STS13_REFSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
85372 /*! @} */
85373 
85374 /*! @name BR9 - Base Register 9 */
85375 /*! @{ */
85376 
85377 #define SEMC_BR9_VLD_MASK                        (0x1U)
85378 #define SEMC_BR9_VLD_SHIFT                       (0U)
85379 /*! VLD - Valid
85380  *  0b0..The memory is invalid, can not be accessed.
85381  *  0b1..The memory is valid, can be accessed.
85382  */
85383 #define SEMC_BR9_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK)
85384 
85385 #define SEMC_BR9_MS_MASK                         (0x3EU)
85386 #define SEMC_BR9_MS_SHIFT                        (1U)
85387 /*! MS - Memory size
85388  *  0b00000..4KB
85389  *  0b00001..8KB
85390  *  0b00010..16KB
85391  *  0b00011..32KB
85392  *  0b00100..64KB
85393  *  0b00101..128KB
85394  *  0b00110..256KB
85395  *  0b00111..512KB
85396  *  0b01000..1MB
85397  *  0b01001..2MB
85398  *  0b01010..4MB
85399  *  0b01011..8MB
85400  *  0b01100..16MB
85401  *  0b01101..32MB
85402  *  0b01110..64MB
85403  *  0b01111..128MB
85404  *  0b10000..256MB
85405  *  0b10001..512MB
85406  *  0b10010..1GB
85407  *  0b10011..2GB
85408  *  0b10100-0b11111..4GB
85409  */
85410 #define SEMC_BR9_MS(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK)
85411 
85412 #define SEMC_BR9_BA_MASK                         (0xFFFFF000U)
85413 #define SEMC_BR9_BA_SHIFT                        (12U)
85414 /*! BA - Base Address
85415  */
85416 #define SEMC_BR9_BA(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK)
85417 /*! @} */
85418 
85419 /*! @name BR10 - Base Register 10 */
85420 /*! @{ */
85421 
85422 #define SEMC_BR10_VLD_MASK                       (0x1U)
85423 #define SEMC_BR10_VLD_SHIFT                      (0U)
85424 /*! VLD - Valid
85425  *  0b0..The memory is invalid, can not be accessed.
85426  *  0b1..The memory is valid, can be accessed.
85427  */
85428 #define SEMC_BR10_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK)
85429 
85430 #define SEMC_BR10_MS_MASK                        (0x3EU)
85431 #define SEMC_BR10_MS_SHIFT                       (1U)
85432 /*! MS - Memory size
85433  *  0b00000..4KB
85434  *  0b00001..8KB
85435  *  0b00010..16KB
85436  *  0b00011..32KB
85437  *  0b00100..64KB
85438  *  0b00101..128KB
85439  *  0b00110..256KB
85440  *  0b00111..512KB
85441  *  0b01000..1MB
85442  *  0b01001..2MB
85443  *  0b01010..4MB
85444  *  0b01011..8MB
85445  *  0b01100..16MB
85446  *  0b01101..32MB
85447  *  0b01110..64MB
85448  *  0b01111..128MB
85449  *  0b10000..256MB
85450  *  0b10001..512MB
85451  *  0b10010..1GB
85452  *  0b10011..2GB
85453  *  0b10100-0b11111..4GB
85454  */
85455 #define SEMC_BR10_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK)
85456 
85457 #define SEMC_BR10_BA_MASK                        (0xFFFFF000U)
85458 #define SEMC_BR10_BA_SHIFT                       (12U)
85459 /*! BA - Base Address
85460  */
85461 #define SEMC_BR10_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK)
85462 /*! @} */
85463 
85464 /*! @name BR11 - Base Register 11 */
85465 /*! @{ */
85466 
85467 #define SEMC_BR11_VLD_MASK                       (0x1U)
85468 #define SEMC_BR11_VLD_SHIFT                      (0U)
85469 /*! VLD - Valid
85470  *  0b0..The memory is invalid, can not be accessed.
85471  *  0b1..The memory is valid, can be accessed.
85472  */
85473 #define SEMC_BR11_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK)
85474 
85475 #define SEMC_BR11_MS_MASK                        (0x3EU)
85476 #define SEMC_BR11_MS_SHIFT                       (1U)
85477 /*! MS - Memory size
85478  *  0b00000..4KB
85479  *  0b00001..8KB
85480  *  0b00010..16KB
85481  *  0b00011..32KB
85482  *  0b00100..64KB
85483  *  0b00101..128KB
85484  *  0b00110..256KB
85485  *  0b00111..512KB
85486  *  0b01000..1MB
85487  *  0b01001..2MB
85488  *  0b01010..4MB
85489  *  0b01011..8MB
85490  *  0b01100..16MB
85491  *  0b01101..32MB
85492  *  0b01110..64MB
85493  *  0b01111..128MB
85494  *  0b10000..256MB
85495  *  0b10001..512MB
85496  *  0b10010..1GB
85497  *  0b10011..2GB
85498  *  0b10100-0b11111..4GB
85499  */
85500 #define SEMC_BR11_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK)
85501 
85502 #define SEMC_BR11_BA_MASK                        (0xFFFFF000U)
85503 #define SEMC_BR11_BA_SHIFT                       (12U)
85504 /*! BA - Base Address
85505  */
85506 #define SEMC_BR11_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK)
85507 /*! @} */
85508 
85509 /*! @name SRAMCR4 - SRAM Control Register 4 */
85510 /*! @{ */
85511 
85512 #define SEMC_SRAMCR4_PS_MASK                     (0x1U)
85513 #define SEMC_SRAMCR4_PS_SHIFT                    (0U)
85514 /*! PS - Port Size
85515  *  0b0..8bit
85516  *  0b1..16bit
85517  */
85518 #define SEMC_SRAMCR4_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK)
85519 
85520 #define SEMC_SRAMCR4_SYNCEN_MASK                 (0x2U)
85521 #define SEMC_SRAMCR4_SYNCEN_SHIFT                (1U)
85522 /*! SYNCEN - Synchronous Mode Enable
85523  *  0b0..Asynchronous mode is enabled.
85524  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
85525  */
85526 #define SEMC_SRAMCR4_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)
85527 
85528 #define SEMC_SRAMCR4_WAITEN_MASK                 (0x4U)
85529 #define SEMC_SRAMCR4_WAITEN_SHIFT                (2U)
85530 /*! WAITEN - Wait Enable
85531  *  0b0..The SEMC does not monitor wait pin.
85532  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
85533  */
85534 #define SEMC_SRAMCR4_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK)
85535 
85536 #define SEMC_SRAMCR4_WAITSP_MASK                 (0x8U)
85537 #define SEMC_SRAMCR4_WAITSP_SHIFT                (3U)
85538 /*! WAITSP - Wait Sample
85539  *  0b0..Wait pin is directly used by the SEMC.
85540  *  0b1..Wait pin is sampled by internal clock before it is used.
85541  */
85542 #define SEMC_SRAMCR4_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK)
85543 
85544 #define SEMC_SRAMCR4_BL_MASK                     (0x70U)
85545 #define SEMC_SRAMCR4_BL_SHIFT                    (4U)
85546 /*! BL - Burst Length
85547  *  0b000..1
85548  *  0b001..2
85549  *  0b010..4
85550  *  0b011..8
85551  *  0b100..16
85552  *  0b101..32
85553  *  0b110..64
85554  *  0b111..64
85555  */
85556 #define SEMC_SRAMCR4_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
85557 
85558 #define SEMC_SRAMCR4_AM_MASK                     (0x300U)
85559 #define SEMC_SRAMCR4_AM_SHIFT                    (8U)
85560 /*! AM - Address Mode
85561  *  0b00..Address/Data MUX mode (ADMUX)
85562  *  0b01..Advanced Address/Data MUX mode (AADM)
85563  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
85564  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
85565  */
85566 #define SEMC_SRAMCR4_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK)
85567 
85568 #define SEMC_SRAMCR4_ADVP_MASK                   (0x400U)
85569 #define SEMC_SRAMCR4_ADVP_SHIFT                  (10U)
85570 /*! ADVP - ADV# polarity
85571  *  0b0..ADV# is active low.
85572  *  0b1..ADV# is active high.
85573  */
85574 #define SEMC_SRAMCR4_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK)
85575 
85576 #define SEMC_SRAMCR4_ADVH_MASK                   (0x800U)
85577 #define SEMC_SRAMCR4_ADVH_SHIFT                  (11U)
85578 /*! ADVH - ADV# level control during address hold state
85579  *  0b0..ADV# is high during address hold state.
85580  *  0b1..ADV# is low during address hold state.
85581  */
85582 #define SEMC_SRAMCR4_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK)
85583 
85584 #define SEMC_SRAMCR4_COL_MASK                    (0xF000U)
85585 #define SEMC_SRAMCR4_COL_SHIFT                   (12U)
85586 /*! COL - Column Address bit width
85587  *  0b0000..12 Bits
85588  *  0b0001..11 Bits
85589  *  0b0010..10 Bits
85590  *  0b0011..9 Bits
85591  *  0b0100..8 Bits
85592  *  0b0101..7 Bits
85593  *  0b0110..6 Bits
85594  *  0b0111..5 Bits
85595  *  0b1000..4 Bits
85596  *  0b1001..3 Bits
85597  *  0b1010..2 Bits
85598  *  0b1011..12 Bits
85599  *  0b1100..12 Bits
85600  *  0b1101..12 Bits
85601  *  0b1110..12 Bits
85602  *  0b1111..12 Bits
85603  */
85604 #define SEMC_SRAMCR4_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK)
85605 /*! @} */
85606 
85607 /*! @name SRAMCR5 - SRAM Control Register 5 */
85608 /*! @{ */
85609 
85610 #define SEMC_SRAMCR5_CES_MASK                    (0xFU)
85611 #define SEMC_SRAMCR5_CES_SHIFT                   (0U)
85612 /*! CES - CE setup time
85613  */
85614 #define SEMC_SRAMCR5_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK)
85615 
85616 #define SEMC_SRAMCR5_CEH_MASK                    (0xF0U)
85617 #define SEMC_SRAMCR5_CEH_SHIFT                   (4U)
85618 /*! CEH - CE hold time
85619  */
85620 #define SEMC_SRAMCR5_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK)
85621 
85622 #define SEMC_SRAMCR5_AS_MASK                     (0xF00U)
85623 #define SEMC_SRAMCR5_AS_SHIFT                    (8U)
85624 /*! AS - Address setup time
85625  */
85626 #define SEMC_SRAMCR5_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK)
85627 
85628 #define SEMC_SRAMCR5_AH_MASK                     (0xF000U)
85629 #define SEMC_SRAMCR5_AH_SHIFT                    (12U)
85630 /*! AH - Address hold time
85631  */
85632 #define SEMC_SRAMCR5_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK)
85633 
85634 #define SEMC_SRAMCR5_WEL_MASK                    (0xF0000U)
85635 #define SEMC_SRAMCR5_WEL_SHIFT                   (16U)
85636 /*! WEL - WE low time
85637  */
85638 #define SEMC_SRAMCR5_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK)
85639 
85640 #define SEMC_SRAMCR5_WEH_MASK                    (0xF00000U)
85641 #define SEMC_SRAMCR5_WEH_SHIFT                   (20U)
85642 /*! WEH - WE high time
85643  */
85644 #define SEMC_SRAMCR5_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK)
85645 
85646 #define SEMC_SRAMCR5_REL_MASK                    (0xF000000U)
85647 #define SEMC_SRAMCR5_REL_SHIFT                   (24U)
85648 /*! REL - RE low time
85649  */
85650 #define SEMC_SRAMCR5_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK)
85651 
85652 #define SEMC_SRAMCR5_REH_MASK                    (0xF0000000U)
85653 #define SEMC_SRAMCR5_REH_SHIFT                   (28U)
85654 /*! REH - RE high time
85655  */
85656 #define SEMC_SRAMCR5_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK)
85657 /*! @} */
85658 
85659 /*! @name SRAMCR6 - SRAM Control Register 6 */
85660 /*! @{ */
85661 
85662 #define SEMC_SRAMCR6_WDS_MASK                    (0xFU)
85663 #define SEMC_SRAMCR6_WDS_SHIFT                   (0U)
85664 /*! WDS - Write Data setup time
85665  */
85666 #define SEMC_SRAMCR6_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK)
85667 
85668 #define SEMC_SRAMCR6_WDH_MASK                    (0xF0U)
85669 #define SEMC_SRAMCR6_WDH_SHIFT                   (4U)
85670 /*! WDH - Write Data hold time
85671  */
85672 #define SEMC_SRAMCR6_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK)
85673 
85674 #define SEMC_SRAMCR6_TA_MASK                     (0xF00U)
85675 #define SEMC_SRAMCR6_TA_SHIFT                    (8U)
85676 /*! TA - Turnaround time
85677  */
85678 #define SEMC_SRAMCR6_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK)
85679 
85680 #define SEMC_SRAMCR6_AWDH_MASK                   (0xF000U)
85681 #define SEMC_SRAMCR6_AWDH_SHIFT                  (12U)
85682 /*! AWDH - Address to write data hold time
85683  */
85684 #define SEMC_SRAMCR6_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK)
85685 
85686 #define SEMC_SRAMCR6_LC_MASK                     (0xF0000U)
85687 #define SEMC_SRAMCR6_LC_SHIFT                    (16U)
85688 /*! LC - Latency count
85689  */
85690 #define SEMC_SRAMCR6_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK)
85691 
85692 #define SEMC_SRAMCR6_RD_MASK                     (0xF00000U)
85693 #define SEMC_SRAMCR6_RD_SHIFT                    (20U)
85694 /*! RD - Read time
85695  */
85696 #define SEMC_SRAMCR6_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK)
85697 
85698 #define SEMC_SRAMCR6_CEITV_MASK                  (0xF000000U)
85699 #define SEMC_SRAMCR6_CEITV_SHIFT                 (24U)
85700 /*! CEITV - CE# interval time
85701  */
85702 #define SEMC_SRAMCR6_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK)
85703 
85704 #define SEMC_SRAMCR6_RDH_MASK                    (0xF0000000U)
85705 #define SEMC_SRAMCR6_RDH_SHIFT                   (28U)
85706 /*! RDH - Read hold time
85707  */
85708 #define SEMC_SRAMCR6_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK)
85709 /*! @} */
85710 
85711 /*! @name DCCR - Delay Chain Control Register */
85712 /*! @{ */
85713 
85714 #define SEMC_DCCR_SDRAMEN_MASK                   (0x1U)
85715 #define SEMC_DCCR_SDRAMEN_SHIFT                  (0U)
85716 /*! SDRAMEN - Delay chain insertion enable for SRAM device.
85717  *  0b0..Delay chain is not inserted.
85718  *  0b1..Delay chain is inserted.
85719  */
85720 #define SEMC_DCCR_SDRAMEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK)
85721 
85722 #define SEMC_DCCR_SDRAMVAL_MASK                  (0x3EU)
85723 #define SEMC_DCCR_SDRAMVAL_SHIFT                 (1U)
85724 /*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device.
85725  */
85726 #define SEMC_DCCR_SDRAMVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK)
85727 
85728 #define SEMC_DCCR_NOREN_MASK                     (0x100U)
85729 #define SEMC_DCCR_NOREN_SHIFT                    (8U)
85730 /*! NOREN - Delay chain insertion enable for NOR device.
85731  *  0b0..Delay chain is not inserted.
85732  *  0b1..Delay chain is inserted.
85733  */
85734 #define SEMC_DCCR_NOREN(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK)
85735 
85736 #define SEMC_DCCR_NORVAL_MASK                    (0x3E00U)
85737 #define SEMC_DCCR_NORVAL_SHIFT                   (9U)
85738 /*! NORVAL - Clock delay line delay cell number selection value for NOR device.
85739  */
85740 #define SEMC_DCCR_NORVAL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK)
85741 
85742 #define SEMC_DCCR_SRAM0EN_MASK                   (0x10000U)
85743 #define SEMC_DCCR_SRAM0EN_SHIFT                  (16U)
85744 /*! SRAM0EN - Delay chain insertion enable for SRAM device 0.
85745  *  0b0..Delay chain is not inserted.
85746  *  0b1..Delay chain is inserted.
85747  */
85748 #define SEMC_DCCR_SRAM0EN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK)
85749 
85750 #define SEMC_DCCR_SRAM0VAL_MASK                  (0x3E0000U)
85751 #define SEMC_DCCR_SRAM0VAL_SHIFT                 (17U)
85752 /*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0.
85753  */
85754 #define SEMC_DCCR_SRAM0VAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK)
85755 
85756 #define SEMC_DCCR_SRAMXEN_MASK                   (0x1000000U)
85757 #define SEMC_DCCR_SRAMXEN_SHIFT                  (24U)
85758 /*! SRAMXEN - Delay chain insertion enable for SRAM device 1-3.
85759  *  0b0..Delay chain is not inserted.
85760  *  0b1..Delay chain is inserted.
85761  */
85762 #define SEMC_DCCR_SRAMXEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK)
85763 
85764 #define SEMC_DCCR_SRAMXVAL_MASK                  (0x3E000000U)
85765 #define SEMC_DCCR_SRAMXVAL_SHIFT                 (25U)
85766 /*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3.
85767  */
85768 #define SEMC_DCCR_SRAMXVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK)
85769 /*! @} */
85770 
85771 
85772 /*!
85773  * @}
85774  */ /* end of group SEMC_Register_Masks */
85775 
85776 
85777 /* SEMC - Peripheral instance base addresses */
85778 /** Peripheral SEMC base address */
85779 #define SEMC_BASE                                (0x400D4000u)
85780 /** Peripheral SEMC base pointer */
85781 #define SEMC                                     ((SEMC_Type *)SEMC_BASE)
85782 /** Array initializer of SEMC peripheral base addresses */
85783 #define SEMC_BASE_ADDRS                          { SEMC_BASE }
85784 /** Array initializer of SEMC peripheral base pointers */
85785 #define SEMC_BASE_PTRS                           { SEMC }
85786 /** Interrupt vectors for the SEMC peripheral type */
85787 #define SEMC_IRQS                                { SEMC_IRQn }
85788 
85789 /*!
85790  * @}
85791  */ /* end of group SEMC_Peripheral_Access_Layer */
85792 
85793 
85794 /* ----------------------------------------------------------------------------
85795    -- SNVS Peripheral Access Layer
85796    ---------------------------------------------------------------------------- */
85797 
85798 /*!
85799  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
85800  * @{
85801  */
85802 
85803 /** SNVS - Register Layout Typedef */
85804 typedef struct {
85805   __IO uint32_t HPLR;                              /**< SNVS_HP Lock Register, offset: 0x0 */
85806   __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
85807   __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
85808   __IO uint32_t HPSICR;                            /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
85809   __IO uint32_t HPSVCR;                            /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
85810   __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
85811   __IO uint32_t HPSVSR;                            /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
85812   __IO uint32_t HPHACIVR;                          /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
85813   __I  uint32_t HPHACR;                            /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
85814   __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
85815   __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
85816   __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
85817   __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
85818   __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
85819   __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
85820   __IO uint32_t LPMKCR;                            /**< SNVS_LP Master Key Control Register, offset: 0x3C */
85821   __IO uint32_t LPSVCR;                            /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
85822   __IO uint32_t LPTGFCR;                           /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */
85823   __IO uint32_t LPTDCR;                            /**< SNVS_LP Tamper Detect Configuration Register, offset: 0x48 */
85824   __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
85825   __IO uint32_t LPSRTCMR;                          /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
85826   __IO uint32_t LPSRTCLR;                          /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
85827   __IO uint32_t LPTAR;                             /**< SNVS_LP Time Alarm Register, offset: 0x58 */
85828   __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
85829   __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
85830   __IO uint32_t LPLVDR;                            /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */
85831   __IO uint32_t LPGPR0_LEGACY_ALIAS;               /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
85832   __IO uint32_t LPZMKR[8];                         /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
85833        uint8_t RESERVED_0[4];
85834   __IO uint32_t LPGPR_ALIAS[4];                    /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
85835   __IO uint32_t LPTDC2R;                           /**< SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0 */
85836   __IO uint32_t LPTDSR;                            /**< SNVS_LP Tamper Detectors Status Register, offset: 0xA4 */
85837   __IO uint32_t LPTGF1CR;                          /**< SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8 */
85838   __IO uint32_t LPTGF2CR;                          /**< SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC */
85839        uint8_t RESERVED_1[16];
85840   __O  uint32_t LPATCR[5];                         /**< SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4 */
85841        uint8_t RESERVED_2[12];
85842   __IO uint32_t LPATCTLR;                          /**< SNVS_LP Active Tamper Control Register, offset: 0xE0 */
85843   __IO uint32_t LPATCLKR;                          /**< SNVS_LP Active Tamper Clock Control Register, offset: 0xE4 */
85844   __IO uint32_t LPATRC1R;                          /**< SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8 */
85845   __IO uint32_t LPATRC2R;                          /**< SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC */
85846        uint8_t RESERVED_3[16];
85847   __IO uint32_t LPGPR[4];                          /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
85848        uint8_t RESERVED_4[2792];
85849   __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
85850   __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
85851 } SNVS_Type;
85852 
85853 /* ----------------------------------------------------------------------------
85854    -- SNVS Register Masks
85855    ---------------------------------------------------------------------------- */
85856 
85857 /*!
85858  * @addtogroup SNVS_Register_Masks SNVS Register Masks
85859  * @{
85860  */
85861 
85862 /*! @name HPLR - SNVS_HP Lock Register */
85863 /*! @{ */
85864 
85865 #define SNVS_HPLR_ZMK_WSL_MASK                   (0x1U)
85866 #define SNVS_HPLR_ZMK_WSL_SHIFT                  (0U)
85867 /*! ZMK_WSL
85868  *  0b0..Write access is allowed
85869  *  0b1..Write access is not allowed
85870  */
85871 #define SNVS_HPLR_ZMK_WSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
85872 
85873 #define SNVS_HPLR_ZMK_RSL_MASK                   (0x2U)
85874 #define SNVS_HPLR_ZMK_RSL_SHIFT                  (1U)
85875 /*! ZMK_RSL
85876  *  0b0..Read access is allowed (only in software Programming mode)
85877  *  0b1..Read access is not allowed
85878  */
85879 #define SNVS_HPLR_ZMK_RSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
85880 
85881 #define SNVS_HPLR_SRTC_SL_MASK                   (0x4U)
85882 #define SNVS_HPLR_SRTC_SL_SHIFT                  (2U)
85883 /*! SRTC_SL
85884  *  0b0..Write access is allowed
85885  *  0b1..Write access is not allowed
85886  */
85887 #define SNVS_HPLR_SRTC_SL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
85888 
85889 #define SNVS_HPLR_LPCALB_SL_MASK                 (0x8U)
85890 #define SNVS_HPLR_LPCALB_SL_SHIFT                (3U)
85891 /*! LPCALB_SL
85892  *  0b0..Write access is allowed
85893  *  0b1..Write access is not allowed
85894  */
85895 #define SNVS_HPLR_LPCALB_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
85896 
85897 #define SNVS_HPLR_MC_SL_MASK                     (0x10U)
85898 #define SNVS_HPLR_MC_SL_SHIFT                    (4U)
85899 /*! MC_SL
85900  *  0b0..Write access (increment) is allowed
85901  *  0b1..Write access (increment) is not allowed
85902  */
85903 #define SNVS_HPLR_MC_SL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
85904 
85905 #define SNVS_HPLR_GPR_SL_MASK                    (0x20U)
85906 #define SNVS_HPLR_GPR_SL_SHIFT                   (5U)
85907 /*! GPR_SL
85908  *  0b0..Write access is allowed
85909  *  0b1..Write access is not allowed
85910  */
85911 #define SNVS_HPLR_GPR_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
85912 
85913 #define SNVS_HPLR_LPSVCR_SL_MASK                 (0x40U)
85914 #define SNVS_HPLR_LPSVCR_SL_SHIFT                (6U)
85915 /*! LPSVCR_SL
85916  *  0b0..Write access is allowed
85917  *  0b1..Write access is not allowed
85918  */
85919 #define SNVS_HPLR_LPSVCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
85920 
85921 #define SNVS_HPLR_LPTGFCR_SL_MASK                (0x80U)
85922 #define SNVS_HPLR_LPTGFCR_SL_SHIFT               (7U)
85923 /*! LPTGFCR_SL
85924  *  0b0..Write access is allowed
85925  *  0b1..Write access is not allowed
85926  */
85927 #define SNVS_HPLR_LPTGFCR_SL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
85928 
85929 #define SNVS_HPLR_LPSECR_SL_MASK                 (0x100U)
85930 #define SNVS_HPLR_LPSECR_SL_SHIFT                (8U)
85931 /*! LPSECR_SL
85932  *  0b0..Write access is allowed
85933  *  0b1..Write access is not allowed
85934  */
85935 #define SNVS_HPLR_LPSECR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
85936 
85937 #define SNVS_HPLR_MKS_SL_MASK                    (0x200U)
85938 #define SNVS_HPLR_MKS_SL_SHIFT                   (9U)
85939 /*! MKS_SL
85940  *  0b0..Write access is allowed
85941  *  0b1..Write access is not allowed
85942  */
85943 #define SNVS_HPLR_MKS_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
85944 
85945 #define SNVS_HPLR_HPSVCR_L_MASK                  (0x10000U)
85946 #define SNVS_HPLR_HPSVCR_L_SHIFT                 (16U)
85947 /*! HPSVCR_L
85948  *  0b0..Write access is allowed
85949  *  0b1..Write access is not allowed
85950  */
85951 #define SNVS_HPLR_HPSVCR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
85952 
85953 #define SNVS_HPLR_HPSICR_L_MASK                  (0x20000U)
85954 #define SNVS_HPLR_HPSICR_L_SHIFT                 (17U)
85955 /*! HPSICR_L
85956  *  0b0..Write access is allowed
85957  *  0b1..Write access is not allowed
85958  */
85959 #define SNVS_HPLR_HPSICR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
85960 
85961 #define SNVS_HPLR_HAC_L_MASK                     (0x40000U)
85962 #define SNVS_HPLR_HAC_L_SHIFT                    (18U)
85963 /*! HAC_L
85964  *  0b0..Write access is allowed
85965  *  0b1..Write access is not allowed
85966  */
85967 #define SNVS_HPLR_HAC_L(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
85968 
85969 #define SNVS_HPLR_AT1_SL_MASK                    (0x1000000U)
85970 #define SNVS_HPLR_AT1_SL_SHIFT                   (24U)
85971 /*! AT1_SL
85972  *  0b0..Write access is allowed.
85973  *  0b1..Write access is not allowed.
85974  */
85975 #define SNVS_HPLR_AT1_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
85976 
85977 #define SNVS_HPLR_AT2_SL_MASK                    (0x2000000U)
85978 #define SNVS_HPLR_AT2_SL_SHIFT                   (25U)
85979 /*! AT2_SL
85980  *  0b0..Write access is allowed.
85981  *  0b1..Write access is not allowed.
85982  */
85983 #define SNVS_HPLR_AT2_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
85984 
85985 #define SNVS_HPLR_AT3_SL_MASK                    (0x4000000U)
85986 #define SNVS_HPLR_AT3_SL_SHIFT                   (26U)
85987 /*! AT3_SL
85988  *  0b0..Write access is allowed.
85989  *  0b1..Write access is not allowed.
85990  */
85991 #define SNVS_HPLR_AT3_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
85992 
85993 #define SNVS_HPLR_AT4_SL_MASK                    (0x8000000U)
85994 #define SNVS_HPLR_AT4_SL_SHIFT                   (27U)
85995 /*! AT4_SL
85996  *  0b0..Write access is allowed.
85997  *  0b1..Write access is not allowed.
85998  */
85999 #define SNVS_HPLR_AT4_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
86000 
86001 #define SNVS_HPLR_AT5_SL_MASK                    (0x10000000U)
86002 #define SNVS_HPLR_AT5_SL_SHIFT                   (28U)
86003 /*! AT5_SL
86004  *  0b0..Write access is allowed.
86005  *  0b1..Write access is not allowed.
86006  */
86007 #define SNVS_HPLR_AT5_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
86008 /*! @} */
86009 
86010 /*! @name HPCOMR - SNVS_HP Command Register */
86011 /*! @{ */
86012 
86013 #define SNVS_HPCOMR_SSM_ST_MASK                  (0x1U)
86014 #define SNVS_HPCOMR_SSM_ST_SHIFT                 (0U)
86015 #define SNVS_HPCOMR_SSM_ST(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
86016 
86017 #define SNVS_HPCOMR_SSM_ST_DIS_MASK              (0x2U)
86018 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             (1U)
86019 /*! SSM_ST_DIS
86020  *  0b0..Secure to Trusted State transition is enabled
86021  *  0b1..Secure to Trusted State transition is disabled
86022  */
86023 #define SNVS_HPCOMR_SSM_ST_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
86024 
86025 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            (0x4U)
86026 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           (2U)
86027 /*! SSM_SFNS_DIS
86028  *  0b0..Soft Fail to Non-Secure State transition is enabled
86029  *  0b1..Soft Fail to Non-Secure State transition is disabled
86030  */
86031 #define SNVS_HPCOMR_SSM_SFNS_DIS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
86032 
86033 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
86034 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
86035 /*! LP_SWR
86036  *  0b0..No Action
86037  *  0b1..Reset LP section
86038  */
86039 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
86040 
86041 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
86042 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
86043 /*! LP_SWR_DIS
86044  *  0b0..LP software reset is enabled
86045  *  0b1..LP software reset is disabled
86046  */
86047 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
86048 
86049 #define SNVS_HPCOMR_SW_SV_MASK                   (0x100U)
86050 #define SNVS_HPCOMR_SW_SV_SHIFT                  (8U)
86051 #define SNVS_HPCOMR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
86052 
86053 #define SNVS_HPCOMR_SW_FSV_MASK                  (0x200U)
86054 #define SNVS_HPCOMR_SW_FSV_SHIFT                 (9U)
86055 #define SNVS_HPCOMR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
86056 
86057 #define SNVS_HPCOMR_SW_LPSV_MASK                 (0x400U)
86058 #define SNVS_HPCOMR_SW_LPSV_SHIFT                (10U)
86059 #define SNVS_HPCOMR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
86060 
86061 #define SNVS_HPCOMR_PROG_ZMK_MASK                (0x1000U)
86062 #define SNVS_HPCOMR_PROG_ZMK_SHIFT               (12U)
86063 /*! PROG_ZMK
86064  *  0b0..No Action
86065  *  0b1..Activate hardware key programming mechanism
86066  */
86067 #define SNVS_HPCOMR_PROG_ZMK(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
86068 
86069 #define SNVS_HPCOMR_MKS_EN_MASK                  (0x2000U)
86070 #define SNVS_HPCOMR_MKS_EN_SHIFT                 (13U)
86071 /*! MKS_EN
86072  *  0b0..OTP master key is selected as an SNVS master key
86073  *  0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
86074  */
86075 #define SNVS_HPCOMR_MKS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
86076 
86077 #define SNVS_HPCOMR_HAC_EN_MASK                  (0x10000U)
86078 #define SNVS_HPCOMR_HAC_EN_SHIFT                 (16U)
86079 /*! HAC_EN
86080  *  0b0..High Assurance Counter is disabled
86081  *  0b1..High Assurance Counter is enabled
86082  */
86083 #define SNVS_HPCOMR_HAC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
86084 
86085 #define SNVS_HPCOMR_HAC_LOAD_MASK                (0x20000U)
86086 #define SNVS_HPCOMR_HAC_LOAD_SHIFT               (17U)
86087 /*! HAC_LOAD
86088  *  0b0..No Action
86089  *  0b1..Load the HAC
86090  */
86091 #define SNVS_HPCOMR_HAC_LOAD(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
86092 
86093 #define SNVS_HPCOMR_HAC_CLEAR_MASK               (0x40000U)
86094 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT              (18U)
86095 /*! HAC_CLEAR
86096  *  0b0..No Action
86097  *  0b1..Clear the HAC
86098  */
86099 #define SNVS_HPCOMR_HAC_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
86100 
86101 #define SNVS_HPCOMR_HAC_STOP_MASK                (0x80000U)
86102 #define SNVS_HPCOMR_HAC_STOP_SHIFT               (19U)
86103 #define SNVS_HPCOMR_HAC_STOP(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
86104 
86105 #define SNVS_HPCOMR_NPSWA_EN_MASK                (0x80000000U)
86106 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               (31U)
86107 #define SNVS_HPCOMR_NPSWA_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
86108 /*! @} */
86109 
86110 /*! @name HPCR - SNVS_HP Control Register */
86111 /*! @{ */
86112 
86113 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
86114 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
86115 /*! RTC_EN
86116  *  0b0..RTC is disabled
86117  *  0b1..RTC is enabled
86118  */
86119 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
86120 
86121 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
86122 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
86123 /*! HPTA_EN
86124  *  0b0..HP Time Alarm Interrupt is disabled
86125  *  0b1..HP Time Alarm Interrupt is enabled
86126  */
86127 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
86128 
86129 #define SNVS_HPCR_DIS_PI_MASK                    (0x4U)
86130 #define SNVS_HPCR_DIS_PI_SHIFT                   (2U)
86131 /*! DIS_PI
86132  *  0b0..Periodic interrupt will trigger a functional interrupt
86133  *  0b1..Disable periodic interrupt in the function interrupt
86134  */
86135 #define SNVS_HPCR_DIS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
86136 
86137 #define SNVS_HPCR_PI_EN_MASK                     (0x8U)
86138 #define SNVS_HPCR_PI_EN_SHIFT                    (3U)
86139 /*! PI_EN
86140  *  0b0..HP Periodic Interrupt is disabled
86141  *  0b1..HP Periodic Interrupt is enabled
86142  */
86143 #define SNVS_HPCR_PI_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
86144 
86145 #define SNVS_HPCR_PI_FREQ_MASK                   (0xF0U)
86146 #define SNVS_HPCR_PI_FREQ_SHIFT                  (4U)
86147 /*! PI_FREQ
86148  *  0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
86149  *  0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
86150  *  0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
86151  *  0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
86152  *  0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
86153  *  0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
86154  *  0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
86155  *  0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
86156  *  0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
86157  *  0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
86158  *  0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
86159  *  0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
86160  *  0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
86161  *  0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
86162  *  0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
86163  *  0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
86164  */
86165 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
86166 
86167 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
86168 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
86169 /*! HPCALB_EN
86170  *  0b0..HP Timer calibration disabled
86171  *  0b1..HP Timer calibration enabled
86172  */
86173 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
86174 
86175 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
86176 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
86177 /*! HPCALB_VAL
86178  *  0b00000..+0 counts per each 32768 ticks of the counter
86179  *  0b00001..+1 counts per each 32768 ticks of the counter
86180  *  0b00010..+2 counts per each 32768 ticks of the counter
86181  *  0b01111..+15 counts per each 32768 ticks of the counter
86182  *  0b10000..-16 counts per each 32768 ticks of the counter
86183  *  0b10001..-15 counts per each 32768 ticks of the counter
86184  *  0b11110..-2 counts per each 32768 ticks of the counter
86185  *  0b11111..-1 counts per each 32768 ticks of the counter
86186  */
86187 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
86188 
86189 #define SNVS_HPCR_HP_TS_MASK                     (0x10000U)
86190 #define SNVS_HPCR_HP_TS_SHIFT                    (16U)
86191 /*! HP_TS
86192  *  0b0..No Action
86193  *  0b1..Synchronize the HP Time Counter to the LP Time Counter
86194  */
86195 #define SNVS_HPCR_HP_TS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
86196 
86197 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
86198 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
86199 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
86200 
86201 #define SNVS_HPCR_BTN_MASK_MASK                  (0x8000000U)
86202 #define SNVS_HPCR_BTN_MASK_SHIFT                 (27U)
86203 #define SNVS_HPCR_BTN_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
86204 /*! @} */
86205 
86206 /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
86207 /*! @{ */
86208 
86209 #define SNVS_HPSICR_CAAM_EN_MASK                 (0x1U)
86210 #define SNVS_HPSICR_CAAM_EN_SHIFT                (0U)
86211 /*! CAAM_EN
86212  *  0b0..CAAM Security Violation Interrupt is Disabled
86213  *  0b1..CAAM Security Violation Interrupt is Enabled
86214  */
86215 #define SNVS_HPSICR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
86216 
86217 #define SNVS_HPSICR_JTAGC_EN_MASK                (0x2U)
86218 #define SNVS_HPSICR_JTAGC_EN_SHIFT               (1U)
86219 /*! JTAGC_EN
86220  *  0b0..JTAG Active Interrupt is Disabled
86221  *  0b1..JTAG Active Interrupt is Enabled
86222  */
86223 #define SNVS_HPSICR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
86224 
86225 #define SNVS_HPSICR_WDOG2_EN_MASK                (0x4U)
86226 #define SNVS_HPSICR_WDOG2_EN_SHIFT               (2U)
86227 /*! WDOG2_EN
86228  *  0b0..Watchdog 2 Reset Interrupt is Disabled
86229  *  0b1..Watchdog 2 Reset Interrupt is Enabled
86230  */
86231 #define SNVS_HPSICR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
86232 
86233 #define SNVS_HPSICR_SRC_EN_MASK                  (0x10U)
86234 #define SNVS_HPSICR_SRC_EN_SHIFT                 (4U)
86235 /*! SRC_EN
86236  *  0b0..Internal Boot Interrupt is Disabled
86237  *  0b1..Internal Boot Interrupt is Enabled
86238  */
86239 #define SNVS_HPSICR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
86240 
86241 #define SNVS_HPSICR_OCOTP_EN_MASK                (0x20U)
86242 #define SNVS_HPSICR_OCOTP_EN_SHIFT               (5U)
86243 /*! OCOTP_EN
86244  *  0b0..OCOTP attack error Interrupt is Disabled
86245  *  0b1..OCOTP attack error Interrupt is Enabled
86246  */
86247 #define SNVS_HPSICR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
86248 
86249 #define SNVS_HPSICR_LPSVI_EN_MASK                (0x80000000U)
86250 #define SNVS_HPSICR_LPSVI_EN_SHIFT               (31U)
86251 /*! LPSVI_EN
86252  *  0b0..LP Security Violation Interrupt is Disabled
86253  *  0b1..LP Security Violation Interrupt is Enabled
86254  */
86255 #define SNVS_HPSICR_LPSVI_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
86256 /*! @} */
86257 
86258 /*! @name HPSVCR - SNVS_HP Security Violation Control Register */
86259 /*! @{ */
86260 
86261 #define SNVS_HPSVCR_CAAM_CFG_MASK                (0x1U)
86262 #define SNVS_HPSVCR_CAAM_CFG_SHIFT               (0U)
86263 /*! CAAM_CFG
86264  *  0b0..CAAM Security Violation is a non-fatal violation
86265  *  0b1..CAAM Security Violation is a fatal violation
86266  */
86267 #define SNVS_HPSVCR_CAAM_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
86268 
86269 #define SNVS_HPSVCR_JTAGC_CFG_MASK               (0x2U)
86270 #define SNVS_HPSVCR_JTAGC_CFG_SHIFT              (1U)
86271 /*! JTAGC_CFG
86272  *  0b0..JTAG Active is a non-fatal violation
86273  *  0b1..JTAG Active is a fatal violation
86274  */
86275 #define SNVS_HPSVCR_JTAGC_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
86276 
86277 #define SNVS_HPSVCR_WDOG2_CFG_MASK               (0x4U)
86278 #define SNVS_HPSVCR_WDOG2_CFG_SHIFT              (2U)
86279 /*! WDOG2_CFG
86280  *  0b0..Watchdog 2 Reset is a non-fatal violation
86281  *  0b1..Watchdog 2 Reset is a fatal violation
86282  */
86283 #define SNVS_HPSVCR_WDOG2_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
86284 
86285 #define SNVS_HPSVCR_SRC_CFG_MASK                 (0x10U)
86286 #define SNVS_HPSVCR_SRC_CFG_SHIFT                (4U)
86287 /*! SRC_CFG
86288  *  0b0..Internal Boot is a non-fatal violation
86289  *  0b1..Internal Boot is a fatal violation
86290  */
86291 #define SNVS_HPSVCR_SRC_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
86292 
86293 #define SNVS_HPSVCR_OCOTP_CFG_MASK               (0x60U)
86294 #define SNVS_HPSVCR_OCOTP_CFG_SHIFT              (5U)
86295 /*! OCOTP_CFG
86296  *  0b00..OCOTP attack error is disabled
86297  *  0b01..OCOTP attack error is a non-fatal violation
86298  *  0b1x..OCOTP attack error is a fatal violation
86299  */
86300 #define SNVS_HPSVCR_OCOTP_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
86301 
86302 #define SNVS_HPSVCR_LPSV_CFG_MASK                (0xC0000000U)
86303 #define SNVS_HPSVCR_LPSV_CFG_SHIFT               (30U)
86304 /*! LPSV_CFG
86305  *  0b00..LP security violation is disabled
86306  *  0b01..LP security violation is a non-fatal violation
86307  *  0b1x..LP security violation is a fatal violation
86308  */
86309 #define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
86310 /*! @} */
86311 
86312 /*! @name HPSR - SNVS_HP Status Register */
86313 /*! @{ */
86314 
86315 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
86316 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
86317 /*! HPTA
86318  *  0b0..No time alarm interrupt occurred.
86319  *  0b1..A time alarm interrupt occurred.
86320  */
86321 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
86322 
86323 #define SNVS_HPSR_PI_MASK                        (0x2U)
86324 #define SNVS_HPSR_PI_SHIFT                       (1U)
86325 /*! PI
86326  *  0b0..No periodic interrupt occurred.
86327  *  0b1..A periodic interrupt occurred.
86328  */
86329 #define SNVS_HPSR_PI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
86330 
86331 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
86332 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
86333 #define SNVS_HPSR_LPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
86334 
86335 #define SNVS_HPSR_BTN_MASK                       (0x40U)
86336 #define SNVS_HPSR_BTN_SHIFT                      (6U)
86337 #define SNVS_HPSR_BTN(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
86338 
86339 #define SNVS_HPSR_BI_MASK                        (0x80U)
86340 #define SNVS_HPSR_BI_SHIFT                       (7U)
86341 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
86342 
86343 #define SNVS_HPSR_SSM_STATE_MASK                 (0xF00U)
86344 #define SNVS_HPSR_SSM_STATE_SHIFT                (8U)
86345 /*! SSM_STATE
86346  *  0b0000..Init
86347  *  0b0001..Hard Fail
86348  *  0b0011..Soft Fail
86349  *  0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
86350  *  0b1001..Check
86351  *  0b1011..Non-Secure
86352  *  0b1101..Trusted
86353  *  0b1111..Secure
86354  */
86355 #define SNVS_HPSR_SSM_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
86356 
86357 #define SNVS_HPSR_SYS_SECURITY_CFG_MASK          (0x7000U)
86358 #define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT         (12U)
86359 /*! SYS_SECURITY_CFG
86360  *  0b000..Fab Configuration - the default configuration of newly fabricated chips
86361  *  0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown
86362  *  0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown
86363  *  0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis
86364  */
86365 #define SNVS_HPSR_SYS_SECURITY_CFG(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
86366 
86367 #define SNVS_HPSR_SYS_SECURE_BOOT_MASK           (0x8000U)
86368 #define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT          (15U)
86369 #define SNVS_HPSR_SYS_SECURE_BOOT(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
86370 
86371 #define SNVS_HPSR_OTPMK_ZERO_MASK                (0x8000000U)
86372 #define SNVS_HPSR_OTPMK_ZERO_SHIFT               (27U)
86373 /*! OTPMK_ZERO
86374  *  0b0..The OTPMK is not zero.
86375  *  0b1..The OTPMK is zero.
86376  */
86377 #define SNVS_HPSR_OTPMK_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
86378 
86379 #define SNVS_HPSR_ZMK_ZERO_MASK                  (0x80000000U)
86380 #define SNVS_HPSR_ZMK_ZERO_SHIFT                 (31U)
86381 /*! ZMK_ZERO
86382  *  0b0..The ZMK is not zero.
86383  *  0b1..The ZMK is zero.
86384  */
86385 #define SNVS_HPSR_ZMK_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
86386 /*! @} */
86387 
86388 /*! @name HPSVSR - SNVS_HP Security Violation Status Register */
86389 /*! @{ */
86390 
86391 #define SNVS_HPSVSR_CAAM_MASK                    (0x1U)
86392 #define SNVS_HPSVSR_CAAM_SHIFT                   (0U)
86393 /*! CAAM
86394  *  0b0..No CAAM Security Violation security violation was detected.
86395  *  0b1..CAAM Security Violation security violation was detected.
86396  */
86397 #define SNVS_HPSVSR_CAAM(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
86398 
86399 #define SNVS_HPSVSR_JTAGC_MASK                   (0x2U)
86400 #define SNVS_HPSVSR_JTAGC_SHIFT                  (1U)
86401 /*! JTAGC
86402  *  0b0..No JTAG Active security violation was detected.
86403  *  0b1..JTAG Active security violation was detected.
86404  */
86405 #define SNVS_HPSVSR_JTAGC(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
86406 
86407 #define SNVS_HPSVSR_WDOG2_MASK                   (0x4U)
86408 #define SNVS_HPSVSR_WDOG2_SHIFT                  (2U)
86409 /*! WDOG2
86410  *  0b0..No Watchdog 2 Reset security violation was detected.
86411  *  0b1..Watchdog 2 Reset security violation was detected.
86412  */
86413 #define SNVS_HPSVSR_WDOG2(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
86414 
86415 #define SNVS_HPSVSR_SRC_MASK                     (0x10U)
86416 #define SNVS_HPSVSR_SRC_SHIFT                    (4U)
86417 /*! SRC
86418  *  0b0..No Internal Boot security violation was detected.
86419  *  0b1..Internal Boot security violation was detected.
86420  */
86421 #define SNVS_HPSVSR_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
86422 
86423 #define SNVS_HPSVSR_OCOTP_MASK                   (0x20U)
86424 #define SNVS_HPSVSR_OCOTP_SHIFT                  (5U)
86425 /*! OCOTP
86426  *  0b0..No OCOTP attack error security violation was detected.
86427  *  0b1..OCOTP attack error security violation was detected.
86428  */
86429 #define SNVS_HPSVSR_OCOTP(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
86430 
86431 #define SNVS_HPSVSR_SW_SV_MASK                   (0x2000U)
86432 #define SNVS_HPSVSR_SW_SV_SHIFT                  (13U)
86433 #define SNVS_HPSVSR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
86434 
86435 #define SNVS_HPSVSR_SW_FSV_MASK                  (0x4000U)
86436 #define SNVS_HPSVSR_SW_FSV_SHIFT                 (14U)
86437 #define SNVS_HPSVSR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
86438 
86439 #define SNVS_HPSVSR_SW_LPSV_MASK                 (0x8000U)
86440 #define SNVS_HPSVSR_SW_LPSV_SHIFT                (15U)
86441 #define SNVS_HPSVSR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
86442 
86443 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK            (0x1FF0000U)
86444 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT           (16U)
86445 #define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
86446 
86447 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            (0x8000000U)
86448 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           (27U)
86449 /*! ZMK_ECC_FAIL
86450  *  0b0..ZMK ECC Failure was not detected.
86451  *  0b1..ZMK ECC Failure was detected.
86452  */
86453 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
86454 
86455 #define SNVS_HPSVSR_LP_SEC_VIO_MASK              (0x80000000U)
86456 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT             (31U)
86457 #define SNVS_HPSVSR_LP_SEC_VIO(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
86458 /*! @} */
86459 
86460 /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
86461 /*! @{ */
86462 
86463 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK        (0xFFFFFFFFU)
86464 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT       (0U)
86465 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
86466 /*! @} */
86467 
86468 /*! @name HPHACR - SNVS_HP High Assurance Counter Register */
86469 /*! @{ */
86470 
86471 #define SNVS_HPHACR_HAC_COUNTER_MASK             (0xFFFFFFFFU)
86472 #define SNVS_HPHACR_HAC_COUNTER_SHIFT            (0U)
86473 #define SNVS_HPHACR_HAC_COUNTER(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
86474 /*! @} */
86475 
86476 /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
86477 /*! @{ */
86478 
86479 #define SNVS_HPRTCMR_RTC_MASK                    (0x7FFFU)
86480 #define SNVS_HPRTCMR_RTC_SHIFT                   (0U)
86481 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
86482 /*! @} */
86483 
86484 /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
86485 /*! @{ */
86486 
86487 #define SNVS_HPRTCLR_RTC_MASK                    (0xFFFFFFFFU)
86488 #define SNVS_HPRTCLR_RTC_SHIFT                   (0U)
86489 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
86490 /*! @} */
86491 
86492 /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
86493 /*! @{ */
86494 
86495 #define SNVS_HPTAMR_HPTA_MS_MASK                 (0x7FFFU)
86496 #define SNVS_HPTAMR_HPTA_MS_SHIFT                (0U)
86497 #define SNVS_HPTAMR_HPTA_MS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
86498 /*! @} */
86499 
86500 /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
86501 /*! @{ */
86502 
86503 #define SNVS_HPTALR_HPTA_LS_MASK                 (0xFFFFFFFFU)
86504 #define SNVS_HPTALR_HPTA_LS_SHIFT                (0U)
86505 #define SNVS_HPTALR_HPTA_LS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
86506 /*! @} */
86507 
86508 /*! @name LPLR - SNVS_LP Lock Register */
86509 /*! @{ */
86510 
86511 #define SNVS_LPLR_ZMK_WHL_MASK                   (0x1U)
86512 #define SNVS_LPLR_ZMK_WHL_SHIFT                  (0U)
86513 /*! ZMK_WHL
86514  *  0b0..Write access is allowed.
86515  *  0b1..Write access is not allowed.
86516  */
86517 #define SNVS_LPLR_ZMK_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
86518 
86519 #define SNVS_LPLR_ZMK_RHL_MASK                   (0x2U)
86520 #define SNVS_LPLR_ZMK_RHL_SHIFT                  (1U)
86521 /*! ZMK_RHL
86522  *  0b0..Read access is allowed (only in software programming mode).
86523  *  0b1..Read access is not allowed.
86524  */
86525 #define SNVS_LPLR_ZMK_RHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
86526 
86527 #define SNVS_LPLR_SRTC_HL_MASK                   (0x4U)
86528 #define SNVS_LPLR_SRTC_HL_SHIFT                  (2U)
86529 /*! SRTC_HL
86530  *  0b0..Write access is allowed.
86531  *  0b1..Write access is not allowed.
86532  */
86533 #define SNVS_LPLR_SRTC_HL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
86534 
86535 #define SNVS_LPLR_LPCALB_HL_MASK                 (0x8U)
86536 #define SNVS_LPLR_LPCALB_HL_SHIFT                (3U)
86537 /*! LPCALB_HL
86538  *  0b0..Write access is allowed.
86539  *  0b1..Write access is not allowed.
86540  */
86541 #define SNVS_LPLR_LPCALB_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
86542 
86543 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
86544 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
86545 /*! MC_HL
86546  *  0b0..Write access (increment) is allowed.
86547  *  0b1..Write access (increment) is not allowed.
86548  */
86549 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
86550 
86551 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
86552 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
86553 /*! GPR_HL
86554  *  0b0..Write access is allowed.
86555  *  0b1..Write access is not allowed.
86556  */
86557 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
86558 
86559 #define SNVS_LPLR_LPSVCR_HL_MASK                 (0x40U)
86560 #define SNVS_LPLR_LPSVCR_HL_SHIFT                (6U)
86561 /*! LPSVCR_HL
86562  *  0b0..Write access is allowed.
86563  *  0b1..Write access is not allowed.
86564  */
86565 #define SNVS_LPLR_LPSVCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
86566 
86567 #define SNVS_LPLR_LPTGFCR_HL_MASK                (0x80U)
86568 #define SNVS_LPLR_LPTGFCR_HL_SHIFT               (7U)
86569 /*! LPTGFCR_HL
86570  *  0b0..Write access is allowed.
86571  *  0b1..Write access is not allowed.
86572  */
86573 #define SNVS_LPLR_LPTGFCR_HL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
86574 
86575 #define SNVS_LPLR_LPSECR_HL_MASK                 (0x100U)
86576 #define SNVS_LPLR_LPSECR_HL_SHIFT                (8U)
86577 /*! LPSECR_HL
86578  *  0b0..Write access is allowed.
86579  *  0b1..Write access is not allowed.
86580  */
86581 #define SNVS_LPLR_LPSECR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
86582 
86583 #define SNVS_LPLR_MKS_HL_MASK                    (0x200U)
86584 #define SNVS_LPLR_MKS_HL_SHIFT                   (9U)
86585 /*! MKS_HL
86586  *  0b0..Write access is allowed.
86587  *  0b1..Write access is not allowed.
86588  */
86589 #define SNVS_LPLR_MKS_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
86590 
86591 #define SNVS_LPLR_AT1_HL_MASK                    (0x1000000U)
86592 #define SNVS_LPLR_AT1_HL_SHIFT                   (24U)
86593 /*! AT1_HL
86594  *  0b0..Write access is allowed.
86595  *  0b1..Write access is not allowed.
86596  */
86597 #define SNVS_LPLR_AT1_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
86598 
86599 #define SNVS_LPLR_AT2_HL_MASK                    (0x2000000U)
86600 #define SNVS_LPLR_AT2_HL_SHIFT                   (25U)
86601 /*! AT2_HL
86602  *  0b0..Write access is allowed.
86603  *  0b1..Write access is not allowed.
86604  */
86605 #define SNVS_LPLR_AT2_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
86606 
86607 #define SNVS_LPLR_AT3_HL_MASK                    (0x4000000U)
86608 #define SNVS_LPLR_AT3_HL_SHIFT                   (26U)
86609 /*! AT3_HL
86610  *  0b0..Write access is allowed.
86611  *  0b1..Write access is not allowed.
86612  */
86613 #define SNVS_LPLR_AT3_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
86614 
86615 #define SNVS_LPLR_AT4_HL_MASK                    (0x8000000U)
86616 #define SNVS_LPLR_AT4_HL_SHIFT                   (27U)
86617 /*! AT4_HL
86618  *  0b0..Write access is allowed.
86619  *  0b1..Write access is not allowed.
86620  */
86621 #define SNVS_LPLR_AT4_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
86622 
86623 #define SNVS_LPLR_AT5_HL_MASK                    (0x10000000U)
86624 #define SNVS_LPLR_AT5_HL_SHIFT                   (28U)
86625 /*! AT5_HL
86626  *  0b0..Write access is allowed.
86627  *  0b1..Write access is not allowed.
86628  */
86629 #define SNVS_LPLR_AT5_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
86630 /*! @} */
86631 
86632 /*! @name LPCR - SNVS_LP Control Register */
86633 /*! @{ */
86634 
86635 #define SNVS_LPCR_SRTC_ENV_MASK                  (0x1U)
86636 #define SNVS_LPCR_SRTC_ENV_SHIFT                 (0U)
86637 /*! SRTC_ENV
86638  *  0b0..SRTC is disabled or invalid.
86639  *  0b1..SRTC is enabled and valid.
86640  */
86641 #define SNVS_LPCR_SRTC_ENV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
86642 
86643 #define SNVS_LPCR_LPTA_EN_MASK                   (0x2U)
86644 #define SNVS_LPCR_LPTA_EN_SHIFT                  (1U)
86645 /*! LPTA_EN
86646  *  0b0..LP time alarm interrupt is disabled.
86647  *  0b1..LP time alarm interrupt is enabled.
86648  */
86649 #define SNVS_LPCR_LPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
86650 
86651 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
86652 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
86653 /*! MC_ENV
86654  *  0b0..MC is disabled or invalid.
86655  *  0b1..MC is enabled and valid.
86656  */
86657 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
86658 
86659 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
86660 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
86661 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
86662 
86663 #define SNVS_LPCR_SRTC_INV_EN_MASK               (0x10U)
86664 #define SNVS_LPCR_SRTC_INV_EN_SHIFT              (4U)
86665 /*! SRTC_INV_EN
86666  *  0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)).
86667  *  0b1..SRTC is invalidated in the case of security violation.
86668  */
86669 #define SNVS_LPCR_SRTC_INV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
86670 
86671 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
86672 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
86673 /*! DP_EN
86674  *  0b0..Smart PMIC enabled.
86675  *  0b1..Dumb PMIC enabled.
86676  */
86677 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
86678 
86679 #define SNVS_LPCR_TOP_MASK                       (0x40U)
86680 #define SNVS_LPCR_TOP_SHIFT                      (6U)
86681 /*! TOP
86682  *  0b0..Leave system power on.
86683  *  0b1..Turn off system power.
86684  */
86685 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
86686 
86687 #define SNVS_LPCR_LVD_EN_MASK                    (0x80U)
86688 #define SNVS_LPCR_LVD_EN_SHIFT                   (7U)
86689 #define SNVS_LPCR_LVD_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
86690 
86691 #define SNVS_LPCR_LPCALB_EN_MASK                 (0x100U)
86692 #define SNVS_LPCR_LPCALB_EN_SHIFT                (8U)
86693 /*! LPCALB_EN
86694  *  0b0..SRTC Time calibration is disabled.
86695  *  0b1..SRTC Time calibration is enabled.
86696  */
86697 #define SNVS_LPCR_LPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
86698 
86699 #define SNVS_LPCR_LPCALB_VAL_MASK                (0x7C00U)
86700 #define SNVS_LPCR_LPCALB_VAL_SHIFT               (10U)
86701 /*! LPCALB_VAL
86702  *  0b00000..+0 counts per each 32768 ticks of the counter clock
86703  *  0b00001..+1 counts per each 32768 ticks of the counter clock
86704  *  0b00010..+2 counts per each 32768 ticks of the counter clock
86705  *  0b01111..+15 counts per each 32768 ticks of the counter clock
86706  *  0b10000..-16 counts per each 32768 ticks of the counter clock
86707  *  0b10001..-15 counts per each 32768 ticks of the counter clock
86708  *  0b11110..-2 counts per each 32768 ticks of the counter clock
86709  *  0b11111..-1 counts per each 32768 ticks of the counter clock
86710  */
86711 #define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
86712 
86713 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
86714 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
86715 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
86716 
86717 #define SNVS_LPCR_DEBOUNCE_MASK                  (0xC0000U)
86718 #define SNVS_LPCR_DEBOUNCE_SHIFT                 (18U)
86719 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
86720 
86721 #define SNVS_LPCR_ON_TIME_MASK                   (0x300000U)
86722 #define SNVS_LPCR_ON_TIME_SHIFT                  (20U)
86723 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
86724 
86725 #define SNVS_LPCR_PK_EN_MASK                     (0x400000U)
86726 #define SNVS_LPCR_PK_EN_SHIFT                    (22U)
86727 #define SNVS_LPCR_PK_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
86728 
86729 #define SNVS_LPCR_PK_OVERRIDE_MASK               (0x800000U)
86730 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              (23U)
86731 #define SNVS_LPCR_PK_OVERRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
86732 
86733 #define SNVS_LPCR_GPR_Z_DIS_MASK                 (0x1000000U)
86734 #define SNVS_LPCR_GPR_Z_DIS_SHIFT                (24U)
86735 #define SNVS_LPCR_GPR_Z_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
86736 /*! @} */
86737 
86738 /*! @name LPMKCR - SNVS_LP Master Key Control Register */
86739 /*! @{ */
86740 
86741 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          (0x3U)
86742 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         (0U)
86743 /*! MASTER_KEY_SEL
86744  *  0b0x..Select one time programmable master key.
86745  *  0b10..Select zeroizable master key when MKS_EN bit is set .
86746  *  0b11..Select combined master key when MKS_EN bit is set .
86747  */
86748 #define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
86749 
86750 #define SNVS_LPMKCR_ZMK_HWP_MASK                 (0x4U)
86751 #define SNVS_LPMKCR_ZMK_HWP_SHIFT                (2U)
86752 /*! ZMK_HWP
86753  *  0b0..ZMK is in the software programming mode.
86754  *  0b1..ZMK is in the hardware programming mode.
86755  */
86756 #define SNVS_LPMKCR_ZMK_HWP(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
86757 
86758 #define SNVS_LPMKCR_ZMK_VAL_MASK                 (0x8U)
86759 #define SNVS_LPMKCR_ZMK_VAL_SHIFT                (3U)
86760 /*! ZMK_VAL
86761  *  0b0..ZMK is not valid.
86762  *  0b1..ZMK is valid.
86763  */
86764 #define SNVS_LPMKCR_ZMK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
86765 
86766 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK              (0x10U)
86767 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             (4U)
86768 /*! ZMK_ECC_EN
86769  *  0b0..ZMK ECC check is disabled.
86770  *  0b1..ZMK ECC check is enabled.
86771  */
86772 #define SNVS_LPMKCR_ZMK_ECC_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
86773 
86774 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           (0xFF80U)
86775 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          (7U)
86776 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
86777 /*! @} */
86778 
86779 /*! @name LPSVCR - SNVS_LP Security Violation Control Register */
86780 /*! @{ */
86781 
86782 #define SNVS_LPSVCR_CAAM_EN_MASK                 (0x1U)
86783 #define SNVS_LPSVCR_CAAM_EN_SHIFT                (0U)
86784 /*! CAAM_EN
86785  *  0b0..CAAM Security Violation is disabled in the LP domain.
86786  *  0b1..CAAM Security Violation is enabled in the LP domain.
86787  */
86788 #define SNVS_LPSVCR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
86789 
86790 #define SNVS_LPSVCR_JTAGC_EN_MASK                (0x2U)
86791 #define SNVS_LPSVCR_JTAGC_EN_SHIFT               (1U)
86792 /*! JTAGC_EN
86793  *  0b0..JTAG Active is disabled in the LP domain.
86794  *  0b1..JTAG Active is enabled in the LP domain.
86795  */
86796 #define SNVS_LPSVCR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
86797 
86798 #define SNVS_LPSVCR_WDOG2_EN_MASK                (0x4U)
86799 #define SNVS_LPSVCR_WDOG2_EN_SHIFT               (2U)
86800 /*! WDOG2_EN
86801  *  0b0..Watchdog 2 Reset is disabled in the LP domain.
86802  *  0b1..Watchdog 2 Reset is enabled in the LP domain.
86803  */
86804 #define SNVS_LPSVCR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
86805 
86806 #define SNVS_LPSVCR_SRC_EN_MASK                  (0x10U)
86807 #define SNVS_LPSVCR_SRC_EN_SHIFT                 (4U)
86808 /*! SRC_EN
86809  *  0b0..Internal Boot is disabled in the LP domain.
86810  *  0b1..Internal Boot is enabled in the LP domain.
86811  */
86812 #define SNVS_LPSVCR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
86813 
86814 #define SNVS_LPSVCR_OCOTP_EN_MASK                (0x20U)
86815 #define SNVS_LPSVCR_OCOTP_EN_SHIFT               (5U)
86816 /*! OCOTP_EN
86817  *  0b0..OCOTP attack error is disabled in the LP domain.
86818  *  0b1..OCOTP attack error is enabled in the LP domain.
86819  */
86820 #define SNVS_LPSVCR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
86821 /*! @} */
86822 
86823 /*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */
86824 /*! @{ */
86825 
86826 #define SNVS_LPTGFCR_WMTGF_MASK                  (0x1FU)
86827 #define SNVS_LPTGFCR_WMTGF_SHIFT                 (0U)
86828 #define SNVS_LPTGFCR_WMTGF(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
86829 
86830 #define SNVS_LPTGFCR_WMTGF_EN_MASK               (0x80U)
86831 #define SNVS_LPTGFCR_WMTGF_EN_SHIFT              (7U)
86832 /*! WMTGF_EN
86833  *  0b0..Wire-mesh tamper glitch filter is bypassed.
86834  *  0b1..Wire-mesh tamper glitch filter is enabled.
86835  */
86836 #define SNVS_LPTGFCR_WMTGF_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
86837 
86838 #define SNVS_LPTGFCR_ETGF1_MASK                  (0x7F0000U)
86839 #define SNVS_LPTGFCR_ETGF1_SHIFT                 (16U)
86840 #define SNVS_LPTGFCR_ETGF1(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
86841 
86842 #define SNVS_LPTGFCR_ETGF1_EN_MASK               (0x800000U)
86843 #define SNVS_LPTGFCR_ETGF1_EN_SHIFT              (23U)
86844 /*! ETGF1_EN
86845  *  0b0..External tamper glitch filter 1 is bypassed.
86846  *  0b1..External tamper glitch filter 1 is enabled.
86847  */
86848 #define SNVS_LPTGFCR_ETGF1_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
86849 
86850 #define SNVS_LPTGFCR_ETGF2_MASK                  (0x7F000000U)
86851 #define SNVS_LPTGFCR_ETGF2_SHIFT                 (24U)
86852 #define SNVS_LPTGFCR_ETGF2(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
86853 
86854 #define SNVS_LPTGFCR_ETGF2_EN_MASK               (0x80000000U)
86855 #define SNVS_LPTGFCR_ETGF2_EN_SHIFT              (31U)
86856 /*! ETGF2_EN
86857  *  0b0..External tamper glitch filter 2 is bypassed.
86858  *  0b1..External tamper glitch filter 2 is enabled.
86859  */
86860 #define SNVS_LPTGFCR_ETGF2_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
86861 /*! @} */
86862 
86863 /*! @name LPTDCR - SNVS_LP Tamper Detect Configuration Register */
86864 /*! @{ */
86865 
86866 #define SNVS_LPTDCR_SRTCR_EN_MASK                (0x2U)
86867 #define SNVS_LPTDCR_SRTCR_EN_SHIFT               (1U)
86868 /*! SRTCR_EN
86869  *  0b0..SRTC rollover is disabled.
86870  *  0b1..SRTC rollover is enabled.
86871  */
86872 #define SNVS_LPTDCR_SRTCR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
86873 
86874 #define SNVS_LPTDCR_MCR_EN_MASK                  (0x4U)
86875 #define SNVS_LPTDCR_MCR_EN_SHIFT                 (2U)
86876 /*! MCR_EN
86877  *  0b0..MC rollover is disabled.
86878  *  0b1..MC rollover is enabled.
86879  */
86880 #define SNVS_LPTDCR_MCR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
86881 
86882 #define SNVS_LPTDCR_CT_EN_MASK                   (0x10U)
86883 #define SNVS_LPTDCR_CT_EN_SHIFT                  (4U)
86884 /*! CT_EN
86885  *  0b0..Clock tamper is disabled.
86886  *  0b1..Clock tamper is enabled.
86887  */
86888 #define SNVS_LPTDCR_CT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
86889 
86890 #define SNVS_LPTDCR_TT_EN_MASK                   (0x20U)
86891 #define SNVS_LPTDCR_TT_EN_SHIFT                  (5U)
86892 /*! TT_EN
86893  *  0b0..Temperature tamper is disabled.
86894  *  0b1..Temperature tamper is enabled.
86895  */
86896 #define SNVS_LPTDCR_TT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
86897 
86898 #define SNVS_LPTDCR_VT_EN_MASK                   (0x40U)
86899 #define SNVS_LPTDCR_VT_EN_SHIFT                  (6U)
86900 /*! VT_EN
86901  *  0b0..Voltage tamper is disabled.
86902  *  0b1..Voltage tamper is enabled.
86903  */
86904 #define SNVS_LPTDCR_VT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
86905 
86906 #define SNVS_LPTDCR_WMT1_EN_MASK                 (0x80U)
86907 #define SNVS_LPTDCR_WMT1_EN_SHIFT                (7U)
86908 /*! WMT1_EN
86909  *  0b0..Wire-mesh tamper 1 is disabled.
86910  *  0b1..Wire-mesh tamper 1 is enabled.
86911  */
86912 #define SNVS_LPTDCR_WMT1_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
86913 
86914 #define SNVS_LPTDCR_WMT2_EN_MASK                 (0x100U)
86915 #define SNVS_LPTDCR_WMT2_EN_SHIFT                (8U)
86916 /*! WMT2_EN
86917  *  0b0..Wire-mesh tamper 2 is disabled.
86918  *  0b1..Wire-mesh tamper 2 is enabled.
86919  */
86920 #define SNVS_LPTDCR_WMT2_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
86921 
86922 #define SNVS_LPTDCR_ET1_EN_MASK                  (0x200U)
86923 #define SNVS_LPTDCR_ET1_EN_SHIFT                 (9U)
86924 /*! ET1_EN
86925  *  0b0..External tamper 1 is disabled.
86926  *  0b1..External tamper 1 is enabled.
86927  */
86928 #define SNVS_LPTDCR_ET1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
86929 
86930 #define SNVS_LPTDCR_ET2_EN_MASK                  (0x400U)
86931 #define SNVS_LPTDCR_ET2_EN_SHIFT                 (10U)
86932 /*! ET2_EN
86933  *  0b0..External tamper 2 is disabled.
86934  *  0b1..External tamper 2 is enabled.
86935  */
86936 #define SNVS_LPTDCR_ET2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
86937 
86938 #define SNVS_LPTDCR_ET1P_MASK                    (0x800U)
86939 #define SNVS_LPTDCR_ET1P_SHIFT                   (11U)
86940 /*! ET1P
86941  *  0b0..External tamper 1 is active low.
86942  *  0b1..External tamper 1 is active high.
86943  */
86944 #define SNVS_LPTDCR_ET1P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
86945 
86946 #define SNVS_LPTDCR_ET2P_MASK                    (0x1000U)
86947 #define SNVS_LPTDCR_ET2P_SHIFT                   (12U)
86948 /*! ET2P
86949  *  0b0..External tamper 2 is active low.
86950  *  0b1..External tamper 2 is active high.
86951  */
86952 #define SNVS_LPTDCR_ET2P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
86953 
86954 #define SNVS_LPTDCR_PFD_OBSERV_MASK              (0x4000U)
86955 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT             (14U)
86956 #define SNVS_LPTDCR_PFD_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
86957 
86958 #define SNVS_LPTDCR_POR_OBSERV_MASK              (0x8000U)
86959 #define SNVS_LPTDCR_POR_OBSERV_SHIFT             (15U)
86960 #define SNVS_LPTDCR_POR_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
86961 
86962 #define SNVS_LPTDCR_LTDC_MASK                    (0x70000U)
86963 #define SNVS_LPTDCR_LTDC_SHIFT                   (16U)
86964 #define SNVS_LPTDCR_LTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
86965 
86966 #define SNVS_LPTDCR_HTDC_MASK                    (0x700000U)
86967 #define SNVS_LPTDCR_HTDC_SHIFT                   (20U)
86968 #define SNVS_LPTDCR_HTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
86969 
86970 #define SNVS_LPTDCR_VRC_MASK                     (0x7000000U)
86971 #define SNVS_LPTDCR_VRC_SHIFT                    (24U)
86972 #define SNVS_LPTDCR_VRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
86973 
86974 #define SNVS_LPTDCR_OSCB_MASK                    (0x10000000U)
86975 #define SNVS_LPTDCR_OSCB_SHIFT                   (28U)
86976 /*! OSCB
86977  *  0b0..Normal SRTC clock oscillator not bypassed.
86978  *  0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
86979  */
86980 #define SNVS_LPTDCR_OSCB(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
86981 /*! @} */
86982 
86983 /*! @name LPSR - SNVS_LP Status Register */
86984 /*! @{ */
86985 
86986 #define SNVS_LPSR_LPTA_MASK                      (0x1U)
86987 #define SNVS_LPSR_LPTA_SHIFT                     (0U)
86988 /*! LPTA
86989  *  0b0..No time alarm interrupt occurred.
86990  *  0b1..A time alarm interrupt occurred.
86991  */
86992 #define SNVS_LPSR_LPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
86993 
86994 #define SNVS_LPSR_SRTCR_MASK                     (0x2U)
86995 #define SNVS_LPSR_SRTCR_SHIFT                    (1U)
86996 /*! SRTCR
86997  *  0b0..SRTC has not reached its maximum value.
86998  *  0b1..SRTC has reached its maximum value.
86999  */
87000 #define SNVS_LPSR_SRTCR(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
87001 
87002 #define SNVS_LPSR_MCR_MASK                       (0x4U)
87003 #define SNVS_LPSR_MCR_SHIFT                      (2U)
87004 /*! MCR
87005  *  0b0..MC has not reached its maximum value.
87006  *  0b1..MC has reached its maximum value.
87007  */
87008 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
87009 
87010 #define SNVS_LPSR_LVD_MASK                       (0x8U)
87011 #define SNVS_LPSR_LVD_SHIFT                      (3U)
87012 /*! LVD
87013  *  0b0..No low voltage event detected.
87014  *  0b1..Low voltage event is detected.
87015  */
87016 #define SNVS_LPSR_LVD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
87017 
87018 #define SNVS_LPSR_CTD_MASK                       (0x10U)
87019 #define SNVS_LPSR_CTD_SHIFT                      (4U)
87020 /*! CTD
87021  *  0b0..No clock tamper.
87022  *  0b1..Clock tamper is detected.
87023  */
87024 #define SNVS_LPSR_CTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
87025 
87026 #define SNVS_LPSR_TTD_MASK                       (0x20U)
87027 #define SNVS_LPSR_TTD_SHIFT                      (5U)
87028 /*! TTD
87029  *  0b0..No temperature tamper.
87030  *  0b1..Temperature tamper is detected.
87031  */
87032 #define SNVS_LPSR_TTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
87033 
87034 #define SNVS_LPSR_VTD_MASK                       (0x40U)
87035 #define SNVS_LPSR_VTD_SHIFT                      (6U)
87036 /*! VTD
87037  *  0b0..Voltage tampering not detected.
87038  *  0b1..Voltage tampering detected.
87039  */
87040 #define SNVS_LPSR_VTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
87041 
87042 #define SNVS_LPSR_WMT1D_MASK                     (0x80U)
87043 #define SNVS_LPSR_WMT1D_SHIFT                    (7U)
87044 /*! WMT1D
87045  *  0b0..Wire-mesh tampering 1 not detected.
87046  *  0b1..Wire-mesh tampering 1 detected.
87047  */
87048 #define SNVS_LPSR_WMT1D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
87049 
87050 #define SNVS_LPSR_WMT2D_MASK                     (0x100U)
87051 #define SNVS_LPSR_WMT2D_SHIFT                    (8U)
87052 /*! WMT2D
87053  *  0b0..Wire-mesh tampering 2 not detected.
87054  *  0b1..Wire-mesh tampering 2 detected.
87055  */
87056 #define SNVS_LPSR_WMT2D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
87057 
87058 #define SNVS_LPSR_ET1D_MASK                      (0x200U)
87059 #define SNVS_LPSR_ET1D_SHIFT                     (9U)
87060 /*! ET1D
87061  *  0b0..External tampering 1 not detected.
87062  *  0b1..External tampering 1 detected.
87063  */
87064 #define SNVS_LPSR_ET1D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
87065 
87066 #define SNVS_LPSR_ET2D_MASK                      (0x400U)
87067 #define SNVS_LPSR_ET2D_SHIFT                     (10U)
87068 /*! ET2D
87069  *  0b0..External tampering 2 not detected.
87070  *  0b1..External tampering 2 detected.
87071  */
87072 #define SNVS_LPSR_ET2D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
87073 
87074 #define SNVS_LPSR_ESVD_MASK                      (0x10000U)
87075 #define SNVS_LPSR_ESVD_SHIFT                     (16U)
87076 /*! ESVD
87077  *  0b0..No external security violation.
87078  *  0b1..External security violation is detected.
87079  */
87080 #define SNVS_LPSR_ESVD(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
87081 
87082 #define SNVS_LPSR_EO_MASK                        (0x20000U)
87083 #define SNVS_LPSR_EO_SHIFT                       (17U)
87084 /*! EO
87085  *  0b0..Emergency off was not detected.
87086  *  0b1..Emergency off was detected.
87087  */
87088 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
87089 
87090 #define SNVS_LPSR_SPOF_MASK                      (0x40000U)
87091 #define SNVS_LPSR_SPOF_SHIFT                     (18U)
87092 /*! SPOF
87093  *  0b0..Set Power Off was not detected.
87094  *  0b1..Set Power Off was detected.
87095  */
87096 #define SNVS_LPSR_SPOF(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
87097 
87098 #define SNVS_LPSR_LPNS_MASK                      (0x40000000U)
87099 #define SNVS_LPSR_LPNS_SHIFT                     (30U)
87100 /*! LPNS
87101  *  0b0..LP section was not programmed in the non-secure state.
87102  *  0b1..LP section was programmed in the non-secure state.
87103  */
87104 #define SNVS_LPSR_LPNS(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
87105 
87106 #define SNVS_LPSR_LPS_MASK                       (0x80000000U)
87107 #define SNVS_LPSR_LPS_SHIFT                      (31U)
87108 /*! LPS
87109  *  0b0..LP section was not programmed in secure or trusted state.
87110  *  0b1..LP section was programmed in secure or trusted state.
87111  */
87112 #define SNVS_LPSR_LPS(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
87113 /*! @} */
87114 
87115 /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
87116 /*! @{ */
87117 
87118 #define SNVS_LPSRTCMR_SRTC_MASK                  (0x7FFFU)
87119 #define SNVS_LPSRTCMR_SRTC_SHIFT                 (0U)
87120 #define SNVS_LPSRTCMR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
87121 /*! @} */
87122 
87123 /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
87124 /*! @{ */
87125 
87126 #define SNVS_LPSRTCLR_SRTC_MASK                  (0xFFFFFFFFU)
87127 #define SNVS_LPSRTCLR_SRTC_SHIFT                 (0U)
87128 #define SNVS_LPSRTCLR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
87129 /*! @} */
87130 
87131 /*! @name LPTAR - SNVS_LP Time Alarm Register */
87132 /*! @{ */
87133 
87134 #define SNVS_LPTAR_LPTA_MASK                     (0xFFFFFFFFU)
87135 #define SNVS_LPTAR_LPTA_SHIFT                    (0U)
87136 #define SNVS_LPTAR_LPTA(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
87137 /*! @} */
87138 
87139 /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
87140 /*! @{ */
87141 
87142 #define SNVS_LPSMCMR_MON_COUNTER_MASK            (0xFFFFU)
87143 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           (0U)
87144 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
87145 
87146 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            (0xFFFF0000U)
87147 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           (16U)
87148 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
87149 /*! @} */
87150 
87151 /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
87152 /*! @{ */
87153 
87154 #define SNVS_LPSMCLR_MON_COUNTER_MASK            (0xFFFFFFFFU)
87155 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           (0U)
87156 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
87157 /*! @} */
87158 
87159 /*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */
87160 /*! @{ */
87161 
87162 #define SNVS_LPLVDR_LVD_MASK                     (0xFFFFFFFFU)
87163 #define SNVS_LPLVDR_LVD_SHIFT                    (0U)
87164 #define SNVS_LPLVDR_LVD(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
87165 /*! @} */
87166 
87167 /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
87168 /*! @{ */
87169 
87170 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK        (0xFFFFFFFFU)
87171 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT       (0U)
87172 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
87173 /*! @} */
87174 
87175 /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
87176 /*! @{ */
87177 
87178 #define SNVS_LPZMKR_ZMK_MASK                     (0xFFFFFFFFU)
87179 #define SNVS_LPZMKR_ZMK_SHIFT                    (0U)
87180 #define SNVS_LPZMKR_ZMK(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
87181 /*! @} */
87182 
87183 /* The count of SNVS_LPZMKR */
87184 #define SNVS_LPZMKR_COUNT                        (8U)
87185 
87186 /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
87187 /*! @{ */
87188 
87189 #define SNVS_LPGPR_ALIAS_GPR_MASK                (0xFFFFFFFFU)
87190 #define SNVS_LPGPR_ALIAS_GPR_SHIFT               (0U)
87191 #define SNVS_LPGPR_ALIAS_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
87192 /*! @} */
87193 
87194 /* The count of SNVS_LPGPR_ALIAS */
87195 #define SNVS_LPGPR_ALIAS_COUNT                   (4U)
87196 
87197 /*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */
87198 /*! @{ */
87199 
87200 #define SNVS_LPTDC2R_ET3_EN_MASK                 (0x1U)
87201 #define SNVS_LPTDC2R_ET3_EN_SHIFT                (0U)
87202 /*! ET3_EN
87203  *  0b0..External tamper 3 is disabled.
87204  *  0b1..External tamper 3 is enabled.
87205  */
87206 #define SNVS_LPTDC2R_ET3_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
87207 
87208 #define SNVS_LPTDC2R_ET4_EN_MASK                 (0x2U)
87209 #define SNVS_LPTDC2R_ET4_EN_SHIFT                (1U)
87210 /*! ET4_EN
87211  *  0b0..External tamper 4 is disabled.
87212  *  0b1..External tamper 4 is enabled.
87213  */
87214 #define SNVS_LPTDC2R_ET4_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
87215 
87216 #define SNVS_LPTDC2R_ET5_EN_MASK                 (0x4U)
87217 #define SNVS_LPTDC2R_ET5_EN_SHIFT                (2U)
87218 /*! ET5_EN
87219  *  0b0..External tamper 5 is disabled.
87220  *  0b1..External tamper 5 is enabled.
87221  */
87222 #define SNVS_LPTDC2R_ET5_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
87223 
87224 #define SNVS_LPTDC2R_ET6_EN_MASK                 (0x8U)
87225 #define SNVS_LPTDC2R_ET6_EN_SHIFT                (3U)
87226 /*! ET6_EN
87227  *  0b0..External tamper 6 is disabled.
87228  *  0b1..External tamper 6 is enabled.
87229  */
87230 #define SNVS_LPTDC2R_ET6_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
87231 
87232 #define SNVS_LPTDC2R_ET7_EN_MASK                 (0x10U)
87233 #define SNVS_LPTDC2R_ET7_EN_SHIFT                (4U)
87234 /*! ET7_EN
87235  *  0b0..External tamper 7 is disabled.
87236  *  0b1..External tamper 7 is enabled.
87237  */
87238 #define SNVS_LPTDC2R_ET7_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
87239 
87240 #define SNVS_LPTDC2R_ET8_EN_MASK                 (0x20U)
87241 #define SNVS_LPTDC2R_ET8_EN_SHIFT                (5U)
87242 /*! ET8_EN
87243  *  0b0..External tamper 8 is disabled.
87244  *  0b1..External tamper 8 is enabled.
87245  */
87246 #define SNVS_LPTDC2R_ET8_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
87247 
87248 #define SNVS_LPTDC2R_ET9_EN_MASK                 (0x40U)
87249 #define SNVS_LPTDC2R_ET9_EN_SHIFT                (6U)
87250 /*! ET9_EN
87251  *  0b0..External tamper 9 is disabled.
87252  *  0b1..External tamper 9 is enabled.
87253  */
87254 #define SNVS_LPTDC2R_ET9_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
87255 
87256 #define SNVS_LPTDC2R_ET10_EN_MASK                (0x80U)
87257 #define SNVS_LPTDC2R_ET10_EN_SHIFT               (7U)
87258 /*! ET10_EN
87259  *  0b0..External tamper 10 is disabled.
87260  *  0b1..External tamper 10 is enabled.
87261  */
87262 #define SNVS_LPTDC2R_ET10_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
87263 
87264 #define SNVS_LPTDC2R_ET3P_MASK                   (0x10000U)
87265 #define SNVS_LPTDC2R_ET3P_SHIFT                  (16U)
87266 /*! ET3P
87267  *  0b0..External tamper 3 active low.
87268  *  0b1..External tamper 3 active high.
87269  */
87270 #define SNVS_LPTDC2R_ET3P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
87271 
87272 #define SNVS_LPTDC2R_ET4P_MASK                   (0x20000U)
87273 #define SNVS_LPTDC2R_ET4P_SHIFT                  (17U)
87274 /*! ET4P
87275  *  0b0..External tamper 4 is active low.
87276  *  0b1..External tamper 4 is active high.
87277  */
87278 #define SNVS_LPTDC2R_ET4P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
87279 
87280 #define SNVS_LPTDC2R_ET5P_MASK                   (0x40000U)
87281 #define SNVS_LPTDC2R_ET5P_SHIFT                  (18U)
87282 /*! ET5P
87283  *  0b0..External tamper 5 is active low.
87284  *  0b1..External tamper 5 is active high.
87285  */
87286 #define SNVS_LPTDC2R_ET5P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
87287 
87288 #define SNVS_LPTDC2R_ET6P_MASK                   (0x80000U)
87289 #define SNVS_LPTDC2R_ET6P_SHIFT                  (19U)
87290 /*! ET6P
87291  *  0b0..External tamper 6 is active low.
87292  *  0b1..External tamper 6 is active high.
87293  */
87294 #define SNVS_LPTDC2R_ET6P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
87295 
87296 #define SNVS_LPTDC2R_ET7P_MASK                   (0x100000U)
87297 #define SNVS_LPTDC2R_ET7P_SHIFT                  (20U)
87298 /*! ET7P
87299  *  0b0..External tamper 7 is active low.
87300  *  0b1..External tamper 7 is active high.
87301  */
87302 #define SNVS_LPTDC2R_ET7P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
87303 
87304 #define SNVS_LPTDC2R_ET8P_MASK                   (0x200000U)
87305 #define SNVS_LPTDC2R_ET8P_SHIFT                  (21U)
87306 /*! ET8P
87307  *  0b0..External tamper 8 is active low.
87308  *  0b1..External tamper 8 is active high.
87309  */
87310 #define SNVS_LPTDC2R_ET8P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
87311 
87312 #define SNVS_LPTDC2R_ET9P_MASK                   (0x400000U)
87313 #define SNVS_LPTDC2R_ET9P_SHIFT                  (22U)
87314 /*! ET9P
87315  *  0b0..External tamper 9 is active low.
87316  *  0b1..External tamper 9 is active high.
87317  */
87318 #define SNVS_LPTDC2R_ET9P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
87319 
87320 #define SNVS_LPTDC2R_ET10P_MASK                  (0x800000U)
87321 #define SNVS_LPTDC2R_ET10P_SHIFT                 (23U)
87322 /*! ET10P
87323  *  0b0..External tamper 10 is active low.
87324  *  0b1..External tamper 10 is active high.
87325  */
87326 #define SNVS_LPTDC2R_ET10P(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
87327 /*! @} */
87328 
87329 /*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */
87330 /*! @{ */
87331 
87332 #define SNVS_LPTDSR_ET3D_MASK                    (0x1U)
87333 #define SNVS_LPTDSR_ET3D_SHIFT                   (0U)
87334 /*! ET3D
87335  *  0b0..External tamper 3 is not detected.
87336  *  0b1..External tamper 3 is detected.
87337  */
87338 #define SNVS_LPTDSR_ET3D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
87339 
87340 #define SNVS_LPTDSR_ET4D_MASK                    (0x2U)
87341 #define SNVS_LPTDSR_ET4D_SHIFT                   (1U)
87342 /*! ET4D
87343  *  0b0..External tamper 4 is not detected.
87344  *  0b1..External tamper 4 is detected.
87345  */
87346 #define SNVS_LPTDSR_ET4D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
87347 
87348 #define SNVS_LPTDSR_ET5D_MASK                    (0x4U)
87349 #define SNVS_LPTDSR_ET5D_SHIFT                   (2U)
87350 /*! ET5D
87351  *  0b0..External tamper 5 is not detected.
87352  *  0b1..External tamper 5 is detected.
87353  */
87354 #define SNVS_LPTDSR_ET5D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
87355 
87356 #define SNVS_LPTDSR_ET6D_MASK                    (0x8U)
87357 #define SNVS_LPTDSR_ET6D_SHIFT                   (3U)
87358 /*! ET6D
87359  *  0b0..External tamper 6 is not detected.
87360  *  0b1..External tamper 6 is detected.
87361  */
87362 #define SNVS_LPTDSR_ET6D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
87363 
87364 #define SNVS_LPTDSR_ET7D_MASK                    (0x10U)
87365 #define SNVS_LPTDSR_ET7D_SHIFT                   (4U)
87366 /*! ET7D
87367  *  0b0..External tamper 7 is not detected.
87368  *  0b1..External tamper 7 is detected.
87369  */
87370 #define SNVS_LPTDSR_ET7D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
87371 
87372 #define SNVS_LPTDSR_ET8D_MASK                    (0x20U)
87373 #define SNVS_LPTDSR_ET8D_SHIFT                   (5U)
87374 /*! ET8D
87375  *  0b0..External tamper 8 is not detected.
87376  *  0b1..External tamper 8 is detected.
87377  */
87378 #define SNVS_LPTDSR_ET8D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
87379 
87380 #define SNVS_LPTDSR_ET9D_MASK                    (0x40U)
87381 #define SNVS_LPTDSR_ET9D_SHIFT                   (6U)
87382 /*! ET9D
87383  *  0b0..External tamper 9 is not detected.
87384  *  0b1..External tamper 9 is detected.
87385  */
87386 #define SNVS_LPTDSR_ET9D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
87387 
87388 #define SNVS_LPTDSR_ET10D_MASK                   (0x80U)
87389 #define SNVS_LPTDSR_ET10D_SHIFT                  (7U)
87390 /*! ET10D
87391  *  0b0..External tamper 10 is not detected.
87392  *  0b1..External tamper 10 is detected.
87393  */
87394 #define SNVS_LPTDSR_ET10D(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
87395 /*! @} */
87396 
87397 /*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */
87398 /*! @{ */
87399 
87400 #define SNVS_LPTGF1CR_ETGF3_MASK                 (0x7FU)
87401 #define SNVS_LPTGF1CR_ETGF3_SHIFT                (0U)
87402 #define SNVS_LPTGF1CR_ETGF3(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
87403 
87404 #define SNVS_LPTGF1CR_ETGF3_EN_MASK              (0x80U)
87405 #define SNVS_LPTGF1CR_ETGF3_EN_SHIFT             (7U)
87406 /*! ETGF3_EN
87407  *  0b0..External tamper glitch filter 3 is bypassed.
87408  *  0b1..External tamper glitch filter 3 is enabled.
87409  */
87410 #define SNVS_LPTGF1CR_ETGF3_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
87411 
87412 #define SNVS_LPTGF1CR_ETGF4_MASK                 (0x7F00U)
87413 #define SNVS_LPTGF1CR_ETGF4_SHIFT                (8U)
87414 #define SNVS_LPTGF1CR_ETGF4(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
87415 
87416 #define SNVS_LPTGF1CR_ETGF4_EN_MASK              (0x8000U)
87417 #define SNVS_LPTGF1CR_ETGF4_EN_SHIFT             (15U)
87418 /*! ETGF4_EN
87419  *  0b0..External tamper glitch filter 4 is bypassed.
87420  *  0b1..External tamper glitch filter 4 is enabled.
87421  */
87422 #define SNVS_LPTGF1CR_ETGF4_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
87423 
87424 #define SNVS_LPTGF1CR_ETGF5_MASK                 (0x7F0000U)
87425 #define SNVS_LPTGF1CR_ETGF5_SHIFT                (16U)
87426 #define SNVS_LPTGF1CR_ETGF5(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
87427 
87428 #define SNVS_LPTGF1CR_ETGF5_EN_MASK              (0x800000U)
87429 #define SNVS_LPTGF1CR_ETGF5_EN_SHIFT             (23U)
87430 /*! ETGF5_EN
87431  *  0b0..External tamper glitch filter 5 is bypassed.
87432  *  0b1..External tamper glitch filter 5 is enabled.
87433  */
87434 #define SNVS_LPTGF1CR_ETGF5_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
87435 
87436 #define SNVS_LPTGF1CR_ETGF6_MASK                 (0x7F000000U)
87437 #define SNVS_LPTGF1CR_ETGF6_SHIFT                (24U)
87438 #define SNVS_LPTGF1CR_ETGF6(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
87439 
87440 #define SNVS_LPTGF1CR_ETGF6_EN_MASK              (0x80000000U)
87441 #define SNVS_LPTGF1CR_ETGF6_EN_SHIFT             (31U)
87442 /*! ETGF6_EN
87443  *  0b0..External tamper glitch filter 6 is bypassed.
87444  *  0b1..External tamper glitch filter 6 is enabled.
87445  */
87446 #define SNVS_LPTGF1CR_ETGF6_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
87447 /*! @} */
87448 
87449 /*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */
87450 /*! @{ */
87451 
87452 #define SNVS_LPTGF2CR_ETGF7_MASK                 (0x7FU)
87453 #define SNVS_LPTGF2CR_ETGF7_SHIFT                (0U)
87454 #define SNVS_LPTGF2CR_ETGF7(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
87455 
87456 #define SNVS_LPTGF2CR_ETGF7_EN_MASK              (0x80U)
87457 #define SNVS_LPTGF2CR_ETGF7_EN_SHIFT             (7U)
87458 /*! ETGF7_EN
87459  *  0b0..External tamper glitch filter 7 is bypassed.
87460  *  0b1..External tamper glitch filter 7 is enabled.
87461  */
87462 #define SNVS_LPTGF2CR_ETGF7_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
87463 
87464 #define SNVS_LPTGF2CR_ETGF8_MASK                 (0x7F00U)
87465 #define SNVS_LPTGF2CR_ETGF8_SHIFT                (8U)
87466 #define SNVS_LPTGF2CR_ETGF8(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
87467 
87468 #define SNVS_LPTGF2CR_ETGF8_EN_MASK              (0x8000U)
87469 #define SNVS_LPTGF2CR_ETGF8_EN_SHIFT             (15U)
87470 /*! ETGF8_EN
87471  *  0b0..External tamper glitch filter 8 is bypassed.
87472  *  0b1..External tamper glitch filter 8 is enabled.
87473  */
87474 #define SNVS_LPTGF2CR_ETGF8_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
87475 
87476 #define SNVS_LPTGF2CR_ETGF9_MASK                 (0x7F0000U)
87477 #define SNVS_LPTGF2CR_ETGF9_SHIFT                (16U)
87478 #define SNVS_LPTGF2CR_ETGF9(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
87479 
87480 #define SNVS_LPTGF2CR_ETGF9_EN_MASK              (0x800000U)
87481 #define SNVS_LPTGF2CR_ETGF9_EN_SHIFT             (23U)
87482 /*! ETGF9_EN
87483  *  0b0..External tamper glitch filter 9 is bypassed.
87484  *  0b1..External tamper glitch filter 9 is enabled.
87485  */
87486 #define SNVS_LPTGF2CR_ETGF9_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
87487 
87488 #define SNVS_LPTGF2CR_ETGF10_MASK                (0x7F000000U)
87489 #define SNVS_LPTGF2CR_ETGF10_SHIFT               (24U)
87490 #define SNVS_LPTGF2CR_ETGF10(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
87491 
87492 #define SNVS_LPTGF2CR_ETGF10_EN_MASK             (0x80000000U)
87493 #define SNVS_LPTGF2CR_ETGF10_EN_SHIFT            (31U)
87494 /*! ETGF10_EN
87495  *  0b0..External tamper glitch filter 10 is bypassed.
87496  *  0b1..External tamper glitch filter 10 is enabled.
87497  */
87498 #define SNVS_LPTGF2CR_ETGF10_EN(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
87499 /*! @} */
87500 
87501 /*! @name LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register */
87502 /*! @{ */
87503 
87504 #define SNVS_LPATCR_Seed_MASK                    (0xFFFFU)
87505 #define SNVS_LPATCR_Seed_SHIFT                   (0U)
87506 #define SNVS_LPATCR_Seed(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
87507 
87508 #define SNVS_LPATCR_Polynomial_MASK              (0xFFFF0000U)
87509 #define SNVS_LPATCR_Polynomial_SHIFT             (16U)
87510 #define SNVS_LPATCR_Polynomial(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
87511 /*! @} */
87512 
87513 /* The count of SNVS_LPATCR */
87514 #define SNVS_LPATCR_COUNT                        (5U)
87515 
87516 /*! @name LPATCTLR - SNVS_LP Active Tamper Control Register */
87517 /*! @{ */
87518 
87519 #define SNVS_LPATCTLR_AT1_EN_MASK                (0x1U)
87520 #define SNVS_LPATCTLR_AT1_EN_SHIFT               (0U)
87521 /*! AT1_EN
87522  *  0b0..Active Tamper 1 is disabled.
87523  *  0b1..Active Tamper 1 is enabled.
87524  */
87525 #define SNVS_LPATCTLR_AT1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
87526 
87527 #define SNVS_LPATCTLR_AT2_EN_MASK                (0x2U)
87528 #define SNVS_LPATCTLR_AT2_EN_SHIFT               (1U)
87529 /*! AT2_EN
87530  *  0b0..Active Tamper 2 is disabled.
87531  *  0b1..Active Tamper 2 is enabled.
87532  */
87533 #define SNVS_LPATCTLR_AT2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
87534 
87535 #define SNVS_LPATCTLR_AT3_EN_MASK                (0x4U)
87536 #define SNVS_LPATCTLR_AT3_EN_SHIFT               (2U)
87537 /*! AT3_EN
87538  *  0b0..Active Tamper 3 is disabled.
87539  *  0b1..Active Tamper 3 is enabled.
87540  */
87541 #define SNVS_LPATCTLR_AT3_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
87542 
87543 #define SNVS_LPATCTLR_AT4_EN_MASK                (0x8U)
87544 #define SNVS_LPATCTLR_AT4_EN_SHIFT               (3U)
87545 /*! AT4_EN
87546  *  0b0..Active Tamper 4 is disabled.
87547  *  0b1..Active Tamper 4 is enabled.
87548  */
87549 #define SNVS_LPATCTLR_AT4_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
87550 
87551 #define SNVS_LPATCTLR_AT5_EN_MASK                (0x10U)
87552 #define SNVS_LPATCTLR_AT5_EN_SHIFT               (4U)
87553 /*! AT5_EN
87554  *  0b0..Active Tamper 5 is disabled.
87555  *  0b1..Active Tamper 5 is enabled.
87556  */
87557 #define SNVS_LPATCTLR_AT5_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
87558 
87559 #define SNVS_LPATCTLR_AT1_PAD_EN_MASK            (0x10000U)
87560 #define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT           (16U)
87561 /*! AT1_PAD_EN
87562  *  0b0..Active Tamper 1 is disabled.
87563  *  0b1..Active Tamper 1 is enabled.
87564  */
87565 #define SNVS_LPATCTLR_AT1_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
87566 
87567 #define SNVS_LPATCTLR_AT2_PAD_EN_MASK            (0x20000U)
87568 #define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT           (17U)
87569 /*! AT2_PAD_EN
87570  *  0b0..Active Tamper 2 is disabled.
87571  *  0b1..Active Tamper 2 is enabled.
87572  */
87573 #define SNVS_LPATCTLR_AT2_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
87574 
87575 #define SNVS_LPATCTLR_AT3_PAD_EN_MASK            (0x40000U)
87576 #define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT           (18U)
87577 /*! AT3_PAD_EN
87578  *  0b0..Active Tamper 3 is disabled.
87579  *  0b1..Active Tamper 3 is enabled
87580  */
87581 #define SNVS_LPATCTLR_AT3_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
87582 
87583 #define SNVS_LPATCTLR_AT4_PAD_EN_MASK            (0x80000U)
87584 #define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT           (19U)
87585 /*! AT4_PAD_EN
87586  *  0b0..Active Tamper 4 is disabled.
87587  *  0b1..Active Tamper 4 is enabled.
87588  */
87589 #define SNVS_LPATCTLR_AT4_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
87590 
87591 #define SNVS_LPATCTLR_AT5_PAD_EN_MASK            (0x100000U)
87592 #define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT           (20U)
87593 /*! AT5_PAD_EN
87594  *  0b0..Active Tamper 5 is disabled.
87595  *  0b1..Active Tamper 5 is enabled.
87596  */
87597 #define SNVS_LPATCTLR_AT5_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
87598 /*! @} */
87599 
87600 /*! @name LPATCLKR - SNVS_LP Active Tamper Clock Control Register */
87601 /*! @{ */
87602 
87603 #define SNVS_LPATCLKR_AT1_CLK_CTL_MASK           (0x3U)
87604 #define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT          (0U)
87605 #define SNVS_LPATCLKR_AT1_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
87606 
87607 #define SNVS_LPATCLKR_AT2_CLK_CTL_MASK           (0x30U)
87608 #define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT          (4U)
87609 #define SNVS_LPATCLKR_AT2_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
87610 
87611 #define SNVS_LPATCLKR_AT3_CLK_CTL_MASK           (0x300U)
87612 #define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT          (8U)
87613 #define SNVS_LPATCLKR_AT3_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
87614 
87615 #define SNVS_LPATCLKR_AT4_CLK_CTL_MASK           (0x3000U)
87616 #define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT          (12U)
87617 #define SNVS_LPATCLKR_AT4_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
87618 
87619 #define SNVS_LPATCLKR_AT5_CLK_CTL_MASK           (0x30000U)
87620 #define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT          (16U)
87621 #define SNVS_LPATCLKR_AT5_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
87622 /*! @} */
87623 
87624 /*! @name LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register */
87625 /*! @{ */
87626 
87627 #define SNVS_LPATRC1R_ET1RCTL_MASK               (0x7U)
87628 #define SNVS_LPATRC1R_ET1RCTL_SHIFT              (0U)
87629 #define SNVS_LPATRC1R_ET1RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
87630 
87631 #define SNVS_LPATRC1R_ET2RCTL_MASK               (0x70U)
87632 #define SNVS_LPATRC1R_ET2RCTL_SHIFT              (4U)
87633 #define SNVS_LPATRC1R_ET2RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
87634 
87635 #define SNVS_LPATRC1R_ET3RCTL_MASK               (0x700U)
87636 #define SNVS_LPATRC1R_ET3RCTL_SHIFT              (8U)
87637 #define SNVS_LPATRC1R_ET3RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
87638 
87639 #define SNVS_LPATRC1R_ET4RCTL_MASK               (0x7000U)
87640 #define SNVS_LPATRC1R_ET4RCTL_SHIFT              (12U)
87641 #define SNVS_LPATRC1R_ET4RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
87642 
87643 #define SNVS_LPATRC1R_ET5RCTL_MASK               (0x70000U)
87644 #define SNVS_LPATRC1R_ET5RCTL_SHIFT              (16U)
87645 #define SNVS_LPATRC1R_ET5RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
87646 
87647 #define SNVS_LPATRC1R_ET6RCTL_MASK               (0x700000U)
87648 #define SNVS_LPATRC1R_ET6RCTL_SHIFT              (20U)
87649 #define SNVS_LPATRC1R_ET6RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
87650 
87651 #define SNVS_LPATRC1R_ET7RCTL_MASK               (0x7000000U)
87652 #define SNVS_LPATRC1R_ET7RCTL_SHIFT              (24U)
87653 #define SNVS_LPATRC1R_ET7RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
87654 
87655 #define SNVS_LPATRC1R_ET8RCTL_MASK               (0x70000000U)
87656 #define SNVS_LPATRC1R_ET8RCTL_SHIFT              (28U)
87657 #define SNVS_LPATRC1R_ET8RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
87658 /*! @} */
87659 
87660 /*! @name LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register */
87661 /*! @{ */
87662 
87663 #define SNVS_LPATRC2R_ET9RCTL_MASK               (0x7U)
87664 #define SNVS_LPATRC2R_ET9RCTL_SHIFT              (0U)
87665 #define SNVS_LPATRC2R_ET9RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
87666 
87667 #define SNVS_LPATRC2R_ET10RCTL_MASK              (0x70U)
87668 #define SNVS_LPATRC2R_ET10RCTL_SHIFT             (4U)
87669 #define SNVS_LPATRC2R_ET10RCTL(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
87670 /*! @} */
87671 
87672 /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
87673 /*! @{ */
87674 
87675 #define SNVS_LPGPR_GPR_MASK                      (0xFFFFFFFFU)
87676 #define SNVS_LPGPR_GPR_SHIFT                     (0U)
87677 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
87678 /*! @} */
87679 
87680 /* The count of SNVS_LPGPR */
87681 #define SNVS_LPGPR_COUNT                         (4U)
87682 
87683 /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
87684 /*! @{ */
87685 
87686 #define SNVS_HPVIDR1_MINOR_REV_MASK              (0xFFU)
87687 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             (0U)
87688 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
87689 
87690 #define SNVS_HPVIDR1_MAJOR_REV_MASK              (0xFF00U)
87691 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             (8U)
87692 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
87693 
87694 #define SNVS_HPVIDR1_IP_ID_MASK                  (0xFFFF0000U)
87695 #define SNVS_HPVIDR1_IP_ID_SHIFT                 (16U)
87696 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
87697 /*! @} */
87698 
87699 /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
87700 /*! @{ */
87701 
87702 #define SNVS_HPVIDR2_ECO_REV_MASK                (0xFF00U)
87703 #define SNVS_HPVIDR2_ECO_REV_SHIFT               (8U)
87704 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
87705 
87706 #define SNVS_HPVIDR2_IP_ERA_MASK                 (0xFF000000U)
87707 #define SNVS_HPVIDR2_IP_ERA_SHIFT                (24U)
87708 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
87709 /*! @} */
87710 
87711 
87712 /*!
87713  * @}
87714  */ /* end of group SNVS_Register_Masks */
87715 
87716 
87717 /* SNVS - Peripheral instance base addresses */
87718 /** Peripheral SNVS base address */
87719 #define SNVS_BASE                                (0x40C90000u)
87720 /** Peripheral SNVS base pointer */
87721 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
87722 /** Array initializer of SNVS peripheral base addresses */
87723 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
87724 /** Array initializer of SNVS peripheral base pointers */
87725 #define SNVS_BASE_PTRS                           { SNVS }
87726 /** Interrupt vectors for the SNVS peripheral type */
87727 #define SNVS_IRQS                                { SNVS_PULSE_EVENT_IRQn }
87728 #define SNVS_CONSOLIDATED_IRQS                   { SNVS_HP_NON_TZ_IRQn }
87729 #define SNVS_SECURITY_IRQS                       { SNVS_HP_TZ_IRQn }
87730 
87731 /*!
87732  * @}
87733  */ /* end of group SNVS_Peripheral_Access_Layer */
87734 
87735 
87736 /* ----------------------------------------------------------------------------
87737    -- SPDIF Peripheral Access Layer
87738    ---------------------------------------------------------------------------- */
87739 
87740 /*!
87741  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
87742  * @{
87743  */
87744 
87745 /** SPDIF - Register Layout Typedef */
87746 typedef struct {
87747   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
87748   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
87749   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
87750   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
87751   union {                                          /* offset: 0x10 */
87752     __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
87753     __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
87754   };
87755   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
87756   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
87757   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
87758   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
87759   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
87760   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
87761   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
87762   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
87763   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
87764   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
87765        uint8_t RESERVED_0[8];
87766   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
87767        uint8_t RESERVED_1[8];
87768   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
87769 } SPDIF_Type;
87770 
87771 /* ----------------------------------------------------------------------------
87772    -- SPDIF Register Masks
87773    ---------------------------------------------------------------------------- */
87774 
87775 /*!
87776  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
87777  * @{
87778  */
87779 
87780 /*! @name SCR - SPDIF Configuration Register */
87781 /*! @{ */
87782 
87783 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
87784 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
87785 /*! USrc_Sel - USrc_Sel
87786  *  0b00..No embedded U channel
87787  *  0b01..U channel from SPDIF receive block (CD mode)
87788  *  0b10..Reserved
87789  *  0b11..U channel from on chip transmitter
87790  */
87791 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
87792 
87793 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
87794 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
87795 /*! TxSel - TxSel
87796  *  0b000..Off and output 0
87797  *  0b001..Feed-through SPDIFIN
87798  *  0b101..Tx Normal operation
87799  */
87800 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
87801 
87802 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
87803 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
87804 /*! ValCtrl - ValCtrl
87805  *  0b0..Outgoing Validity always set
87806  *  0b1..Outgoing Validity always clear
87807  */
87808 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
87809 
87810 #define SPDIF_SCR_INPUTSRCSEL_MASK               (0xC0U)
87811 #define SPDIF_SCR_INPUTSRCSEL_SHIFT              (6U)
87812 /*! InputSrcSel - InputSrcSel
87813  *  0b00..SPDIF_IN
87814  *  0b01-0b11..None
87815  */
87816 #define SPDIF_SCR_INPUTSRCSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
87817 
87818 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
87819 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
87820 /*! DMA_TX_En - DMA_TX_En
87821  */
87822 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
87823 
87824 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
87825 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
87826 /*! DMA_Rx_En - DMA_Rx_En
87827  */
87828 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
87829 
87830 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
87831 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
87832 /*! TxFIFO_Ctrl - TxFIFO_Ctrl
87833  *  0b00..Send out digital zero on SPDIF Tx
87834  *  0b01..Tx Normal operation
87835  *  0b10..Reset to 1 sample remaining
87836  *  0b11..Reserved
87837  */
87838 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
87839 
87840 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
87841 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
87842 /*! soft_reset - soft_reset
87843  */
87844 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
87845 
87846 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
87847 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
87848 /*! LOW_POWER - LOW_POWER
87849  */
87850 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
87851 
87852 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
87853 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
87854 /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
87855  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
87856  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
87857  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
87858  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
87859  */
87860 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
87861 
87862 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
87863 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
87864 /*! TxAutoSync - TxAutoSync
87865  *  0b0..Tx FIFO auto sync off
87866  *  0b1..Tx FIFO auto sync on
87867  */
87868 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
87869 
87870 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
87871 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
87872 /*! RxAutoSync - RxAutoSync
87873  *  0b0..Rx FIFO auto sync off
87874  *  0b1..RxFIFO auto sync on
87875  */
87876 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
87877 
87878 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
87879 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
87880 /*! RxFIFOFull_Sel - RxFIFOFull_Sel
87881  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
87882  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
87883  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
87884  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
87885  */
87886 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
87887 
87888 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
87889 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
87890 /*! RxFIFO_Rst - RxFIFO_Rst
87891  *  0b0..Normal operation
87892  *  0b1..Reset register to 1 sample remaining
87893  */
87894 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
87895 
87896 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
87897 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
87898 /*! RxFIFO_Off_On - RxFIFO_Off_On
87899  *  0b0..SPDIF Rx FIFO is on
87900  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
87901  */
87902 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
87903 
87904 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
87905 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
87906 /*! RxFIFO_Ctrl - RxFIFO_Ctrl
87907  *  0b0..Normal operation
87908  *  0b1..Always read zero from Rx data register
87909  */
87910 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
87911 /*! @} */
87912 
87913 /*! @name SRCD - CDText Control Register */
87914 /*! @{ */
87915 
87916 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
87917 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
87918 /*! USyncMode - USyncMode
87919  *  0b0..Non-CD data
87920  *  0b1..CD user channel subcode
87921  */
87922 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
87923 /*! @} */
87924 
87925 /*! @name SRPC - PhaseConfig Register */
87926 /*! @{ */
87927 
87928 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
87929 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
87930 /*! GainSel - GainSel
87931  *  0b000..24*(2**10)
87932  *  0b001..16*(2**10)
87933  *  0b010..12*(2**10)
87934  *  0b011..8*(2**10)
87935  *  0b100..6*(2**10)
87936  *  0b101..4*(2**10)
87937  *  0b110..3*(2**10)
87938  */
87939 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
87940 
87941 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
87942 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
87943 /*! LOCK - LOCK
87944  */
87945 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
87946 
87947 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
87948 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
87949 /*! ClkSrc_Sel - ClkSrc_Sel
87950  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
87951  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
87952  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
87953  *  0b0101..REF_CLK_32K (XTALOSC)
87954  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
87955  *  0b1000..SPDIF_EXT_CLK
87956  */
87957 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
87958 /*! @} */
87959 
87960 /*! @name SIE - InterruptEn Register */
87961 /*! @{ */
87962 
87963 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
87964 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
87965 /*! RxFIFOFul - RxFIFOFul
87966  */
87967 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
87968 
87969 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
87970 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
87971 /*! TxEm - TxEm
87972  */
87973 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
87974 
87975 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
87976 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
87977 /*! LockLoss - LockLoss
87978  */
87979 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
87980 
87981 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
87982 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
87983 /*! RxFIFOResyn - RxFIFOResyn
87984  */
87985 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
87986 
87987 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
87988 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
87989 /*! RxFIFOUnOv - RxFIFOUnOv
87990  */
87991 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
87992 
87993 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
87994 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
87995 /*! UQErr - UQErr
87996  */
87997 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
87998 
87999 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
88000 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
88001 /*! UQSync - UQSync
88002  */
88003 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
88004 
88005 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
88006 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
88007 /*! QRxOv - QRxOv
88008  */
88009 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
88010 
88011 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
88012 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
88013 /*! QRxFul - QRxFul
88014  */
88015 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
88016 
88017 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
88018 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
88019 /*! URxOv - URxOv
88020  */
88021 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
88022 
88023 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
88024 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
88025 /*! URxFul - URxFul
88026  */
88027 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
88028 
88029 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
88030 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
88031 /*! BitErr - BitErr
88032  */
88033 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
88034 
88035 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
88036 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
88037 /*! SymErr - SymErr
88038  */
88039 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
88040 
88041 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
88042 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
88043 /*! ValNoGood - ValNoGood
88044  */
88045 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
88046 
88047 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
88048 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
88049 /*! CNew - CNew
88050  */
88051 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
88052 
88053 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
88054 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
88055 /*! TxResyn - TxResyn
88056  */
88057 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
88058 
88059 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
88060 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
88061 /*! TxUnOv - TxUnOv
88062  */
88063 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
88064 
88065 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
88066 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
88067 /*! Lock - Lock
88068  */
88069 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
88070 /*! @} */
88071 
88072 /*! @name SIC - InterruptClear Register */
88073 /*! @{ */
88074 
88075 #define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
88076 #define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
88077 /*! LockLoss - LockLoss
88078  */
88079 #define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
88080 
88081 #define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
88082 #define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
88083 /*! RxFIFOResyn - RxFIFOResyn
88084  */
88085 #define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
88086 
88087 #define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
88088 #define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
88089 /*! RxFIFOUnOv - RxFIFOUnOv
88090  */
88091 #define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
88092 
88093 #define SPDIF_SIC_UQERR_MASK                     (0x20U)
88094 #define SPDIF_SIC_UQERR_SHIFT                    (5U)
88095 /*! UQErr - UQErr
88096  */
88097 #define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
88098 
88099 #define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
88100 #define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
88101 /*! UQSync - UQSync
88102  */
88103 #define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
88104 
88105 #define SPDIF_SIC_QRXOV_MASK                     (0x80U)
88106 #define SPDIF_SIC_QRXOV_SHIFT                    (7U)
88107 /*! QRxOv - QRxOv
88108  */
88109 #define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
88110 
88111 #define SPDIF_SIC_URXOV_MASK                     (0x200U)
88112 #define SPDIF_SIC_URXOV_SHIFT                    (9U)
88113 /*! URxOv - URxOv
88114  */
88115 #define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
88116 
88117 #define SPDIF_SIC_BITERR_MASK                    (0x4000U)
88118 #define SPDIF_SIC_BITERR_SHIFT                   (14U)
88119 /*! BitErr - BitErr
88120  */
88121 #define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
88122 
88123 #define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
88124 #define SPDIF_SIC_SYMERR_SHIFT                   (15U)
88125 /*! SymErr - SymErr
88126  */
88127 #define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
88128 
88129 #define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
88130 #define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
88131 /*! ValNoGood - ValNoGood
88132  */
88133 #define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
88134 
88135 #define SPDIF_SIC_CNEW_MASK                      (0x20000U)
88136 #define SPDIF_SIC_CNEW_SHIFT                     (17U)
88137 /*! CNew - CNew
88138  */
88139 #define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
88140 
88141 #define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
88142 #define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
88143 /*! TxResyn - TxResyn
88144  */
88145 #define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
88146 
88147 #define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
88148 #define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
88149 /*! TxUnOv - TxUnOv
88150  */
88151 #define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
88152 
88153 #define SPDIF_SIC_LOCK_MASK                      (0x100000U)
88154 #define SPDIF_SIC_LOCK_SHIFT                     (20U)
88155 /*! Lock - Lock
88156  */
88157 #define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
88158 /*! @} */
88159 
88160 /*! @name SIS - InterruptStat Register */
88161 /*! @{ */
88162 
88163 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
88164 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
88165 /*! RxFIFOFul - RxFIFOFul
88166  */
88167 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
88168 
88169 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
88170 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
88171 /*! TxEm - TxEm
88172  */
88173 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
88174 
88175 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
88176 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
88177 /*! LockLoss - LockLoss
88178  */
88179 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
88180 
88181 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
88182 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
88183 /*! RxFIFOResyn - RxFIFOResyn
88184  */
88185 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
88186 
88187 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
88188 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
88189 /*! RxFIFOUnOv - RxFIFOUnOv
88190  */
88191 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
88192 
88193 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
88194 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
88195 /*! UQErr - UQErr
88196  */
88197 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
88198 
88199 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
88200 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
88201 /*! UQSync - UQSync
88202  */
88203 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
88204 
88205 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
88206 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
88207 /*! QRxOv - QRxOv
88208  */
88209 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
88210 
88211 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
88212 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
88213 /*! QRxFul - QRxFul
88214  */
88215 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
88216 
88217 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
88218 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
88219 /*! URxOv - URxOv
88220  */
88221 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
88222 
88223 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
88224 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
88225 /*! URxFul - URxFul
88226  */
88227 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
88228 
88229 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
88230 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
88231 /*! BitErr - BitErr
88232  */
88233 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
88234 
88235 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
88236 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
88237 /*! SymErr - SymErr
88238  */
88239 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
88240 
88241 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
88242 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
88243 /*! ValNoGood - ValNoGood
88244  */
88245 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
88246 
88247 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
88248 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
88249 /*! CNew - CNew
88250  */
88251 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
88252 
88253 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
88254 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
88255 /*! TxResyn - TxResyn
88256  */
88257 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
88258 
88259 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
88260 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
88261 /*! TxUnOv - TxUnOv
88262  */
88263 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
88264 
88265 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
88266 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
88267 /*! Lock - Lock
88268  */
88269 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
88270 /*! @} */
88271 
88272 /*! @name SRL - SPDIFRxLeft Register */
88273 /*! @{ */
88274 
88275 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
88276 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
88277 /*! RxDataLeft - RxDataLeft
88278  */
88279 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
88280 /*! @} */
88281 
88282 /*! @name SRR - SPDIFRxRight Register */
88283 /*! @{ */
88284 
88285 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
88286 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
88287 /*! RxDataRight - RxDataRight
88288  */
88289 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
88290 /*! @} */
88291 
88292 /*! @name SRCSH - SPDIFRxCChannel_h Register */
88293 /*! @{ */
88294 
88295 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
88296 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
88297 /*! RxCChannel_h - RxCChannel_h
88298  */
88299 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
88300 /*! @} */
88301 
88302 /*! @name SRCSL - SPDIFRxCChannel_l Register */
88303 /*! @{ */
88304 
88305 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
88306 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
88307 /*! RxCChannel_l - RxCChannel_l
88308  */
88309 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
88310 /*! @} */
88311 
88312 /*! @name SRU - UchannelRx Register */
88313 /*! @{ */
88314 
88315 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
88316 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
88317 /*! RxUChannel - RxUChannel
88318  */
88319 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
88320 /*! @} */
88321 
88322 /*! @name SRQ - QchannelRx Register */
88323 /*! @{ */
88324 
88325 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
88326 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
88327 /*! RxQChannel - RxQChannel
88328  */
88329 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
88330 /*! @} */
88331 
88332 /*! @name STL - SPDIFTxLeft Register */
88333 /*! @{ */
88334 
88335 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
88336 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
88337 /*! TxDataLeft - TxDataLeft
88338  */
88339 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
88340 /*! @} */
88341 
88342 /*! @name STR - SPDIFTxRight Register */
88343 /*! @{ */
88344 
88345 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
88346 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
88347 /*! TxDataRight - TxDataRight
88348  */
88349 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
88350 /*! @} */
88351 
88352 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
88353 /*! @{ */
88354 
88355 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
88356 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
88357 /*! TxCChannelCons_h - TxCChannelCons_h
88358  */
88359 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
88360 /*! @} */
88361 
88362 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
88363 /*! @{ */
88364 
88365 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
88366 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
88367 /*! TxCChannelCons_l - TxCChannelCons_l
88368  */
88369 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
88370 /*! @} */
88371 
88372 /*! @name SRFM - FreqMeas Register */
88373 /*! @{ */
88374 
88375 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
88376 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
88377 /*! FreqMeas - FreqMeas
88378  */
88379 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
88380 /*! @} */
88381 
88382 /*! @name STC - SPDIFTxClk Register */
88383 /*! @{ */
88384 
88385 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
88386 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
88387 /*! TxClk_DF - TxClk_DF
88388  *  0b0000000..divider factor is 1
88389  *  0b0000001..divider factor is 2
88390  *  0b1111111..divider factor is 128
88391  */
88392 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
88393 
88394 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
88395 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
88396 /*! tx_all_clk_en - tx_all_clk_en
88397  *  0b0..disable transfer clock.
88398  *  0b1..enable transfer clock.
88399  */
88400 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
88401 
88402 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
88403 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
88404 /*! TxClk_Source - TxClk_Source
88405  *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
88406  *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
88407  *  0b011..SPDIF_EXT_CLK, from pads
88408  *  0b101..ipg_clk input (frequency divided)
88409  */
88410 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
88411 
88412 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
88413 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
88414 /*! SYSCLK_DF - SYSCLK_DF
88415  *  0b000000000..no clock signal
88416  *  0b000000001..divider factor is 2
88417  *  0b111111111..divider factor is 512
88418  */
88419 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
88420 /*! @} */
88421 
88422 
88423 /*!
88424  * @}
88425  */ /* end of group SPDIF_Register_Masks */
88426 
88427 
88428 /* SPDIF - Peripheral instance base addresses */
88429 /** Peripheral SPDIF base address */
88430 #define SPDIF_BASE                               (0x40400000u)
88431 /** Peripheral SPDIF base pointer */
88432 #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
88433 /** Array initializer of SPDIF peripheral base addresses */
88434 #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
88435 /** Array initializer of SPDIF peripheral base pointers */
88436 #define SPDIF_BASE_PTRS                          { SPDIF }
88437 /** Interrupt vectors for the SPDIF peripheral type */
88438 #define SPDIF_IRQS                               { SPDIF_IRQn }
88439 
88440 /*!
88441  * @}
88442  */ /* end of group SPDIF_Peripheral_Access_Layer */
88443 
88444 
88445 /* ----------------------------------------------------------------------------
88446    -- SRAM Peripheral Access Layer
88447    ---------------------------------------------------------------------------- */
88448 
88449 /*!
88450  * @addtogroup SRAM_Peripheral_Access_Layer SRAM Peripheral Access Layer
88451  * @{
88452  */
88453 
88454 /** SRAM - Register Layout Typedef */
88455 typedef struct {
88456        uint8_t RESERVED_0[12288];
88457   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x3000 */
88458 } SRAM_Type;
88459 
88460 /* ----------------------------------------------------------------------------
88461    -- SRAM Register Masks
88462    ---------------------------------------------------------------------------- */
88463 
88464 /*!
88465  * @addtogroup SRAM_Register_Masks SRAM Register Masks
88466  * @{
88467  */
88468 
88469 /*! @name CTRL - Control Register */
88470 /*! @{ */
88471 
88472 #define SRAM_CTRL_RAM_RD_EN_MASK                 (0x1U)
88473 #define SRAM_CTRL_RAM_RD_EN_SHIFT                (0U)
88474 /*! RAM_RD_EN - RAM Read Enable (with lock)
88475  *  0b0..Disable read access
88476  *  0b1..Enable read access
88477  */
88478 #define SRAM_CTRL_RAM_RD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
88479 
88480 #define SRAM_CTRL_RAM_WR_EN_MASK                 (0x2U)
88481 #define SRAM_CTRL_RAM_WR_EN_SHIFT                (1U)
88482 /*! RAM_WR_EN - RAM Write Enable (with lock)
88483  *  0b0..Disable write access
88484  *  0b1..Enable write access
88485  */
88486 #define SRAM_CTRL_RAM_WR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
88487 
88488 #define SRAM_CTRL_PWR_EN_MASK                    (0x3CU)
88489 #define SRAM_CTRL_PWR_EN_SHIFT                   (2U)
88490 /*! PWR_EN - Power Enable (with lock)
88491  */
88492 #define SRAM_CTRL_PWR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
88493 
88494 #define SRAM_CTRL_TAMPER_BLOCK_EN_MASK           (0x40U)
88495 #define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT          (6U)
88496 /*! TAMPER_BLOCK_EN - Tamper Block Enable (with lock)
88497  *  0b0..Allow R/W access to secure RAM when tamper is detected
88498  *  0b1..Block R/W access to secure RAM when tamper is detected
88499  */
88500 #define SRAM_CTRL_TAMPER_BLOCK_EN(x)             (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
88501 
88502 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK         (0x80U)
88503 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT        (7U)
88504 /*! TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock)
88505  *  0b0..Disable the turn off function when tamper is detected
88506  *  0b1..Turn off power for all secure RAM banks when tamper is detected
88507  */
88508 #define SRAM_CTRL_TAMPER_PWR_OFF_EN(x)           (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
88509 
88510 #define SRAM_CTRL_LOCK_BIT_MASK                  (0xFF0000U)
88511 #define SRAM_CTRL_LOCK_BIT_SHIFT                 (16U)
88512 /*! LOCK_BIT - Lock bits
88513  */
88514 #define SRAM_CTRL_LOCK_BIT(x)                    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
88515 /*! @} */
88516 
88517 
88518 /*!
88519  * @}
88520  */ /* end of group SRAM_Register_Masks */
88521 
88522 
88523 /* SRAM - Peripheral instance base addresses */
88524 /** Peripheral SRAM base address */
88525 #define SRAM_BASE                                (0x40C9C000u)
88526 /** Peripheral SRAM base pointer */
88527 #define SRAM                                     ((SRAM_Type *)SRAM_BASE)
88528 /** Array initializer of SRAM peripheral base addresses */
88529 #define SRAM_BASE_ADDRS                          { SRAM_BASE }
88530 /** Array initializer of SRAM peripheral base pointers */
88531 #define SRAM_BASE_PTRS                           { SRAM }
88532 
88533 /*!
88534  * @}
88535  */ /* end of group SRAM_Peripheral_Access_Layer */
88536 
88537 
88538 /* ----------------------------------------------------------------------------
88539    -- SRC Peripheral Access Layer
88540    ---------------------------------------------------------------------------- */
88541 
88542 /*!
88543  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
88544  * @{
88545  */
88546 
88547 /** SRC - Register Layout Typedef */
88548 typedef struct {
88549   __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x0 */
88550   __IO uint32_t SRMR;                              /**< SRC Reset Mode Register, offset: 0x4 */
88551   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x8 */
88552   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0xC */
88553   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x10 */
88554   __IO uint32_t GPR[20];                           /**< SRC General Purpose Register, array offset: 0x14, array step: 0x4 */
88555        uint8_t RESERVED_0[412];
88556   __IO uint32_t AUTHEN_MEGA;                       /**< Slice Authentication Register, offset: 0x200 */
88557   __IO uint32_t CTRL_MEGA;                         /**< Slice Control Register, offset: 0x204 */
88558   __IO uint32_t SETPOINT_MEGA;                     /**< Slice Setpoint Config Register, offset: 0x208 */
88559   __IO uint32_t DOMAIN_MEGA;                       /**< Slice Domain Config Register, offset: 0x20C */
88560   __IO uint32_t STAT_MEGA;                         /**< Slice Status Register, offset: 0x210 */
88561        uint8_t RESERVED_1[12];
88562   __IO uint32_t AUTHEN_DISPLAY;                    /**< Slice Authentication Register, offset: 0x220 */
88563   __IO uint32_t CTRL_DISPLAY;                      /**< Slice Control Register, offset: 0x224 */
88564   __IO uint32_t SETPOINT_DISPLAY;                  /**< Slice Setpoint Config Register, offset: 0x228 */
88565   __IO uint32_t DOMAIN_DISPLAY;                    /**< Slice Domain Config Register, offset: 0x22C */
88566   __IO uint32_t STAT_DISPLAY;                      /**< Slice Status Register, offset: 0x230 */
88567        uint8_t RESERVED_2[12];
88568   __IO uint32_t AUTHEN_WAKEUP;                     /**< Slice Authentication Register, offset: 0x240 */
88569   __IO uint32_t CTRL_WAKEUP;                       /**< Slice Control Register, offset: 0x244 */
88570   __IO uint32_t SETPOINT_WAKEUP;                   /**< Slice Setpoint Config Register, offset: 0x248 */
88571   __IO uint32_t DOMAIN_WAKEUP;                     /**< Slice Domain Config Register, offset: 0x24C */
88572   __IO uint32_t STAT_WAKEUP;                       /**< Slice Status Register, offset: 0x250 */
88573        uint8_t RESERVED_3[44];
88574   __IO uint32_t AUTHEN_M4CORE;                     /**< Slice Authentication Register, offset: 0x280 */
88575   __IO uint32_t CTRL_M4CORE;                       /**< Slice Control Register, offset: 0x284 */
88576   __IO uint32_t SETPOINT_M4CORE;                   /**< Slice Setpoint Config Register, offset: 0x288 */
88577   __IO uint32_t DOMAIN_M4CORE;                     /**< Slice Domain Config Register, offset: 0x28C */
88578   __IO uint32_t STAT_M4CORE;                       /**< Slice Status Register, offset: 0x290 */
88579        uint8_t RESERVED_4[12];
88580   __IO uint32_t AUTHEN_M7CORE;                     /**< Slice Authentication Register, offset: 0x2A0 */
88581   __IO uint32_t CTRL_M7CORE;                       /**< Slice Control Register, offset: 0x2A4 */
88582   __IO uint32_t SETPOINT_M7CORE;                   /**< Slice Setpoint Config Register, offset: 0x2A8 */
88583   __IO uint32_t DOMAIN_M7CORE;                     /**< Slice Domain Config Register, offset: 0x2AC */
88584   __IO uint32_t STAT_M7CORE;                       /**< Slice Status Register, offset: 0x2B0 */
88585        uint8_t RESERVED_5[12];
88586   __IO uint32_t AUTHEN_M4DEBUG;                    /**< Slice Authentication Register, offset: 0x2C0 */
88587   __IO uint32_t CTRL_M4DEBUG;                      /**< Slice Control Register, offset: 0x2C4 */
88588   __IO uint32_t SETPOINT_M4DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2C8 */
88589   __IO uint32_t DOMAIN_M4DEBUG;                    /**< Slice Domain Config Register, offset: 0x2CC */
88590   __IO uint32_t STAT_M4DEBUG;                      /**< Slice Status Register, offset: 0x2D0 */
88591        uint8_t RESERVED_6[12];
88592   __IO uint32_t AUTHEN_M7DEBUG;                    /**< Slice Authentication Register, offset: 0x2E0 */
88593   __IO uint32_t CTRL_M7DEBUG;                      /**< Slice Control Register, offset: 0x2E4 */
88594   __IO uint32_t SETPOINT_M7DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2E8 */
88595   __IO uint32_t DOMAIN_M7DEBUG;                    /**< Slice Domain Config Register, offset: 0x2EC */
88596   __IO uint32_t STAT_M7DEBUG;                      /**< Slice Status Register, offset: 0x2F0 */
88597        uint8_t RESERVED_7[12];
88598   __IO uint32_t AUTHEN_USBPHY1;                    /**< Slice Authentication Register, offset: 0x300 */
88599   __IO uint32_t CTRL_USBPHY1;                      /**< Slice Control Register, offset: 0x304 */
88600   __IO uint32_t SETPOINT_USBPHY1;                  /**< Slice Setpoint Config Register, offset: 0x308 */
88601   __IO uint32_t DOMAIN_USBPHY1;                    /**< Slice Domain Config Register, offset: 0x30C */
88602   __IO uint32_t STAT_USBPHY1;                      /**< Slice Status Register, offset: 0x310 */
88603        uint8_t RESERVED_8[12];
88604   __IO uint32_t AUTHEN_USBPHY2;                    /**< Slice Authentication Register, offset: 0x320 */
88605   __IO uint32_t CTRL_USBPHY2;                      /**< Slice Control Register, offset: 0x324 */
88606   __IO uint32_t SETPOINT_USBPHY2;                  /**< Slice Setpoint Config Register, offset: 0x328 */
88607   __IO uint32_t DOMAIN_USBPHY2;                    /**< Slice Domain Config Register, offset: 0x32C */
88608   __IO uint32_t STAT_USBPHY2;                      /**< Slice Status Register, offset: 0x330 */
88609 } SRC_Type;
88610 
88611 /* ----------------------------------------------------------------------------
88612    -- SRC Register Masks
88613    ---------------------------------------------------------------------------- */
88614 
88615 /*!
88616  * @addtogroup SRC_Register_Masks SRC Register Masks
88617  * @{
88618  */
88619 
88620 /*! @name SCR - SRC Control Register */
88621 /*! @{ */
88622 
88623 #define SRC_SCR_BT_RELEASE_M4_MASK               (0x1U)
88624 #define SRC_SCR_BT_RELEASE_M4_SHIFT              (0U)
88625 /*! BT_RELEASE_M4
88626  *  0b0..cm4 core reset is asserted
88627  *  0b1..cm4 core reset is released
88628  */
88629 #define SRC_SCR_BT_RELEASE_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)
88630 
88631 #define SRC_SCR_BT_RELEASE_M7_MASK               (0x2U)
88632 #define SRC_SCR_BT_RELEASE_M7_SHIFT              (1U)
88633 /*! BT_RELEASE_M7
88634  *  0b0..cm7 core reset is asserted
88635  *  0b1..cm7 core reset is released
88636  */
88637 #define SRC_SCR_BT_RELEASE_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)
88638 /*! @} */
88639 
88640 /*! @name SRMR - SRC Reset Mode Register */
88641 /*! @{ */
88642 
88643 #define SRC_SRMR_WDOG_RESET_MODE_MASK            (0x3U)
88644 #define SRC_SRMR_WDOG_RESET_MODE_SHIFT           (0U)
88645 /*! WDOG_RESET_MODE - Wdog reset mode configuration
88646  *  0b00..reset system
88647  *  0b01..reserved
88648  *  0b10..reserved
88649  *  0b11..do not reset anything
88650  */
88651 #define SRC_SRMR_WDOG_RESET_MODE(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)
88652 
88653 #define SRC_SRMR_WDOG3_RESET_MODE_MASK           (0xCU)
88654 #define SRC_SRMR_WDOG3_RESET_MODE_SHIFT          (2U)
88655 /*! WDOG3_RESET_MODE - Wdog3 reset mode configuration
88656  *  0b00..reset system
88657  *  0b01..reserved
88658  *  0b10..reserved
88659  *  0b11..do not reset anything
88660  */
88661 #define SRC_SRMR_WDOG3_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)
88662 
88663 #define SRC_SRMR_WDOG4_RESET_MODE_MASK           (0x30U)
88664 #define SRC_SRMR_WDOG4_RESET_MODE_SHIFT          (4U)
88665 /*! WDOG4_RESET_MODE - Wdog4 reset mode configuration
88666  *  0b00..reset system
88667  *  0b01..reserved
88668  *  0b10..reserved
88669  *  0b11..do not reset anything
88670  */
88671 #define SRC_SRMR_WDOG4_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)
88672 
88673 #define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK        (0xC0U)
88674 #define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT       (6U)
88675 /*! M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration
88676  *  0b00..reset system
88677  *  0b01..reserved
88678  *  0b10..reserved
88679  *  0b11..do not reset anything
88680  */
88681 #define SRC_SRMR_M4LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)
88682 
88683 #define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK        (0x300U)
88684 #define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT       (8U)
88685 /*! M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration
88686  *  0b00..reset system
88687  *  0b01..reserved
88688  *  0b10..reserved
88689  *  0b11..do not reset anything
88690  */
88691 #define SRC_SRMR_M7LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)
88692 
88693 #define SRC_SRMR_M4REQ_RESET_MODE_MASK           (0xC00U)
88694 #define SRC_SRMR_M4REQ_RESET_MODE_SHIFT          (10U)
88695 /*! M4REQ_RESET_MODE - M4 request reset configuration
88696  *  0b00..reset system
88697  *  0b01..reserved
88698  *  0b10..reserved
88699  *  0b11..do not reset anything
88700  */
88701 #define SRC_SRMR_M4REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)
88702 
88703 #define SRC_SRMR_M7REQ_RESET_MODE_MASK           (0x3000U)
88704 #define SRC_SRMR_M7REQ_RESET_MODE_SHIFT          (12U)
88705 /*! M7REQ_RESET_MODE - M7 request reset configuration
88706  *  0b00..reset system
88707  *  0b01..reserved
88708  *  0b10..reserved
88709  *  0b11..do not reset anything
88710  */
88711 #define SRC_SRMR_M7REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)
88712 
88713 #define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK       (0xC000U)
88714 #define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT      (14U)
88715 /*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration
88716  *  0b00..reset system
88717  *  0b01..reserved
88718  *  0b10..reserved
88719  *  0b11..do not reset anything
88720  */
88721 #define SRC_SRMR_TEMPSENSE_RESET_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)
88722 
88723 #define SRC_SRMR_CSU_RESET_MODE_MASK             (0x30000U)
88724 #define SRC_SRMR_CSU_RESET_MODE_SHIFT            (16U)
88725 /*! CSU_RESET_MODE - CSU reset mode configuration
88726  *  0b00..reset system
88727  *  0b01..reserved
88728  *  0b10..reserved
88729  *  0b11..do not reset anything
88730  */
88731 #define SRC_SRMR_CSU_RESET_MODE(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)
88732 
88733 #define SRC_SRMR_JTAGSW_RESET_MODE_MASK          (0xC0000U)
88734 #define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT         (18U)
88735 /*! JTAGSW_RESET_MODE - Jtag SW reset mode configuration
88736  *  0b00..reset system
88737  *  0b01..reserved
88738  *  0b10..reserved
88739  *  0b11..do not reset anything
88740  */
88741 #define SRC_SRMR_JTAGSW_RESET_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)
88742 
88743 #define SRC_SRMR_OVERVOLT_RESET_MODE_MASK        (0x300000U)
88744 #define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT       (20U)
88745 /*! OVERVOLT_RESET_MODE - Jtag SW reset mode configuration
88746  *  0b00..reset system
88747  *  0b01..reserved
88748  *  0b10..reserved
88749  *  0b11..do not reset anything
88750  */
88751 #define SRC_SRMR_OVERVOLT_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)
88752 /*! @} */
88753 
88754 /*! @name SBMR1 - SRC Boot Mode Register 1 */
88755 /*! @{ */
88756 
88757 #define SRC_SBMR1_BOOT_CFG1_MASK                 (0xFFU)
88758 #define SRC_SBMR1_BOOT_CFG1_SHIFT                (0U)
88759 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
88760 
88761 #define SRC_SBMR1_BOOT_CFG2_MASK                 (0xFF00U)
88762 #define SRC_SBMR1_BOOT_CFG2_SHIFT                (8U)
88763 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
88764 
88765 #define SRC_SBMR1_BOOT_CFG3_MASK                 (0xFF0000U)
88766 #define SRC_SBMR1_BOOT_CFG3_SHIFT                (16U)
88767 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
88768 
88769 #define SRC_SBMR1_BOOT_CFG4_MASK                 (0xFF000000U)
88770 #define SRC_SBMR1_BOOT_CFG4_SHIFT                (24U)
88771 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
88772 /*! @} */
88773 
88774 /*! @name SBMR2 - SRC Boot Mode Register 2 */
88775 /*! @{ */
88776 
88777 #define SRC_SBMR2_SEC_CONFIG_MASK                (0x3U)
88778 #define SRC_SBMR2_SEC_CONFIG_SHIFT               (0U)
88779 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
88780 
88781 #define SRC_SBMR2_BT_FUSE_SEL_MASK               (0x10U)
88782 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              (4U)
88783 #define SRC_SBMR2_BT_FUSE_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
88784 
88785 #define SRC_SBMR2_BMOD_MASK                      (0x3000000U)
88786 #define SRC_SBMR2_BMOD_SHIFT                     (24U)
88787 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
88788 /*! @} */
88789 
88790 /*! @name SRSR - SRC Reset Status Register */
88791 /*! @{ */
88792 
88793 #define SRC_SRSR_IPP_RESET_B_M7_MASK             (0x1U)
88794 #define SRC_SRSR_IPP_RESET_B_M7_SHIFT            (0U)
88795 /*! IPP_RESET_B_M7
88796  *  0b0..Reset is not a result of ipp_reset_b pin.
88797  *  0b1..Reset is a result of ipp_reset_b pin.
88798  */
88799 #define SRC_SRSR_IPP_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)
88800 
88801 #define SRC_SRSR_M7_REQUEST_M7_MASK              (0x2U)
88802 #define SRC_SRSR_M7_REQUEST_M7_SHIFT             (1U)
88803 /*! M7_REQUEST_M7
88804  *  0b0..Reset is not a result of m7 reset request.
88805  *  0b1..Reset is a result of m7 reset request.
88806  */
88807 #define SRC_SRSR_M7_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)
88808 
88809 #define SRC_SRSR_M7_LOCKUP_M7_MASK               (0x4U)
88810 #define SRC_SRSR_M7_LOCKUP_M7_SHIFT              (2U)
88811 /*! M7_LOCKUP_M7
88812  *  0b0..Reset is not a result of the mentioned case.
88813  *  0b1..Reset is a result of the mentioned case.
88814  */
88815 #define SRC_SRSR_M7_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)
88816 
88817 #define SRC_SRSR_CSU_RESET_B_M7_MASK             (0x8U)
88818 #define SRC_SRSR_CSU_RESET_B_M7_SHIFT            (3U)
88819 /*! CSU_RESET_B_M7
88820  *  0b0..Reset is not a result of the csu_reset_b event.
88821  *  0b1..Reset is a result of the csu_reset_b event.
88822  */
88823 #define SRC_SRSR_CSU_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)
88824 
88825 #define SRC_SRSR_IPP_USER_RESET_B_M7_MASK        (0x10U)
88826 #define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT       (4U)
88827 /*! IPP_USER_RESET_B_M7
88828  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
88829  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
88830  */
88831 #define SRC_SRSR_IPP_USER_RESET_B_M7(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)
88832 
88833 #define SRC_SRSR_WDOG_RST_B_M7_MASK              (0x20U)
88834 #define SRC_SRSR_WDOG_RST_B_M7_SHIFT             (5U)
88835 /*! WDOG_RST_B_M7
88836  *  0b0..Reset is not a result of the watchdog time-out event.
88837  *  0b1..Reset is a result of the watchdog time-out event.
88838  */
88839 #define SRC_SRSR_WDOG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)
88840 
88841 #define SRC_SRSR_JTAG_RST_B_M7_MASK              (0x40U)
88842 #define SRC_SRSR_JTAG_RST_B_M7_SHIFT             (6U)
88843 /*! JTAG_RST_B_M7
88844  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
88845  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
88846  */
88847 #define SRC_SRSR_JTAG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)
88848 
88849 #define SRC_SRSR_JTAG_SW_RST_M7_MASK             (0x80U)
88850 #define SRC_SRSR_JTAG_SW_RST_M7_SHIFT            (7U)
88851 /*! JTAG_SW_RST_M7
88852  *  0b0..Reset is not a result of software reset from JTAG.
88853  *  0b1..Reset is a result of software reset from JTAG.
88854  */
88855 #define SRC_SRSR_JTAG_SW_RST_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)
88856 
88857 #define SRC_SRSR_WDOG3_RST_B_M7_MASK             (0x100U)
88858 #define SRC_SRSR_WDOG3_RST_B_M7_SHIFT            (8U)
88859 /*! WDOG3_RST_B_M7
88860  *  0b0..Reset is not a result of the watchdog3 time-out event.
88861  *  0b1..Reset is a result of the watchdog3 time-out event.
88862  */
88863 #define SRC_SRSR_WDOG3_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)
88864 
88865 #define SRC_SRSR_WDOG4_RST_B_M7_MASK             (0x200U)
88866 #define SRC_SRSR_WDOG4_RST_B_M7_SHIFT            (9U)
88867 /*! WDOG4_RST_B_M7
88868  *  0b0..Reset is not a result of the watchdog4 time-out event.
88869  *  0b1..Reset is a result of the watchdog4 time-out event.
88870  */
88871 #define SRC_SRSR_WDOG4_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)
88872 
88873 #define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK         (0x400U)
88874 #define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT        (10U)
88875 /*! TEMPSENSE_RST_B_M7
88876  *  0b0..Reset is not a result of software reset from Temperature Sensor.
88877  *  0b1..Reset is a result of software reset from Temperature Sensor.
88878  */
88879 #define SRC_SRSR_TEMPSENSE_RST_B_M7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)
88880 
88881 #define SRC_SRSR_M4_REQUEST_M7_MASK              (0x800U)
88882 #define SRC_SRSR_M4_REQUEST_M7_SHIFT             (11U)
88883 /*! M4_REQUEST_M7
88884  *  0b0..Reset is not a result of m4 reset request.
88885  *  0b1..Reset is a result of m4 reset request.
88886  */
88887 #define SRC_SRSR_M4_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)
88888 
88889 #define SRC_SRSR_M4_LOCKUP_M7_MASK               (0x1000U)
88890 #define SRC_SRSR_M4_LOCKUP_M7_SHIFT              (12U)
88891 /*! M4_LOCKUP_M7
88892  *  0b0..Reset is not a result of the mentioned case.
88893  *  0b1..Reset is a result of the mentioned case.
88894  */
88895 #define SRC_SRSR_M4_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)
88896 
88897 #define SRC_SRSR_OVERVOLT_RST_M7_MASK            (0x2000U)
88898 #define SRC_SRSR_OVERVOLT_RST_M7_SHIFT           (13U)
88899 /*! OVERVOLT_RST_M7
88900  *  0b0..Reset is not a result of the mentioned case.
88901  *  0b1..Reset is a result of the mentioned case.
88902  */
88903 #define SRC_SRSR_OVERVOLT_RST_M7(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)
88904 
88905 #define SRC_SRSR_CDOG_RST_M7_MASK                (0x4000U)
88906 #define SRC_SRSR_CDOG_RST_M7_SHIFT               (14U)
88907 /*! CDOG_RST_M7
88908  *  0b0..Reset is not a result of the mentioned case.
88909  *  0b1..Reset is a result of the mentioned case.
88910  */
88911 #define SRC_SRSR_CDOG_RST_M7(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)
88912 
88913 #define SRC_SRSR_IPP_RESET_B_M4_MASK             (0x10000U)
88914 #define SRC_SRSR_IPP_RESET_B_M4_SHIFT            (16U)
88915 /*! IPP_RESET_B_M4
88916  *  0b0..Reset is not a result of ipp_reset_b pin.
88917  *  0b1..Reset is a result of ipp_reset_b pin.
88918  */
88919 #define SRC_SRSR_IPP_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)
88920 
88921 #define SRC_SRSR_M4_REQUEST_M4_MASK              (0x20000U)
88922 #define SRC_SRSR_M4_REQUEST_M4_SHIFT             (17U)
88923 /*! M4_REQUEST_M4
88924  *  0b0..Reset is not a result of m4 reset request.
88925  *  0b1..Reset is a result of m4 reset request.
88926  */
88927 #define SRC_SRSR_M4_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)
88928 
88929 #define SRC_SRSR_M4_LOCKUP_M4_MASK               (0x40000U)
88930 #define SRC_SRSR_M4_LOCKUP_M4_SHIFT              (18U)
88931 /*! M4_LOCKUP_M4
88932  *  0b0..Reset is not a result of the mentioned case.
88933  *  0b1..Reset is a result of the mentioned case.
88934  */
88935 #define SRC_SRSR_M4_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)
88936 
88937 #define SRC_SRSR_CSU_RESET_B_M4_MASK             (0x80000U)
88938 #define SRC_SRSR_CSU_RESET_B_M4_SHIFT            (19U)
88939 /*! CSU_RESET_B_M4
88940  *  0b0..Reset is not a result of the csu_reset_b event.
88941  *  0b1..Reset is a result of the csu_reset_b event.
88942  */
88943 #define SRC_SRSR_CSU_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)
88944 
88945 #define SRC_SRSR_IPP_USER_RESET_B_M4_MASK        (0x100000U)
88946 #define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT       (20U)
88947 /*! IPP_USER_RESET_B_M4
88948  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
88949  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
88950  */
88951 #define SRC_SRSR_IPP_USER_RESET_B_M4(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)
88952 
88953 #define SRC_SRSR_WDOG_RST_B_M4_MASK              (0x200000U)
88954 #define SRC_SRSR_WDOG_RST_B_M4_SHIFT             (21U)
88955 /*! WDOG_RST_B_M4
88956  *  0b0..Reset is not a result of the watchdog time-out event.
88957  *  0b1..Reset is a result of the watchdog time-out event.
88958  */
88959 #define SRC_SRSR_WDOG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)
88960 
88961 #define SRC_SRSR_JTAG_RST_B_M4_MASK              (0x400000U)
88962 #define SRC_SRSR_JTAG_RST_B_M4_SHIFT             (22U)
88963 /*! JTAG_RST_B_M4
88964  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
88965  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
88966  */
88967 #define SRC_SRSR_JTAG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)
88968 
88969 #define SRC_SRSR_JTAG_SW_RST_M4_MASK             (0x800000U)
88970 #define SRC_SRSR_JTAG_SW_RST_M4_SHIFT            (23U)
88971 /*! JTAG_SW_RST_M4
88972  *  0b0..Reset is not a result of software reset from JTAG.
88973  *  0b1..Reset is a result of software reset from JTAG.
88974  */
88975 #define SRC_SRSR_JTAG_SW_RST_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)
88976 
88977 #define SRC_SRSR_WDOG3_RST_B_M4_MASK             (0x1000000U)
88978 #define SRC_SRSR_WDOG3_RST_B_M4_SHIFT            (24U)
88979 /*! WDOG3_RST_B_M4
88980  *  0b0..Reset is not a result of the watchdog3 time-out event.
88981  *  0b1..Reset is a result of the watchdog3 time-out event.
88982  */
88983 #define SRC_SRSR_WDOG3_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)
88984 
88985 #define SRC_SRSR_WDOG4_RST_B_M4_MASK             (0x2000000U)
88986 #define SRC_SRSR_WDOG4_RST_B_M4_SHIFT            (25U)
88987 /*! WDOG4_RST_B_M4
88988  *  0b0..Reset is not a result of the watchdog4 time-out event.
88989  *  0b1..Reset is a result of the watchdog4 time-out event.
88990  */
88991 #define SRC_SRSR_WDOG4_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)
88992 
88993 #define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK         (0x4000000U)
88994 #define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT        (26U)
88995 /*! TEMPSENSE_RST_B_M4
88996  *  0b0..Reset is not a result of software reset from Temperature Sensor.
88997  *  0b1..Reset is a result of software reset from Temperature Sensor.
88998  */
88999 #define SRC_SRSR_TEMPSENSE_RST_B_M4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)
89000 
89001 #define SRC_SRSR_M7_REQUEST_M4_MASK              (0x8000000U)
89002 #define SRC_SRSR_M7_REQUEST_M4_SHIFT             (27U)
89003 /*! M7_REQUEST_M4
89004  *  0b0..Reset is not a result of m7 reset request.
89005  *  0b1..Reset is a result of m7 reset request.
89006  */
89007 #define SRC_SRSR_M7_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)
89008 
89009 #define SRC_SRSR_M7_LOCKUP_M4_MASK               (0x10000000U)
89010 #define SRC_SRSR_M7_LOCKUP_M4_SHIFT              (28U)
89011 /*! M7_LOCKUP_M4
89012  *  0b0..Reset is not a result of the mentioned case.
89013  *  0b1..Reset is a result of the mentioned case.
89014  */
89015 #define SRC_SRSR_M7_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)
89016 
89017 #define SRC_SRSR_OVERVOLT_RST_M4_MASK            (0x20000000U)
89018 #define SRC_SRSR_OVERVOLT_RST_M4_SHIFT           (29U)
89019 /*! OVERVOLT_RST_M4
89020  *  0b0..Reset is not a result of the mentioned case.
89021  *  0b1..Reset is a result of the mentioned case.
89022  */
89023 #define SRC_SRSR_OVERVOLT_RST_M4(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)
89024 
89025 #define SRC_SRSR_CDOG_RST_M4_MASK                (0x40000000U)
89026 #define SRC_SRSR_CDOG_RST_M4_SHIFT               (30U)
89027 /*! CDOG_RST_M4
89028  *  0b0..Reset is not a result of the mentioned case.
89029  *  0b1..Reset is a result of the mentioned case.
89030  */
89031 #define SRC_SRSR_CDOG_RST_M4(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)
89032 /*! @} */
89033 
89034 /*! @name GPR - SRC General Purpose Register */
89035 /*! @{ */
89036 
89037 #define SRC_GPR_GPR_MASK                         (0xFFFFFFFFU)
89038 #define SRC_GPR_GPR_SHIFT                        (0U)
89039 /*! GPR - General Purpose Register.
89040  */
89041 #define SRC_GPR_GPR(x)                           (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)
89042 /*! @} */
89043 
89044 /* The count of SRC_GPR */
89045 #define SRC_GPR_COUNT                            (20U)
89046 
89047 /*! @name AUTHEN_MEGA - Slice Authentication Register */
89048 /*! @{ */
89049 
89050 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK         (0x1U)
89051 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT        (0U)
89052 /*! DOMAIN_MODE
89053  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89054  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89055  */
89056 #define SRC_AUTHEN_MEGA_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)
89057 
89058 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK       (0x2U)
89059 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT      (1U)
89060 /*! SETPOINT_MODE
89061  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89062  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89063  */
89064 #define SRC_AUTHEN_MEGA_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)
89065 
89066 #define SRC_AUTHEN_MEGA_LOCK_MODE_MASK           (0x80U)
89067 #define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT          (7U)
89068 /*! LOCK_MODE - Domain/Setpoint mode lock
89069  */
89070 #define SRC_AUTHEN_MEGA_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)
89071 
89072 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK         (0xF00U)
89073 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT        (8U)
89074 #define SRC_AUTHEN_MEGA_ASSIGN_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)
89075 
89076 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK         (0x8000U)
89077 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT        (15U)
89078 /*! LOCK_ASSIGN - Assign list lock
89079  */
89080 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)
89081 
89082 #define SRC_AUTHEN_MEGA_WHITE_LIST_MASK          (0xF0000U)
89083 #define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT         (16U)
89084 /*! WHITE_LIST - Domain ID white list
89085  */
89086 #define SRC_AUTHEN_MEGA_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)
89087 
89088 #define SRC_AUTHEN_MEGA_LOCK_LIST_MASK           (0x800000U)
89089 #define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT          (23U)
89090 /*! LOCK_LIST - White list lock
89091  */
89092 #define SRC_AUTHEN_MEGA_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)
89093 
89094 #define SRC_AUTHEN_MEGA_USER_MASK                (0x1000000U)
89095 #define SRC_AUTHEN_MEGA_USER_SHIFT               (24U)
89096 /*! USER - Allow user mode access
89097  */
89098 #define SRC_AUTHEN_MEGA_USER(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)
89099 
89100 #define SRC_AUTHEN_MEGA_NONSECURE_MASK           (0x2000000U)
89101 #define SRC_AUTHEN_MEGA_NONSECURE_SHIFT          (25U)
89102 /*! NONSECURE - Allow non-secure mode access
89103  */
89104 #define SRC_AUTHEN_MEGA_NONSECURE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)
89105 
89106 #define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK        (0x80000000U)
89107 #define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT       (31U)
89108 /*! LOCK_SETTING - Lock NONSECURE and USER
89109  */
89110 #define SRC_AUTHEN_MEGA_LOCK_SETTING(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)
89111 /*! @} */
89112 
89113 /*! @name CTRL_MEGA - Slice Control Register */
89114 /*! @{ */
89115 
89116 #define SRC_CTRL_MEGA_SW_RESET_MASK              (0x1U)
89117 #define SRC_CTRL_MEGA_SW_RESET_SHIFT             (0U)
89118 /*! SW_RESET
89119  *  0b0..do not assert slice software reset
89120  *  0b1..assert slice software reset
89121  */
89122 #define SRC_CTRL_MEGA_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)
89123 /*! @} */
89124 
89125 /*! @name SETPOINT_MEGA - Slice Setpoint Config Register */
89126 /*! @{ */
89127 
89128 #define SRC_SETPOINT_MEGA_SETPOINT0_MASK         (0x1U)
89129 #define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT        (0U)
89130 /*! SETPOINT0 - SETPOINT0
89131  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89132  *  0b1..Slice reset will be asserted when system in Setpoint n
89133  */
89134 #define SRC_SETPOINT_MEGA_SETPOINT0(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)
89135 
89136 #define SRC_SETPOINT_MEGA_SETPOINT1_MASK         (0x2U)
89137 #define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT        (1U)
89138 /*! SETPOINT1 - SETPOINT1
89139  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89140  *  0b1..Slice reset will be asserted when system in Setpoint n
89141  */
89142 #define SRC_SETPOINT_MEGA_SETPOINT1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)
89143 
89144 #define SRC_SETPOINT_MEGA_SETPOINT2_MASK         (0x4U)
89145 #define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT        (2U)
89146 /*! SETPOINT2 - SETPOINT2
89147  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89148  *  0b1..Slice reset will be asserted when system in Setpoint n
89149  */
89150 #define SRC_SETPOINT_MEGA_SETPOINT2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)
89151 
89152 #define SRC_SETPOINT_MEGA_SETPOINT3_MASK         (0x8U)
89153 #define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT        (3U)
89154 /*! SETPOINT3 - SETPOINT3
89155  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89156  *  0b1..Slice reset will be asserted when system in Setpoint n
89157  */
89158 #define SRC_SETPOINT_MEGA_SETPOINT3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)
89159 
89160 #define SRC_SETPOINT_MEGA_SETPOINT4_MASK         (0x10U)
89161 #define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT        (4U)
89162 /*! SETPOINT4 - SETPOINT4
89163  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89164  *  0b1..Slice reset will be asserted when system in Setpoint n
89165  */
89166 #define SRC_SETPOINT_MEGA_SETPOINT4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)
89167 
89168 #define SRC_SETPOINT_MEGA_SETPOINT5_MASK         (0x20U)
89169 #define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT        (5U)
89170 /*! SETPOINT5 - SETPOINT5
89171  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89172  *  0b1..Slice reset will be asserted when system in Setpoint n
89173  */
89174 #define SRC_SETPOINT_MEGA_SETPOINT5(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)
89175 
89176 #define SRC_SETPOINT_MEGA_SETPOINT6_MASK         (0x40U)
89177 #define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT        (6U)
89178 /*! SETPOINT6 - SETPOINT6
89179  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89180  *  0b1..Slice reset will be asserted when system in Setpoint n
89181  */
89182 #define SRC_SETPOINT_MEGA_SETPOINT6(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)
89183 
89184 #define SRC_SETPOINT_MEGA_SETPOINT7_MASK         (0x80U)
89185 #define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT        (7U)
89186 /*! SETPOINT7 - SETPOINT7
89187  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89188  *  0b1..Slice reset will be asserted when system in Setpoint n
89189  */
89190 #define SRC_SETPOINT_MEGA_SETPOINT7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)
89191 
89192 #define SRC_SETPOINT_MEGA_SETPOINT8_MASK         (0x100U)
89193 #define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT        (8U)
89194 /*! SETPOINT8 - SETPOINT8
89195  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89196  *  0b1..Slice reset will be asserted when system in Setpoint n
89197  */
89198 #define SRC_SETPOINT_MEGA_SETPOINT8(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)
89199 
89200 #define SRC_SETPOINT_MEGA_SETPOINT9_MASK         (0x200U)
89201 #define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT        (9U)
89202 /*! SETPOINT9 - SETPOINT9
89203  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89204  *  0b1..Slice reset will be asserted when system in Setpoint n
89205  */
89206 #define SRC_SETPOINT_MEGA_SETPOINT9(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)
89207 
89208 #define SRC_SETPOINT_MEGA_SETPOINT10_MASK        (0x400U)
89209 #define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT       (10U)
89210 /*! SETPOINT10 - SETPOINT10
89211  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89212  *  0b1..Slice reset will be asserted when system in Setpoint n
89213  */
89214 #define SRC_SETPOINT_MEGA_SETPOINT10(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)
89215 
89216 #define SRC_SETPOINT_MEGA_SETPOINT11_MASK        (0x800U)
89217 #define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT       (11U)
89218 /*! SETPOINT11 - SETPOINT11
89219  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89220  *  0b1..Slice reset will be asserted when system in Setpoint n
89221  */
89222 #define SRC_SETPOINT_MEGA_SETPOINT11(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)
89223 
89224 #define SRC_SETPOINT_MEGA_SETPOINT12_MASK        (0x1000U)
89225 #define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT       (12U)
89226 /*! SETPOINT12 - SETPOINT12
89227  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89228  *  0b1..Slice reset will be asserted when system in Setpoint n
89229  */
89230 #define SRC_SETPOINT_MEGA_SETPOINT12(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)
89231 
89232 #define SRC_SETPOINT_MEGA_SETPOINT13_MASK        (0x2000U)
89233 #define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT       (13U)
89234 /*! SETPOINT13 - SETPOINT13
89235  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89236  *  0b1..Slice reset will be asserted when system in Setpoint n
89237  */
89238 #define SRC_SETPOINT_MEGA_SETPOINT13(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)
89239 
89240 #define SRC_SETPOINT_MEGA_SETPOINT14_MASK        (0x4000U)
89241 #define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT       (14U)
89242 /*! SETPOINT14 - SETPOINT14
89243  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89244  *  0b1..Slice reset will be asserted when system in Setpoint n
89245  */
89246 #define SRC_SETPOINT_MEGA_SETPOINT14(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)
89247 
89248 #define SRC_SETPOINT_MEGA_SETPOINT15_MASK        (0x8000U)
89249 #define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT       (15U)
89250 /*! SETPOINT15 - SETPOINT15
89251  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89252  *  0b1..Slice reset will be asserted when system in Setpoint n
89253  */
89254 #define SRC_SETPOINT_MEGA_SETPOINT15(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)
89255 /*! @} */
89256 
89257 /*! @name DOMAIN_MEGA - Slice Domain Config Register */
89258 /*! @{ */
89259 
89260 #define SRC_DOMAIN_MEGA_CPU0_RUN_MASK            (0x1U)
89261 #define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT           (0U)
89262 /*! CPU0_RUN - CPU mode setting for RUN
89263  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89264  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89265  */
89266 #define SRC_DOMAIN_MEGA_CPU0_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)
89267 
89268 #define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK           (0x2U)
89269 #define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT          (1U)
89270 /*! CPU0_WAIT - CPU mode setting for WAIT
89271  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89272  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89273  */
89274 #define SRC_DOMAIN_MEGA_CPU0_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)
89275 
89276 #define SRC_DOMAIN_MEGA_CPU0_STOP_MASK           (0x4U)
89277 #define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT          (2U)
89278 /*! CPU0_STOP - CPU mode setting for STOP
89279  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89280  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89281  */
89282 #define SRC_DOMAIN_MEGA_CPU0_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)
89283 
89284 #define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK           (0x8U)
89285 #define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT          (3U)
89286 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89287  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89288  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89289  */
89290 #define SRC_DOMAIN_MEGA_CPU0_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)
89291 
89292 #define SRC_DOMAIN_MEGA_CPU1_RUN_MASK            (0x10U)
89293 #define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT           (4U)
89294 /*! CPU1_RUN - CPU mode setting for RUN
89295  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89296  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89297  */
89298 #define SRC_DOMAIN_MEGA_CPU1_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)
89299 
89300 #define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK           (0x20U)
89301 #define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT          (5U)
89302 /*! CPU1_WAIT - CPU mode setting for WAIT
89303  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89304  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89305  */
89306 #define SRC_DOMAIN_MEGA_CPU1_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)
89307 
89308 #define SRC_DOMAIN_MEGA_CPU1_STOP_MASK           (0x40U)
89309 #define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT          (6U)
89310 /*! CPU1_STOP - CPU mode setting for STOP
89311  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89312  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89313  */
89314 #define SRC_DOMAIN_MEGA_CPU1_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)
89315 
89316 #define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK           (0x80U)
89317 #define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT          (7U)
89318 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89319  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89320  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89321  */
89322 #define SRC_DOMAIN_MEGA_CPU1_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)
89323 /*! @} */
89324 
89325 /*! @name STAT_MEGA - Slice Status Register */
89326 /*! @{ */
89327 
89328 #define SRC_STAT_MEGA_UNDER_RST_MASK             (0x1U)
89329 #define SRC_STAT_MEGA_UNDER_RST_SHIFT            (0U)
89330 /*! UNDER_RST
89331  *  0b0..the reset is finished
89332  *  0b1..the reset is in process
89333  */
89334 #define SRC_STAT_MEGA_UNDER_RST(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)
89335 
89336 #define SRC_STAT_MEGA_RST_BY_HW_MASK             (0x4U)
89337 #define SRC_STAT_MEGA_RST_BY_HW_SHIFT            (2U)
89338 /*! RST_BY_HW
89339  *  0b0..the reset is not caused by the power mode transfer
89340  *  0b1..the reset is caused by the power mode transfer
89341  */
89342 #define SRC_STAT_MEGA_RST_BY_HW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)
89343 
89344 #define SRC_STAT_MEGA_RST_BY_SW_MASK             (0x8U)
89345 #define SRC_STAT_MEGA_RST_BY_SW_SHIFT            (3U)
89346 /*! RST_BY_SW
89347  *  0b0..the reset is not caused by software setting
89348  *  0b1..the reset is caused by software setting
89349  */
89350 #define SRC_STAT_MEGA_RST_BY_SW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)
89351 /*! @} */
89352 
89353 /*! @name AUTHEN_DISPLAY - Slice Authentication Register */
89354 /*! @{ */
89355 
89356 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK      (0x1U)
89357 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT     (0U)
89358 /*! DOMAIN_MODE
89359  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89360  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89361  */
89362 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)
89363 
89364 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK    (0x2U)
89365 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT   (1U)
89366 /*! SETPOINT_MODE
89367  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89368  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89369  */
89370 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)
89371 
89372 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK        (0x80U)
89373 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT       (7U)
89374 /*! LOCK_MODE - Domain/Setpoint mode lock
89375  */
89376 #define SRC_AUTHEN_DISPLAY_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)
89377 
89378 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK      (0xF00U)
89379 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT     (8U)
89380 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)
89381 
89382 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK      (0x8000U)
89383 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT     (15U)
89384 /*! LOCK_ASSIGN - Assign list lock
89385  */
89386 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)
89387 
89388 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK       (0xF0000U)
89389 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT      (16U)
89390 /*! WHITE_LIST - Domain ID white list
89391  */
89392 #define SRC_AUTHEN_DISPLAY_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)
89393 
89394 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK        (0x800000U)
89395 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT       (23U)
89396 /*! LOCK_LIST - White list lock
89397  */
89398 #define SRC_AUTHEN_DISPLAY_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)
89399 
89400 #define SRC_AUTHEN_DISPLAY_USER_MASK             (0x1000000U)
89401 #define SRC_AUTHEN_DISPLAY_USER_SHIFT            (24U)
89402 /*! USER - Allow user mode access
89403  */
89404 #define SRC_AUTHEN_DISPLAY_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)
89405 
89406 #define SRC_AUTHEN_DISPLAY_NONSECURE_MASK        (0x2000000U)
89407 #define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT       (25U)
89408 /*! NONSECURE - Allow non-secure mode access
89409  */
89410 #define SRC_AUTHEN_DISPLAY_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)
89411 
89412 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK     (0x80000000U)
89413 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT    (31U)
89414 /*! LOCK_SETTING - Lock NONSECURE and USER
89415  */
89416 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)
89417 /*! @} */
89418 
89419 /*! @name CTRL_DISPLAY - Slice Control Register */
89420 /*! @{ */
89421 
89422 #define SRC_CTRL_DISPLAY_SW_RESET_MASK           (0x1U)
89423 #define SRC_CTRL_DISPLAY_SW_RESET_SHIFT          (0U)
89424 /*! SW_RESET
89425  *  0b0..do not assert slice software reset
89426  *  0b1..assert slice software reset
89427  */
89428 #define SRC_CTRL_DISPLAY_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)
89429 /*! @} */
89430 
89431 /*! @name SETPOINT_DISPLAY - Slice Setpoint Config Register */
89432 /*! @{ */
89433 
89434 #define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK      (0x1U)
89435 #define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT     (0U)
89436 /*! SETPOINT0 - SETPOINT0
89437  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89438  *  0b1..Slice reset will be asserted when system in Setpoint n
89439  */
89440 #define SRC_SETPOINT_DISPLAY_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)
89441 
89442 #define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK      (0x2U)
89443 #define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT     (1U)
89444 /*! SETPOINT1 - SETPOINT1
89445  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89446  *  0b1..Slice reset will be asserted when system in Setpoint n
89447  */
89448 #define SRC_SETPOINT_DISPLAY_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)
89449 
89450 #define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK      (0x4U)
89451 #define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT     (2U)
89452 /*! SETPOINT2 - SETPOINT2
89453  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89454  *  0b1..Slice reset will be asserted when system in Setpoint n
89455  */
89456 #define SRC_SETPOINT_DISPLAY_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)
89457 
89458 #define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK      (0x8U)
89459 #define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT     (3U)
89460 /*! SETPOINT3 - SETPOINT3
89461  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89462  *  0b1..Slice reset will be asserted when system in Setpoint n
89463  */
89464 #define SRC_SETPOINT_DISPLAY_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)
89465 
89466 #define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK      (0x10U)
89467 #define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT     (4U)
89468 /*! SETPOINT4 - SETPOINT4
89469  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89470  *  0b1..Slice reset will be asserted when system in Setpoint n
89471  */
89472 #define SRC_SETPOINT_DISPLAY_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)
89473 
89474 #define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK      (0x20U)
89475 #define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT     (5U)
89476 /*! SETPOINT5 - SETPOINT5
89477  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89478  *  0b1..Slice reset will be asserted when system in Setpoint n
89479  */
89480 #define SRC_SETPOINT_DISPLAY_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)
89481 
89482 #define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK      (0x40U)
89483 #define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT     (6U)
89484 /*! SETPOINT6 - SETPOINT6
89485  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89486  *  0b1..Slice reset will be asserted when system in Setpoint n
89487  */
89488 #define SRC_SETPOINT_DISPLAY_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)
89489 
89490 #define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK      (0x80U)
89491 #define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT     (7U)
89492 /*! SETPOINT7 - SETPOINT7
89493  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89494  *  0b1..Slice reset will be asserted when system in Setpoint n
89495  */
89496 #define SRC_SETPOINT_DISPLAY_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)
89497 
89498 #define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK      (0x100U)
89499 #define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT     (8U)
89500 /*! SETPOINT8 - SETPOINT8
89501  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89502  *  0b1..Slice reset will be asserted when system in Setpoint n
89503  */
89504 #define SRC_SETPOINT_DISPLAY_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)
89505 
89506 #define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK      (0x200U)
89507 #define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT     (9U)
89508 /*! SETPOINT9 - SETPOINT9
89509  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89510  *  0b1..Slice reset will be asserted when system in Setpoint n
89511  */
89512 #define SRC_SETPOINT_DISPLAY_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)
89513 
89514 #define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK     (0x400U)
89515 #define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT    (10U)
89516 /*! SETPOINT10 - SETPOINT10
89517  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89518  *  0b1..Slice reset will be asserted when system in Setpoint n
89519  */
89520 #define SRC_SETPOINT_DISPLAY_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)
89521 
89522 #define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK     (0x800U)
89523 #define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT    (11U)
89524 /*! SETPOINT11 - SETPOINT11
89525  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89526  *  0b1..Slice reset will be asserted when system in Setpoint n
89527  */
89528 #define SRC_SETPOINT_DISPLAY_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)
89529 
89530 #define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK     (0x1000U)
89531 #define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT    (12U)
89532 /*! SETPOINT12 - SETPOINT12
89533  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89534  *  0b1..Slice reset will be asserted when system in Setpoint n
89535  */
89536 #define SRC_SETPOINT_DISPLAY_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)
89537 
89538 #define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK     (0x2000U)
89539 #define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT    (13U)
89540 /*! SETPOINT13 - SETPOINT13
89541  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89542  *  0b1..Slice reset will be asserted when system in Setpoint n
89543  */
89544 #define SRC_SETPOINT_DISPLAY_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)
89545 
89546 #define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK     (0x4000U)
89547 #define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT    (14U)
89548 /*! SETPOINT14 - SETPOINT14
89549  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89550  *  0b1..Slice reset will be asserted when system in Setpoint n
89551  */
89552 #define SRC_SETPOINT_DISPLAY_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)
89553 
89554 #define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK     (0x8000U)
89555 #define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT    (15U)
89556 /*! SETPOINT15 - SETPOINT15
89557  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89558  *  0b1..Slice reset will be asserted when system in Setpoint n
89559  */
89560 #define SRC_SETPOINT_DISPLAY_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)
89561 /*! @} */
89562 
89563 /*! @name DOMAIN_DISPLAY - Slice Domain Config Register */
89564 /*! @{ */
89565 
89566 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK         (0x1U)
89567 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT        (0U)
89568 /*! CPU0_RUN - CPU mode setting for RUN
89569  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89570  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89571  */
89572 #define SRC_DOMAIN_DISPLAY_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)
89573 
89574 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK        (0x2U)
89575 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT       (1U)
89576 /*! CPU0_WAIT - CPU mode setting for WAIT
89577  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89578  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89579  */
89580 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)
89581 
89582 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK        (0x4U)
89583 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT       (2U)
89584 /*! CPU0_STOP - CPU mode setting for STOP
89585  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89586  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89587  */
89588 #define SRC_DOMAIN_DISPLAY_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)
89589 
89590 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK        (0x8U)
89591 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT       (3U)
89592 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89593  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89594  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89595  */
89596 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)
89597 
89598 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK         (0x10U)
89599 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT        (4U)
89600 /*! CPU1_RUN - CPU mode setting for RUN
89601  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89602  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89603  */
89604 #define SRC_DOMAIN_DISPLAY_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)
89605 
89606 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK        (0x20U)
89607 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT       (5U)
89608 /*! CPU1_WAIT - CPU mode setting for WAIT
89609  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89610  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89611  */
89612 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)
89613 
89614 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK        (0x40U)
89615 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT       (6U)
89616 /*! CPU1_STOP - CPU mode setting for STOP
89617  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89618  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89619  */
89620 #define SRC_DOMAIN_DISPLAY_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)
89621 
89622 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK        (0x80U)
89623 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT       (7U)
89624 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89625  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89626  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89627  */
89628 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)
89629 /*! @} */
89630 
89631 /*! @name STAT_DISPLAY - Slice Status Register */
89632 /*! @{ */
89633 
89634 #define SRC_STAT_DISPLAY_UNDER_RST_MASK          (0x1U)
89635 #define SRC_STAT_DISPLAY_UNDER_RST_SHIFT         (0U)
89636 /*! UNDER_RST
89637  *  0b0..the reset is finished
89638  *  0b1..the reset is in process
89639  */
89640 #define SRC_STAT_DISPLAY_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)
89641 
89642 #define SRC_STAT_DISPLAY_RST_BY_HW_MASK          (0x4U)
89643 #define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT         (2U)
89644 /*! RST_BY_HW
89645  *  0b0..the reset is not caused by the power mode transfer
89646  *  0b1..the reset is caused by the power mode transfer
89647  */
89648 #define SRC_STAT_DISPLAY_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)
89649 
89650 #define SRC_STAT_DISPLAY_RST_BY_SW_MASK          (0x8U)
89651 #define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT         (3U)
89652 /*! RST_BY_SW
89653  *  0b0..the reset is not caused by software setting
89654  *  0b1..the reset is caused by software setting
89655  */
89656 #define SRC_STAT_DISPLAY_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)
89657 /*! @} */
89658 
89659 /*! @name AUTHEN_WAKEUP - Slice Authentication Register */
89660 /*! @{ */
89661 
89662 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK       (0x1U)
89663 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT      (0U)
89664 /*! DOMAIN_MODE
89665  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89666  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89667  */
89668 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)
89669 
89670 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK     (0x2U)
89671 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT    (1U)
89672 /*! SETPOINT_MODE
89673  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89674  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89675  */
89676 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)
89677 
89678 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK         (0x80U)
89679 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT        (7U)
89680 /*! LOCK_MODE - Domain/Setpoint mode lock
89681  */
89682 #define SRC_AUTHEN_WAKEUP_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)
89683 
89684 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK       (0xF00U)
89685 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT      (8U)
89686 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)
89687 
89688 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK       (0x8000U)
89689 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT      (15U)
89690 /*! LOCK_ASSIGN - Assign list lock
89691  */
89692 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)
89693 
89694 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK        (0xF0000U)
89695 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT       (16U)
89696 /*! WHITE_LIST - Domain ID white list
89697  */
89698 #define SRC_AUTHEN_WAKEUP_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)
89699 
89700 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK         (0x800000U)
89701 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT        (23U)
89702 /*! LOCK_LIST - White list lock
89703  */
89704 #define SRC_AUTHEN_WAKEUP_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)
89705 
89706 #define SRC_AUTHEN_WAKEUP_USER_MASK              (0x1000000U)
89707 #define SRC_AUTHEN_WAKEUP_USER_SHIFT             (24U)
89708 /*! USER - Allow user mode access
89709  */
89710 #define SRC_AUTHEN_WAKEUP_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)
89711 
89712 #define SRC_AUTHEN_WAKEUP_NONSECURE_MASK         (0x2000000U)
89713 #define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT        (25U)
89714 /*! NONSECURE - Allow non-secure mode access
89715  */
89716 #define SRC_AUTHEN_WAKEUP_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)
89717 
89718 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK      (0x80000000U)
89719 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT     (31U)
89720 /*! LOCK_SETTING - Lock NONSECURE and USER
89721  */
89722 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)
89723 /*! @} */
89724 
89725 /*! @name CTRL_WAKEUP - Slice Control Register */
89726 /*! @{ */
89727 
89728 #define SRC_CTRL_WAKEUP_SW_RESET_MASK            (0x1U)
89729 #define SRC_CTRL_WAKEUP_SW_RESET_SHIFT           (0U)
89730 /*! SW_RESET
89731  *  0b0..do not assert slice software reset
89732  *  0b1..assert slice software reset
89733  */
89734 #define SRC_CTRL_WAKEUP_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)
89735 /*! @} */
89736 
89737 /*! @name SETPOINT_WAKEUP - Slice Setpoint Config Register */
89738 /*! @{ */
89739 
89740 #define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK       (0x1U)
89741 #define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT      (0U)
89742 /*! SETPOINT0 - SETPOINT0
89743  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89744  *  0b1..Slice reset will be asserted when system in Setpoint n
89745  */
89746 #define SRC_SETPOINT_WAKEUP_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)
89747 
89748 #define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK       (0x2U)
89749 #define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT      (1U)
89750 /*! SETPOINT1 - SETPOINT1
89751  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89752  *  0b1..Slice reset will be asserted when system in Setpoint n
89753  */
89754 #define SRC_SETPOINT_WAKEUP_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)
89755 
89756 #define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK       (0x4U)
89757 #define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT      (2U)
89758 /*! SETPOINT2 - SETPOINT2
89759  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89760  *  0b1..Slice reset will be asserted when system in Setpoint n
89761  */
89762 #define SRC_SETPOINT_WAKEUP_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)
89763 
89764 #define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK       (0x8U)
89765 #define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT      (3U)
89766 /*! SETPOINT3 - SETPOINT3
89767  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89768  *  0b1..Slice reset will be asserted when system in Setpoint n
89769  */
89770 #define SRC_SETPOINT_WAKEUP_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)
89771 
89772 #define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK       (0x10U)
89773 #define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT      (4U)
89774 /*! SETPOINT4 - SETPOINT4
89775  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89776  *  0b1..Slice reset will be asserted when system in Setpoint n
89777  */
89778 #define SRC_SETPOINT_WAKEUP_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)
89779 
89780 #define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK       (0x20U)
89781 #define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT      (5U)
89782 /*! SETPOINT5 - SETPOINT5
89783  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89784  *  0b1..Slice reset will be asserted when system in Setpoint n
89785  */
89786 #define SRC_SETPOINT_WAKEUP_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)
89787 
89788 #define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK       (0x40U)
89789 #define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT      (6U)
89790 /*! SETPOINT6 - SETPOINT6
89791  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89792  *  0b1..Slice reset will be asserted when system in Setpoint n
89793  */
89794 #define SRC_SETPOINT_WAKEUP_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)
89795 
89796 #define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK       (0x80U)
89797 #define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT      (7U)
89798 /*! SETPOINT7 - SETPOINT7
89799  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89800  *  0b1..Slice reset will be asserted when system in Setpoint n
89801  */
89802 #define SRC_SETPOINT_WAKEUP_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)
89803 
89804 #define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK       (0x100U)
89805 #define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT      (8U)
89806 /*! SETPOINT8 - SETPOINT8
89807  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89808  *  0b1..Slice reset will be asserted when system in Setpoint n
89809  */
89810 #define SRC_SETPOINT_WAKEUP_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)
89811 
89812 #define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK       (0x200U)
89813 #define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT      (9U)
89814 /*! SETPOINT9 - SETPOINT9
89815  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89816  *  0b1..Slice reset will be asserted when system in Setpoint n
89817  */
89818 #define SRC_SETPOINT_WAKEUP_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)
89819 
89820 #define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK      (0x400U)
89821 #define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT     (10U)
89822 /*! SETPOINT10 - SETPOINT10
89823  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89824  *  0b1..Slice reset will be asserted when system in Setpoint n
89825  */
89826 #define SRC_SETPOINT_WAKEUP_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)
89827 
89828 #define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK      (0x800U)
89829 #define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT     (11U)
89830 /*! SETPOINT11 - SETPOINT11
89831  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89832  *  0b1..Slice reset will be asserted when system in Setpoint n
89833  */
89834 #define SRC_SETPOINT_WAKEUP_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)
89835 
89836 #define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK      (0x1000U)
89837 #define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT     (12U)
89838 /*! SETPOINT12 - SETPOINT12
89839  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89840  *  0b1..Slice reset will be asserted when system in Setpoint n
89841  */
89842 #define SRC_SETPOINT_WAKEUP_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)
89843 
89844 #define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK      (0x2000U)
89845 #define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT     (13U)
89846 /*! SETPOINT13 - SETPOINT13
89847  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89848  *  0b1..Slice reset will be asserted when system in Setpoint n
89849  */
89850 #define SRC_SETPOINT_WAKEUP_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)
89851 
89852 #define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK      (0x4000U)
89853 #define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT     (14U)
89854 /*! SETPOINT14 - SETPOINT14
89855  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89856  *  0b1..Slice reset will be asserted when system in Setpoint n
89857  */
89858 #define SRC_SETPOINT_WAKEUP_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)
89859 
89860 #define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK      (0x8000U)
89861 #define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT     (15U)
89862 /*! SETPOINT15 - SETPOINT15
89863  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89864  *  0b1..Slice reset will be asserted when system in Setpoint n
89865  */
89866 #define SRC_SETPOINT_WAKEUP_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)
89867 /*! @} */
89868 
89869 /*! @name DOMAIN_WAKEUP - Slice Domain Config Register */
89870 /*! @{ */
89871 
89872 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK          (0x1U)
89873 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT         (0U)
89874 /*! CPU0_RUN - CPU mode setting for RUN
89875  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89876  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89877  */
89878 #define SRC_DOMAIN_WAKEUP_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)
89879 
89880 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK         (0x2U)
89881 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT        (1U)
89882 /*! CPU0_WAIT - CPU mode setting for WAIT
89883  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89884  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89885  */
89886 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)
89887 
89888 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK         (0x4U)
89889 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT        (2U)
89890 /*! CPU0_STOP - CPU mode setting for STOP
89891  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89892  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89893  */
89894 #define SRC_DOMAIN_WAKEUP_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)
89895 
89896 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK         (0x8U)
89897 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT        (3U)
89898 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89899  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89900  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89901  */
89902 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)
89903 
89904 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK          (0x10U)
89905 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT         (4U)
89906 /*! CPU1_RUN - CPU mode setting for RUN
89907  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89908  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89909  */
89910 #define SRC_DOMAIN_WAKEUP_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)
89911 
89912 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK         (0x20U)
89913 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT        (5U)
89914 /*! CPU1_WAIT - CPU mode setting for WAIT
89915  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89916  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89917  */
89918 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)
89919 
89920 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK         (0x40U)
89921 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT        (6U)
89922 /*! CPU1_STOP - CPU mode setting for STOP
89923  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89924  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89925  */
89926 #define SRC_DOMAIN_WAKEUP_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)
89927 
89928 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK         (0x80U)
89929 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT        (7U)
89930 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89931  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89932  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89933  */
89934 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)
89935 /*! @} */
89936 
89937 /*! @name STAT_WAKEUP - Slice Status Register */
89938 /*! @{ */
89939 
89940 #define SRC_STAT_WAKEUP_UNDER_RST_MASK           (0x1U)
89941 #define SRC_STAT_WAKEUP_UNDER_RST_SHIFT          (0U)
89942 /*! UNDER_RST
89943  *  0b0..the reset is finished
89944  *  0b1..the reset is in process
89945  */
89946 #define SRC_STAT_WAKEUP_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)
89947 
89948 #define SRC_STAT_WAKEUP_RST_BY_HW_MASK           (0x4U)
89949 #define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT          (2U)
89950 /*! RST_BY_HW
89951  *  0b0..the reset is not caused by the power mode transfer
89952  *  0b1..the reset is caused by the power mode transfer
89953  */
89954 #define SRC_STAT_WAKEUP_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)
89955 
89956 #define SRC_STAT_WAKEUP_RST_BY_SW_MASK           (0x8U)
89957 #define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT          (3U)
89958 /*! RST_BY_SW
89959  *  0b0..the reset is not caused by software setting
89960  *  0b1..the reset is caused by software setting
89961  */
89962 #define SRC_STAT_WAKEUP_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)
89963 /*! @} */
89964 
89965 /*! @name AUTHEN_M4CORE - Slice Authentication Register */
89966 /*! @{ */
89967 
89968 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK       (0x1U)
89969 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT      (0U)
89970 /*! DOMAIN_MODE
89971  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89972  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89973  */
89974 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)
89975 
89976 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK     (0x2U)
89977 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT    (1U)
89978 /*! SETPOINT_MODE
89979  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89980  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89981  */
89982 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)
89983 
89984 #define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK         (0x80U)
89985 #define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT        (7U)
89986 /*! LOCK_MODE - Domain/Setpoint mode lock
89987  */
89988 #define SRC_AUTHEN_M4CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)
89989 
89990 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK       (0xF00U)
89991 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT      (8U)
89992 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)
89993 
89994 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK       (0x8000U)
89995 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT      (15U)
89996 /*! LOCK_ASSIGN - Assign list lock
89997  */
89998 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)
89999 
90000 #define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK        (0xF0000U)
90001 #define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT       (16U)
90002 /*! WHITE_LIST - Domain ID white list
90003  */
90004 #define SRC_AUTHEN_M4CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)
90005 
90006 #define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK         (0x800000U)
90007 #define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT        (23U)
90008 /*! LOCK_LIST - White list lock
90009  */
90010 #define SRC_AUTHEN_M4CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)
90011 
90012 #define SRC_AUTHEN_M4CORE_USER_MASK              (0x1000000U)
90013 #define SRC_AUTHEN_M4CORE_USER_SHIFT             (24U)
90014 /*! USER - Allow user mode access
90015  */
90016 #define SRC_AUTHEN_M4CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)
90017 
90018 #define SRC_AUTHEN_M4CORE_NONSECURE_MASK         (0x2000000U)
90019 #define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT        (25U)
90020 /*! NONSECURE - Allow non-secure mode access
90021  */
90022 #define SRC_AUTHEN_M4CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)
90023 
90024 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK      (0x80000000U)
90025 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT     (31U)
90026 /*! LOCK_SETTING - Lock NONSECURE and USER
90027  */
90028 #define SRC_AUTHEN_M4CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)
90029 /*! @} */
90030 
90031 /*! @name CTRL_M4CORE - Slice Control Register */
90032 /*! @{ */
90033 
90034 #define SRC_CTRL_M4CORE_SW_RESET_MASK            (0x1U)
90035 #define SRC_CTRL_M4CORE_SW_RESET_SHIFT           (0U)
90036 /*! SW_RESET
90037  *  0b0..do not assert slice software reset
90038  *  0b1..assert slice software reset
90039  */
90040 #define SRC_CTRL_M4CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)
90041 /*! @} */
90042 
90043 /*! @name SETPOINT_M4CORE - Slice Setpoint Config Register */
90044 /*! @{ */
90045 
90046 #define SRC_SETPOINT_M4CORE_SETPOINT0_MASK       (0x1U)
90047 #define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT      (0U)
90048 /*! SETPOINT0 - SETPOINT0
90049  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90050  *  0b1..Slice reset will be asserted when system in Setpoint n
90051  */
90052 #define SRC_SETPOINT_M4CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)
90053 
90054 #define SRC_SETPOINT_M4CORE_SETPOINT1_MASK       (0x2U)
90055 #define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT      (1U)
90056 /*! SETPOINT1 - SETPOINT1
90057  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90058  *  0b1..Slice reset will be asserted when system in Setpoint n
90059  */
90060 #define SRC_SETPOINT_M4CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)
90061 
90062 #define SRC_SETPOINT_M4CORE_SETPOINT2_MASK       (0x4U)
90063 #define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT      (2U)
90064 /*! SETPOINT2 - SETPOINT2
90065  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90066  *  0b1..Slice reset will be asserted when system in Setpoint n
90067  */
90068 #define SRC_SETPOINT_M4CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)
90069 
90070 #define SRC_SETPOINT_M4CORE_SETPOINT3_MASK       (0x8U)
90071 #define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT      (3U)
90072 /*! SETPOINT3 - SETPOINT3
90073  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90074  *  0b1..Slice reset will be asserted when system in Setpoint n
90075  */
90076 #define SRC_SETPOINT_M4CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)
90077 
90078 #define SRC_SETPOINT_M4CORE_SETPOINT4_MASK       (0x10U)
90079 #define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT      (4U)
90080 /*! SETPOINT4 - SETPOINT4
90081  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90082  *  0b1..Slice reset will be asserted when system in Setpoint n
90083  */
90084 #define SRC_SETPOINT_M4CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)
90085 
90086 #define SRC_SETPOINT_M4CORE_SETPOINT5_MASK       (0x20U)
90087 #define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT      (5U)
90088 /*! SETPOINT5 - SETPOINT5
90089  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90090  *  0b1..Slice reset will be asserted when system in Setpoint n
90091  */
90092 #define SRC_SETPOINT_M4CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)
90093 
90094 #define SRC_SETPOINT_M4CORE_SETPOINT6_MASK       (0x40U)
90095 #define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT      (6U)
90096 /*! SETPOINT6 - SETPOINT6
90097  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90098  *  0b1..Slice reset will be asserted when system in Setpoint n
90099  */
90100 #define SRC_SETPOINT_M4CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)
90101 
90102 #define SRC_SETPOINT_M4CORE_SETPOINT7_MASK       (0x80U)
90103 #define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT      (7U)
90104 /*! SETPOINT7 - SETPOINT7
90105  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90106  *  0b1..Slice reset will be asserted when system in Setpoint n
90107  */
90108 #define SRC_SETPOINT_M4CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)
90109 
90110 #define SRC_SETPOINT_M4CORE_SETPOINT8_MASK       (0x100U)
90111 #define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT      (8U)
90112 /*! SETPOINT8 - SETPOINT8
90113  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90114  *  0b1..Slice reset will be asserted when system in Setpoint n
90115  */
90116 #define SRC_SETPOINT_M4CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)
90117 
90118 #define SRC_SETPOINT_M4CORE_SETPOINT9_MASK       (0x200U)
90119 #define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT      (9U)
90120 /*! SETPOINT9 - SETPOINT9
90121  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90122  *  0b1..Slice reset will be asserted when system in Setpoint n
90123  */
90124 #define SRC_SETPOINT_M4CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)
90125 
90126 #define SRC_SETPOINT_M4CORE_SETPOINT10_MASK      (0x400U)
90127 #define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT     (10U)
90128 /*! SETPOINT10 - SETPOINT10
90129  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90130  *  0b1..Slice reset will be asserted when system in Setpoint n
90131  */
90132 #define SRC_SETPOINT_M4CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)
90133 
90134 #define SRC_SETPOINT_M4CORE_SETPOINT11_MASK      (0x800U)
90135 #define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT     (11U)
90136 /*! SETPOINT11 - SETPOINT11
90137  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90138  *  0b1..Slice reset will be asserted when system in Setpoint n
90139  */
90140 #define SRC_SETPOINT_M4CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)
90141 
90142 #define SRC_SETPOINT_M4CORE_SETPOINT12_MASK      (0x1000U)
90143 #define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT     (12U)
90144 /*! SETPOINT12 - SETPOINT12
90145  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90146  *  0b1..Slice reset will be asserted when system in Setpoint n
90147  */
90148 #define SRC_SETPOINT_M4CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)
90149 
90150 #define SRC_SETPOINT_M4CORE_SETPOINT13_MASK      (0x2000U)
90151 #define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT     (13U)
90152 /*! SETPOINT13 - SETPOINT13
90153  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90154  *  0b1..Slice reset will be asserted when system in Setpoint n
90155  */
90156 #define SRC_SETPOINT_M4CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)
90157 
90158 #define SRC_SETPOINT_M4CORE_SETPOINT14_MASK      (0x4000U)
90159 #define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT     (14U)
90160 /*! SETPOINT14 - SETPOINT14
90161  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90162  *  0b1..Slice reset will be asserted when system in Setpoint n
90163  */
90164 #define SRC_SETPOINT_M4CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)
90165 
90166 #define SRC_SETPOINT_M4CORE_SETPOINT15_MASK      (0x8000U)
90167 #define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT     (15U)
90168 /*! SETPOINT15 - SETPOINT15
90169  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90170  *  0b1..Slice reset will be asserted when system in Setpoint n
90171  */
90172 #define SRC_SETPOINT_M4CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)
90173 /*! @} */
90174 
90175 /*! @name DOMAIN_M4CORE - Slice Domain Config Register */
90176 /*! @{ */
90177 
90178 #define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK          (0x1U)
90179 #define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT         (0U)
90180 /*! CPU0_RUN - CPU mode setting for RUN
90181  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90182  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90183  */
90184 #define SRC_DOMAIN_M4CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)
90185 
90186 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK         (0x2U)
90187 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT        (1U)
90188 /*! CPU0_WAIT - CPU mode setting for WAIT
90189  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90190  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90191  */
90192 #define SRC_DOMAIN_M4CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)
90193 
90194 #define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK         (0x4U)
90195 #define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT        (2U)
90196 /*! CPU0_STOP - CPU mode setting for STOP
90197  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90198  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90199  */
90200 #define SRC_DOMAIN_M4CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)
90201 
90202 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK         (0x8U)
90203 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT        (3U)
90204 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90205  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90206  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90207  */
90208 #define SRC_DOMAIN_M4CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)
90209 
90210 #define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK          (0x10U)
90211 #define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT         (4U)
90212 /*! CPU1_RUN - CPU mode setting for RUN
90213  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90214  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90215  */
90216 #define SRC_DOMAIN_M4CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)
90217 
90218 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK         (0x20U)
90219 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT        (5U)
90220 /*! CPU1_WAIT - CPU mode setting for WAIT
90221  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90222  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90223  */
90224 #define SRC_DOMAIN_M4CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)
90225 
90226 #define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK         (0x40U)
90227 #define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT        (6U)
90228 /*! CPU1_STOP - CPU mode setting for STOP
90229  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90230  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90231  */
90232 #define SRC_DOMAIN_M4CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)
90233 
90234 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK         (0x80U)
90235 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT        (7U)
90236 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90237  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90238  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90239  */
90240 #define SRC_DOMAIN_M4CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)
90241 /*! @} */
90242 
90243 /*! @name STAT_M4CORE - Slice Status Register */
90244 /*! @{ */
90245 
90246 #define SRC_STAT_M4CORE_UNDER_RST_MASK           (0x1U)
90247 #define SRC_STAT_M4CORE_UNDER_RST_SHIFT          (0U)
90248 /*! UNDER_RST
90249  *  0b0..the reset is finished
90250  *  0b1..the reset is in process
90251  */
90252 #define SRC_STAT_M4CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)
90253 
90254 #define SRC_STAT_M4CORE_RST_BY_HW_MASK           (0x4U)
90255 #define SRC_STAT_M4CORE_RST_BY_HW_SHIFT          (2U)
90256 /*! RST_BY_HW
90257  *  0b0..the reset is not caused by the power mode transfer
90258  *  0b1..the reset is caused by the power mode transfer
90259  */
90260 #define SRC_STAT_M4CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)
90261 
90262 #define SRC_STAT_M4CORE_RST_BY_SW_MASK           (0x8U)
90263 #define SRC_STAT_M4CORE_RST_BY_SW_SHIFT          (3U)
90264 /*! RST_BY_SW
90265  *  0b0..the reset is not caused by software setting
90266  *  0b1..the reset is caused by software setting
90267  */
90268 #define SRC_STAT_M4CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)
90269 /*! @} */
90270 
90271 /*! @name AUTHEN_M7CORE - Slice Authentication Register */
90272 /*! @{ */
90273 
90274 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK       (0x1U)
90275 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT      (0U)
90276 /*! DOMAIN_MODE
90277  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90278  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90279  */
90280 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)
90281 
90282 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK     (0x2U)
90283 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT    (1U)
90284 /*! SETPOINT_MODE
90285  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90286  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90287  */
90288 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)
90289 
90290 #define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK         (0x80U)
90291 #define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT        (7U)
90292 /*! LOCK_MODE - Domain/Setpoint mode lock
90293  */
90294 #define SRC_AUTHEN_M7CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)
90295 
90296 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK       (0xF00U)
90297 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT      (8U)
90298 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)
90299 
90300 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK       (0x8000U)
90301 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT      (15U)
90302 /*! LOCK_ASSIGN - Assign list lock
90303  */
90304 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)
90305 
90306 #define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK        (0xF0000U)
90307 #define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT       (16U)
90308 /*! WHITE_LIST - Domain ID white list
90309  */
90310 #define SRC_AUTHEN_M7CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)
90311 
90312 #define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK         (0x800000U)
90313 #define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT        (23U)
90314 /*! LOCK_LIST - White list lock
90315  */
90316 #define SRC_AUTHEN_M7CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)
90317 
90318 #define SRC_AUTHEN_M7CORE_USER_MASK              (0x1000000U)
90319 #define SRC_AUTHEN_M7CORE_USER_SHIFT             (24U)
90320 /*! USER - Allow user mode access
90321  */
90322 #define SRC_AUTHEN_M7CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)
90323 
90324 #define SRC_AUTHEN_M7CORE_NONSECURE_MASK         (0x2000000U)
90325 #define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT        (25U)
90326 /*! NONSECURE - Allow non-secure mode access
90327  */
90328 #define SRC_AUTHEN_M7CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)
90329 
90330 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK      (0x80000000U)
90331 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT     (31U)
90332 /*! LOCK_SETTING - Lock NONSECURE and USER
90333  */
90334 #define SRC_AUTHEN_M7CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)
90335 /*! @} */
90336 
90337 /*! @name CTRL_M7CORE - Slice Control Register */
90338 /*! @{ */
90339 
90340 #define SRC_CTRL_M7CORE_SW_RESET_MASK            (0x1U)
90341 #define SRC_CTRL_M7CORE_SW_RESET_SHIFT           (0U)
90342 /*! SW_RESET
90343  *  0b0..do not assert slice software reset
90344  *  0b1..assert slice software reset
90345  */
90346 #define SRC_CTRL_M7CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)
90347 /*! @} */
90348 
90349 /*! @name SETPOINT_M7CORE - Slice Setpoint Config Register */
90350 /*! @{ */
90351 
90352 #define SRC_SETPOINT_M7CORE_SETPOINT0_MASK       (0x1U)
90353 #define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT      (0U)
90354 /*! SETPOINT0 - SETPOINT0
90355  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90356  *  0b1..Slice reset will be asserted when system in Setpoint n
90357  */
90358 #define SRC_SETPOINT_M7CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)
90359 
90360 #define SRC_SETPOINT_M7CORE_SETPOINT1_MASK       (0x2U)
90361 #define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT      (1U)
90362 /*! SETPOINT1 - SETPOINT1
90363  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90364  *  0b1..Slice reset will be asserted when system in Setpoint n
90365  */
90366 #define SRC_SETPOINT_M7CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)
90367 
90368 #define SRC_SETPOINT_M7CORE_SETPOINT2_MASK       (0x4U)
90369 #define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT      (2U)
90370 /*! SETPOINT2 - SETPOINT2
90371  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90372  *  0b1..Slice reset will be asserted when system in Setpoint n
90373  */
90374 #define SRC_SETPOINT_M7CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)
90375 
90376 #define SRC_SETPOINT_M7CORE_SETPOINT3_MASK       (0x8U)
90377 #define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT      (3U)
90378 /*! SETPOINT3 - SETPOINT3
90379  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90380  *  0b1..Slice reset will be asserted when system in Setpoint n
90381  */
90382 #define SRC_SETPOINT_M7CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)
90383 
90384 #define SRC_SETPOINT_M7CORE_SETPOINT4_MASK       (0x10U)
90385 #define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT      (4U)
90386 /*! SETPOINT4 - SETPOINT4
90387  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90388  *  0b1..Slice reset will be asserted when system in Setpoint n
90389  */
90390 #define SRC_SETPOINT_M7CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)
90391 
90392 #define SRC_SETPOINT_M7CORE_SETPOINT5_MASK       (0x20U)
90393 #define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT      (5U)
90394 /*! SETPOINT5 - SETPOINT5
90395  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90396  *  0b1..Slice reset will be asserted when system in Setpoint n
90397  */
90398 #define SRC_SETPOINT_M7CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)
90399 
90400 #define SRC_SETPOINT_M7CORE_SETPOINT6_MASK       (0x40U)
90401 #define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT      (6U)
90402 /*! SETPOINT6 - SETPOINT6
90403  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90404  *  0b1..Slice reset will be asserted when system in Setpoint n
90405  */
90406 #define SRC_SETPOINT_M7CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)
90407 
90408 #define SRC_SETPOINT_M7CORE_SETPOINT7_MASK       (0x80U)
90409 #define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT      (7U)
90410 /*! SETPOINT7 - SETPOINT7
90411  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90412  *  0b1..Slice reset will be asserted when system in Setpoint n
90413  */
90414 #define SRC_SETPOINT_M7CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)
90415 
90416 #define SRC_SETPOINT_M7CORE_SETPOINT8_MASK       (0x100U)
90417 #define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT      (8U)
90418 /*! SETPOINT8 - SETPOINT8
90419  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90420  *  0b1..Slice reset will be asserted when system in Setpoint n
90421  */
90422 #define SRC_SETPOINT_M7CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)
90423 
90424 #define SRC_SETPOINT_M7CORE_SETPOINT9_MASK       (0x200U)
90425 #define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT      (9U)
90426 /*! SETPOINT9 - SETPOINT9
90427  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90428  *  0b1..Slice reset will be asserted when system in Setpoint n
90429  */
90430 #define SRC_SETPOINT_M7CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)
90431 
90432 #define SRC_SETPOINT_M7CORE_SETPOINT10_MASK      (0x400U)
90433 #define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT     (10U)
90434 /*! SETPOINT10 - SETPOINT10
90435  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90436  *  0b1..Slice reset will be asserted when system in Setpoint n
90437  */
90438 #define SRC_SETPOINT_M7CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)
90439 
90440 #define SRC_SETPOINT_M7CORE_SETPOINT11_MASK      (0x800U)
90441 #define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT     (11U)
90442 /*! SETPOINT11 - SETPOINT11
90443  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90444  *  0b1..Slice reset will be asserted when system in Setpoint n
90445  */
90446 #define SRC_SETPOINT_M7CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)
90447 
90448 #define SRC_SETPOINT_M7CORE_SETPOINT12_MASK      (0x1000U)
90449 #define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT     (12U)
90450 /*! SETPOINT12 - SETPOINT12
90451  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90452  *  0b1..Slice reset will be asserted when system in Setpoint n
90453  */
90454 #define SRC_SETPOINT_M7CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)
90455 
90456 #define SRC_SETPOINT_M7CORE_SETPOINT13_MASK      (0x2000U)
90457 #define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT     (13U)
90458 /*! SETPOINT13 - SETPOINT13
90459  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90460  *  0b1..Slice reset will be asserted when system in Setpoint n
90461  */
90462 #define SRC_SETPOINT_M7CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)
90463 
90464 #define SRC_SETPOINT_M7CORE_SETPOINT14_MASK      (0x4000U)
90465 #define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT     (14U)
90466 /*! SETPOINT14 - SETPOINT14
90467  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90468  *  0b1..Slice reset will be asserted when system in Setpoint n
90469  */
90470 #define SRC_SETPOINT_M7CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)
90471 
90472 #define SRC_SETPOINT_M7CORE_SETPOINT15_MASK      (0x8000U)
90473 #define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT     (15U)
90474 /*! SETPOINT15 - SETPOINT15
90475  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90476  *  0b1..Slice reset will be asserted when system in Setpoint n
90477  */
90478 #define SRC_SETPOINT_M7CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)
90479 /*! @} */
90480 
90481 /*! @name DOMAIN_M7CORE - Slice Domain Config Register */
90482 /*! @{ */
90483 
90484 #define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK          (0x1U)
90485 #define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT         (0U)
90486 /*! CPU0_RUN - CPU mode setting for RUN
90487  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90488  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90489  */
90490 #define SRC_DOMAIN_M7CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)
90491 
90492 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK         (0x2U)
90493 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT        (1U)
90494 /*! CPU0_WAIT - CPU mode setting for WAIT
90495  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90496  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90497  */
90498 #define SRC_DOMAIN_M7CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)
90499 
90500 #define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK         (0x4U)
90501 #define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT        (2U)
90502 /*! CPU0_STOP - CPU mode setting for STOP
90503  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90504  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90505  */
90506 #define SRC_DOMAIN_M7CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)
90507 
90508 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK         (0x8U)
90509 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT        (3U)
90510 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90511  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90512  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90513  */
90514 #define SRC_DOMAIN_M7CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)
90515 
90516 #define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK          (0x10U)
90517 #define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT         (4U)
90518 /*! CPU1_RUN - CPU mode setting for RUN
90519  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90520  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90521  */
90522 #define SRC_DOMAIN_M7CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)
90523 
90524 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK         (0x20U)
90525 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT        (5U)
90526 /*! CPU1_WAIT - CPU mode setting for WAIT
90527  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90528  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90529  */
90530 #define SRC_DOMAIN_M7CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)
90531 
90532 #define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK         (0x40U)
90533 #define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT        (6U)
90534 /*! CPU1_STOP - CPU mode setting for STOP
90535  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90536  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90537  */
90538 #define SRC_DOMAIN_M7CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)
90539 
90540 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK         (0x80U)
90541 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT        (7U)
90542 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90543  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90544  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90545  */
90546 #define SRC_DOMAIN_M7CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)
90547 /*! @} */
90548 
90549 /*! @name STAT_M7CORE - Slice Status Register */
90550 /*! @{ */
90551 
90552 #define SRC_STAT_M7CORE_UNDER_RST_MASK           (0x1U)
90553 #define SRC_STAT_M7CORE_UNDER_RST_SHIFT          (0U)
90554 /*! UNDER_RST
90555  *  0b0..the reset is finished
90556  *  0b1..the reset is in process
90557  */
90558 #define SRC_STAT_M7CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)
90559 
90560 #define SRC_STAT_M7CORE_RST_BY_HW_MASK           (0x4U)
90561 #define SRC_STAT_M7CORE_RST_BY_HW_SHIFT          (2U)
90562 /*! RST_BY_HW
90563  *  0b0..the reset is not caused by the power mode transfer
90564  *  0b1..the reset is caused by the power mode transfer
90565  */
90566 #define SRC_STAT_M7CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)
90567 
90568 #define SRC_STAT_M7CORE_RST_BY_SW_MASK           (0x8U)
90569 #define SRC_STAT_M7CORE_RST_BY_SW_SHIFT          (3U)
90570 /*! RST_BY_SW
90571  *  0b0..the reset is not caused by software setting
90572  *  0b1..the reset is caused by software setting
90573  */
90574 #define SRC_STAT_M7CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)
90575 /*! @} */
90576 
90577 /*! @name AUTHEN_M4DEBUG - Slice Authentication Register */
90578 /*! @{ */
90579 
90580 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK      (0x1U)
90581 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT     (0U)
90582 /*! DOMAIN_MODE
90583  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90584  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90585  */
90586 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)
90587 
90588 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK    (0x2U)
90589 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT   (1U)
90590 /*! SETPOINT_MODE
90591  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90592  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90593  */
90594 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)
90595 
90596 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK        (0x80U)
90597 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT       (7U)
90598 /*! LOCK_MODE - Domain/Setpoint mode lock
90599  */
90600 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)
90601 
90602 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK      (0xF00U)
90603 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT     (8U)
90604 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)
90605 
90606 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
90607 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT     (15U)
90608 /*! LOCK_ASSIGN - Assign list lock
90609  */
90610 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)
90611 
90612 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK       (0xF0000U)
90613 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT      (16U)
90614 /*! WHITE_LIST - Domain ID white list
90615  */
90616 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)
90617 
90618 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK        (0x800000U)
90619 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT       (23U)
90620 /*! LOCK_LIST - White list lock
90621  */
90622 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)
90623 
90624 #define SRC_AUTHEN_M4DEBUG_USER_MASK             (0x1000000U)
90625 #define SRC_AUTHEN_M4DEBUG_USER_SHIFT            (24U)
90626 /*! USER - Allow user mode access
90627  */
90628 #define SRC_AUTHEN_M4DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)
90629 
90630 #define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK        (0x2000000U)
90631 #define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT       (25U)
90632 /*! NONSECURE - Allow non-secure mode access
90633  */
90634 #define SRC_AUTHEN_M4DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)
90635 
90636 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK     (0x80000000U)
90637 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT    (31U)
90638 /*! LOCK_SETTING - Lock NONSECURE and USER
90639  */
90640 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)
90641 /*! @} */
90642 
90643 /*! @name CTRL_M4DEBUG - Slice Control Register */
90644 /*! @{ */
90645 
90646 #define SRC_CTRL_M4DEBUG_SW_RESET_MASK           (0x1U)
90647 #define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT          (0U)
90648 /*! SW_RESET
90649  *  0b0..do not assert slice software reset
90650  *  0b1..assert slice software reset
90651  */
90652 #define SRC_CTRL_M4DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)
90653 /*! @} */
90654 
90655 /*! @name SETPOINT_M4DEBUG - Slice Setpoint Config Register */
90656 /*! @{ */
90657 
90658 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK      (0x1U)
90659 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT     (0U)
90660 /*! SETPOINT0 - SETPOINT0
90661  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90662  *  0b1..Slice reset will be asserted when system in Setpoint n
90663  */
90664 #define SRC_SETPOINT_M4DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)
90665 
90666 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK      (0x2U)
90667 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT     (1U)
90668 /*! SETPOINT1 - SETPOINT1
90669  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90670  *  0b1..Slice reset will be asserted when system in Setpoint n
90671  */
90672 #define SRC_SETPOINT_M4DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)
90673 
90674 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK      (0x4U)
90675 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT     (2U)
90676 /*! SETPOINT2 - SETPOINT2
90677  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90678  *  0b1..Slice reset will be asserted when system in Setpoint n
90679  */
90680 #define SRC_SETPOINT_M4DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)
90681 
90682 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK      (0x8U)
90683 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT     (3U)
90684 /*! SETPOINT3 - SETPOINT3
90685  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90686  *  0b1..Slice reset will be asserted when system in Setpoint n
90687  */
90688 #define SRC_SETPOINT_M4DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)
90689 
90690 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK      (0x10U)
90691 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT     (4U)
90692 /*! SETPOINT4 - SETPOINT4
90693  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90694  *  0b1..Slice reset will be asserted when system in Setpoint n
90695  */
90696 #define SRC_SETPOINT_M4DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)
90697 
90698 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK      (0x20U)
90699 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT     (5U)
90700 /*! SETPOINT5 - SETPOINT5
90701  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90702  *  0b1..Slice reset will be asserted when system in Setpoint n
90703  */
90704 #define SRC_SETPOINT_M4DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)
90705 
90706 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK      (0x40U)
90707 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT     (6U)
90708 /*! SETPOINT6 - SETPOINT6
90709  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90710  *  0b1..Slice reset will be asserted when system in Setpoint n
90711  */
90712 #define SRC_SETPOINT_M4DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)
90713 
90714 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK      (0x80U)
90715 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT     (7U)
90716 /*! SETPOINT7 - SETPOINT7
90717  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90718  *  0b1..Slice reset will be asserted when system in Setpoint n
90719  */
90720 #define SRC_SETPOINT_M4DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)
90721 
90722 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK      (0x100U)
90723 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT     (8U)
90724 /*! SETPOINT8 - SETPOINT8
90725  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90726  *  0b1..Slice reset will be asserted when system in Setpoint n
90727  */
90728 #define SRC_SETPOINT_M4DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)
90729 
90730 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK      (0x200U)
90731 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT     (9U)
90732 /*! SETPOINT9 - SETPOINT9
90733  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90734  *  0b1..Slice reset will be asserted when system in Setpoint n
90735  */
90736 #define SRC_SETPOINT_M4DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)
90737 
90738 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK     (0x400U)
90739 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT    (10U)
90740 /*! SETPOINT10 - SETPOINT10
90741  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90742  *  0b1..Slice reset will be asserted when system in Setpoint n
90743  */
90744 #define SRC_SETPOINT_M4DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)
90745 
90746 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK     (0x800U)
90747 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT    (11U)
90748 /*! SETPOINT11 - SETPOINT11
90749  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90750  *  0b1..Slice reset will be asserted when system in Setpoint n
90751  */
90752 #define SRC_SETPOINT_M4DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)
90753 
90754 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK     (0x1000U)
90755 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT    (12U)
90756 /*! SETPOINT12 - SETPOINT12
90757  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90758  *  0b1..Slice reset will be asserted when system in Setpoint n
90759  */
90760 #define SRC_SETPOINT_M4DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)
90761 
90762 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK     (0x2000U)
90763 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT    (13U)
90764 /*! SETPOINT13 - SETPOINT13
90765  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90766  *  0b1..Slice reset will be asserted when system in Setpoint n
90767  */
90768 #define SRC_SETPOINT_M4DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)
90769 
90770 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK     (0x4000U)
90771 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT    (14U)
90772 /*! SETPOINT14 - SETPOINT14
90773  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90774  *  0b1..Slice reset will be asserted when system in Setpoint n
90775  */
90776 #define SRC_SETPOINT_M4DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)
90777 
90778 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK     (0x8000U)
90779 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT    (15U)
90780 /*! SETPOINT15 - SETPOINT15
90781  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90782  *  0b1..Slice reset will be asserted when system in Setpoint n
90783  */
90784 #define SRC_SETPOINT_M4DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)
90785 /*! @} */
90786 
90787 /*! @name DOMAIN_M4DEBUG - Slice Domain Config Register */
90788 /*! @{ */
90789 
90790 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK         (0x1U)
90791 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT        (0U)
90792 /*! CPU0_RUN - CPU mode setting for RUN
90793  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90794  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90795  */
90796 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)
90797 
90798 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK        (0x2U)
90799 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT       (1U)
90800 /*! CPU0_WAIT - CPU mode setting for WAIT
90801  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90802  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90803  */
90804 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)
90805 
90806 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK        (0x4U)
90807 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT       (2U)
90808 /*! CPU0_STOP - CPU mode setting for STOP
90809  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90810  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90811  */
90812 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)
90813 
90814 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK        (0x8U)
90815 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT       (3U)
90816 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90817  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90818  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90819  */
90820 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)
90821 
90822 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK         (0x10U)
90823 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT        (4U)
90824 /*! CPU1_RUN - CPU mode setting for RUN
90825  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90826  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90827  */
90828 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)
90829 
90830 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK        (0x20U)
90831 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT       (5U)
90832 /*! CPU1_WAIT - CPU mode setting for WAIT
90833  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90834  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90835  */
90836 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)
90837 
90838 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK        (0x40U)
90839 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT       (6U)
90840 /*! CPU1_STOP - CPU mode setting for STOP
90841  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90842  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90843  */
90844 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)
90845 
90846 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK        (0x80U)
90847 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT       (7U)
90848 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90849  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90850  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90851  */
90852 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)
90853 /*! @} */
90854 
90855 /*! @name STAT_M4DEBUG - Slice Status Register */
90856 /*! @{ */
90857 
90858 #define SRC_STAT_M4DEBUG_UNDER_RST_MASK          (0x1U)
90859 #define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT         (0U)
90860 /*! UNDER_RST
90861  *  0b0..the reset is finished
90862  *  0b1..the reset is in process
90863  */
90864 #define SRC_STAT_M4DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)
90865 
90866 #define SRC_STAT_M4DEBUG_RST_BY_HW_MASK          (0x4U)
90867 #define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT         (2U)
90868 /*! RST_BY_HW
90869  *  0b0..the reset is not caused by the power mode transfer
90870  *  0b1..the reset is caused by the power mode transfer
90871  */
90872 #define SRC_STAT_M4DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)
90873 
90874 #define SRC_STAT_M4DEBUG_RST_BY_SW_MASK          (0x8U)
90875 #define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT         (3U)
90876 /*! RST_BY_SW
90877  *  0b0..the reset is not caused by software setting
90878  *  0b1..the reset is caused by software setting
90879  */
90880 #define SRC_STAT_M4DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)
90881 /*! @} */
90882 
90883 /*! @name AUTHEN_M7DEBUG - Slice Authentication Register */
90884 /*! @{ */
90885 
90886 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK      (0x1U)
90887 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT     (0U)
90888 /*! DOMAIN_MODE
90889  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90890  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90891  */
90892 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)
90893 
90894 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK    (0x2U)
90895 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT   (1U)
90896 /*! SETPOINT_MODE
90897  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90898  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90899  */
90900 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)
90901 
90902 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK        (0x80U)
90903 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT       (7U)
90904 /*! LOCK_MODE - Domain/Setpoint mode lock
90905  */
90906 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)
90907 
90908 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK      (0xF00U)
90909 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT     (8U)
90910 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)
90911 
90912 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
90913 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT     (15U)
90914 /*! LOCK_ASSIGN - Assign list lock
90915  */
90916 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)
90917 
90918 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK       (0xF0000U)
90919 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT      (16U)
90920 /*! WHITE_LIST - Domain ID white list
90921  */
90922 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)
90923 
90924 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK        (0x800000U)
90925 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT       (23U)
90926 /*! LOCK_LIST - White list lock
90927  */
90928 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)
90929 
90930 #define SRC_AUTHEN_M7DEBUG_USER_MASK             (0x1000000U)
90931 #define SRC_AUTHEN_M7DEBUG_USER_SHIFT            (24U)
90932 /*! USER - Allow user mode access
90933  */
90934 #define SRC_AUTHEN_M7DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)
90935 
90936 #define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK        (0x2000000U)
90937 #define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT       (25U)
90938 /*! NONSECURE - Allow non-secure mode access
90939  */
90940 #define SRC_AUTHEN_M7DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)
90941 
90942 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK     (0x80000000U)
90943 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT    (31U)
90944 /*! LOCK_SETTING - Lock NONSECURE and USER
90945  */
90946 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)
90947 /*! @} */
90948 
90949 /*! @name CTRL_M7DEBUG - Slice Control Register */
90950 /*! @{ */
90951 
90952 #define SRC_CTRL_M7DEBUG_SW_RESET_MASK           (0x1U)
90953 #define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT          (0U)
90954 /*! SW_RESET
90955  *  0b0..do not assert slice software reset
90956  *  0b1..assert slice software reset
90957  */
90958 #define SRC_CTRL_M7DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)
90959 /*! @} */
90960 
90961 /*! @name SETPOINT_M7DEBUG - Slice Setpoint Config Register */
90962 /*! @{ */
90963 
90964 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK      (0x1U)
90965 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT     (0U)
90966 /*! SETPOINT0 - SETPOINT0
90967  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90968  *  0b1..Slice reset will be asserted when system in Setpoint n
90969  */
90970 #define SRC_SETPOINT_M7DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)
90971 
90972 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK      (0x2U)
90973 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT     (1U)
90974 /*! SETPOINT1 - SETPOINT1
90975  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90976  *  0b1..Slice reset will be asserted when system in Setpoint n
90977  */
90978 #define SRC_SETPOINT_M7DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)
90979 
90980 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK      (0x4U)
90981 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT     (2U)
90982 /*! SETPOINT2 - SETPOINT2
90983  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90984  *  0b1..Slice reset will be asserted when system in Setpoint n
90985  */
90986 #define SRC_SETPOINT_M7DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)
90987 
90988 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK      (0x8U)
90989 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT     (3U)
90990 /*! SETPOINT3 - SETPOINT3
90991  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90992  *  0b1..Slice reset will be asserted when system in Setpoint n
90993  */
90994 #define SRC_SETPOINT_M7DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)
90995 
90996 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK      (0x10U)
90997 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT     (4U)
90998 /*! SETPOINT4 - SETPOINT4
90999  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91000  *  0b1..Slice reset will be asserted when system in Setpoint n
91001  */
91002 #define SRC_SETPOINT_M7DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)
91003 
91004 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK      (0x20U)
91005 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT     (5U)
91006 /*! SETPOINT5 - SETPOINT5
91007  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91008  *  0b1..Slice reset will be asserted when system in Setpoint n
91009  */
91010 #define SRC_SETPOINT_M7DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)
91011 
91012 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK      (0x40U)
91013 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT     (6U)
91014 /*! SETPOINT6 - SETPOINT6
91015  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91016  *  0b1..Slice reset will be asserted when system in Setpoint n
91017  */
91018 #define SRC_SETPOINT_M7DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)
91019 
91020 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK      (0x80U)
91021 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT     (7U)
91022 /*! SETPOINT7 - SETPOINT7
91023  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91024  *  0b1..Slice reset will be asserted when system in Setpoint n
91025  */
91026 #define SRC_SETPOINT_M7DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)
91027 
91028 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK      (0x100U)
91029 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT     (8U)
91030 /*! SETPOINT8 - SETPOINT8
91031  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91032  *  0b1..Slice reset will be asserted when system in Setpoint n
91033  */
91034 #define SRC_SETPOINT_M7DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)
91035 
91036 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK      (0x200U)
91037 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT     (9U)
91038 /*! SETPOINT9 - SETPOINT9
91039  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91040  *  0b1..Slice reset will be asserted when system in Setpoint n
91041  */
91042 #define SRC_SETPOINT_M7DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)
91043 
91044 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK     (0x400U)
91045 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT    (10U)
91046 /*! SETPOINT10 - SETPOINT10
91047  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91048  *  0b1..Slice reset will be asserted when system in Setpoint n
91049  */
91050 #define SRC_SETPOINT_M7DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)
91051 
91052 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK     (0x800U)
91053 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT    (11U)
91054 /*! SETPOINT11 - SETPOINT11
91055  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91056  *  0b1..Slice reset will be asserted when system in Setpoint n
91057  */
91058 #define SRC_SETPOINT_M7DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)
91059 
91060 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK     (0x1000U)
91061 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT    (12U)
91062 /*! SETPOINT12 - SETPOINT12
91063  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91064  *  0b1..Slice reset will be asserted when system in Setpoint n
91065  */
91066 #define SRC_SETPOINT_M7DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)
91067 
91068 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK     (0x2000U)
91069 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT    (13U)
91070 /*! SETPOINT13 - SETPOINT13
91071  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91072  *  0b1..Slice reset will be asserted when system in Setpoint n
91073  */
91074 #define SRC_SETPOINT_M7DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)
91075 
91076 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK     (0x4000U)
91077 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT    (14U)
91078 /*! SETPOINT14 - SETPOINT14
91079  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91080  *  0b1..Slice reset will be asserted when system in Setpoint n
91081  */
91082 #define SRC_SETPOINT_M7DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)
91083 
91084 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK     (0x8000U)
91085 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT    (15U)
91086 /*! SETPOINT15 - SETPOINT15
91087  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91088  *  0b1..Slice reset will be asserted when system in Setpoint n
91089  */
91090 #define SRC_SETPOINT_M7DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)
91091 /*! @} */
91092 
91093 /*! @name DOMAIN_M7DEBUG - Slice Domain Config Register */
91094 /*! @{ */
91095 
91096 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK         (0x1U)
91097 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT        (0U)
91098 /*! CPU0_RUN - CPU mode setting for RUN
91099  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
91100  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
91101  */
91102 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)
91103 
91104 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK        (0x2U)
91105 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT       (1U)
91106 /*! CPU0_WAIT - CPU mode setting for WAIT
91107  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
91108  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
91109  */
91110 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)
91111 
91112 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK        (0x4U)
91113 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT       (2U)
91114 /*! CPU0_STOP - CPU mode setting for STOP
91115  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
91116  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
91117  */
91118 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)
91119 
91120 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK        (0x8U)
91121 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT       (3U)
91122 /*! CPU0_SUSP - CPU mode setting for SUSPEND
91123  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
91124  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
91125  */
91126 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)
91127 
91128 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK         (0x10U)
91129 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT        (4U)
91130 /*! CPU1_RUN - CPU mode setting for RUN
91131  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
91132  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
91133  */
91134 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)
91135 
91136 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK        (0x20U)
91137 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT       (5U)
91138 /*! CPU1_WAIT - CPU mode setting for WAIT
91139  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
91140  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
91141  */
91142 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)
91143 
91144 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK        (0x40U)
91145 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT       (6U)
91146 /*! CPU1_STOP - CPU mode setting for STOP
91147  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
91148  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
91149  */
91150 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)
91151 
91152 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK        (0x80U)
91153 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT       (7U)
91154 /*! CPU1_SUSP - CPU mode setting for SUSPEND
91155  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
91156  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
91157  */
91158 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)
91159 /*! @} */
91160 
91161 /*! @name STAT_M7DEBUG - Slice Status Register */
91162 /*! @{ */
91163 
91164 #define SRC_STAT_M7DEBUG_UNDER_RST_MASK          (0x1U)
91165 #define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT         (0U)
91166 /*! UNDER_RST
91167  *  0b0..the reset is finished
91168  *  0b1..the reset is in process
91169  */
91170 #define SRC_STAT_M7DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)
91171 
91172 #define SRC_STAT_M7DEBUG_RST_BY_HW_MASK          (0x4U)
91173 #define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT         (2U)
91174 /*! RST_BY_HW
91175  *  0b0..the reset is not caused by the power mode transfer
91176  *  0b1..the reset is caused by the power mode transfer
91177  */
91178 #define SRC_STAT_M7DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)
91179 
91180 #define SRC_STAT_M7DEBUG_RST_BY_SW_MASK          (0x8U)
91181 #define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT         (3U)
91182 /*! RST_BY_SW
91183  *  0b0..the reset is not caused by software setting
91184  *  0b1..the reset is caused by software setting
91185  */
91186 #define SRC_STAT_M7DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)
91187 /*! @} */
91188 
91189 /*! @name AUTHEN_USBPHY1 - Slice Authentication Register */
91190 /*! @{ */
91191 
91192 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK      (0x1U)
91193 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT     (0U)
91194 /*! DOMAIN_MODE
91195  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
91196  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
91197  */
91198 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)
91199 
91200 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK    (0x2U)
91201 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT   (1U)
91202 /*! SETPOINT_MODE
91203  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
91204  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
91205  */
91206 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)
91207 
91208 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK        (0x80U)
91209 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT       (7U)
91210 /*! LOCK_MODE - Domain/Setpoint mode lock
91211  */
91212 #define SRC_AUTHEN_USBPHY1_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)
91213 
91214 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK      (0xF00U)
91215 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT     (8U)
91216 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)
91217 
91218 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK      (0x8000U)
91219 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT     (15U)
91220 /*! LOCK_ASSIGN - Assign list lock
91221  */
91222 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)
91223 
91224 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK       (0xF0000U)
91225 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT      (16U)
91226 /*! WHITE_LIST - Domain ID white list
91227  */
91228 #define SRC_AUTHEN_USBPHY1_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)
91229 
91230 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK        (0x800000U)
91231 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT       (23U)
91232 /*! LOCK_LIST - White list lock
91233  */
91234 #define SRC_AUTHEN_USBPHY1_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)
91235 
91236 #define SRC_AUTHEN_USBPHY1_USER_MASK             (0x1000000U)
91237 #define SRC_AUTHEN_USBPHY1_USER_SHIFT            (24U)
91238 /*! USER - Allow user mode access
91239  */
91240 #define SRC_AUTHEN_USBPHY1_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)
91241 
91242 #define SRC_AUTHEN_USBPHY1_NONSECURE_MASK        (0x2000000U)
91243 #define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT       (25U)
91244 /*! NONSECURE - Allow non-secure mode access
91245  */
91246 #define SRC_AUTHEN_USBPHY1_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)
91247 
91248 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK     (0x80000000U)
91249 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT    (31U)
91250 /*! LOCK_SETTING - Lock NONSECURE and USER
91251  */
91252 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)
91253 /*! @} */
91254 
91255 /*! @name CTRL_USBPHY1 - Slice Control Register */
91256 /*! @{ */
91257 
91258 #define SRC_CTRL_USBPHY1_SW_RESET_MASK           (0x1U)
91259 #define SRC_CTRL_USBPHY1_SW_RESET_SHIFT          (0U)
91260 /*! SW_RESET
91261  *  0b0..do not assert slice software reset
91262  *  0b1..assert slice software reset
91263  */
91264 #define SRC_CTRL_USBPHY1_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)
91265 /*! @} */
91266 
91267 /*! @name SETPOINT_USBPHY1 - Slice Setpoint Config Register */
91268 /*! @{ */
91269 
91270 #define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK      (0x1U)
91271 #define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT     (0U)
91272 /*! SETPOINT0 - SETPOINT0
91273  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91274  *  0b1..Slice reset will be asserted when system in Setpoint n
91275  */
91276 #define SRC_SETPOINT_USBPHY1_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)
91277 
91278 #define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK      (0x2U)
91279 #define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT     (1U)
91280 /*! SETPOINT1 - SETPOINT1
91281  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91282  *  0b1..Slice reset will be asserted when system in Setpoint n
91283  */
91284 #define SRC_SETPOINT_USBPHY1_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)
91285 
91286 #define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK      (0x4U)
91287 #define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT     (2U)
91288 /*! SETPOINT2 - SETPOINT2
91289  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91290  *  0b1..Slice reset will be asserted when system in Setpoint n
91291  */
91292 #define SRC_SETPOINT_USBPHY1_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)
91293 
91294 #define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK      (0x8U)
91295 #define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT     (3U)
91296 /*! SETPOINT3 - SETPOINT3
91297  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91298  *  0b1..Slice reset will be asserted when system in Setpoint n
91299  */
91300 #define SRC_SETPOINT_USBPHY1_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)
91301 
91302 #define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK      (0x10U)
91303 #define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT     (4U)
91304 /*! SETPOINT4 - SETPOINT4
91305  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91306  *  0b1..Slice reset will be asserted when system in Setpoint n
91307  */
91308 #define SRC_SETPOINT_USBPHY1_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)
91309 
91310 #define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK      (0x20U)
91311 #define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT     (5U)
91312 /*! SETPOINT5 - SETPOINT5
91313  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91314  *  0b1..Slice reset will be asserted when system in Setpoint n
91315  */
91316 #define SRC_SETPOINT_USBPHY1_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)
91317 
91318 #define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK      (0x40U)
91319 #define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT     (6U)
91320 /*! SETPOINT6 - SETPOINT6
91321  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91322  *  0b1..Slice reset will be asserted when system in Setpoint n
91323  */
91324 #define SRC_SETPOINT_USBPHY1_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)
91325 
91326 #define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK      (0x80U)
91327 #define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT     (7U)
91328 /*! SETPOINT7 - SETPOINT7
91329  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91330  *  0b1..Slice reset will be asserted when system in Setpoint n
91331  */
91332 #define SRC_SETPOINT_USBPHY1_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)
91333 
91334 #define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK      (0x100U)
91335 #define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT     (8U)
91336 /*! SETPOINT8 - SETPOINT8
91337  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91338  *  0b1..Slice reset will be asserted when system in Setpoint n
91339  */
91340 #define SRC_SETPOINT_USBPHY1_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)
91341 
91342 #define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK      (0x200U)
91343 #define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT     (9U)
91344 /*! SETPOINT9 - SETPOINT9
91345  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91346  *  0b1..Slice reset will be asserted when system in Setpoint n
91347  */
91348 #define SRC_SETPOINT_USBPHY1_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)
91349 
91350 #define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK     (0x400U)
91351 #define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT    (10U)
91352 /*! SETPOINT10 - SETPOINT10
91353  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91354  *  0b1..Slice reset will be asserted when system in Setpoint n
91355  */
91356 #define SRC_SETPOINT_USBPHY1_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)
91357 
91358 #define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK     (0x800U)
91359 #define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT    (11U)
91360 /*! SETPOINT11 - SETPOINT11
91361  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91362  *  0b1..Slice reset will be asserted when system in Setpoint n
91363  */
91364 #define SRC_SETPOINT_USBPHY1_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)
91365 
91366 #define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK     (0x1000U)
91367 #define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT    (12U)
91368 /*! SETPOINT12 - SETPOINT12
91369  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91370  *  0b1..Slice reset will be asserted when system in Setpoint n
91371  */
91372 #define SRC_SETPOINT_USBPHY1_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)
91373 
91374 #define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK     (0x2000U)
91375 #define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT    (13U)
91376 /*! SETPOINT13 - SETPOINT13
91377  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91378  *  0b1..Slice reset will be asserted when system in Setpoint n
91379  */
91380 #define SRC_SETPOINT_USBPHY1_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)
91381 
91382 #define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK     (0x4000U)
91383 #define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT    (14U)
91384 /*! SETPOINT14 - SETPOINT14
91385  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91386  *  0b1..Slice reset will be asserted when system in Setpoint n
91387  */
91388 #define SRC_SETPOINT_USBPHY1_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)
91389 
91390 #define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK     (0x8000U)
91391 #define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT    (15U)
91392 /*! SETPOINT15 - SETPOINT15
91393  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91394  *  0b1..Slice reset will be asserted when system in Setpoint n
91395  */
91396 #define SRC_SETPOINT_USBPHY1_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)
91397 /*! @} */
91398 
91399 /*! @name DOMAIN_USBPHY1 - Slice Domain Config Register */
91400 /*! @{ */
91401 
91402 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK         (0x1U)
91403 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT        (0U)
91404 /*! CPU0_RUN - CPU mode setting for RUN
91405  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
91406  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
91407  */
91408 #define SRC_DOMAIN_USBPHY1_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)
91409 
91410 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK        (0x2U)
91411 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT       (1U)
91412 /*! CPU0_WAIT - CPU mode setting for WAIT
91413  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
91414  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
91415  */
91416 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)
91417 
91418 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK        (0x4U)
91419 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT       (2U)
91420 /*! CPU0_STOP - CPU mode setting for STOP
91421  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
91422  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
91423  */
91424 #define SRC_DOMAIN_USBPHY1_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)
91425 
91426 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK        (0x8U)
91427 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT       (3U)
91428 /*! CPU0_SUSP - CPU mode setting for SUSPEND
91429  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
91430  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
91431  */
91432 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)
91433 
91434 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK         (0x10U)
91435 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT        (4U)
91436 /*! CPU1_RUN - CPU mode setting for RUN
91437  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
91438  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
91439  */
91440 #define SRC_DOMAIN_USBPHY1_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)
91441 
91442 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK        (0x20U)
91443 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT       (5U)
91444 /*! CPU1_WAIT - CPU mode setting for WAIT
91445  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
91446  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
91447  */
91448 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)
91449 
91450 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK        (0x40U)
91451 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT       (6U)
91452 /*! CPU1_STOP - CPU mode setting for STOP
91453  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
91454  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
91455  */
91456 #define SRC_DOMAIN_USBPHY1_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)
91457 
91458 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK        (0x80U)
91459 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT       (7U)
91460 /*! CPU1_SUSP - CPU mode setting for SUSPEND
91461  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
91462  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
91463  */
91464 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)
91465 /*! @} */
91466 
91467 /*! @name STAT_USBPHY1 - Slice Status Register */
91468 /*! @{ */
91469 
91470 #define SRC_STAT_USBPHY1_UNDER_RST_MASK          (0x1U)
91471 #define SRC_STAT_USBPHY1_UNDER_RST_SHIFT         (0U)
91472 /*! UNDER_RST
91473  *  0b0..the reset is finished
91474  *  0b1..the reset is in process
91475  */
91476 #define SRC_STAT_USBPHY1_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)
91477 
91478 #define SRC_STAT_USBPHY1_RST_BY_HW_MASK          (0x4U)
91479 #define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT         (2U)
91480 /*! RST_BY_HW
91481  *  0b0..the reset is not caused by the power mode transfer
91482  *  0b1..the reset is caused by the power mode transfer
91483  */
91484 #define SRC_STAT_USBPHY1_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)
91485 
91486 #define SRC_STAT_USBPHY1_RST_BY_SW_MASK          (0x8U)
91487 #define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT         (3U)
91488 /*! RST_BY_SW
91489  *  0b0..the reset is not caused by software setting
91490  *  0b1..the reset is caused by software setting
91491  */
91492 #define SRC_STAT_USBPHY1_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)
91493 /*! @} */
91494 
91495 /*! @name AUTHEN_USBPHY2 - Slice Authentication Register */
91496 /*! @{ */
91497 
91498 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK      (0x1U)
91499 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT     (0U)
91500 /*! DOMAIN_MODE
91501  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
91502  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
91503  */
91504 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)
91505 
91506 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK    (0x2U)
91507 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT   (1U)
91508 /*! SETPOINT_MODE
91509  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
91510  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
91511  */
91512 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)
91513 
91514 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK        (0x80U)
91515 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT       (7U)
91516 /*! LOCK_MODE - Domain/Setpoint mode lock
91517  */
91518 #define SRC_AUTHEN_USBPHY2_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)
91519 
91520 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK      (0xF00U)
91521 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT     (8U)
91522 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)
91523 
91524 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK      (0x8000U)
91525 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT     (15U)
91526 /*! LOCK_ASSIGN - Assign list lock
91527  */
91528 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)
91529 
91530 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK       (0xF0000U)
91531 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT      (16U)
91532 /*! WHITE_LIST - Domain ID white list
91533  */
91534 #define SRC_AUTHEN_USBPHY2_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)
91535 
91536 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK        (0x800000U)
91537 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT       (23U)
91538 /*! LOCK_LIST - White list lock
91539  */
91540 #define SRC_AUTHEN_USBPHY2_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)
91541 
91542 #define SRC_AUTHEN_USBPHY2_USER_MASK             (0x1000000U)
91543 #define SRC_AUTHEN_USBPHY2_USER_SHIFT            (24U)
91544 /*! USER - Allow user mode access
91545  */
91546 #define SRC_AUTHEN_USBPHY2_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)
91547 
91548 #define SRC_AUTHEN_USBPHY2_NONSECURE_MASK        (0x2000000U)
91549 #define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT       (25U)
91550 /*! NONSECURE - Allow non-secure mode access
91551  */
91552 #define SRC_AUTHEN_USBPHY2_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)
91553 
91554 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK     (0x80000000U)
91555 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT    (31U)
91556 /*! LOCK_SETTING - Lock NONSECURE and USER
91557  */
91558 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)
91559 /*! @} */
91560 
91561 /*! @name CTRL_USBPHY2 - Slice Control Register */
91562 /*! @{ */
91563 
91564 #define SRC_CTRL_USBPHY2_SW_RESET_MASK           (0x1U)
91565 #define SRC_CTRL_USBPHY2_SW_RESET_SHIFT          (0U)
91566 /*! SW_RESET
91567  *  0b0..do not assert slice software reset
91568  *  0b1..assert slice software reset
91569  */
91570 #define SRC_CTRL_USBPHY2_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)
91571 /*! @} */
91572 
91573 /*! @name SETPOINT_USBPHY2 - Slice Setpoint Config Register */
91574 /*! @{ */
91575 
91576 #define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK      (0x1U)
91577 #define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT     (0U)
91578 /*! SETPOINT0 - SETPOINT0
91579  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91580  *  0b1..Slice reset will be asserted when system in Setpoint n
91581  */
91582 #define SRC_SETPOINT_USBPHY2_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)
91583 
91584 #define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK      (0x2U)
91585 #define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT     (1U)
91586 /*! SETPOINT1 - SETPOINT1
91587  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91588  *  0b1..Slice reset will be asserted when system in Setpoint n
91589  */
91590 #define SRC_SETPOINT_USBPHY2_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)
91591 
91592 #define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK      (0x4U)
91593 #define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT     (2U)
91594 /*! SETPOINT2 - SETPOINT2
91595  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91596  *  0b1..Slice reset will be asserted when system in Setpoint n
91597  */
91598 #define SRC_SETPOINT_USBPHY2_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)
91599 
91600 #define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK      (0x8U)
91601 #define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT     (3U)
91602 /*! SETPOINT3 - SETPOINT3
91603  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91604  *  0b1..Slice reset will be asserted when system in Setpoint n
91605  */
91606 #define SRC_SETPOINT_USBPHY2_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)
91607 
91608 #define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK      (0x10U)
91609 #define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT     (4U)
91610 /*! SETPOINT4 - SETPOINT4
91611  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91612  *  0b1..Slice reset will be asserted when system in Setpoint n
91613  */
91614 #define SRC_SETPOINT_USBPHY2_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)
91615 
91616 #define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK      (0x20U)
91617 #define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT     (5U)
91618 /*! SETPOINT5 - SETPOINT5
91619  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91620  *  0b1..Slice reset will be asserted when system in Setpoint n
91621  */
91622 #define SRC_SETPOINT_USBPHY2_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)
91623 
91624 #define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK      (0x40U)
91625 #define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT     (6U)
91626 /*! SETPOINT6 - SETPOINT6
91627  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91628  *  0b1..Slice reset will be asserted when system in Setpoint n
91629  */
91630 #define SRC_SETPOINT_USBPHY2_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)
91631 
91632 #define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK      (0x80U)
91633 #define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT     (7U)
91634 /*! SETPOINT7 - SETPOINT7
91635  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91636  *  0b1..Slice reset will be asserted when system in Setpoint n
91637  */
91638 #define SRC_SETPOINT_USBPHY2_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)
91639 
91640 #define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK      (0x100U)
91641 #define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT     (8U)
91642 /*! SETPOINT8 - SETPOINT8
91643  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91644  *  0b1..Slice reset will be asserted when system in Setpoint n
91645  */
91646 #define SRC_SETPOINT_USBPHY2_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)
91647 
91648 #define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK      (0x200U)
91649 #define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT     (9U)
91650 /*! SETPOINT9 - SETPOINT9
91651  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91652  *  0b1..Slice reset will be asserted when system in Setpoint n
91653  */
91654 #define SRC_SETPOINT_USBPHY2_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)
91655 
91656 #define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK     (0x400U)
91657 #define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT    (10U)
91658 /*! SETPOINT10 - SETPOINT10
91659  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91660  *  0b1..Slice reset will be asserted when system in Setpoint n
91661  */
91662 #define SRC_SETPOINT_USBPHY2_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)
91663 
91664 #define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK     (0x800U)
91665 #define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT    (11U)
91666 /*! SETPOINT11 - SETPOINT11
91667  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91668  *  0b1..Slice reset will be asserted when system in Setpoint n
91669  */
91670 #define SRC_SETPOINT_USBPHY2_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)
91671 
91672 #define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK     (0x1000U)
91673 #define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT    (12U)
91674 /*! SETPOINT12 - SETPOINT12
91675  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91676  *  0b1..Slice reset will be asserted when system in Setpoint n
91677  */
91678 #define SRC_SETPOINT_USBPHY2_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)
91679 
91680 #define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK     (0x2000U)
91681 #define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT    (13U)
91682 /*! SETPOINT13 - SETPOINT13
91683  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91684  *  0b1..Slice reset will be asserted when system in Setpoint n
91685  */
91686 #define SRC_SETPOINT_USBPHY2_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)
91687 
91688 #define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK     (0x4000U)
91689 #define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT    (14U)
91690 /*! SETPOINT14 - SETPOINT14
91691  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91692  *  0b1..Slice reset will be asserted when system in Setpoint n
91693  */
91694 #define SRC_SETPOINT_USBPHY2_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)
91695 
91696 #define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK     (0x8000U)
91697 #define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT    (15U)
91698 /*! SETPOINT15 - SETPOINT15
91699  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91700  *  0b1..Slice reset will be asserted when system in Setpoint n
91701  */
91702 #define SRC_SETPOINT_USBPHY2_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)
91703 /*! @} */
91704 
91705 /*! @name DOMAIN_USBPHY2 - Slice Domain Config Register */
91706 /*! @{ */
91707 
91708 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK         (0x1U)
91709 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT        (0U)
91710 /*! CPU0_RUN - CPU mode setting for RUN
91711  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
91712  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
91713  */
91714 #define SRC_DOMAIN_USBPHY2_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)
91715 
91716 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK        (0x2U)
91717 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT       (1U)
91718 /*! CPU0_WAIT - CPU mode setting for WAIT
91719  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
91720  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
91721  */
91722 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)
91723 
91724 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK        (0x4U)
91725 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT       (2U)
91726 /*! CPU0_STOP - CPU mode setting for STOP
91727  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
91728  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
91729  */
91730 #define SRC_DOMAIN_USBPHY2_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)
91731 
91732 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK        (0x8U)
91733 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT       (3U)
91734 /*! CPU0_SUSP - CPU mode setting for SUSPEND
91735  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
91736  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
91737  */
91738 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)
91739 
91740 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK         (0x10U)
91741 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT        (4U)
91742 /*! CPU1_RUN - CPU mode setting for RUN
91743  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
91744  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
91745  */
91746 #define SRC_DOMAIN_USBPHY2_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)
91747 
91748 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK        (0x20U)
91749 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT       (5U)
91750 /*! CPU1_WAIT - CPU mode setting for WAIT
91751  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
91752  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
91753  */
91754 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)
91755 
91756 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK        (0x40U)
91757 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT       (6U)
91758 /*! CPU1_STOP - CPU mode setting for STOP
91759  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
91760  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
91761  */
91762 #define SRC_DOMAIN_USBPHY2_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)
91763 
91764 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK        (0x80U)
91765 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT       (7U)
91766 /*! CPU1_SUSP - CPU mode setting for SUSPEND
91767  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
91768  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
91769  */
91770 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)
91771 /*! @} */
91772 
91773 /*! @name STAT_USBPHY2 - Slice Status Register */
91774 /*! @{ */
91775 
91776 #define SRC_STAT_USBPHY2_UNDER_RST_MASK          (0x1U)
91777 #define SRC_STAT_USBPHY2_UNDER_RST_SHIFT         (0U)
91778 /*! UNDER_RST
91779  *  0b0..the reset is finished
91780  *  0b1..the reset is in process
91781  */
91782 #define SRC_STAT_USBPHY2_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)
91783 
91784 #define SRC_STAT_USBPHY2_RST_BY_HW_MASK          (0x4U)
91785 #define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT         (2U)
91786 /*! RST_BY_HW
91787  *  0b0..the reset is not caused by the power mode transfer
91788  *  0b1..the reset is caused by the power mode transfer
91789  */
91790 #define SRC_STAT_USBPHY2_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)
91791 
91792 #define SRC_STAT_USBPHY2_RST_BY_SW_MASK          (0x8U)
91793 #define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT         (3U)
91794 /*! RST_BY_SW
91795  *  0b0..the reset is not caused by software setting
91796  *  0b1..the reset is caused by software setting
91797  */
91798 #define SRC_STAT_USBPHY2_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)
91799 /*! @} */
91800 
91801 
91802 /*!
91803  * @}
91804  */ /* end of group SRC_Register_Masks */
91805 
91806 
91807 /* SRC - Peripheral instance base addresses */
91808 /** Peripheral SRC base address */
91809 #define SRC_BASE                                 (0x40C04000u)
91810 /** Peripheral SRC base pointer */
91811 #define SRC                                      ((SRC_Type *)SRC_BASE)
91812 /** Array initializer of SRC peripheral base addresses */
91813 #define SRC_BASE_ADDRS                           { SRC_BASE }
91814 /** Array initializer of SRC peripheral base pointers */
91815 #define SRC_BASE_PTRS                            { SRC }
91816 
91817 /*!
91818  * @}
91819  */ /* end of group SRC_Peripheral_Access_Layer */
91820 
91821 
91822 /* ----------------------------------------------------------------------------
91823    -- SSARC_HP Peripheral Access Layer
91824    ---------------------------------------------------------------------------- */
91825 
91826 /*!
91827  * @addtogroup SSARC_HP_Peripheral_Access_Layer SSARC_HP Peripheral Access Layer
91828  * @{
91829  */
91830 
91831 /** SSARC_HP - Register Layout Typedef */
91832 typedef struct {
91833   struct {                                         /* offset: 0x0, array step: 0x10 */
91834     __IO uint32_t SRAM0;                             /**< Description Address Register, array offset: 0x0, array step: 0x10 */
91835     __IO uint32_t SRAM1;                             /**< Description Data Register, array offset: 0x4, array step: 0x10 */
91836     __IO uint32_t SRAM2;                             /**< Description Control Register, array offset: 0x8, array step: 0x10 */
91837          uint8_t RESERVED_0[4];
91838   } DESC[1024];
91839 } SSARC_HP_Type;
91840 
91841 /* ----------------------------------------------------------------------------
91842    -- SSARC_HP Register Masks
91843    ---------------------------------------------------------------------------- */
91844 
91845 /*!
91846  * @addtogroup SSARC_HP_Register_Masks SSARC_HP Register Masks
91847  * @{
91848  */
91849 
91850 /*! @name SRAM0 - Description Address Register */
91851 /*! @{ */
91852 
91853 #define SSARC_HP_SRAM0_ADDR_MASK                 (0xFFFFFFFFU)
91854 #define SSARC_HP_SRAM0_ADDR_SHIFT                (0U)
91855 /*! ADDR - Address field
91856  */
91857 #define SSARC_HP_SRAM0_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK)
91858 /*! @} */
91859 
91860 /* The count of SSARC_HP_SRAM0 */
91861 #define SSARC_HP_SRAM0_COUNT                     (1024U)
91862 
91863 /*! @name SRAM1 - Description Data Register */
91864 /*! @{ */
91865 
91866 #define SSARC_HP_SRAM1_DATA_MASK                 (0xFFFFFFFFU)
91867 #define SSARC_HP_SRAM1_DATA_SHIFT                (0U)
91868 /*! DATA - Data field
91869  */
91870 #define SSARC_HP_SRAM1_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK)
91871 /*! @} */
91872 
91873 /* The count of SSARC_HP_SRAM1 */
91874 #define SSARC_HP_SRAM1_COUNT                     (1024U)
91875 
91876 /*! @name SRAM2 - Description Control Register */
91877 /*! @{ */
91878 
91879 #define SSARC_HP_SRAM2_TYPE_MASK                 (0x7U)
91880 #define SSARC_HP_SRAM2_TYPE_SHIFT                (0U)
91881 /*! TYPE - Type field
91882  *  0b000..SR
91883  *  0b001..WO
91884  *  0b010..RMW_OR
91885  *  0b011..RMW_AND
91886  *  0b100..DELAY
91887  *  0b101..POLLING_0
91888  *  0b110..POLLING_1
91889  *  0b111..Reserved
91890  */
91891 #define SSARC_HP_SRAM2_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK)
91892 
91893 #define SSARC_HP_SRAM2_SV_EN_MASK                (0x10U)
91894 #define SSARC_HP_SRAM2_SV_EN_SHIFT               (4U)
91895 /*! SV_EN - Save Enable
91896  *  0b0..Do not use this descriptor in the save operation
91897  *  0b1..Use this descriptor in the save operation
91898  */
91899 #define SSARC_HP_SRAM2_SV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK)
91900 
91901 #define SSARC_HP_SRAM2_RT_EN_MASK                (0x20U)
91902 #define SSARC_HP_SRAM2_RT_EN_SHIFT               (5U)
91903 /*! RT_EN - Restore Enable
91904  *  0b0..Do not use this descriptor for the restore operation
91905  *  0b1..Use this descriptor for the restore operation
91906  */
91907 #define SSARC_HP_SRAM2_RT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK)
91908 
91909 #define SSARC_HP_SRAM2_SIZE_MASK                 (0xC0U)
91910 #define SSARC_HP_SRAM2_SIZE_SHIFT                (6U)
91911 /*! SIZE - Size field
91912  *  0b00..8-bit
91913  *  0b01..16-bit
91914  *  0b10..32-bit
91915  *  0b11..Reserved
91916  */
91917 #define SSARC_HP_SRAM2_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK)
91918 /*! @} */
91919 
91920 /* The count of SSARC_HP_SRAM2 */
91921 #define SSARC_HP_SRAM2_COUNT                     (1024U)
91922 
91923 
91924 /*!
91925  * @}
91926  */ /* end of group SSARC_HP_Register_Masks */
91927 
91928 
91929 /* SSARC_HP - Peripheral instance base addresses */
91930 /** Peripheral SSARC_HP base address */
91931 #define SSARC_HP_BASE                            (0x40CB4000u)
91932 /** Peripheral SSARC_HP base pointer */
91933 #define SSARC_HP                                 ((SSARC_HP_Type *)SSARC_HP_BASE)
91934 /** Array initializer of SSARC_HP peripheral base addresses */
91935 #define SSARC_HP_BASE_ADDRS                      { SSARC_HP_BASE }
91936 /** Array initializer of SSARC_HP peripheral base pointers */
91937 #define SSARC_HP_BASE_PTRS                       { SSARC_HP }
91938 
91939 /*!
91940  * @}
91941  */ /* end of group SSARC_HP_Peripheral_Access_Layer */
91942 
91943 
91944 /* ----------------------------------------------------------------------------
91945    -- SSARC_LP Peripheral Access Layer
91946    ---------------------------------------------------------------------------- */
91947 
91948 /*!
91949  * @addtogroup SSARC_LP_Peripheral_Access_Layer SSARC_LP Peripheral Access Layer
91950  * @{
91951  */
91952 
91953 /** SSARC_LP - Register Layout Typedef */
91954 typedef struct {
91955   struct {                                         /* offset: 0x0, array step: 0x20 */
91956     __IO uint32_t DESC_CTRL0;                        /**< Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20 */
91957     __IO uint32_t DESC_CTRL1;                        /**< Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20 */
91958     __IO uint32_t DESC_ADDR_UP;                      /**< Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20 */
91959     __IO uint32_t DESC_ADDR_DOWN;                    /**< Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20 */
91960          uint8_t RESERVED_0[16];
91961   } GROUPS[16];
91962   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x200 */
91963   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x204 */
91964        uint8_t RESERVED_0[4];
91965   __IO uint32_t HP_TIMEOUT;                        /**< HP Timeout Register, offset: 0x20C */
91966        uint8_t RESERVED_1[12];
91967   __I  uint32_t HW_GROUP_PENDING;                  /**< Hardware Request Pending Register, offset: 0x21C */
91968   __I  uint32_t SW_GROUP_PENDING;                  /**< Software Request Pending Register, offset: 0x220 */
91969 } SSARC_LP_Type;
91970 
91971 /* ----------------------------------------------------------------------------
91972    -- SSARC_LP Register Masks
91973    ---------------------------------------------------------------------------- */
91974 
91975 /*!
91976  * @addtogroup SSARC_LP_Register_Masks SSARC_LP Register Masks
91977  * @{
91978  */
91979 
91980 /*! @name DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register */
91981 /*! @{ */
91982 
91983 #define SSARC_LP_DESC_CTRL0_START_MASK           (0x3FFU)
91984 #define SSARC_LP_DESC_CTRL0_START_SHIFT          (0U)
91985 /*! START - Start index
91986  */
91987 #define SSARC_LP_DESC_CTRL0_START(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK)
91988 
91989 #define SSARC_LP_DESC_CTRL0_END_MASK             (0xFFC00U)
91990 #define SSARC_LP_DESC_CTRL0_END_SHIFT            (10U)
91991 /*! END - End index
91992  */
91993 #define SSARC_LP_DESC_CTRL0_END(x)               (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK)
91994 
91995 #define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK        (0x100000U)
91996 #define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT       (20U)
91997 /*! SV_ORDER - Save Order
91998  *  0b0..Descriptors within the group are processed from start to end
91999  *  0b1..Descriptors within the group are processed from end to start
92000  */
92001 #define SSARC_LP_DESC_CTRL0_SV_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK)
92002 
92003 #define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK        (0x200000U)
92004 #define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT       (21U)
92005 /*! RT_ORDER - Restore order
92006  *  0b0..Descriptors within the group are processed from start to end
92007  *  0b1..Descriptors within the group are processed from end to start
92008  */
92009 #define SSARC_LP_DESC_CTRL0_RT_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK)
92010 /*! @} */
92011 
92012 /* The count of SSARC_LP_DESC_CTRL0 */
92013 #define SSARC_LP_DESC_CTRL0_COUNT                (16U)
92014 
92015 /*! @name DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register */
92016 /*! @{ */
92017 
92018 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK      (0x1U)
92019 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT     (0U)
92020 /*! SW_TRIG_SV - Software trigger save
92021  *  0b1..Request a software save operation/software restore operation in progress
92022  *  0b0..No software save request/software restore request complete
92023  */
92024 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK)
92025 
92026 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK      (0x2U)
92027 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT     (1U)
92028 /*! SW_TRIG_RT - Software trigger restore
92029  *  0b1..Request a software restore operation/software restore operation in progress
92030  *  0b0..No software restore request/software restore request complete
92031  */
92032 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK)
92033 
92034 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK    (0x70U)
92035 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT   (4U)
92036 /*! POWER_DOMAIN
92037  *  0b000..PGMC_BPC0
92038  *  0b001..PGMC_BPC1
92039  *  0b010..PGMC_BPC2
92040  *  0b011..PGMC_BPC3
92041  *  0b100..PGMC_BPC4
92042  *  0b101..PGMC_BPC5
92043  *  0b110..PGMC_BPC6
92044  *  0b111..PGMC_BPC7
92045  */
92046 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK)
92047 
92048 #define SSARC_LP_DESC_CTRL1_GP_EN_MASK           (0x80U)
92049 #define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT          (7U)
92050 /*! GP_EN - Group Enable
92051  *  0b0..Group disabled
92052  *  0b1..Group enabled
92053  */
92054 #define SSARC_LP_DESC_CTRL1_GP_EN(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK)
92055 
92056 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK     (0xF00U)
92057 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT    (8U)
92058 /*! SV_PRIORITY - Save Priority
92059  */
92060 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK)
92061 
92062 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK     (0xF000U)
92063 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT    (12U)
92064 /*! RT_PRIORITY - Restore Priority
92065  */
92066 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK)
92067 
92068 #define SSARC_LP_DESC_CTRL1_CPUD_MASK            (0x30000U)
92069 #define SSARC_LP_DESC_CTRL1_CPUD_SHIFT           (16U)
92070 /*! CPUD - CPU Domain
92071  */
92072 #define SSARC_LP_DESC_CTRL1_CPUD(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK)
92073 
92074 #define SSARC_LP_DESC_CTRL1_RL_MASK              (0x40000U)
92075 #define SSARC_LP_DESC_CTRL1_RL_SHIFT             (18U)
92076 /*! RL - Read Lock
92077  *  0b1..Group is locked (read access not allowed)
92078  *  0b0..Group is unlocked (read access allowed)
92079  */
92080 #define SSARC_LP_DESC_CTRL1_RL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK)
92081 
92082 #define SSARC_LP_DESC_CTRL1_WL_MASK              (0x80000U)
92083 #define SSARC_LP_DESC_CTRL1_WL_SHIFT             (19U)
92084 /*! WL - Write Lock
92085  *  0b1..Group is locked (write access not allowed)
92086  *  0b0..Group is unlocked (write access allowed)
92087  */
92088 #define SSARC_LP_DESC_CTRL1_WL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK)
92089 
92090 #define SSARC_LP_DESC_CTRL1_DL_MASK              (0x100000U)
92091 #define SSARC_LP_DESC_CTRL1_DL_SHIFT             (20U)
92092 /*! DL - Domain lock
92093  *  0b1..Lock
92094  *  0b0..Unlock
92095  */
92096 #define SSARC_LP_DESC_CTRL1_DL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK)
92097 /*! @} */
92098 
92099 /* The count of SSARC_LP_DESC_CTRL1 */
92100 #define SSARC_LP_DESC_CTRL1_COUNT                (16U)
92101 
92102 /*! @name DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register */
92103 /*! @{ */
92104 
92105 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK       (0xFFFFFFFFU)
92106 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT      (0U)
92107 /*! ADDR_UP - Address field (High)
92108  */
92109 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK)
92110 /*! @} */
92111 
92112 /* The count of SSARC_LP_DESC_ADDR_UP */
92113 #define SSARC_LP_DESC_ADDR_UP_COUNT              (16U)
92114 
92115 /*! @name DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register */
92116 /*! @{ */
92117 
92118 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK   (0xFFFFFFFFU)
92119 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT  (0U)
92120 /*! ADDR_DOWN - Address field (Low)
92121  */
92122 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK)
92123 /*! @} */
92124 
92125 /* The count of SSARC_LP_DESC_ADDR_DOWN */
92126 #define SSARC_LP_DESC_ADDR_DOWN_COUNT            (16U)
92127 
92128 /*! @name CTRL - Control Register */
92129 /*! @{ */
92130 
92131 #define SSARC_LP_CTRL_DIS_HW_REQ_MASK            (0x8000000U)
92132 #define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT           (27U)
92133 /*! DIS_HW_REQ - Save/Restore request disable
92134  *  0b0..PGMC save/restore requests enabled
92135  *  0b1..PGMC save/restore requests disabled
92136  */
92137 #define SSARC_LP_CTRL_DIS_HW_REQ(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
92138 
92139 #define SSARC_LP_CTRL_SW_RESET_MASK              (0x80000000U)
92140 #define SSARC_LP_CTRL_SW_RESET_SHIFT             (31U)
92141 /*! SW_RESET - Software reset
92142  */
92143 #define SSARC_LP_CTRL_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)
92144 /*! @} */
92145 
92146 /*! @name INT_STATUS - Interrupt Status Register */
92147 /*! @{ */
92148 
92149 #define SSARC_LP_INT_STATUS_ERR_INDEX_MASK       (0x3FFU)
92150 #define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT      (0U)
92151 /*! ERR_INDEX - Error Index
92152  */
92153 #define SSARC_LP_INT_STATUS_ERR_INDEX(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK)
92154 
92155 #define SSARC_LP_INT_STATUS_AHB_RESP_MASK        (0xC00U)
92156 #define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT       (10U)
92157 /*! AHB_RESP - AHB Bus response field
92158  */
92159 #define SSARC_LP_INT_STATUS_AHB_RESP(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK)
92160 
92161 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK  (0x8000000U)
92162 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U)
92163 /*! GROUP_CONFLICT - Group Conflict field
92164  *  0b1..A group conflict error has occurred
92165  *  0b0..No group conflict error
92166  */
92167 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x)    (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
92168 
92169 #define SSARC_LP_INT_STATUS_TIMEOUT_MASK         (0x10000000U)
92170 #define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT        (28U)
92171 /*! TIMEOUT - Timeout field
92172  *  0b1..A timeout event has occurred
92173  *  0b0..No timeout event
92174  */
92175 #define SSARC_LP_INT_STATUS_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK)
92176 
92177 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK     (0x20000000U)
92178 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT    (29U)
92179 /*! SW_REQ_DONE - Software Request Done
92180  *  0b1..Atleast one software triggered has been complete
92181  *  0b0..No software triggered requests or software triggered request still in progress
92182  */
92183 #define SSARC_LP_INT_STATUS_SW_REQ_DONE(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK)
92184 
92185 #define SSARC_LP_INT_STATUS_AHB_ERR_MASK         (0x40000000U)
92186 #define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT        (30U)
92187 /*! AHB_ERR - AHB Error field
92188  *  0b1..An AHB error has occurred
92189  *  0b0..No AHB error
92190  */
92191 #define SSARC_LP_INT_STATUS_AHB_ERR(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK)
92192 
92193 #define SSARC_LP_INT_STATUS_ADDR_ERR_MASK        (0x80000000U)
92194 #define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT       (31U)
92195 /*! ADDR_ERR - Address Error field
92196  *  0b1..An address error has occurred
92197  *  0b0..No address error
92198  */
92199 #define SSARC_LP_INT_STATUS_ADDR_ERR(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK)
92200 /*! @} */
92201 
92202 /*! @name HP_TIMEOUT - HP Timeout Register */
92203 /*! @{ */
92204 
92205 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK   (0xFFFFFFFFU)
92206 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT  (0U)
92207 /*! TIMEOUT_VALUE - Time out value
92208  */
92209 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK)
92210 /*! @} */
92211 
92212 /*! @name HW_GROUP_PENDING - Hardware Request Pending Register */
92213 /*! @{ */
92214 
92215 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU)
92216 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U)
92217 /*! HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request
92218  */
92219 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK)
92220 
92221 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U)
92222 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U)
92223 /*! HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request
92224  */
92225 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK)
92226 /*! @} */
92227 
92228 /*! @name SW_GROUP_PENDING - Software Request Pending Register */
92229 /*! @{ */
92230 
92231 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU)
92232 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U)
92233 /*! SW_SAVE_PENDING - This field indicates which groups are pending for save from software request
92234  */
92235 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK)
92236 
92237 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U)
92238 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U)
92239 /*! SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request
92240  */
92241 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK)
92242 /*! @} */
92243 
92244 
92245 /*!
92246  * @}
92247  */ /* end of group SSARC_LP_Register_Masks */
92248 
92249 
92250 /* SSARC_LP - Peripheral instance base addresses */
92251 /** Peripheral SSARC_LP base address */
92252 #define SSARC_LP_BASE                            (0x40CB8000u)
92253 /** Peripheral SSARC_LP base pointer */
92254 #define SSARC_LP                                 ((SSARC_LP_Type *)SSARC_LP_BASE)
92255 /** Array initializer of SSARC_LP peripheral base addresses */
92256 #define SSARC_LP_BASE_ADDRS                      { SSARC_LP_BASE }
92257 /** Array initializer of SSARC_LP peripheral base pointers */
92258 #define SSARC_LP_BASE_PTRS                       { SSARC_LP }
92259 
92260 /*!
92261  * @}
92262  */ /* end of group SSARC_LP_Peripheral_Access_Layer */
92263 
92264 
92265 /* ----------------------------------------------------------------------------
92266    -- TMPSNS Peripheral Access Layer
92267    ---------------------------------------------------------------------------- */
92268 
92269 /*!
92270  * @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer
92271  * @{
92272  */
92273 
92274 /** TMPSNS - Register Layout Typedef */
92275 typedef struct {
92276   __IO uint32_t CTRL0;                             /**< Temperature Sensor Control Register 0, offset: 0x0 */
92277   __IO uint32_t CTRL0_SET;                         /**< Temperature Sensor Control Register 0, offset: 0x4 */
92278   __IO uint32_t CTRL0_CLR;                         /**< Temperature Sensor Control Register 0, offset: 0x8 */
92279   __IO uint32_t CTRL0_TOG;                         /**< Temperature Sensor Control Register 0, offset: 0xC */
92280   __IO uint32_t CTRL1;                             /**< Temperature Sensor Control Register 1, offset: 0x10 */
92281   __IO uint32_t CTRL1_SET;                         /**< Temperature Sensor Control Register 1, offset: 0x14 */
92282   __IO uint32_t CTRL1_CLR;                         /**< Temperature Sensor Control Register 1, offset: 0x18 */
92283   __IO uint32_t CTRL1_TOG;                         /**< Temperature Sensor Control Register 1, offset: 0x1C */
92284   __IO uint32_t RANGE0;                            /**< Temperature Sensor Range Register 0, offset: 0x20 */
92285   __IO uint32_t RANGE0_SET;                        /**< Temperature Sensor Range Register 0, offset: 0x24 */
92286   __IO uint32_t RANGE0_CLR;                        /**< Temperature Sensor Range Register 0, offset: 0x28 */
92287   __IO uint32_t RANGE0_TOG;                        /**< Temperature Sensor Range Register 0, offset: 0x2C */
92288   __IO uint32_t RANGE1;                            /**< Temperature Sensor Range Register 1, offset: 0x30 */
92289   __IO uint32_t RANGE1_SET;                        /**< Temperature Sensor Range Register 1, offset: 0x34 */
92290   __IO uint32_t RANGE1_CLR;                        /**< Temperature Sensor Range Register 1, offset: 0x38 */
92291   __IO uint32_t RANGE1_TOG;                        /**< Temperature Sensor Range Register 1, offset: 0x3C */
92292        uint8_t RESERVED_0[16];
92293   __IO uint32_t STATUS0;                           /**< Temperature Sensor Status Register 0, offset: 0x50 */
92294 } TMPSNS_Type;
92295 
92296 /* ----------------------------------------------------------------------------
92297    -- TMPSNS Register Masks
92298    ---------------------------------------------------------------------------- */
92299 
92300 /*!
92301  * @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks
92302  * @{
92303  */
92304 
92305 /*! @name CTRL0 - Temperature Sensor Control Register 0 */
92306 /*! @{ */
92307 
92308 #define TMPSNS_CTRL0_SLOPE_CAL_MASK              (0x3FU)
92309 #define TMPSNS_CTRL0_SLOPE_CAL_SHIFT             (0U)
92310 /*! SLOPE_CAL - Ramp slope calibration control
92311  */
92312 #define TMPSNS_CTRL0_SLOPE_CAL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK)
92313 
92314 #define TMPSNS_CTRL0_V_SEL_MASK                  (0x300U)
92315 #define TMPSNS_CTRL0_V_SEL_SHIFT                 (8U)
92316 /*! V_SEL - Voltage Select
92317  *  0b00..Normal temperature measuring mode
92318  *  0b01-0b10..Reserved
92319  */
92320 #define TMPSNS_CTRL0_V_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK)
92321 
92322 #define TMPSNS_CTRL0_IBIAS_TRIM_MASK             (0xF000U)
92323 #define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT            (12U)
92324 /*! IBIAS_TRIM - Current bias trim value
92325  */
92326 #define TMPSNS_CTRL0_IBIAS_TRIM(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK)
92327 /*! @} */
92328 
92329 /*! @name CTRL0_SET - Temperature Sensor Control Register 0 */
92330 /*! @{ */
92331 
92332 #define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK          (0x3FU)
92333 #define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT         (0U)
92334 /*! SLOPE_CAL - Ramp slope calibration control
92335  */
92336 #define TMPSNS_CTRL0_SET_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK)
92337 
92338 #define TMPSNS_CTRL0_SET_V_SEL_MASK              (0x300U)
92339 #define TMPSNS_CTRL0_SET_V_SEL_SHIFT             (8U)
92340 /*! V_SEL - Voltage Select
92341  */
92342 #define TMPSNS_CTRL0_SET_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK)
92343 
92344 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK         (0xF000U)
92345 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT        (12U)
92346 /*! IBIAS_TRIM - Current bias trim value
92347  */
92348 #define TMPSNS_CTRL0_SET_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK)
92349 /*! @} */
92350 
92351 /*! @name CTRL0_CLR - Temperature Sensor Control Register 0 */
92352 /*! @{ */
92353 
92354 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK          (0x3FU)
92355 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT         (0U)
92356 /*! SLOPE_CAL - Ramp slope calibration control
92357  */
92358 #define TMPSNS_CTRL0_CLR_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK)
92359 
92360 #define TMPSNS_CTRL0_CLR_V_SEL_MASK              (0x300U)
92361 #define TMPSNS_CTRL0_CLR_V_SEL_SHIFT             (8U)
92362 /*! V_SEL - Voltage Select
92363  */
92364 #define TMPSNS_CTRL0_CLR_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK)
92365 
92366 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK         (0xF000U)
92367 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT        (12U)
92368 /*! IBIAS_TRIM - Current bias trim value
92369  */
92370 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK)
92371 /*! @} */
92372 
92373 /*! @name CTRL0_TOG - Temperature Sensor Control Register 0 */
92374 /*! @{ */
92375 
92376 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK          (0x3FU)
92377 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT         (0U)
92378 /*! SLOPE_CAL - Ramp slope calibration control
92379  */
92380 #define TMPSNS_CTRL0_TOG_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK)
92381 
92382 #define TMPSNS_CTRL0_TOG_V_SEL_MASK              (0x300U)
92383 #define TMPSNS_CTRL0_TOG_V_SEL_SHIFT             (8U)
92384 /*! V_SEL - Voltage Select
92385  */
92386 #define TMPSNS_CTRL0_TOG_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK)
92387 
92388 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK         (0xF000U)
92389 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT        (12U)
92390 /*! IBIAS_TRIM - Current bias trim value
92391  */
92392 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK)
92393 /*! @} */
92394 
92395 /*! @name CTRL1 - Temperature Sensor Control Register 1 */
92396 /*! @{ */
92397 
92398 #define TMPSNS_CTRL1_FREQ_MASK                   (0xFFFFU)
92399 #define TMPSNS_CTRL1_FREQ_SHIFT                  (0U)
92400 /*! FREQ - Temperature Measurement Frequency
92401  *  0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0.
92402  *  0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
92403  */
92404 #define TMPSNS_CTRL1_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
92405 
92406 #define TMPSNS_CTRL1_FINISH_IE_MASK              (0x10000U)
92407 #define TMPSNS_CTRL1_FINISH_IE_SHIFT             (16U)
92408 /*! FINISH_IE - Measurement finished interrupt enable
92409  *  0b0..Interrupt is disabled
92410  *  0b1..Interrupt is enabled
92411  */
92412 #define TMPSNS_CTRL1_FINISH_IE(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
92413 
92414 #define TMPSNS_CTRL1_LOW_TEMP_IE_MASK            (0x20000U)
92415 #define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT           (17U)
92416 /*! LOW_TEMP_IE - Low temperature interrupt enable
92417  *  0b0..Interrupt is disabled
92418  *  0b1..Interrupt is enabled
92419  */
92420 #define TMPSNS_CTRL1_LOW_TEMP_IE(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
92421 
92422 #define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK           (0x40000U)
92423 #define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT          (18U)
92424 /*! HIGH_TEMP_IE - High temperature interrupt enable
92425  *  0b0..Interrupt is disabled
92426  *  0b1..Interrupt is enabled
92427  */
92428 #define TMPSNS_CTRL1_HIGH_TEMP_IE(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
92429 
92430 #define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK          (0x80000U)
92431 #define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT         (19U)
92432 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92433  *  0b0..Interrupt is disabled
92434  *  0b1..Interrupt is enabled
92435  */
92436 #define TMPSNS_CTRL1_PANIC_TEMP_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
92437 
92438 #define TMPSNS_CTRL1_START_MASK                  (0x400000U)
92439 #define TMPSNS_CTRL1_START_SHIFT                 (22U)
92440 /*! START - Start Temperature Measurement
92441  *  0b0..No new temperature reading taken
92442  *  0b1..Initiate a new temperature reading
92443  */
92444 #define TMPSNS_CTRL1_START(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
92445 
92446 #define TMPSNS_CTRL1_PWD_MASK                    (0x800000U)
92447 #define TMPSNS_CTRL1_PWD_SHIFT                   (23U)
92448 /*! PWD - Temperature Sensor Power Down
92449  *  0b0..Sensor is active
92450  *  0b1..Sensor is powered down
92451  */
92452 #define TMPSNS_CTRL1_PWD(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
92453 
92454 #define TMPSNS_CTRL1_RFU_MASK                    (0x7F000000U)
92455 #define TMPSNS_CTRL1_RFU_SHIFT                   (24U)
92456 /*! RFU - Read/Writeable field. Reserved for future use
92457  */
92458 #define TMPSNS_CTRL1_RFU(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK)
92459 
92460 #define TMPSNS_CTRL1_PWD_FULL_MASK               (0x80000000U)
92461 #define TMPSNS_CTRL1_PWD_FULL_SHIFT              (31U)
92462 /*! PWD_FULL - Temperature Sensor Full Power Down
92463  *  0b0..Sensor is active
92464  *  0b1..Sensor is powered down
92465  */
92466 #define TMPSNS_CTRL1_PWD_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
92467 /*! @} */
92468 
92469 /*! @name CTRL1_SET - Temperature Sensor Control Register 1 */
92470 /*! @{ */
92471 
92472 #define TMPSNS_CTRL1_SET_FREQ_MASK               (0xFFFFU)
92473 #define TMPSNS_CTRL1_SET_FREQ_SHIFT              (0U)
92474 /*! FREQ - Temperature Measurement Frequency
92475  */
92476 #define TMPSNS_CTRL1_SET_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
92477 
92478 #define TMPSNS_CTRL1_SET_FINISH_IE_MASK          (0x10000U)
92479 #define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT         (16U)
92480 /*! FINISH_IE - Measurement finished interrupt enable
92481  */
92482 #define TMPSNS_CTRL1_SET_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
92483 
92484 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK        (0x20000U)
92485 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT       (17U)
92486 /*! LOW_TEMP_IE - Low temperature interrupt enable
92487  */
92488 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
92489 
92490 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK       (0x40000U)
92491 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT      (18U)
92492 /*! HIGH_TEMP_IE - High temperature interrupt enable
92493  */
92494 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
92495 
92496 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK      (0x80000U)
92497 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT     (19U)
92498 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92499  */
92500 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
92501 
92502 #define TMPSNS_CTRL1_SET_START_MASK              (0x400000U)
92503 #define TMPSNS_CTRL1_SET_START_SHIFT             (22U)
92504 /*! START - Start Temperature Measurement
92505  */
92506 #define TMPSNS_CTRL1_SET_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
92507 
92508 #define TMPSNS_CTRL1_SET_PWD_MASK                (0x800000U)
92509 #define TMPSNS_CTRL1_SET_PWD_SHIFT               (23U)
92510 /*! PWD - Temperature Sensor Power Down
92511  */
92512 #define TMPSNS_CTRL1_SET_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
92513 
92514 #define TMPSNS_CTRL1_SET_RFU_MASK                (0x7F000000U)
92515 #define TMPSNS_CTRL1_SET_RFU_SHIFT               (24U)
92516 /*! RFU - Read/Writeable field. Reserved for future use
92517  */
92518 #define TMPSNS_CTRL1_SET_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK)
92519 
92520 #define TMPSNS_CTRL1_SET_PWD_FULL_MASK           (0x80000000U)
92521 #define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT          (31U)
92522 /*! PWD_FULL - Temperature Sensor Full Power Down
92523  */
92524 #define TMPSNS_CTRL1_SET_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
92525 /*! @} */
92526 
92527 /*! @name CTRL1_CLR - Temperature Sensor Control Register 1 */
92528 /*! @{ */
92529 
92530 #define TMPSNS_CTRL1_CLR_FREQ_MASK               (0xFFFFU)
92531 #define TMPSNS_CTRL1_CLR_FREQ_SHIFT              (0U)
92532 /*! FREQ - Temperature Measurement Frequency
92533  */
92534 #define TMPSNS_CTRL1_CLR_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
92535 
92536 #define TMPSNS_CTRL1_CLR_FINISH_IE_MASK          (0x10000U)
92537 #define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT         (16U)
92538 /*! FINISH_IE - Measurement finished interrupt enable
92539  */
92540 #define TMPSNS_CTRL1_CLR_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
92541 
92542 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK        (0x20000U)
92543 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT       (17U)
92544 /*! LOW_TEMP_IE - Low temperature interrupt enable
92545  */
92546 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
92547 
92548 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK       (0x40000U)
92549 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT      (18U)
92550 /*! HIGH_TEMP_IE - High temperature interrupt enable
92551  */
92552 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
92553 
92554 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK      (0x80000U)
92555 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT     (19U)
92556 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92557  */
92558 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
92559 
92560 #define TMPSNS_CTRL1_CLR_START_MASK              (0x400000U)
92561 #define TMPSNS_CTRL1_CLR_START_SHIFT             (22U)
92562 /*! START - Start Temperature Measurement
92563  */
92564 #define TMPSNS_CTRL1_CLR_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
92565 
92566 #define TMPSNS_CTRL1_CLR_PWD_MASK                (0x800000U)
92567 #define TMPSNS_CTRL1_CLR_PWD_SHIFT               (23U)
92568 /*! PWD - Temperature Sensor Power Down
92569  */
92570 #define TMPSNS_CTRL1_CLR_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
92571 
92572 #define TMPSNS_CTRL1_CLR_RFU_MASK                (0x7F000000U)
92573 #define TMPSNS_CTRL1_CLR_RFU_SHIFT               (24U)
92574 /*! RFU - Read/Writeable field. Reserved for future use
92575  */
92576 #define TMPSNS_CTRL1_CLR_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK)
92577 
92578 #define TMPSNS_CTRL1_CLR_PWD_FULL_MASK           (0x80000000U)
92579 #define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT          (31U)
92580 /*! PWD_FULL - Temperature Sensor Full Power Down
92581  */
92582 #define TMPSNS_CTRL1_CLR_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
92583 /*! @} */
92584 
92585 /*! @name CTRL1_TOG - Temperature Sensor Control Register 1 */
92586 /*! @{ */
92587 
92588 #define TMPSNS_CTRL1_TOG_FREQ_MASK               (0xFFFFU)
92589 #define TMPSNS_CTRL1_TOG_FREQ_SHIFT              (0U)
92590 /*! FREQ - Temperature Measurement Frequency
92591  */
92592 #define TMPSNS_CTRL1_TOG_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
92593 
92594 #define TMPSNS_CTRL1_TOG_FINISH_IE_MASK          (0x10000U)
92595 #define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT         (16U)
92596 /*! FINISH_IE - Measurement finished interrupt enable
92597  */
92598 #define TMPSNS_CTRL1_TOG_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
92599 
92600 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK        (0x20000U)
92601 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT       (17U)
92602 /*! LOW_TEMP_IE - Low temperature interrupt enable
92603  */
92604 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
92605 
92606 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK       (0x40000U)
92607 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT      (18U)
92608 /*! HIGH_TEMP_IE - High temperature interrupt enable
92609  */
92610 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
92611 
92612 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK      (0x80000U)
92613 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT     (19U)
92614 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92615  */
92616 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
92617 
92618 #define TMPSNS_CTRL1_TOG_START_MASK              (0x400000U)
92619 #define TMPSNS_CTRL1_TOG_START_SHIFT             (22U)
92620 /*! START - Start Temperature Measurement
92621  */
92622 #define TMPSNS_CTRL1_TOG_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
92623 
92624 #define TMPSNS_CTRL1_TOG_PWD_MASK                (0x800000U)
92625 #define TMPSNS_CTRL1_TOG_PWD_SHIFT               (23U)
92626 /*! PWD - Temperature Sensor Power Down
92627  */
92628 #define TMPSNS_CTRL1_TOG_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
92629 
92630 #define TMPSNS_CTRL1_TOG_RFU_MASK                (0x7F000000U)
92631 #define TMPSNS_CTRL1_TOG_RFU_SHIFT               (24U)
92632 /*! RFU - Read/Writeable field. Reserved for future use
92633  */
92634 #define TMPSNS_CTRL1_TOG_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK)
92635 
92636 #define TMPSNS_CTRL1_TOG_PWD_FULL_MASK           (0x80000000U)
92637 #define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT          (31U)
92638 /*! PWD_FULL - Temperature Sensor Full Power Down
92639  */
92640 #define TMPSNS_CTRL1_TOG_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
92641 /*! @} */
92642 
92643 /*! @name RANGE0 - Temperature Sensor Range Register 0 */
92644 /*! @{ */
92645 
92646 #define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK          (0xFFFU)
92647 #define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT         (0U)
92648 /*! LOW_TEMP_VAL - Low temperature threshold value
92649  */
92650 #define TMPSNS_RANGE0_LOW_TEMP_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
92651 
92652 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK         (0xFFF0000U)
92653 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT        (16U)
92654 /*! HIGH_TEMP_VAL - High temperature threshold value
92655  */
92656 #define TMPSNS_RANGE0_HIGH_TEMP_VAL(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
92657 /*! @} */
92658 
92659 /*! @name RANGE0_SET - Temperature Sensor Range Register 0 */
92660 /*! @{ */
92661 
92662 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK      (0xFFFU)
92663 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT     (0U)
92664 /*! LOW_TEMP_VAL - Low temperature threshold value
92665  */
92666 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
92667 
92668 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92669 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT    (16U)
92670 /*! HIGH_TEMP_VAL - High temperature threshold value
92671  */
92672 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
92673 /*! @} */
92674 
92675 /*! @name RANGE0_CLR - Temperature Sensor Range Register 0 */
92676 /*! @{ */
92677 
92678 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK      (0xFFFU)
92679 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT     (0U)
92680 /*! LOW_TEMP_VAL - Low temperature threshold value
92681  */
92682 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
92683 
92684 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92685 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT    (16U)
92686 /*! HIGH_TEMP_VAL - High temperature threshold value
92687  */
92688 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
92689 /*! @} */
92690 
92691 /*! @name RANGE0_TOG - Temperature Sensor Range Register 0 */
92692 /*! @{ */
92693 
92694 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK      (0xFFFU)
92695 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT     (0U)
92696 /*! LOW_TEMP_VAL - Low temperature threshold value
92697  */
92698 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
92699 
92700 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92701 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT    (16U)
92702 /*! HIGH_TEMP_VAL - High temperature threshold value
92703  */
92704 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
92705 /*! @} */
92706 
92707 /*! @name RANGE1 - Temperature Sensor Range Register 1 */
92708 /*! @{ */
92709 
92710 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK        (0xFFFU)
92711 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT       (0U)
92712 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92713  */
92714 #define TMPSNS_RANGE1_PANIC_TEMP_VAL(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
92715 /*! @} */
92716 
92717 /*! @name RANGE1_SET - Temperature Sensor Range Register 1 */
92718 /*! @{ */
92719 
92720 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK    (0xFFFU)
92721 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT   (0U)
92722 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92723  */
92724 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
92725 /*! @} */
92726 
92727 /*! @name RANGE1_CLR - Temperature Sensor Range Register 1 */
92728 /*! @{ */
92729 
92730 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK    (0xFFFU)
92731 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT   (0U)
92732 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92733  */
92734 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
92735 /*! @} */
92736 
92737 /*! @name RANGE1_TOG - Temperature Sensor Range Register 1 */
92738 /*! @{ */
92739 
92740 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK    (0xFFFU)
92741 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT   (0U)
92742 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92743  */
92744 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
92745 /*! @} */
92746 
92747 /*! @name STATUS0 - Temperature Sensor Status Register 0 */
92748 /*! @{ */
92749 
92750 #define TMPSNS_STATUS0_TEMP_VAL_MASK             (0xFFFU)
92751 #define TMPSNS_STATUS0_TEMP_VAL_SHIFT            (0U)
92752 /*! TEMP_VAL - Measured temperature value
92753  */
92754 #define TMPSNS_STATUS0_TEMP_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
92755 
92756 #define TMPSNS_STATUS0_FINISH_MASK               (0x10000U)
92757 #define TMPSNS_STATUS0_FINISH_SHIFT              (16U)
92758 /*! FINISH - Temperature measurement complete
92759  *  0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0)
92760  *  0b1..Temperature reading is complete and new temperature value available for reading
92761  */
92762 #define TMPSNS_STATUS0_FINISH(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
92763 
92764 #define TMPSNS_STATUS0_LOW_TEMP_MASK             (0x20000U)
92765 #define TMPSNS_STATUS0_LOW_TEMP_SHIFT            (17U)
92766 /*! LOW_TEMP - Low temperature alarm bit
92767  *  0b0..No Low temperature alert
92768  *  0b1..Low temperature alert
92769  */
92770 #define TMPSNS_STATUS0_LOW_TEMP(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
92771 
92772 #define TMPSNS_STATUS0_HIGH_TEMP_MASK            (0x40000U)
92773 #define TMPSNS_STATUS0_HIGH_TEMP_SHIFT           (18U)
92774 /*! HIGH_TEMP - High temperature alarm bit
92775  *  0b0..No High temperature alert
92776  *  0b1..High temperature alert
92777  */
92778 #define TMPSNS_STATUS0_HIGH_TEMP(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
92779 
92780 #define TMPSNS_STATUS0_PANIC_TEMP_MASK           (0x80000U)
92781 #define TMPSNS_STATUS0_PANIC_TEMP_SHIFT          (19U)
92782 /*! PANIC_TEMP - Panic temperature alarm bit
92783  *  0b0..No Panic temperature alert
92784  *  0b1..Panic temperature alert
92785  */
92786 #define TMPSNS_STATUS0_PANIC_TEMP(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK)
92787 /*! @} */
92788 
92789 
92790 /*!
92791  * @}
92792  */ /* end of group TMPSNS_Register_Masks */
92793 
92794 
92795 /* TMPSNS - Peripheral instance base addresses */
92796 /** Peripheral TMPSNS base address */
92797 #define TMPSNS_BASE                              (0u)
92798 /** Peripheral TMPSNS base pointer */
92799 #define TMPSNS                                   ((TMPSNS_Type *)TMPSNS_BASE)
92800 /** Array initializer of TMPSNS peripheral base addresses */
92801 #define TMPSNS_BASE_ADDRS                        { TMPSNS_BASE }
92802 /** Array initializer of TMPSNS peripheral base pointers */
92803 #define TMPSNS_BASE_PTRS                         { TMPSNS }
92804 
92805 /*!
92806  * @}
92807  */ /* end of group TMPSNS_Peripheral_Access_Layer */
92808 
92809 
92810 /* ----------------------------------------------------------------------------
92811    -- TMR Peripheral Access Layer
92812    ---------------------------------------------------------------------------- */
92813 
92814 /*!
92815  * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
92816  * @{
92817  */
92818 
92819 /** TMR - Register Layout Typedef */
92820 typedef struct {
92821   struct {                                         /* offset: 0x0, array step: 0x20 */
92822     __IO uint16_t COMP1;                             /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
92823     __IO uint16_t COMP2;                             /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
92824     __IO uint16_t CAPT;                              /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
92825     __IO uint16_t LOAD;                              /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
92826     __IO uint16_t HOLD;                              /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
92827     __IO uint16_t CNTR;                              /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
92828     __IO uint16_t CTRL;                              /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
92829     __IO uint16_t SCTRL;                             /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
92830     __IO uint16_t CMPLD1;                            /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
92831     __IO uint16_t CMPLD2;                            /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
92832     __IO uint16_t CSCTRL;                            /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
92833     __IO uint16_t FILT;                              /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
92834     __IO uint16_t DMA;                               /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
92835          uint8_t RESERVED_0[4];
92836     __IO uint16_t ENBL;                              /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
92837   } CHANNEL[4];
92838 } TMR_Type;
92839 
92840 /* ----------------------------------------------------------------------------
92841    -- TMR Register Masks
92842    ---------------------------------------------------------------------------- */
92843 
92844 /*!
92845  * @addtogroup TMR_Register_Masks TMR Register Masks
92846  * @{
92847  */
92848 
92849 /*! @name COMP1 - Timer Channel Compare Register 1 */
92850 /*! @{ */
92851 
92852 #define TMR_COMP1_COMPARISON_1_MASK              (0xFFFFU)
92853 #define TMR_COMP1_COMPARISON_1_SHIFT             (0U)
92854 /*! COMPARISON_1 - Comparison Value 1
92855  */
92856 #define TMR_COMP1_COMPARISON_1(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
92857 /*! @} */
92858 
92859 /* The count of TMR_COMP1 */
92860 #define TMR_COMP1_COUNT                          (4U)
92861 
92862 /*! @name COMP2 - Timer Channel Compare Register 2 */
92863 /*! @{ */
92864 
92865 #define TMR_COMP2_COMPARISON_2_MASK              (0xFFFFU)
92866 #define TMR_COMP2_COMPARISON_2_SHIFT             (0U)
92867 /*! COMPARISON_2 - Comparison Value 2
92868  */
92869 #define TMR_COMP2_COMPARISON_2(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
92870 /*! @} */
92871 
92872 /* The count of TMR_COMP2 */
92873 #define TMR_COMP2_COUNT                          (4U)
92874 
92875 /*! @name CAPT - Timer Channel Capture Register */
92876 /*! @{ */
92877 
92878 #define TMR_CAPT_CAPTURE_MASK                    (0xFFFFU)
92879 #define TMR_CAPT_CAPTURE_SHIFT                   (0U)
92880 /*! CAPTURE - Capture Value
92881  */
92882 #define TMR_CAPT_CAPTURE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
92883 /*! @} */
92884 
92885 /* The count of TMR_CAPT */
92886 #define TMR_CAPT_COUNT                           (4U)
92887 
92888 /*! @name LOAD - Timer Channel Load Register */
92889 /*! @{ */
92890 
92891 #define TMR_LOAD_LOAD_MASK                       (0xFFFFU)
92892 #define TMR_LOAD_LOAD_SHIFT                      (0U)
92893 /*! LOAD - Timer Load Register
92894  */
92895 #define TMR_LOAD_LOAD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
92896 /*! @} */
92897 
92898 /* The count of TMR_LOAD */
92899 #define TMR_LOAD_COUNT                           (4U)
92900 
92901 /*! @name HOLD - Timer Channel Hold Register */
92902 /*! @{ */
92903 
92904 #define TMR_HOLD_HOLD_MASK                       (0xFFFFU)
92905 #define TMR_HOLD_HOLD_SHIFT                      (0U)
92906 /*! HOLD - HOLD
92907  */
92908 #define TMR_HOLD_HOLD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
92909 /*! @} */
92910 
92911 /* The count of TMR_HOLD */
92912 #define TMR_HOLD_COUNT                           (4U)
92913 
92914 /*! @name CNTR - Timer Channel Counter Register */
92915 /*! @{ */
92916 
92917 #define TMR_CNTR_COUNTER_MASK                    (0xFFFFU)
92918 #define TMR_CNTR_COUNTER_SHIFT                   (0U)
92919 /*! COUNTER - COUNTER
92920  */
92921 #define TMR_CNTR_COUNTER(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
92922 /*! @} */
92923 
92924 /* The count of TMR_CNTR */
92925 #define TMR_CNTR_COUNT                           (4U)
92926 
92927 /*! @name CTRL - Timer Channel Control Register */
92928 /*! @{ */
92929 
92930 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
92931 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
92932 /*! OUTMODE - Output Mode
92933  *  0b000..Asserted while counter is active
92934  *  0b001..Clear OFLAG output on successful compare
92935  *  0b010..Set OFLAG output on successful compare
92936  *  0b011..Toggle OFLAG output on successful compare
92937  *  0b100..Toggle OFLAG output using alternating compare registers
92938  *  0b101..Set on compare, cleared on secondary source input edge
92939  *  0b110..Set on compare, cleared on counter rollover
92940  *  0b111..Enable gated clock output while counter is active
92941  */
92942 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
92943 
92944 #define TMR_CTRL_COINIT_MASK                     (0x8U)
92945 #define TMR_CTRL_COINIT_SHIFT                    (3U)
92946 /*! COINIT - Co-Channel Initialization
92947  *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
92948  *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
92949  */
92950 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
92951 
92952 #define TMR_CTRL_DIR_MASK                        (0x10U)
92953 #define TMR_CTRL_DIR_SHIFT                       (4U)
92954 /*! DIR - Count Direction
92955  *  0b0..Count up.
92956  *  0b1..Count down.
92957  */
92958 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
92959 
92960 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
92961 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
92962 /*! LENGTH - Count Length
92963  *  0b0..Count until roll over at $FFFF and continue from $0000.
92964  *  0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
92965  *       reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
92966  *       When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
92967  *       comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
92968  *       value is reached, re-initializes, counts until COMP1 value is reached, and so on.
92969  */
92970 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
92971 
92972 #define TMR_CTRL_ONCE_MASK                       (0x40U)
92973 #define TMR_CTRL_ONCE_SHIFT                      (6U)
92974 /*! ONCE - Count Once
92975  *  0b0..Count repeatedly.
92976  *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
92977  *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
92978  *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
92979  *       the COMP2 value, and then stops.
92980  */
92981 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
92982 
92983 #define TMR_CTRL_SCS_MASK                        (0x180U)
92984 #define TMR_CTRL_SCS_SHIFT                       (7U)
92985 /*! SCS - Secondary Count Source
92986  *  0b00..Counter 0 input pin
92987  *  0b01..Counter 1 input pin
92988  *  0b10..Counter 2 input pin
92989  *  0b11..Counter 3 input pin
92990  */
92991 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
92992 
92993 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
92994 #define TMR_CTRL_PCS_SHIFT                       (9U)
92995 /*! PCS - Primary Count Source
92996  *  0b0000..Counter 0 input pin
92997  *  0b0001..Counter 1 input pin
92998  *  0b0010..Counter 2 input pin
92999  *  0b0011..Counter 3 input pin
93000  *  0b0100..Counter 0 output
93001  *  0b0101..Counter 1 output
93002  *  0b0110..Counter 2 output
93003  *  0b0111..Counter 3 output
93004  *  0b1000..IP bus clock divide by 1 prescaler
93005  *  0b1001..IP bus clock divide by 2 prescaler
93006  *  0b1010..IP bus clock divide by 4 prescaler
93007  *  0b1011..IP bus clock divide by 8 prescaler
93008  *  0b1100..IP bus clock divide by 16 prescaler
93009  *  0b1101..IP bus clock divide by 32 prescaler
93010  *  0b1110..IP bus clock divide by 64 prescaler
93011  *  0b1111..IP bus clock divide by 128 prescaler
93012  */
93013 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
93014 
93015 #define TMR_CTRL_CM_MASK                         (0xE000U)
93016 #define TMR_CTRL_CM_SHIFT                        (13U)
93017 /*! CM - Count Mode
93018  *  0b000..No operation
93019  *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
93020  *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
93021  *         edges are counted regardless of the value of SCTRL[IPS].
93022  *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
93023  *  0b011..Count rising edges of primary source while secondary input high active
93024  *  0b100..Quadrature count mode, uses primary and secondary sources
93025  *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
93026  *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
93027  *  0b110..Edge of secondary source triggers primary count until compare
93028  *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
93029  */
93030 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
93031 /*! @} */
93032 
93033 /* The count of TMR_CTRL */
93034 #define TMR_CTRL_COUNT                           (4U)
93035 
93036 /*! @name SCTRL - Timer Channel Status and Control Register */
93037 /*! @{ */
93038 
93039 #define TMR_SCTRL_OEN_MASK                       (0x1U)
93040 #define TMR_SCTRL_OEN_SHIFT                      (0U)
93041 /*! OEN - Output Enable
93042  *  0b0..The external pin is configured as an input.
93043  *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
93044  *       their input see the driven value. The polarity of the signal is determined by OPS.
93045  */
93046 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
93047 
93048 #define TMR_SCTRL_OPS_MASK                       (0x2U)
93049 #define TMR_SCTRL_OPS_SHIFT                      (1U)
93050 /*! OPS - Output Polarity Select
93051  *  0b0..True polarity.
93052  *  0b1..Inverted polarity.
93053  */
93054 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
93055 
93056 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
93057 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
93058 /*! FORCE - Force OFLAG Output
93059  */
93060 #define TMR_SCTRL_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
93061 
93062 #define TMR_SCTRL_VAL_MASK                       (0x8U)
93063 #define TMR_SCTRL_VAL_SHIFT                      (3U)
93064 /*! VAL - Forced OFLAG Value
93065  */
93066 #define TMR_SCTRL_VAL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
93067 
93068 #define TMR_SCTRL_EEOF_MASK                      (0x10U)
93069 #define TMR_SCTRL_EEOF_SHIFT                     (4U)
93070 /*! EEOF - Enable External OFLAG Force
93071  */
93072 #define TMR_SCTRL_EEOF(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
93073 
93074 #define TMR_SCTRL_MSTR_MASK                      (0x20U)
93075 #define TMR_SCTRL_MSTR_SHIFT                     (5U)
93076 /*! MSTR - Master Mode
93077  */
93078 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
93079 
93080 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
93081 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
93082 /*! CAPTURE_MODE - Input Capture Mode
93083  *  0b00..Capture function is disabled
93084  *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
93085  *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
93086  *  0b11..Load capture register on both edges of input
93087  */
93088 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
93089 
93090 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
93091 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
93092 /*! INPUT - External Input Signal
93093  */
93094 #define TMR_SCTRL_INPUT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
93095 
93096 #define TMR_SCTRL_IPS_MASK                       (0x200U)
93097 #define TMR_SCTRL_IPS_SHIFT                      (9U)
93098 /*! IPS - Input Polarity Select
93099  */
93100 #define TMR_SCTRL_IPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
93101 
93102 #define TMR_SCTRL_IEFIE_MASK                     (0x400U)
93103 #define TMR_SCTRL_IEFIE_SHIFT                    (10U)
93104 /*! IEFIE - Input Edge Flag Interrupt Enable
93105  */
93106 #define TMR_SCTRL_IEFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
93107 
93108 #define TMR_SCTRL_IEF_MASK                       (0x800U)
93109 #define TMR_SCTRL_IEF_SHIFT                      (11U)
93110 /*! IEF - Input Edge Flag
93111  */
93112 #define TMR_SCTRL_IEF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
93113 
93114 #define TMR_SCTRL_TOFIE_MASK                     (0x1000U)
93115 #define TMR_SCTRL_TOFIE_SHIFT                    (12U)
93116 /*! TOFIE - Timer Overflow Flag Interrupt Enable
93117  */
93118 #define TMR_SCTRL_TOFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
93119 
93120 #define TMR_SCTRL_TOF_MASK                       (0x2000U)
93121 #define TMR_SCTRL_TOF_SHIFT                      (13U)
93122 /*! TOF - Timer Overflow Flag
93123  */
93124 #define TMR_SCTRL_TOF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
93125 
93126 #define TMR_SCTRL_TCFIE_MASK                     (0x4000U)
93127 #define TMR_SCTRL_TCFIE_SHIFT                    (14U)
93128 /*! TCFIE - Timer Compare Flag Interrupt Enable
93129  */
93130 #define TMR_SCTRL_TCFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
93131 
93132 #define TMR_SCTRL_TCF_MASK                       (0x8000U)
93133 #define TMR_SCTRL_TCF_SHIFT                      (15U)
93134 /*! TCF - Timer Compare Flag
93135  */
93136 #define TMR_SCTRL_TCF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
93137 /*! @} */
93138 
93139 /* The count of TMR_SCTRL */
93140 #define TMR_SCTRL_COUNT                          (4U)
93141 
93142 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
93143 /*! @{ */
93144 
93145 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK        (0xFFFFU)
93146 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT       (0U)
93147 /*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1
93148  */
93149 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
93150 /*! @} */
93151 
93152 /* The count of TMR_CMPLD1 */
93153 #define TMR_CMPLD1_COUNT                         (4U)
93154 
93155 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
93156 /*! @{ */
93157 
93158 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK        (0xFFFFU)
93159 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT       (0U)
93160 /*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2
93161  */
93162 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
93163 /*! @} */
93164 
93165 /* The count of TMR_CMPLD2 */
93166 #define TMR_CMPLD2_COUNT                         (4U)
93167 
93168 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
93169 /*! @{ */
93170 
93171 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
93172 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
93173 /*! CL1 - Compare Load Control 1
93174  *  0b00..Never preload
93175  *  0b01..Load upon successful compare with the value in COMP1
93176  *  0b10..Load upon successful compare with the value in COMP2
93177  *  0b11..Reserved
93178  */
93179 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
93180 
93181 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
93182 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
93183 /*! CL2 - Compare Load Control 2
93184  *  0b00..Never preload
93185  *  0b01..Load upon successful compare with the value in COMP1
93186  *  0b10..Load upon successful compare with the value in COMP2
93187  *  0b11..Reserved
93188  */
93189 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
93190 
93191 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
93192 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
93193 /*! TCF1 - Timer Compare 1 Interrupt Flag
93194  */
93195 #define TMR_CSCTRL_TCF1(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
93196 
93197 #define TMR_CSCTRL_TCF2_MASK                     (0x20U)
93198 #define TMR_CSCTRL_TCF2_SHIFT                    (5U)
93199 /*! TCF2 - Timer Compare 2 Interrupt Flag
93200  */
93201 #define TMR_CSCTRL_TCF2(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
93202 
93203 #define TMR_CSCTRL_TCF1EN_MASK                   (0x40U)
93204 #define TMR_CSCTRL_TCF1EN_SHIFT                  (6U)
93205 /*! TCF1EN - Timer Compare 1 Interrupt Enable
93206  */
93207 #define TMR_CSCTRL_TCF1EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
93208 
93209 #define TMR_CSCTRL_TCF2EN_MASK                   (0x80U)
93210 #define TMR_CSCTRL_TCF2EN_SHIFT                  (7U)
93211 /*! TCF2EN - Timer Compare 2 Interrupt Enable
93212  */
93213 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
93214 
93215 #define TMR_CSCTRL_UP_MASK                       (0x200U)
93216 #define TMR_CSCTRL_UP_SHIFT                      (9U)
93217 /*! UP - Counting Direction Indicator
93218  *  0b0..The last count was in the DOWN direction.
93219  *  0b1..The last count was in the UP direction.
93220  */
93221 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
93222 
93223 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
93224 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
93225 /*! TCI - Triggered Count Initialization Control
93226  *  0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
93227  *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
93228  */
93229 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
93230 
93231 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
93232 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
93233 /*! ROC - Reload on Capture
93234  *  0b0..Do not reload the counter on a capture event.
93235  *  0b1..Reload the counter on a capture event.
93236  */
93237 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
93238 
93239 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
93240 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
93241 /*! ALT_LOAD - Alternative Load Enable
93242  *  0b0..Counter can be re-initialized only with the LOAD register.
93243  *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
93244  */
93245 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
93246 
93247 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
93248 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
93249 /*! FAULT - Fault Enable
93250  *  0b0..Fault function disabled.
93251  *  0b1..Fault function enabled.
93252  */
93253 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
93254 
93255 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
93256 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
93257 /*! DBG_EN - Debug Actions Enable
93258  *  0b00..Continue with normal operation during debug mode. (default)
93259  *  0b01..Halt TMR counter during debug mode.
93260  *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
93261  *  0b11..Both halt counter and force output to 0 during debug mode.
93262  */
93263 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
93264 /*! @} */
93265 
93266 /* The count of TMR_CSCTRL */
93267 #define TMR_CSCTRL_COUNT                         (4U)
93268 
93269 /*! @name FILT - Timer Channel Input Filter Register */
93270 /*! @{ */
93271 
93272 #define TMR_FILT_FILT_PER_MASK                   (0xFFU)
93273 #define TMR_FILT_FILT_PER_SHIFT                  (0U)
93274 /*! FILT_PER - Input Filter Sample Period
93275  */
93276 #define TMR_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
93277 
93278 #define TMR_FILT_FILT_CNT_MASK                   (0x700U)
93279 #define TMR_FILT_FILT_CNT_SHIFT                  (8U)
93280 /*! FILT_CNT - Input Filter Sample Count
93281  */
93282 #define TMR_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
93283 /*! @} */
93284 
93285 /* The count of TMR_FILT */
93286 #define TMR_FILT_COUNT                           (4U)
93287 
93288 /*! @name DMA - Timer Channel DMA Enable Register */
93289 /*! @{ */
93290 
93291 #define TMR_DMA_IEFDE_MASK                       (0x1U)
93292 #define TMR_DMA_IEFDE_SHIFT                      (0U)
93293 /*! IEFDE - Input Edge Flag DMA Enable
93294  */
93295 #define TMR_DMA_IEFDE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
93296 
93297 #define TMR_DMA_CMPLD1DE_MASK                    (0x2U)
93298 #define TMR_DMA_CMPLD1DE_SHIFT                   (1U)
93299 /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable
93300  */
93301 #define TMR_DMA_CMPLD1DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
93302 
93303 #define TMR_DMA_CMPLD2DE_MASK                    (0x4U)
93304 #define TMR_DMA_CMPLD2DE_SHIFT                   (2U)
93305 /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable
93306  */
93307 #define TMR_DMA_CMPLD2DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
93308 /*! @} */
93309 
93310 /* The count of TMR_DMA */
93311 #define TMR_DMA_COUNT                            (4U)
93312 
93313 /*! @name ENBL - Timer Channel Enable Register */
93314 /*! @{ */
93315 
93316 #define TMR_ENBL_ENBL_MASK                       (0xFU)
93317 #define TMR_ENBL_ENBL_SHIFT                      (0U)
93318 /*! ENBL - Timer Channel Enable
93319  *  0b0000..Timer channel is disabled.
93320  *  0b0001..Timer channel is enabled. (default)
93321  */
93322 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
93323 /*! @} */
93324 
93325 /* The count of TMR_ENBL */
93326 #define TMR_ENBL_COUNT                           (4U)
93327 
93328 
93329 /*!
93330  * @}
93331  */ /* end of group TMR_Register_Masks */
93332 
93333 
93334 /* TMR - Peripheral instance base addresses */
93335 /** Peripheral TMR1 base address */
93336 #define TMR1_BASE                                (0x4015C000u)
93337 /** Peripheral TMR1 base pointer */
93338 #define TMR1                                     ((TMR_Type *)TMR1_BASE)
93339 /** Peripheral TMR2 base address */
93340 #define TMR2_BASE                                (0x40160000u)
93341 /** Peripheral TMR2 base pointer */
93342 #define TMR2                                     ((TMR_Type *)TMR2_BASE)
93343 /** Peripheral TMR3 base address */
93344 #define TMR3_BASE                                (0x40164000u)
93345 /** Peripheral TMR3 base pointer */
93346 #define TMR3                                     ((TMR_Type *)TMR3_BASE)
93347 /** Peripheral TMR4 base address */
93348 #define TMR4_BASE                                (0x40168000u)
93349 /** Peripheral TMR4 base pointer */
93350 #define TMR4                                     ((TMR_Type *)TMR4_BASE)
93351 /** Array initializer of TMR peripheral base addresses */
93352 #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
93353 /** Array initializer of TMR peripheral base pointers */
93354 #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
93355 /** Interrupt vectors for the TMR peripheral type */
93356 #define TMR_IRQS                                 { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
93357 
93358 /*!
93359  * @}
93360  */ /* end of group TMR_Peripheral_Access_Layer */
93361 
93362 
93363 /* ----------------------------------------------------------------------------
93364    -- USB Peripheral Access Layer
93365    ---------------------------------------------------------------------------- */
93366 
93367 /*!
93368  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
93369  * @{
93370  */
93371 
93372 /** USB - Register Layout Typedef */
93373 typedef struct {
93374   __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
93375   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
93376   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
93377   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
93378   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
93379   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
93380        uint8_t RESERVED_0[104];
93381   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
93382   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
93383   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
93384   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
93385   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
93386        uint8_t RESERVED_1[108];
93387   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
93388        uint8_t RESERVED_2[1];
93389   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
93390   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
93391   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
93392        uint8_t RESERVED_3[20];
93393   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
93394        uint8_t RESERVED_4[2];
93395   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
93396        uint8_t RESERVED_5[24];
93397   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
93398   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
93399   __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
93400   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
93401        uint8_t RESERVED_6[4];
93402   union {                                          /* offset: 0x154 */
93403     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
93404     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
93405   };
93406   union {                                          /* offset: 0x158 */
93407     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
93408     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
93409   };
93410        uint8_t RESERVED_7[4];
93411   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
93412   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
93413        uint8_t RESERVED_8[16];
93414   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
93415   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
93416   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
93417   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
93418        uint8_t RESERVED_9[28];
93419   __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
93420   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
93421   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
93422   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
93423   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
93424   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
93425   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
93426   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
93427   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
93428 } USB_Type;
93429 
93430 /* ----------------------------------------------------------------------------
93431    -- USB Register Masks
93432    ---------------------------------------------------------------------------- */
93433 
93434 /*!
93435  * @addtogroup USB_Register_Masks USB Register Masks
93436  * @{
93437  */
93438 
93439 /*! @name ID - Identification register */
93440 /*! @{ */
93441 
93442 #define USB_ID_ID_MASK                           (0x3FU)
93443 #define USB_ID_ID_SHIFT                          (0U)
93444 /*! ID - ID
93445  */
93446 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
93447 
93448 #define USB_ID_NID_MASK                          (0x3F00U)
93449 #define USB_ID_NID_SHIFT                         (8U)
93450 /*! NID - NID
93451  */
93452 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
93453 
93454 #define USB_ID_REVISION_MASK                     (0xFF0000U)
93455 #define USB_ID_REVISION_SHIFT                    (16U)
93456 /*! REVISION - REVISION
93457  */
93458 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
93459 /*! @} */
93460 
93461 /*! @name HWGENERAL - Hardware General */
93462 /*! @{ */
93463 
93464 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
93465 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
93466 /*! PHYW - PHYW
93467  *  0b00..8 bit wide data bus (Software non-programmable)
93468  *  0b01..16 bit wide data bus (Software non-programmable)
93469  *  0b10..Reset to 8 bit wide data bus (Software programmable)
93470  *  0b11..Reset to 16 bit wide data bus (Software programmable)
93471  */
93472 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
93473 
93474 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
93475 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
93476 /*! PHYM - PHYM
93477  *  0b000..UTMI/UMTI+
93478  *  0b001..ULPI DDR
93479  *  0b010..ULPI
93480  *  0b011..Serial Only
93481  *  0b100..Software programmable - reset to UTMI/UTMI+
93482  *  0b101..Software programmable - reset to ULPI DDR
93483  *  0b110..Software programmable - reset to ULPI
93484  *  0b111..Software programmable - reset to Serial
93485  */
93486 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
93487 
93488 #define USB_HWGENERAL_SM_MASK                    (0x600U)
93489 #define USB_HWGENERAL_SM_SHIFT                   (9U)
93490 /*! SM - SM
93491  *  0b00..No Serial Engine, always use parallel signalling.
93492  *  0b01..Serial Engine present, always use serial signalling for FS/LS.
93493  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
93494  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
93495  */
93496 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
93497 /*! @} */
93498 
93499 /*! @name HWHOST - Host Hardware Parameters */
93500 /*! @{ */
93501 
93502 #define USB_HWHOST_HC_MASK                       (0x1U)
93503 #define USB_HWHOST_HC_SHIFT                      (0U)
93504 /*! HC - HC
93505  *  0b1..Supported
93506  *  0b0..Not supported
93507  */
93508 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
93509 
93510 #define USB_HWHOST_NPORT_MASK                    (0xEU)
93511 #define USB_HWHOST_NPORT_SHIFT                   (1U)
93512 /*! NPORT - NPORT
93513  */
93514 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
93515 /*! @} */
93516 
93517 /*! @name HWDEVICE - Device Hardware Parameters */
93518 /*! @{ */
93519 
93520 #define USB_HWDEVICE_DC_MASK                     (0x1U)
93521 #define USB_HWDEVICE_DC_SHIFT                    (0U)
93522 /*! DC - DC
93523  *  0b1..Supported
93524  *  0b0..Not supported
93525  */
93526 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
93527 
93528 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
93529 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
93530 /*! DEVEP - DEVEP
93531  */
93532 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
93533 /*! @} */
93534 
93535 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
93536 /*! @{ */
93537 
93538 #define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
93539 #define USB_HWTXBUF_TXBURST_SHIFT                (0U)
93540 /*! TXBURST - TXBURST
93541  */
93542 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
93543 
93544 #define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
93545 #define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
93546 /*! TXCHANADD - TXCHANADD
93547  */
93548 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
93549 /*! @} */
93550 
93551 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
93552 /*! @{ */
93553 
93554 #define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
93555 #define USB_HWRXBUF_RXBURST_SHIFT                (0U)
93556 /*! RXBURST - RXBURST
93557  */
93558 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
93559 
93560 #define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
93561 #define USB_HWRXBUF_RXADD_SHIFT                  (8U)
93562 /*! RXADD - RXADD
93563  */
93564 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
93565 /*! @} */
93566 
93567 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
93568 /*! @{ */
93569 
93570 #define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
93571 #define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
93572 /*! GPTLD - GPTLD
93573  */
93574 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
93575 /*! @} */
93576 
93577 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
93578 /*! @{ */
93579 
93580 #define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
93581 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
93582 /*! GPTCNT - GPTCNT
93583  */
93584 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
93585 
93586 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
93587 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
93588 /*! GPTMODE - GPTMODE
93589  *  0b0..One Shot Mode
93590  *  0b1..Repeat Mode
93591  */
93592 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
93593 
93594 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
93595 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
93596 /*! GPTRST - GPTRST
93597  *  0b0..No action
93598  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
93599  */
93600 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
93601 
93602 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
93603 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
93604 /*! GPTRUN - GPTRUN
93605  *  0b0..Stop counting
93606  *  0b1..Run
93607  */
93608 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
93609 /*! @} */
93610 
93611 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
93612 /*! @{ */
93613 
93614 #define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
93615 #define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
93616 /*! GPTLD - GPTLD
93617  */
93618 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
93619 /*! @} */
93620 
93621 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
93622 /*! @{ */
93623 
93624 #define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
93625 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
93626 /*! GPTCNT - GPTCNT
93627  */
93628 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
93629 
93630 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
93631 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
93632 /*! GPTMODE - GPTMODE
93633  *  0b0..One Shot Mode
93634  *  0b1..Repeat Mode
93635  */
93636 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
93637 
93638 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
93639 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
93640 /*! GPTRST - GPTRST
93641  *  0b0..No action
93642  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
93643  */
93644 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
93645 
93646 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
93647 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
93648 /*! GPTRUN - GPTRUN
93649  *  0b0..Stop counting
93650  *  0b1..Run
93651  */
93652 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
93653 /*! @} */
93654 
93655 /*! @name SBUSCFG - System Bus Config */
93656 /*! @{ */
93657 
93658 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
93659 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
93660 /*! AHBBRST - AHBBRST
93661  *  0b000..Incremental burst of unspecified length only
93662  *  0b001..INCR4 burst, then single transfer
93663  *  0b010..INCR8 burst, INCR4 burst, then single transfer
93664  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
93665  *  0b100..Reserved, don't use
93666  *  0b101..INCR4 burst, then incremental burst of unspecified length
93667  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
93668  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
93669  */
93670 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
93671 /*! @} */
93672 
93673 /*! @name CAPLENGTH - Capability Registers Length */
93674 /*! @{ */
93675 
93676 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
93677 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
93678 /*! CAPLENGTH - CAPLENGTH
93679  */
93680 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
93681 /*! @} */
93682 
93683 /*! @name HCIVERSION - Host Controller Interface Version */
93684 /*! @{ */
93685 
93686 #define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
93687 #define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
93688 /*! HCIVERSION - HCIVERSION
93689  */
93690 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
93691 /*! @} */
93692 
93693 /*! @name HCSPARAMS - Host Controller Structural Parameters */
93694 /*! @{ */
93695 
93696 #define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
93697 #define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
93698 /*! N_PORTS - N_PORTS
93699  */
93700 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
93701 
93702 #define USB_HCSPARAMS_PPC_MASK                   (0x10U)
93703 #define USB_HCSPARAMS_PPC_SHIFT                  (4U)
93704 /*! PPC - PPC
93705  */
93706 #define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
93707 
93708 #define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
93709 #define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
93710 /*! N_PCC - N_PCC
93711  */
93712 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
93713 
93714 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
93715 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
93716 /*! N_CC - N_CC
93717  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
93718  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
93719  */
93720 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
93721 
93722 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
93723 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
93724 /*! PI - PI
93725  */
93726 #define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
93727 
93728 #define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
93729 #define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
93730 /*! N_PTT - N_PTT
93731  */
93732 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
93733 
93734 #define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
93735 #define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
93736 /*! N_TT - N_TT
93737  */
93738 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
93739 /*! @} */
93740 
93741 /*! @name HCCPARAMS - Host Controller Capability Parameters */
93742 /*! @{ */
93743 
93744 #define USB_HCCPARAMS_ADC_MASK                   (0x1U)
93745 #define USB_HCCPARAMS_ADC_SHIFT                  (0U)
93746 /*! ADC - ADC
93747  */
93748 #define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
93749 
93750 #define USB_HCCPARAMS_PFL_MASK                   (0x2U)
93751 #define USB_HCCPARAMS_PFL_SHIFT                  (1U)
93752 /*! PFL - PFL
93753  */
93754 #define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
93755 
93756 #define USB_HCCPARAMS_ASP_MASK                   (0x4U)
93757 #define USB_HCCPARAMS_ASP_SHIFT                  (2U)
93758 /*! ASP - ASP
93759  */
93760 #define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
93761 
93762 #define USB_HCCPARAMS_IST_MASK                   (0xF0U)
93763 #define USB_HCCPARAMS_IST_SHIFT                  (4U)
93764 /*! IST - IST
93765  */
93766 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
93767 
93768 #define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
93769 #define USB_HCCPARAMS_EECP_SHIFT                 (8U)
93770 /*! EECP - EECP
93771  */
93772 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
93773 /*! @} */
93774 
93775 /*! @name DCIVERSION - Device Controller Interface Version */
93776 /*! @{ */
93777 
93778 #define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
93779 #define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
93780 /*! DCIVERSION - DCIVERSION
93781  */
93782 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
93783 /*! @} */
93784 
93785 /*! @name DCCPARAMS - Device Controller Capability Parameters */
93786 /*! @{ */
93787 
93788 #define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
93789 #define USB_DCCPARAMS_DEN_SHIFT                  (0U)
93790 /*! DEN - DEN
93791  */
93792 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
93793 
93794 #define USB_DCCPARAMS_DC_MASK                    (0x80U)
93795 #define USB_DCCPARAMS_DC_SHIFT                   (7U)
93796 /*! DC - DC
93797  */
93798 #define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
93799 
93800 #define USB_DCCPARAMS_HC_MASK                    (0x100U)
93801 #define USB_DCCPARAMS_HC_SHIFT                   (8U)
93802 /*! HC - HC
93803  */
93804 #define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
93805 /*! @} */
93806 
93807 /*! @name USBCMD - USB Command Register */
93808 /*! @{ */
93809 
93810 #define USB_USBCMD_RS_MASK                       (0x1U)
93811 #define USB_USBCMD_RS_SHIFT                      (0U)
93812 /*! RS - RS
93813  */
93814 #define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
93815 
93816 #define USB_USBCMD_RST_MASK                      (0x2U)
93817 #define USB_USBCMD_RST_SHIFT                     (1U)
93818 /*! RST - RST
93819  */
93820 #define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
93821 
93822 #define USB_USBCMD_FS_1_MASK                     (0xCU)
93823 #define USB_USBCMD_FS_1_SHIFT                    (2U)
93824 /*! FS_1 - FS_1
93825  */
93826 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
93827 
93828 #define USB_USBCMD_PSE_MASK                      (0x10U)
93829 #define USB_USBCMD_PSE_SHIFT                     (4U)
93830 /*! PSE - PSE
93831  *  0b0..Do not process the Periodic Schedule
93832  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
93833  */
93834 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
93835 
93836 #define USB_USBCMD_ASE_MASK                      (0x20U)
93837 #define USB_USBCMD_ASE_SHIFT                     (5U)
93838 /*! ASE - ASE
93839  *  0b0..Do not process the Asynchronous Schedule.
93840  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
93841  */
93842 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
93843 
93844 #define USB_USBCMD_IAA_MASK                      (0x40U)
93845 #define USB_USBCMD_IAA_SHIFT                     (6U)
93846 /*! IAA - IAA
93847  */
93848 #define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
93849 
93850 #define USB_USBCMD_ASP_MASK                      (0x300U)
93851 #define USB_USBCMD_ASP_SHIFT                     (8U)
93852 /*! ASP - ASP
93853  */
93854 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
93855 
93856 #define USB_USBCMD_ASPE_MASK                     (0x800U)
93857 #define USB_USBCMD_ASPE_SHIFT                    (11U)
93858 /*! ASPE - ASPE
93859  */
93860 #define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
93861 
93862 #define USB_USBCMD_SUTW_MASK                     (0x2000U)
93863 #define USB_USBCMD_SUTW_SHIFT                    (13U)
93864 /*! SUTW - SUTW
93865  */
93866 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
93867 
93868 #define USB_USBCMD_ATDTW_MASK                    (0x4000U)
93869 #define USB_USBCMD_ATDTW_SHIFT                   (14U)
93870 /*! ATDTW - ATDTW
93871  */
93872 #define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
93873 
93874 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
93875 #define USB_USBCMD_FS_2_SHIFT                    (15U)
93876 /*! FS_2 - FS_2
93877  */
93878 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
93879 
93880 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
93881 #define USB_USBCMD_ITC_SHIFT                     (16U)
93882 /*! ITC - ITC
93883  *  0b00000000..Immediate (no threshold)
93884  *  0b00000001..1 micro-frame
93885  *  0b00000010..2 micro-frames
93886  *  0b00000100..4 micro-frames
93887  *  0b00001000..8 micro-frames
93888  *  0b00010000..16 micro-frames
93889  *  0b00100000..32 micro-frames
93890  *  0b01000000..64 micro-frames
93891  */
93892 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
93893 /*! @} */
93894 
93895 /*! @name USBSTS - USB Status Register */
93896 /*! @{ */
93897 
93898 #define USB_USBSTS_UI_MASK                       (0x1U)
93899 #define USB_USBSTS_UI_SHIFT                      (0U)
93900 /*! UI - UI
93901  */
93902 #define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
93903 
93904 #define USB_USBSTS_UEI_MASK                      (0x2U)
93905 #define USB_USBSTS_UEI_SHIFT                     (1U)
93906 /*! UEI - UEI
93907  */
93908 #define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
93909 
93910 #define USB_USBSTS_PCI_MASK                      (0x4U)
93911 #define USB_USBSTS_PCI_SHIFT                     (2U)
93912 /*! PCI - PCI
93913  */
93914 #define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
93915 
93916 #define USB_USBSTS_FRI_MASK                      (0x8U)
93917 #define USB_USBSTS_FRI_SHIFT                     (3U)
93918 /*! FRI - FRI
93919  */
93920 #define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
93921 
93922 #define USB_USBSTS_SEI_MASK                      (0x10U)
93923 #define USB_USBSTS_SEI_SHIFT                     (4U)
93924 /*! SEI - SEI
93925  */
93926 #define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
93927 
93928 #define USB_USBSTS_AAI_MASK                      (0x20U)
93929 #define USB_USBSTS_AAI_SHIFT                     (5U)
93930 /*! AAI - AAI
93931  */
93932 #define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
93933 
93934 #define USB_USBSTS_URI_MASK                      (0x40U)
93935 #define USB_USBSTS_URI_SHIFT                     (6U)
93936 /*! URI - URI
93937  */
93938 #define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
93939 
93940 #define USB_USBSTS_SRI_MASK                      (0x80U)
93941 #define USB_USBSTS_SRI_SHIFT                     (7U)
93942 /*! SRI - SRI
93943  */
93944 #define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
93945 
93946 #define USB_USBSTS_SLI_MASK                      (0x100U)
93947 #define USB_USBSTS_SLI_SHIFT                     (8U)
93948 /*! SLI - SLI
93949  */
93950 #define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
93951 
93952 #define USB_USBSTS_ULPII_MASK                    (0x400U)
93953 #define USB_USBSTS_ULPII_SHIFT                   (10U)
93954 /*! ULPII - ULPII
93955  */
93956 #define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
93957 
93958 #define USB_USBSTS_HCH_MASK                      (0x1000U)
93959 #define USB_USBSTS_HCH_SHIFT                     (12U)
93960 /*! HCH - HCH
93961  */
93962 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
93963 
93964 #define USB_USBSTS_RCL_MASK                      (0x2000U)
93965 #define USB_USBSTS_RCL_SHIFT                     (13U)
93966 /*! RCL - RCL
93967  */
93968 #define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
93969 
93970 #define USB_USBSTS_PS_MASK                       (0x4000U)
93971 #define USB_USBSTS_PS_SHIFT                      (14U)
93972 /*! PS - PS
93973  */
93974 #define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
93975 
93976 #define USB_USBSTS_AS_MASK                       (0x8000U)
93977 #define USB_USBSTS_AS_SHIFT                      (15U)
93978 /*! AS - AS
93979  */
93980 #define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
93981 
93982 #define USB_USBSTS_NAKI_MASK                     (0x10000U)
93983 #define USB_USBSTS_NAKI_SHIFT                    (16U)
93984 /*! NAKI - NAKI
93985  */
93986 #define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
93987 
93988 #define USB_USBSTS_TI0_MASK                      (0x1000000U)
93989 #define USB_USBSTS_TI0_SHIFT                     (24U)
93990 /*! TI0 - TI0
93991  */
93992 #define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
93993 
93994 #define USB_USBSTS_TI1_MASK                      (0x2000000U)
93995 #define USB_USBSTS_TI1_SHIFT                     (25U)
93996 /*! TI1 - TI1
93997  */
93998 #define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
93999 /*! @} */
94000 
94001 /*! @name USBINTR - Interrupt Enable Register */
94002 /*! @{ */
94003 
94004 #define USB_USBINTR_UE_MASK                      (0x1U)
94005 #define USB_USBINTR_UE_SHIFT                     (0U)
94006 /*! UE - UE
94007  */
94008 #define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
94009 
94010 #define USB_USBINTR_UEE_MASK                     (0x2U)
94011 #define USB_USBINTR_UEE_SHIFT                    (1U)
94012 /*! UEE - UEE
94013  */
94014 #define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
94015 
94016 #define USB_USBINTR_PCE_MASK                     (0x4U)
94017 #define USB_USBINTR_PCE_SHIFT                    (2U)
94018 /*! PCE - PCE
94019  */
94020 #define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
94021 
94022 #define USB_USBINTR_FRE_MASK                     (0x8U)
94023 #define USB_USBINTR_FRE_SHIFT                    (3U)
94024 /*! FRE - FRE
94025  */
94026 #define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
94027 
94028 #define USB_USBINTR_SEE_MASK                     (0x10U)
94029 #define USB_USBINTR_SEE_SHIFT                    (4U)
94030 /*! SEE - SEE
94031  */
94032 #define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
94033 
94034 #define USB_USBINTR_AAE_MASK                     (0x20U)
94035 #define USB_USBINTR_AAE_SHIFT                    (5U)
94036 /*! AAE - AAE
94037  */
94038 #define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
94039 
94040 #define USB_USBINTR_URE_MASK                     (0x40U)
94041 #define USB_USBINTR_URE_SHIFT                    (6U)
94042 /*! URE - URE
94043  */
94044 #define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
94045 
94046 #define USB_USBINTR_SRE_MASK                     (0x80U)
94047 #define USB_USBINTR_SRE_SHIFT                    (7U)
94048 /*! SRE - SRE
94049  */
94050 #define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
94051 
94052 #define USB_USBINTR_SLE_MASK                     (0x100U)
94053 #define USB_USBINTR_SLE_SHIFT                    (8U)
94054 /*! SLE - SLE
94055  */
94056 #define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
94057 
94058 #define USB_USBINTR_ULPIE_MASK                   (0x400U)
94059 #define USB_USBINTR_ULPIE_SHIFT                  (10U)
94060 /*! ULPIE - ULPIE
94061  */
94062 #define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
94063 
94064 #define USB_USBINTR_NAKE_MASK                    (0x10000U)
94065 #define USB_USBINTR_NAKE_SHIFT                   (16U)
94066 /*! NAKE - NAKE
94067  */
94068 #define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
94069 
94070 #define USB_USBINTR_UAIE_MASK                    (0x40000U)
94071 #define USB_USBINTR_UAIE_SHIFT                   (18U)
94072 /*! UAIE - UAIE
94073  */
94074 #define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
94075 
94076 #define USB_USBINTR_UPIE_MASK                    (0x80000U)
94077 #define USB_USBINTR_UPIE_SHIFT                   (19U)
94078 /*! UPIE - UPIE
94079  */
94080 #define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
94081 
94082 #define USB_USBINTR_TIE0_MASK                    (0x1000000U)
94083 #define USB_USBINTR_TIE0_SHIFT                   (24U)
94084 /*! TIE0 - TIE0
94085  */
94086 #define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
94087 
94088 #define USB_USBINTR_TIE1_MASK                    (0x2000000U)
94089 #define USB_USBINTR_TIE1_SHIFT                   (25U)
94090 /*! TIE1 - TIE1
94091  */
94092 #define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
94093 /*! @} */
94094 
94095 /*! @name FRINDEX - USB Frame Index */
94096 /*! @{ */
94097 
94098 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
94099 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
94100 /*! FRINDEX - FRINDEX
94101  *  0b00000000000000..(1024) 12
94102  *  0b00000000000001..(512) 11
94103  *  0b00000000000010..(256) 10
94104  *  0b00000000000011..(128) 9
94105  *  0b00000000000100..(64) 8
94106  *  0b00000000000101..(32) 7
94107  *  0b00000000000110..(16) 6
94108  *  0b00000000000111..(8) 5
94109  */
94110 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
94111 /*! @} */
94112 
94113 /*! @name DEVICEADDR - Device Address */
94114 /*! @{ */
94115 
94116 #define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
94117 #define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
94118 /*! USBADRA - USBADRA
94119  */
94120 #define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
94121 
94122 #define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
94123 #define USB_DEVICEADDR_USBADR_SHIFT              (25U)
94124 /*! USBADR - USBADR
94125  */
94126 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
94127 /*! @} */
94128 
94129 /*! @name PERIODICLISTBASE - Frame List Base Address */
94130 /*! @{ */
94131 
94132 #define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
94133 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
94134 /*! BASEADR - BASEADR
94135  */
94136 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
94137 /*! @} */
94138 
94139 /*! @name ASYNCLISTADDR - Next Asynch. Address */
94140 /*! @{ */
94141 
94142 #define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
94143 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
94144 /*! ASYBASE - ASYBASE
94145  */
94146 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
94147 /*! @} */
94148 
94149 /*! @name ENDPTLISTADDR - Endpoint List Address */
94150 /*! @{ */
94151 
94152 #define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
94153 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
94154 /*! EPBASE - EPBASE
94155  */
94156 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
94157 /*! @} */
94158 
94159 /*! @name BURSTSIZE - Programmable Burst Size */
94160 /*! @{ */
94161 
94162 #define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
94163 #define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
94164 /*! RXPBURST - RXPBURST
94165  */
94166 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
94167 
94168 #define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
94169 #define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
94170 /*! TXPBURST - TXPBURST
94171  */
94172 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
94173 /*! @} */
94174 
94175 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
94176 /*! @{ */
94177 
94178 #define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
94179 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
94180 /*! TXSCHOH - TXSCHOH
94181  */
94182 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
94183 
94184 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
94185 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
94186 /*! TXSCHHEALTH - TXSCHHEALTH
94187  */
94188 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
94189 
94190 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
94191 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
94192 /*! TXFIFOTHRES - TXFIFOTHRES
94193  */
94194 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
94195 /*! @} */
94196 
94197 /*! @name ENDPTNAK - Endpoint NAK */
94198 /*! @{ */
94199 
94200 #define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
94201 #define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
94202 /*! EPRN - EPRN
94203  */
94204 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
94205 
94206 #define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
94207 #define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
94208 /*! EPTN - EPTN
94209  */
94210 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
94211 /*! @} */
94212 
94213 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
94214 /*! @{ */
94215 
94216 #define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
94217 #define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
94218 /*! EPRNE - EPRNE
94219  */
94220 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
94221 
94222 #define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
94223 #define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
94224 /*! EPTNE - EPTNE
94225  */
94226 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
94227 /*! @} */
94228 
94229 /*! @name CONFIGFLAG - Configure Flag Register */
94230 /*! @{ */
94231 
94232 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
94233 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
94234 /*! CF - CF
94235  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
94236  *  0b1..Port routing control logic default-routes all ports to this host controller.
94237  */
94238 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
94239 /*! @} */
94240 
94241 /*! @name PORTSC1 - Port Status & Control */
94242 /*! @{ */
94243 
94244 #define USB_PORTSC1_CCS_MASK                     (0x1U)
94245 #define USB_PORTSC1_CCS_SHIFT                    (0U)
94246 /*! CCS - CCS
94247  */
94248 #define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
94249 
94250 #define USB_PORTSC1_CSC_MASK                     (0x2U)
94251 #define USB_PORTSC1_CSC_SHIFT                    (1U)
94252 /*! CSC - CSC
94253  */
94254 #define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
94255 
94256 #define USB_PORTSC1_PE_MASK                      (0x4U)
94257 #define USB_PORTSC1_PE_SHIFT                     (2U)
94258 /*! PE - PE
94259  */
94260 #define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
94261 
94262 #define USB_PORTSC1_PEC_MASK                     (0x8U)
94263 #define USB_PORTSC1_PEC_SHIFT                    (3U)
94264 /*! PEC - PEC
94265  */
94266 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
94267 
94268 #define USB_PORTSC1_OCA_MASK                     (0x10U)
94269 #define USB_PORTSC1_OCA_SHIFT                    (4U)
94270 /*! OCA - OCA
94271  *  0b1..This port currently has an over-current condition
94272  *  0b0..This port does not have an over-current condition.
94273  */
94274 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
94275 
94276 #define USB_PORTSC1_OCC_MASK                     (0x20U)
94277 #define USB_PORTSC1_OCC_SHIFT                    (5U)
94278 /*! OCC - OCC
94279  */
94280 #define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
94281 
94282 #define USB_PORTSC1_FPR_MASK                     (0x40U)
94283 #define USB_PORTSC1_FPR_SHIFT                    (6U)
94284 /*! FPR - FPR
94285  */
94286 #define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
94287 
94288 #define USB_PORTSC1_SUSP_MASK                    (0x80U)
94289 #define USB_PORTSC1_SUSP_SHIFT                   (7U)
94290 /*! SUSP - SUSP
94291  */
94292 #define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
94293 
94294 #define USB_PORTSC1_PR_MASK                      (0x100U)
94295 #define USB_PORTSC1_PR_SHIFT                     (8U)
94296 /*! PR - PR
94297  */
94298 #define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
94299 
94300 #define USB_PORTSC1_HSP_MASK                     (0x200U)
94301 #define USB_PORTSC1_HSP_SHIFT                    (9U)
94302 /*! HSP - HSP
94303  */
94304 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
94305 
94306 #define USB_PORTSC1_LS_MASK                      (0xC00U)
94307 #define USB_PORTSC1_LS_SHIFT                     (10U)
94308 /*! LS - LS
94309  *  0b00..SE0
94310  *  0b10..J-state
94311  *  0b01..K-state
94312  *  0b11..Undefined
94313  */
94314 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
94315 
94316 #define USB_PORTSC1_PP_MASK                      (0x1000U)
94317 #define USB_PORTSC1_PP_SHIFT                     (12U)
94318 /*! PP - PP
94319  */
94320 #define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
94321 
94322 #define USB_PORTSC1_PO_MASK                      (0x2000U)
94323 #define USB_PORTSC1_PO_SHIFT                     (13U)
94324 /*! PO - PO
94325  */
94326 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
94327 
94328 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
94329 #define USB_PORTSC1_PIC_SHIFT                    (14U)
94330 /*! PIC - PIC
94331  *  0b00..Port indicators are off
94332  *  0b01..Amber
94333  *  0b10..Green
94334  *  0b11..Undefined
94335  */
94336 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
94337 
94338 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
94339 #define USB_PORTSC1_PTC_SHIFT                    (16U)
94340 /*! PTC - PTC
94341  *  0b0000..TEST_MODE_DISABLE
94342  *  0b0001..J_STATE
94343  *  0b0010..K_STATE
94344  *  0b0011..SE0 (host) / NAK (device)
94345  *  0b0100..Packet
94346  *  0b0101..FORCE_ENABLE_HS
94347  *  0b0110..FORCE_ENABLE_FS
94348  *  0b0111..FORCE_ENABLE_LS
94349  *  0b1000-0b1111..Reserved
94350  */
94351 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
94352 
94353 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
94354 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
94355 /*! WKCN - WKCN
94356  */
94357 #define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
94358 
94359 #define USB_PORTSC1_WKDC_MASK                    (0x200000U)
94360 #define USB_PORTSC1_WKDC_SHIFT                   (21U)
94361 /*! WKDC - WKDC
94362  */
94363 #define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
94364 
94365 #define USB_PORTSC1_WKOC_MASK                    (0x400000U)
94366 #define USB_PORTSC1_WKOC_SHIFT                   (22U)
94367 /*! WKOC - WKOC
94368  */
94369 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
94370 
94371 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
94372 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
94373 /*! PHCD - PHCD
94374  *  0b1..Disable PHY clock
94375  *  0b0..Enable PHY clock
94376  */
94377 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
94378 
94379 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
94380 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
94381 /*! PFSC - PFSC
94382  *  0b1..Forced to full speed
94383  *  0b0..Normal operation
94384  */
94385 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
94386 
94387 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
94388 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
94389 /*! PTS_2 - PTS_2
94390  */
94391 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
94392 
94393 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
94394 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
94395 /*! PSPD - PSPD
94396  *  0b00..Full Speed
94397  *  0b01..Low Speed
94398  *  0b10..High Speed
94399  *  0b11..Undefined
94400  */
94401 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
94402 
94403 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
94404 #define USB_PORTSC1_PTW_SHIFT                    (28U)
94405 /*! PTW - PTW
94406  *  0b0..Select the 8-bit UTMI interface [60MHz]
94407  *  0b1..Select the 16-bit UTMI interface [30MHz]
94408  */
94409 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
94410 
94411 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
94412 #define USB_PORTSC1_STS_SHIFT                    (29U)
94413 /*! STS - STS
94414  */
94415 #define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
94416 
94417 #define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
94418 #define USB_PORTSC1_PTS_1_SHIFT                  (30U)
94419 /*! PTS_1 - PTS_1
94420  */
94421 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
94422 /*! @} */
94423 
94424 /*! @name OTGSC - On-The-Go Status & control */
94425 /*! @{ */
94426 
94427 #define USB_OTGSC_VD_MASK                        (0x1U)
94428 #define USB_OTGSC_VD_SHIFT                       (0U)
94429 /*! VD - VD
94430  */
94431 #define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
94432 
94433 #define USB_OTGSC_VC_MASK                        (0x2U)
94434 #define USB_OTGSC_VC_SHIFT                       (1U)
94435 /*! VC - VC
94436  */
94437 #define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
94438 
94439 #define USB_OTGSC_OT_MASK                        (0x8U)
94440 #define USB_OTGSC_OT_SHIFT                       (3U)
94441 /*! OT - OT
94442  */
94443 #define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
94444 
94445 #define USB_OTGSC_DP_MASK                        (0x10U)
94446 #define USB_OTGSC_DP_SHIFT                       (4U)
94447 /*! DP - DP
94448  */
94449 #define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
94450 
94451 #define USB_OTGSC_IDPU_MASK                      (0x20U)
94452 #define USB_OTGSC_IDPU_SHIFT                     (5U)
94453 /*! IDPU - IDPU
94454  */
94455 #define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
94456 
94457 #define USB_OTGSC_ID_MASK                        (0x100U)
94458 #define USB_OTGSC_ID_SHIFT                       (8U)
94459 /*! ID - ID
94460  */
94461 #define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
94462 
94463 #define USB_OTGSC_AVV_MASK                       (0x200U)
94464 #define USB_OTGSC_AVV_SHIFT                      (9U)
94465 /*! AVV - AVV
94466  */
94467 #define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
94468 
94469 #define USB_OTGSC_ASV_MASK                       (0x400U)
94470 #define USB_OTGSC_ASV_SHIFT                      (10U)
94471 /*! ASV - ASV
94472  */
94473 #define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
94474 
94475 #define USB_OTGSC_BSV_MASK                       (0x800U)
94476 #define USB_OTGSC_BSV_SHIFT                      (11U)
94477 /*! BSV - BSV
94478  */
94479 #define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
94480 
94481 #define USB_OTGSC_BSE_MASK                       (0x1000U)
94482 #define USB_OTGSC_BSE_SHIFT                      (12U)
94483 /*! BSE - BSE
94484  */
94485 #define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
94486 
94487 #define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
94488 #define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
94489 /*! TOG_1MS - TOG_1MS
94490  */
94491 #define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
94492 
94493 #define USB_OTGSC_DPS_MASK                       (0x4000U)
94494 #define USB_OTGSC_DPS_SHIFT                      (14U)
94495 /*! DPS - DPS
94496  */
94497 #define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
94498 
94499 #define USB_OTGSC_IDIS_MASK                      (0x10000U)
94500 #define USB_OTGSC_IDIS_SHIFT                     (16U)
94501 /*! IDIS - IDIS
94502  */
94503 #define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
94504 
94505 #define USB_OTGSC_AVVIS_MASK                     (0x20000U)
94506 #define USB_OTGSC_AVVIS_SHIFT                    (17U)
94507 /*! AVVIS - AVVIS
94508  */
94509 #define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
94510 
94511 #define USB_OTGSC_ASVIS_MASK                     (0x40000U)
94512 #define USB_OTGSC_ASVIS_SHIFT                    (18U)
94513 /*! ASVIS - ASVIS
94514  */
94515 #define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
94516 
94517 #define USB_OTGSC_BSVIS_MASK                     (0x80000U)
94518 #define USB_OTGSC_BSVIS_SHIFT                    (19U)
94519 /*! BSVIS - BSVIS
94520  */
94521 #define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
94522 
94523 #define USB_OTGSC_BSEIS_MASK                     (0x100000U)
94524 #define USB_OTGSC_BSEIS_SHIFT                    (20U)
94525 /*! BSEIS - BSEIS
94526  */
94527 #define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
94528 
94529 #define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
94530 #define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
94531 /*! STATUS_1MS - STATUS_1MS
94532  */
94533 #define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
94534 
94535 #define USB_OTGSC_DPIS_MASK                      (0x400000U)
94536 #define USB_OTGSC_DPIS_SHIFT                     (22U)
94537 /*! DPIS - DPIS
94538  */
94539 #define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
94540 
94541 #define USB_OTGSC_IDIE_MASK                      (0x1000000U)
94542 #define USB_OTGSC_IDIE_SHIFT                     (24U)
94543 /*! IDIE - IDIE
94544  */
94545 #define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
94546 
94547 #define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
94548 #define USB_OTGSC_AVVIE_SHIFT                    (25U)
94549 /*! AVVIE - AVVIE
94550  */
94551 #define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
94552 
94553 #define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
94554 #define USB_OTGSC_ASVIE_SHIFT                    (26U)
94555 /*! ASVIE - ASVIE
94556  */
94557 #define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
94558 
94559 #define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
94560 #define USB_OTGSC_BSVIE_SHIFT                    (27U)
94561 /*! BSVIE - BSVIE
94562  */
94563 #define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
94564 
94565 #define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
94566 #define USB_OTGSC_BSEIE_SHIFT                    (28U)
94567 /*! BSEIE - BSEIE
94568  */
94569 #define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
94570 
94571 #define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
94572 #define USB_OTGSC_EN_1MS_SHIFT                   (29U)
94573 /*! EN_1MS - EN_1MS
94574  */
94575 #define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
94576 
94577 #define USB_OTGSC_DPIE_MASK                      (0x40000000U)
94578 #define USB_OTGSC_DPIE_SHIFT                     (30U)
94579 /*! DPIE - DPIE
94580  */
94581 #define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
94582 /*! @} */
94583 
94584 /*! @name USBMODE - USB Device Mode */
94585 /*! @{ */
94586 
94587 #define USB_USBMODE_CM_MASK                      (0x3U)
94588 #define USB_USBMODE_CM_SHIFT                     (0U)
94589 /*! CM - CM
94590  *  0b00..Idle [Default for combination host/device]
94591  *  0b01..Reserved
94592  *  0b10..Device Controller [Default for device only controller]
94593  *  0b11..Host Controller [Default for host only controller]
94594  */
94595 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
94596 
94597 #define USB_USBMODE_ES_MASK                      (0x4U)
94598 #define USB_USBMODE_ES_SHIFT                     (2U)
94599 /*! ES - ES
94600  *  0b0..Little Endian [Default]
94601  *  0b1..Big Endian
94602  */
94603 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
94604 
94605 #define USB_USBMODE_SLOM_MASK                    (0x8U)
94606 #define USB_USBMODE_SLOM_SHIFT                   (3U)
94607 /*! SLOM - SLOM
94608  *  0b0..Setup Lockouts On (default);
94609  *  0b1..Setup Lockouts Off
94610  */
94611 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
94612 
94613 #define USB_USBMODE_SDIS_MASK                    (0x10U)
94614 #define USB_USBMODE_SDIS_SHIFT                   (4U)
94615 /*! SDIS - SDIS
94616  */
94617 #define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
94618 /*! @} */
94619 
94620 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
94621 /*! @{ */
94622 
94623 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
94624 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
94625 /*! ENDPTSETUPSTAT - ENDPTSETUPSTAT
94626  */
94627 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
94628 /*! @} */
94629 
94630 /*! @name ENDPTPRIME - Endpoint Prime */
94631 /*! @{ */
94632 
94633 #define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
94634 #define USB_ENDPTPRIME_PERB_SHIFT                (0U)
94635 /*! PERB - PERB
94636  */
94637 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
94638 
94639 #define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
94640 #define USB_ENDPTPRIME_PETB_SHIFT                (16U)
94641 /*! PETB - PETB
94642  */
94643 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
94644 /*! @} */
94645 
94646 /*! @name ENDPTFLUSH - Endpoint Flush */
94647 /*! @{ */
94648 
94649 #define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
94650 #define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
94651 /*! FERB - FERB
94652  */
94653 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
94654 
94655 #define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
94656 #define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
94657 /*! FETB - FETB
94658  */
94659 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
94660 /*! @} */
94661 
94662 /*! @name ENDPTSTAT - Endpoint Status */
94663 /*! @{ */
94664 
94665 #define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
94666 #define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
94667 /*! ERBR - ERBR
94668  */
94669 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
94670 
94671 #define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
94672 #define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
94673 /*! ETBR - ETBR
94674  */
94675 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
94676 /*! @} */
94677 
94678 /*! @name ENDPTCOMPLETE - Endpoint Complete */
94679 /*! @{ */
94680 
94681 #define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
94682 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
94683 /*! ERCE - ERCE
94684  */
94685 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
94686 
94687 #define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
94688 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
94689 /*! ETCE - ETCE
94690  */
94691 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
94692 /*! @} */
94693 
94694 /*! @name ENDPTCTRL0 - Endpoint Control0 */
94695 /*! @{ */
94696 
94697 #define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
94698 #define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
94699 /*! RXS - RXS
94700  */
94701 #define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
94702 
94703 #define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
94704 #define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
94705 /*! RXT - RXT
94706  */
94707 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
94708 
94709 #define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
94710 #define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
94711 /*! RXE - RXE
94712  */
94713 #define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
94714 
94715 #define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
94716 #define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
94717 /*! TXS - TXS
94718  */
94719 #define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
94720 
94721 #define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
94722 #define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
94723 /*! TXT - TXT
94724  */
94725 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
94726 
94727 #define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
94728 #define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
94729 /*! TXE - TXE
94730  */
94731 #define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
94732 /*! @} */
94733 
94734 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
94735 /*! @{ */
94736 
94737 #define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
94738 #define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
94739 /*! RXS - RXS
94740  */
94741 #define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
94742 
94743 #define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
94744 #define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
94745 /*! RXD - RXD
94746  */
94747 #define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
94748 
94749 #define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
94750 #define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
94751 /*! RXT - RXT
94752  */
94753 #define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
94754 
94755 #define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
94756 #define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
94757 /*! RXI - RXI
94758  */
94759 #define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
94760 
94761 #define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
94762 #define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
94763 /*! RXR - RXR
94764  */
94765 #define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
94766 
94767 #define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
94768 #define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
94769 /*! RXE - RXE
94770  */
94771 #define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
94772 
94773 #define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
94774 #define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
94775 /*! TXS - TXS
94776  */
94777 #define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
94778 
94779 #define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
94780 #define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
94781 /*! TXD - TXD
94782  */
94783 #define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
94784 
94785 #define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
94786 #define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
94787 /*! TXT - TXT
94788  */
94789 #define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
94790 
94791 #define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
94792 #define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
94793 /*! TXI - TXI
94794  */
94795 #define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
94796 
94797 #define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
94798 #define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
94799 /*! TXR - TXR
94800  */
94801 #define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
94802 
94803 #define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
94804 #define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
94805 /*! TXE - TXE
94806  */
94807 #define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
94808 /*! @} */
94809 
94810 /* The count of USB_ENDPTCTRL */
94811 #define USB_ENDPTCTRL_COUNT                      (7U)
94812 
94813 
94814 /*!
94815  * @}
94816  */ /* end of group USB_Register_Masks */
94817 
94818 
94819 /* USB - Peripheral instance base addresses */
94820 /** Peripheral USB_OTG1 base address */
94821 #define USB_OTG1_BASE                            (0x40430000u)
94822 /** Peripheral USB_OTG1 base pointer */
94823 #define USB_OTG1                                 ((USB_Type *)USB_OTG1_BASE)
94824 /** Peripheral USB_OTG2 base address */
94825 #define USB_OTG2_BASE                            (0x4042C000u)
94826 /** Peripheral USB_OTG2 base pointer */
94827 #define USB_OTG2                                 ((USB_Type *)USB_OTG2_BASE)
94828 /** Array initializer of USB peripheral base addresses */
94829 #define USB_BASE_ADDRS                           { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
94830 /** Array initializer of USB peripheral base pointers */
94831 #define USB_BASE_PTRS                            { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
94832 /** Interrupt vectors for the USB peripheral type */
94833 #define USB_IRQS                                 { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
94834 /* Backward compatibility */
94835 #define GPTIMER0CTL                              GPTIMER0CTRL
94836 #define GPTIMER1CTL                              GPTIMER1CTRL
94837 #define USB_SBUSCFG                              SBUSCFG
94838 #define EPLISTADDR                               ENDPTLISTADDR
94839 #define EPSETUPSR                                ENDPTSETUPSTAT
94840 #define EPPRIME                                  ENDPTPRIME
94841 #define EPFLUSH                                  ENDPTFLUSH
94842 #define EPSR                                     ENDPTSTAT
94843 #define EPCOMPLETE                               ENDPTCOMPLETE
94844 #define EPCR                                     ENDPTCTRL
94845 #define EPCR0                                    ENDPTCTRL0
94846 #define USBHS_ID_ID_MASK                         USB_ID_ID_MASK
94847 #define USBHS_ID_ID_SHIFT                        USB_ID_ID_SHIFT
94848 #define USBHS_ID_ID(x)                           USB_ID_ID(x)
94849 #define USBHS_ID_NID_MASK                        USB_ID_NID_MASK
94850 #define USBHS_ID_NID_SHIFT                       USB_ID_NID_SHIFT
94851 #define USBHS_ID_NID(x)                          USB_ID_NID(x)
94852 #define USBHS_ID_REVISION_MASK                   USB_ID_REVISION_MASK
94853 #define USBHS_ID_REVISION_SHIFT                  USB_ID_REVISION_SHIFT
94854 #define USBHS_ID_REVISION(x)                     USB_ID_REVISION(x)
94855 #define USBHS_HWGENERAL_PHYW_MASK                USB_HWGENERAL_PHYW_MASK
94856 #define USBHS_HWGENERAL_PHYW_SHIFT               USB_HWGENERAL_PHYW_SHIFT
94857 #define USBHS_HWGENERAL_PHYW(x)                  USB_HWGENERAL_PHYW(x)
94858 #define USBHS_HWGENERAL_PHYM_MASK                USB_HWGENERAL_PHYM_MASK
94859 #define USBHS_HWGENERAL_PHYM_SHIFT               USB_HWGENERAL_PHYM_SHIFT
94860 #define USBHS_HWGENERAL_PHYM(x)                  USB_HWGENERAL_PHYM(x)
94861 #define USBHS_HWGENERAL_SM_MASK                  USB_HWGENERAL_SM_MASK
94862 #define USBHS_HWGENERAL_SM_SHIFT                 USB_HWGENERAL_SM_SHIFT
94863 #define USBHS_HWGENERAL_SM(x)                    USB_HWGENERAL_SM(x)
94864 #define USBHS_HWHOST_HC_MASK                     USB_HWHOST_HC_MASK
94865 #define USBHS_HWHOST_HC_SHIFT                    USB_HWHOST_HC_SHIFT
94866 #define USBHS_HWHOST_HC(x)                       USB_HWHOST_HC(x)
94867 #define USBHS_HWHOST_NPORT_MASK                  USB_HWHOST_NPORT_MASK
94868 #define USBHS_HWHOST_NPORT_SHIFT                 USB_HWHOST_NPORT_SHIFT
94869 #define USBHS_HWHOST_NPORT(x)                    USB_HWHOST_NPORT(x)
94870 #define USBHS_HWDEVICE_DC_MASK                   USB_HWDEVICE_DC_MASK
94871 #define USBHS_HWDEVICE_DC_SHIFT                  USB_HWDEVICE_DC_SHIFT
94872 #define USBHS_HWDEVICE_DC(x)                     USB_HWDEVICE_DC(x)
94873 #define USBHS_HWDEVICE_DEVEP_MASK                USB_HWDEVICE_DEVEP_MASK
94874 #define USBHS_HWDEVICE_DEVEP_SHIFT               USB_HWDEVICE_DEVEP_SHIFT
94875 #define USBHS_HWDEVICE_DEVEP(x)                  USB_HWDEVICE_DEVEP(x)
94876 #define USBHS_HWTXBUF_TXBURST_MASK               USB_HWTXBUF_TXBURST_MASK
94877 #define USBHS_HWTXBUF_TXBURST_SHIFT              USB_HWTXBUF_TXBURST_SHIFT
94878 #define USBHS_HWTXBUF_TXBURST(x)                 USB_HWTXBUF_TXBURST(x)
94879 #define USBHS_HWTXBUF_TXCHANADD_MASK             USB_HWTXBUF_TXCHANADD_MASK
94880 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            USB_HWTXBUF_TXCHANADD_SHIFT
94881 #define USBHS_HWTXBUF_TXCHANADD(x)               USB_HWTXBUF_TXCHANADD(x)
94882 #define USBHS_HWRXBUF_RXBURST_MASK               USB_HWRXBUF_RXBURST_MASK
94883 #define USBHS_HWRXBUF_RXBURST_SHIFT              USB_HWRXBUF_RXBURST_SHIFT
94884 #define USBHS_HWRXBUF_RXBURST(x)                 USB_HWRXBUF_RXBURST(x)
94885 #define USBHS_HWRXBUF_RXADD_MASK                 USB_HWRXBUF_RXADD_MASK
94886 #define USBHS_HWRXBUF_RXADD_SHIFT                USB_HWRXBUF_RXADD_SHIFT
94887 #define USBHS_HWRXBUF_RXADD(x)                   USB_HWRXBUF_RXADD(x)
94888 #define USBHS_GPTIMER0LD_GPTLD_MASK              USB_GPTIMER0LD_GPTLD_MASK
94889 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             USB_GPTIMER0LD_GPTLD_SHIFT
94890 #define USBHS_GPTIMER0LD_GPTLD(x)                USB_GPTIMER0LD_GPTLD(x)
94891 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            USB_GPTIMER0CTRL_GPTCNT_MASK
94892 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USB_GPTIMER0CTRL_GPTCNT_SHIFT
94893 #define USBHS_GPTIMER0CTL_GPTCNT(x)              USB_GPTIMER0CTRL_GPTCNT(x)
94894 #define USBHS_GPTIMER0CTL_MODE_MASK              USB_GPTIMER0CTRL_GPTMODE_MASK
94895 #define USBHS_GPTIMER0CTL_MODE_SHIFT             USB_GPTIMER0CTRL_GPTMODE_SHIFT
94896 #define USBHS_GPTIMER0CTL_MODE(x)                USB_GPTIMER0CTRL_GPTMODE(x)
94897 #define USBHS_GPTIMER0CTL_RST_MASK               USB_GPTIMER0CTRL_GPTRST_MASK
94898 #define USBHS_GPTIMER0CTL_RST_SHIFT              USB_GPTIMER0CTRL_GPTRST_SHIFT
94899 #define USBHS_GPTIMER0CTL_RST(x)                 USB_GPTIMER0CTRL_GPTRST(x)
94900 #define USBHS_GPTIMER0CTL_RUN_MASK               USB_GPTIMER0CTRL_GPTRUN_MASK
94901 #define USBHS_GPTIMER0CTL_RUN_SHIFT              USB_GPTIMER0CTRL_GPTRUN_SHIFT
94902 #define USBHS_GPTIMER0CTL_RUN(x)                 USB_GPTIMER0CTRL_GPTRUN(x)
94903 #define USBHS_GPTIMER1LD_GPTLD_MASK              USB_GPTIMER1LD_GPTLD_MASK
94904 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             USB_GPTIMER1LD_GPTLD_SHIFT
94905 #define USBHS_GPTIMER1LD_GPTLD(x)                USB_GPTIMER1LD_GPTLD(x)
94906 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            USB_GPTIMER1CTRL_GPTCNT_MASK
94907 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USB_GPTIMER1CTRL_GPTCNT_SHIFT
94908 #define USBHS_GPTIMER1CTL_GPTCNT(x)              USB_GPTIMER1CTRL_GPTCNT(x)
94909 #define USBHS_GPTIMER1CTL_MODE_MASK              USB_GPTIMER1CTRL_GPTMODE_MASK
94910 #define USBHS_GPTIMER1CTL_MODE_SHIFT             USB_GPTIMER1CTRL_GPTMODE_SHIFT
94911 #define USBHS_GPTIMER1CTL_MODE(x)                USB_GPTIMER1CTRL_GPTMODE(x)
94912 #define USBHS_GPTIMER1CTL_RST_MASK               USB_GPTIMER1CTRL_GPTRST_MASK
94913 #define USBHS_GPTIMER1CTL_RST_SHIFT              USB_GPTIMER1CTRL_GPTRST_SHIFT
94914 #define USBHS_GPTIMER1CTL_RST(x)                 USB_GPTIMER1CTRL_GPTRST(x)
94915 #define USBHS_GPTIMER1CTL_RUN_MASK               USB_GPTIMER1CTRL_GPTRUN_MASK
94916 #define USBHS_GPTIMER1CTL_RUN_SHIFT              USB_GPTIMER1CTRL_GPTRUN_SHIFT
94917 #define USBHS_GPTIMER1CTL_RUN(x)                 USB_GPTIMER1CTRL_GPTRUN(x)
94918 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USB_SBUSCFG_AHBBRST_MASK
94919 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USB_SBUSCFG_AHBBRST_SHIFT
94920 #define USBHS_USB_SBUSCFG_BURSTMODE(x)           USB_SBUSCFG_AHBBRST(x)
94921 #define USBHS_HCIVERSION_CAPLENGTH(x)            USB_HCIVERSION_CAPLENGTH(x)
94922 #define USBHS_HCIVERSION_HCIVERSION_MASK         USB_HCIVERSION_HCIVERSION_MASK
94923 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        USB_HCIVERSION_HCIVERSION_SHIFT
94924 #define USBHS_HCIVERSION_HCIVERSION(x)           USB_HCIVERSION_HCIVERSION(x)
94925 #define USBHS_HCSPARAMS_N_PORTS_MASK             USB_HCSPARAMS_N_PORTS_MASK
94926 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            USB_HCSPARAMS_N_PORTS_SHIFT
94927 #define USBHS_HCSPARAMS_N_PORTS(x)               USB_HCSPARAMS_N_PORTS(x)
94928 #define USBHS_HCSPARAMS_PPC_MASK                 USB_HCSPARAMS_PPC_MASK
94929 #define USBHS_HCSPARAMS_PPC_SHIFT                USB_HCSPARAMS_PPC_SHIFT
94930 #define USBHS_HCSPARAMS_PPC(x)                   USB_HCSPARAMS_PPC(x)
94931 #define USBHS_HCSPARAMS_N_PCC_MASK               USB_HCSPARAMS_N_PCC_MASK
94932 #define USBHS_HCSPARAMS_N_PCC_SHIFT              USB_HCSPARAMS_N_PCC_SHIFT
94933 #define USBHS_HCSPARAMS_N_PCC(x)                 USB_HCSPARAMS_N_PCC(x)
94934 #define USBHS_HCSPARAMS_N_CC_MASK                USB_HCSPARAMS_N_CC_MASK
94935 #define USBHS_HCSPARAMS_N_CC_SHIFT               USB_HCSPARAMS_N_CC_SHIFT
94936 #define USBHS_HCSPARAMS_N_CC(x)                  USB_HCSPARAMS_N_CC(x)
94937 #define USBHS_HCSPARAMS_PI_MASK                  USB_HCSPARAMS_PI_MASK
94938 #define USBHS_HCSPARAMS_PI_SHIFT                 USB_HCSPARAMS_PI_SHIFT
94939 #define USBHS_HCSPARAMS_PI(x)                    USB_HCSPARAMS_PI(x)
94940 #define USBHS_HCSPARAMS_N_PTT_MASK               USB_HCSPARAMS_N_PTT_MASK
94941 #define USBHS_HCSPARAMS_N_PTT_SHIFT              USB_HCSPARAMS_N_PTT_SHIFT
94942 #define USBHS_HCSPARAMS_N_PTT(x)                 USB_HCSPARAMS_N_PTT(x)
94943 #define USBHS_HCSPARAMS_N_TT_MASK                USB_HCSPARAMS_N_TT_MASK
94944 #define USBHS_HCSPARAMS_N_TT_SHIFT               USB_HCSPARAMS_N_TT_SHIFT
94945 #define USBHS_HCSPARAMS_N_TT(x)                  USB_HCSPARAMS_N_TT(x)
94946 #define USBHS_HCCPARAMS_ADC_MASK                 USB_HCCPARAMS_ADC_MASK
94947 #define USBHS_HCCPARAMS_ADC_SHIFT                USB_HCCPARAMS_ADC_SHIFT
94948 #define USBHS_HCCPARAMS_ADC(x)                   USB_HCCPARAMS_ADC(x)
94949 #define USBHS_HCCPARAMS_PFL_MASK                 USB_HCCPARAMS_PFL_MASK
94950 #define USBHS_HCCPARAMS_PFL_SHIFT                USB_HCCPARAMS_PFL_SHIFT
94951 #define USBHS_HCCPARAMS_PFL(x)                   USB_HCCPARAMS_PFL(x)
94952 #define USBHS_HCCPARAMS_ASP_MASK                 USB_HCCPARAMS_ASP_MASK
94953 #define USBHS_HCCPARAMS_ASP_SHIFT                USB_HCCPARAMS_ASP_SHIFT
94954 #define USBHS_HCCPARAMS_ASP(x)                   USB_HCCPARAMS_ASP(x)
94955 #define USBHS_HCCPARAMS_IST_MASK                 USB_HCCPARAMS_IST_MASK
94956 #define USBHS_HCCPARAMS_IST_SHIFT                USB_HCCPARAMS_IST_SHIFT
94957 #define USBHS_HCCPARAMS_IST(x)                   USB_HCCPARAMS_IST(x)
94958 #define USBHS_HCCPARAMS_EECP_MASK                USB_HCCPARAMS_EECP_MASK
94959 #define USBHS_HCCPARAMS_EECP_SHIFT               USB_HCCPARAMS_EECP_SHIFT
94960 #define USBHS_HCCPARAMS_EECP(x)                  USB_HCCPARAMS_EECP(x)
94961 #define USBHS_DCIVERSION_DCIVERSION_MASK         USB_DCIVERSION_DCIVERSION_MASK
94962 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        USB_DCIVERSION_DCIVERSION_SHIFT
94963 #define USBHS_DCIVERSION_DCIVERSION(x)           USB_DCIVERSION_DCIVERSION(x)
94964 #define USBHS_DCCPARAMS_DEN_MASK                 USB_DCCPARAMS_DEN_MASK
94965 #define USBHS_DCCPARAMS_DEN_SHIFT                USB_DCCPARAMS_DEN_SHIFT
94966 #define USBHS_DCCPARAMS_DEN(x)                   USB_DCCPARAMS_DEN(x)
94967 #define USBHS_DCCPARAMS_DC_MASK                  USB_DCCPARAMS_DC_MASK
94968 #define USBHS_DCCPARAMS_DC_SHIFT                 USB_DCCPARAMS_DC_SHIFT
94969 #define USBHS_DCCPARAMS_DC(x)                    USB_DCCPARAMS_DC(x)
94970 #define USBHS_DCCPARAMS_HC_MASK                  USB_DCCPARAMS_HC_MASK
94971 #define USBHS_DCCPARAMS_HC_SHIFT                 USB_DCCPARAMS_HC_SHIFT
94972 #define USBHS_DCCPARAMS_HC(x)                    USB_DCCPARAMS_HC(x)
94973 #define USBHS_USBCMD_RS_MASK                     USB_USBCMD_RS_MASK
94974 #define USBHS_USBCMD_RS_SHIFT                    USB_USBCMD_RS_SHIFT
94975 #define USBHS_USBCMD_RS(x)                       USB_USBCMD_RS(x)
94976 #define USBHS_USBCMD_RST_MASK                    USB_USBCMD_RST_MASK
94977 #define USBHS_USBCMD_RST_SHIFT                   USB_USBCMD_RST_SHIFT
94978 #define USBHS_USBCMD_RST(x)                      USB_USBCMD_RST(x)
94979 #define USBHS_USBCMD_FS_MASK                     USB_USBCMD_FS_1_MASK
94980 #define USBHS_USBCMD_FS_SHIFT                    USB_USBCMD_FS_1_SHIFT
94981 #define USBHS_USBCMD_FS(x)                       USB_USBCMD_FS_1(x)
94982 #define USBHS_USBCMD_PSE_MASK                    USB_USBCMD_PSE_MASK
94983 #define USBHS_USBCMD_PSE_SHIFT                   USB_USBCMD_PSE_SHIFT
94984 #define USBHS_USBCMD_PSE(x)                      USB_USBCMD_PSE(x)
94985 #define USBHS_USBCMD_ASE_MASK                    USB_USBCMD_ASE_MASK
94986 #define USBHS_USBCMD_ASE_SHIFT                   USB_USBCMD_ASE_SHIFT
94987 #define USBHS_USBCMD_ASE(x)                      USB_USBCMD_ASE(x)
94988 #define USBHS_USBCMD_IAA_MASK                    USB_USBCMD_IAA_MASK
94989 #define USBHS_USBCMD_IAA_SHIFT                   USB_USBCMD_IAA_SHIFT
94990 #define USBHS_USBCMD_IAA(x)                      USB_USBCMD_IAA(x)
94991 #define USBHS_USBCMD_ASP_MASK                    USB_USBCMD_ASP_MASK
94992 #define USBHS_USBCMD_ASP_SHIFT                   USB_USBCMD_ASP_SHIFT
94993 #define USBHS_USBCMD_ASP(x)                      USB_USBCMD_ASP(x)
94994 #define USBHS_USBCMD_ASPE_MASK                   USB_USBCMD_ASPE_MASK
94995 #define USBHS_USBCMD_ASPE_SHIFT                  USB_USBCMD_ASPE_SHIFT
94996 #define USBHS_USBCMD_ASPE(x)                     USB_USBCMD_ASPE(x)
94997 #define USBHS_USBCMD_ATDTW_MASK                  USB_USBCMD_ATDTW_MASK
94998 #define USBHS_USBCMD_ATDTW_SHIFT                 USB_USBCMD_ATDTW_SHIFT
94999 #define USBHS_USBCMD_ATDTW(x)                    USB_USBCMD_ATDTW(x)
95000 #define USBHS_USBCMD_SUTW_MASK                   USB_USBCMD_SUTW_MASK
95001 #define USBHS_USBCMD_SUTW_SHIFT                  USB_USBCMD_SUTW_SHIFT
95002 #define USBHS_USBCMD_SUTW(x)                     USB_USBCMD_SUTW(x)
95003 #define USBHS_USBCMD_FS2_MASK                    USB_USBCMD_FS_2_MASK
95004 #define USBHS_USBCMD_FS2_SHIFT                   USB_USBCMD_FS_2_SHIFT
95005 #define USBHS_USBCMD_FS2(x)                      USB_USBCMD_FS_2(x)
95006 #define USBHS_USBCMD_ITC_MASK                    USB_USBCMD_ITC_MASK
95007 #define USBHS_USBCMD_ITC_SHIFT                   USB_USBCMD_ITC_SHIFT
95008 #define USBHS_USBCMD_ITC(x)                      USB_USBCMD_ITC(x)
95009 #define USBHS_USBSTS_UI_MASK                     USB_USBSTS_UI_MASK
95010 #define USBHS_USBSTS_UI_SHIFT                    USB_USBSTS_UI_SHIFT
95011 #define USBHS_USBSTS_UI(x)                       USB_USBSTS_UI(x)
95012 #define USBHS_USBSTS_UEI_MASK                    USB_USBSTS_UEI_MASK
95013 #define USBHS_USBSTS_UEI_SHIFT                   USB_USBSTS_UEI_SHIFT
95014 #define USBHS_USBSTS_UEI(x)                      USB_USBSTS_UEI(x)
95015 #define USBHS_USBSTS_PCI_MASK                    USB_USBSTS_PCI_MASK
95016 #define USBHS_USBSTS_PCI_SHIFT                   USB_USBSTS_PCI_SHIFT
95017 #define USBHS_USBSTS_PCI(x)                      USB_USBSTS_PCI(x)
95018 #define USBHS_USBSTS_FRI_MASK                    USB_USBSTS_FRI_MASK
95019 #define USBHS_USBSTS_FRI_SHIFT                   USB_USBSTS_FRI_SHIFT
95020 #define USBHS_USBSTS_FRI(x)                      USB_USBSTS_FRI(x)
95021 #define USBHS_USBSTS_SEI_MASK                    USB_USBSTS_SEI_MASK
95022 #define USBHS_USBSTS_SEI_SHIFT                   USB_USBSTS_SEI_SHIFT
95023 #define USBHS_USBSTS_SEI(x)                      USB_USBSTS_SEI(x)
95024 #define USBHS_USBSTS_AAI_MASK                    USB_USBSTS_AAI_MASK
95025 #define USBHS_USBSTS_AAI_SHIFT                   USB_USBSTS_AAI_SHIFT
95026 #define USBHS_USBSTS_AAI(x)                      USB_USBSTS_AAI(x)
95027 #define USBHS_USBSTS_URI_MASK                    USB_USBSTS_URI_MASK
95028 #define USBHS_USBSTS_URI_SHIFT                   USB_USBSTS_URI_SHIFT
95029 #define USBHS_USBSTS_URI(x)                      USB_USBSTS_URI(x)
95030 #define USBHS_USBSTS_SRI_MASK                    USB_USBSTS_SRI_MASK
95031 #define USBHS_USBSTS_SRI_SHIFT                   USB_USBSTS_SRI_SHIFT
95032 #define USBHS_USBSTS_SRI(x)                      USB_USBSTS_SRI(x)
95033 #define USBHS_USBSTS_SLI_MASK                    USB_USBSTS_SLI_MASK
95034 #define USBHS_USBSTS_SLI_SHIFT                   USB_USBSTS_SLI_SHIFT
95035 #define USBHS_USBSTS_SLI(x)                      USB_USBSTS_SLI(x)
95036 #define USBHS_USBSTS_ULPII_MASK                  USB_USBSTS_ULPII_MASK
95037 #define USBHS_USBSTS_ULPII_SHIFT                 USB_USBSTS_ULPII_SHIFT
95038 #define USBHS_USBSTS_ULPII(x)                    USB_USBSTS_ULPII(x)
95039 #define USBHS_USBSTS_HCH_MASK                    USB_USBSTS_HCH_MASK
95040 #define USBHS_USBSTS_HCH_SHIFT                   USB_USBSTS_HCH_SHIFT
95041 #define USBHS_USBSTS_HCH(x)                      USB_USBSTS_HCH(x)
95042 #define USBHS_USBSTS_RCL_MASK                    USB_USBSTS_RCL_MASK
95043 #define USBHS_USBSTS_RCL_SHIFT                   USB_USBSTS_RCL_SHIFT
95044 #define USBHS_USBSTS_RCL(x)                      USB_USBSTS_RCL(x)
95045 #define USBHS_USBSTS_PS_MASK                     USB_USBSTS_PS_MASK
95046 #define USBHS_USBSTS_PS_SHIFT                    USB_USBSTS_PS_SHIFT
95047 #define USBHS_USBSTS_PS(x)                       USB_USBSTS_PS(x)
95048 #define USBHS_USBSTS_AS_MASK                     USB_USBSTS_AS_MASK
95049 #define USBHS_USBSTS_AS_SHIFT                    USB_USBSTS_AS_SHIFT
95050 #define USBHS_USBSTS_AS(x)                       USB_USBSTS_AS(x)
95051 #define USBHS_USBSTS_NAKI_MASK                   USB_USBSTS_NAKI_MASK
95052 #define USBHS_USBSTS_NAKI_SHIFT                  USB_USBSTS_NAKI_SHIFT
95053 #define USBHS_USBSTS_NAKI(x)                     USB_USBSTS_NAKI(x)
95054 #define USBHS_USBSTS_TI0_MASK                    USB_USBSTS_TI0_MASK
95055 #define USBHS_USBSTS_TI0_SHIFT                   USB_USBSTS_TI0_SHIFT
95056 #define USBHS_USBSTS_TI0(x)                      USB_USBSTS_TI0(x)
95057 #define USBHS_USBSTS_TI1_MASK                    USB_USBSTS_TI1_MASK
95058 #define USBHS_USBSTS_TI1_SHIFT                   USB_USBSTS_TI1_SHIFT
95059 #define USBHS_USBSTS_TI1(x)                      USB_USBSTS_TI1(x)
95060 #define USBHS_USBINTR_UE_MASK                    USB_USBINTR_UE_MASK
95061 #define USBHS_USBINTR_UE_SHIFT                   USB_USBINTR_UE_SHIFT
95062 #define USBHS_USBINTR_UE(x)                      USB_USBINTR_UE(x)
95063 #define USBHS_USBINTR_UEE_MASK                   USB_USBINTR_UEE_MASK
95064 #define USBHS_USBINTR_UEE_SHIFT                  USB_USBINTR_UEE_SHIFT
95065 #define USBHS_USBINTR_UEE(x)                     USB_USBINTR_UEE(x)
95066 #define USBHS_USBINTR_PCE_MASK                   USB_USBINTR_PCE_MASK
95067 #define USBHS_USBINTR_PCE_SHIFT                  USB_USBINTR_PCE_SHIFT
95068 #define USBHS_USBINTR_PCE(x)                     USB_USBINTR_PCE(x)
95069 #define USBHS_USBINTR_FRE_MASK                   USB_USBINTR_FRE_MASK
95070 #define USBHS_USBINTR_FRE_SHIFT                  USB_USBINTR_FRE_SHIFT
95071 #define USBHS_USBINTR_FRE(x)                     USB_USBINTR_FRE(x)
95072 #define USBHS_USBINTR_SEE_MASK                   USB_USBINTR_SEE_MASK
95073 #define USBHS_USBINTR_SEE_SHIFT                  USB_USBINTR_SEE_SHIFT
95074 #define USBHS_USBINTR_SEE(x)                     USB_USBINTR_SEE(x)
95075 #define USBHS_USBINTR_AAE_MASK                   USB_USBINTR_AAE_MASK
95076 #define USBHS_USBINTR_AAE_SHIFT                  USB_USBINTR_AAE_SHIFT
95077 #define USBHS_USBINTR_AAE(x)                     USB_USBINTR_AAE(x)
95078 #define USBHS_USBINTR_URE_MASK                   USB_USBINTR_URE_MASK
95079 #define USBHS_USBINTR_URE_SHIFT                  USB_USBINTR_URE_SHIFT
95080 #define USBHS_USBINTR_URE(x)                     USB_USBINTR_URE(x)
95081 #define USBHS_USBINTR_SRE_MASK                   USB_USBINTR_SRE_MASK
95082 #define USBHS_USBINTR_SRE_SHIFT                  USB_USBINTR_SRE_SHIFT
95083 #define USBHS_USBINTR_SRE(x)                     USB_USBINTR_SRE(x)
95084 #define USBHS_USBINTR_SLE_MASK                   USB_USBINTR_SLE_MASK
95085 #define USBHS_USBINTR_SLE_SHIFT                  USB_USBINTR_SLE_SHIFT
95086 #define USBHS_USBINTR_SLE(x)                     USB_USBINTR_SLE(x)
95087 #define USBHS_USBINTR_ULPIE_MASK                 USB_USBINTR_ULPIE_MASK
95088 #define USBHS_USBINTR_ULPIE_SHIFT                USB_USBINTR_ULPIE_SHIFT
95089 #define USBHS_USBINTR_ULPIE(x)                   USB_USBINTR_ULPIE(x)
95090 #define USBHS_USBINTR_NAKE_MASK                  USB_USBINTR_NAKE_MASK
95091 #define USBHS_USBINTR_NAKE_SHIFT                 USB_USBINTR_NAKE_SHIFT
95092 #define USBHS_USBINTR_NAKE(x)                    USB_USBINTR_NAKE(x)
95093 #define USBHS_USBINTR_UAIE_MASK                  USB_USBINTR_UAIE_MASK
95094 #define USBHS_USBINTR_UAIE_SHIFT                 USB_USBINTR_UAIE_SHIFT
95095 #define USBHS_USBINTR_UAIE(x)                    USB_USBINTR_UAIE(x)
95096 #define USBHS_USBINTR_UPIE_MASK                  USB_USBINTR_UPIE_MASK
95097 #define USBHS_USBINTR_UPIE_SHIFT                 USB_USBINTR_UPIE_SHIFT
95098 #define USBHS_USBINTR_UPIE(x)                    USB_USBINTR_UPIE(x)
95099 #define USBHS_USBINTR_TIE0_MASK                  USB_USBINTR_TIE0_MASK
95100 #define USBHS_USBINTR_TIE0_SHIFT                 USB_USBINTR_TIE0_SHIFT
95101 #define USBHS_USBINTR_TIE0(x)                    USB_USBINTR_TIE0(x)
95102 #define USBHS_USBINTR_TIE1_MASK                  USB_USBINTR_TIE1_MASK
95103 #define USBHS_USBINTR_TIE1_SHIFT                 USB_USBINTR_TIE1_SHIFT
95104 #define USBHS_USBINTR_TIE1(x)                    USB_USBINTR_TIE1(x)
95105 #define USBHS_FRINDEX_FRINDEX_MASK               USB_FRINDEX_FRINDEX_MASK
95106 #define USBHS_FRINDEX_FRINDEX_SHIFT              USB_FRINDEX_FRINDEX_SHIFT
95107 #define USBHS_FRINDEX_FRINDEX(x)                 USB_FRINDEX_FRINDEX(x)
95108 #define USBHS_DEVICEADDR_USBADRA_MASK            USB_DEVICEADDR_USBADRA_MASK
95109 #define USBHS_DEVICEADDR_USBADRA_SHIFT           USB_DEVICEADDR_USBADRA_SHIFT
95110 #define USBHS_DEVICEADDR_USBADRA(x)              USB_DEVICEADDR_USBADRA(x)
95111 #define USBHS_DEVICEADDR_USBADR_MASK             USB_DEVICEADDR_USBADR_MASK
95112 #define USBHS_DEVICEADDR_USBADR_SHIFT            USB_DEVICEADDR_USBADR_SHIFT
95113 #define USBHS_DEVICEADDR_USBADR(x)               USB_DEVICEADDR_USBADR(x)
95114 #define USBHS_PERIODICLISTBASE_PERBASE_MASK      USB_PERIODICLISTBASE_BASEADR_MASK
95115 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USB_PERIODICLISTBASE_BASEADR_SHIFT
95116 #define USBHS_PERIODICLISTBASE_PERBASE(x)        USB_PERIODICLISTBASE_BASEADR(x)
95117 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USB_ASYNCLISTADDR_ASYBASE_MASK
95118 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USB_ASYNCLISTADDR_ASYBASE_SHIFT
95119 #define USBHS_ASYNCLISTADDR_ASYBASE(x)           USB_ASYNCLISTADDR_ASYBASE(x)
95120 #define USBHS_EPLISTADDR_EPBASE_MASK             USB_ENDPTLISTADDR_EPBASE_MASK
95121 #define USBHS_EPLISTADDR_EPBASE_SHIFT            USB_ENDPTLISTADDR_EPBASE_SHIFT
95122 #define USBHS_EPLISTADDR_EPBASE(x)               USB_ENDPTLISTADDR_EPBASE(x)
95123 #define USBHS_BURSTSIZE_RXPBURST_MASK            USB_BURSTSIZE_RXPBURST_MASK
95124 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           USB_BURSTSIZE_RXPBURST_SHIFT
95125 #define USBHS_BURSTSIZE_RXPBURST(x)              USB_BURSTSIZE_RXPBURST(x)
95126 #define USBHS_BURSTSIZE_TXPBURST_MASK            USB_BURSTSIZE_TXPBURST_MASK
95127 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           USB_BURSTSIZE_TXPBURST_SHIFT
95128 #define USBHS_BURSTSIZE_TXPBURST(x)              USB_BURSTSIZE_TXPBURST(x)
95129 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          USB_TXFILLTUNING_TXSCHOH_MASK
95130 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USB_TXFILLTUNING_TXSCHOH_SHIFT
95131 #define USBHS_TXFILLTUNING_TXSCHOH(x)            USB_TXFILLTUNING_TXSCHOH(x)
95132 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USB_TXFILLTUNING_TXSCHHEALTH_MASK
95133 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
95134 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USB_TXFILLTUNING_TXSCHHEALTH(x)
95135 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USB_TXFILLTUNING_TXFIFOTHRES_MASK
95136 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
95137 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USB_TXFILLTUNING_TXFIFOTHRES(x)
95138 #define USBHS_ENDPTNAK_EPRN_MASK                 USB_ENDPTNAK_EPRN_MASK
95139 #define USBHS_ENDPTNAK_EPRN_SHIFT                USB_ENDPTNAK_EPRN_SHIFT
95140 #define USBHS_ENDPTNAK_EPRN(x)                   USB_ENDPTNAK_EPRN(x)
95141 #define USBHS_ENDPTNAK_EPTN_MASK                 USB_ENDPTNAK_EPTN_MASK
95142 #define USBHS_ENDPTNAK_EPTN_SHIFT                USB_ENDPTNAK_EPTN_SHIFT
95143 #define USBHS_ENDPTNAK_EPTN(x)                   USB_ENDPTNAK_EPTN(x)
95144 #define USBHS_ENDPTNAKEN_EPRNE_MASK              USB_ENDPTNAKEN_EPRNE_MASK
95145 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USB_ENDPTNAKEN_EPRNE_SHIFT
95146 #define USBHS_ENDPTNAKEN_EPRNE(x)                USB_ENDPTNAKEN_EPRNE(x)
95147 #define USBHS_ENDPTNAKEN_EPTNE_MASK              USB_ENDPTNAKEN_EPTNE_MASK
95148 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USB_ENDPTNAKEN_EPTNE_SHIFT
95149 #define USBHS_ENDPTNAKEN_EPTNE(x)                USB_ENDPTNAKEN_EPTNE(x)
95150 #define USBHS_CONFIGFLAG_CF_MASK                 USB_CONFIGFLAG_CF_MASK
95151 #define USBHS_CONFIGFLAG_CF_SHIFT                USB_CONFIGFLAG_CF_SHIFT
95152 #define USBHS_CONFIGFLAG_CF(x)                   USB_CONFIGFLAG_CF(x)
95153 #define USBHS_PORTSC1_CCS_MASK                   USB_PORTSC1_CCS_MASK
95154 #define USBHS_PORTSC1_CCS_SHIFT                  USB_PORTSC1_CCS_SHIFT
95155 #define USBHS_PORTSC1_CCS(x)                     USB_PORTSC1_CCS(x)
95156 #define USBHS_PORTSC1_CSC_MASK                   USB_PORTSC1_CSC_MASK
95157 #define USBHS_PORTSC1_CSC_SHIFT                  USB_PORTSC1_CSC_SHIFT
95158 #define USBHS_PORTSC1_CSC(x)                     USB_PORTSC1_CSC(x)
95159 #define USBHS_PORTSC1_PE_MASK                    USB_PORTSC1_PE_MASK
95160 #define USBHS_PORTSC1_PE_SHIFT                   USB_PORTSC1_PE_SHIFT
95161 #define USBHS_PORTSC1_PE(x)                      USB_PORTSC1_PE(x)
95162 #define USBHS_PORTSC1_PEC_MASK                   USB_PORTSC1_PEC_MASK
95163 #define USBHS_PORTSC1_PEC_SHIFT                  USB_PORTSC1_PEC_SHIFT
95164 #define USBHS_PORTSC1_PEC(x)                     USB_PORTSC1_PEC(x)
95165 #define USBHS_PORTSC1_OCA_MASK                   USB_PORTSC1_OCA_MASK
95166 #define USBHS_PORTSC1_OCA_SHIFT                  USB_PORTSC1_OCA_SHIFT
95167 #define USBHS_PORTSC1_OCA(x)                     USB_PORTSC1_OCA(x)
95168 #define USBHS_PORTSC1_OCC_MASK                   USB_PORTSC1_OCC_MASK
95169 #define USBHS_PORTSC1_OCC_SHIFT                  USB_PORTSC1_OCC_SHIFT
95170 #define USBHS_PORTSC1_OCC(x)                     USB_PORTSC1_OCC(x)
95171 #define USBHS_PORTSC1_FPR_MASK                   USB_PORTSC1_FPR_MASK
95172 #define USBHS_PORTSC1_FPR_SHIFT                  USB_PORTSC1_FPR_SHIFT
95173 #define USBHS_PORTSC1_FPR(x)                     USB_PORTSC1_FPR(x)
95174 #define USBHS_PORTSC1_SUSP_MASK                  USB_PORTSC1_SUSP_MASK
95175 #define USBHS_PORTSC1_SUSP_SHIFT                 USB_PORTSC1_SUSP_SHIFT
95176 #define USBHS_PORTSC1_SUSP(x)                    USB_PORTSC1_SUSP(x)
95177 #define USBHS_PORTSC1_PR_MASK                    USB_PORTSC1_PR_MASK
95178 #define USBHS_PORTSC1_PR_SHIFT                   USB_PORTSC1_PR_SHIFT
95179 #define USBHS_PORTSC1_PR(x)                      USB_PORTSC1_PR(x)
95180 #define USBHS_PORTSC1_HSP_MASK                   USB_PORTSC1_HSP_MASK
95181 #define USBHS_PORTSC1_HSP_SHIFT                  USB_PORTSC1_HSP_SHIFT
95182 #define USBHS_PORTSC1_HSP(x)                     USB_PORTSC1_HSP(x)
95183 #define USBHS_PORTSC1_LS_MASK                    USB_PORTSC1_LS_MASK
95184 #define USBHS_PORTSC1_LS_SHIFT                   USB_PORTSC1_LS_SHIFT
95185 #define USBHS_PORTSC1_LS(x)                      USB_PORTSC1_LS(x)
95186 #define USBHS_PORTSC1_PP_MASK                    USB_PORTSC1_PP_MASK
95187 #define USBHS_PORTSC1_PP_SHIFT                   USB_PORTSC1_PP_SHIFT
95188 #define USBHS_PORTSC1_PP(x)                      USB_PORTSC1_PP(x)
95189 #define USBHS_PORTSC1_PO_MASK                    USB_PORTSC1_PO_MASK
95190 #define USBHS_PORTSC1_PO_SHIFT                   USB_PORTSC1_PO_SHIFT
95191 #define USBHS_PORTSC1_PO(x)                      USB_PORTSC1_PO(x)
95192 #define USBHS_PORTSC1_PIC_MASK                   USB_PORTSC1_PIC_MASK
95193 #define USBHS_PORTSC1_PIC_SHIFT                  USB_PORTSC1_PIC_SHIFT
95194 #define USBHS_PORTSC1_PIC(x)                     USB_PORTSC1_PIC(x)
95195 #define USBHS_PORTSC1_PTC_MASK                   USB_PORTSC1_PTC_MASK
95196 #define USBHS_PORTSC1_PTC_SHIFT                  USB_PORTSC1_PTC_SHIFT
95197 #define USBHS_PORTSC1_PTC(x)                     USB_PORTSC1_PTC(x)
95198 #define USBHS_PORTSC1_WKCN_MASK                  USB_PORTSC1_WKCN_MASK
95199 #define USBHS_PORTSC1_WKCN_SHIFT                 USB_PORTSC1_WKCN_SHIFT
95200 #define USBHS_PORTSC1_WKCN(x)                    USB_PORTSC1_WKCN(x)
95201 #define USBHS_PORTSC1_WKDS_MASK                  USB_PORTSC1_WKDC_MASK
95202 #define USBHS_PORTSC1_WKDS_SHIFT                 USB_PORTSC1_WKDC_SHIFT
95203 #define USBHS_PORTSC1_WKDS(x)                    USB_PORTSC1_WKDC(x)
95204 #define USBHS_PORTSC1_WKOC_MASK                  USB_PORTSC1_WKOC_MASK
95205 #define USBHS_PORTSC1_WKOC_SHIFT                 USB_PORTSC1_WKOC_SHIFT
95206 #define USBHS_PORTSC1_WKOC(x)                    USB_PORTSC1_WKOC(x)
95207 #define USBHS_PORTSC1_PHCD_MASK                  USB_PORTSC1_PHCD_MASK
95208 #define USBHS_PORTSC1_PHCD_SHIFT                 USB_PORTSC1_PHCD_SHIFT
95209 #define USBHS_PORTSC1_PHCD(x)                    USB_PORTSC1_PHCD(x)
95210 #define USBHS_PORTSC1_PFSC_MASK                  USB_PORTSC1_PFSC_MASK
95211 #define USBHS_PORTSC1_PFSC_SHIFT                 USB_PORTSC1_PFSC_SHIFT
95212 #define USBHS_PORTSC1_PFSC(x)                    USB_PORTSC1_PFSC(x)
95213 #define USBHS_PORTSC1_PTS2_MASK                  USB_PORTSC1_PTS_2_MASK
95214 #define USBHS_PORTSC1_PTS2_SHIFT                 USB_PORTSC1_PTS_2_SHIFT
95215 #define USBHS_PORTSC1_PTS2(x)                    USB_PORTSC1_PTS_2(x)
95216 #define USBHS_PORTSC1_PSPD_MASK                  USB_PORTSC1_PSPD_MASK
95217 #define USBHS_PORTSC1_PSPD_SHIFT                 USB_PORTSC1_PSPD_SHIFT
95218 #define USBHS_PORTSC1_PSPD(x)                    USB_PORTSC1_PSPD(x)
95219 #define USBHS_PORTSC1_PTW_MASK                   USB_PORTSC1_PTW_MASK
95220 #define USBHS_PORTSC1_PTW_SHIFT                  USB_PORTSC1_PTW_SHIFT
95221 #define USBHS_PORTSC1_PTW(x)                     USB_PORTSC1_PTW(x)
95222 #define USBHS_PORTSC1_STS_MASK                   USB_PORTSC1_STS_MASK
95223 #define USBHS_PORTSC1_STS_SHIFT                  USB_PORTSC1_STS_SHIFT
95224 #define USBHS_PORTSC1_STS(x)                     USB_PORTSC1_STS(x)
95225 #define USBHS_PORTSC1_PTS_MASK                   USB_PORTSC1_PTS_1_MASK
95226 #define USBHS_PORTSC1_PTS_SHIFT                  USB_PORTSC1_PTS_1_SHIFT
95227 #define USBHS_PORTSC1_PTS(x)                     USB_PORTSC1_PTS_1(x)
95228 #define USBHS_OTGSC_VD_MASK                      USB_OTGSC_VD_MASK
95229 #define USBHS_OTGSC_VD_SHIFT                     USB_OTGSC_VD_SHIFT
95230 #define USBHS_OTGSC_VD(x)                        USB_OTGSC_VD(x)
95231 #define USBHS_OTGSC_VC_MASK                      USB_OTGSC_VC_MASK
95232 #define USBHS_OTGSC_VC_SHIFT                     USB_OTGSC_VC_SHIFT
95233 #define USBHS_OTGSC_VC(x)                        USB_OTGSC_VC(x)
95234 #define USBHS_OTGSC_OT_MASK                      USB_OTGSC_OT_MASK
95235 #define USBHS_OTGSC_OT_SHIFT                     USB_OTGSC_OT_SHIFT
95236 #define USBHS_OTGSC_OT(x)                        USB_OTGSC_OT(x)
95237 #define USBHS_OTGSC_DP_MASK                      USB_OTGSC_DP_MASK
95238 #define USBHS_OTGSC_DP_SHIFT                     USB_OTGSC_DP_SHIFT
95239 #define USBHS_OTGSC_DP(x)                        USB_OTGSC_DP(x)
95240 #define USBHS_OTGSC_IDPU_MASK                    USB_OTGSC_IDPU_MASK
95241 #define USBHS_OTGSC_IDPU_SHIFT                   USB_OTGSC_IDPU_SHIFT
95242 #define USBHS_OTGSC_IDPU(x)                      USB_OTGSC_IDPU(x)
95243 #define USBHS_OTGSC_ID_MASK                      USB_OTGSC_ID_MASK
95244 #define USBHS_OTGSC_ID_SHIFT                     USB_OTGSC_ID_SHIFT
95245 #define USBHS_OTGSC_ID(x)                        USB_OTGSC_ID(x)
95246 #define USBHS_OTGSC_AVV_MASK                     USB_OTGSC_AVV_MASK
95247 #define USBHS_OTGSC_AVV_SHIFT                    USB_OTGSC_AVV_SHIFT
95248 #define USBHS_OTGSC_AVV(x)                       USB_OTGSC_AVV(x)
95249 #define USBHS_OTGSC_ASV_MASK                     USB_OTGSC_ASV_MASK
95250 #define USBHS_OTGSC_ASV_SHIFT                    USB_OTGSC_ASV_SHIFT
95251 #define USBHS_OTGSC_ASV(x)                       USB_OTGSC_ASV(x)
95252 #define USBHS_OTGSC_BSV_MASK                     USB_OTGSC_BSV_MASK
95253 #define USBHS_OTGSC_BSV_SHIFT                    USB_OTGSC_BSV_SHIFT
95254 #define USBHS_OTGSC_BSV(x)                       USB_OTGSC_BSV(x)
95255 #define USBHS_OTGSC_BSE_MASK                     USB_OTGSC_BSE_MASK
95256 #define USBHS_OTGSC_BSE_SHIFT                    USB_OTGSC_BSE_SHIFT
95257 #define USBHS_OTGSC_BSE(x)                       USB_OTGSC_BSE(x)
95258 #define USBHS_OTGSC_MST_MASK                     USB_OTGSC_TOG_1MS_MASK
95259 #define USBHS_OTGSC_MST_SHIFT                    USB_OTGSC_TOG_1MS_SHIFT
95260 #define USBHS_OTGSC_MST(x)                       USB_OTGSC_TOG_1MS(x)
95261 #define USBHS_OTGSC_DPS_MASK                     USB_OTGSC_DPS_MASK
95262 #define USBHS_OTGSC_DPS_SHIFT                    USB_OTGSC_DPS_SHIFT
95263 #define USBHS_OTGSC_DPS(x)                       USB_OTGSC_DPS(x)
95264 #define USBHS_OTGSC_IDIS_MASK                    USB_OTGSC_IDIS_MASK
95265 #define USBHS_OTGSC_IDIS_SHIFT                   USB_OTGSC_IDIS_SHIFT
95266 #define USBHS_OTGSC_IDIS(x)                      USB_OTGSC_IDIS(x)
95267 #define USBHS_OTGSC_AVVIS_MASK                   USB_OTGSC_AVVIS_MASK
95268 #define USBHS_OTGSC_AVVIS_SHIFT                  USB_OTGSC_AVVIS_SHIFT
95269 #define USBHS_OTGSC_AVVIS(x)                     USB_OTGSC_AVVIS(x)
95270 #define USBHS_OTGSC_ASVIS_MASK                   USB_OTGSC_ASVIS_MASK
95271 #define USBHS_OTGSC_ASVIS_SHIFT                  USB_OTGSC_ASVIS_SHIFT
95272 #define USBHS_OTGSC_ASVIS(x)                     USB_OTGSC_ASVIS(x)
95273 #define USBHS_OTGSC_BSVIS_MASK                   USB_OTGSC_BSVIS_MASK
95274 #define USBHS_OTGSC_BSVIS_SHIFT                  USB_OTGSC_BSVIS_SHIFT
95275 #define USBHS_OTGSC_BSVIS(x)                     USB_OTGSC_BSVIS(x)
95276 #define USBHS_OTGSC_BSEIS_MASK                   USB_OTGSC_BSEIS_MASK
95277 #define USBHS_OTGSC_BSEIS_SHIFT                  USB_OTGSC_BSEIS_SHIFT
95278 #define USBHS_OTGSC_BSEIS(x)                     USB_OTGSC_BSEIS(x)
95279 #define USBHS_OTGSC_MSS_MASK                     USB_OTGSC_STATUS_1MS_MASK
95280 #define USBHS_OTGSC_MSS_SHIFT                    USB_OTGSC_STATUS_1MS_SHIFT
95281 #define USBHS_OTGSC_MSS(x)                       USB_OTGSC_STATUS_1MS(x)
95282 #define USBHS_OTGSC_DPIS_MASK                    USB_OTGSC_DPIS_MASK
95283 #define USBHS_OTGSC_DPIS_SHIFT                   USB_OTGSC_DPIS_SHIFT
95284 #define USBHS_OTGSC_DPIS(x)                      USB_OTGSC_DPIS(x)
95285 #define USBHS_OTGSC_IDIE_MASK                    USB_OTGSC_IDIE_MASK
95286 #define USBHS_OTGSC_IDIE_SHIFT                   USB_OTGSC_IDIE_SHIFT
95287 #define USBHS_OTGSC_IDIE(x)                      USB_OTGSC_IDIE(x)
95288 #define USBHS_OTGSC_AVVIE_MASK                   USB_OTGSC_AVVIE_MASK
95289 #define USBHS_OTGSC_AVVIE_SHIFT                  USB_OTGSC_AVVIE_SHIFT
95290 #define USBHS_OTGSC_AVVIE(x)                     USB_OTGSC_AVVIE(x)
95291 #define USBHS_OTGSC_ASVIE_MASK                   USB_OTGSC_ASVIE_MASK
95292 #define USBHS_OTGSC_ASVIE_SHIFT                  USB_OTGSC_ASVIE_SHIFT
95293 #define USBHS_OTGSC_ASVIE(x)                     USB_OTGSC_ASVIE(x)
95294 #define USBHS_OTGSC_BSVIE_MASK                   USB_OTGSC_BSVIE_MASK
95295 #define USBHS_OTGSC_BSVIE_SHIFT                  USB_OTGSC_BSVIE_SHIFT
95296 #define USBHS_OTGSC_BSVIE(x)                     USB_OTGSC_BSVIE(x)
95297 #define USBHS_OTGSC_BSEIE_MASK                   USB_OTGSC_BSEIE_MASK
95298 #define USBHS_OTGSC_BSEIE_SHIFT                  USB_OTGSC_BSEIE_SHIFT
95299 #define USBHS_OTGSC_BSEIE(x)                     USB_OTGSC_BSEIE(x)
95300 #define USBHS_OTGSC_MSE_MASK                     USB_OTGSC_EN_1MS_MASK
95301 #define USBHS_OTGSC_MSE_SHIFT                    USB_OTGSC_EN_1MS_SHIFT
95302 #define USBHS_OTGSC_MSE(x)                       USB_OTGSC_EN_1MS(x)
95303 #define USBHS_OTGSC_DPIE_MASK                    USB_OTGSC_DPIE_MASK
95304 #define USBHS_OTGSC_DPIE_SHIFT                   USB_OTGSC_DPIE_SHIFT
95305 #define USBHS_OTGSC_DPIE(x)                      USB_OTGSC_DPIE(x)
95306 #define USBHS_USBMODE_CM_MASK                    USB_USBMODE_CM_MASK
95307 #define USBHS_USBMODE_CM_SHIFT                   USB_USBMODE_CM_SHIFT
95308 #define USBHS_USBMODE_CM(x)                      USB_USBMODE_CM(x)
95309 #define USBHS_USBMODE_ES_MASK                    USB_USBMODE_ES_MASK
95310 #define USBHS_USBMODE_ES_SHIFT                   USB_USBMODE_ES_SHIFT
95311 #define USBHS_USBMODE_ES(x)                      USB_USBMODE_ES(x)
95312 #define USBHS_USBMODE_SLOM_MASK                  USB_USBMODE_SLOM_MASK
95313 #define USBHS_USBMODE_SLOM_SHIFT                 USB_USBMODE_SLOM_SHIFT
95314 #define USBHS_USBMODE_SLOM(x)                    USB_USBMODE_SLOM(x)
95315 #define USBHS_USBMODE_SDIS_MASK                  USB_USBMODE_SDIS_MASK
95316 #define USBHS_USBMODE_SDIS_SHIFT                 USB_USBMODE_SDIS_SHIFT
95317 #define USBHS_USBMODE_SDIS(x)                    USB_USBMODE_SDIS(x)
95318 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
95319 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
95320 #define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
95321 #define USBHS_EPPRIME_PERB_MASK                  USB_ENDPTPRIME_PERB_MASK
95322 #define USBHS_EPPRIME_PERB_SHIFT                 USB_ENDPTPRIME_PERB_SHIFT
95323 #define USBHS_EPPRIME_PERB(x)                    USB_ENDPTPRIME_PERB(x)
95324 #define USBHS_EPPRIME_PETB_MASK                  USB_ENDPTPRIME_PETB_MASK
95325 #define USBHS_EPPRIME_PETB_SHIFT                 USB_ENDPTPRIME_PETB_SHIFT
95326 #define USBHS_EPPRIME_PETB(x)                    USB_ENDPTPRIME_PETB(x)
95327 #define USBHS_EPFLUSH_FERB_MASK                  USB_ENDPTFLUSH_FERB_MASK
95328 #define USBHS_EPFLUSH_FERB_SHIFT                 USB_ENDPTFLUSH_FERB_SHIFT
95329 #define USBHS_EPFLUSH_FERB(x)                    USB_ENDPTFLUSH_FERB(x)
95330 #define USBHS_EPFLUSH_FETB_MASK                  USB_ENDPTFLUSH_FETB_MASK
95331 #define USBHS_EPFLUSH_FETB_SHIFT                 USB_ENDPTFLUSH_FETB_SHIFT
95332 #define USBHS_EPFLUSH_FETB(x)                    USB_ENDPTFLUSH_FETB(x)
95333 #define USBHS_EPSR_ERBR_MASK                     USB_ENDPTSTAT_ERBR_MASK
95334 #define USBHS_EPSR_ERBR_SHIFT                    USB_ENDPTSTAT_ERBR_SHIFT
95335 #define USBHS_EPSR_ERBR(x)                       USB_ENDPTSTAT_ERBR(x)
95336 #define USBHS_EPSR_ETBR_MASK                     USB_ENDPTSTAT_ETBR_MASK
95337 #define USBHS_EPSR_ETBR_SHIFT                    USB_ENDPTSTAT_ETBR_SHIFT
95338 #define USBHS_EPSR_ETBR(x)                       USB_ENDPTSTAT_ETBR(x)
95339 #define USBHS_EPCOMPLETE_ERCE_MASK               USB_ENDPTCOMPLETE_ERCE_MASK
95340 #define USBHS_EPCOMPLETE_ERCE_SHIFT              USB_ENDPTCOMPLETE_ERCE_SHIFT
95341 #define USBHS_EPCOMPLETE_ERCE(x)                 USB_ENDPTCOMPLETE_ERCE(x)
95342 #define USBHS_EPCOMPLETE_ETCE_MASK               USB_ENDPTCOMPLETE_ETCE_MASK
95343 #define USBHS_EPCOMPLETE_ETCE_SHIFT              USB_ENDPTCOMPLETE_ETCE_SHIFT
95344 #define USBHS_EPCOMPLETE_ETCE(x)                 USB_ENDPTCOMPLETE_ETCE(x)
95345 #define USBHS_EPCR0_RXS_MASK                     USB_ENDPTCTRL0_RXS_MASK
95346 #define USBHS_EPCR0_RXS_SHIFT                    USB_ENDPTCTRL0_RXS_SHIFT
95347 #define USBHS_EPCR0_RXS(x)                       USB_ENDPTCTRL0_RXS(x)
95348 #define USBHS_EPCR0_RXT_MASK                     USB_ENDPTCTRL0_RXT_MASK
95349 #define USBHS_EPCR0_RXT_SHIFT                    USB_ENDPTCTRL0_RXT_SHIFT
95350 #define USBHS_EPCR0_RXT(x)                       USB_ENDPTCTRL0_RXT(x)
95351 #define USBHS_EPCR0_RXE_MASK                     USB_ENDPTCTRL0_RXE_MASK
95352 #define USBHS_EPCR0_RXE_SHIFT                    USB_ENDPTCTRL0_RXE_SHIFT
95353 #define USBHS_EPCR0_RXE(x)                       USB_ENDPTCTRL0_RXE(x)
95354 #define USBHS_EPCR0_TXS_MASK                     USB_ENDPTCTRL0_TXS_MASK
95355 #define USBHS_EPCR0_TXS_SHIFT                    USB_ENDPTCTRL0_TXS_SHIFT
95356 #define USBHS_EPCR0_TXS(x)                       USB_ENDPTCTRL0_TXS(x)
95357 #define USBHS_EPCR0_TXT_MASK                     USB_ENDPTCTRL0_TXT_MASK
95358 #define USBHS_EPCR0_TXT_SHIFT                    USB_ENDPTCTRL0_TXT_SHIFT
95359 #define USBHS_EPCR0_TXT(x)                       USB_ENDPTCTRL0_TXT(x)
95360 #define USBHS_EPCR0_TXE_MASK                     USB_ENDPTCTRL0_TXE_MASK
95361 #define USBHS_EPCR0_TXE_SHIFT                    USB_ENDPTCTRL0_TXE_SHIFT
95362 #define USBHS_EPCR0_TXE(x)                       USB_ENDPTCTRL0_TXE(x)
95363 #define USBHS_EPCR_RXS_MASK                      USB_ENDPTCTRL_RXS_MASK
95364 #define USBHS_EPCR_RXS_SHIFT                     USB_ENDPTCTRL_RXS_SHIFT
95365 #define USBHS_EPCR_RXS(x)                        USB_ENDPTCTRL_RXS(x)
95366 #define USBHS_EPCR_RXD_MASK                      USB_ENDPTCTRL_RXD_MASK
95367 #define USBHS_EPCR_RXD_SHIFT                     USB_ENDPTCTRL_RXD_SHIFT
95368 #define USBHS_EPCR_RXD(x)                        USB_ENDPTCTRL_RXD(x)
95369 #define USBHS_EPCR_RXT_MASK                      USB_ENDPTCTRL_RXT_MASK
95370 #define USBHS_EPCR_RXT_SHIFT                     USB_ENDPTCTRL_RXT_SHIFT
95371 #define USBHS_EPCR_RXT(x)                        USB_ENDPTCTRL_RXT(x)
95372 #define USBHS_EPCR_RXI_MASK                      USB_ENDPTCTRL_RXI_MASK
95373 #define USBHS_EPCR_RXI_SHIFT                     USB_ENDPTCTRL_RXI_SHIFT
95374 #define USBHS_EPCR_RXI(x)                        USB_ENDPTCTRL_RXI(x)
95375 #define USBHS_EPCR_RXR_MASK                      USB_ENDPTCTRL_RXR_MASK
95376 #define USBHS_EPCR_RXR_SHIFT                     USB_ENDPTCTRL_RXR_SHIFT
95377 #define USBHS_EPCR_RXR(x)                        USB_ENDPTCTRL_RXR(x)
95378 #define USBHS_EPCR_RXE_MASK                      USB_ENDPTCTRL_RXE_MASK
95379 #define USBHS_EPCR_RXE_SHIFT                     USB_ENDPTCTRL_RXE_SHIFT
95380 #define USBHS_EPCR_RXE(x)                        USB_ENDPTCTRL_RXE(x)
95381 #define USBHS_EPCR_TXS_MASK                      USB_ENDPTCTRL_TXS_MASK
95382 #define USBHS_EPCR_TXS_SHIFT                     USB_ENDPTCTRL_TXS_SHIFT
95383 #define USBHS_EPCR_TXS(x)                        USB_ENDPTCTRL_TXS(x)
95384 #define USBHS_EPCR_TXD_MASK                      USB_ENDPTCTRL_TXD_MASK
95385 #define USBHS_EPCR_TXD_SHIFT                     USB_ENDPTCTRL_TXD_SHIFT
95386 #define USBHS_EPCR_TXD(x)                        USB_ENDPTCTRL_TXD(x)
95387 #define USBHS_EPCR_TXT_MASK                      USB_ENDPTCTRL_TXT_MASK
95388 #define USBHS_EPCR_TXT_SHIFT                     USB_ENDPTCTRL_TXT_SHIFT
95389 #define USBHS_EPCR_TXT(x)                        USB_ENDPTCTRL_TXT(x)
95390 #define USBHS_EPCR_TXI_MASK                      USB_ENDPTCTRL_TXI_MASK
95391 #define USBHS_EPCR_TXI_SHIFT                     USB_ENDPTCTRL_TXI_SHIFT
95392 #define USBHS_EPCR_TXI(x)                        USB_ENDPTCTRL_TXI(x)
95393 #define USBHS_EPCR_TXR_MASK                      USB_ENDPTCTRL_TXR_MASK
95394 #define USBHS_EPCR_TXR_SHIFT                     USB_ENDPTCTRL_TXR_SHIFT
95395 #define USBHS_EPCR_TXR(x)                        USB_ENDPTCTRL_TXR(x)
95396 #define USBHS_EPCR_TXE_MASK                      USB_ENDPTCTRL_TXE_MASK
95397 #define USBHS_EPCR_TXE_SHIFT                     USB_ENDPTCTRL_TXE_SHIFT
95398 #define USBHS_EPCR_TXE(x)                        USB_ENDPTCTRL_TXE(x)
95399 #define USBHS_EPCR_COUNT                         USB_ENDPTCTRL_COUNT
95400 #define USBHS_Type                               USB_Type
95401 #define USBHS_BASE_ADDRS                         { USB_OTG1_BASE, USB_OTG2_BASE }
95402 #define USBHS_IRQS                               { USB_OTG1_IRQn, USB_OTG2_IRQn }
95403 #define USBHS_IRQHandler                         USB_OTG1_IRQHandler
95404 
95405 
95406 /*!
95407  * @}
95408  */ /* end of group USB_Peripheral_Access_Layer */
95409 
95410 
95411 /* ----------------------------------------------------------------------------
95412    -- USBHSDCD Peripheral Access Layer
95413    ---------------------------------------------------------------------------- */
95414 
95415 /*!
95416  * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
95417  * @{
95418  */
95419 
95420 /** USBHSDCD - Register Layout Typedef */
95421 typedef struct {
95422   __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
95423   __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
95424   __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
95425   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
95426   __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
95427   __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
95428   union {                                          /* offset: 0x18 */
95429     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
95430     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
95431   };
95432 } USBHSDCD_Type;
95433 
95434 /* ----------------------------------------------------------------------------
95435    -- USBHSDCD Register Masks
95436    ---------------------------------------------------------------------------- */
95437 
95438 /*!
95439  * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
95440  * @{
95441  */
95442 
95443 /*! @name CONTROL - Control register */
95444 /*! @{ */
95445 
95446 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
95447 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
95448 /*! IACK - Interrupt Acknowledge
95449  *  0b0..Do not clear the interrupt.
95450  *  0b1..Clear the IF bit (interrupt flag).
95451  */
95452 #define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
95453 
95454 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
95455 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
95456 /*! IF - Interrupt Flag
95457  *  0b0..No interrupt is pending.
95458  *  0b1..An interrupt is pending.
95459  */
95460 #define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
95461 
95462 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
95463 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
95464 /*! IE - Interrupt Enable
95465  *  0b0..Disable interrupts to the system.
95466  *  0b1..Enable interrupts to the system.
95467  */
95468 #define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
95469 
95470 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
95471 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
95472 /*! BC12 - BC12
95473  *  0b0..Compatible with BC1.1 (default)
95474  *  0b1..Compatible with BC1.2
95475  */
95476 #define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
95477 
95478 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
95479 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
95480 /*! START - Start Change Detection Sequence
95481  *  0b0..Do not start the sequence. Writes of this value have no effect.
95482  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
95483  */
95484 #define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
95485 
95486 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
95487 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
95488 /*! SR - Software Reset
95489  *  0b0..Do not perform a software reset.
95490  *  0b1..Perform a software reset.
95491  */
95492 #define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
95493 /*! @} */
95494 
95495 /*! @name CLOCK - Clock register */
95496 /*! @{ */
95497 
95498 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
95499 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
95500 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
95501  *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
95502  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
95503  */
95504 #define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
95505 
95506 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
95507 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
95508 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
95509  */
95510 #define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
95511 /*! @} */
95512 
95513 /*! @name STATUS - Status register */
95514 /*! @{ */
95515 
95516 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
95517 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
95518 /*! SEQ_RES - Charger Detection Sequence Results
95519  *  0b00..No results to report.
95520  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
95521  *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
95522  *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
95523  *        detection has completed.)
95524  *  0b11..Attached to a DCP.
95525  */
95526 #define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
95527 
95528 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
95529 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
95530 /*! SEQ_STAT - Charger Detection Sequence Status
95531  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
95532  *  0b01..Data pin contact detection is complete.
95533  *  0b10..Charging port detection is complete.
95534  *  0b11..Charger type detection is complete.
95535  */
95536 #define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
95537 
95538 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
95539 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
95540 /*! ERR - Error Flag
95541  *  0b0..No sequence errors.
95542  *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
95543  */
95544 #define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
95545 
95546 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
95547 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
95548 /*! TO - Timeout Flag
95549  *  0b0..The detection sequence has not been running for over 1s.
95550  *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
95551  */
95552 #define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
95553 
95554 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
95555 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
95556 /*! ACTIVE - Active Status Indicator
95557  *  0b0..The sequence is not running.
95558  *  0b1..The sequence is running.
95559  */
95560 #define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
95561 /*! @} */
95562 
95563 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
95564 /*! @{ */
95565 
95566 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
95567 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
95568 /*! PS - Phase Selection
95569  *  0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
95570  *        unexpected conditions on USB_DP and USB_DM pins. (Default)
95571  *  0b01..Reserved, not for customer use.
95572  *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
95573  *  0b11..Reserved, not for customer use.
95574  */
95575 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
95576 /*! @} */
95577 
95578 /*! @name TIMER0 - TIMER0 register */
95579 /*! @{ */
95580 
95581 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
95582 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
95583 /*! TUNITCON - Unit Connection Timer Elapse (in ms)
95584  */
95585 #define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
95586 
95587 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
95588 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
95589 /*! TSEQ_INIT - Sequence Initiation Time
95590  *  0b0000000000-0b1111111111..0ms - 1023ms
95591  */
95592 #define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
95593 /*! @} */
95594 
95595 /*! @name TIMER1 - TIMER1 register */
95596 /*! @{ */
95597 
95598 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
95599 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
95600 /*! TVDPSRC_ON - Time Period Comparator Enabled
95601  *  0b0000000001-0b1111111111..1ms - 1023ms
95602  */
95603 #define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
95604 
95605 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
95606 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
95607 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
95608  *  0b0000000001-0b1111111111..1ms - 1023ms
95609  */
95610 #define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
95611 /*! @} */
95612 
95613 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
95614 /*! @{ */
95615 
95616 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
95617 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
95618 /*! CHECK_DM - Time Before Check of D- Line
95619  *  0b0001-0b1111..1ms - 15ms
95620  */
95621 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
95622 
95623 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
95624 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
95625 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
95626  *  0b0000000001-0b1111111111..1ms - 1023ms
95627  */
95628 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
95629 /*! @} */
95630 
95631 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
95632 /*! @{ */
95633 
95634 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
95635 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
95636 /*! TVDMSRC_ON - TVDMSRC_ON
95637  *  0b0000000000-0b0000101000..0ms - 40ms
95638  */
95639 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
95640 
95641 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
95642 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
95643 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
95644  *  0b0000000001-0b1111111111..1ms - 1023ms
95645  */
95646 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
95647 /*! @} */
95648 
95649 
95650 /*!
95651  * @}
95652  */ /* end of group USBHSDCD_Register_Masks */
95653 
95654 
95655 /* USBHSDCD - Peripheral instance base addresses */
95656 /** Peripheral USBHSDCD1 base address */
95657 #define USBHSDCD1_BASE                           (0x40434800u)
95658 /** Peripheral USBHSDCD1 base pointer */
95659 #define USBHSDCD1                                ((USBHSDCD_Type *)USBHSDCD1_BASE)
95660 /** Peripheral USBHSDCD2 base address */
95661 #define USBHSDCD2_BASE                           (0x40438800u)
95662 /** Peripheral USBHSDCD2 base pointer */
95663 #define USBHSDCD2                                ((USBHSDCD_Type *)USBHSDCD2_BASE)
95664 /** Array initializer of USBHSDCD peripheral base addresses */
95665 #define USBHSDCD_BASE_ADDRS                      { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
95666 /** Array initializer of USBHSDCD peripheral base pointers */
95667 #define USBHSDCD_BASE_PTRS                       { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
95668 
95669 /*!
95670  * @}
95671  */ /* end of group USBHSDCD_Peripheral_Access_Layer */
95672 
95673 
95674 /* ----------------------------------------------------------------------------
95675    -- USBNC Peripheral Access Layer
95676    ---------------------------------------------------------------------------- */
95677 
95678 /*!
95679  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
95680  * @{
95681  */
95682 
95683 /** USBNC - Register Layout Typedef */
95684 typedef struct {
95685   __IO uint32_t CTRL1;                             /**< USB OTG Control 1 Register, offset: 0x0 */
95686   __IO uint32_t CTRL2;                             /**< USB OTG Control 2 Register, offset: 0x4 */
95687        uint8_t RESERVED_0[8];
95688   __IO uint32_t HSIC_CTRL;                         /**< USB Host HSIC Control Register, offset: 0x10 */
95689 } USBNC_Type;
95690 
95691 /* ----------------------------------------------------------------------------
95692    -- USBNC Register Masks
95693    ---------------------------------------------------------------------------- */
95694 
95695 /*!
95696  * @addtogroup USBNC_Register_Masks USBNC Register Masks
95697  * @{
95698  */
95699 
95700 /*! @name CTRL1 - USB OTG Control 1 Register */
95701 /*! @{ */
95702 
95703 #define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
95704 #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
95705 /*! OVER_CUR_DIS - OVER_CUR_DIS
95706  *  0b1..Disables overcurrent detection
95707  *  0b0..Enables overcurrent detection
95708  */
95709 #define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
95710 
95711 #define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
95712 #define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
95713 /*! OVER_CUR_POL - OVER_CUR_POL
95714  *  0b1..Low active (low on this signal represents an overcurrent condition)
95715  *  0b0..High active (high on this signal represents an overcurrent condition)
95716  */
95717 #define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
95718 
95719 #define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
95720 #define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
95721 /*! PWR_POL - PWR_POL
95722  *  0b1..PMIC Power Pin is High active.
95723  *  0b0..PMIC Power Pin is Low active.
95724  */
95725 #define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
95726 
95727 #define USBNC_CTRL1_WIE_MASK                     (0x400U)
95728 #define USBNC_CTRL1_WIE_SHIFT                    (10U)
95729 /*! WIE - WIE
95730  *  0b1..Interrupt Enabled
95731  *  0b0..Interrupt Disabled
95732  */
95733 #define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
95734 
95735 #define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
95736 #define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
95737 /*! WKUP_SW_EN - WKUP_SW_EN
95738  *  0b1..Enable
95739  *  0b0..Disable
95740  */
95741 #define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
95742 
95743 #define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
95744 #define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
95745 /*! WKUP_SW - WKUP_SW
95746  *  0b1..Force wake-up
95747  *  0b0..Inactive
95748  */
95749 #define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
95750 
95751 #define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
95752 #define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
95753 /*! WKUP_ID_EN - WKUP_ID_EN
95754  *  0b1..Enable
95755  *  0b0..Disable
95756  */
95757 #define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
95758 
95759 #define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
95760 #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
95761 /*! WKUP_VBUS_EN - WKUP_VBUS_EN
95762  *  0b1..Enable
95763  *  0b0..Disable
95764  */
95765 #define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
95766 
95767 #define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
95768 #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
95769 /*! WKUP_DPDM_EN - Wake-up on DPDM change enable
95770  *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
95771  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
95772  */
95773 #define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
95774 
95775 #define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
95776 #define USBNC_CTRL1_WIR_SHIFT                    (31U)
95777 /*! WIR - WIR
95778  *  0b1..Wake-up Interrupt Request received
95779  *  0b0..No wake-up interrupt request received
95780  */
95781 #define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
95782 /*! @} */
95783 
95784 /*! @name CTRL2 - USB OTG Control 2 Register */
95785 /*! @{ */
95786 
95787 #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
95788 #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
95789 /*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL
95790  *  0b00..vbus_valid
95791  *  0b01..sess_valid
95792  *  0b10..sess_valid
95793  *  0b11..sess_valid
95794  */
95795 #define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
95796 
95797 #define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
95798 #define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
95799 /*! AUTURESUME_EN - Auto Resume Enable
95800  *  0b0..Default
95801  */
95802 #define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
95803 
95804 #define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
95805 #define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
95806 /*! LOWSPEED_EN - LOWSPEED_EN
95807  *  0b0..Default
95808  */
95809 #define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
95810 
95811 #define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
95812 #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
95813 /*! UTMI_CLK_VLD - UTMI_CLK_VLD
95814  *  0b0..Default
95815  */
95816 #define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
95817 /*! @} */
95818 
95819 /*! @name HSIC_CTRL - USB Host HSIC Control Register */
95820 /*! @{ */
95821 
95822 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK         (0x800U)
95823 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT        (11U)
95824 /*! HSIC_CLK_ON - HSIC_CLK_ON
95825  *  0b1..Active
95826  *  0b0..Inactive
95827  */
95828 #define USBNC_HSIC_CTRL_HSIC_CLK_ON(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
95829 
95830 #define USBNC_HSIC_CTRL_HSIC_EN_MASK             (0x1000U)
95831 #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT            (12U)
95832 /*! HSIC_EN - HSIC_EN
95833  *  0b1..Enabled
95834  *  0b0..Disabled
95835  */
95836 #define USBNC_HSIC_CTRL_HSIC_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
95837 
95838 #define USBNC_HSIC_CTRL_CLK_VLD_MASK             (0x80000000U)
95839 #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT            (31U)
95840 /*! CLK_VLD - CLK_VLD
95841  *  0b1..Valid
95842  *  0b0..Invalid
95843  */
95844 #define USBNC_HSIC_CTRL_CLK_VLD(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
95845 /*! @} */
95846 
95847 
95848 /*!
95849  * @}
95850  */ /* end of group USBNC_Register_Masks */
95851 
95852 
95853 /* USBNC - Peripheral instance base addresses */
95854 /** Peripheral USBNC_OTG1 base address */
95855 #define USBNC_OTG1_BASE                          (0x40430200u)
95856 /** Peripheral USBNC_OTG1 base pointer */
95857 #define USBNC_OTG1                               ((USBNC_Type *)USBNC_OTG1_BASE)
95858 /** Peripheral USBNC_OTG2 base address */
95859 #define USBNC_OTG2_BASE                          (0x4042C200u)
95860 /** Peripheral USBNC_OTG2 base pointer */
95861 #define USBNC_OTG2                               ((USBNC_Type *)USBNC_OTG2_BASE)
95862 /** Array initializer of USBNC peripheral base addresses */
95863 #define USBNC_BASE_ADDRS                         { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
95864 /** Array initializer of USBNC peripheral base pointers */
95865 #define USBNC_BASE_PTRS                          { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
95866 /* Backward compatibility */
95867 #define USB_OTGn_CTRL     CTRL1
95868 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK     USBNC_CTRL1_OVER_CUR_DIS_MASK
95869 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT     USBNC_CTRL1_OVER_CUR_DIS_SHIFT
95870 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)     USBNC_CTRL1_OVER_CUR_DIS(x)
95871 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK     USBNC_CTRL1_OVER_CUR_POL_MASK
95872 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT     USBNC_CTRL1_OVER_CUR_POL_SHIFT
95873 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)     USBNC_CTRL1_OVER_CUR_POL(x)
95874 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK     USBNC_CTRL1_PWR_POL_MASK
95875 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT     USBNC_CTRL1_PWR_POL_SHIFT
95876 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)     USBNC_CTRL1_PWR_POL(x)
95877 #define USBNC_USB_OTGn_CTRL_WIE_MASK     USBNC_CTRL1_WIE_MASK
95878 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT     USBNC_CTRL1_WIE_SHIFT
95879 #define USBNC_USB_OTGn_CTRL_WIE(x)     USBNC_CTRL1_WIE(x)
95880 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK     USBNC_CTRL1_WKUP_SW_EN_MASK
95881 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     USBNC_CTRL1_WKUP_SW_EN_SHIFT
95882 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)     USBNC_CTRL1_WKUP_SW_EN(x)
95883 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK     USBNC_CTRL1_WKUP_SW_MASK
95884 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT     USBNC_CTRL1_WKUP_SW_SHIFT
95885 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)     USBNC_CTRL1_WKUP_SW(x)
95886 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK     USBNC_CTRL1_WKUP_ID_EN_MASK
95887 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     USBNC_CTRL1_WKUP_ID_EN_SHIFT
95888 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)     USBNC_CTRL1_WKUP_ID_EN(x)
95889 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK     USBNC_CTRL1_WKUP_VBUS_EN_MASK
95890 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT     USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
95891 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)     USBNC_CTRL1_WKUP_VBUS_EN(x)
95892 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK     USBNC_CTRL1_WKUP_DPDM_EN_MASK
95893 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT     USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
95894 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)     USBNC_CTRL1_WKUP_DPDM_EN(x)
95895 #define USBNC_USB_OTGn_CTRL_WIR_MASK     USBNC_CTRL1_WIR_MASK
95896 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT     USBNC_CTRL1_WIR_SHIFT
95897 #define USBNC_USB_OTGn_CTRL_WIR(x)     USBNC_CTRL1_WIR(x)
95898 
95899 
95900 /*!
95901  * @}
95902  */ /* end of group USBNC_Peripheral_Access_Layer */
95903 
95904 
95905 /* ----------------------------------------------------------------------------
95906    -- USBPHY Peripheral Access Layer
95907    ---------------------------------------------------------------------------- */
95908 
95909 /*!
95910  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
95911  * @{
95912  */
95913 
95914 /** USBPHY - Register Layout Typedef */
95915 typedef struct {
95916   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
95917   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
95918   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
95919   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
95920   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
95921   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
95922   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
95923   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
95924   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
95925   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
95926   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
95927   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
95928   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
95929   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
95930   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
95931   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
95932   __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
95933        uint8_t RESERVED_0[12];
95934   __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50 */
95935   __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
95936   __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
95937   __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
95938   __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
95939        uint8_t RESERVED_1[12];
95940   __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
95941   __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
95942   __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
95943   __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
95944   __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
95945        uint8_t RESERVED_2[28];
95946   __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
95947   __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
95948   __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
95949   __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
95950        uint8_t RESERVED_3[16];
95951   __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
95952   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
95953   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
95954   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
95955   __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
95956        uint8_t RESERVED_4[12];
95957   __IO uint32_t USB1_CHRG_DETECT;                  /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
95958   __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
95959   __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
95960   __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USB PHY Charger Detect Control Register, offset: 0xEC */
95961   __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
95962        uint8_t RESERVED_5[12];
95963   __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
95964   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
95965   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
95966   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
95967   __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
95968   __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
95969   __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
95970   __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
95971   __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
95972   __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
95973   __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
95974   __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
95975   __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
95976   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
95977   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
95978   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
95979 } USBPHY_Type;
95980 
95981 /* ----------------------------------------------------------------------------
95982    -- USBPHY Register Masks
95983    ---------------------------------------------------------------------------- */
95984 
95985 /*!
95986  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
95987  * @{
95988  */
95989 
95990 /*! @name PWD - USB PHY Power-Down Register */
95991 /*! @{ */
95992 
95993 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
95994 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
95995 /*! TXPWDFS - TXPWDFS
95996  *  0b0..Normal operation.
95997  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
95998  */
95999 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
96000 
96001 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
96002 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
96003 /*! TXPWDIBIAS - TXPWDIBIAS
96004  *  0b0..Normal operation
96005  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
96006  *       is in suspend mode. This effectively powers down the entire USB transmit path
96007  */
96008 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
96009 
96010 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
96011 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
96012 /*! TXPWDV2I - TXPWDV2I
96013  *  0b0..Normal operation.
96014  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
96015  */
96016 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
96017 
96018 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
96019 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
96020 /*! RXPWDENV - RXPWDENV
96021  *  0b0..Normal operation.
96022  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
96023  */
96024 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
96025 
96026 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
96027 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
96028 /*! RXPWD1PT1 - RXPWD1PT1
96029  *  0b0..Normal operation
96030  *  0b1..Power-down the USB full-speed differential receiver.
96031  */
96032 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
96033 
96034 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
96035 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
96036 /*! RXPWDDIFF - RXPWDDIFF
96037  *  0b0..Normal operation.
96038  *  0b1..Power-down the USB high-speed differential receiver
96039  */
96040 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
96041 
96042 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
96043 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
96044 /*! RXPWDRX - RXPWDRX
96045  *  0b0..Normal operation
96046  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
96047  */
96048 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
96049 /*! @} */
96050 
96051 /*! @name PWD_SET - USB PHY Power-Down Register */
96052 /*! @{ */
96053 
96054 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
96055 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
96056 /*! TXPWDFS - TXPWDFS
96057  */
96058 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
96059 
96060 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
96061 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
96062 /*! TXPWDIBIAS - TXPWDIBIAS
96063  */
96064 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
96065 
96066 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
96067 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
96068 /*! TXPWDV2I - TXPWDV2I
96069  */
96070 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
96071 
96072 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
96073 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
96074 /*! RXPWDENV - RXPWDENV
96075  */
96076 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
96077 
96078 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
96079 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
96080 /*! RXPWD1PT1 - RXPWD1PT1
96081  */
96082 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
96083 
96084 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
96085 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
96086 /*! RXPWDDIFF - RXPWDDIFF
96087  */
96088 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
96089 
96090 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
96091 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
96092 /*! RXPWDRX - RXPWDRX
96093  */
96094 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
96095 /*! @} */
96096 
96097 /*! @name PWD_CLR - USB PHY Power-Down Register */
96098 /*! @{ */
96099 
96100 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
96101 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
96102 /*! TXPWDFS - TXPWDFS
96103  */
96104 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
96105 
96106 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
96107 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
96108 /*! TXPWDIBIAS - TXPWDIBIAS
96109  */
96110 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
96111 
96112 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
96113 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
96114 /*! TXPWDV2I - TXPWDV2I
96115  */
96116 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
96117 
96118 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
96119 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
96120 /*! RXPWDENV - RXPWDENV
96121  */
96122 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
96123 
96124 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
96125 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
96126 /*! RXPWD1PT1 - RXPWD1PT1
96127  */
96128 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
96129 
96130 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
96131 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
96132 /*! RXPWDDIFF - RXPWDDIFF
96133  */
96134 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
96135 
96136 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
96137 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
96138 /*! RXPWDRX - RXPWDRX
96139  */
96140 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
96141 /*! @} */
96142 
96143 /*! @name PWD_TOG - USB PHY Power-Down Register */
96144 /*! @{ */
96145 
96146 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
96147 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
96148 /*! TXPWDFS - TXPWDFS
96149  */
96150 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
96151 
96152 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
96153 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
96154 /*! TXPWDIBIAS - TXPWDIBIAS
96155  */
96156 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
96157 
96158 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
96159 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
96160 /*! TXPWDV2I - TXPWDV2I
96161  */
96162 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
96163 
96164 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
96165 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
96166 /*! RXPWDENV - RXPWDENV
96167  */
96168 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
96169 
96170 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
96171 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
96172 /*! RXPWD1PT1 - RXPWD1PT1
96173  */
96174 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
96175 
96176 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
96177 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
96178 /*! RXPWDDIFF - RXPWDDIFF
96179  */
96180 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
96181 
96182 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
96183 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
96184 /*! RXPWDRX - RXPWDRX
96185  */
96186 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
96187 /*! @} */
96188 
96189 /*! @name TX - USB PHY Transmitter Control Register */
96190 /*! @{ */
96191 
96192 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
96193 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
96194 /*! D_CAL - D_CAL
96195  *  0b0000..Maximum current, approximately 19% above nominal.
96196  *  0b0111..Nominal
96197  *  0b1111..Minimum current, approximately 19% below nominal.
96198  */
96199 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
96200 
96201 #define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
96202 #define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
96203 /*! TXCAL45DN - TXCAL45DN
96204  */
96205 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
96206 
96207 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
96208 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
96209 /*! TXCAL45DP - TXCAL45DP
96210  */
96211 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
96212 /*! @} */
96213 
96214 /*! @name TX_SET - USB PHY Transmitter Control Register */
96215 /*! @{ */
96216 
96217 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
96218 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
96219 /*! D_CAL - D_CAL
96220  */
96221 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
96222 
96223 #define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
96224 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
96225 /*! TXCAL45DN - TXCAL45DN
96226  */
96227 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
96228 
96229 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
96230 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
96231 /*! TXCAL45DP - TXCAL45DP
96232  */
96233 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
96234 /*! @} */
96235 
96236 /*! @name TX_CLR - USB PHY Transmitter Control Register */
96237 /*! @{ */
96238 
96239 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
96240 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
96241 /*! D_CAL - D_CAL
96242  */
96243 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
96244 
96245 #define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
96246 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
96247 /*! TXCAL45DN - TXCAL45DN
96248  */
96249 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
96250 
96251 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
96252 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
96253 /*! TXCAL45DP - TXCAL45DP
96254  */
96255 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
96256 /*! @} */
96257 
96258 /*! @name TX_TOG - USB PHY Transmitter Control Register */
96259 /*! @{ */
96260 
96261 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
96262 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
96263 /*! D_CAL - D_CAL
96264  */
96265 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
96266 
96267 #define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
96268 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
96269 /*! TXCAL45DN - TXCAL45DN
96270  */
96271 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
96272 
96273 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
96274 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
96275 /*! TXCAL45DP - TXCAL45DP
96276  */
96277 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
96278 /*! @} */
96279 
96280 /*! @name RX - USB PHY Receiver Control Register */
96281 /*! @{ */
96282 
96283 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
96284 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
96285 /*! ENVADJ - ENVADJ
96286  *  0b000..Trip-Level Voltage is 0.1000 V
96287  *  0b001..Trip-Level Voltage is 0.1125 V
96288  *  0b010..Trip-Level Voltage is 0.1250 V
96289  *  0b011..Trip-Level Voltage is 0.0875 V
96290  *  0b1xx..Reserved
96291  */
96292 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
96293 
96294 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
96295 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
96296 /*! DISCONADJ - DISCONADJ
96297  *  0b000..Trip-Level Voltage is 0.56875 V
96298  *  0b001..Trip-Level Voltage is 0.55000 V
96299  *  0b010..Trip-Level Voltage is 0.58125 V
96300  *  0b011..Trip-Level Voltage is 0.60000 V
96301  *  0b1xx..Reserved
96302  */
96303 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
96304 
96305 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
96306 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
96307 /*! RXDBYPASS - RXDBYPASS
96308  *  0b0..Normal operation.
96309  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
96310  */
96311 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
96312 /*! @} */
96313 
96314 /*! @name RX_SET - USB PHY Receiver Control Register */
96315 /*! @{ */
96316 
96317 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
96318 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
96319 /*! ENVADJ - ENVADJ
96320  */
96321 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
96322 
96323 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
96324 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
96325 /*! DISCONADJ - DISCONADJ
96326  */
96327 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
96328 
96329 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
96330 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
96331 /*! RXDBYPASS - RXDBYPASS
96332  */
96333 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
96334 /*! @} */
96335 
96336 /*! @name RX_CLR - USB PHY Receiver Control Register */
96337 /*! @{ */
96338 
96339 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
96340 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
96341 /*! ENVADJ - ENVADJ
96342  */
96343 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
96344 
96345 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
96346 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
96347 /*! DISCONADJ - DISCONADJ
96348  */
96349 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
96350 
96351 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
96352 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
96353 /*! RXDBYPASS - RXDBYPASS
96354  */
96355 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
96356 /*! @} */
96357 
96358 /*! @name RX_TOG - USB PHY Receiver Control Register */
96359 /*! @{ */
96360 
96361 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
96362 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
96363 /*! ENVADJ - ENVADJ
96364  */
96365 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
96366 
96367 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
96368 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
96369 /*! DISCONADJ - DISCONADJ
96370  */
96371 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
96372 
96373 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
96374 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
96375 /*! RXDBYPASS - RXDBYPASS
96376  */
96377 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
96378 /*! @} */
96379 
96380 /*! @name CTRL - USB PHY General Control Register */
96381 /*! @{ */
96382 
96383 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
96384 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
96385 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96386  */
96387 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
96388 
96389 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
96390 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
96391 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96392  */
96393 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
96394 
96395 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
96396 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
96397 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96398  */
96399 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
96400 
96401 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
96402 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
96403 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96404  */
96405 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
96406 
96407 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
96408 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
96409 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96410  *  0b0..Disables 200kohm pullup resistors on DP and DN pins
96411  *  0b1..Enables 200kohm pullup resistors on DP and DN pins
96412  */
96413 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
96414 
96415 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
96416 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
96417 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96418  */
96419 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
96420 
96421 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
96422 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
96423 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96424  */
96425 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
96426 
96427 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
96428 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
96429 /*! ENOTGIDDETECT - ENOTGIDDETECT
96430  */
96431 #define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
96432 
96433 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
96434 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
96435 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96436  */
96437 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
96438 
96439 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
96440 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
96441 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96442  */
96443 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
96444 
96445 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
96446 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
96447 /*! RESUME_IRQ - RESUME_IRQ
96448  */
96449 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
96450 
96451 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
96452 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
96453 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96454  */
96455 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
96456 
96457 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
96458 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
96459 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96460  */
96461 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
96462 
96463 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
96464 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
96465 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96466  */
96467 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
96468 
96469 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
96470 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
96471 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96472  */
96473 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
96474 
96475 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
96476 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
96477 /*! ENIRQWAKEUP - ENIRQWAKEUP
96478  */
96479 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
96480 
96481 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
96482 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
96483 /*! WAKEUP_IRQ - WAKEUP_IRQ
96484  */
96485 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
96486 
96487 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
96488 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
96489 /*! AUTORESUME_EN - AUTORESUME_EN
96490  */
96491 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
96492 
96493 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
96494 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
96495 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96496  */
96497 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
96498 
96499 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
96500 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
96501 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96502  */
96503 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
96504 
96505 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
96506 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
96507 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96508  */
96509 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
96510 
96511 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK            (0x400000U)
96512 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           (22U)
96513 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96514  */
96515 #define USBPHY_CTRL_ENIDCHG_WKUP(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
96516 
96517 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
96518 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
96519 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96520  */
96521 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
96522 
96523 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
96524 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
96525 /*! FSDLL_RST_EN - FSDLL_RST_EN
96526  */
96527 #define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
96528 
96529 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
96530 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
96531 /*! OTG_ID_VALUE - OTG_ID_VALUE
96532  */
96533 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
96534 
96535 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
96536 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
96537 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96538  */
96539 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
96540 
96541 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
96542 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
96543 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96544  */
96545 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
96546 
96547 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
96548 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
96549 /*! CLKGATE - CLKGATE
96550  */
96551 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
96552 
96553 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
96554 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
96555 /*! SFTRST - SFTRST
96556  */
96557 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
96558 /*! @} */
96559 
96560 /*! @name CTRL_SET - USB PHY General Control Register */
96561 /*! @{ */
96562 
96563 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96564 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96565 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96566  */
96567 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
96568 
96569 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
96570 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
96571 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96572  */
96573 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
96574 
96575 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
96576 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
96577 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96578  */
96579 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
96580 
96581 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96582 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96583 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96584  */
96585 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
96586 
96587 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
96588 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
96589 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96590  */
96591 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
96592 
96593 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
96594 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
96595 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96596  */
96597 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
96598 
96599 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
96600 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
96601 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96602  */
96603 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
96604 
96605 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
96606 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
96607 /*! ENOTGIDDETECT - ENOTGIDDETECT
96608  */
96609 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
96610 
96611 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
96612 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
96613 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96614  */
96615 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
96616 
96617 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
96618 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
96619 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96620  */
96621 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
96622 
96623 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
96624 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
96625 /*! RESUME_IRQ - RESUME_IRQ
96626  */
96627 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
96628 
96629 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
96630 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
96631 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96632  */
96633 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
96634 
96635 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
96636 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
96637 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96638  */
96639 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
96640 
96641 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
96642 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
96643 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96644  */
96645 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
96646 
96647 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
96648 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
96649 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96650  */
96651 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
96652 
96653 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
96654 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
96655 /*! ENIRQWAKEUP - ENIRQWAKEUP
96656  */
96657 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
96658 
96659 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
96660 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
96661 /*! WAKEUP_IRQ - WAKEUP_IRQ
96662  */
96663 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
96664 
96665 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
96666 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
96667 /*! AUTORESUME_EN - AUTORESUME_EN
96668  */
96669 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
96670 
96671 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
96672 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
96673 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96674  */
96675 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
96676 
96677 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
96678 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
96679 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96680  */
96681 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
96682 
96683 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
96684 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
96685 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96686  */
96687 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
96688 
96689 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        (0x400000U)
96690 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       (22U)
96691 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96692  */
96693 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
96694 
96695 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
96696 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
96697 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96698  */
96699 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
96700 
96701 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
96702 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
96703 /*! FSDLL_RST_EN - FSDLL_RST_EN
96704  */
96705 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
96706 
96707 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
96708 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
96709 /*! OTG_ID_VALUE - OTG_ID_VALUE
96710  */
96711 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
96712 
96713 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
96714 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
96715 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96716  */
96717 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
96718 
96719 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
96720 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
96721 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96722  */
96723 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
96724 
96725 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
96726 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
96727 /*! CLKGATE - CLKGATE
96728  */
96729 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
96730 
96731 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
96732 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
96733 /*! SFTRST - SFTRST
96734  */
96735 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
96736 /*! @} */
96737 
96738 /*! @name CTRL_CLR - USB PHY General Control Register */
96739 /*! @{ */
96740 
96741 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96742 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96743 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96744  */
96745 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
96746 
96747 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
96748 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
96749 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96750  */
96751 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
96752 
96753 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
96754 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
96755 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96756  */
96757 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
96758 
96759 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96760 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96761 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96762  */
96763 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
96764 
96765 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
96766 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
96767 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96768  */
96769 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
96770 
96771 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
96772 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
96773 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96774  */
96775 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
96776 
96777 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
96778 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
96779 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96780  */
96781 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
96782 
96783 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
96784 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
96785 /*! ENOTGIDDETECT - ENOTGIDDETECT
96786  */
96787 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
96788 
96789 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
96790 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
96791 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96792  */
96793 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
96794 
96795 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
96796 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
96797 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96798  */
96799 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
96800 
96801 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
96802 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
96803 /*! RESUME_IRQ - RESUME_IRQ
96804  */
96805 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
96806 
96807 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
96808 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
96809 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96810  */
96811 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
96812 
96813 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
96814 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
96815 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96816  */
96817 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
96818 
96819 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
96820 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
96821 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96822  */
96823 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
96824 
96825 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
96826 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
96827 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96828  */
96829 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
96830 
96831 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
96832 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
96833 /*! ENIRQWAKEUP - ENIRQWAKEUP
96834  */
96835 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
96836 
96837 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
96838 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
96839 /*! WAKEUP_IRQ - WAKEUP_IRQ
96840  */
96841 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
96842 
96843 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
96844 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
96845 /*! AUTORESUME_EN - AUTORESUME_EN
96846  */
96847 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
96848 
96849 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
96850 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
96851 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96852  */
96853 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
96854 
96855 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
96856 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
96857 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96858  */
96859 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
96860 
96861 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
96862 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
96863 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96864  */
96865 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
96866 
96867 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        (0x400000U)
96868 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       (22U)
96869 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96870  */
96871 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
96872 
96873 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
96874 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
96875 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96876  */
96877 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
96878 
96879 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
96880 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
96881 /*! FSDLL_RST_EN - FSDLL_RST_EN
96882  */
96883 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
96884 
96885 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
96886 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
96887 /*! OTG_ID_VALUE - OTG_ID_VALUE
96888  */
96889 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
96890 
96891 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
96892 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
96893 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96894  */
96895 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
96896 
96897 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
96898 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
96899 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96900  */
96901 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
96902 
96903 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
96904 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
96905 /*! CLKGATE - CLKGATE
96906  */
96907 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
96908 
96909 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
96910 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
96911 /*! SFTRST - SFTRST
96912  */
96913 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
96914 /*! @} */
96915 
96916 /*! @name CTRL_TOG - USB PHY General Control Register */
96917 /*! @{ */
96918 
96919 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96920 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96921 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96922  */
96923 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
96924 
96925 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
96926 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
96927 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96928  */
96929 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
96930 
96931 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
96932 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
96933 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96934  */
96935 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
96936 
96937 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96938 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96939 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96940  */
96941 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
96942 
96943 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
96944 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
96945 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96946  */
96947 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
96948 
96949 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
96950 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
96951 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96952  */
96953 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
96954 
96955 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
96956 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
96957 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96958  */
96959 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
96960 
96961 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
96962 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
96963 /*! ENOTGIDDETECT - ENOTGIDDETECT
96964  */
96965 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
96966 
96967 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
96968 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
96969 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96970  */
96971 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
96972 
96973 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
96974 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
96975 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96976  */
96977 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
96978 
96979 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
96980 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
96981 /*! RESUME_IRQ - RESUME_IRQ
96982  */
96983 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
96984 
96985 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
96986 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
96987 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96988  */
96989 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
96990 
96991 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
96992 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
96993 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96994  */
96995 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
96996 
96997 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
96998 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
96999 /*! ENUTMILEVEL2 - ENUTMILEVEL2
97000  */
97001 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
97002 
97003 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
97004 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
97005 /*! ENUTMILEVEL3 - ENUTMILEVEL3
97006  */
97007 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
97008 
97009 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
97010 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
97011 /*! ENIRQWAKEUP - ENIRQWAKEUP
97012  */
97013 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
97014 
97015 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
97016 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
97017 /*! WAKEUP_IRQ - WAKEUP_IRQ
97018  */
97019 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
97020 
97021 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
97022 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
97023 /*! AUTORESUME_EN - AUTORESUME_EN
97024  */
97025 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
97026 
97027 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
97028 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
97029 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
97030  */
97031 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
97032 
97033 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
97034 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
97035 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
97036  */
97037 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
97038 
97039 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
97040 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
97041 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
97042  */
97043 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
97044 
97045 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        (0x400000U)
97046 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       (22U)
97047 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
97048  */
97049 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
97050 
97051 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
97052 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
97053 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
97054  */
97055 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
97056 
97057 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
97058 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
97059 /*! FSDLL_RST_EN - FSDLL_RST_EN
97060  */
97061 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
97062 
97063 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
97064 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
97065 /*! OTG_ID_VALUE - OTG_ID_VALUE
97066  */
97067 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
97068 
97069 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
97070 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
97071 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
97072  */
97073 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
97074 
97075 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
97076 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
97077 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
97078  */
97079 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
97080 
97081 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
97082 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
97083 /*! CLKGATE - CLKGATE
97084  */
97085 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
97086 
97087 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
97088 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
97089 /*! SFTRST - SFTRST
97090  */
97091 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
97092 /*! @} */
97093 
97094 /*! @name STATUS - USB PHY Status Register */
97095 /*! @{ */
97096 
97097 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
97098 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
97099 /*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS
97100  *  0b0..USB cable disconnect has not been detected at the local host
97101  *  0b1..USB cable disconnect has been detected at the local host
97102  */
97103 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
97104 
97105 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
97106 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
97107 /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
97108  *  0b0..No attachment to a USB host is detected
97109  *  0b1..Cable attachment to a USB host is detected
97110  */
97111 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
97112 
97113 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
97114 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
97115 /*! OTGID_STATUS - OTGID_STATUS
97116  */
97117 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
97118 
97119 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
97120 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
97121 /*! RESUME_STATUS - RESUME_STATUS
97122  */
97123 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
97124 /*! @} */
97125 
97126 /*! @name DEBUG - USB PHY Debug Register */
97127 /*! @{ */
97128 
97129 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
97130 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
97131 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
97132  */
97133 #define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
97134 
97135 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
97136 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
97137 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
97138  */
97139 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
97140 
97141 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
97142 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
97143 /*! HSTPULLDOWN - HSTPULLDOWN
97144  */
97145 #define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
97146 
97147 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
97148 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
97149 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
97150  */
97151 #define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
97152 
97153 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
97154 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
97155 /*! TX2RXCOUNT - TX2RXCOUNT
97156  */
97157 #define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
97158 
97159 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
97160 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
97161 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
97162  */
97163 #define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
97164 
97165 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
97166 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
97167 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
97168  */
97169 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
97170 
97171 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
97172 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
97173 /*! ENSQUELCHRESET - ENSQUELCHRESET
97174  */
97175 #define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
97176 
97177 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
97178 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
97179 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
97180  */
97181 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
97182 
97183 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
97184 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
97185 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
97186  */
97187 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
97188 
97189 #define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
97190 #define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
97191 /*! CLKGATE - CLKGATE
97192  */
97193 #define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
97194 /*! @} */
97195 
97196 /*! @name DEBUG_SET - USB PHY Debug Register */
97197 /*! @{ */
97198 
97199 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
97200 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
97201 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
97202  */
97203 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
97204 
97205 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
97206 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
97207 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
97208  */
97209 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
97210 
97211 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
97212 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
97213 /*! HSTPULLDOWN - HSTPULLDOWN
97214  */
97215 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
97216 
97217 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
97218 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
97219 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
97220  */
97221 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
97222 
97223 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
97224 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
97225 /*! TX2RXCOUNT - TX2RXCOUNT
97226  */
97227 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
97228 
97229 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
97230 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
97231 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
97232  */
97233 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
97234 
97235 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
97236 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
97237 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
97238  */
97239 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
97240 
97241 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
97242 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
97243 /*! ENSQUELCHRESET - ENSQUELCHRESET
97244  */
97245 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
97246 
97247 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
97248 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
97249 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
97250  */
97251 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
97252 
97253 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
97254 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
97255 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
97256  */
97257 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
97258 
97259 #define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
97260 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
97261 /*! CLKGATE - CLKGATE
97262  */
97263 #define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
97264 /*! @} */
97265 
97266 /*! @name DEBUG_CLR - USB PHY Debug Register */
97267 /*! @{ */
97268 
97269 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
97270 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
97271 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
97272  */
97273 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
97274 
97275 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
97276 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
97277 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
97278  */
97279 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
97280 
97281 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
97282 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
97283 /*! HSTPULLDOWN - HSTPULLDOWN
97284  */
97285 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
97286 
97287 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
97288 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
97289 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
97290  */
97291 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
97292 
97293 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
97294 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
97295 /*! TX2RXCOUNT - TX2RXCOUNT
97296  */
97297 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
97298 
97299 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
97300 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
97301 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
97302  */
97303 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
97304 
97305 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
97306 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
97307 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
97308  */
97309 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
97310 
97311 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
97312 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
97313 /*! ENSQUELCHRESET - ENSQUELCHRESET
97314  */
97315 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
97316 
97317 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
97318 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
97319 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
97320  */
97321 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
97322 
97323 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
97324 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
97325 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
97326  */
97327 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
97328 
97329 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
97330 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
97331 /*! CLKGATE - CLKGATE
97332  */
97333 #define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
97334 /*! @} */
97335 
97336 /*! @name DEBUG_TOG - USB PHY Debug Register */
97337 /*! @{ */
97338 
97339 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
97340 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
97341 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
97342  */
97343 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
97344 
97345 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
97346 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
97347 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
97348  */
97349 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
97350 
97351 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
97352 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
97353 /*! HSTPULLDOWN - HSTPULLDOWN
97354  */
97355 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
97356 
97357 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
97358 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
97359 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
97360  */
97361 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
97362 
97363 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
97364 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
97365 /*! TX2RXCOUNT - TX2RXCOUNT
97366  */
97367 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
97368 
97369 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
97370 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
97371 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
97372  */
97373 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
97374 
97375 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
97376 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
97377 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
97378  */
97379 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
97380 
97381 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
97382 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
97383 /*! ENSQUELCHRESET - ENSQUELCHRESET
97384  */
97385 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
97386 
97387 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
97388 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
97389 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
97390  */
97391 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
97392 
97393 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
97394 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
97395 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
97396  */
97397 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
97398 
97399 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
97400 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
97401 /*! CLKGATE - CLKGATE
97402  */
97403 #define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
97404 /*! @} */
97405 
97406 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
97407 /*! @{ */
97408 
97409 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
97410 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
97411 /*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT
97412  */
97413 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
97414 
97415 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
97416 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
97417 /*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT
97418  */
97419 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
97420 
97421 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
97422 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
97423 /*! SQUELCH_COUNT - SQUELCH_COUNT
97424  */
97425 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
97426 /*! @} */
97427 
97428 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
97429 /*! @{ */
97430 
97431 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
97432 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
97433 /*! ENTAILADJVD - ENTAILADJVD
97434  *  0b00..Delay is nominal
97435  *  0b01..Delay is +20%
97436  *  0b10..Delay is -20%
97437  *  0b11..Delay is -40%
97438  */
97439 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
97440 
97441 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97442 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97443 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97444  */
97445 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)
97446 
97447 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97448 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97449 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97450  */
97451 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)
97452 
97453 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
97454 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT  (17U)
97455 /*! USB2_REFBIAS_LOWPWR - to be added
97456  */
97457 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)
97458 
97459 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
97460 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
97461 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97462  */
97463 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
97464 
97465 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
97466 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
97467 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97468  */
97469 #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
97470 /*! @} */
97471 
97472 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
97473 /*! @{ */
97474 
97475 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
97476 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
97477 /*! ENTAILADJVD - ENTAILADJVD
97478  */
97479 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
97480 
97481 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97482 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97483 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97484  */
97485 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)
97486 
97487 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97488 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97489 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97490  */
97491 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)
97492 
97493 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97494 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97495 /*! USB2_REFBIAS_LOWPWR - to be added
97496  */
97497 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)
97498 
97499 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97500 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97501 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97502  */
97503 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
97504 
97505 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
97506 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
97507 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97508  */
97509 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
97510 /*! @} */
97511 
97512 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
97513 /*! @{ */
97514 
97515 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
97516 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
97517 /*! ENTAILADJVD - ENTAILADJVD
97518  */
97519 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
97520 
97521 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97522 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97523 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97524  */
97525 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)
97526 
97527 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97528 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97529 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97530  */
97531 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)
97532 
97533 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97534 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97535 /*! USB2_REFBIAS_LOWPWR - to be added
97536  */
97537 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)
97538 
97539 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97540 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97541 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97542  */
97543 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
97544 
97545 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
97546 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
97547 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97548  */
97549 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
97550 /*! @} */
97551 
97552 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
97553 /*! @{ */
97554 
97555 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
97556 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
97557 /*! ENTAILADJVD - ENTAILADJVD
97558  */
97559 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
97560 
97561 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97562 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97563 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97564  */
97565 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)
97566 
97567 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97568 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97569 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97570  */
97571 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)
97572 
97573 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97574 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97575 /*! USB2_REFBIAS_LOWPWR - to be added
97576  */
97577 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)
97578 
97579 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97580 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97581 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97582  */
97583 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
97584 
97585 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
97586 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
97587 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97588  */
97589 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
97590 /*! @} */
97591 
97592 /*! @name VERSION - UTMI RTL Version */
97593 /*! @{ */
97594 
97595 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
97596 #define USBPHY_VERSION_STEP_SHIFT                (0U)
97597 /*! STEP - STEP
97598  */
97599 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
97600 
97601 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
97602 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
97603 /*! MINOR - MINOR
97604  */
97605 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
97606 
97607 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
97608 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
97609 /*! MAJOR - MAJOR
97610  */
97611 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
97612 /*! @} */
97613 
97614 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
97615 /*! @{ */
97616 
97617 #define USBPHY_PLL_SIC_PLL_POSTDIV_MASK          (0x1CU)
97618 #define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT         (2U)
97619 /*! PLL_POSTDIV - PLL_POSTDIV
97620  */
97621 #define USBPHY_PLL_SIC_PLL_POSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
97622 
97623 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
97624 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
97625 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97626  */
97627 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
97628 
97629 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
97630 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
97631 /*! PLL_POWER - PLL_POWER
97632  */
97633 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
97634 
97635 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
97636 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
97637 /*! PLL_ENABLE - PLL_ENABLE
97638  */
97639 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
97640 
97641 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
97642 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
97643 /*! PLL_BYPASS - PLL_BYPASS
97644  */
97645 #define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
97646 
97647 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
97648 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
97649 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97650  *  0b0..Selects PLL_POWER to control the reference bias
97651  *  0b1..Selects REFBIAS_PWD to control the reference bias.
97652  */
97653 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
97654 
97655 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
97656 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
97657 /*! REFBIAS_PWD - Power down the reference bias
97658  */
97659 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
97660 
97661 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
97662 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
97663 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97664  */
97665 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
97666 
97667 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
97668 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
97669 /*! PLL_DIV_SEL - PLL_DIV_SEL
97670  *  0b000..Divide by 13
97671  *  0b001..Divide by 15
97672  *  0b010..Divide by 16
97673  *  0b011..Divide by 20
97674  *  0b100..Divide by 22
97675  *  0b101..Divide by 25
97676  *  0b110..Divide by 30
97677  *  0b111..Divide by 240
97678  */
97679 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
97680 
97681 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
97682 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
97683 /*! PLL_LOCK - PLL_LOCK
97684  *  0b0..PLL is not currently locked
97685  *  0b1..PLL is currently locked
97686  */
97687 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
97688 /*! @} */
97689 
97690 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
97691 /*! @{ */
97692 
97693 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK      (0x1CU)
97694 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT     (2U)
97695 /*! PLL_POSTDIV - PLL_POSTDIV
97696  */
97697 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)
97698 
97699 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
97700 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
97701 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97702  */
97703 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
97704 
97705 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
97706 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
97707 /*! PLL_POWER - PLL_POWER
97708  */
97709 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
97710 
97711 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
97712 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
97713 /*! PLL_ENABLE - PLL_ENABLE
97714  */
97715 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
97716 
97717 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
97718 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
97719 /*! PLL_BYPASS - PLL_BYPASS
97720  */
97721 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
97722 
97723 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
97724 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
97725 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97726  */
97727 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
97728 
97729 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
97730 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
97731 /*! REFBIAS_PWD - Power down the reference bias
97732  */
97733 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
97734 
97735 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
97736 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
97737 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97738  */
97739 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
97740 
97741 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
97742 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
97743 /*! PLL_DIV_SEL - PLL_DIV_SEL
97744  */
97745 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
97746 
97747 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
97748 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
97749 /*! PLL_LOCK - PLL_LOCK
97750  */
97751 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
97752 /*! @} */
97753 
97754 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
97755 /*! @{ */
97756 
97757 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK      (0x1CU)
97758 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT     (2U)
97759 /*! PLL_POSTDIV - PLL_POSTDIV
97760  */
97761 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)
97762 
97763 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
97764 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
97765 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97766  */
97767 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
97768 
97769 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
97770 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
97771 /*! PLL_POWER - PLL_POWER
97772  */
97773 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
97774 
97775 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
97776 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
97777 /*! PLL_ENABLE - PLL_ENABLE
97778  */
97779 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
97780 
97781 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
97782 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
97783 /*! PLL_BYPASS - PLL_BYPASS
97784  */
97785 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
97786 
97787 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
97788 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
97789 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97790  */
97791 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
97792 
97793 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
97794 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
97795 /*! REFBIAS_PWD - Power down the reference bias
97796  */
97797 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
97798 
97799 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
97800 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
97801 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97802  */
97803 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
97804 
97805 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
97806 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
97807 /*! PLL_DIV_SEL - PLL_DIV_SEL
97808  */
97809 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
97810 
97811 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
97812 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
97813 /*! PLL_LOCK - PLL_LOCK
97814  */
97815 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
97816 /*! @} */
97817 
97818 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
97819 /*! @{ */
97820 
97821 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK      (0x1CU)
97822 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT     (2U)
97823 /*! PLL_POSTDIV - PLL_POSTDIV
97824  */
97825 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)
97826 
97827 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
97828 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
97829 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97830  */
97831 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
97832 
97833 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
97834 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
97835 /*! PLL_POWER - PLL_POWER
97836  */
97837 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
97838 
97839 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
97840 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
97841 /*! PLL_ENABLE - PLL_ENABLE
97842  */
97843 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
97844 
97845 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
97846 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
97847 /*! PLL_BYPASS - PLL_BYPASS
97848  */
97849 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
97850 
97851 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
97852 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
97853 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97854  */
97855 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
97856 
97857 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
97858 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
97859 /*! REFBIAS_PWD - Power down the reference bias
97860  */
97861 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
97862 
97863 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
97864 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
97865 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97866  */
97867 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
97868 
97869 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
97870 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
97871 /*! PLL_DIV_SEL - PLL_DIV_SEL
97872  */
97873 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
97874 
97875 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
97876 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
97877 /*! PLL_LOCK - PLL_LOCK
97878  */
97879 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
97880 /*! @} */
97881 
97882 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
97883 /*! @{ */
97884 
97885 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
97886 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
97887 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
97888  *  0b000..4.0 V
97889  *  0b001..4.1 V
97890  *  0b010..4.2 V
97891  *  0b011..4.3 V
97892  *  0b100..4.4 V (Default)
97893  *  0b101..4.5 V
97894  *  0b110..4.6 V
97895  *  0b111..4.7 V
97896  */
97897 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
97898 
97899 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
97900 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
97901 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
97902  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
97903  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
97904  */
97905 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
97906 
97907 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
97908 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
97909 /*! SESSEND_OVERRIDE - Override value for SESSEND
97910  */
97911 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
97912 
97913 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
97914 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
97915 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
97916  */
97917 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
97918 
97919 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
97920 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
97921 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
97922  */
97923 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
97924 
97925 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
97926 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
97927 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
97928  */
97929 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
97930 
97931 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
97932 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
97933 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97934  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
97935  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
97936  */
97937 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
97938 
97939 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
97940 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
97941 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97942  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
97943  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
97944  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
97945  *  0b11..Reserved, do not use
97946  */
97947 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
97948 
97949 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
97950 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
97951 /*! ID_OVERRIDE_EN - TBA
97952  */
97953 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
97954 
97955 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
97956 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
97957 /*! ID_OVERRIDE - TBA
97958  */
97959 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
97960 
97961 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
97962 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
97963 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
97964  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
97965  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
97966  */
97967 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
97968 
97969 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
97970 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
97971 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
97972  *  0b000..Powers down the VBUS_VALID comparator
97973  *  0b001..Enables the SESS_VALID comparator (default)
97974  *  0b010..Enables the 3Vdetect (default)
97975  */
97976 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
97977 
97978 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
97979 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
97980 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
97981  *  0b0..VBUS discharge resistor is disabled (Default)
97982  *  0b1..VBUS discharge resistor is enabled
97983  */
97984 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
97985 
97986 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
97987 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
97988 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
97989  *  0b0..Disable resistive charger detection resistors on DP and DP
97990  *  0b1..Enable resistive charger detection resistors on DP and DP
97991  */
97992 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
97993 /*! @} */
97994 
97995 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
97996 /*! @{ */
97997 
97998 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
97999 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
98000 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
98001  */
98002 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
98003 
98004 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
98005 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
98006 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
98007  */
98008 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
98009 
98010 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
98011 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
98012 /*! SESSEND_OVERRIDE - Override value for SESSEND
98013  */
98014 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
98015 
98016 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
98017 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
98018 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
98019  */
98020 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
98021 
98022 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
98023 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
98024 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
98025  */
98026 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
98027 
98028 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
98029 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
98030 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
98031  */
98032 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
98033 
98034 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
98035 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
98036 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98037  */
98038 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
98039 
98040 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
98041 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
98042 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98043  */
98044 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
98045 
98046 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
98047 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
98048 /*! ID_OVERRIDE_EN - TBA
98049  */
98050 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
98051 
98052 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
98053 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
98054 /*! ID_OVERRIDE - TBA
98055  */
98056 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
98057 
98058 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
98059 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
98060 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
98061  */
98062 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
98063 
98064 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
98065 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
98066 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
98067  */
98068 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
98069 
98070 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
98071 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
98072 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
98073  */
98074 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
98075 
98076 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
98077 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
98078 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
98079  */
98080 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
98081 /*! @} */
98082 
98083 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
98084 /*! @{ */
98085 
98086 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
98087 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
98088 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
98089  */
98090 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
98091 
98092 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
98093 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
98094 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
98095  */
98096 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
98097 
98098 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
98099 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
98100 /*! SESSEND_OVERRIDE - Override value for SESSEND
98101  */
98102 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
98103 
98104 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
98105 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
98106 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
98107  */
98108 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
98109 
98110 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
98111 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
98112 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
98113  */
98114 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
98115 
98116 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
98117 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
98118 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
98119  */
98120 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
98121 
98122 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
98123 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
98124 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98125  */
98126 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
98127 
98128 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
98129 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
98130 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98131  */
98132 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
98133 
98134 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
98135 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
98136 /*! ID_OVERRIDE_EN - TBA
98137  */
98138 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
98139 
98140 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
98141 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
98142 /*! ID_OVERRIDE - TBA
98143  */
98144 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
98145 
98146 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
98147 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
98148 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
98149  */
98150 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
98151 
98152 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
98153 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
98154 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
98155  */
98156 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
98157 
98158 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
98159 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
98160 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
98161  */
98162 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
98163 
98164 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
98165 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
98166 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
98167  */
98168 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
98169 /*! @} */
98170 
98171 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
98172 /*! @{ */
98173 
98174 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
98175 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
98176 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
98177  */
98178 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
98179 
98180 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
98181 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
98182 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
98183  */
98184 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
98185 
98186 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
98187 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
98188 /*! SESSEND_OVERRIDE - Override value for SESSEND
98189  */
98190 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
98191 
98192 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
98193 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
98194 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
98195  */
98196 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
98197 
98198 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
98199 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
98200 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
98201  */
98202 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
98203 
98204 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
98205 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
98206 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
98207  */
98208 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
98209 
98210 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
98211 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
98212 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98213  */
98214 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
98215 
98216 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
98217 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
98218 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
98219  */
98220 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
98221 
98222 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
98223 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
98224 /*! ID_OVERRIDE_EN - TBA
98225  */
98226 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
98227 
98228 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
98229 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
98230 /*! ID_OVERRIDE - TBA
98231  */
98232 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
98233 
98234 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
98235 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
98236 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
98237  */
98238 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
98239 
98240 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
98241 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
98242 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
98243  */
98244 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
98245 
98246 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
98247 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
98248 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
98249  */
98250 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
98251 
98252 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
98253 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
98254 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
98255  */
98256 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
98257 /*! @} */
98258 
98259 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
98260 /*! @{ */
98261 
98262 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
98263 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
98264 /*! SESSEND - Session End indicator
98265  *  0b0..The VBUS voltage is above the Session Valid threshold
98266  *  0b1..The VBUS voltage is below the Session Valid threshold
98267  */
98268 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
98269 
98270 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
98271 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
98272 /*! BVALID - B-Device Session Valid status
98273  *  0b0..The VBUS voltage is below the Session Valid threshold
98274  *  0b1..The VBUS voltage is above the Session Valid threshold
98275  */
98276 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
98277 
98278 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
98279 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
98280 /*! AVALID - A-Device Session Valid status
98281  *  0b0..The VBUS voltage is below the Session Valid threshold
98282  *  0b1..The VBUS voltage is above the Session Valid threshold
98283  */
98284 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
98285 
98286 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
98287 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
98288 /*! VBUS_VALID - VBUS voltage status
98289  *  0b0..VBUS is below the comparator threshold
98290  *  0b1..VBUS is above the comparator threshold
98291  */
98292 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
98293 
98294 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
98295 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
98296 /*! VBUS_VALID_3V - VBUS_VALID_3V detector status
98297  *  0b0..VBUS voltage is below VBUS_VALID_3V threshold
98298  *  0b1..VBUS voltage is above VBUS_VALID_3V threshold
98299  */
98300 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
98301 /*! @} */
98302 
98303 /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
98304 /*! @{ */
98305 
98306 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
98307 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
98308 /*! PULLUP_DP - PULLUP_DP
98309  */
98310 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
98311 
98312 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK    (0x800000U)
98313 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT   (23U)
98314 /*! BGR_BIAS - BGR_BIAS
98315  *  0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default)
98316  *  0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference
98317  */
98318 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)
98319 /*! @} */
98320 
98321 /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
98322 /*! @{ */
98323 
98324 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
98325 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
98326 /*! PULLUP_DP - PULLUP_DP
98327  */
98328 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
98329 
98330 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
98331 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
98332 /*! BGR_BIAS - BGR_BIAS
98333  */
98334 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)
98335 /*! @} */
98336 
98337 /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
98338 /*! @{ */
98339 
98340 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
98341 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
98342 /*! PULLUP_DP - PULLUP_DP
98343  */
98344 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
98345 
98346 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
98347 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
98348 /*! BGR_BIAS - BGR_BIAS
98349  */
98350 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)
98351 /*! @} */
98352 
98353 /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
98354 /*! @{ */
98355 
98356 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
98357 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
98358 /*! PULLUP_DP - PULLUP_DP
98359  */
98360 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
98361 
98362 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
98363 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
98364 /*! BGR_BIAS - BGR_BIAS
98365  */
98366 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)
98367 /*! @} */
98368 
98369 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
98370 /*! @{ */
98371 
98372 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
98373 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
98374 /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
98375  *  0b0..No USB cable attachment has been detected
98376  *  0b1..A USB cable attachment between the device and host has been detected
98377  */
98378 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
98379 
98380 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
98381 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
98382 /*! CHRG_DETECTED - Battery Charging Primary Detection phase output
98383  *  0b0..Standard Downstream Port (SDP) has been detected
98384  *  0b1..Charging Port has been detected
98385  */
98386 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
98387 
98388 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK  (0x4U)
98389 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
98390 /*! DN_STATE - DN_STATE
98391  *  0b0..DN pin voltage is < 0.8V
98392  *  0b1..DN pin voltage is > 2.0V
98393  */
98394 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)
98395 
98396 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
98397 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
98398 /*! DP_STATE - DP_STATE
98399  *  0b0..DP pin voltage is < 0.8V
98400  *  0b1..DP pin voltage is > 2.0V
98401  */
98402 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
98403 
98404 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
98405 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
98406 /*! SECDET_DCP - Battery Charging Secondary Detection phase output
98407  *  0b0..Charging Downstream Port (CDP) has been detected
98408  *  0b1..Downstream Charging Port (DCP) has been detected
98409  */
98410 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
98411 /*! @} */
98412 
98413 /*! @name ANACTRL - USB PHY Analog Control Register */
98414 /*! @{ */
98415 
98416 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
98417 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
98418 /*! DEV_PULLDOWN - DEV_PULLDOWN
98419  *  0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode.
98420  *  0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode.
98421  */
98422 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
98423 /*! @} */
98424 
98425 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
98426 /*! @{ */
98427 
98428 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
98429 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
98430 /*! DEV_PULLDOWN - DEV_PULLDOWN
98431  */
98432 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
98433 /*! @} */
98434 
98435 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
98436 /*! @{ */
98437 
98438 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
98439 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
98440 /*! DEV_PULLDOWN - DEV_PULLDOWN
98441  */
98442 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
98443 /*! @} */
98444 
98445 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
98446 /*! @{ */
98447 
98448 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
98449 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
98450 /*! DEV_PULLDOWN - DEV_PULLDOWN
98451  */
98452 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
98453 /*! @} */
98454 
98455 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
98456 /*! @{ */
98457 
98458 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
98459 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
98460 /*! UTMI_TESTSTART - UTMI_TESTSTART
98461  */
98462 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
98463 
98464 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
98465 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
98466 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98467  */
98468 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
98469 
98470 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
98471 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
98472 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98473  */
98474 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
98475 
98476 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
98477 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
98478 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98479  */
98480 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
98481 
98482 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
98483 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
98484 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98485  */
98486 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
98487 
98488 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
98489 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
98490 /*! TSTI_TX_EN - TSTI_TX_EN
98491  */
98492 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
98493 
98494 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
98495 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
98496 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98497  */
98498 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
98499 
98500 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
98501 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
98502 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98503  */
98504 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
98505 
98506 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
98507 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
98508 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98509  */
98510 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
98511 
98512 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98513 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
98514 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98515  */
98516 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
98517 
98518 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
98519 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
98520 /*! TSTPKT - TSTPKT
98521  */
98522 #define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
98523 /*! @} */
98524 
98525 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
98526 /*! @{ */
98527 
98528 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
98529 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
98530 /*! UTMI_TESTSTART - UTMI_TESTSTART
98531  */
98532 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
98533 
98534 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
98535 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
98536 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98537  */
98538 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
98539 
98540 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
98541 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
98542 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98543  */
98544 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
98545 
98546 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
98547 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
98548 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98549  */
98550 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
98551 
98552 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
98553 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
98554 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98555  */
98556 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
98557 
98558 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
98559 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
98560 /*! TSTI_TX_EN - TSTI_TX_EN
98561  */
98562 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
98563 
98564 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
98565 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
98566 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98567  */
98568 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
98569 
98570 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
98571 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
98572 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98573  */
98574 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
98575 
98576 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
98577 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
98578 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98579  */
98580 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
98581 
98582 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98583 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
98584 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98585  */
98586 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
98587 
98588 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
98589 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
98590 /*! TSTPKT - TSTPKT
98591  */
98592 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
98593 /*! @} */
98594 
98595 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
98596 /*! @{ */
98597 
98598 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
98599 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
98600 /*! UTMI_TESTSTART - UTMI_TESTSTART
98601  */
98602 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
98603 
98604 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
98605 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
98606 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98607  */
98608 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
98609 
98610 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
98611 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
98612 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98613  */
98614 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
98615 
98616 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
98617 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
98618 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98619  */
98620 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
98621 
98622 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
98623 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
98624 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98625  */
98626 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
98627 
98628 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
98629 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
98630 /*! TSTI_TX_EN - TSTI_TX_EN
98631  */
98632 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
98633 
98634 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
98635 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
98636 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98637  */
98638 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
98639 
98640 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
98641 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
98642 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98643  */
98644 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
98645 
98646 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
98647 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
98648 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98649  */
98650 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
98651 
98652 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98653 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
98654 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98655  */
98656 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
98657 
98658 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
98659 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
98660 /*! TSTPKT - TSTPKT
98661  */
98662 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
98663 /*! @} */
98664 
98665 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
98666 /*! @{ */
98667 
98668 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
98669 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
98670 /*! UTMI_TESTSTART - UTMI_TESTSTART
98671  */
98672 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
98673 
98674 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
98675 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
98676 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98677  */
98678 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
98679 
98680 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
98681 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
98682 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98683  */
98684 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
98685 
98686 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
98687 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
98688 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98689  */
98690 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
98691 
98692 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
98693 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
98694 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98695  */
98696 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
98697 
98698 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
98699 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
98700 /*! TSTI_TX_EN - TSTI_TX_EN
98701  */
98702 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
98703 
98704 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
98705 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
98706 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98707  */
98708 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
98709 
98710 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
98711 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
98712 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98713  */
98714 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
98715 
98716 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
98717 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
98718 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98719  */
98720 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
98721 
98722 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98723 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
98724 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98725  */
98726 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
98727 
98728 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
98729 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
98730 /*! TSTPKT - TSTPKT
98731  */
98732 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
98733 /*! @} */
98734 
98735 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
98736 /*! @{ */
98737 
98738 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
98739 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
98740 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98741  */
98742 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
98743 
98744 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98745 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
98746 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98747  */
98748 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
98749 /*! @} */
98750 
98751 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
98752 /*! @{ */
98753 
98754 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
98755 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
98756 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98757  */
98758 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
98759 
98760 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98761 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
98762 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98763  */
98764 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
98765 /*! @} */
98766 
98767 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
98768 /*! @{ */
98769 
98770 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
98771 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
98772 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98773  */
98774 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
98775 
98776 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98777 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
98778 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98779  */
98780 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
98781 /*! @} */
98782 
98783 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
98784 /*! @{ */
98785 
98786 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
98787 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
98788 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98789  */
98790 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
98791 
98792 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98793 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
98794 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98795  */
98796 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
98797 /*! @} */
98798 
98799 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
98800 /*! @{ */
98801 
98802 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98803 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98804 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98805  */
98806 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
98807 
98808 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98809 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98810 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98811  */
98812 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98813 
98814 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98815 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98816 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98817  */
98818 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
98819 
98820 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98821 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98822 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98823  */
98824 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98825 
98826 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98827 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98828 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98829  */
98830 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98831 
98832 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98833 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98834 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98835  */
98836 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98837 
98838 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98839 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98840 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98841  */
98842 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98843 
98844 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98845 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98846 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98847  */
98848 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98849 
98850 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98851 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98852 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98853  */
98854 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
98855 
98856 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98857 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98858 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98859  */
98860 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98861 
98862 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98863 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98864 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98865  */
98866 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98867 
98868 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98869 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98870 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98871  */
98872 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
98873 
98874 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98875 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98876 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98877  */
98878 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
98879 
98880 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98881 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98882 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98883  */
98884 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
98885 /*! @} */
98886 
98887 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
98888 /*! @{ */
98889 
98890 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98891 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98892 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98893  */
98894 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
98895 
98896 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98897 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98898 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98899  */
98900 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98901 
98902 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98903 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98904 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98905  */
98906 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
98907 
98908 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98909 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98910 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98911  */
98912 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98913 
98914 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98915 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98916 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98917  */
98918 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98919 
98920 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98921 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98922 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98923  */
98924 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98925 
98926 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98927 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98928 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98929  */
98930 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98931 
98932 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98933 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98934 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98935  */
98936 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98937 
98938 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98939 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98940 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98941  */
98942 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
98943 
98944 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98945 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98946 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98947  */
98948 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98949 
98950 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98951 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98952 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98953  */
98954 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98955 
98956 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98957 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98958 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98959  */
98960 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
98961 
98962 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98963 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98964 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98965  */
98966 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
98967 
98968 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98969 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98970 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98971  */
98972 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
98973 /*! @} */
98974 
98975 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
98976 /*! @{ */
98977 
98978 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98979 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98980 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98981  */
98982 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
98983 
98984 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98985 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98986 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98987  */
98988 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98989 
98990 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98991 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98992 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98993  */
98994 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
98995 
98996 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98997 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98998 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98999  */
99000 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
99001 
99002 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
99003 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
99004 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
99005  */
99006 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)
99007 
99008 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
99009 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
99010 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
99011  */
99012 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
99013 
99014 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
99015 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
99016 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
99017  */
99018 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
99019 
99020 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
99021 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
99022 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
99023  */
99024 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
99025 
99026 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
99027 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
99028 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
99029  */
99030 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
99031 
99032 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
99033 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
99034 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
99035  */
99036 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
99037 
99038 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
99039 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
99040 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
99041  */
99042 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
99043 
99044 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
99045 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
99046 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
99047  */
99048 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
99049 
99050 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
99051 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
99052 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
99053  */
99054 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
99055 
99056 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
99057 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
99058 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
99059  */
99060 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
99061 /*! @} */
99062 
99063 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
99064 /*! @{ */
99065 
99066 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
99067 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
99068 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
99069  */
99070 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
99071 
99072 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
99073 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
99074 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
99075  */
99076 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
99077 
99078 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
99079 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
99080 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
99081  */
99082 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
99083 
99084 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
99085 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
99086 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
99087  */
99088 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
99089 
99090 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
99091 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
99092 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
99093  */
99094 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)
99095 
99096 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
99097 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
99098 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
99099  */
99100 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
99101 
99102 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
99103 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
99104 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
99105  */
99106 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
99107 
99108 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
99109 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
99110 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
99111  */
99112 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
99113 
99114 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
99115 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
99116 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
99117  */
99118 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
99119 
99120 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
99121 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
99122 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
99123  */
99124 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
99125 
99126 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
99127 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
99128 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
99129  */
99130 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
99131 
99132 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
99133 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
99134 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
99135  */
99136 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
99137 
99138 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
99139 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
99140 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
99141  */
99142 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
99143 
99144 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
99145 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
99146 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
99147  */
99148 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
99149 /*! @} */
99150 
99151 
99152 /*!
99153  * @}
99154  */ /* end of group USBPHY_Register_Masks */
99155 
99156 
99157 /* USBPHY - Peripheral instance base addresses */
99158 /** Peripheral USBPHY1 base address */
99159 #define USBPHY1_BASE                             (0x40434000u)
99160 /** Peripheral USBPHY1 base pointer */
99161 #define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
99162 /** Peripheral USBPHY2 base address */
99163 #define USBPHY2_BASE                             (0x40438000u)
99164 /** Peripheral USBPHY2 base pointer */
99165 #define USBPHY2                                  ((USBPHY_Type *)USBPHY2_BASE)
99166 /** Array initializer of USBPHY peripheral base addresses */
99167 #define USBPHY_BASE_ADDRS                        { 0u, USBPHY1_BASE, USBPHY2_BASE }
99168 /** Array initializer of USBPHY peripheral base pointers */
99169 #define USBPHY_BASE_PTRS                         { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
99170 /** Interrupt vectors for the USBPHY peripheral type */
99171 #define USBPHY_IRQS                              { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
99172 /* Backward compatibility */
99173 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
99174 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
99175 #define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
99176 #define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
99177 #define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
99178 #define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)
99179 
99180 
99181 /*!
99182  * @}
99183  */ /* end of group USBPHY_Peripheral_Access_Layer */
99184 
99185 
99186 /* ----------------------------------------------------------------------------
99187    -- USDHC Peripheral Access Layer
99188    ---------------------------------------------------------------------------- */
99189 
99190 /*!
99191  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
99192  * @{
99193  */
99194 
99195 /** USDHC - Register Layout Typedef */
99196 typedef struct {
99197   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
99198   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
99199   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
99200   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
99201   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
99202   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
99203   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
99204   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
99205   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
99206   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
99207   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
99208   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
99209   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
99210   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
99211   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
99212   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
99213   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
99214   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
99215   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
99216        uint8_t RESERVED_0[4];
99217   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
99218   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
99219   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
99220        uint8_t RESERVED_1[4];
99221   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
99222   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
99223   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
99224        uint8_t RESERVED_2[4];
99225   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
99226   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
99227        uint8_t RESERVED_3[72];
99228   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
99229   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
99230   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
99231   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
99232 } USDHC_Type;
99233 
99234 /* ----------------------------------------------------------------------------
99235    -- USDHC Register Masks
99236    ---------------------------------------------------------------------------- */
99237 
99238 /*!
99239  * @addtogroup USDHC_Register_Masks USDHC Register Masks
99240  * @{
99241  */
99242 
99243 /*! @name DS_ADDR - DMA System Address */
99244 /*! @{ */
99245 
99246 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
99247 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
99248 /*! DS_ADDR - System address
99249  */
99250 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
99251 /*! @} */
99252 
99253 /*! @name BLK_ATT - Block Attributes */
99254 /*! @{ */
99255 
99256 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
99257 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
99258 /*! BLKSIZE - Transfer block size
99259  *  0b1000000000000..4096 bytes
99260  *  0b0100000000000..2048 bytes
99261  *  0b0001000000000..512 bytes
99262  *  0b0000111111111..511 bytes
99263  *  0b0000000000100..4 bytes
99264  *  0b0000000000011..3 bytes
99265  *  0b0000000000010..2 bytes
99266  *  0b0000000000001..1 byte
99267  *  0b0000000000000..No data transfer
99268  */
99269 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
99270 
99271 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
99272 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
99273 /*! BLKCNT - Blocks count for current transfer
99274  *  0b1111111111111111..65535 blocks
99275  *  0b0000000000000010..2 blocks
99276  *  0b0000000000000001..1 block
99277  *  0b0000000000000000..Stop count
99278  */
99279 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
99280 /*! @} */
99281 
99282 /*! @name CMD_ARG - Command Argument */
99283 /*! @{ */
99284 
99285 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
99286 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
99287 /*! CMDARG - Command argument
99288  */
99289 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
99290 /*! @} */
99291 
99292 /*! @name CMD_XFR_TYP - Command Transfer Type */
99293 /*! @{ */
99294 
99295 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
99296 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
99297 /*! RSPTYP - Response type select
99298  *  0b00..No response
99299  *  0b01..Response length 136
99300  *  0b10..Response length 48
99301  *  0b11..Response length 48, check busy after response
99302  */
99303 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
99304 
99305 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
99306 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
99307 /*! CCCEN - Command CRC check enable
99308  *  0b1..Enables command CRC check
99309  *  0b0..Disables command CRC check
99310  */
99311 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
99312 
99313 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
99314 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
99315 /*! CICEN - Command index check enable
99316  *  0b1..Enables command index check
99317  *  0b0..Disable command index check
99318  */
99319 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
99320 
99321 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
99322 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
99323 /*! DPSEL - Data present select
99324  *  0b1..Data present
99325  *  0b0..No data present
99326  */
99327 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
99328 
99329 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
99330 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
99331 /*! CMDTYP - Command type
99332  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
99333  *  0b10..Resume CMD52 for writing function select in CCCR
99334  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
99335  *  0b00..Normal other commands
99336  */
99337 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
99338 
99339 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
99340 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
99341 /*! CMDINX - Command index
99342  */
99343 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
99344 /*! @} */
99345 
99346 /*! @name CMD_RSP0 - Command Response0 */
99347 /*! @{ */
99348 
99349 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
99350 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
99351 /*! CMDRSP0 - Command response 0
99352  */
99353 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
99354 /*! @} */
99355 
99356 /*! @name CMD_RSP1 - Command Response1 */
99357 /*! @{ */
99358 
99359 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
99360 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
99361 /*! CMDRSP1 - Command response 1
99362  */
99363 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
99364 /*! @} */
99365 
99366 /*! @name CMD_RSP2 - Command Response2 */
99367 /*! @{ */
99368 
99369 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
99370 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
99371 /*! CMDRSP2 - Command response 2
99372  */
99373 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
99374 /*! @} */
99375 
99376 /*! @name CMD_RSP3 - Command Response3 */
99377 /*! @{ */
99378 
99379 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
99380 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
99381 /*! CMDRSP3 - Command response 3
99382  */
99383 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
99384 /*! @} */
99385 
99386 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
99387 /*! @{ */
99388 
99389 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
99390 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
99391 /*! DATCONT - Data content
99392  */
99393 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
99394 /*! @} */
99395 
99396 /*! @name PRES_STATE - Present State */
99397 /*! @{ */
99398 
99399 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
99400 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
99401 /*! CIHB - Command inhibit (CMD)
99402  *  0b1..Cannot issue command
99403  *  0b0..Can issue command using only CMD line
99404  */
99405 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
99406 
99407 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
99408 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
99409 /*! CDIHB - Command Inhibit Data (DATA)
99410  *  0b1..Cannot issue command that uses the DATA line
99411  *  0b0..Can issue command that uses the DATA line
99412  */
99413 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
99414 
99415 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
99416 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
99417 /*! DLA - Data line active
99418  *  0b1..DATA line active
99419  *  0b0..DATA line inactive
99420  */
99421 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
99422 
99423 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
99424 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
99425 /*! SDSTB - SD clock stable
99426  *  0b1..Clock is stable.
99427  *  0b0..Clock is changing frequency and not stable.
99428  */
99429 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
99430 
99431 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
99432 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
99433 /*! IPGOFF - Peripheral clock gated off internally
99434  *  0b1..Peripheral clock is gated off.
99435  *  0b0..Peripheral clock is active.
99436  */
99437 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
99438 
99439 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
99440 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
99441 /*! HCKOFF - HCLK gated off internally
99442  *  0b1..HCLK is gated off.
99443  *  0b0..HCLK is active.
99444  */
99445 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
99446 
99447 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
99448 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
99449 /*! PEROFF - IPG_PERCLK gated off internally
99450  *  0b1..IPG_PERCLK is gated off.
99451  *  0b0..IPG_PERCLK is active.
99452  */
99453 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
99454 
99455 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
99456 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
99457 /*! SDOFF - SD clock gated off internally
99458  *  0b1..SD clock is gated off.
99459  *  0b0..SD clock is active.
99460  */
99461 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
99462 
99463 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
99464 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
99465 /*! WTA - Write transfer active
99466  *  0b1..Transferring data
99467  *  0b0..No valid data
99468  */
99469 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
99470 
99471 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
99472 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
99473 /*! RTA - Read transfer active
99474  *  0b1..Transferring data
99475  *  0b0..No valid data
99476  */
99477 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
99478 
99479 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
99480 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
99481 /*! BWEN - Buffer write enable
99482  *  0b1..Write enable
99483  *  0b0..Write disable
99484  */
99485 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
99486 
99487 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
99488 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
99489 /*! BREN - Buffer read enable
99490  *  0b1..Read enable
99491  *  0b0..Read disable
99492  */
99493 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
99494 
99495 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
99496 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
99497 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
99498  *  0b1..Sampling clock needs re-tuning
99499  *  0b0..Fixed or well tuned sampling clock
99500  */
99501 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
99502 
99503 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
99504 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
99505 /*! TSCD - Tap select change done
99506  *  0b1..Delay cell select change is finished.
99507  *  0b0..Delay cell select change is not finished.
99508  */
99509 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
99510 
99511 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
99512 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
99513 /*! CINST - Card inserted
99514  *  0b1..Card inserted
99515  *  0b0..Power on reset or no card
99516  */
99517 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
99518 
99519 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
99520 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
99521 /*! CDPL - Card detect pin level
99522  *  0b1..Card present (CD_B = 0)
99523  *  0b0..No card present (CD_B = 1)
99524  */
99525 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
99526 
99527 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
99528 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
99529 /*! WPSPL - Write protect switch pin level
99530  *  0b1..Write enabled (WP = 0)
99531  *  0b0..Write protected (WP = 1)
99532  */
99533 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
99534 
99535 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
99536 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
99537 /*! CLSL - CMD line signal level
99538  */
99539 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
99540 
99541 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
99542 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
99543 /*! DLSL - DATA[7:0] line signal level
99544  *  0b00000111..Data 7 line signal level
99545  *  0b00000110..Data 6 line signal level
99546  *  0b00000101..Data 5 line signal level
99547  *  0b00000100..Data 4 line signal level
99548  *  0b00000011..Data 3 line signal level
99549  *  0b00000010..Data 2 line signal level
99550  *  0b00000001..Data 1 line signal level
99551  *  0b00000000..Data 0 line signal level
99552  */
99553 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
99554 /*! @} */
99555 
99556 /*! @name PROT_CTRL - Protocol Control */
99557 /*! @{ */
99558 
99559 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
99560 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
99561 /*! DTW - Data transfer width
99562  *  0b10..8-bit mode
99563  *  0b01..4-bit mode
99564  *  0b00..1-bit mode
99565  *  0b11..Reserved
99566  */
99567 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
99568 
99569 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
99570 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
99571 /*! D3CD - DATA3 as card detection pin
99572  *  0b1..DATA3 as card detection pin
99573  *  0b0..DATA3 does not monitor card insertion
99574  */
99575 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
99576 
99577 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
99578 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
99579 /*! EMODE - Endian mode
99580  *  0b00..Big endian mode
99581  *  0b01..Half word big endian mode
99582  *  0b10..Little endian mode
99583  *  0b11..Reserved
99584  */
99585 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
99586 
99587 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
99588 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
99589 /*! CDTL - Card detect test level
99590  *  0b1..Card detect test level is 1, card inserted
99591  *  0b0..Card detect test level is 0, no card inserted
99592  */
99593 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
99594 
99595 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
99596 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
99597 /*! CDSS - Card detect signal selection
99598  *  0b1..Card detection test level is selected (for test purpose).
99599  *  0b0..Card detection level is selected (for normal purpose).
99600  */
99601 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
99602 
99603 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
99604 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
99605 /*! DMASEL - DMA select
99606  *  0b00..No DMA or simple DMA is selected.
99607  *  0b01..ADMA1 is selected.
99608  *  0b10..ADMA2 is selected.
99609  *  0b11..Reserved
99610  */
99611 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
99612 
99613 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
99614 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
99615 /*! SABGREQ - Stop at block gap request
99616  *  0b1..Stop
99617  *  0b0..Transfer
99618  */
99619 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
99620 
99621 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
99622 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
99623 /*! CREQ - Continue request
99624  *  0b1..Restart
99625  *  0b0..No effect
99626  */
99627 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
99628 
99629 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
99630 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
99631 /*! RWCTL - Read wait control
99632  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
99633  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
99634  */
99635 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
99636 
99637 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
99638 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
99639 /*! IABG - Interrupt at block gap
99640  *  0b1..Enables interrupt at block gap
99641  *  0b0..Disables interrupt at block gap
99642  */
99643 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
99644 
99645 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
99646 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
99647 /*! RD_DONE_NO_8CLK - Read performed number 8 clock
99648  */
99649 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
99650 
99651 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
99652 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
99653 /*! WECINT - Wakeup event enable on card interrupt
99654  *  0b1..Enables wakeup event enable on card interrupt
99655  *  0b0..Disables wakeup event enable on card interrupt
99656  */
99657 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
99658 
99659 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
99660 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
99661 /*! WECINS - Wakeup event enable on SD card insertion
99662  *  0b1..Enable wakeup event enable on SD card insertion
99663  *  0b0..Disable wakeup event enable on SD card insertion
99664  */
99665 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
99666 
99667 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
99668 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
99669 /*! WECRM - Wakeup event enable on SD card removal
99670  *  0b1..Enables wakeup event enable on SD card removal
99671  *  0b0..Disables wakeup event enable on SD card removal
99672  */
99673 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
99674 
99675 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
99676 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
99677 /*! NON_EXACT_BLK_RD - Non-exact block read
99678  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
99679  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
99680  */
99681 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
99682 /*! @} */
99683 
99684 /*! @name SYS_CTRL - System Control */
99685 /*! @{ */
99686 
99687 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
99688 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
99689 /*! DVS - Divisor
99690  *  0b0000..Divide-by-1
99691  *  0b0001..Divide-by-2
99692  *  0b1110..Divide-by-15
99693  *  0b1111..Divide-by-16
99694  */
99695 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
99696 
99697 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
99698 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
99699 /*! SDCLKFS - SDCLK frequency select
99700  */
99701 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
99702 
99703 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
99704 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
99705 /*! DTOCV - Data timeout counter value
99706  *  0b1111..SDCLK x 2 29
99707  *  0b1110..SDCLK x 2 28
99708  *  0b1101..SDCLK x 2 27
99709  *  0b1100..SDCLK x 2 26
99710  *  0b1011..SDCLK x 2 25
99711  *  0b1010..SDCLK x 2 24
99712  *  0b1001..SDCLK x 2 23
99713  *  0b1000..SDCLK x 2 22
99714  *  0b0111..SDCLK x 2 21
99715  *  0b0110..SDCLK x 2 20
99716  *  0b0101..SDCLK x 2 19
99717  *  0b0100..SDCLK x 2 18
99718  *  0b0011..SDCLK x 2 17
99719  *  0b0010..SDCLK x 2 16
99720  *  0b0001..SDCLK x 2 15
99721  *  0b0000..SDCLK x 2 14
99722  */
99723 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
99724 
99725 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
99726 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
99727 /*! IPP_RST_N - Hardware reset
99728  */
99729 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
99730 
99731 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
99732 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
99733 /*! RSTA - Software reset for all
99734  *  0b1..Reset
99735  *  0b0..No reset
99736  */
99737 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
99738 
99739 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
99740 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
99741 /*! RSTC - Software reset for CMD line
99742  *  0b1..Reset
99743  *  0b0..No reset
99744  */
99745 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
99746 
99747 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
99748 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
99749 /*! RSTD - Software reset for data line
99750  *  0b1..Reset
99751  *  0b0..No reset
99752  */
99753 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
99754 
99755 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
99756 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
99757 /*! INITA - Initialization active
99758  */
99759 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
99760 
99761 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
99762 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
99763 /*! RSTT - Reset tuning
99764  */
99765 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
99766 /*! @} */
99767 
99768 /*! @name INT_STATUS - Interrupt Status */
99769 /*! @{ */
99770 
99771 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
99772 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
99773 /*! CC - Command complete
99774  *  0b1..Command complete
99775  *  0b0..Command not complete
99776  */
99777 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
99778 
99779 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
99780 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
99781 /*! TC - Transfer complete
99782  *  0b1..Transfer complete
99783  *  0b0..Transfer does not complete
99784  */
99785 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
99786 
99787 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
99788 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
99789 /*! BGE - Block gap event
99790  *  0b1..Transaction stopped at block gap
99791  *  0b0..No block gap event
99792  */
99793 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
99794 
99795 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
99796 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
99797 /*! DINT - DMA interrupt
99798  *  0b1..DMA interrupt is generated.
99799  *  0b0..No DMA interrupt
99800  */
99801 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
99802 
99803 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
99804 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
99805 /*! BWR - Buffer write ready
99806  *  0b1..Ready to write buffer
99807  *  0b0..Not ready to write buffer
99808  */
99809 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
99810 
99811 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
99812 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
99813 /*! BRR - Buffer read ready
99814  *  0b1..Ready to read buffer
99815  *  0b0..Not ready to read buffer
99816  */
99817 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
99818 
99819 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
99820 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
99821 /*! CINS - Card insertion
99822  *  0b1..Card inserted
99823  *  0b0..Card state unstable or removed
99824  */
99825 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
99826 
99827 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
99828 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
99829 /*! CRM - Card removal
99830  *  0b1..Card removed
99831  *  0b0..Card state unstable or inserted
99832  */
99833 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
99834 
99835 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
99836 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
99837 /*! CINT - Card interrupt
99838  *  0b1..Generate card interrupt
99839  *  0b0..No card interrupt
99840  */
99841 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
99842 
99843 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
99844 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
99845 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
99846  *  0b1..Re-tuning should be performed.
99847  *  0b0..Re-tuning is not required.
99848  */
99849 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
99850 
99851 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
99852 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
99853 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
99854  */
99855 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
99856 
99857 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
99858 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
99859 /*! CTOE - Command timeout error
99860  *  0b1..Time out
99861  *  0b0..No error
99862  */
99863 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
99864 
99865 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
99866 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
99867 /*! CCE - Command CRC error
99868  *  0b1..CRC error generated
99869  *  0b0..No error
99870  */
99871 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
99872 
99873 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
99874 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
99875 /*! CEBE - Command end bit error
99876  *  0b1..End bit error generated
99877  *  0b0..No error
99878  */
99879 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
99880 
99881 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
99882 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
99883 /*! CIE - Command index error
99884  *  0b1..Error
99885  *  0b0..No error
99886  */
99887 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
99888 
99889 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
99890 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
99891 /*! DTOE - Data timeout error
99892  *  0b1..Time out
99893  *  0b0..No error
99894  */
99895 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
99896 
99897 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
99898 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
99899 /*! DCE - Data CRC error
99900  *  0b1..Error
99901  *  0b0..No error
99902  */
99903 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
99904 
99905 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
99906 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
99907 /*! DEBE - Data end bit error
99908  *  0b1..Error
99909  *  0b0..No error
99910  */
99911 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
99912 
99913 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
99914 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
99915 /*! AC12E - Auto CMD12 error
99916  *  0b1..Error
99917  *  0b0..No error
99918  */
99919 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
99920 
99921 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
99922 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
99923 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
99924  */
99925 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
99926 
99927 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
99928 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
99929 /*! DMAE - DMA error
99930  *  0b1..Error
99931  *  0b0..No error
99932  */
99933 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
99934 /*! @} */
99935 
99936 /*! @name INT_STATUS_EN - Interrupt Status Enable */
99937 /*! @{ */
99938 
99939 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
99940 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
99941 /*! CCSEN - Command complete status enable
99942  *  0b1..Enabled
99943  *  0b0..Masked
99944  */
99945 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
99946 
99947 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
99948 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
99949 /*! TCSEN - Transfer complete status enable
99950  *  0b1..Enabled
99951  *  0b0..Masked
99952  */
99953 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
99954 
99955 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
99956 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
99957 /*! BGESEN - Block gap event status enable
99958  *  0b1..Enabled
99959  *  0b0..Masked
99960  */
99961 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
99962 
99963 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
99964 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
99965 /*! DINTSEN - DMA interrupt status enable
99966  *  0b1..Enabled
99967  *  0b0..Masked
99968  */
99969 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
99970 
99971 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
99972 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
99973 /*! BWRSEN - Buffer write ready status enable
99974  *  0b1..Enabled
99975  *  0b0..Masked
99976  */
99977 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
99978 
99979 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
99980 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
99981 /*! BRRSEN - Buffer read ready status enable
99982  *  0b1..Enabled
99983  *  0b0..Masked
99984  */
99985 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
99986 
99987 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
99988 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
99989 /*! CINSSEN - Card insertion status enable
99990  *  0b1..Enabled
99991  *  0b0..Masked
99992  */
99993 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
99994 
99995 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
99996 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
99997 /*! CRMSEN - Card removal status enable
99998  *  0b1..Enabled
99999  *  0b0..Masked
100000  */
100001 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
100002 
100003 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
100004 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
100005 /*! CINTSEN - Card interrupt status enable
100006  *  0b1..Enabled
100007  *  0b0..Masked
100008  */
100009 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
100010 
100011 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
100012 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
100013 /*! RTESEN - Re-tuning event status enable
100014  *  0b1..Enabled
100015  *  0b0..Masked
100016  */
100017 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
100018 
100019 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
100020 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
100021 /*! TPSEN - Tuning pass status enable
100022  *  0b1..Enabled
100023  *  0b0..Masked
100024  */
100025 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
100026 
100027 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
100028 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
100029 /*! CTOESEN - Command timeout error status enable
100030  *  0b1..Enabled
100031  *  0b0..Masked
100032  */
100033 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
100034 
100035 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
100036 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
100037 /*! CCESEN - Command CRC error status enable
100038  *  0b1..Enabled
100039  *  0b0..Masked
100040  */
100041 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
100042 
100043 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
100044 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
100045 /*! CEBESEN - Command end bit error status enable
100046  *  0b1..Enabled
100047  *  0b0..Masked
100048  */
100049 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
100050 
100051 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
100052 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
100053 /*! CIESEN - Command index error status enable
100054  *  0b1..Enabled
100055  *  0b0..Masked
100056  */
100057 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
100058 
100059 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
100060 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
100061 /*! DTOESEN - Data timeout error status enable
100062  *  0b1..Enabled
100063  *  0b0..Masked
100064  */
100065 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
100066 
100067 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
100068 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
100069 /*! DCESEN - Data CRC error status enable
100070  *  0b1..Enabled
100071  *  0b0..Masked
100072  */
100073 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
100074 
100075 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
100076 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
100077 /*! DEBESEN - Data end bit error status enable
100078  *  0b1..Enabled
100079  *  0b0..Masked
100080  */
100081 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
100082 
100083 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
100084 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
100085 /*! AC12ESEN - Auto CMD12 error status enable
100086  *  0b1..Enabled
100087  *  0b0..Masked
100088  */
100089 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
100090 
100091 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
100092 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
100093 /*! TNESEN - Tuning error status enable
100094  *  0b1..Enabled
100095  *  0b0..Masked
100096  */
100097 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
100098 
100099 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
100100 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
100101 /*! DMAESEN - DMA error status enable
100102  *  0b1..Enabled
100103  *  0b0..Masked
100104  */
100105 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
100106 /*! @} */
100107 
100108 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
100109 /*! @{ */
100110 
100111 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
100112 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
100113 /*! CCIEN - Command complete interrupt enable
100114  *  0b1..Enabled
100115  *  0b0..Masked
100116  */
100117 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
100118 
100119 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
100120 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
100121 /*! TCIEN - Transfer complete interrupt enable
100122  *  0b1..Enabled
100123  *  0b0..Masked
100124  */
100125 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
100126 
100127 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
100128 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
100129 /*! BGEIEN - Block gap event interrupt enable
100130  *  0b1..Enabled
100131  *  0b0..Masked
100132  */
100133 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
100134 
100135 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
100136 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
100137 /*! DINTIEN - DMA interrupt enable
100138  *  0b1..Enabled
100139  *  0b0..Masked
100140  */
100141 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
100142 
100143 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
100144 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
100145 /*! BWRIEN - Buffer write ready interrupt enable
100146  *  0b1..Enabled
100147  *  0b0..Masked
100148  */
100149 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
100150 
100151 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
100152 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
100153 /*! BRRIEN - Buffer read ready interrupt enable
100154  *  0b1..Enabled
100155  *  0b0..Masked
100156  */
100157 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
100158 
100159 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
100160 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
100161 /*! CINSIEN - Card insertion interrupt enable
100162  *  0b1..Enabled
100163  *  0b0..Masked
100164  */
100165 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
100166 
100167 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
100168 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
100169 /*! CRMIEN - Card removal interrupt enable
100170  *  0b1..Enabled
100171  *  0b0..Masked
100172  */
100173 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
100174 
100175 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
100176 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
100177 /*! CINTIEN - Card interrupt enable
100178  *  0b1..Enabled
100179  *  0b0..Masked
100180  */
100181 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
100182 
100183 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
100184 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
100185 /*! RTEIEN - Re-tuning event interrupt enable
100186  *  0b1..Enabled
100187  *  0b0..Masked
100188  */
100189 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
100190 
100191 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
100192 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
100193 /*! TPIEN - Tuning Pass interrupt enable
100194  *  0b1..Enabled
100195  *  0b0..Masked
100196  */
100197 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
100198 
100199 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
100200 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
100201 /*! CTOEIEN - Command timeout error interrupt enable
100202  *  0b1..Enabled
100203  *  0b0..Masked
100204  */
100205 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
100206 
100207 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
100208 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
100209 /*! CCEIEN - Command CRC error interrupt enable
100210  *  0b1..Enabled
100211  *  0b0..Masked
100212  */
100213 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
100214 
100215 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
100216 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
100217 /*! CEBEIEN - Command end bit error interrupt enable
100218  *  0b1..Enabled
100219  *  0b0..Masked
100220  */
100221 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
100222 
100223 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
100224 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
100225 /*! CIEIEN - Command index error interrupt enable
100226  *  0b1..Enabled
100227  *  0b0..Masked
100228  */
100229 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
100230 
100231 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
100232 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
100233 /*! DTOEIEN - Data timeout error interrupt enable
100234  *  0b1..Enabled
100235  *  0b0..Masked
100236  */
100237 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
100238 
100239 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
100240 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
100241 /*! DCEIEN - Data CRC error interrupt enable
100242  *  0b1..Enabled
100243  *  0b0..Masked
100244  */
100245 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
100246 
100247 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
100248 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
100249 /*! DEBEIEN - Data end bit error interrupt enable
100250  *  0b1..Enabled
100251  *  0b0..Masked
100252  */
100253 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
100254 
100255 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
100256 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
100257 /*! AC12EIEN - Auto CMD12 error interrupt enable
100258  *  0b1..Enabled
100259  *  0b0..Masked
100260  */
100261 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
100262 
100263 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
100264 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
100265 /*! TNEIEN - Tuning error interrupt enable
100266  *  0b1..Enabled
100267  *  0b0..Masked
100268  */
100269 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
100270 
100271 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
100272 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
100273 /*! DMAEIEN - DMA error interrupt enable
100274  *  0b1..Enable
100275  *  0b0..Masked
100276  */
100277 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
100278 /*! @} */
100279 
100280 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
100281 /*! @{ */
100282 
100283 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
100284 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
100285 /*! AC12NE - Auto CMD12 not executed
100286  *  0b1..Not executed
100287  *  0b0..Executed
100288  */
100289 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
100290 
100291 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
100292 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
100293 /*! AC12TOE - Auto CMD12 / 23 timeout error
100294  *  0b1..Time out
100295  *  0b0..No error
100296  */
100297 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
100298 
100299 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
100300 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
100301 /*! AC12EBE - Auto CMD12 / 23 end bit error
100302  *  0b1..End bit error generated
100303  *  0b0..No error
100304  */
100305 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
100306 
100307 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
100308 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
100309 /*! AC12CE - Auto CMD12 / 23 CRC error
100310  *  0b1..CRC error met in Auto CMD12/23 response
100311  *  0b0..No CRC error
100312  */
100313 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
100314 
100315 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
100316 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
100317 /*! AC12IE - Auto CMD12 / 23 index error
100318  *  0b1..Error, the CMD index in response is not CMD12/23
100319  *  0b0..No error
100320  */
100321 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
100322 
100323 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
100324 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
100325 /*! CNIBAC12E - Command not issued by Auto CMD12 error
100326  *  0b1..Not issued
100327  *  0b0..No error
100328  */
100329 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
100330 
100331 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
100332 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
100333 /*! EXECUTE_TUNING - Execute tuning
100334  *  0b1..Start tuning procedure
100335  *  0b0..Tuning procedure is aborted
100336  */
100337 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
100338 
100339 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
100340 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
100341 /*! SMP_CLK_SEL - Sample clock select
100342  *  0b1..Tuned clock is used to sample data
100343  *  0b0..Fixed clock is used to sample data
100344  */
100345 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
100346 /*! @} */
100347 
100348 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
100349 /*! @{ */
100350 
100351 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
100352 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
100353 /*! SDR50_SUPPORT - SDR50 support
100354  */
100355 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
100356 
100357 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
100358 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
100359 /*! SDR104_SUPPORT - SDR104 support
100360  */
100361 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
100362 
100363 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
100364 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
100365 /*! DDR50_SUPPORT - DDR50 support
100366  */
100367 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
100368 
100369 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
100370 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
100371 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
100372  *  0b1..SDR50 supports tuning
100373  *  0b0..SDR50 does not support tuning
100374  */
100375 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
100376 
100377 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
100378 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
100379 /*! MBL - Max block length
100380  *  0b000..512 bytes
100381  *  0b001..1024 bytes
100382  *  0b010..2048 bytes
100383  *  0b011..4096 bytes
100384  */
100385 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
100386 
100387 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
100388 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
100389 /*! ADMAS - ADMA support
100390  *  0b1..Advanced DMA supported
100391  *  0b0..Advanced DMA not supported
100392  */
100393 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
100394 
100395 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
100396 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
100397 /*! HSS - High speed support
100398  *  0b1..High speed supported
100399  *  0b0..High speed not supported
100400  */
100401 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
100402 
100403 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
100404 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
100405 /*! DMAS - DMA support
100406  *  0b1..DMA supported
100407  *  0b0..DMA not supported
100408  */
100409 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
100410 
100411 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
100412 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
100413 /*! SRS - Suspend / resume support
100414  *  0b1..Supported
100415  *  0b0..Not supported
100416  */
100417 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
100418 
100419 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
100420 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
100421 /*! VS33 - Voltage support 3.3 V
100422  *  0b1..3.3 V supported
100423  *  0b0..3.3 V not supported
100424  */
100425 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
100426 
100427 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
100428 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
100429 /*! VS30 - Voltage support 3.0 V
100430  *  0b1..3.0 V supported
100431  *  0b0..3.0 V not supported
100432  */
100433 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
100434 
100435 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
100436 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
100437 /*! VS18 - Voltage support 1.8 V
100438  *  0b1..1.8 V supported
100439  *  0b0..1.8 V not supported
100440  */
100441 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
100442 /*! @} */
100443 
100444 /*! @name WTMK_LVL - Watermark Level */
100445 /*! @{ */
100446 
100447 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
100448 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
100449 /*! RD_WML - Read watermark level
100450  */
100451 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
100452 
100453 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
100454 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
100455 /*! WR_WML - Write watermark level
100456  */
100457 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
100458 /*! @} */
100459 
100460 /*! @name MIX_CTRL - Mixer Control */
100461 /*! @{ */
100462 
100463 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
100464 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
100465 /*! DMAEN - DMA enable
100466  *  0b1..Enable
100467  *  0b0..Disable
100468  */
100469 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
100470 
100471 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
100472 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
100473 /*! BCEN - Block count enable
100474  *  0b1..Enable
100475  *  0b0..Disable
100476  */
100477 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
100478 
100479 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
100480 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
100481 /*! AC12EN - Auto CMD12 enable
100482  *  0b1..Enable
100483  *  0b0..Disable
100484  */
100485 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
100486 
100487 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
100488 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
100489 /*! DDR_EN - Dual data rate mode selection
100490  */
100491 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
100492 
100493 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
100494 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
100495 /*! DTDSEL - Data transfer direction select
100496  *  0b1..Read (Card to host)
100497  *  0b0..Write (Host to card)
100498  */
100499 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
100500 
100501 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
100502 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
100503 /*! MSBSEL - Multi / Single block select
100504  *  0b1..Multiple blocks
100505  *  0b0..Single block
100506  */
100507 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
100508 
100509 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
100510 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
100511 /*! NIBBLE_POS - Nibble position indication
100512  */
100513 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
100514 
100515 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
100516 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
100517 /*! AC23EN - Auto CMD23 enable
100518  */
100519 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
100520 
100521 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
100522 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
100523 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
100524  *  0b1..Execute tuning
100525  *  0b0..Not tuned or tuning completed
100526  */
100527 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
100528 
100529 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
100530 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
100531 /*! SMP_CLK_SEL - Clock selection
100532  *  0b1..Tuned clock is used to sample data / cmd
100533  *  0b0..Fixed clock is used to sample data / cmd
100534  */
100535 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
100536 
100537 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
100538 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
100539 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
100540  *  0b1..Enable auto tuning
100541  *  0b0..Disable auto tuning
100542  */
100543 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
100544 
100545 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
100546 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
100547 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
100548  *  0b1..Feedback clock comes from the ipp_card_clk_out
100549  *  0b0..Feedback clock comes from the loopback CLK
100550  */
100551 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
100552 
100553 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
100554 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
100555 /*! HS400_MODE - Enable HS400 mode
100556  */
100557 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
100558 /*! @} */
100559 
100560 /*! @name FORCE_EVENT - Force Event */
100561 /*! @{ */
100562 
100563 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
100564 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
100565 /*! FEVTAC12NE - Force event auto command 12 not executed
100566  */
100567 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
100568 
100569 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
100570 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
100571 /*! FEVTAC12TOE - Force event auto command 12 time out error
100572  */
100573 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
100574 
100575 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
100576 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
100577 /*! FEVTAC12CE - Force event auto command 12 CRC error
100578  */
100579 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
100580 
100581 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
100582 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
100583 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error
100584  */
100585 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
100586 
100587 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
100588 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
100589 /*! FEVTAC12IE - Force event Auto Command 12 index error
100590  */
100591 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
100592 
100593 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
100594 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
100595 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
100596  */
100597 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
100598 
100599 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
100600 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
100601 /*! FEVTCTOE - Force event command time out error
100602  */
100603 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
100604 
100605 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
100606 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
100607 /*! FEVTCCE - Force event command CRC error
100608  */
100609 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
100610 
100611 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
100612 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
100613 /*! FEVTCEBE - Force event command end bit error
100614  */
100615 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
100616 
100617 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
100618 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
100619 /*! FEVTCIE - Force event command index error
100620  */
100621 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
100622 
100623 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
100624 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
100625 /*! FEVTDTOE - Force event data time out error
100626  */
100627 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
100628 
100629 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
100630 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
100631 /*! FEVTDCE - Force event data CRC error
100632  */
100633 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
100634 
100635 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
100636 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
100637 /*! FEVTDEBE - Force event data end bit error
100638  */
100639 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
100640 
100641 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
100642 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
100643 /*! FEVTAC12E - Force event Auto Command 12 error
100644  */
100645 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
100646 
100647 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
100648 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
100649 /*! FEVTTNE - Force tuning error
100650  */
100651 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
100652 
100653 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
100654 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
100655 /*! FEVTDMAE - Force event DMA error
100656  */
100657 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
100658 
100659 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
100660 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
100661 /*! FEVTCINT - Force event card interrupt
100662  */
100663 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
100664 /*! @} */
100665 
100666 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
100667 /*! @{ */
100668 
100669 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
100670 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
100671 /*! ADMAES - ADMA error state (when ADMA error is occurred)
100672  */
100673 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
100674 
100675 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
100676 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
100677 /*! ADMALME - ADMA length mismatch error
100678  *  0b1..Error
100679  *  0b0..No error
100680  */
100681 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
100682 
100683 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
100684 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
100685 /*! ADMADCE - ADMA descriptor error
100686  *  0b1..Error
100687  *  0b0..No error
100688  */
100689 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
100690 /*! @} */
100691 
100692 /*! @name ADMA_SYS_ADDR - ADMA System Address */
100693 /*! @{ */
100694 
100695 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
100696 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
100697 /*! ADS_ADDR - ADMA system address
100698  */
100699 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
100700 /*! @} */
100701 
100702 /*! @name DLL_CTRL - DLL (Delay Line) Control */
100703 /*! @{ */
100704 
100705 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
100706 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
100707 /*! DLL_CTRL_ENABLE - DLL and delay chain
100708  */
100709 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
100710 
100711 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
100712 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
100713 /*! DLL_CTRL_RESET - DLL reset
100714  */
100715 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
100716 
100717 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
100718 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
100719 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
100720  */
100721 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
100722 
100723 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
100724 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
100725 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
100726  */
100727 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
100728 
100729 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
100730 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
100731 /*! DLL_CTRL_GATE_UPDATE - DLL gate update
100732  */
100733 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
100734 
100735 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
100736 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
100737 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
100738  */
100739 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
100740 
100741 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
100742 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
100743 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
100744  */
100745 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
100746 
100747 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
100748 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
100749 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
100750  */
100751 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
100752 
100753 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
100754 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
100755 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
100756  */
100757 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
100758 
100759 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
100760 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
100761 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
100762  */
100763 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
100764 /*! @} */
100765 
100766 /*! @name DLL_STATUS - DLL Status */
100767 /*! @{ */
100768 
100769 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
100770 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
100771 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status
100772  */
100773 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
100774 
100775 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
100776 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
100777 /*! DLL_STS_REF_LOCK - Reference DLL lock status
100778  */
100779 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
100780 
100781 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
100782 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
100783 /*! DLL_STS_SLV_SEL - Slave delay line select status
100784  */
100785 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
100786 
100787 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
100788 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
100789 /*! DLL_STS_REF_SEL - Reference delay line select taps
100790  */
100791 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
100792 /*! @} */
100793 
100794 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
100795 /*! @{ */
100796 
100797 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
100798 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
100799 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
100800  */
100801 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
100802 
100803 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
100804 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
100805 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
100806  */
100807 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
100808 
100809 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
100810 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
100811 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
100812  */
100813 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
100814 
100815 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
100816 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
100817 /*! NXT_ERR - NXT error
100818  */
100819 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
100820 
100821 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
100822 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
100823 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
100824  */
100825 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
100826 
100827 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
100828 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
100829 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
100830  */
100831 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
100832 
100833 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
100834 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
100835 /*! TAP_SEL_PRE - TAP_SEL_PRE
100836  */
100837 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
100838 
100839 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
100840 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
100841 /*! PRE_ERR - PRE error
100842  */
100843 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
100844 /*! @} */
100845 
100846 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
100847 /*! @{ */
100848 
100849 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
100850 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
100851 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
100852  */
100853 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
100854 
100855 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
100856 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
100857 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
100858  */
100859 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
100860 
100861 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
100862 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
100863 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
100864  */
100865 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
100866 
100867 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
100868 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
100869 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
100870  */
100871 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
100872 
100873 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
100874 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
100875 /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update
100876  */
100877 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
100878 
100879 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
100880 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
100881 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
100882  */
100883 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
100884 
100885 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
100886 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
100887 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
100888  */
100889 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
100890 
100891 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
100892 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
100893 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
100894  */
100895 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
100896 
100897 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
100898 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
100899 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
100900  */
100901 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
100902 /*! @} */
100903 
100904 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
100905 /*! @{ */
100906 
100907 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
100908 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
100909 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
100910  */
100911 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
100912 
100913 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
100914 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
100915 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
100916  */
100917 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
100918 
100919 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
100920 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
100921 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
100922  */
100923 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
100924 
100925 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
100926 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
100927 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
100928  */
100929 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
100930 /*! @} */
100931 
100932 /*! @name VEND_SPEC - Vendor Specific Register */
100933 /*! @{ */
100934 
100935 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
100936 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
100937 /*! VSELECT - Voltage selection
100938  *  0b1..Change the voltage to low voltage range, around 1.8 V
100939  *  0b0..Change the voltage to high voltage range, around 3.0 V
100940  */
100941 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
100942 
100943 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
100944 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
100945 /*! CONFLICT_CHK_EN - Conflict check enable
100946  *  0b0..Conflict check disable
100947  *  0b1..Conflict check enable
100948  */
100949 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
100950 
100951 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
100952 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
100953 /*! AC12_WR_CHKBUSY_EN - Check busy enable
100954  *  0b0..Do not check busy after auto CMD12 for write data packet
100955  *  0b1..Check busy after auto CMD12 for write data packet
100956  */
100957 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
100958 
100959 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
100960 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
100961 /*! FRC_SDCLK_ON - Force CLK
100962  *  0b0..CLK active or inactive is fully controlled by the hardware.
100963  *  0b1..Force CLK active
100964  */
100965 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
100966 
100967 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
100968 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
100969 /*! CRC_CHK_DIS - CRC Check Disable
100970  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
100971  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
100972  */
100973 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
100974 
100975 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
100976 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
100977 /*! CMD_BYTE_EN - Byte access
100978  *  0b0..Disable
100979  *  0b1..Enable
100980  */
100981 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
100982 /*! @} */
100983 
100984 /*! @name MMC_BOOT - MMC Boot */
100985 /*! @{ */
100986 
100987 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
100988 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
100989 /*! DTOCV_ACK - Boot ACK time out
100990  *  0b0000..SDCLK x 2^14
100991  *  0b0001..SDCLK x 2^15
100992  *  0b0010..SDCLK x 2^16
100993  *  0b0011..SDCLK x 2^17
100994  *  0b0100..SDCLK x 2^18
100995  *  0b0101..SDCLK x 2^19
100996  *  0b0110..SDCLK x 2^20
100997  *  0b0111..SDCLK x 2^21
100998  *  0b1110..SDCLK x 2^28
100999  *  0b1111..SDCLK x 2^29
101000  */
101001 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
101002 
101003 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
101004 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
101005 /*! BOOT_ACK - BOOT ACK
101006  *  0b0..No ack
101007  *  0b1..Ack
101008  */
101009 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
101010 
101011 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
101012 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
101013 /*! BOOT_MODE - Boot mode
101014  *  0b0..Normal boot
101015  *  0b1..Alternative boot
101016  */
101017 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
101018 
101019 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
101020 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
101021 /*! BOOT_EN - Boot enable
101022  *  0b0..Fast boot disable
101023  *  0b1..Fast boot enable
101024  */
101025 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
101026 
101027 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
101028 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
101029 /*! AUTO_SABG_EN - Auto stop at block gap
101030  */
101031 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
101032 
101033 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
101034 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
101035 /*! DISABLE_TIME_OUT - Time out
101036  *  0b0..Enable time out
101037  *  0b1..Disable time out
101038  */
101039 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
101040 
101041 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
101042 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
101043 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
101044  */
101045 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
101046 /*! @} */
101047 
101048 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
101049 /*! @{ */
101050 
101051 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
101052 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
101053 /*! CARD_INT_D3_TEST - Card interrupt detection test
101054  *  0b0..Check the card interrupt only when DATA3 is high.
101055  *  0b1..Check the card interrupt by ignoring the status of DATA3.
101056  */
101057 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
101058 
101059 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
101060 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
101061 /*! TUNING_8bit_EN - Tuning 8bit enable
101062  */
101063 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
101064 
101065 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
101066 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
101067 /*! TUNING_1bit_EN - Tuning 1bit enable
101068  */
101069 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
101070 
101071 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
101072 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
101073 /*! TUNING_CMD_EN - Tuning command enable
101074  *  0b0..Auto tuning circuit does not check the CMD line.
101075  *  0b1..Auto tuning circuit checks the CMD line.
101076  */
101077 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
101078 
101079 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
101080 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
101081 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
101082  */
101083 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
101084 
101085 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
101086 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
101087 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
101088  */
101089 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
101090 
101091 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
101092 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
101093 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
101094  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
101095  *  0b0..Disable
101096  */
101097 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
101098 /*! @} */
101099 
101100 /*! @name TUNING_CTRL - Tuning Control */
101101 /*! @{ */
101102 
101103 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
101104 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
101105 /*! TUNING_START_TAP - Tuning start
101106  */
101107 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
101108 
101109 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
101110 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
101111 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning
101112  */
101113 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
101114 
101115 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
101116 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
101117 /*! TUNING_COUNTER - Tuning counter
101118  */
101119 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
101120 
101121 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
101122 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
101123 /*! TUNING_STEP - TUNING_STEP
101124  */
101125 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
101126 
101127 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
101128 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
101129 /*! TUNING_WINDOW - Data window
101130  */
101131 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
101132 
101133 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
101134 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
101135 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable
101136  */
101137 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
101138 /*! @} */
101139 
101140 
101141 /*!
101142  * @}
101143  */ /* end of group USDHC_Register_Masks */
101144 
101145 
101146 /* USDHC - Peripheral instance base addresses */
101147 /** Peripheral USDHC1 base address */
101148 #define USDHC1_BASE                              (0x40418000u)
101149 /** Peripheral USDHC1 base pointer */
101150 #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
101151 /** Peripheral USDHC2 base address */
101152 #define USDHC2_BASE                              (0x4041C000u)
101153 /** Peripheral USDHC2 base pointer */
101154 #define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
101155 /** Array initializer of USDHC peripheral base addresses */
101156 #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE, USDHC2_BASE }
101157 /** Array initializer of USDHC peripheral base pointers */
101158 #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1, USDHC2 }
101159 /** Interrupt vectors for the USDHC peripheral type */
101160 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
101161 
101162 /*!
101163  * @}
101164  */ /* end of group USDHC_Peripheral_Access_Layer */
101165 
101166 
101167 /* ----------------------------------------------------------------------------
101168    -- VIDEO_MUX Peripheral Access Layer
101169    ---------------------------------------------------------------------------- */
101170 
101171 /*!
101172  * @addtogroup VIDEO_MUX_Peripheral_Access_Layer VIDEO_MUX Peripheral Access Layer
101173  * @{
101174  */
101175 
101176 /** VIDEO_MUX - Register Layout Typedef */
101177 typedef struct {
101178   struct {                                         /* offset: 0x0 */
101179     __IO uint32_t RW;                                /**< Video mux Control Register, offset: 0x0 */
101180     __IO uint32_t SET;                               /**< Video mux Control Register, offset: 0x4 */
101181     __IO uint32_t CLR;                               /**< Video mux Control Register, offset: 0x8 */
101182     __IO uint32_t TOG;                               /**< Video mux Control Register, offset: 0xC */
101183   } VID_MUX_CTRL;
101184        uint8_t RESERVED_0[16];
101185   struct {                                         /* offset: 0x20 */
101186     __IO uint32_t RW;                                /**< Pixel Link Master(PLM) Control Register, offset: 0x20 */
101187     __IO uint32_t SET;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x24 */
101188     __IO uint32_t CLR;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x28 */
101189     __IO uint32_t TOG;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x2C */
101190   } PLM_CTRL;
101191   struct {                                         /* offset: 0x30 */
101192     __IO uint32_t RW;                                /**< YUV420 Control Register, offset: 0x30 */
101193     __IO uint32_t SET;                               /**< YUV420 Control Register, offset: 0x34 */
101194     __IO uint32_t CLR;                               /**< YUV420 Control Register, offset: 0x38 */
101195     __IO uint32_t TOG;                               /**< YUV420 Control Register, offset: 0x3C */
101196   } YUV420_CTRL;
101197        uint8_t RESERVED_1[16];
101198   struct {                                         /* offset: 0x50 */
101199     __IO uint32_t RW;                                /**< Data Disable Register, offset: 0x50 */
101200     __IO uint32_t SET;                               /**< Data Disable Register, offset: 0x54 */
101201     __IO uint32_t CLR;                               /**< Data Disable Register, offset: 0x58 */
101202     __IO uint32_t TOG;                               /**< Data Disable Register, offset: 0x5C */
101203   } CFG_DT_DISABLE;
101204        uint8_t RESERVED_2[16];
101205   struct {                                         /* offset: 0x70 */
101206     __IO uint32_t RW;                                /**< MIPI DSI Control Register, offset: 0x70 */
101207     __IO uint32_t SET;                               /**< MIPI DSI Control Register, offset: 0x74 */
101208     __IO uint32_t CLR;                               /**< MIPI DSI Control Register, offset: 0x78 */
101209     __IO uint32_t TOG;                               /**< MIPI DSI Control Register, offset: 0x7C */
101210   } MIPI_DSI_CTRL;
101211 } VIDEO_MUX_Type;
101212 
101213 /* ----------------------------------------------------------------------------
101214    -- VIDEO_MUX Register Masks
101215    ---------------------------------------------------------------------------- */
101216 
101217 /*!
101218  * @addtogroup VIDEO_MUX_Register_Masks VIDEO_MUX Register Masks
101219  * @{
101220  */
101221 
101222 /*! @name VID_MUX_CTRL - Video mux Control Register */
101223 /*! @{ */
101224 
101225 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK      (0x1U)
101226 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT     (0U)
101227 /*! CSI_SEL - CSI sensor data input mux selector
101228  *  0b0..CSI sensor data is from Parallel CSI
101229  *  0b1..CSI sensor data is from MIPI CSI
101230  */
101231 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
101232 
101233 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
101234 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT  (1U)
101235 /*! LCDIF2_SEL - LCDIF2 sensor data input mux selector
101236  *  0b0..LCDIFv2 sensor data is from Parallel CSI
101237  *  0b1..LCDIFv2 sensor data is from MIPI CSI
101238  */
101239 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
101240 
101241 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U)
101242 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U)
101243 /*! MIPI_DSI_SEL - MIPI DSI video data input mux selector
101244  *  0b0..MIPI DSI video data is from eLCDIF
101245  *  0b1..MIPI DSI video data is from LCDIFv2
101246  */
101247 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
101248 
101249 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U)
101250 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U)
101251 /*! PARA_LCD_SEL - Parallel LCDIF video data input mux selector
101252  *  0b0..Parallel LCDIF video data is from eLCDIF
101253  *  0b1..Parallel LCDIF video data is from LCDIFv2
101254  */
101255 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
101256 /*! @} */
101257 
101258 /*! @name PLM_CTRL - Pixel Link Master(PLM) Control Register */
101259 /*! @{ */
101260 
101261 #define VIDEO_MUX_PLM_CTRL_ENABLE_MASK           (0x1U)
101262 #define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT          (0U)
101263 /*! ENABLE - Enable the output of HYSNC and VSYNC
101264  *  0b0..No active HSYNC and VSYNC output
101265  *  0b1..Active HSYNC and VSYNC output
101266  */
101267 #define VIDEO_MUX_PLM_CTRL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
101268 
101269 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
101270 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT  (1U)
101271 /*! VSYNC_OVERRIDE - VSYNC override
101272  *  0b1..VSYNC is asserted
101273  *  0b0..VSYNC is not asserted
101274  */
101275 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
101276 
101277 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
101278 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT  (2U)
101279 /*! HSYNC_OVERRIDE - HSYNC override
101280  *  0b1..HSYNC is asserted
101281  *  0b0..HSYNC is not asserted
101282  */
101283 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
101284 
101285 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
101286 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT  (3U)
101287 /*! VALID_OVERRIDE - Valid override
101288  *  0b0..HSYNC and VSYNC is asserted
101289  *  0b1..HSYNC and VSYNC is not asserted
101290  */
101291 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
101292 
101293 #define VIDEO_MUX_PLM_CTRL_POLARITY_MASK         (0x10U)
101294 #define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT        (4U)
101295 /*! POLARITY - Polarity of HYSNC/VSYNC
101296  *  0b0..Keep the current polarity of HSYNC and VSYNC
101297  *  0b1..Invert the polarity of HSYNC and VSYNC
101298  */
101299 #define VIDEO_MUX_PLM_CTRL_POLARITY(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
101300 /*! @} */
101301 
101302 /*! @name YUV420_CTRL - YUV420 Control Register */
101303 /*! @{ */
101304 
101305 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U)
101306 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U)
101307 /*! FST_LN_DATA_TYPE - Data type of First Line
101308  *  0b0..Odd (default)
101309  *  0b1..Even
101310  */
101311 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
101312 /*! @} */
101313 
101314 /*! @name CFG_DT_DISABLE - Data Disable Register */
101315 /*! @{ */
101316 
101317 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU)
101318 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U)
101319 /*! CFG_DT_DISABLE - Data Type Disable
101320  */
101321 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
101322 /*! @} */
101323 
101324 /*! @name MIPI_DSI_CTRL - MIPI DSI Control Register */
101325 /*! @{ */
101326 
101327 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK      (0x1U)
101328 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT     (0U)
101329 /*! DPI_SD - Shut Down - Control to shutdown display (type 4 only)
101330  *  0b0..No effect
101331  *  0b1..Send shutdown command
101332  */
101333 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
101334 
101335 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK      (0x2U)
101336 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT     (1U)
101337 /*! DPI_CM - Color Mode control
101338  *  0b0..Normal Mode
101339  *  0b1..Low-color mode
101340  */
101341 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
101342 /*! @} */
101343 
101344 
101345 /*!
101346  * @}
101347  */ /* end of group VIDEO_MUX_Register_Masks */
101348 
101349 
101350 /* VIDEO_MUX - Peripheral instance base addresses */
101351 /** Peripheral VIDEO_MUX base address */
101352 #define VIDEO_MUX_BASE                           (0x40818000u)
101353 /** Peripheral VIDEO_MUX base pointer */
101354 #define VIDEO_MUX                                ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
101355 /** Array initializer of VIDEO_MUX peripheral base addresses */
101356 #define VIDEO_MUX_BASE_ADDRS                     { VIDEO_MUX_BASE }
101357 /** Array initializer of VIDEO_MUX peripheral base pointers */
101358 #define VIDEO_MUX_BASE_PTRS                      { VIDEO_MUX }
101359 
101360 /*!
101361  * @}
101362  */ /* end of group VIDEO_MUX_Peripheral_Access_Layer */
101363 
101364 
101365 /* ----------------------------------------------------------------------------
101366    -- VIDEO_PLL Peripheral Access Layer
101367    ---------------------------------------------------------------------------- */
101368 
101369 /*!
101370  * @addtogroup VIDEO_PLL_Peripheral_Access_Layer VIDEO_PLL Peripheral Access Layer
101371  * @{
101372  */
101373 
101374 /** VIDEO_PLL - Register Layout Typedef */
101375 typedef struct {
101376   struct {                                         /* offset: 0x0 */
101377     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
101378     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
101379     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
101380     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
101381   } CTRL0;
101382   struct {                                         /* offset: 0x10 */
101383     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
101384     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
101385     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
101386     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
101387   } SPREAD_SPECTRUM;
101388   struct {                                         /* offset: 0x20 */
101389     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
101390     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
101391     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
101392     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
101393   } NUMERATOR;
101394   struct {                                         /* offset: 0x30 */
101395     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
101396     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
101397     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
101398     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
101399   } DENOMINATOR;
101400 } VIDEO_PLL_Type;
101401 
101402 /* ----------------------------------------------------------------------------
101403    -- VIDEO_PLL Register Masks
101404    ---------------------------------------------------------------------------- */
101405 
101406 /*!
101407  * @addtogroup VIDEO_PLL_Register_Masks VIDEO_PLL Register Masks
101408  * @{
101409  */
101410 
101411 /*! @name CTRL0 - Fractional PLL Control Register */
101412 /*! @{ */
101413 
101414 #define VIDEO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
101415 #define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
101416 /*! DIV_SELECT - DIV_SELECT
101417  */
101418 #define VIDEO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK)
101419 
101420 #define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
101421 #define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
101422 /*! ENABLE_ALT - ENABLE_ALT
101423  *  0b0..Disable the alternate clock output
101424  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
101425  */
101426 #define VIDEO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK)
101427 
101428 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
101429 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
101430 /*! HOLD_RING_OFF - PLL Start up initialization
101431  *  0b0..Normal operation
101432  *  0b1..Initialize PLL start up
101433  */
101434 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK)
101435 
101436 #define VIDEO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
101437 #define VIDEO_PLL_CTRL0_POWERUP_SHIFT            (14U)
101438 /*! POWERUP - POWERUP
101439  *  0b1..Power Up the PLL
101440  *  0b0..Power down the PLL
101441  */
101442 #define VIDEO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK)
101443 
101444 #define VIDEO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
101445 #define VIDEO_PLL_CTRL0_ENABLE_SHIFT             (15U)
101446 /*! ENABLE - ENABLE
101447  *  0b1..Enable the clock output
101448  *  0b0..Disable the clock output
101449  */
101450 #define VIDEO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK)
101451 
101452 #define VIDEO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
101453 #define VIDEO_PLL_CTRL0_BYPASS_SHIFT             (16U)
101454 /*! BYPASS - BYPASS
101455  *  0b1..Bypass the PLL
101456  *  0b0..No Bypass
101457  */
101458 #define VIDEO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK)
101459 
101460 #define VIDEO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
101461 #define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
101462 /*! DITHER_EN - DITHER_EN
101463  *  0b0..Disable Dither
101464  *  0b1..Enable Dither
101465  */
101466 #define VIDEO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK)
101467 
101468 #define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
101469 #define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
101470 /*! BIAS_TRIM - BIAS_TRIM
101471  */
101472 #define VIDEO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK)
101473 
101474 #define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
101475 #define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
101476 /*! PLL_REG_EN - PLL_REG_EN
101477  */
101478 #define VIDEO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK)
101479 
101480 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
101481 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
101482 /*! POST_DIV_SEL - Post Divide Select
101483  *  0b000..Divide by 1
101484  *  0b001..Divide by 2
101485  *  0b010..Divide by 4
101486  *  0b011..Divide by 8
101487  *  0b100..Divide by 16
101488  *  0b101..Divide by 32
101489  */
101490 #define VIDEO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK)
101491 
101492 #define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
101493 #define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
101494 /*! BIAS_SELECT - BIAS_SELECT
101495  *  0b0..Used in SoCs with a bias current of 10uA
101496  *  0b1..Used in SoCs with a bias current of 2uA
101497  */
101498 #define VIDEO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK)
101499 /*! @} */
101500 
101501 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
101502 /*! @{ */
101503 
101504 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
101505 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
101506 /*! STEP - Step
101507  */
101508 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK)
101509 
101510 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
101511 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
101512 /*! ENABLE - Enable
101513  */
101514 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
101515 
101516 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
101517 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
101518 /*! STOP - Stop
101519  */
101520 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK)
101521 /*! @} */
101522 
101523 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
101524 /*! @{ */
101525 
101526 #define VIDEO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
101527 #define VIDEO_PLL_NUMERATOR_NUM_SHIFT            (0U)
101528 /*! NUM - Numerator
101529  */
101530 #define VIDEO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK)
101531 /*! @} */
101532 
101533 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
101534 /*! @{ */
101535 
101536 #define VIDEO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
101537 #define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
101538 /*! DENOM - Denominator
101539  */
101540 #define VIDEO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK)
101541 /*! @} */
101542 
101543 
101544 /*!
101545  * @}
101546  */ /* end of group VIDEO_PLL_Register_Masks */
101547 
101548 
101549 /* VIDEO_PLL - Peripheral instance base addresses */
101550 /** Peripheral VIDEO_PLL base address */
101551 #define VIDEO_PLL_BASE                           (0u)
101552 /** Peripheral VIDEO_PLL base pointer */
101553 #define VIDEO_PLL                                ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
101554 /** Array initializer of VIDEO_PLL peripheral base addresses */
101555 #define VIDEO_PLL_BASE_ADDRS                     { VIDEO_PLL_BASE }
101556 /** Array initializer of VIDEO_PLL peripheral base pointers */
101557 #define VIDEO_PLL_BASE_PTRS                      { VIDEO_PLL }
101558 
101559 /*!
101560  * @}
101561  */ /* end of group VIDEO_PLL_Peripheral_Access_Layer */
101562 
101563 
101564 /* ----------------------------------------------------------------------------
101565    -- VMBANDGAP Peripheral Access Layer
101566    ---------------------------------------------------------------------------- */
101567 
101568 /*!
101569  * @addtogroup VMBANDGAP_Peripheral_Access_Layer VMBANDGAP Peripheral Access Layer
101570  * @{
101571  */
101572 
101573 /** VMBANDGAP - Register Layout Typedef */
101574 typedef struct {
101575   struct {                                         /* offset: 0x0 */
101576     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
101577     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
101578     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
101579     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
101580   } CTRL0;
101581        uint8_t RESERVED_0[64];
101582   struct {                                         /* offset: 0x50 */
101583     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
101584     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
101585     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
101586     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
101587   } STAT0;
101588 } VMBANDGAP_Type;
101589 
101590 /* ----------------------------------------------------------------------------
101591    -- VMBANDGAP Register Masks
101592    ---------------------------------------------------------------------------- */
101593 
101594 /*!
101595  * @addtogroup VMBANDGAP_Register_Masks VMBANDGAP Register Masks
101596  * @{
101597  */
101598 
101599 /*! @name CTRL0 - Analog Control Register CTRL0 */
101600 /*! @{ */
101601 
101602 #define VMBANDGAP_CTRL0_REFTOP_PWD_MASK          (0x1U)
101603 #define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT         (0U)
101604 /*! REFTOP_PWD - Master power-down for bandgap module
101605  */
101606 #define VMBANDGAP_CTRL0_REFTOP_PWD(x)            (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
101607 
101608 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
101609 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
101610 /*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer
101611  */
101612 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)  (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
101613 
101614 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK     (0x4U)
101615 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT    (2U)
101616 /*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap
101617  */
101618 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
101619 
101620 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK     (0x8U)
101621 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT    (3U)
101622 /*! REFTOP_LOWPOWER - Low-power control bit
101623  */
101624 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
101625 
101626 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK  (0x10U)
101627 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
101628 /*! REFTOP_SELFBIASOFF - bandgap self-bias control bit
101629  */
101630 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)    (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
101631 /*! @} */
101632 
101633 /*! @name STAT0 - Analog Status Register STAT0 */
101634 /*! @{ */
101635 
101636 #define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK        (0x1U)
101637 #define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT       (0U)
101638 /*! REFTOP_VBGUP - Brief description here
101639  */
101640 #define VMBANDGAP_STAT0_REFTOP_VBGUP(x)          (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
101641 
101642 #define VMBANDGAP_STAT0_VDD1_PORB_MASK           (0x2U)
101643 #define VMBANDGAP_STAT0_VDD1_PORB_SHIFT          (1U)
101644 /*! VDD1_PORB - Brief description here
101645  */
101646 #define VMBANDGAP_STAT0_VDD1_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
101647 
101648 #define VMBANDGAP_STAT0_VDD2_PORB_MASK           (0x4U)
101649 #define VMBANDGAP_STAT0_VDD2_PORB_SHIFT          (2U)
101650 /*! VDD2_PORB - Brief description here
101651  */
101652 #define VMBANDGAP_STAT0_VDD2_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
101653 
101654 #define VMBANDGAP_STAT0_VDD3_PORB_MASK           (0x8U)
101655 #define VMBANDGAP_STAT0_VDD3_PORB_SHIFT          (3U)
101656 /*! VDD3_PORB - Brief description here
101657  */
101658 #define VMBANDGAP_STAT0_VDD3_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK)
101659 /*! @} */
101660 
101661 
101662 /*!
101663  * @}
101664  */ /* end of group VMBANDGAP_Register_Masks */
101665 
101666 
101667 /* VMBANDGAP - Peripheral instance base addresses */
101668 /** Peripheral VMBANDGAP base address */
101669 #define VMBANDGAP_BASE                           (0u)
101670 /** Peripheral VMBANDGAP base pointer */
101671 #define VMBANDGAP                                ((VMBANDGAP_Type *)VMBANDGAP_BASE)
101672 /** Array initializer of VMBANDGAP peripheral base addresses */
101673 #define VMBANDGAP_BASE_ADDRS                     { VMBANDGAP_BASE }
101674 /** Array initializer of VMBANDGAP peripheral base pointers */
101675 #define VMBANDGAP_BASE_PTRS                      { VMBANDGAP }
101676 
101677 /*!
101678  * @}
101679  */ /* end of group VMBANDGAP_Peripheral_Access_Layer */
101680 
101681 
101682 /* ----------------------------------------------------------------------------
101683    -- WDOG Peripheral Access Layer
101684    ---------------------------------------------------------------------------- */
101685 
101686 /*!
101687  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
101688  * @{
101689  */
101690 
101691 /** WDOG - Register Layout Typedef */
101692 typedef struct {
101693   __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
101694   __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
101695   __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
101696   __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
101697   __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
101698 } WDOG_Type;
101699 
101700 /* ----------------------------------------------------------------------------
101701    -- WDOG Register Masks
101702    ---------------------------------------------------------------------------- */
101703 
101704 /*!
101705  * @addtogroup WDOG_Register_Masks WDOG Register Masks
101706  * @{
101707  */
101708 
101709 /*! @name WCR - Watchdog Control Register */
101710 /*! @{ */
101711 
101712 #define WDOG_WCR_WDZST_MASK                      (0x1U)
101713 #define WDOG_WCR_WDZST_SHIFT                     (0U)
101714 /*! WDZST - WDZST
101715  *  0b0..Continue timer operation (Default).
101716  *  0b1..Suspend the watchdog timer.
101717  */
101718 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
101719 
101720 #define WDOG_WCR_WDBG_MASK                       (0x2U)
101721 #define WDOG_WCR_WDBG_SHIFT                      (1U)
101722 /*! WDBG - WDBG
101723  *  0b0..Continue WDOG timer operation (Default).
101724  *  0b1..Suspend the watchdog timer.
101725  */
101726 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
101727 
101728 #define WDOG_WCR_WDE_MASK                        (0x4U)
101729 #define WDOG_WCR_WDE_SHIFT                       (2U)
101730 /*! WDE - WDE
101731  *  0b0..Disable the Watchdog (Default).
101732  *  0b1..Enable the Watchdog.
101733  */
101734 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
101735 
101736 #define WDOG_WCR_WDT_MASK                        (0x8U)
101737 #define WDOG_WCR_WDT_SHIFT                       (3U)
101738 /*! WDT - WDT
101739  *  0b0..No effect on WDOG_B (Default).
101740  *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
101741  */
101742 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
101743 
101744 #define WDOG_WCR_SRS_MASK                        (0x10U)
101745 #define WDOG_WCR_SRS_SHIFT                       (4U)
101746 /*! SRS - SRS
101747  *  0b0..Assert system reset signal.
101748  *  0b1..No effect on the system (Default).
101749  */
101750 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
101751 
101752 #define WDOG_WCR_WDA_MASK                        (0x20U)
101753 #define WDOG_WCR_WDA_SHIFT                       (5U)
101754 /*! WDA - WDA
101755  *  0b0..Assert WDOG_B output.
101756  *  0b1..No effect on system (Default).
101757  */
101758 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
101759 
101760 #define WDOG_WCR_SRE_MASK                        (0x40U)
101761 #define WDOG_WCR_SRE_SHIFT                       (6U)
101762 /*! SRE - Software Reset Extension, an optional way to generate software reset
101763  *  0b0..using original way to generate software reset (default)
101764  *  0b1..using new way to generate software reset.
101765  */
101766 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
101767 
101768 #define WDOG_WCR_WDW_MASK                        (0x80U)
101769 #define WDOG_WCR_WDW_SHIFT                       (7U)
101770 /*! WDW - WDW
101771  *  0b0..Continue WDOG timer operation (Default).
101772  *  0b1..Suspend WDOG timer operation.
101773  */
101774 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
101775 
101776 #define WDOG_WCR_WT_MASK                         (0xFF00U)
101777 #define WDOG_WCR_WT_SHIFT                        (8U)
101778 /*! WT - WT
101779  *  0b00000000..- 0.5 Seconds (Default).
101780  *  0b00000001..- 1.0 Seconds.
101781  *  0b00000010..- 1.5 Seconds.
101782  *  0b00000011..- 2.0 Seconds.
101783  *  0b11111111..- 128 Seconds.
101784  */
101785 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
101786 /*! @} */
101787 
101788 /*! @name WSR - Watchdog Service Register */
101789 /*! @{ */
101790 
101791 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
101792 #define WDOG_WSR_WSR_SHIFT                       (0U)
101793 /*! WSR - WSR
101794  *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
101795  *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
101796  */
101797 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
101798 /*! @} */
101799 
101800 /*! @name WRSR - Watchdog Reset Status Register */
101801 /*! @{ */
101802 
101803 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
101804 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
101805 /*! SFTW - SFTW
101806  *  0b0..Reset is not the result of a software reset.
101807  *  0b1..Reset is the result of a software reset.
101808  */
101809 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
101810 
101811 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
101812 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
101813 /*! TOUT - TOUT
101814  *  0b0..Reset is not the result of a WDOG timeout.
101815  *  0b1..Reset is the result of a WDOG timeout.
101816  */
101817 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
101818 
101819 #define WDOG_WRSR_POR_MASK                       (0x10U)
101820 #define WDOG_WRSR_POR_SHIFT                      (4U)
101821 /*! POR - POR
101822  *  0b0..Reset is not the result of a power on reset.
101823  *  0b1..Reset is the result of a power on reset.
101824  */
101825 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
101826 /*! @} */
101827 
101828 /*! @name WICR - Watchdog Interrupt Control Register */
101829 /*! @{ */
101830 
101831 #define WDOG_WICR_WICT_MASK                      (0xFFU)
101832 #define WDOG_WICR_WICT_SHIFT                     (0U)
101833 /*! WICT - WICT
101834  *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
101835  *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
101836  *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
101837  *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
101838  */
101839 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
101840 
101841 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
101842 #define WDOG_WICR_WTIS_SHIFT                     (14U)
101843 /*! WTIS - WTIS
101844  *  0b0..No interrupt has occurred (Default).
101845  *  0b1..Interrupt has occurred
101846  */
101847 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
101848 
101849 #define WDOG_WICR_WIE_MASK                       (0x8000U)
101850 #define WDOG_WICR_WIE_SHIFT                      (15U)
101851 /*! WIE - WIE
101852  *  0b0..Disable Interrupt (Default).
101853  *  0b1..Enable Interrupt.
101854  */
101855 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
101856 /*! @} */
101857 
101858 /*! @name WMCR - Watchdog Miscellaneous Control Register */
101859 /*! @{ */
101860 
101861 #define WDOG_WMCR_PDE_MASK                       (0x1U)
101862 #define WDOG_WMCR_PDE_SHIFT                      (0U)
101863 /*! PDE - PDE
101864  *  0b0..Power Down Counter of WDOG is disabled.
101865  *  0b1..Power Down Counter of WDOG is enabled (Default).
101866  */
101867 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
101868 /*! @} */
101869 
101870 
101871 /*!
101872  * @}
101873  */ /* end of group WDOG_Register_Masks */
101874 
101875 
101876 /* WDOG - Peripheral instance base addresses */
101877 /** Peripheral WDOG1 base address */
101878 #define WDOG1_BASE                               (0x40030000u)
101879 /** Peripheral WDOG1 base pointer */
101880 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
101881 /** Peripheral WDOG2 base address */
101882 #define WDOG2_BASE                               (0x40034000u)
101883 /** Peripheral WDOG2 base pointer */
101884 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
101885 /** Array initializer of WDOG peripheral base addresses */
101886 #define WDOG_BASE_ADDRS                          { 0u, WDOG1_BASE, WDOG2_BASE }
101887 /** Array initializer of WDOG peripheral base pointers */
101888 #define WDOG_BASE_PTRS                           { (WDOG_Type *)0u, WDOG1, WDOG2 }
101889 /** Interrupt vectors for the WDOG peripheral type */
101890 #define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
101891 
101892 /*!
101893  * @}
101894  */ /* end of group WDOG_Peripheral_Access_Layer */
101895 
101896 
101897 /* ----------------------------------------------------------------------------
101898    -- XBARA Peripheral Access Layer
101899    ---------------------------------------------------------------------------- */
101900 
101901 /*!
101902  * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
101903  * @{
101904  */
101905 
101906 /** XBARA - Register Layout Typedef */
101907 typedef struct {
101908   __IO uint16_t SEL0;                              /**< Crossbar A Select Register 0, offset: 0x0 */
101909   __IO uint16_t SEL1;                              /**< Crossbar A Select Register 1, offset: 0x2 */
101910   __IO uint16_t SEL2;                              /**< Crossbar A Select Register 2, offset: 0x4 */
101911   __IO uint16_t SEL3;                              /**< Crossbar A Select Register 3, offset: 0x6 */
101912   __IO uint16_t SEL4;                              /**< Crossbar A Select Register 4, offset: 0x8 */
101913   __IO uint16_t SEL5;                              /**< Crossbar A Select Register 5, offset: 0xA */
101914   __IO uint16_t SEL6;                              /**< Crossbar A Select Register 6, offset: 0xC */
101915   __IO uint16_t SEL7;                              /**< Crossbar A Select Register 7, offset: 0xE */
101916   __IO uint16_t SEL8;                              /**< Crossbar A Select Register 8, offset: 0x10 */
101917   __IO uint16_t SEL9;                              /**< Crossbar A Select Register 9, offset: 0x12 */
101918   __IO uint16_t SEL10;                             /**< Crossbar A Select Register 10, offset: 0x14 */
101919   __IO uint16_t SEL11;                             /**< Crossbar A Select Register 11, offset: 0x16 */
101920   __IO uint16_t SEL12;                             /**< Crossbar A Select Register 12, offset: 0x18 */
101921   __IO uint16_t SEL13;                             /**< Crossbar A Select Register 13, offset: 0x1A */
101922   __IO uint16_t SEL14;                             /**< Crossbar A Select Register 14, offset: 0x1C */
101923   __IO uint16_t SEL15;                             /**< Crossbar A Select Register 15, offset: 0x1E */
101924   __IO uint16_t SEL16;                             /**< Crossbar A Select Register 16, offset: 0x20 */
101925   __IO uint16_t SEL17;                             /**< Crossbar A Select Register 17, offset: 0x22 */
101926   __IO uint16_t SEL18;                             /**< Crossbar A Select Register 18, offset: 0x24 */
101927   __IO uint16_t SEL19;                             /**< Crossbar A Select Register 19, offset: 0x26 */
101928   __IO uint16_t SEL20;                             /**< Crossbar A Select Register 20, offset: 0x28 */
101929   __IO uint16_t SEL21;                             /**< Crossbar A Select Register 21, offset: 0x2A */
101930   __IO uint16_t SEL22;                             /**< Crossbar A Select Register 22, offset: 0x2C */
101931   __IO uint16_t SEL23;                             /**< Crossbar A Select Register 23, offset: 0x2E */
101932   __IO uint16_t SEL24;                             /**< Crossbar A Select Register 24, offset: 0x30 */
101933   __IO uint16_t SEL25;                             /**< Crossbar A Select Register 25, offset: 0x32 */
101934   __IO uint16_t SEL26;                             /**< Crossbar A Select Register 26, offset: 0x34 */
101935   __IO uint16_t SEL27;                             /**< Crossbar A Select Register 27, offset: 0x36 */
101936   __IO uint16_t SEL28;                             /**< Crossbar A Select Register 28, offset: 0x38 */
101937   __IO uint16_t SEL29;                             /**< Crossbar A Select Register 29, offset: 0x3A */
101938   __IO uint16_t SEL30;                             /**< Crossbar A Select Register 30, offset: 0x3C */
101939   __IO uint16_t SEL31;                             /**< Crossbar A Select Register 31, offset: 0x3E */
101940   __IO uint16_t SEL32;                             /**< Crossbar A Select Register 32, offset: 0x40 */
101941   __IO uint16_t SEL33;                             /**< Crossbar A Select Register 33, offset: 0x42 */
101942   __IO uint16_t SEL34;                             /**< Crossbar A Select Register 34, offset: 0x44 */
101943   __IO uint16_t SEL35;                             /**< Crossbar A Select Register 35, offset: 0x46 */
101944   __IO uint16_t SEL36;                             /**< Crossbar A Select Register 36, offset: 0x48 */
101945   __IO uint16_t SEL37;                             /**< Crossbar A Select Register 37, offset: 0x4A */
101946   __IO uint16_t SEL38;                             /**< Crossbar A Select Register 38, offset: 0x4C */
101947   __IO uint16_t SEL39;                             /**< Crossbar A Select Register 39, offset: 0x4E */
101948   __IO uint16_t SEL40;                             /**< Crossbar A Select Register 40, offset: 0x50 */
101949   __IO uint16_t SEL41;                             /**< Crossbar A Select Register 41, offset: 0x52 */
101950   __IO uint16_t SEL42;                             /**< Crossbar A Select Register 42, offset: 0x54 */
101951   __IO uint16_t SEL43;                             /**< Crossbar A Select Register 43, offset: 0x56 */
101952   __IO uint16_t SEL44;                             /**< Crossbar A Select Register 44, offset: 0x58 */
101953   __IO uint16_t SEL45;                             /**< Crossbar A Select Register 45, offset: 0x5A */
101954   __IO uint16_t SEL46;                             /**< Crossbar A Select Register 46, offset: 0x5C */
101955   __IO uint16_t SEL47;                             /**< Crossbar A Select Register 47, offset: 0x5E */
101956   __IO uint16_t SEL48;                             /**< Crossbar A Select Register 48, offset: 0x60 */
101957   __IO uint16_t SEL49;                             /**< Crossbar A Select Register 49, offset: 0x62 */
101958   __IO uint16_t SEL50;                             /**< Crossbar A Select Register 50, offset: 0x64 */
101959   __IO uint16_t SEL51;                             /**< Crossbar A Select Register 51, offset: 0x66 */
101960   __IO uint16_t SEL52;                             /**< Crossbar A Select Register 52, offset: 0x68 */
101961   __IO uint16_t SEL53;                             /**< Crossbar A Select Register 53, offset: 0x6A */
101962   __IO uint16_t SEL54;                             /**< Crossbar A Select Register 54, offset: 0x6C */
101963   __IO uint16_t SEL55;                             /**< Crossbar A Select Register 55, offset: 0x6E */
101964   __IO uint16_t SEL56;                             /**< Crossbar A Select Register 56, offset: 0x70 */
101965   __IO uint16_t SEL57;                             /**< Crossbar A Select Register 57, offset: 0x72 */
101966   __IO uint16_t SEL58;                             /**< Crossbar A Select Register 58, offset: 0x74 */
101967   __IO uint16_t SEL59;                             /**< Crossbar A Select Register 59, offset: 0x76 */
101968   __IO uint16_t SEL60;                             /**< Crossbar A Select Register 60, offset: 0x78 */
101969   __IO uint16_t SEL61;                             /**< Crossbar A Select Register 61, offset: 0x7A */
101970   __IO uint16_t SEL62;                             /**< Crossbar A Select Register 62, offset: 0x7C */
101971   __IO uint16_t SEL63;                             /**< Crossbar A Select Register 63, offset: 0x7E */
101972   __IO uint16_t SEL64;                             /**< Crossbar A Select Register 64, offset: 0x80 */
101973   __IO uint16_t SEL65;                             /**< Crossbar A Select Register 65, offset: 0x82 */
101974   __IO uint16_t SEL66;                             /**< Crossbar A Select Register 66, offset: 0x84 */
101975   __IO uint16_t SEL67;                             /**< Crossbar A Select Register 67, offset: 0x86 */
101976   __IO uint16_t SEL68;                             /**< Crossbar A Select Register 68, offset: 0x88 */
101977   __IO uint16_t SEL69;                             /**< Crossbar A Select Register 69, offset: 0x8A */
101978   __IO uint16_t SEL70;                             /**< Crossbar A Select Register 70, offset: 0x8C */
101979   __IO uint16_t SEL71;                             /**< Crossbar A Select Register 71, offset: 0x8E */
101980   __IO uint16_t SEL72;                             /**< Crossbar A Select Register 72, offset: 0x90 */
101981   __IO uint16_t SEL73;                             /**< Crossbar A Select Register 73, offset: 0x92 */
101982   __IO uint16_t SEL74;                             /**< Crossbar A Select Register 74, offset: 0x94 */
101983   __IO uint16_t SEL75;                             /**< Crossbar A Select Register 75, offset: 0x96 */
101984   __IO uint16_t SEL76;                             /**< Crossbar A Select Register 76, offset: 0x98 */
101985   __IO uint16_t SEL77;                             /**< Crossbar A Select Register 77, offset: 0x9A */
101986   __IO uint16_t SEL78;                             /**< Crossbar A Select Register 78, offset: 0x9C */
101987   __IO uint16_t SEL79;                             /**< Crossbar A Select Register 79, offset: 0x9E */
101988   __IO uint16_t SEL80;                             /**< Crossbar A Select Register 80, offset: 0xA0 */
101989   __IO uint16_t SEL81;                             /**< Crossbar A Select Register 81, offset: 0xA2 */
101990   __IO uint16_t SEL82;                             /**< Crossbar A Select Register 82, offset: 0xA4 */
101991   __IO uint16_t SEL83;                             /**< Crossbar A Select Register 83, offset: 0xA6 */
101992   __IO uint16_t SEL84;                             /**< Crossbar A Select Register 84, offset: 0xA8 */
101993   __IO uint16_t SEL85;                             /**< Crossbar A Select Register 85, offset: 0xAA */
101994   __IO uint16_t SEL86;                             /**< Crossbar A Select Register 86, offset: 0xAC */
101995   __IO uint16_t SEL87;                             /**< Crossbar A Select Register 87, offset: 0xAE */
101996   __IO uint16_t CTRL0;                             /**< Crossbar A Control Register 0, offset: 0xB0 */
101997   __IO uint16_t CTRL1;                             /**< Crossbar A Control Register 1, offset: 0xB2 */
101998 } XBARA_Type;
101999 
102000 /* ----------------------------------------------------------------------------
102001    -- XBARA Register Masks
102002    ---------------------------------------------------------------------------- */
102003 
102004 /*!
102005  * @addtogroup XBARA_Register_Masks XBARA Register Masks
102006  * @{
102007  */
102008 
102009 /*! @name SEL0 - Crossbar A Select Register 0 */
102010 /*! @{ */
102011 
102012 #define XBARA_SEL0_SEL0_MASK                     (0xFFU)
102013 #define XBARA_SEL0_SEL0_SHIFT                    (0U)
102014 #define XBARA_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
102015 
102016 #define XBARA_SEL0_SEL1_MASK                     (0xFF00U)
102017 #define XBARA_SEL0_SEL1_SHIFT                    (8U)
102018 #define XBARA_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
102019 /*! @} */
102020 
102021 /*! @name SEL1 - Crossbar A Select Register 1 */
102022 /*! @{ */
102023 
102024 #define XBARA_SEL1_SEL2_MASK                     (0xFFU)
102025 #define XBARA_SEL1_SEL2_SHIFT                    (0U)
102026 #define XBARA_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
102027 
102028 #define XBARA_SEL1_SEL3_MASK                     (0xFF00U)
102029 #define XBARA_SEL1_SEL3_SHIFT                    (8U)
102030 #define XBARA_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
102031 /*! @} */
102032 
102033 /*! @name SEL2 - Crossbar A Select Register 2 */
102034 /*! @{ */
102035 
102036 #define XBARA_SEL2_SEL4_MASK                     (0xFFU)
102037 #define XBARA_SEL2_SEL4_SHIFT                    (0U)
102038 #define XBARA_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
102039 
102040 #define XBARA_SEL2_SEL5_MASK                     (0xFF00U)
102041 #define XBARA_SEL2_SEL5_SHIFT                    (8U)
102042 #define XBARA_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
102043 /*! @} */
102044 
102045 /*! @name SEL3 - Crossbar A Select Register 3 */
102046 /*! @{ */
102047 
102048 #define XBARA_SEL3_SEL6_MASK                     (0xFFU)
102049 #define XBARA_SEL3_SEL6_SHIFT                    (0U)
102050 #define XBARA_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
102051 
102052 #define XBARA_SEL3_SEL7_MASK                     (0xFF00U)
102053 #define XBARA_SEL3_SEL7_SHIFT                    (8U)
102054 #define XBARA_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
102055 /*! @} */
102056 
102057 /*! @name SEL4 - Crossbar A Select Register 4 */
102058 /*! @{ */
102059 
102060 #define XBARA_SEL4_SEL8_MASK                     (0xFFU)
102061 #define XBARA_SEL4_SEL8_SHIFT                    (0U)
102062 #define XBARA_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
102063 
102064 #define XBARA_SEL4_SEL9_MASK                     (0xFF00U)
102065 #define XBARA_SEL4_SEL9_SHIFT                    (8U)
102066 #define XBARA_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
102067 /*! @} */
102068 
102069 /*! @name SEL5 - Crossbar A Select Register 5 */
102070 /*! @{ */
102071 
102072 #define XBARA_SEL5_SEL10_MASK                    (0xFFU)
102073 #define XBARA_SEL5_SEL10_SHIFT                   (0U)
102074 #define XBARA_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
102075 
102076 #define XBARA_SEL5_SEL11_MASK                    (0xFF00U)
102077 #define XBARA_SEL5_SEL11_SHIFT                   (8U)
102078 #define XBARA_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
102079 /*! @} */
102080 
102081 /*! @name SEL6 - Crossbar A Select Register 6 */
102082 /*! @{ */
102083 
102084 #define XBARA_SEL6_SEL12_MASK                    (0xFFU)
102085 #define XBARA_SEL6_SEL12_SHIFT                   (0U)
102086 #define XBARA_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
102087 
102088 #define XBARA_SEL6_SEL13_MASK                    (0xFF00U)
102089 #define XBARA_SEL6_SEL13_SHIFT                   (8U)
102090 #define XBARA_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
102091 /*! @} */
102092 
102093 /*! @name SEL7 - Crossbar A Select Register 7 */
102094 /*! @{ */
102095 
102096 #define XBARA_SEL7_SEL14_MASK                    (0xFFU)
102097 #define XBARA_SEL7_SEL14_SHIFT                   (0U)
102098 #define XBARA_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
102099 
102100 #define XBARA_SEL7_SEL15_MASK                    (0xFF00U)
102101 #define XBARA_SEL7_SEL15_SHIFT                   (8U)
102102 #define XBARA_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
102103 /*! @} */
102104 
102105 /*! @name SEL8 - Crossbar A Select Register 8 */
102106 /*! @{ */
102107 
102108 #define XBARA_SEL8_SEL16_MASK                    (0xFFU)
102109 #define XBARA_SEL8_SEL16_SHIFT                   (0U)
102110 #define XBARA_SEL8_SEL16(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
102111 
102112 #define XBARA_SEL8_SEL17_MASK                    (0xFF00U)
102113 #define XBARA_SEL8_SEL17_SHIFT                   (8U)
102114 #define XBARA_SEL8_SEL17(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
102115 /*! @} */
102116 
102117 /*! @name SEL9 - Crossbar A Select Register 9 */
102118 /*! @{ */
102119 
102120 #define XBARA_SEL9_SEL18_MASK                    (0xFFU)
102121 #define XBARA_SEL9_SEL18_SHIFT                   (0U)
102122 #define XBARA_SEL9_SEL18(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
102123 
102124 #define XBARA_SEL9_SEL19_MASK                    (0xFF00U)
102125 #define XBARA_SEL9_SEL19_SHIFT                   (8U)
102126 #define XBARA_SEL9_SEL19(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
102127 /*! @} */
102128 
102129 /*! @name SEL10 - Crossbar A Select Register 10 */
102130 /*! @{ */
102131 
102132 #define XBARA_SEL10_SEL20_MASK                   (0xFFU)
102133 #define XBARA_SEL10_SEL20_SHIFT                  (0U)
102134 #define XBARA_SEL10_SEL20(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
102135 
102136 #define XBARA_SEL10_SEL21_MASK                   (0xFF00U)
102137 #define XBARA_SEL10_SEL21_SHIFT                  (8U)
102138 #define XBARA_SEL10_SEL21(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
102139 /*! @} */
102140 
102141 /*! @name SEL11 - Crossbar A Select Register 11 */
102142 /*! @{ */
102143 
102144 #define XBARA_SEL11_SEL22_MASK                   (0xFFU)
102145 #define XBARA_SEL11_SEL22_SHIFT                  (0U)
102146 #define XBARA_SEL11_SEL22(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
102147 
102148 #define XBARA_SEL11_SEL23_MASK                   (0xFF00U)
102149 #define XBARA_SEL11_SEL23_SHIFT                  (8U)
102150 #define XBARA_SEL11_SEL23(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
102151 /*! @} */
102152 
102153 /*! @name SEL12 - Crossbar A Select Register 12 */
102154 /*! @{ */
102155 
102156 #define XBARA_SEL12_SEL24_MASK                   (0xFFU)
102157 #define XBARA_SEL12_SEL24_SHIFT                  (0U)
102158 #define XBARA_SEL12_SEL24(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
102159 
102160 #define XBARA_SEL12_SEL25_MASK                   (0xFF00U)
102161 #define XBARA_SEL12_SEL25_SHIFT                  (8U)
102162 #define XBARA_SEL12_SEL25(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
102163 /*! @} */
102164 
102165 /*! @name SEL13 - Crossbar A Select Register 13 */
102166 /*! @{ */
102167 
102168 #define XBARA_SEL13_SEL26_MASK                   (0xFFU)
102169 #define XBARA_SEL13_SEL26_SHIFT                  (0U)
102170 #define XBARA_SEL13_SEL26(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
102171 
102172 #define XBARA_SEL13_SEL27_MASK                   (0xFF00U)
102173 #define XBARA_SEL13_SEL27_SHIFT                  (8U)
102174 #define XBARA_SEL13_SEL27(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
102175 /*! @} */
102176 
102177 /*! @name SEL14 - Crossbar A Select Register 14 */
102178 /*! @{ */
102179 
102180 #define XBARA_SEL14_SEL28_MASK                   (0xFFU)
102181 #define XBARA_SEL14_SEL28_SHIFT                  (0U)
102182 #define XBARA_SEL14_SEL28(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
102183 
102184 #define XBARA_SEL14_SEL29_MASK                   (0xFF00U)
102185 #define XBARA_SEL14_SEL29_SHIFT                  (8U)
102186 #define XBARA_SEL14_SEL29(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
102187 /*! @} */
102188 
102189 /*! @name SEL15 - Crossbar A Select Register 15 */
102190 /*! @{ */
102191 
102192 #define XBARA_SEL15_SEL30_MASK                   (0xFFU)
102193 #define XBARA_SEL15_SEL30_SHIFT                  (0U)
102194 #define XBARA_SEL15_SEL30(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
102195 
102196 #define XBARA_SEL15_SEL31_MASK                   (0xFF00U)
102197 #define XBARA_SEL15_SEL31_SHIFT                  (8U)
102198 #define XBARA_SEL15_SEL31(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
102199 /*! @} */
102200 
102201 /*! @name SEL16 - Crossbar A Select Register 16 */
102202 /*! @{ */
102203 
102204 #define XBARA_SEL16_SEL32_MASK                   (0xFFU)
102205 #define XBARA_SEL16_SEL32_SHIFT                  (0U)
102206 #define XBARA_SEL16_SEL32(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
102207 
102208 #define XBARA_SEL16_SEL33_MASK                   (0xFF00U)
102209 #define XBARA_SEL16_SEL33_SHIFT                  (8U)
102210 #define XBARA_SEL16_SEL33(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
102211 /*! @} */
102212 
102213 /*! @name SEL17 - Crossbar A Select Register 17 */
102214 /*! @{ */
102215 
102216 #define XBARA_SEL17_SEL34_MASK                   (0xFFU)
102217 #define XBARA_SEL17_SEL34_SHIFT                  (0U)
102218 #define XBARA_SEL17_SEL34(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
102219 
102220 #define XBARA_SEL17_SEL35_MASK                   (0xFF00U)
102221 #define XBARA_SEL17_SEL35_SHIFT                  (8U)
102222 #define XBARA_SEL17_SEL35(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
102223 /*! @} */
102224 
102225 /*! @name SEL18 - Crossbar A Select Register 18 */
102226 /*! @{ */
102227 
102228 #define XBARA_SEL18_SEL36_MASK                   (0xFFU)
102229 #define XBARA_SEL18_SEL36_SHIFT                  (0U)
102230 #define XBARA_SEL18_SEL36(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
102231 
102232 #define XBARA_SEL18_SEL37_MASK                   (0xFF00U)
102233 #define XBARA_SEL18_SEL37_SHIFT                  (8U)
102234 #define XBARA_SEL18_SEL37(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
102235 /*! @} */
102236 
102237 /*! @name SEL19 - Crossbar A Select Register 19 */
102238 /*! @{ */
102239 
102240 #define XBARA_SEL19_SEL38_MASK                   (0xFFU)
102241 #define XBARA_SEL19_SEL38_SHIFT                  (0U)
102242 #define XBARA_SEL19_SEL38(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
102243 
102244 #define XBARA_SEL19_SEL39_MASK                   (0xFF00U)
102245 #define XBARA_SEL19_SEL39_SHIFT                  (8U)
102246 #define XBARA_SEL19_SEL39(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
102247 /*! @} */
102248 
102249 /*! @name SEL20 - Crossbar A Select Register 20 */
102250 /*! @{ */
102251 
102252 #define XBARA_SEL20_SEL40_MASK                   (0xFFU)
102253 #define XBARA_SEL20_SEL40_SHIFT                  (0U)
102254 #define XBARA_SEL20_SEL40(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
102255 
102256 #define XBARA_SEL20_SEL41_MASK                   (0xFF00U)
102257 #define XBARA_SEL20_SEL41_SHIFT                  (8U)
102258 #define XBARA_SEL20_SEL41(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
102259 /*! @} */
102260 
102261 /*! @name SEL21 - Crossbar A Select Register 21 */
102262 /*! @{ */
102263 
102264 #define XBARA_SEL21_SEL42_MASK                   (0xFFU)
102265 #define XBARA_SEL21_SEL42_SHIFT                  (0U)
102266 #define XBARA_SEL21_SEL42(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
102267 
102268 #define XBARA_SEL21_SEL43_MASK                   (0xFF00U)
102269 #define XBARA_SEL21_SEL43_SHIFT                  (8U)
102270 #define XBARA_SEL21_SEL43(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
102271 /*! @} */
102272 
102273 /*! @name SEL22 - Crossbar A Select Register 22 */
102274 /*! @{ */
102275 
102276 #define XBARA_SEL22_SEL44_MASK                   (0xFFU)
102277 #define XBARA_SEL22_SEL44_SHIFT                  (0U)
102278 #define XBARA_SEL22_SEL44(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
102279 
102280 #define XBARA_SEL22_SEL45_MASK                   (0xFF00U)
102281 #define XBARA_SEL22_SEL45_SHIFT                  (8U)
102282 #define XBARA_SEL22_SEL45(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
102283 /*! @} */
102284 
102285 /*! @name SEL23 - Crossbar A Select Register 23 */
102286 /*! @{ */
102287 
102288 #define XBARA_SEL23_SEL46_MASK                   (0xFFU)
102289 #define XBARA_SEL23_SEL46_SHIFT                  (0U)
102290 #define XBARA_SEL23_SEL46(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
102291 
102292 #define XBARA_SEL23_SEL47_MASK                   (0xFF00U)
102293 #define XBARA_SEL23_SEL47_SHIFT                  (8U)
102294 #define XBARA_SEL23_SEL47(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
102295 /*! @} */
102296 
102297 /*! @name SEL24 - Crossbar A Select Register 24 */
102298 /*! @{ */
102299 
102300 #define XBARA_SEL24_SEL48_MASK                   (0xFFU)
102301 #define XBARA_SEL24_SEL48_SHIFT                  (0U)
102302 #define XBARA_SEL24_SEL48(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
102303 
102304 #define XBARA_SEL24_SEL49_MASK                   (0xFF00U)
102305 #define XBARA_SEL24_SEL49_SHIFT                  (8U)
102306 #define XBARA_SEL24_SEL49(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
102307 /*! @} */
102308 
102309 /*! @name SEL25 - Crossbar A Select Register 25 */
102310 /*! @{ */
102311 
102312 #define XBARA_SEL25_SEL50_MASK                   (0xFFU)
102313 #define XBARA_SEL25_SEL50_SHIFT                  (0U)
102314 #define XBARA_SEL25_SEL50(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
102315 
102316 #define XBARA_SEL25_SEL51_MASK                   (0xFF00U)
102317 #define XBARA_SEL25_SEL51_SHIFT                  (8U)
102318 #define XBARA_SEL25_SEL51(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
102319 /*! @} */
102320 
102321 /*! @name SEL26 - Crossbar A Select Register 26 */
102322 /*! @{ */
102323 
102324 #define XBARA_SEL26_SEL52_MASK                   (0xFFU)
102325 #define XBARA_SEL26_SEL52_SHIFT                  (0U)
102326 #define XBARA_SEL26_SEL52(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
102327 
102328 #define XBARA_SEL26_SEL53_MASK                   (0xFF00U)
102329 #define XBARA_SEL26_SEL53_SHIFT                  (8U)
102330 #define XBARA_SEL26_SEL53(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
102331 /*! @} */
102332 
102333 /*! @name SEL27 - Crossbar A Select Register 27 */
102334 /*! @{ */
102335 
102336 #define XBARA_SEL27_SEL54_MASK                   (0xFFU)
102337 #define XBARA_SEL27_SEL54_SHIFT                  (0U)
102338 #define XBARA_SEL27_SEL54(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
102339 
102340 #define XBARA_SEL27_SEL55_MASK                   (0xFF00U)
102341 #define XBARA_SEL27_SEL55_SHIFT                  (8U)
102342 #define XBARA_SEL27_SEL55(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
102343 /*! @} */
102344 
102345 /*! @name SEL28 - Crossbar A Select Register 28 */
102346 /*! @{ */
102347 
102348 #define XBARA_SEL28_SEL56_MASK                   (0xFFU)
102349 #define XBARA_SEL28_SEL56_SHIFT                  (0U)
102350 #define XBARA_SEL28_SEL56(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
102351 
102352 #define XBARA_SEL28_SEL57_MASK                   (0xFF00U)
102353 #define XBARA_SEL28_SEL57_SHIFT                  (8U)
102354 #define XBARA_SEL28_SEL57(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
102355 /*! @} */
102356 
102357 /*! @name SEL29 - Crossbar A Select Register 29 */
102358 /*! @{ */
102359 
102360 #define XBARA_SEL29_SEL58_MASK                   (0xFFU)
102361 #define XBARA_SEL29_SEL58_SHIFT                  (0U)
102362 #define XBARA_SEL29_SEL58(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
102363 
102364 #define XBARA_SEL29_SEL59_MASK                   (0xFF00U)
102365 #define XBARA_SEL29_SEL59_SHIFT                  (8U)
102366 #define XBARA_SEL29_SEL59(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
102367 /*! @} */
102368 
102369 /*! @name SEL30 - Crossbar A Select Register 30 */
102370 /*! @{ */
102371 
102372 #define XBARA_SEL30_SEL60_MASK                   (0xFFU)
102373 #define XBARA_SEL30_SEL60_SHIFT                  (0U)
102374 #define XBARA_SEL30_SEL60(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
102375 
102376 #define XBARA_SEL30_SEL61_MASK                   (0xFF00U)
102377 #define XBARA_SEL30_SEL61_SHIFT                  (8U)
102378 #define XBARA_SEL30_SEL61(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
102379 /*! @} */
102380 
102381 /*! @name SEL31 - Crossbar A Select Register 31 */
102382 /*! @{ */
102383 
102384 #define XBARA_SEL31_SEL62_MASK                   (0xFFU)
102385 #define XBARA_SEL31_SEL62_SHIFT                  (0U)
102386 #define XBARA_SEL31_SEL62(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
102387 
102388 #define XBARA_SEL31_SEL63_MASK                   (0xFF00U)
102389 #define XBARA_SEL31_SEL63_SHIFT                  (8U)
102390 #define XBARA_SEL31_SEL63(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
102391 /*! @} */
102392 
102393 /*! @name SEL32 - Crossbar A Select Register 32 */
102394 /*! @{ */
102395 
102396 #define XBARA_SEL32_SEL64_MASK                   (0xFFU)
102397 #define XBARA_SEL32_SEL64_SHIFT                  (0U)
102398 #define XBARA_SEL32_SEL64(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
102399 
102400 #define XBARA_SEL32_SEL65_MASK                   (0xFF00U)
102401 #define XBARA_SEL32_SEL65_SHIFT                  (8U)
102402 #define XBARA_SEL32_SEL65(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
102403 /*! @} */
102404 
102405 /*! @name SEL33 - Crossbar A Select Register 33 */
102406 /*! @{ */
102407 
102408 #define XBARA_SEL33_SEL66_MASK                   (0xFFU)
102409 #define XBARA_SEL33_SEL66_SHIFT                  (0U)
102410 #define XBARA_SEL33_SEL66(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
102411 
102412 #define XBARA_SEL33_SEL67_MASK                   (0xFF00U)
102413 #define XBARA_SEL33_SEL67_SHIFT                  (8U)
102414 #define XBARA_SEL33_SEL67(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
102415 /*! @} */
102416 
102417 /*! @name SEL34 - Crossbar A Select Register 34 */
102418 /*! @{ */
102419 
102420 #define XBARA_SEL34_SEL68_MASK                   (0xFFU)
102421 #define XBARA_SEL34_SEL68_SHIFT                  (0U)
102422 #define XBARA_SEL34_SEL68(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
102423 
102424 #define XBARA_SEL34_SEL69_MASK                   (0xFF00U)
102425 #define XBARA_SEL34_SEL69_SHIFT                  (8U)
102426 #define XBARA_SEL34_SEL69(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
102427 /*! @} */
102428 
102429 /*! @name SEL35 - Crossbar A Select Register 35 */
102430 /*! @{ */
102431 
102432 #define XBARA_SEL35_SEL70_MASK                   (0xFFU)
102433 #define XBARA_SEL35_SEL70_SHIFT                  (0U)
102434 #define XBARA_SEL35_SEL70(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
102435 
102436 #define XBARA_SEL35_SEL71_MASK                   (0xFF00U)
102437 #define XBARA_SEL35_SEL71_SHIFT                  (8U)
102438 #define XBARA_SEL35_SEL71(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
102439 /*! @} */
102440 
102441 /*! @name SEL36 - Crossbar A Select Register 36 */
102442 /*! @{ */
102443 
102444 #define XBARA_SEL36_SEL72_MASK                   (0xFFU)
102445 #define XBARA_SEL36_SEL72_SHIFT                  (0U)
102446 #define XBARA_SEL36_SEL72(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
102447 
102448 #define XBARA_SEL36_SEL73_MASK                   (0xFF00U)
102449 #define XBARA_SEL36_SEL73_SHIFT                  (8U)
102450 #define XBARA_SEL36_SEL73(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
102451 /*! @} */
102452 
102453 /*! @name SEL37 - Crossbar A Select Register 37 */
102454 /*! @{ */
102455 
102456 #define XBARA_SEL37_SEL74_MASK                   (0xFFU)
102457 #define XBARA_SEL37_SEL74_SHIFT                  (0U)
102458 #define XBARA_SEL37_SEL74(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
102459 
102460 #define XBARA_SEL37_SEL75_MASK                   (0xFF00U)
102461 #define XBARA_SEL37_SEL75_SHIFT                  (8U)
102462 #define XBARA_SEL37_SEL75(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
102463 /*! @} */
102464 
102465 /*! @name SEL38 - Crossbar A Select Register 38 */
102466 /*! @{ */
102467 
102468 #define XBARA_SEL38_SEL76_MASK                   (0xFFU)
102469 #define XBARA_SEL38_SEL76_SHIFT                  (0U)
102470 #define XBARA_SEL38_SEL76(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
102471 
102472 #define XBARA_SEL38_SEL77_MASK                   (0xFF00U)
102473 #define XBARA_SEL38_SEL77_SHIFT                  (8U)
102474 #define XBARA_SEL38_SEL77(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
102475 /*! @} */
102476 
102477 /*! @name SEL39 - Crossbar A Select Register 39 */
102478 /*! @{ */
102479 
102480 #define XBARA_SEL39_SEL78_MASK                   (0xFFU)
102481 #define XBARA_SEL39_SEL78_SHIFT                  (0U)
102482 #define XBARA_SEL39_SEL78(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
102483 
102484 #define XBARA_SEL39_SEL79_MASK                   (0xFF00U)
102485 #define XBARA_SEL39_SEL79_SHIFT                  (8U)
102486 #define XBARA_SEL39_SEL79(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
102487 /*! @} */
102488 
102489 /*! @name SEL40 - Crossbar A Select Register 40 */
102490 /*! @{ */
102491 
102492 #define XBARA_SEL40_SEL80_MASK                   (0xFFU)
102493 #define XBARA_SEL40_SEL80_SHIFT                  (0U)
102494 #define XBARA_SEL40_SEL80(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
102495 
102496 #define XBARA_SEL40_SEL81_MASK                   (0xFF00U)
102497 #define XBARA_SEL40_SEL81_SHIFT                  (8U)
102498 #define XBARA_SEL40_SEL81(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
102499 /*! @} */
102500 
102501 /*! @name SEL41 - Crossbar A Select Register 41 */
102502 /*! @{ */
102503 
102504 #define XBARA_SEL41_SEL82_MASK                   (0xFFU)
102505 #define XBARA_SEL41_SEL82_SHIFT                  (0U)
102506 #define XBARA_SEL41_SEL82(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
102507 
102508 #define XBARA_SEL41_SEL83_MASK                   (0xFF00U)
102509 #define XBARA_SEL41_SEL83_SHIFT                  (8U)
102510 #define XBARA_SEL41_SEL83(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
102511 /*! @} */
102512 
102513 /*! @name SEL42 - Crossbar A Select Register 42 */
102514 /*! @{ */
102515 
102516 #define XBARA_SEL42_SEL84_MASK                   (0xFFU)
102517 #define XBARA_SEL42_SEL84_SHIFT                  (0U)
102518 #define XBARA_SEL42_SEL84(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
102519 
102520 #define XBARA_SEL42_SEL85_MASK                   (0xFF00U)
102521 #define XBARA_SEL42_SEL85_SHIFT                  (8U)
102522 #define XBARA_SEL42_SEL85(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
102523 /*! @} */
102524 
102525 /*! @name SEL43 - Crossbar A Select Register 43 */
102526 /*! @{ */
102527 
102528 #define XBARA_SEL43_SEL86_MASK                   (0xFFU)
102529 #define XBARA_SEL43_SEL86_SHIFT                  (0U)
102530 #define XBARA_SEL43_SEL86(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
102531 
102532 #define XBARA_SEL43_SEL87_MASK                   (0xFF00U)
102533 #define XBARA_SEL43_SEL87_SHIFT                  (8U)
102534 #define XBARA_SEL43_SEL87(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
102535 /*! @} */
102536 
102537 /*! @name SEL44 - Crossbar A Select Register 44 */
102538 /*! @{ */
102539 
102540 #define XBARA_SEL44_SEL88_MASK                   (0xFFU)
102541 #define XBARA_SEL44_SEL88_SHIFT                  (0U)
102542 #define XBARA_SEL44_SEL88(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
102543 
102544 #define XBARA_SEL44_SEL89_MASK                   (0xFF00U)
102545 #define XBARA_SEL44_SEL89_SHIFT                  (8U)
102546 #define XBARA_SEL44_SEL89(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
102547 /*! @} */
102548 
102549 /*! @name SEL45 - Crossbar A Select Register 45 */
102550 /*! @{ */
102551 
102552 #define XBARA_SEL45_SEL90_MASK                   (0xFFU)
102553 #define XBARA_SEL45_SEL90_SHIFT                  (0U)
102554 #define XBARA_SEL45_SEL90(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
102555 
102556 #define XBARA_SEL45_SEL91_MASK                   (0xFF00U)
102557 #define XBARA_SEL45_SEL91_SHIFT                  (8U)
102558 #define XBARA_SEL45_SEL91(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
102559 /*! @} */
102560 
102561 /*! @name SEL46 - Crossbar A Select Register 46 */
102562 /*! @{ */
102563 
102564 #define XBARA_SEL46_SEL92_MASK                   (0xFFU)
102565 #define XBARA_SEL46_SEL92_SHIFT                  (0U)
102566 #define XBARA_SEL46_SEL92(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
102567 
102568 #define XBARA_SEL46_SEL93_MASK                   (0xFF00U)
102569 #define XBARA_SEL46_SEL93_SHIFT                  (8U)
102570 #define XBARA_SEL46_SEL93(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
102571 /*! @} */
102572 
102573 /*! @name SEL47 - Crossbar A Select Register 47 */
102574 /*! @{ */
102575 
102576 #define XBARA_SEL47_SEL94_MASK                   (0xFFU)
102577 #define XBARA_SEL47_SEL94_SHIFT                  (0U)
102578 #define XBARA_SEL47_SEL94(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
102579 
102580 #define XBARA_SEL47_SEL95_MASK                   (0xFF00U)
102581 #define XBARA_SEL47_SEL95_SHIFT                  (8U)
102582 #define XBARA_SEL47_SEL95(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
102583 /*! @} */
102584 
102585 /*! @name SEL48 - Crossbar A Select Register 48 */
102586 /*! @{ */
102587 
102588 #define XBARA_SEL48_SEL96_MASK                   (0xFFU)
102589 #define XBARA_SEL48_SEL96_SHIFT                  (0U)
102590 #define XBARA_SEL48_SEL96(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
102591 
102592 #define XBARA_SEL48_SEL97_MASK                   (0xFF00U)
102593 #define XBARA_SEL48_SEL97_SHIFT                  (8U)
102594 #define XBARA_SEL48_SEL97(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
102595 /*! @} */
102596 
102597 /*! @name SEL49 - Crossbar A Select Register 49 */
102598 /*! @{ */
102599 
102600 #define XBARA_SEL49_SEL98_MASK                   (0xFFU)
102601 #define XBARA_SEL49_SEL98_SHIFT                  (0U)
102602 #define XBARA_SEL49_SEL98(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
102603 
102604 #define XBARA_SEL49_SEL99_MASK                   (0xFF00U)
102605 #define XBARA_SEL49_SEL99_SHIFT                  (8U)
102606 #define XBARA_SEL49_SEL99(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
102607 /*! @} */
102608 
102609 /*! @name SEL50 - Crossbar A Select Register 50 */
102610 /*! @{ */
102611 
102612 #define XBARA_SEL50_SEL100_MASK                  (0xFFU)
102613 #define XBARA_SEL50_SEL100_SHIFT                 (0U)
102614 #define XBARA_SEL50_SEL100(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
102615 
102616 #define XBARA_SEL50_SEL101_MASK                  (0xFF00U)
102617 #define XBARA_SEL50_SEL101_SHIFT                 (8U)
102618 #define XBARA_SEL50_SEL101(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
102619 /*! @} */
102620 
102621 /*! @name SEL51 - Crossbar A Select Register 51 */
102622 /*! @{ */
102623 
102624 #define XBARA_SEL51_SEL102_MASK                  (0xFFU)
102625 #define XBARA_SEL51_SEL102_SHIFT                 (0U)
102626 #define XBARA_SEL51_SEL102(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
102627 
102628 #define XBARA_SEL51_SEL103_MASK                  (0xFF00U)
102629 #define XBARA_SEL51_SEL103_SHIFT                 (8U)
102630 #define XBARA_SEL51_SEL103(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
102631 /*! @} */
102632 
102633 /*! @name SEL52 - Crossbar A Select Register 52 */
102634 /*! @{ */
102635 
102636 #define XBARA_SEL52_SEL104_MASK                  (0xFFU)
102637 #define XBARA_SEL52_SEL104_SHIFT                 (0U)
102638 #define XBARA_SEL52_SEL104(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
102639 
102640 #define XBARA_SEL52_SEL105_MASK                  (0xFF00U)
102641 #define XBARA_SEL52_SEL105_SHIFT                 (8U)
102642 #define XBARA_SEL52_SEL105(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
102643 /*! @} */
102644 
102645 /*! @name SEL53 - Crossbar A Select Register 53 */
102646 /*! @{ */
102647 
102648 #define XBARA_SEL53_SEL106_MASK                  (0xFFU)
102649 #define XBARA_SEL53_SEL106_SHIFT                 (0U)
102650 #define XBARA_SEL53_SEL106(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
102651 
102652 #define XBARA_SEL53_SEL107_MASK                  (0xFF00U)
102653 #define XBARA_SEL53_SEL107_SHIFT                 (8U)
102654 #define XBARA_SEL53_SEL107(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
102655 /*! @} */
102656 
102657 /*! @name SEL54 - Crossbar A Select Register 54 */
102658 /*! @{ */
102659 
102660 #define XBARA_SEL54_SEL108_MASK                  (0xFFU)
102661 #define XBARA_SEL54_SEL108_SHIFT                 (0U)
102662 #define XBARA_SEL54_SEL108(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
102663 
102664 #define XBARA_SEL54_SEL109_MASK                  (0xFF00U)
102665 #define XBARA_SEL54_SEL109_SHIFT                 (8U)
102666 #define XBARA_SEL54_SEL109(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
102667 /*! @} */
102668 
102669 /*! @name SEL55 - Crossbar A Select Register 55 */
102670 /*! @{ */
102671 
102672 #define XBARA_SEL55_SEL110_MASK                  (0xFFU)
102673 #define XBARA_SEL55_SEL110_SHIFT                 (0U)
102674 #define XBARA_SEL55_SEL110(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
102675 
102676 #define XBARA_SEL55_SEL111_MASK                  (0xFF00U)
102677 #define XBARA_SEL55_SEL111_SHIFT                 (8U)
102678 #define XBARA_SEL55_SEL111(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
102679 /*! @} */
102680 
102681 /*! @name SEL56 - Crossbar A Select Register 56 */
102682 /*! @{ */
102683 
102684 #define XBARA_SEL56_SEL112_MASK                  (0xFFU)
102685 #define XBARA_SEL56_SEL112_SHIFT                 (0U)
102686 #define XBARA_SEL56_SEL112(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
102687 
102688 #define XBARA_SEL56_SEL113_MASK                  (0xFF00U)
102689 #define XBARA_SEL56_SEL113_SHIFT                 (8U)
102690 #define XBARA_SEL56_SEL113(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
102691 /*! @} */
102692 
102693 /*! @name SEL57 - Crossbar A Select Register 57 */
102694 /*! @{ */
102695 
102696 #define XBARA_SEL57_SEL114_MASK                  (0xFFU)
102697 #define XBARA_SEL57_SEL114_SHIFT                 (0U)
102698 #define XBARA_SEL57_SEL114(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
102699 
102700 #define XBARA_SEL57_SEL115_MASK                  (0xFF00U)
102701 #define XBARA_SEL57_SEL115_SHIFT                 (8U)
102702 #define XBARA_SEL57_SEL115(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
102703 /*! @} */
102704 
102705 /*! @name SEL58 - Crossbar A Select Register 58 */
102706 /*! @{ */
102707 
102708 #define XBARA_SEL58_SEL116_MASK                  (0xFFU)
102709 #define XBARA_SEL58_SEL116_SHIFT                 (0U)
102710 #define XBARA_SEL58_SEL116(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
102711 
102712 #define XBARA_SEL58_SEL117_MASK                  (0xFF00U)
102713 #define XBARA_SEL58_SEL117_SHIFT                 (8U)
102714 #define XBARA_SEL58_SEL117(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
102715 /*! @} */
102716 
102717 /*! @name SEL59 - Crossbar A Select Register 59 */
102718 /*! @{ */
102719 
102720 #define XBARA_SEL59_SEL118_MASK                  (0xFFU)
102721 #define XBARA_SEL59_SEL118_SHIFT                 (0U)
102722 #define XBARA_SEL59_SEL118(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
102723 
102724 #define XBARA_SEL59_SEL119_MASK                  (0xFF00U)
102725 #define XBARA_SEL59_SEL119_SHIFT                 (8U)
102726 #define XBARA_SEL59_SEL119(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
102727 /*! @} */
102728 
102729 /*! @name SEL60 - Crossbar A Select Register 60 */
102730 /*! @{ */
102731 
102732 #define XBARA_SEL60_SEL120_MASK                  (0xFFU)
102733 #define XBARA_SEL60_SEL120_SHIFT                 (0U)
102734 #define XBARA_SEL60_SEL120(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
102735 
102736 #define XBARA_SEL60_SEL121_MASK                  (0xFF00U)
102737 #define XBARA_SEL60_SEL121_SHIFT                 (8U)
102738 #define XBARA_SEL60_SEL121(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
102739 /*! @} */
102740 
102741 /*! @name SEL61 - Crossbar A Select Register 61 */
102742 /*! @{ */
102743 
102744 #define XBARA_SEL61_SEL122_MASK                  (0xFFU)
102745 #define XBARA_SEL61_SEL122_SHIFT                 (0U)
102746 #define XBARA_SEL61_SEL122(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
102747 
102748 #define XBARA_SEL61_SEL123_MASK                  (0xFF00U)
102749 #define XBARA_SEL61_SEL123_SHIFT                 (8U)
102750 #define XBARA_SEL61_SEL123(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
102751 /*! @} */
102752 
102753 /*! @name SEL62 - Crossbar A Select Register 62 */
102754 /*! @{ */
102755 
102756 #define XBARA_SEL62_SEL124_MASK                  (0xFFU)
102757 #define XBARA_SEL62_SEL124_SHIFT                 (0U)
102758 #define XBARA_SEL62_SEL124(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
102759 
102760 #define XBARA_SEL62_SEL125_MASK                  (0xFF00U)
102761 #define XBARA_SEL62_SEL125_SHIFT                 (8U)
102762 #define XBARA_SEL62_SEL125(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
102763 /*! @} */
102764 
102765 /*! @name SEL63 - Crossbar A Select Register 63 */
102766 /*! @{ */
102767 
102768 #define XBARA_SEL63_SEL126_MASK                  (0xFFU)
102769 #define XBARA_SEL63_SEL126_SHIFT                 (0U)
102770 #define XBARA_SEL63_SEL126(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
102771 
102772 #define XBARA_SEL63_SEL127_MASK                  (0xFF00U)
102773 #define XBARA_SEL63_SEL127_SHIFT                 (8U)
102774 #define XBARA_SEL63_SEL127(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
102775 /*! @} */
102776 
102777 /*! @name SEL64 - Crossbar A Select Register 64 */
102778 /*! @{ */
102779 
102780 #define XBARA_SEL64_SEL128_MASK                  (0xFFU)
102781 #define XBARA_SEL64_SEL128_SHIFT                 (0U)
102782 #define XBARA_SEL64_SEL128(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
102783 
102784 #define XBARA_SEL64_SEL129_MASK                  (0xFF00U)
102785 #define XBARA_SEL64_SEL129_SHIFT                 (8U)
102786 #define XBARA_SEL64_SEL129(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
102787 /*! @} */
102788 
102789 /*! @name SEL65 - Crossbar A Select Register 65 */
102790 /*! @{ */
102791 
102792 #define XBARA_SEL65_SEL130_MASK                  (0xFFU)
102793 #define XBARA_SEL65_SEL130_SHIFT                 (0U)
102794 #define XBARA_SEL65_SEL130(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
102795 
102796 #define XBARA_SEL65_SEL131_MASK                  (0xFF00U)
102797 #define XBARA_SEL65_SEL131_SHIFT                 (8U)
102798 #define XBARA_SEL65_SEL131(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
102799 /*! @} */
102800 
102801 /*! @name SEL66 - Crossbar A Select Register 66 */
102802 /*! @{ */
102803 
102804 #define XBARA_SEL66_SEL132_MASK                  (0xFFU)
102805 #define XBARA_SEL66_SEL132_SHIFT                 (0U)
102806 #define XBARA_SEL66_SEL132(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)
102807 
102808 #define XBARA_SEL66_SEL133_MASK                  (0xFF00U)
102809 #define XBARA_SEL66_SEL133_SHIFT                 (8U)
102810 #define XBARA_SEL66_SEL133(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)
102811 /*! @} */
102812 
102813 /*! @name SEL67 - Crossbar A Select Register 67 */
102814 /*! @{ */
102815 
102816 #define XBARA_SEL67_SEL134_MASK                  (0xFFU)
102817 #define XBARA_SEL67_SEL134_SHIFT                 (0U)
102818 #define XBARA_SEL67_SEL134(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)
102819 
102820 #define XBARA_SEL67_SEL135_MASK                  (0xFF00U)
102821 #define XBARA_SEL67_SEL135_SHIFT                 (8U)
102822 #define XBARA_SEL67_SEL135(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)
102823 /*! @} */
102824 
102825 /*! @name SEL68 - Crossbar A Select Register 68 */
102826 /*! @{ */
102827 
102828 #define XBARA_SEL68_SEL136_MASK                  (0xFFU)
102829 #define XBARA_SEL68_SEL136_SHIFT                 (0U)
102830 #define XBARA_SEL68_SEL136(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)
102831 
102832 #define XBARA_SEL68_SEL137_MASK                  (0xFF00U)
102833 #define XBARA_SEL68_SEL137_SHIFT                 (8U)
102834 #define XBARA_SEL68_SEL137(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)
102835 /*! @} */
102836 
102837 /*! @name SEL69 - Crossbar A Select Register 69 */
102838 /*! @{ */
102839 
102840 #define XBARA_SEL69_SEL138_MASK                  (0xFFU)
102841 #define XBARA_SEL69_SEL138_SHIFT                 (0U)
102842 #define XBARA_SEL69_SEL138(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)
102843 
102844 #define XBARA_SEL69_SEL139_MASK                  (0xFF00U)
102845 #define XBARA_SEL69_SEL139_SHIFT                 (8U)
102846 #define XBARA_SEL69_SEL139(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)
102847 /*! @} */
102848 
102849 /*! @name SEL70 - Crossbar A Select Register 70 */
102850 /*! @{ */
102851 
102852 #define XBARA_SEL70_SEL140_MASK                  (0xFFU)
102853 #define XBARA_SEL70_SEL140_SHIFT                 (0U)
102854 #define XBARA_SEL70_SEL140(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)
102855 
102856 #define XBARA_SEL70_SEL141_MASK                  (0xFF00U)
102857 #define XBARA_SEL70_SEL141_SHIFT                 (8U)
102858 #define XBARA_SEL70_SEL141(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)
102859 /*! @} */
102860 
102861 /*! @name SEL71 - Crossbar A Select Register 71 */
102862 /*! @{ */
102863 
102864 #define XBARA_SEL71_SEL142_MASK                  (0xFFU)
102865 #define XBARA_SEL71_SEL142_SHIFT                 (0U)
102866 #define XBARA_SEL71_SEL142(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)
102867 
102868 #define XBARA_SEL71_SEL143_MASK                  (0xFF00U)
102869 #define XBARA_SEL71_SEL143_SHIFT                 (8U)
102870 #define XBARA_SEL71_SEL143(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)
102871 /*! @} */
102872 
102873 /*! @name SEL72 - Crossbar A Select Register 72 */
102874 /*! @{ */
102875 
102876 #define XBARA_SEL72_SEL144_MASK                  (0xFFU)
102877 #define XBARA_SEL72_SEL144_SHIFT                 (0U)
102878 #define XBARA_SEL72_SEL144(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)
102879 
102880 #define XBARA_SEL72_SEL145_MASK                  (0xFF00U)
102881 #define XBARA_SEL72_SEL145_SHIFT                 (8U)
102882 #define XBARA_SEL72_SEL145(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)
102883 /*! @} */
102884 
102885 /*! @name SEL73 - Crossbar A Select Register 73 */
102886 /*! @{ */
102887 
102888 #define XBARA_SEL73_SEL146_MASK                  (0xFFU)
102889 #define XBARA_SEL73_SEL146_SHIFT                 (0U)
102890 #define XBARA_SEL73_SEL146(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)
102891 
102892 #define XBARA_SEL73_SEL147_MASK                  (0xFF00U)
102893 #define XBARA_SEL73_SEL147_SHIFT                 (8U)
102894 #define XBARA_SEL73_SEL147(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)
102895 /*! @} */
102896 
102897 /*! @name SEL74 - Crossbar A Select Register 74 */
102898 /*! @{ */
102899 
102900 #define XBARA_SEL74_SEL148_MASK                  (0xFFU)
102901 #define XBARA_SEL74_SEL148_SHIFT                 (0U)
102902 #define XBARA_SEL74_SEL148(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)
102903 
102904 #define XBARA_SEL74_SEL149_MASK                  (0xFF00U)
102905 #define XBARA_SEL74_SEL149_SHIFT                 (8U)
102906 #define XBARA_SEL74_SEL149(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)
102907 /*! @} */
102908 
102909 /*! @name SEL75 - Crossbar A Select Register 75 */
102910 /*! @{ */
102911 
102912 #define XBARA_SEL75_SEL150_MASK                  (0xFFU)
102913 #define XBARA_SEL75_SEL150_SHIFT                 (0U)
102914 #define XBARA_SEL75_SEL150(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)
102915 
102916 #define XBARA_SEL75_SEL151_MASK                  (0xFF00U)
102917 #define XBARA_SEL75_SEL151_SHIFT                 (8U)
102918 #define XBARA_SEL75_SEL151(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)
102919 /*! @} */
102920 
102921 /*! @name SEL76 - Crossbar A Select Register 76 */
102922 /*! @{ */
102923 
102924 #define XBARA_SEL76_SEL152_MASK                  (0xFFU)
102925 #define XBARA_SEL76_SEL152_SHIFT                 (0U)
102926 #define XBARA_SEL76_SEL152(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)
102927 
102928 #define XBARA_SEL76_SEL153_MASK                  (0xFF00U)
102929 #define XBARA_SEL76_SEL153_SHIFT                 (8U)
102930 #define XBARA_SEL76_SEL153(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)
102931 /*! @} */
102932 
102933 /*! @name SEL77 - Crossbar A Select Register 77 */
102934 /*! @{ */
102935 
102936 #define XBARA_SEL77_SEL154_MASK                  (0xFFU)
102937 #define XBARA_SEL77_SEL154_SHIFT                 (0U)
102938 #define XBARA_SEL77_SEL154(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)
102939 
102940 #define XBARA_SEL77_SEL155_MASK                  (0xFF00U)
102941 #define XBARA_SEL77_SEL155_SHIFT                 (8U)
102942 #define XBARA_SEL77_SEL155(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)
102943 /*! @} */
102944 
102945 /*! @name SEL78 - Crossbar A Select Register 78 */
102946 /*! @{ */
102947 
102948 #define XBARA_SEL78_SEL156_MASK                  (0xFFU)
102949 #define XBARA_SEL78_SEL156_SHIFT                 (0U)
102950 #define XBARA_SEL78_SEL156(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)
102951 
102952 #define XBARA_SEL78_SEL157_MASK                  (0xFF00U)
102953 #define XBARA_SEL78_SEL157_SHIFT                 (8U)
102954 #define XBARA_SEL78_SEL157(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)
102955 /*! @} */
102956 
102957 /*! @name SEL79 - Crossbar A Select Register 79 */
102958 /*! @{ */
102959 
102960 #define XBARA_SEL79_SEL158_MASK                  (0xFFU)
102961 #define XBARA_SEL79_SEL158_SHIFT                 (0U)
102962 #define XBARA_SEL79_SEL158(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)
102963 
102964 #define XBARA_SEL79_SEL159_MASK                  (0xFF00U)
102965 #define XBARA_SEL79_SEL159_SHIFT                 (8U)
102966 #define XBARA_SEL79_SEL159(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)
102967 /*! @} */
102968 
102969 /*! @name SEL80 - Crossbar A Select Register 80 */
102970 /*! @{ */
102971 
102972 #define XBARA_SEL80_SEL160_MASK                  (0xFFU)
102973 #define XBARA_SEL80_SEL160_SHIFT                 (0U)
102974 #define XBARA_SEL80_SEL160(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)
102975 
102976 #define XBARA_SEL80_SEL161_MASK                  (0xFF00U)
102977 #define XBARA_SEL80_SEL161_SHIFT                 (8U)
102978 #define XBARA_SEL80_SEL161(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)
102979 /*! @} */
102980 
102981 /*! @name SEL81 - Crossbar A Select Register 81 */
102982 /*! @{ */
102983 
102984 #define XBARA_SEL81_SEL162_MASK                  (0xFFU)
102985 #define XBARA_SEL81_SEL162_SHIFT                 (0U)
102986 #define XBARA_SEL81_SEL162(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)
102987 
102988 #define XBARA_SEL81_SEL163_MASK                  (0xFF00U)
102989 #define XBARA_SEL81_SEL163_SHIFT                 (8U)
102990 #define XBARA_SEL81_SEL163(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)
102991 /*! @} */
102992 
102993 /*! @name SEL82 - Crossbar A Select Register 82 */
102994 /*! @{ */
102995 
102996 #define XBARA_SEL82_SEL164_MASK                  (0xFFU)
102997 #define XBARA_SEL82_SEL164_SHIFT                 (0U)
102998 #define XBARA_SEL82_SEL164(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)
102999 
103000 #define XBARA_SEL82_SEL165_MASK                  (0xFF00U)
103001 #define XBARA_SEL82_SEL165_SHIFT                 (8U)
103002 #define XBARA_SEL82_SEL165(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)
103003 /*! @} */
103004 
103005 /*! @name SEL83 - Crossbar A Select Register 83 */
103006 /*! @{ */
103007 
103008 #define XBARA_SEL83_SEL166_MASK                  (0xFFU)
103009 #define XBARA_SEL83_SEL166_SHIFT                 (0U)
103010 #define XBARA_SEL83_SEL166(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)
103011 
103012 #define XBARA_SEL83_SEL167_MASK                  (0xFF00U)
103013 #define XBARA_SEL83_SEL167_SHIFT                 (8U)
103014 #define XBARA_SEL83_SEL167(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)
103015 /*! @} */
103016 
103017 /*! @name SEL84 - Crossbar A Select Register 84 */
103018 /*! @{ */
103019 
103020 #define XBARA_SEL84_SEL168_MASK                  (0xFFU)
103021 #define XBARA_SEL84_SEL168_SHIFT                 (0U)
103022 #define XBARA_SEL84_SEL168(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)
103023 
103024 #define XBARA_SEL84_SEL169_MASK                  (0xFF00U)
103025 #define XBARA_SEL84_SEL169_SHIFT                 (8U)
103026 #define XBARA_SEL84_SEL169(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)
103027 /*! @} */
103028 
103029 /*! @name SEL85 - Crossbar A Select Register 85 */
103030 /*! @{ */
103031 
103032 #define XBARA_SEL85_SEL170_MASK                  (0xFFU)
103033 #define XBARA_SEL85_SEL170_SHIFT                 (0U)
103034 #define XBARA_SEL85_SEL170(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)
103035 
103036 #define XBARA_SEL85_SEL171_MASK                  (0xFF00U)
103037 #define XBARA_SEL85_SEL171_SHIFT                 (8U)
103038 #define XBARA_SEL85_SEL171(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)
103039 /*! @} */
103040 
103041 /*! @name SEL86 - Crossbar A Select Register 86 */
103042 /*! @{ */
103043 
103044 #define XBARA_SEL86_SEL172_MASK                  (0xFFU)
103045 #define XBARA_SEL86_SEL172_SHIFT                 (0U)
103046 #define XBARA_SEL86_SEL172(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)
103047 
103048 #define XBARA_SEL86_SEL173_MASK                  (0xFF00U)
103049 #define XBARA_SEL86_SEL173_SHIFT                 (8U)
103050 #define XBARA_SEL86_SEL173(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)
103051 /*! @} */
103052 
103053 /*! @name SEL87 - Crossbar A Select Register 87 */
103054 /*! @{ */
103055 
103056 #define XBARA_SEL87_SEL174_MASK                  (0xFFU)
103057 #define XBARA_SEL87_SEL174_SHIFT                 (0U)
103058 #define XBARA_SEL87_SEL174(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)
103059 
103060 #define XBARA_SEL87_SEL175_MASK                  (0xFF00U)
103061 #define XBARA_SEL87_SEL175_SHIFT                 (8U)
103062 #define XBARA_SEL87_SEL175(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)
103063 /*! @} */
103064 
103065 /*! @name CTRL0 - Crossbar A Control Register 0 */
103066 /*! @{ */
103067 
103068 #define XBARA_CTRL0_DEN0_MASK                    (0x1U)
103069 #define XBARA_CTRL0_DEN0_SHIFT                   (0U)
103070 /*! DEN0 - DMA Enable for XBAR_OUT0
103071  *  0b0..DMA disabled
103072  *  0b1..DMA enabled
103073  */
103074 #define XBARA_CTRL0_DEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
103075 
103076 #define XBARA_CTRL0_IEN0_MASK                    (0x2U)
103077 #define XBARA_CTRL0_IEN0_SHIFT                   (1U)
103078 /*! IEN0 - Interrupt Enable for XBAR_OUT0
103079  *  0b0..Interrupt disabled
103080  *  0b1..Interrupt enabled
103081  */
103082 #define XBARA_CTRL0_IEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
103083 
103084 #define XBARA_CTRL0_EDGE0_MASK                   (0xCU)
103085 #define XBARA_CTRL0_EDGE0_SHIFT                  (2U)
103086 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0
103087  *  0b00..STS0 never asserts
103088  *  0b01..STS0 asserts on rising edges of XBAR_OUT0
103089  *  0b10..STS0 asserts on falling edges of XBAR_OUT0
103090  *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
103091  */
103092 #define XBARA_CTRL0_EDGE0(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
103093 
103094 #define XBARA_CTRL0_STS0_MASK                    (0x10U)
103095 #define XBARA_CTRL0_STS0_SHIFT                   (4U)
103096 /*! STS0 - Edge detection status for XBAR_OUT0
103097  *  0b0..Active edge not yet detected on XBAR_OUT0
103098  *  0b1..Active edge detected on XBAR_OUT0
103099  */
103100 #define XBARA_CTRL0_STS0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
103101 
103102 #define XBARA_CTRL0_DEN1_MASK                    (0x100U)
103103 #define XBARA_CTRL0_DEN1_SHIFT                   (8U)
103104 /*! DEN1 - DMA Enable for XBAR_OUT1
103105  *  0b0..DMA disabled
103106  *  0b1..DMA enabled
103107  */
103108 #define XBARA_CTRL0_DEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
103109 
103110 #define XBARA_CTRL0_IEN1_MASK                    (0x200U)
103111 #define XBARA_CTRL0_IEN1_SHIFT                   (9U)
103112 /*! IEN1 - Interrupt Enable for XBAR_OUT1
103113  *  0b0..Interrupt disabled
103114  *  0b1..Interrupt enabled
103115  */
103116 #define XBARA_CTRL0_IEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
103117 
103118 #define XBARA_CTRL0_EDGE1_MASK                   (0xC00U)
103119 #define XBARA_CTRL0_EDGE1_SHIFT                  (10U)
103120 /*! EDGE1 - Active edge for edge detection on XBAR_OUT1
103121  *  0b00..STS1 never asserts
103122  *  0b01..STS1 asserts on rising edges of XBAR_OUT1
103123  *  0b10..STS1 asserts on falling edges of XBAR_OUT1
103124  *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
103125  */
103126 #define XBARA_CTRL0_EDGE1(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
103127 
103128 #define XBARA_CTRL0_STS1_MASK                    (0x1000U)
103129 #define XBARA_CTRL0_STS1_SHIFT                   (12U)
103130 /*! STS1 - Edge detection status for XBAR_OUT1
103131  *  0b0..Active edge not yet detected on XBAR_OUT1
103132  *  0b1..Active edge detected on XBAR_OUT1
103133  */
103134 #define XBARA_CTRL0_STS1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
103135 /*! @} */
103136 
103137 /*! @name CTRL1 - Crossbar A Control Register 1 */
103138 /*! @{ */
103139 
103140 #define XBARA_CTRL1_DEN2_MASK                    (0x1U)
103141 #define XBARA_CTRL1_DEN2_SHIFT                   (0U)
103142 /*! DEN2 - DMA Enable for XBAR_OUT2
103143  *  0b0..DMA disabled
103144  *  0b1..DMA enabled
103145  */
103146 #define XBARA_CTRL1_DEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
103147 
103148 #define XBARA_CTRL1_IEN2_MASK                    (0x2U)
103149 #define XBARA_CTRL1_IEN2_SHIFT                   (1U)
103150 /*! IEN2 - Interrupt Enable for XBAR_OUT2
103151  *  0b0..Interrupt disabled
103152  *  0b1..Interrupt enabled
103153  */
103154 #define XBARA_CTRL1_IEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
103155 
103156 #define XBARA_CTRL1_EDGE2_MASK                   (0xCU)
103157 #define XBARA_CTRL1_EDGE2_SHIFT                  (2U)
103158 /*! EDGE2 - Active edge for edge detection on XBAR_OUT2
103159  *  0b00..STS2 never asserts
103160  *  0b01..STS2 asserts on rising edges of XBAR_OUT2
103161  *  0b10..STS2 asserts on falling edges of XBAR_OUT2
103162  *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
103163  */
103164 #define XBARA_CTRL1_EDGE2(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
103165 
103166 #define XBARA_CTRL1_STS2_MASK                    (0x10U)
103167 #define XBARA_CTRL1_STS2_SHIFT                   (4U)
103168 /*! STS2 - Edge detection status for XBAR_OUT2
103169  *  0b0..Active edge not yet detected on XBAR_OUT2
103170  *  0b1..Active edge detected on XBAR_OUT2
103171  */
103172 #define XBARA_CTRL1_STS2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
103173 
103174 #define XBARA_CTRL1_DEN3_MASK                    (0x100U)
103175 #define XBARA_CTRL1_DEN3_SHIFT                   (8U)
103176 /*! DEN3 - DMA Enable for XBAR_OUT3
103177  *  0b0..DMA disabled
103178  *  0b1..DMA enabled
103179  */
103180 #define XBARA_CTRL1_DEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
103181 
103182 #define XBARA_CTRL1_IEN3_MASK                    (0x200U)
103183 #define XBARA_CTRL1_IEN3_SHIFT                   (9U)
103184 /*! IEN3 - Interrupt Enable for XBAR_OUT3
103185  *  0b0..Interrupt disabled
103186  *  0b1..Interrupt enabled
103187  */
103188 #define XBARA_CTRL1_IEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
103189 
103190 #define XBARA_CTRL1_EDGE3_MASK                   (0xC00U)
103191 #define XBARA_CTRL1_EDGE3_SHIFT                  (10U)
103192 /*! EDGE3 - Active edge for edge detection on XBAR_OUT3
103193  *  0b00..STS3 never asserts
103194  *  0b01..STS3 asserts on rising edges of XBAR_OUT3
103195  *  0b10..STS3 asserts on falling edges of XBAR_OUT3
103196  *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
103197  */
103198 #define XBARA_CTRL1_EDGE3(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
103199 
103200 #define XBARA_CTRL1_STS3_MASK                    (0x1000U)
103201 #define XBARA_CTRL1_STS3_SHIFT                   (12U)
103202 /*! STS3 - Edge detection status for XBAR_OUT3
103203  *  0b0..Active edge not yet detected on XBAR_OUT3
103204  *  0b1..Active edge detected on XBAR_OUT3
103205  */
103206 #define XBARA_CTRL1_STS3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
103207 /*! @} */
103208 
103209 
103210 /*!
103211  * @}
103212  */ /* end of group XBARA_Register_Masks */
103213 
103214 
103215 /* XBARA - Peripheral instance base addresses */
103216 /** Peripheral XBARA1 base address */
103217 #define XBARA1_BASE                              (0x4003C000u)
103218 /** Peripheral XBARA1 base pointer */
103219 #define XBARA1                                   ((XBARA_Type *)XBARA1_BASE)
103220 /** Array initializer of XBARA peripheral base addresses */
103221 #define XBARA_BASE_ADDRS                         { 0u, XBARA1_BASE }
103222 /** Array initializer of XBARA peripheral base pointers */
103223 #define XBARA_BASE_PTRS                          { (XBARA_Type *)0u, XBARA1 }
103224 
103225 /*!
103226  * @}
103227  */ /* end of group XBARA_Peripheral_Access_Layer */
103228 
103229 
103230 /* ----------------------------------------------------------------------------
103231    -- XBARB Peripheral Access Layer
103232    ---------------------------------------------------------------------------- */
103233 
103234 /*!
103235  * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
103236  * @{
103237  */
103238 
103239 /** XBARB - Register Layout Typedef */
103240 typedef struct {
103241   __IO uint16_t SEL0;                              /**< Crossbar B Select Register 0, offset: 0x0 */
103242   __IO uint16_t SEL1;                              /**< Crossbar B Select Register 1, offset: 0x2 */
103243   __IO uint16_t SEL2;                              /**< Crossbar B Select Register 2, offset: 0x4 */
103244   __IO uint16_t SEL3;                              /**< Crossbar B Select Register 3, offset: 0x6 */
103245   __IO uint16_t SEL4;                              /**< Crossbar B Select Register 4, offset: 0x8 */
103246   __IO uint16_t SEL5;                              /**< Crossbar B Select Register 5, offset: 0xA */
103247   __IO uint16_t SEL6;                              /**< Crossbar B Select Register 6, offset: 0xC */
103248   __IO uint16_t SEL7;                              /**< Crossbar B Select Register 7, offset: 0xE */
103249 } XBARB_Type;
103250 
103251 /* ----------------------------------------------------------------------------
103252    -- XBARB Register Masks
103253    ---------------------------------------------------------------------------- */
103254 
103255 /*!
103256  * @addtogroup XBARB_Register_Masks XBARB Register Masks
103257  * @{
103258  */
103259 
103260 /*! @name SEL0 - Crossbar B Select Register 0 */
103261 /*! @{ */
103262 
103263 #define XBARB_SEL0_SEL0_MASK                     (0x7FU)
103264 #define XBARB_SEL0_SEL0_SHIFT                    (0U)
103265 #define XBARB_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
103266 
103267 #define XBARB_SEL0_SEL1_MASK                     (0x7F00U)
103268 #define XBARB_SEL0_SEL1_SHIFT                    (8U)
103269 #define XBARB_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
103270 /*! @} */
103271 
103272 /*! @name SEL1 - Crossbar B Select Register 1 */
103273 /*! @{ */
103274 
103275 #define XBARB_SEL1_SEL2_MASK                     (0x7FU)
103276 #define XBARB_SEL1_SEL2_SHIFT                    (0U)
103277 #define XBARB_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
103278 
103279 #define XBARB_SEL1_SEL3_MASK                     (0x7F00U)
103280 #define XBARB_SEL1_SEL3_SHIFT                    (8U)
103281 #define XBARB_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
103282 /*! @} */
103283 
103284 /*! @name SEL2 - Crossbar B Select Register 2 */
103285 /*! @{ */
103286 
103287 #define XBARB_SEL2_SEL4_MASK                     (0x7FU)
103288 #define XBARB_SEL2_SEL4_SHIFT                    (0U)
103289 #define XBARB_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
103290 
103291 #define XBARB_SEL2_SEL5_MASK                     (0x7F00U)
103292 #define XBARB_SEL2_SEL5_SHIFT                    (8U)
103293 #define XBARB_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
103294 /*! @} */
103295 
103296 /*! @name SEL3 - Crossbar B Select Register 3 */
103297 /*! @{ */
103298 
103299 #define XBARB_SEL3_SEL6_MASK                     (0x7FU)
103300 #define XBARB_SEL3_SEL6_SHIFT                    (0U)
103301 #define XBARB_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
103302 
103303 #define XBARB_SEL3_SEL7_MASK                     (0x7F00U)
103304 #define XBARB_SEL3_SEL7_SHIFT                    (8U)
103305 #define XBARB_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
103306 /*! @} */
103307 
103308 /*! @name SEL4 - Crossbar B Select Register 4 */
103309 /*! @{ */
103310 
103311 #define XBARB_SEL4_SEL8_MASK                     (0x7FU)
103312 #define XBARB_SEL4_SEL8_SHIFT                    (0U)
103313 #define XBARB_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
103314 
103315 #define XBARB_SEL4_SEL9_MASK                     (0x7F00U)
103316 #define XBARB_SEL4_SEL9_SHIFT                    (8U)
103317 #define XBARB_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
103318 /*! @} */
103319 
103320 /*! @name SEL5 - Crossbar B Select Register 5 */
103321 /*! @{ */
103322 
103323 #define XBARB_SEL5_SEL10_MASK                    (0x7FU)
103324 #define XBARB_SEL5_SEL10_SHIFT                   (0U)
103325 #define XBARB_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
103326 
103327 #define XBARB_SEL5_SEL11_MASK                    (0x7F00U)
103328 #define XBARB_SEL5_SEL11_SHIFT                   (8U)
103329 #define XBARB_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
103330 /*! @} */
103331 
103332 /*! @name SEL6 - Crossbar B Select Register 6 */
103333 /*! @{ */
103334 
103335 #define XBARB_SEL6_SEL12_MASK                    (0x7FU)
103336 #define XBARB_SEL6_SEL12_SHIFT                   (0U)
103337 #define XBARB_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
103338 
103339 #define XBARB_SEL6_SEL13_MASK                    (0x7F00U)
103340 #define XBARB_SEL6_SEL13_SHIFT                   (8U)
103341 #define XBARB_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
103342 /*! @} */
103343 
103344 /*! @name SEL7 - Crossbar B Select Register 7 */
103345 /*! @{ */
103346 
103347 #define XBARB_SEL7_SEL14_MASK                    (0x7FU)
103348 #define XBARB_SEL7_SEL14_SHIFT                   (0U)
103349 #define XBARB_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
103350 
103351 #define XBARB_SEL7_SEL15_MASK                    (0x7F00U)
103352 #define XBARB_SEL7_SEL15_SHIFT                   (8U)
103353 #define XBARB_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
103354 /*! @} */
103355 
103356 
103357 /*!
103358  * @}
103359  */ /* end of group XBARB_Register_Masks */
103360 
103361 
103362 /* XBARB - Peripheral instance base addresses */
103363 /** Peripheral XBARB2 base address */
103364 #define XBARB2_BASE                              (0x40040000u)
103365 /** Peripheral XBARB2 base pointer */
103366 #define XBARB2                                   ((XBARB_Type *)XBARB2_BASE)
103367 /** Peripheral XBARB3 base address */
103368 #define XBARB3_BASE                              (0x40044000u)
103369 /** Peripheral XBARB3 base pointer */
103370 #define XBARB3                                   ((XBARB_Type *)XBARB3_BASE)
103371 /** Array initializer of XBARB peripheral base addresses */
103372 #define XBARB_BASE_ADDRS                         { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
103373 /** Array initializer of XBARB peripheral base pointers */
103374 #define XBARB_BASE_PTRS                          { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
103375 
103376 /*!
103377  * @}
103378  */ /* end of group XBARB_Peripheral_Access_Layer */
103379 
103380 
103381 /* ----------------------------------------------------------------------------
103382    -- XECC Peripheral Access Layer
103383    ---------------------------------------------------------------------------- */
103384 
103385 /*!
103386  * @addtogroup XECC_Peripheral_Access_Layer XECC Peripheral Access Layer
103387  * @{
103388  */
103389 
103390 /** XECC - Register Layout Typedef */
103391 typedef struct {
103392   __IO uint32_t ECC_CTRL;                          /**< ECC Control Register, offset: 0x0 */
103393   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x4 */
103394   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x8 */
103395   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0xC */
103396   __IO uint32_t ERR_DATA_INJ;                      /**< Error Injection On Write Data, offset: 0x10 */
103397   __IO uint32_t ERR_ECC_INJ;                       /**< Error Injection On ECC Code of Write Data, offset: 0x14 */
103398   __I  uint32_t SINGLE_ERR_ADDR;                   /**< Single Error Address, offset: 0x18 */
103399   __I  uint32_t SINGLE_ERR_DATA;                   /**< Single Error Read Data, offset: 0x1C */
103400   __I  uint32_t SINGLE_ERR_ECC;                    /**< Single Error ECC Code, offset: 0x20 */
103401   __I  uint32_t SINGLE_ERR_POS;                    /**< Single Error Bit Position, offset: 0x24 */
103402   __I  uint32_t SINGLE_ERR_BIT_FIELD;              /**< Single Error Bit Field, offset: 0x28 */
103403   __I  uint32_t MULTI_ERR_ADDR;                    /**< Multiple Error Address, offset: 0x2C */
103404   __I  uint32_t MULTI_ERR_DATA;                    /**< Multiple Error Read Data, offset: 0x30 */
103405   __I  uint32_t MULTI_ERR_ECC;                     /**< Multiple Error ECC code, offset: 0x34 */
103406   __I  uint32_t MULTI_ERR_BIT_FIELD;               /**< Multiple Error Bit Field, offset: 0x38 */
103407   __IO uint32_t ECC_BASE_ADDR0;                    /**< ECC Region 0 Base Address, offset: 0x3C */
103408   __IO uint32_t ECC_END_ADDR0;                     /**< ECC Region 0 End Address, offset: 0x40 */
103409   __IO uint32_t ECC_BASE_ADDR1;                    /**< ECC Region 1 Base Address, offset: 0x44 */
103410   __IO uint32_t ECC_END_ADDR1;                     /**< ECC Region 1 End Address, offset: 0x48 */
103411   __IO uint32_t ECC_BASE_ADDR2;                    /**< ECC Region 2 Base Address, offset: 0x4C */
103412   __IO uint32_t ECC_END_ADDR2;                     /**< ECC Region 2 End Address, offset: 0x50 */
103413   __IO uint32_t ECC_BASE_ADDR3;                    /**< ECC Region 3 Base Address, offset: 0x54 */
103414   __IO uint32_t ECC_END_ADDR3;                     /**< ECC Region 3 End Address, offset: 0x58 */
103415 } XECC_Type;
103416 
103417 /* ----------------------------------------------------------------------------
103418    -- XECC Register Masks
103419    ---------------------------------------------------------------------------- */
103420 
103421 /*!
103422  * @addtogroup XECC_Register_Masks XECC Register Masks
103423  * @{
103424  */
103425 
103426 /*! @name ECC_CTRL - ECC Control Register */
103427 /*! @{ */
103428 
103429 #define XECC_ECC_CTRL_ECC_EN_MASK                (0x1U)
103430 #define XECC_ECC_CTRL_ECC_EN_SHIFT               (0U)
103431 /*! ECC_EN - ECC Function Enable
103432  *  0b0..Disable
103433  *  0b1..Enable
103434  */
103435 #define XECC_ECC_CTRL_ECC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK)
103436 
103437 #define XECC_ECC_CTRL_WECC_EN_MASK               (0x2U)
103438 #define XECC_ECC_CTRL_WECC_EN_SHIFT              (1U)
103439 /*! WECC_EN - Write ECC Encode Function Enable
103440  *  0b0..Disable
103441  *  0b1..Enable
103442  */
103443 #define XECC_ECC_CTRL_WECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK)
103444 
103445 #define XECC_ECC_CTRL_RECC_EN_MASK               (0x4U)
103446 #define XECC_ECC_CTRL_RECC_EN_SHIFT              (2U)
103447 /*! RECC_EN - Read ECC Function Enable
103448  *  0b0..Disable
103449  *  0b1..Enable
103450  */
103451 #define XECC_ECC_CTRL_RECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK)
103452 
103453 #define XECC_ECC_CTRL_SWAP_EN_MASK               (0x8U)
103454 #define XECC_ECC_CTRL_SWAP_EN_SHIFT              (3U)
103455 /*! SWAP_EN - Swap Data Enable
103456  *  0b0..Disable
103457  *  0b1..Enable
103458  */
103459 #define XECC_ECC_CTRL_SWAP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK)
103460 /*! @} */
103461 
103462 /*! @name ERR_STATUS - Error Interrupt Status Register */
103463 /*! @{ */
103464 
103465 #define XECC_ERR_STATUS_SINGLE_ERR_MASK          (0x1U)
103466 #define XECC_ERR_STATUS_SINGLE_ERR_SHIFT         (0U)
103467 /*! SINGLE_ERR - Single Bit Error
103468  *  0b0..Single bit error does not happen.
103469  *  0b1..Single bit error happens.
103470  */
103471 #define XECC_ERR_STATUS_SINGLE_ERR(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)
103472 
103473 #define XECC_ERR_STATUS_MULTI_ERR_MASK           (0x2U)
103474 #define XECC_ERR_STATUS_MULTI_ERR_SHIFT          (1U)
103475 /*! MULTI_ERR - Multiple Bits Error
103476  *  0b0..Multiple bits error does not happen.
103477  *  0b1..Multiple bits error happens.
103478  */
103479 #define XECC_ERR_STATUS_MULTI_ERR(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)
103480 
103481 #define XECC_ERR_STATUS_Reserved1_MASK           (0xFFFFFFFCU)
103482 #define XECC_ERR_STATUS_Reserved1_SHIFT          (2U)
103483 /*! Reserved1 - Reserved
103484  */
103485 #define XECC_ERR_STATUS_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)
103486 /*! @} */
103487 
103488 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
103489 /*! @{ */
103490 
103491 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)
103492 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)
103493 /*! SINGLE_ERR_STAT_EN - Single Bit Error Status Enable
103494  *  0b0..Masked
103495  *  0b1..Enabled
103496  */
103497 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)
103498 
103499 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK  (0x2U)
103500 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)
103501 /*! MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable
103502  *  0b0..Masked
103503  *  0b1..Enabled
103504  */
103505 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)
103506 
103507 #define XECC_ERR_STAT_EN_Reserved1_MASK          (0xFFFFFFFCU)
103508 #define XECC_ERR_STAT_EN_Reserved1_SHIFT         (2U)
103509 /*! Reserved1 - Reserved
103510  */
103511 #define XECC_ERR_STAT_EN_Reserved1(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)
103512 /*! @} */
103513 
103514 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
103515 /*! @{ */
103516 
103517 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK   (0x1U)
103518 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT  (0U)
103519 /*! SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable
103520  *  0b0..Masked
103521  *  0b1..Enabled
103522  */
103523 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)
103524 
103525 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK    (0x2U)
103526 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT   (1U)
103527 /*! MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable
103528  *  0b0..Masked
103529  *  0b1..Enabled
103530  */
103531 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)
103532 
103533 #define XECC_ERR_SIG_EN_Reserved1_MASK           (0xFFFFFFFCU)
103534 #define XECC_ERR_SIG_EN_Reserved1_SHIFT          (2U)
103535 /*! Reserved1 - Reserved
103536  */
103537 #define XECC_ERR_SIG_EN_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)
103538 /*! @} */
103539 
103540 /*! @name ERR_DATA_INJ - Error Injection On Write Data */
103541 /*! @{ */
103542 
103543 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK      (0xFFFFFFFFU)
103544 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT     (0U)
103545 /*! ERR_DATA_INJ - Error Injection On Write Data
103546  */
103547 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ(x)        (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK)
103548 /*! @} */
103549 
103550 /*! @name ERR_ECC_INJ - Error Injection On ECC Code of Write Data */
103551 /*! @{ */
103552 
103553 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK        (0xFFFFFFFFU)
103554 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT       (0U)
103555 /*! ERR_ECC_INJ - Error Injection On ECC Code of Write Data
103556  */
103557 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ(x)          (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK)
103558 /*! @} */
103559 
103560 /*! @name SINGLE_ERR_ADDR - Single Error Address */
103561 /*! @{ */
103562 
103563 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU)
103564 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U)
103565 /*! SINGLE_ERR_ADDR - Single Error Address
103566  */
103567 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK)
103568 /*! @} */
103569 
103570 /*! @name SINGLE_ERR_DATA - Single Error Read Data */
103571 /*! @{ */
103572 
103573 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
103574 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U)
103575 /*! SINGLE_ERR_DATA - Single Error Read Data
103576  */
103577 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK)
103578 /*! @} */
103579 
103580 /*! @name SINGLE_ERR_ECC - Single Error ECC Code */
103581 /*! @{ */
103582 
103583 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK  (0xFFFFFFFFU)
103584 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U)
103585 /*! SINGLE_ERR_ECC - Single Error ECC code
103586  */
103587 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK)
103588 /*! @} */
103589 
103590 /*! @name SINGLE_ERR_POS - Single Error Bit Position */
103591 /*! @{ */
103592 
103593 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK  (0xFFFFFFFFU)
103594 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U)
103595 /*! SINGLE_ERR_POS - Single Error bit Position
103596  */
103597 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK)
103598 /*! @} */
103599 
103600 /*! @name SINGLE_ERR_BIT_FIELD - Single Error Bit Field */
103601 /*! @{ */
103602 
103603 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU)
103604 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U)
103605 /*! SINGLE_ERR_BIT_FIELD - Single Error Bit Field
103606  */
103607 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK)
103608 
103609 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
103610 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
103611 /*! Reserved1 - Reserved
103612  */
103613 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x)   (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK)
103614 /*! @} */
103615 
103616 /*! @name MULTI_ERR_ADDR - Multiple Error Address */
103617 /*! @{ */
103618 
103619 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK  (0xFFFFFFFFU)
103620 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U)
103621 /*! MULTI_ERR_ADDR - Multiple Error Address
103622  */
103623 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK)
103624 /*! @} */
103625 
103626 /*! @name MULTI_ERR_DATA - Multiple Error Read Data */
103627 /*! @{ */
103628 
103629 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK  (0xFFFFFFFFU)
103630 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U)
103631 /*! MULTI_ERR_DATA - Multiple Error Read Data
103632  */
103633 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK)
103634 /*! @} */
103635 
103636 /*! @name MULTI_ERR_ECC - Multiple Error ECC code */
103637 /*! @{ */
103638 
103639 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK    (0xFFFFFFFFU)
103640 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT   (0U)
103641 /*! MULTI_ERR_ECC - Multiple Error ECC code
103642  */
103643 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x)      (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK)
103644 /*! @} */
103645 
103646 /*! @name MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */
103647 /*! @{ */
103648 
103649 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU)
103650 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U)
103651 /*! MULTI_ERR_BIT_FIELD - Multiple Error Bit Field
103652  */
103653 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK)
103654 
103655 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK  (0xFFFFFF00U)
103656 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
103657 /*! Reserved1 - Reserved
103658  */
103659 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK)
103660 /*! @} */
103661 
103662 /*! @name ECC_BASE_ADDR0 - ECC Region 0 Base Address */
103663 /*! @{ */
103664 
103665 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK  (0xFFFFFFFFU)
103666 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U)
103667 /*! ECC_BASE_ADDR0 - ECC Region 0 Base Address
103668  */
103669 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK)
103670 /*! @} */
103671 
103672 /*! @name ECC_END_ADDR0 - ECC Region 0 End Address */
103673 /*! @{ */
103674 
103675 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK    (0xFFFFFFFFU)
103676 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT   (0U)
103677 /*! ECC_END_ADDR0 - ECC Region 0 End Address
103678  */
103679 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK)
103680 /*! @} */
103681 
103682 /*! @name ECC_BASE_ADDR1 - ECC Region 1 Base Address */
103683 /*! @{ */
103684 
103685 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK  (0xFFFFFFFFU)
103686 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U)
103687 /*! ECC_BASE_ADDR1 - ECC Region 1 Base Address
103688  */
103689 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK)
103690 /*! @} */
103691 
103692 /*! @name ECC_END_ADDR1 - ECC Region 1 End Address */
103693 /*! @{ */
103694 
103695 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK    (0xFFFFFFFFU)
103696 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT   (0U)
103697 /*! ECC_END_ADDR1 - ECC Region 1 End Address
103698  */
103699 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK)
103700 /*! @} */
103701 
103702 /*! @name ECC_BASE_ADDR2 - ECC Region 2 Base Address */
103703 /*! @{ */
103704 
103705 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK  (0xFFFFFFFFU)
103706 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U)
103707 /*! ECC_BASE_ADDR2 - ECC Region 2 Base Address
103708  */
103709 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK)
103710 /*! @} */
103711 
103712 /*! @name ECC_END_ADDR2 - ECC Region 2 End Address */
103713 /*! @{ */
103714 
103715 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK    (0xFFFFFFFFU)
103716 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT   (0U)
103717 /*! ECC_END_ADDR2 - ECC Region 2 End Address
103718  */
103719 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK)
103720 /*! @} */
103721 
103722 /*! @name ECC_BASE_ADDR3 - ECC Region 3 Base Address */
103723 /*! @{ */
103724 
103725 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK  (0xFFFFFFFFU)
103726 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U)
103727 /*! ECC_BASE_ADDR3 - ECC Region 3 Base Address
103728  */
103729 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK)
103730 /*! @} */
103731 
103732 /*! @name ECC_END_ADDR3 - ECC Region 3 End Address */
103733 /*! @{ */
103734 
103735 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK    (0xFFFFFFFFU)
103736 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT   (0U)
103737 /*! ECC_END_ADDR3 - ECC Region 3 End Address
103738  */
103739 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK)
103740 /*! @} */
103741 
103742 
103743 /*!
103744  * @}
103745  */ /* end of group XECC_Register_Masks */
103746 
103747 
103748 /* XECC - Peripheral instance base addresses */
103749 /** Peripheral XECC_FLEXSPI1 base address */
103750 #define XECC_FLEXSPI1_BASE                       (0x4001C000u)
103751 /** Peripheral XECC_FLEXSPI1 base pointer */
103752 #define XECC_FLEXSPI1                            ((XECC_Type *)XECC_FLEXSPI1_BASE)
103753 /** Peripheral XECC_FLEXSPI2 base address */
103754 #define XECC_FLEXSPI2_BASE                       (0x40020000u)
103755 /** Peripheral XECC_FLEXSPI2 base pointer */
103756 #define XECC_FLEXSPI2                            ((XECC_Type *)XECC_FLEXSPI2_BASE)
103757 /** Peripheral XECC_SEMC base address */
103758 #define XECC_SEMC_BASE                           (0x40024000u)
103759 /** Peripheral XECC_SEMC base pointer */
103760 #define XECC_SEMC                                ((XECC_Type *)XECC_SEMC_BASE)
103761 /** Array initializer of XECC peripheral base addresses */
103762 #define XECC_BASE_ADDRS                          { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
103763 /** Array initializer of XECC peripheral base pointers */
103764 #define XECC_BASE_PTRS                           { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
103765 
103766 /*!
103767  * @}
103768  */ /* end of group XECC_Peripheral_Access_Layer */
103769 
103770 
103771 /* ----------------------------------------------------------------------------
103772    -- XRDC2 Peripheral Access Layer
103773    ---------------------------------------------------------------------------- */
103774 
103775 /*!
103776  * @addtogroup XRDC2_Peripheral_Access_Layer XRDC2 Peripheral Access Layer
103777  * @{
103778  */
103779 
103780 /** XRDC2 - Register Layout Typedef */
103781 typedef struct {
103782   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
103783   __I  uint32_t SR;                                /**< Status Register, offset: 0x4 */
103784        uint8_t RESERVED_0[4088];
103785   struct {                                         /* offset: 0x1000, array step: 0x8 */
103786     __IO uint32_t MSC_MSAC_W0;                       /**< Memory Slot Access Control, array offset: 0x1000, array step: 0x8 */
103787     __IO uint32_t MSC_MSAC_W1;                       /**< Memory Slot Access Control, array offset: 0x1004, array step: 0x8 */
103788   } MSCI_MSAC_WK[128];
103789        uint8_t RESERVED_1[3072];
103790   struct {                                         /* offset: 0x2000, array step: index*0x100, index2*0x8 */
103791     __IO uint32_t MDAC_MDA_W0;                       /**< Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8 */
103792     __IO uint32_t MDAC_MDA_W1;                       /**< Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8 */
103793   } MDACI_MDAJ[32][32];
103794   struct {                                         /* offset: 0x4000, array step: index*0x800, index2*0x8 */
103795     __IO uint32_t PAC_PDAC_W0;                       /**< Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8 */
103796     __IO uint32_t PAC_PDAC_W1;                       /**< Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8 */
103797   } PACI_PDACJ[8][256];
103798   struct {                                         /* offset: 0x8000, array step: index*0x400, index2*0x20 */
103799     __IO uint32_t MRC_MRGD_W0;                       /**< Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20 */
103800     __IO uint32_t MRC_MRGD_W1;                       /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */
103801     __IO uint32_t MRC_MRGD_W2;                       /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */
103802     __IO uint32_t MRC_MRGD_W3;                       /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */
103803          uint8_t RESERVED_0[4];
103804     __IO uint32_t MRC_MRGD_W5;                       /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */
103805     __IO uint32_t MRC_MRGD_W6;                       /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */
103806          uint8_t RESERVED_1[4];
103807   } MRCI_MRGDJ[32][32];
103808 } XRDC2_Type;
103809 
103810 /* ----------------------------------------------------------------------------
103811    -- XRDC2 Register Masks
103812    ---------------------------------------------------------------------------- */
103813 
103814 /*!
103815  * @addtogroup XRDC2_Register_Masks XRDC2 Register Masks
103816  * @{
103817  */
103818 
103819 /*! @name MCR - Module Control Register */
103820 /*! @{ */
103821 
103822 #define XRDC2_MCR_GVLDM_MASK                     (0x1U)
103823 #define XRDC2_MCR_GVLDM_SHIFT                    (0U)
103824 /*! GVLDM - Global Valid MDAC
103825  *  0b0..MDACs are disabled.
103826  *  0b1..MDACs are enabled.
103827  */
103828 #define XRDC2_MCR_GVLDM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
103829 
103830 #define XRDC2_MCR_GVLDC_MASK                     (0x2U)
103831 #define XRDC2_MCR_GVLDC_SHIFT                    (1U)
103832 /*! GVLDC - Global Valid Access Control
103833  *  0b0..Access controls are disabled, XRDC2 allows all transactions.
103834  *  0b1..Access controls are enabled.
103835  */
103836 #define XRDC2_MCR_GVLDC(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
103837 
103838 #define XRDC2_MCR_GCL_MASK                       (0x30U)
103839 #define XRDC2_MCR_GCL_SHIFT                      (4U)
103840 /*! GCL - Global Configuration Lock
103841  *  0b00..Lock disabled, registers can be written by any domain.
103842  *  0b01..Lock disabled until the next reset, registers can be written by any domain.
103843  *  0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers.
103844  *  0b11..Lock enabled, all registers are read only until the next reset.
103845  */
103846 #define XRDC2_MCR_GCL(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)
103847 /*! @} */
103848 
103849 /*! @name SR - Status Register */
103850 /*! @{ */
103851 
103852 #define XRDC2_SR_DIN_MASK                        (0xFU)
103853 #define XRDC2_SR_DIN_SHIFT                       (0U)
103854 /*! DIN - Domain Identifier Number
103855  */
103856 #define XRDC2_SR_DIN(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
103857 
103858 #define XRDC2_SR_HRL_MASK                        (0xF0U)
103859 #define XRDC2_SR_HRL_SHIFT                       (4U)
103860 /*! HRL - Hardware Revision Level
103861  */
103862 #define XRDC2_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
103863 
103864 #define XRDC2_SR_GCLO_MASK                       (0xF00U)
103865 #define XRDC2_SR_GCLO_SHIFT                      (8U)
103866 /*! GCLO - Global Configuration Lock Owner
103867  */
103868 #define XRDC2_SR_GCLO(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)
103869 /*! @} */
103870 
103871 /*! @name MSC_MSAC_W0 - Memory Slot Access Control */
103872 /*! @{ */
103873 
103874 #define XRDC2_MSC_MSAC_W0_D0ACP_MASK             (0x7U)
103875 #define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT            (0U)
103876 /*! D0ACP - Domain "x" access control policy
103877  */
103878 #define XRDC2_MSC_MSAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
103879 
103880 #define XRDC2_MSC_MSAC_W0_D1ACP_MASK             (0x38U)
103881 #define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT            (3U)
103882 /*! D1ACP - Domain "x" access control policy
103883  */
103884 #define XRDC2_MSC_MSAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
103885 
103886 #define XRDC2_MSC_MSAC_W0_D2ACP_MASK             (0x1C0U)
103887 #define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT            (6U)
103888 /*! D2ACP - Domain "x" access control policy
103889  */
103890 #define XRDC2_MSC_MSAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
103891 
103892 #define XRDC2_MSC_MSAC_W0_D3ACP_MASK             (0xE00U)
103893 #define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT            (9U)
103894 /*! D3ACP - Domain "x" access control policy
103895  */
103896 #define XRDC2_MSC_MSAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
103897 
103898 #define XRDC2_MSC_MSAC_W0_D4ACP_MASK             (0x7000U)
103899 #define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT            (12U)
103900 /*! D4ACP - Domain "x" access control policy
103901  */
103902 #define XRDC2_MSC_MSAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
103903 
103904 #define XRDC2_MSC_MSAC_W0_D5ACP_MASK             (0x38000U)
103905 #define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT            (15U)
103906 /*! D5ACP - Domain "x" access control policy
103907  */
103908 #define XRDC2_MSC_MSAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
103909 
103910 #define XRDC2_MSC_MSAC_W0_D6ACP_MASK             (0x1C0000U)
103911 #define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT            (18U)
103912 /*! D6ACP - Domain "x" access control policy
103913  */
103914 #define XRDC2_MSC_MSAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
103915 
103916 #define XRDC2_MSC_MSAC_W0_D7ACP_MASK             (0xE00000U)
103917 #define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT            (21U)
103918 /*! D7ACP - Domain "x" access control policy
103919  */
103920 #define XRDC2_MSC_MSAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
103921 
103922 #define XRDC2_MSC_MSAC_W0_EALO_MASK              (0xF000000U)
103923 #define XRDC2_MSC_MSAC_W0_EALO_SHIFT             (24U)
103924 /*! EALO - Exclusive Access Lock Owner
103925  */
103926 #define XRDC2_MSC_MSAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)
103927 /*! @} */
103928 
103929 /* The count of XRDC2_MSC_MSAC_W0 */
103930 #define XRDC2_MSC_MSAC_W0_COUNT                  (128U)
103931 
103932 /*! @name MSC_MSAC_W1 - Memory Slot Access Control */
103933 /*! @{ */
103934 
103935 #define XRDC2_MSC_MSAC_W1_D8ACP_MASK             (0x7U)
103936 #define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT            (0U)
103937 /*! D8ACP - Domain "x" access control policy
103938  */
103939 #define XRDC2_MSC_MSAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
103940 
103941 #define XRDC2_MSC_MSAC_W1_D9ACP_MASK             (0x38U)
103942 #define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT            (3U)
103943 /*! D9ACP - Domain "x" access control policy
103944  */
103945 #define XRDC2_MSC_MSAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
103946 
103947 #define XRDC2_MSC_MSAC_W1_D10ACP_MASK            (0x1C0U)
103948 #define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT           (6U)
103949 /*! D10ACP - Domain "x" access control policy
103950  */
103951 #define XRDC2_MSC_MSAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
103952 
103953 #define XRDC2_MSC_MSAC_W1_D11ACP_MASK            (0xE00U)
103954 #define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT           (9U)
103955 /*! D11ACP - Domain "x" access control policy
103956  */
103957 #define XRDC2_MSC_MSAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
103958 
103959 #define XRDC2_MSC_MSAC_W1_D12ACP_MASK            (0x7000U)
103960 #define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT           (12U)
103961 /*! D12ACP - Domain "x" access control policy
103962  */
103963 #define XRDC2_MSC_MSAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
103964 
103965 #define XRDC2_MSC_MSAC_W1_D13ACP_MASK            (0x38000U)
103966 #define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT           (15U)
103967 /*! D13ACP - Domain "x" access control policy
103968  */
103969 #define XRDC2_MSC_MSAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
103970 
103971 #define XRDC2_MSC_MSAC_W1_D14ACP_MASK            (0x1C0000U)
103972 #define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT           (18U)
103973 /*! D14ACP - Domain "x" access control policy
103974  */
103975 #define XRDC2_MSC_MSAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
103976 
103977 #define XRDC2_MSC_MSAC_W1_D15ACP_MASK            (0xE00000U)
103978 #define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT           (21U)
103979 /*! D15ACP - Domain "x" access control policy
103980  */
103981 #define XRDC2_MSC_MSAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
103982 
103983 #define XRDC2_MSC_MSAC_W1_EAL_MASK               (0x3000000U)
103984 #define XRDC2_MSC_MSAC_W1_EAL_SHIFT              (24U)
103985 /*! EAL - Exclusive Access Lock
103986  *  0b00..Lock disabled.
103987  *  0b01..Lock disabled until next reset.
103988  *  0b10..Lock enabled, lock state = available.
103989  *  0b11..Lock enabled, lock state = not available.
103990  */
103991 #define XRDC2_MSC_MSAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
103992 
103993 #define XRDC2_MSC_MSAC_W1_DL2_MASK               (0x60000000U)
103994 #define XRDC2_MSC_MSAC_W1_DL2_SHIFT              (29U)
103995 /*! DL2 - Descriptor Lock
103996  *  0b00..Lock disabled, descriptor registers can be written.
103997  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
103998  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
103999  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
104000  */
104001 #define XRDC2_MSC_MSAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
104002 
104003 #define XRDC2_MSC_MSAC_W1_VLD_MASK               (0x80000000U)
104004 #define XRDC2_MSC_MSAC_W1_VLD_SHIFT              (31U)
104005 /*! VLD - Valid
104006  *  0b0..The MSAC assignment is invalid.
104007  *  0b1..The MSAC assignment is valid.
104008  */
104009 #define XRDC2_MSC_MSAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)
104010 /*! @} */
104011 
104012 /* The count of XRDC2_MSC_MSAC_W1 */
104013 #define XRDC2_MSC_MSAC_W1_COUNT                  (128U)
104014 
104015 /*! @name MDAC_MDA_W0 - Master Domain Assignment */
104016 /*! @{ */
104017 
104018 #define XRDC2_MDAC_MDA_W0_MASK_MASK              (0xFFFFU)
104019 #define XRDC2_MDAC_MDA_W0_MASK_SHIFT             (0U)
104020 /*! MASK - Mask
104021  */
104022 #define XRDC2_MDAC_MDA_W0_MASK(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
104023 
104024 #define XRDC2_MDAC_MDA_W0_MATCH_MASK             (0xFFFF0000U)
104025 #define XRDC2_MDAC_MDA_W0_MATCH_SHIFT            (16U)
104026 /*! MATCH - Match
104027  */
104028 #define XRDC2_MDAC_MDA_W0_MATCH(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)
104029 /*! @} */
104030 
104031 /* The count of XRDC2_MDAC_MDA_W0 */
104032 #define XRDC2_MDAC_MDA_W0_COUNT                  (32U)
104033 
104034 /* The count of XRDC2_MDAC_MDA_W0 */
104035 #define XRDC2_MDAC_MDA_W0_COUNT2                 (32U)
104036 
104037 /*! @name MDAC_MDA_W1 - Master Domain Assignment */
104038 /*! @{ */
104039 
104040 #define XRDC2_MDAC_MDA_W1_DID_MASK               (0xF0000U)
104041 #define XRDC2_MDAC_MDA_W1_DID_SHIFT              (16U)
104042 /*! DID - Domain Identifier
104043  */
104044 #define XRDC2_MDAC_MDA_W1_DID(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
104045 
104046 #define XRDC2_MDAC_MDA_W1_PA_MASK                (0x3000000U)
104047 #define XRDC2_MDAC_MDA_W1_PA_SHIFT               (24U)
104048 /*! PA - Privileged attribute
104049  *  0b00..Use the bus master's privileged/user attribute directly.
104050  *  0b01..Use the bus master's privileged/user attribute directly.
104051  *  0b10..Force the bus attribute for this master to user.
104052  *  0b11..Force the bus attribute for this master to privileged.
104053  */
104054 #define XRDC2_MDAC_MDA_W1_PA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
104055 
104056 #define XRDC2_MDAC_MDA_W1_SA_MASK                (0xC000000U)
104057 #define XRDC2_MDAC_MDA_W1_SA_SHIFT               (26U)
104058 /*! SA - Secure attribute
104059  *  0b00..Use the bus master's secure/nonsecure attribute directly.
104060  *  0b01..Use the bus master's secure/nonsecure attribute directly.
104061  *  0b10..Force the bus attribute for this master to secure.
104062  *  0b11..Force the bus attribute for this master to nonsecure.
104063  */
104064 #define XRDC2_MDAC_MDA_W1_SA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
104065 
104066 #define XRDC2_MDAC_MDA_W1_DL_MASK                (0x40000000U)
104067 #define XRDC2_MDAC_MDA_W1_DL_SHIFT               (30U)
104068 /*! DL - Descriptor Lock
104069  *  0b0..Lock disabled, registers can be written.
104070  *  0b1..Lock enabled, registers are read-only until the next reset.
104071  */
104072 #define XRDC2_MDAC_MDA_W1_DL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
104073 
104074 #define XRDC2_MDAC_MDA_W1_VLD_MASK               (0x80000000U)
104075 #define XRDC2_MDAC_MDA_W1_VLD_SHIFT              (31U)
104076 /*! VLD - Valid
104077  *  0b0..The MDA is invalid.
104078  *  0b1..The MDA is valid.
104079  */
104080 #define XRDC2_MDAC_MDA_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)
104081 /*! @} */
104082 
104083 /* The count of XRDC2_MDAC_MDA_W1 */
104084 #define XRDC2_MDAC_MDA_W1_COUNT                  (32U)
104085 
104086 /* The count of XRDC2_MDAC_MDA_W1 */
104087 #define XRDC2_MDAC_MDA_W1_COUNT2                 (32U)
104088 
104089 /*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */
104090 /*! @{ */
104091 
104092 #define XRDC2_PAC_PDAC_W0_D0ACP_MASK             (0x7U)
104093 #define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT            (0U)
104094 /*! D0ACP - Domain "x" access control policy
104095  */
104096 #define XRDC2_PAC_PDAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
104097 
104098 #define XRDC2_PAC_PDAC_W0_D1ACP_MASK             (0x38U)
104099 #define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT            (3U)
104100 /*! D1ACP - Domain "x" access control policy
104101  */
104102 #define XRDC2_PAC_PDAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
104103 
104104 #define XRDC2_PAC_PDAC_W0_D2ACP_MASK             (0x1C0U)
104105 #define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT            (6U)
104106 /*! D2ACP - Domain "x" access control policy
104107  */
104108 #define XRDC2_PAC_PDAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
104109 
104110 #define XRDC2_PAC_PDAC_W0_D3ACP_MASK             (0xE00U)
104111 #define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT            (9U)
104112 /*! D3ACP - Domain "x" access control policy
104113  */
104114 #define XRDC2_PAC_PDAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
104115 
104116 #define XRDC2_PAC_PDAC_W0_D4ACP_MASK             (0x7000U)
104117 #define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT            (12U)
104118 /*! D4ACP - Domain "x" access control policy
104119  */
104120 #define XRDC2_PAC_PDAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
104121 
104122 #define XRDC2_PAC_PDAC_W0_D5ACP_MASK             (0x38000U)
104123 #define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT            (15U)
104124 /*! D5ACP - Domain "x" access control policy
104125  */
104126 #define XRDC2_PAC_PDAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
104127 
104128 #define XRDC2_PAC_PDAC_W0_D6ACP_MASK             (0x1C0000U)
104129 #define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT            (18U)
104130 /*! D6ACP - Domain "x" access control policy
104131  */
104132 #define XRDC2_PAC_PDAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
104133 
104134 #define XRDC2_PAC_PDAC_W0_D7ACP_MASK             (0xE00000U)
104135 #define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT            (21U)
104136 /*! D7ACP - Domain "x" access control policy
104137  */
104138 #define XRDC2_PAC_PDAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
104139 
104140 #define XRDC2_PAC_PDAC_W0_EALO_MASK              (0xF000000U)
104141 #define XRDC2_PAC_PDAC_W0_EALO_SHIFT             (24U)
104142 /*! EALO - Exclusive Access Lock Owner
104143  */
104144 #define XRDC2_PAC_PDAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)
104145 /*! @} */
104146 
104147 /* The count of XRDC2_PAC_PDAC_W0 */
104148 #define XRDC2_PAC_PDAC_W0_COUNT                  (8U)
104149 
104150 /* The count of XRDC2_PAC_PDAC_W0 */
104151 #define XRDC2_PAC_PDAC_W0_COUNT2                 (256U)
104152 
104153 /*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */
104154 /*! @{ */
104155 
104156 #define XRDC2_PAC_PDAC_W1_D8ACP_MASK             (0x7U)
104157 #define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT            (0U)
104158 /*! D8ACP - Domain "x" access control policy
104159  */
104160 #define XRDC2_PAC_PDAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
104161 
104162 #define XRDC2_PAC_PDAC_W1_D9ACP_MASK             (0x38U)
104163 #define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT            (3U)
104164 /*! D9ACP - Domain "x" access control policy
104165  */
104166 #define XRDC2_PAC_PDAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
104167 
104168 #define XRDC2_PAC_PDAC_W1_D10ACP_MASK            (0x1C0U)
104169 #define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT           (6U)
104170 /*! D10ACP - Domain "x" access control policy
104171  */
104172 #define XRDC2_PAC_PDAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
104173 
104174 #define XRDC2_PAC_PDAC_W1_D11ACP_MASK            (0xE00U)
104175 #define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT           (9U)
104176 /*! D11ACP - Domain "x" access control policy
104177  */
104178 #define XRDC2_PAC_PDAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
104179 
104180 #define XRDC2_PAC_PDAC_W1_D12ACP_MASK            (0x7000U)
104181 #define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT           (12U)
104182 /*! D12ACP - Domain "x" access control policy
104183  */
104184 #define XRDC2_PAC_PDAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
104185 
104186 #define XRDC2_PAC_PDAC_W1_D13ACP_MASK            (0x38000U)
104187 #define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT           (15U)
104188 /*! D13ACP - Domain "x" access control policy
104189  */
104190 #define XRDC2_PAC_PDAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
104191 
104192 #define XRDC2_PAC_PDAC_W1_D14ACP_MASK            (0x1C0000U)
104193 #define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT           (18U)
104194 /*! D14ACP - Domain "x" access control policy
104195  */
104196 #define XRDC2_PAC_PDAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
104197 
104198 #define XRDC2_PAC_PDAC_W1_D15ACP_MASK            (0xE00000U)
104199 #define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT           (21U)
104200 /*! D15ACP - Domain "x" access control policy
104201  */
104202 #define XRDC2_PAC_PDAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
104203 
104204 #define XRDC2_PAC_PDAC_W1_EAL_MASK               (0x3000000U)
104205 #define XRDC2_PAC_PDAC_W1_EAL_SHIFT              (24U)
104206 /*! EAL - Exclusive Access Lock
104207  *  0b00..Lock disabled.
104208  *  0b01..Lock disabled until next reset.
104209  *  0b10..Lock enabled, lock state = available.
104210  *  0b11..Lock enabled, lock state = not available.
104211  */
104212 #define XRDC2_PAC_PDAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
104213 
104214 #define XRDC2_PAC_PDAC_W1_DL2_MASK               (0x60000000U)
104215 #define XRDC2_PAC_PDAC_W1_DL2_SHIFT              (29U)
104216 /*! DL2 - Descriptor Lock
104217  *  0b00..Lock disabled, descriptor registers can be written..
104218  *  0b01..Lock disabled until the next reset, descriptor registers can be written..
104219  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written..
104220  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
104221  */
104222 #define XRDC2_PAC_PDAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
104223 
104224 #define XRDC2_PAC_PDAC_W1_VLD_MASK               (0x80000000U)
104225 #define XRDC2_PAC_PDAC_W1_VLD_SHIFT              (31U)
104226 /*! VLD - Valid
104227  *  0b0..The PDAC assignment is invalid.
104228  *  0b1..The PDAC assignment is valid.
104229  */
104230 #define XRDC2_PAC_PDAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)
104231 /*! @} */
104232 
104233 /* The count of XRDC2_PAC_PDAC_W1 */
104234 #define XRDC2_PAC_PDAC_W1_COUNT                  (8U)
104235 
104236 /* The count of XRDC2_PAC_PDAC_W1 */
104237 #define XRDC2_PAC_PDAC_W1_COUNT2                 (256U)
104238 
104239 /*! @name MRC_MRGD_W0 - Memory Region Descriptor */
104240 /*! @{ */
104241 
104242 #define XRDC2_MRC_MRGD_W0_SRTADDR_MASK           (0xFFFFF000U)
104243 #define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT          (12U)
104244 /*! SRTADDR - Start Address
104245  */
104246 #define XRDC2_MRC_MRGD_W0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)
104247 /*! @} */
104248 
104249 /* The count of XRDC2_MRC_MRGD_W0 */
104250 #define XRDC2_MRC_MRGD_W0_COUNT                  (32U)
104251 
104252 /* The count of XRDC2_MRC_MRGD_W0 */
104253 #define XRDC2_MRC_MRGD_W0_COUNT2                 (32U)
104254 
104255 /*! @name MRC_MRGD_W1 - Memory Region Descriptor */
104256 /*! @{ */
104257 
104258 #define XRDC2_MRC_MRGD_W1_SRTADDR_MASK           (0xFU)
104259 #define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT          (0U)
104260 /*! SRTADDR - Start Address
104261  */
104262 #define XRDC2_MRC_MRGD_W1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)
104263 /*! @} */
104264 
104265 /* The count of XRDC2_MRC_MRGD_W1 */
104266 #define XRDC2_MRC_MRGD_W1_COUNT                  (32U)
104267 
104268 /* The count of XRDC2_MRC_MRGD_W1 */
104269 #define XRDC2_MRC_MRGD_W1_COUNT2                 (32U)
104270 
104271 /*! @name MRC_MRGD_W2 - Memory Region Descriptor */
104272 /*! @{ */
104273 
104274 #define XRDC2_MRC_MRGD_W2_ENDADDR_MASK           (0xFFFFF000U)
104275 #define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT          (12U)
104276 /*! ENDADDR - End Address
104277  */
104278 #define XRDC2_MRC_MRGD_W2_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)
104279 /*! @} */
104280 
104281 /* The count of XRDC2_MRC_MRGD_W2 */
104282 #define XRDC2_MRC_MRGD_W2_COUNT                  (32U)
104283 
104284 /* The count of XRDC2_MRC_MRGD_W2 */
104285 #define XRDC2_MRC_MRGD_W2_COUNT2                 (32U)
104286 
104287 /*! @name MRC_MRGD_W3 - Memory Region Descriptor */
104288 /*! @{ */
104289 
104290 #define XRDC2_MRC_MRGD_W3_ENDADDR_MASK           (0xFU)
104291 #define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT          (0U)
104292 /*! ENDADDR - End Address
104293  */
104294 #define XRDC2_MRC_MRGD_W3_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)
104295 /*! @} */
104296 
104297 /* The count of XRDC2_MRC_MRGD_W3 */
104298 #define XRDC2_MRC_MRGD_W3_COUNT                  (32U)
104299 
104300 /* The count of XRDC2_MRC_MRGD_W3 */
104301 #define XRDC2_MRC_MRGD_W3_COUNT2                 (32U)
104302 
104303 /*! @name MRC_MRGD_W5 - Memory Region Descriptor */
104304 /*! @{ */
104305 
104306 #define XRDC2_MRC_MRGD_W5_D0ACP_MASK             (0x7U)
104307 #define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT            (0U)
104308 /*! D0ACP - Domain "x" access control policy
104309  */
104310 #define XRDC2_MRC_MRGD_W5_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
104311 
104312 #define XRDC2_MRC_MRGD_W5_D1ACP_MASK             (0x38U)
104313 #define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT            (3U)
104314 /*! D1ACP - Domain "x" access control policy
104315  */
104316 #define XRDC2_MRC_MRGD_W5_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
104317 
104318 #define XRDC2_MRC_MRGD_W5_D2ACP_MASK             (0x1C0U)
104319 #define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT            (6U)
104320 /*! D2ACP - Domain "x" access control policy
104321  */
104322 #define XRDC2_MRC_MRGD_W5_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
104323 
104324 #define XRDC2_MRC_MRGD_W5_D3ACP_MASK             (0xE00U)
104325 #define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT            (9U)
104326 /*! D3ACP - Domain "x" access control policy
104327  */
104328 #define XRDC2_MRC_MRGD_W5_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
104329 
104330 #define XRDC2_MRC_MRGD_W5_D4ACP_MASK             (0x7000U)
104331 #define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT            (12U)
104332 /*! D4ACP - Domain "x" access control policy
104333  */
104334 #define XRDC2_MRC_MRGD_W5_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
104335 
104336 #define XRDC2_MRC_MRGD_W5_D5ACP_MASK             (0x38000U)
104337 #define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT            (15U)
104338 /*! D5ACP - Domain "x" access control policy
104339  */
104340 #define XRDC2_MRC_MRGD_W5_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
104341 
104342 #define XRDC2_MRC_MRGD_W5_D6ACP_MASK             (0x1C0000U)
104343 #define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT            (18U)
104344 /*! D6ACP - Domain "x" access control policy
104345  */
104346 #define XRDC2_MRC_MRGD_W5_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
104347 
104348 #define XRDC2_MRC_MRGD_W5_D7ACP_MASK             (0xE00000U)
104349 #define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT            (21U)
104350 /*! D7ACP - Domain "x" access control policy
104351  */
104352 #define XRDC2_MRC_MRGD_W5_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
104353 
104354 #define XRDC2_MRC_MRGD_W5_EALO_MASK              (0xF000000U)
104355 #define XRDC2_MRC_MRGD_W5_EALO_SHIFT             (24U)
104356 /*! EALO - Exclusive Access Lock Owner
104357  */
104358 #define XRDC2_MRC_MRGD_W5_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)
104359 /*! @} */
104360 
104361 /* The count of XRDC2_MRC_MRGD_W5 */
104362 #define XRDC2_MRC_MRGD_W5_COUNT                  (32U)
104363 
104364 /* The count of XRDC2_MRC_MRGD_W5 */
104365 #define XRDC2_MRC_MRGD_W5_COUNT2                 (32U)
104366 
104367 /*! @name MRC_MRGD_W6 - Memory Region Descriptor */
104368 /*! @{ */
104369 
104370 #define XRDC2_MRC_MRGD_W6_D8ACP_MASK             (0x7U)
104371 #define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT            (0U)
104372 /*! D8ACP - Domain "x" access control policy
104373  */
104374 #define XRDC2_MRC_MRGD_W6_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
104375 
104376 #define XRDC2_MRC_MRGD_W6_D9ACP_MASK             (0x38U)
104377 #define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT            (3U)
104378 /*! D9ACP - Domain "x" access control policy
104379  */
104380 #define XRDC2_MRC_MRGD_W6_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
104381 
104382 #define XRDC2_MRC_MRGD_W6_D10ACP_MASK            (0x1C0U)
104383 #define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT           (6U)
104384 /*! D10ACP - Domain "x" access control policy
104385  */
104386 #define XRDC2_MRC_MRGD_W6_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
104387 
104388 #define XRDC2_MRC_MRGD_W6_D11ACP_MASK            (0xE00U)
104389 #define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT           (9U)
104390 /*! D11ACP - Domain "x" access control policy
104391  */
104392 #define XRDC2_MRC_MRGD_W6_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
104393 
104394 #define XRDC2_MRC_MRGD_W6_D12ACP_MASK            (0x7000U)
104395 #define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT           (12U)
104396 /*! D12ACP - Domain "x" access control policy
104397  */
104398 #define XRDC2_MRC_MRGD_W6_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
104399 
104400 #define XRDC2_MRC_MRGD_W6_D13ACP_MASK            (0x38000U)
104401 #define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT           (15U)
104402 /*! D13ACP - Domain "x" access control policy
104403  */
104404 #define XRDC2_MRC_MRGD_W6_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
104405 
104406 #define XRDC2_MRC_MRGD_W6_D14ACP_MASK            (0x1C0000U)
104407 #define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT           (18U)
104408 /*! D14ACP - Domain "x" access control policy
104409  */
104410 #define XRDC2_MRC_MRGD_W6_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
104411 
104412 #define XRDC2_MRC_MRGD_W6_D15ACP_MASK            (0xE00000U)
104413 #define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT           (21U)
104414 /*! D15ACP - Domain "x" access control policy
104415  */
104416 #define XRDC2_MRC_MRGD_W6_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
104417 
104418 #define XRDC2_MRC_MRGD_W6_EAL_MASK               (0x3000000U)
104419 #define XRDC2_MRC_MRGD_W6_EAL_SHIFT              (24U)
104420 /*! EAL - Exclusive Access Lock
104421  *  0b00..Lock disabled.
104422  *  0b01..Lock disabled until next reset.
104423  *  0b10..Lock enabled, lock state = available.
104424  *  0b11..Lock enabled, lock state = not available.
104425  */
104426 #define XRDC2_MRC_MRGD_W6_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
104427 
104428 #define XRDC2_MRC_MRGD_W6_DL2_MASK               (0x60000000U)
104429 #define XRDC2_MRC_MRGD_W6_DL2_SHIFT              (29U)
104430 /*! DL2 - Descriptor Lock
104431  *  0b00..Lock disabled, descriptor registers can be written.
104432  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
104433  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
104434  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
104435  */
104436 #define XRDC2_MRC_MRGD_W6_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
104437 
104438 #define XRDC2_MRC_MRGD_W6_VLD_MASK               (0x80000000U)
104439 #define XRDC2_MRC_MRGD_W6_VLD_SHIFT              (31U)
104440 /*! VLD - Valid
104441  *  0b0..The MRGD is invalid.
104442  *  0b1..The MRGD is valid.
104443  */
104444 #define XRDC2_MRC_MRGD_W6_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)
104445 /*! @} */
104446 
104447 /* The count of XRDC2_MRC_MRGD_W6 */
104448 #define XRDC2_MRC_MRGD_W6_COUNT                  (32U)
104449 
104450 /* The count of XRDC2_MRC_MRGD_W6 */
104451 #define XRDC2_MRC_MRGD_W6_COUNT2                 (32U)
104452 
104453 
104454 /*!
104455  * @}
104456  */ /* end of group XRDC2_Register_Masks */
104457 
104458 
104459 /* XRDC2 - Peripheral instance base addresses */
104460 /** Peripheral XRDC2_D0 base address */
104461 #define XRDC2_D0_BASE                            (0x40CE0000u)
104462 /** Peripheral XRDC2_D0 base pointer */
104463 #define XRDC2_D0                                 ((XRDC2_Type *)XRDC2_D0_BASE)
104464 /** Peripheral XRDC2_D1 base address */
104465 #define XRDC2_D1_BASE                            (0x40CD0000u)
104466 /** Peripheral XRDC2_D1 base pointer */
104467 #define XRDC2_D1                                 ((XRDC2_Type *)XRDC2_D1_BASE)
104468 /** Array initializer of XRDC2 peripheral base addresses */
104469 #define XRDC2_BASE_ADDRS                         { XRDC2_D0_BASE, XRDC2_D1_BASE }
104470 /** Array initializer of XRDC2 peripheral base pointers */
104471 #define XRDC2_BASE_PTRS                          { XRDC2_D0, XRDC2_D1 }
104472 
104473 /*!
104474  * @}
104475  */ /* end of group XRDC2_Peripheral_Access_Layer */
104476 
104477 
104478 /*
104479 ** End of section using anonymous unions
104480 */
104481 
104482 #if defined(__ARMCC_VERSION)
104483   #if (__ARMCC_VERSION >= 6010050)
104484     #pragma clang diagnostic pop
104485   #else
104486     #pragma pop
104487   #endif
104488 #elif defined(__CWCC__)
104489   #pragma pop
104490 #elif defined(__GNUC__)
104491   /* leave anonymous unions enabled */
104492 #elif defined(__IAR_SYSTEMS_ICC__)
104493   #pragma language=default
104494 #else
104495   #error Not supported compiler type
104496 #endif
104497 
104498 /*!
104499  * @}
104500  */ /* end of group Peripheral_access_layer */
104501 
104502 
104503 /* ----------------------------------------------------------------------------
104504    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
104505    ---------------------------------------------------------------------------- */
104506 
104507 /*!
104508  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
104509  * @{
104510  */
104511 
104512 #if defined(__ARMCC_VERSION)
104513   #if (__ARMCC_VERSION >= 6010050)
104514     #pragma clang system_header
104515   #endif
104516 #elif defined(__IAR_SYSTEMS_ICC__)
104517   #pragma system_include
104518 #endif
104519 
104520 /**
104521  * @brief Mask and left-shift a bit field value for use in a register bit range.
104522  * @param field Name of the register bit field.
104523  * @param value Value of the bit field.
104524  * @return Masked and shifted value.
104525  */
104526 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
104527 /**
104528  * @brief Mask and right-shift a register value to extract a bit field value.
104529  * @param field Name of the register bit field.
104530  * @param value Value of the register.
104531  * @return Masked and shifted bit field value.
104532  */
104533 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
104534 
104535 /*!
104536  * @}
104537  */ /* end of group Bit_Field_Generic_Macros */
104538 
104539 
104540 /* ----------------------------------------------------------------------------
104541    -- SDK Compatibility
104542    ---------------------------------------------------------------------------- */
104543 
104544 /*!
104545  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
104546  * @{
104547  */
104548 
104549 /* No SDK compatibility issues. */
104550 
104551 /*!
104552  * @}
104553  */ /* end of group SDK_Compatibility_Symbols */
104554 
104555 
104556 #endif  /* _MIMXRT1176_CM4_H_ */
104557 
104558