1 /*
2  * Copyright 2019 Broadcom
3  * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 #ifndef ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_
8 #define ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_
9 
10 /* Following Memory types supported through MAIR encodings can be passed
11  * by user through "attrs"(attributes) field of specified memory region.
12  * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
13  * so that we can provide encodings upto 7 if needed in future.
14  */
15 #define MT_TYPE_MASK		0x7U
16 #define MT_TYPE(attr)		(attr & MT_TYPE_MASK)
17 #define MT_DEVICE_nGnRnE	0U
18 #define MT_DEVICE_nGnRE		1U
19 #define MT_DEVICE_GRE		2U
20 #define MT_NORMAL_NC		3U
21 #define MT_NORMAL		4U
22 #define MT_NORMAL_WT		5U
23 
24 #define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_nGnRnE * 8)) |	\
25 				(0x04 << (MT_DEVICE_nGnRE * 8))   |	\
26 				(0x0c << (MT_DEVICE_GRE * 8))     |	\
27 				(0x44 << (MT_NORMAL_NC * 8))      |	\
28 				(0xffUL << (MT_NORMAL * 8))	  |	\
29 				(0xbbUL << (MT_NORMAL_WT * 8)))
30 
31 /* More flags from user's perpective are supported using remaining bits
32  * of "attrs" field, i.e. attrs[31:3], underlying code will take care
33  * of setting PTE fields correctly.
34  *
35  * current usage of attrs[31:3] is:
36  * attrs[3] : Access Permissions
37  * attrs[4] : Memory access from secure/ns state
38  * attrs[5] : Execute Permissions privileged mode (PXN)
39  * attrs[6] : Execute Permissions unprivileged mode (UXN)
40  * attrs[7] : Mirror RO/RW permissions to EL0
41  * attrs[8] : Overwrite existing mapping if any
42  *
43  */
44 #define MT_PERM_SHIFT		3U
45 #define MT_SEC_SHIFT		4U
46 #define MT_P_EXECUTE_SHIFT	5U
47 #define MT_U_EXECUTE_SHIFT	6U
48 #define MT_RW_AP_SHIFT		7U
49 #define MT_NO_OVERWRITE_SHIFT	8U
50 
51 #define MT_RO			(0U << MT_PERM_SHIFT)
52 #define MT_RW			(1U << MT_PERM_SHIFT)
53 
54 #define MT_RW_AP_ELx		(1U << MT_RW_AP_SHIFT)
55 #define MT_RW_AP_EL_HIGHER	(0U << MT_RW_AP_SHIFT)
56 
57 #define MT_SECURE		(0U << MT_SEC_SHIFT)
58 #define MT_NS			(1U << MT_SEC_SHIFT)
59 
60 #define MT_P_EXECUTE		(0U << MT_P_EXECUTE_SHIFT)
61 #define MT_P_EXECUTE_NEVER	(1U << MT_P_EXECUTE_SHIFT)
62 
63 #define MT_U_EXECUTE		(0U << MT_U_EXECUTE_SHIFT)
64 #define MT_U_EXECUTE_NEVER	(1U << MT_U_EXECUTE_SHIFT)
65 
66 #define MT_NO_OVERWRITE		(1U << MT_NO_OVERWRITE_SHIFT)
67 
68 #define MT_P_RW_U_RW		(MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
69 #define MT_P_RW_U_NA		(MT_RW | MT_RW_AP_EL_HIGHER  | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
70 #define MT_P_RO_U_RO		(MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
71 #define MT_P_RO_U_NA		(MT_RO | MT_RW_AP_EL_HIGHER  | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
72 #define MT_P_RO_U_RX		(MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE)
73 #define MT_P_RX_U_RX		(MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE)
74 #define MT_P_RX_U_NA		(MT_RO | MT_RW_AP_EL_HIGHER  | MT_P_EXECUTE | MT_U_EXECUTE_NEVER)
75 
76 #ifdef CONFIG_ARMV8_A_NS
77 #define MT_DEFAULT_SECURE_STATE	MT_NS
78 #else
79 #define MT_DEFAULT_SECURE_STATE	MT_SECURE
80 #endif
81 
82 /*
83  * PTE descriptor can be Block descriptor or Table descriptor
84  * or Page descriptor.
85  */
86 #define PTE_DESC_TYPE_MASK	3U
87 #define PTE_BLOCK_DESC		1U
88 #define PTE_TABLE_DESC		3U
89 #define PTE_PAGE_DESC		3U
90 #define PTE_INVALID_DESC	0U
91 
92 /*
93  * Block and Page descriptor attributes fields
94  */
95 #define PTE_BLOCK_DESC_MEMTYPE(x)	(x << 2)
96 #define PTE_BLOCK_DESC_NS		(1ULL << 5)
97 #define PTE_BLOCK_DESC_AP_ELx		(1ULL << 6)
98 #define PTE_BLOCK_DESC_AP_EL_HIGHER	(0ULL << 6)
99 #define PTE_BLOCK_DESC_AP_RO		(1ULL << 7)
100 #define PTE_BLOCK_DESC_AP_RW		(0ULL << 7)
101 #define PTE_BLOCK_DESC_NON_SHARE	(0ULL << 8)
102 #define PTE_BLOCK_DESC_OUTER_SHARE	(2ULL << 8)
103 #define PTE_BLOCK_DESC_INNER_SHARE	(3ULL << 8)
104 #define PTE_BLOCK_DESC_AF		(1ULL << 10)
105 #define PTE_BLOCK_DESC_NG		(1ULL << 11)
106 #define PTE_BLOCK_DESC_PXN		(1ULL << 53)
107 #define PTE_BLOCK_DESC_UXN		(1ULL << 54)
108 
109 /*
110  * TCR definitions.
111  */
112 #define TCR_EL1_IPS_SHIFT	32U
113 #define TCR_EL2_PS_SHIFT	16U
114 #define TCR_EL3_PS_SHIFT	16U
115 
116 #define TCR_T0SZ_SHIFT		0U
117 #define TCR_T0SZ(x)		((64 - (x)) << TCR_T0SZ_SHIFT)
118 
119 #define TCR_IRGN_NC		(0ULL << 8)
120 #define TCR_IRGN_WBWA		(1ULL << 8)
121 #define TCR_IRGN_WT		(2ULL << 8)
122 #define TCR_IRGN_WBNWA		(3ULL << 8)
123 #define TCR_IRGN_MASK		(3ULL << 8)
124 #define TCR_ORGN_NC		(0ULL << 10)
125 #define TCR_ORGN_WBWA		(1ULL << 10)
126 #define TCR_ORGN_WT		(2ULL << 10)
127 #define TCR_ORGN_WBNWA		(3ULL << 10)
128 #define TCR_ORGN_MASK		(3ULL << 10)
129 #define TCR_SHARED_NON		(0ULL << 12)
130 #define TCR_SHARED_OUTER	(2ULL << 12)
131 #define TCR_SHARED_INNER	(3ULL << 12)
132 #define TCR_TG0_4K		(0ULL << 14)
133 #define TCR_TG0_64K		(1ULL << 14)
134 #define TCR_TG0_16K		(2ULL << 14)
135 #define TCR_EPD1_DISABLE	(1ULL << 23)
136 
137 #define TCR_PS_BITS_4GB		0x0ULL
138 #define TCR_PS_BITS_64GB	0x1ULL
139 #define TCR_PS_BITS_1TB		0x2ULL
140 #define TCR_PS_BITS_4TB		0x3ULL
141 #define TCR_PS_BITS_16TB	0x4ULL
142 #define TCR_PS_BITS_256TB	0x5ULL
143 
144 #ifndef _ASMLANGUAGE
145 
146 /* Region definition data structure */
147 struct arm_mmu_region {
148 	/* Region Base Physical Address */
149 	uintptr_t base_pa;
150 	/* Region Base Virtual Address */
151 	uintptr_t base_va;
152 	/* Region size */
153 	size_t size;
154 	/* Region Name */
155 	const char *name;
156 	/* Region Attributes */
157 	uint32_t attrs;
158 };
159 
160 /* MMU configuration data structure */
161 struct arm_mmu_config {
162 	/* Number of regions */
163 	unsigned int num_regions;
164 	/* Regions */
165 	const struct arm_mmu_region *mmu_regions;
166 };
167 
168 struct arm_mmu_ptables {
169 	uint64_t *base_xlat_table;
170 };
171 
172 /* Convenience macros to represent the ARMv8-A-specific
173  * configuration for memory access permission and
174  * cache-ability attribution.
175  */
176 
177 #define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
178 	{\
179 		.name = _name, \
180 		.base_pa = _base_pa, \
181 		.base_va = _base_va, \
182 		.size = _size, \
183 		.attrs = _attrs, \
184 	}
185 
186 #define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
187 	MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
188 
189 /* Reference to the MMU configuration.
190  *
191  * This struct is defined and populated for each SoC (in the SoC definition),
192  * and holds the build-time configuration information for the fixed MMU
193  * regions enabled during kernel initialization.
194  */
195 extern const struct arm_mmu_config mmu_config;
196 
197 struct k_thread;
198 void z_arm64_thread_pt_init(struct k_thread *thread);
199 void z_arm64_swap_ptables(struct k_thread *thread);
200 
201 #endif /* _ASMLANGUAGE */
202 
203 #endif /* ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_ */
204