1 /*******************************************************************************
2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * PolarFire SoC MSS USB Driver Stack
7 * USB Core Interface Layer (USB-CIFL)
8 * USB-CIF.
9 *
10 * This file provides interfaces to perform register bit level
11 * I\O operations which are independent of USB Device/host mode.
12 *
13 */
14
15 #ifndef __MSS_USB_COMMON_REG_IO_H_
16 #define __MSS_USB_COMMON_REG_IO_H_
17
18 #include <stdint.h>
19 #include "mss_usb_common_cif.h"
20 #include "mss_usb_core_regs.h"
21
22 #define __INLINE inline
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /*-------------------------------------------------------------------------*//**
29 * Common function for DEVICE and HOST mode.
30 */
31
32 /*-------------------------------------------------------------------------*//**
33 SOFT_RST register related APIs
34 */
35 static __INLINE void
MSS_USB_CIF_soft_reset(void)36 MSS_USB_CIF_soft_reset
37 (
38 void
39 )
40 {
41 volatile uint8_t soft_reset;
42
43 USB->SOFT_RST = SOFT_RESET_REG_MASK;
44 do {
45 soft_reset = USB->SOFT_RST;
46 } while (soft_reset != 0x00u);
47 }
48
49 /*-------------------------------------------------------------------------*//**
50 POWER register related APIs
51 */
52 static __INLINE void
MSS_USB_CIF_enable_hs_mode(void)53 MSS_USB_CIF_enable_hs_mode
54 (
55 void
56 )
57 {
58 USB->POWER |= POWER_REG_ENABLE_HS_MASK;
59 }
60
61 static __INLINE void
MSS_USB_CIF_disable_hs_mode(void)62 MSS_USB_CIF_disable_hs_mode
63 (
64 void
65 )
66 {
67 USB->POWER &= ~POWER_REG_ENABLE_HS_MASK;
68 }
69
70 /*-------------------------------------------------------------------------*//**
71 Read USB interrupt register to know which interrupt has occurred.
72 */
73 static __INLINE uint8_t
MSS_USB_CIF_read_irq_reg(void)74 MSS_USB_CIF_read_irq_reg
75 (
76 void
77 )
78 {
79 return (USB->USB_IRQ);
80 }
81
82 /*-------------------------------------------------------------------------*//**
83 EP IRQ related APIs
84 */
85 /* TX IRQ related APIs */
86 static __INLINE uint16_t
MSS_USB_CIF_read_tx_ep_irq_reg(void)87 MSS_USB_CIF_read_tx_ep_irq_reg
88 (
89 void
90 )
91 {
92 return (USB->TX_IRQ);
93 }
94
95 static __INLINE uint16_t
MSS_USB_CIF_read_rx_ep_irq_reg(void)96 MSS_USB_CIF_read_rx_ep_irq_reg
97 (
98 void
99 )
100 {
101 return (USB->RX_IRQ);
102 }
103
104 static __INLINE void
MSS_USB_CIF_clr_usb_irq_reg(void)105 MSS_USB_CIF_clr_usb_irq_reg
106 (
107 void
108 )
109 {
110 USB->USB_IRQ = 0u;
111 }
112
113 static __INLINE void
MSS_USB_CIF_tx_ep_enable_irq(mss_usb_ep_num_t ep_num)114 MSS_USB_CIF_tx_ep_enable_irq
115 (
116 mss_usb_ep_num_t ep_num
117 )
118 {
119 USB->TX_IRQ_ENABLE |= (uint16_t)(MSS_USB_WORD_BIT_0_MASK << (uint8_t)ep_num);
120 }
121
122
123 static __INLINE void
MSS_USB_CIF_tx_ep_disable_irq(mss_usb_ep_num_t ep_num)124 MSS_USB_CIF_tx_ep_disable_irq
125 (
126 mss_usb_ep_num_t ep_num
127 )
128 {
129 USB->TX_IRQ_ENABLE &= (uint16_t)(~(MSS_USB_WORD_BIT_0_MASK << (uint8_t)ep_num));
130 }
131
132 static __INLINE void
MSS_USB_CIF_tx_ep_disable_irq_all(void)133 MSS_USB_CIF_tx_ep_disable_irq_all
134 (
135 void
136 )
137 {
138 /* Keep D0, CEP interrupt bit unaltered.*/
139 USB->TX_IRQ_ENABLE = (USB->TX_IRQ_ENABLE & TX_IRQ_ENABLE_REG_CEP_MASK);
140 }
141
142 static __INLINE void
MSS_USB_CIF_rx_ep_enable_irq(mss_usb_ep_num_t ep_num)143 MSS_USB_CIF_rx_ep_enable_irq
144 (
145 mss_usb_ep_num_t ep_num
146 )
147 {
148 USB->RX_IRQ_ENABLE |= (uint16_t)(MSS_USB_WORD_BIT_0_MASK << (uint8_t)ep_num);
149 }
150
151 static __INLINE void
MSS_USB_CIF_rx_ep_disable_irq(mss_usb_ep_num_t ep_num)152 MSS_USB_CIF_rx_ep_disable_irq
153 (
154 mss_usb_ep_num_t ep_num
155 )
156 {
157 USB->RX_IRQ_ENABLE &= (uint16_t)(~(MSS_USB_WORD_BIT_0_MASK << (uint8_t)ep_num));
158 }
159
160 static __INLINE void
MSS_USB_CIF_rx_ep_disable_irq_all(void)161 MSS_USB_CIF_rx_ep_disable_irq_all
162 (
163 void
164 )
165 {
166 USB->RX_IRQ_ENABLE = 0u ;
167 }
168
169 /*-------------------------------------------------------------------------*//**
170 FRAME register related APIs
171 */
172 static __INLINE uint16_t
MSS_USB_CIF_get_last_frame_nbr(void)173 MSS_USB_CIF_get_last_frame_nbr
174 (
175 void
176 )
177 {
178 return (USB->FRAME);
179 }
180
181 /*-------------------------------------------------------------------------*//**
182 DEVCTL register related APIs
183 */
184 static __INLINE mss_usb_core_mode_t
MSS_USB_CIF_get_mode(void)185 MSS_USB_CIF_get_mode
186 (
187 void
188 )
189 {
190 return (((USB->DEV_CTRL & DEV_CTRL_HOST_MODE_MASK) ?
191 MSS_USB_CORE_MODE_HOST : MSS_USB_CORE_MODE_DEVICE));
192 }
193
194 static __INLINE mss_usb_vbus_level_t
MSS_USB_CIF_get_vbus_level(void)195 MSS_USB_CIF_get_vbus_level
196 (
197 void
198 )
199 {
200 uint8_t vbus;
201 mss_usb_vbus_level_t ret_val = VBUS_BLOW_SESSIONEND;
202
203 vbus = (USB->DEV_CTRL & DEV_CTRL_VBUS_MASK);
204
205 switch (vbus)
206 {
207 case VBUS_BELOW_SESSION_END:
208 ret_val = VBUS_BLOW_SESSIONEND;
209 break;
210 case VBUS_ABOVE_SESSION_END:
211 ret_val = VBUS_ABV_SESSIONEND_BLOW_AVALID;
212 break;
213 case VBUS_ABOVE_AVALID:
214 ret_val = VBUS_ABV_AVALID_BLOW_VB_VALID;
215 break;
216 case VBUS_ABOVE_VBUS_VALID:
217 ret_val = VBUS_ABV_VB_VALID;
218 break;
219 default:
220 /* Empty */
221 break;
222
223 }
224 return ret_val;
225 }
226
227 static __INLINE mss_usb_device_role_t
MSS_USB_CIF_get_role(void)228 MSS_USB_CIF_get_role
229 (
230 void
231 )
232 {
233 /* TODO:only valid when session bit is set */
234 return (((USB->DEV_CTRL & DEV_CTRL_B_DEVICE_MASK) ?
235 MSS_USB_DEVICE_ROLE_DEVICE_B : MSS_USB_DEVICE_ROLE_DEVICE_A));
236 }
237
238 static __INLINE uint8_t
MSS_USB_CIF_is_session_on(void)239 MSS_USB_CIF_is_session_on
240 (
241 void
242 )
243 {
244 /* TODO:only valid when session bit is set */
245 return (((USB->DEV_CTRL & DEV_CTRL_SESSION_MASK) ?
246 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
247 }
248
MSS_USB_CIF_start_session(void)249 static __INLINE void MSS_USB_CIF_start_session(void)
250 {
251 USB->DEV_CTRL |= DEV_CTRL_SESSION_MASK;
252 }
MSS_USB_CIF_stop_session(void)253 static __INLINE void MSS_USB_CIF_stop_session(void)
254 {
255 USB->DEV_CTRL &= ~DEV_CTRL_SESSION_MASK;
256 }
257
258 /*-------------------------------------------------------------------------*//**
259 INDEXED registers
260 */
261
262 /*-------------------------------------------------------------------------*//**
263 CSR0L register related APIs
264 */
265 static __INLINE uint8_t
MSS_USB_CIF_cep_is_rxpktrdy(void)266 MSS_USB_CIF_cep_is_rxpktrdy
267 (
268 void
269 )
270 {
271 return (((USB->INDEXED_CSR.DEVICE_EP0.CSR0 & CSR0L_DEV_RX_PKT_RDY_MASK) ?
272 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
273 }
274
275 static __INLINE void
MSS_USB_CIF_cep_set_txpktrdy(void)276 MSS_USB_CIF_cep_set_txpktrdy
277 (
278 void
279 )
280 {
281 USB->INDEXED_CSR.DEVICE_EP0.CSR0 |= CSR0L_DEV_TX_PKT_RDY_MASK;
282 }
283
284 static __INLINE void
MSS_USB_CIF_cep_clr_stall_sent(void)285 MSS_USB_CIF_cep_clr_stall_sent
286 (
287 void
288 )
289 {
290 USB->INDEXED_CSR.DEVICE_EP0.CSR0 &= ~CSR0L_DEV_STALL_SENT_MASK;
291 }
292
293 static __INLINE uint8_t
MSS_USB_CIF_cep_is_stall_sent(void)294 MSS_USB_CIF_cep_is_stall_sent
295 (
296 void
297 )
298 {
299 return (((USB->INDEXED_CSR.DEVICE_EP0.CSR0 & CSR0L_DEV_STALL_SENT_MASK) ?
300 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
301 }
302
303 static __INLINE void
MSS_USB_CIF_cep_clr_setupend(void)304 MSS_USB_CIF_cep_clr_setupend
305 (
306 void
307 )
308 {
309 /* Setting SERVICED_SETUP_END bit clears SetupEnd bit */
310 USB->INDEXED_CSR.DEVICE_EP0.CSR0 |= CSR0L_DEV_SERVICED_SETUP_END_MASK;
311 }
312 static __INLINE uint8_t
MSS_USB_CIF_cep_is_setupend(void)313 MSS_USB_CIF_cep_is_setupend
314 (
315 void
316 )
317 {
318 return (((USB->INDEXED_CSR.DEVICE_EP0.CSR0 & CSR0L_DEV_SETUP_END_MASK) ?
319 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
320 }
321
322 static __INLINE void
MSS_USB_CIF_cep_reset_csr0_reg(void)323 MSS_USB_CIF_cep_reset_csr0_reg
324 (
325 void
326 )
327 {
328 /* load the reset value for the register */
329 USB->INDEXED_CSR.DEVICE_EP0.CSR0 = 0u;
330 }
331
332 /*-------------------------------------------------------------------------*//**
333 CNTRH0 register related APIs
334 */
335 static __INLINE uint8_t
MSS_USB_CIF_cep_rx_byte_count(void)336 MSS_USB_CIF_cep_rx_byte_count
337 (
338 void
339 )
340 {
341 /* TODO:confirm CSR0.D0 bit before returning */
342 return (USB->INDEXED_CSR.DEVICE_EP0.COUNT0 & COUNT0_REG_MASK);
343 }
344
345 /*-------------------------------------------------------------------------*//**
346 TXMAXP register related APIs
347 */
348 static __INLINE void
MSS_USB_CIF_tx_ep_set_max_pkt(mss_usb_ep_num_t ep_num,mss_usb_xfr_type_t xfr_type,uint16_t max_pkt_size,uint8_t num_usb_pkt)349 MSS_USB_CIF_tx_ep_set_max_pkt
350 (
351 mss_usb_ep_num_t ep_num,
352 mss_usb_xfr_type_t xfr_type,
353 uint16_t max_pkt_size,
354 uint8_t num_usb_pkt
355 )
356 {
357 /* TODO:make sure that there is no data in FIFO before writing into the maxP
358 reg
359 */
360 if ((ep_num > MSS_USB_CEP) && ((max_pkt_size % 8) == 0u) && (num_usb_pkt > 0u))
361 {
362 if((num_usb_pkt > 31u))
363 {
364 /* not allowed */
365 }
366 else
367 {
368 USB->ENDPOINT[ep_num].TX_MAX_P = 0u;
369 USB->ENDPOINT[ep_num].TX_MAX_P = num_usb_pkt - 1u;
370 USB->ENDPOINT[ep_num].TX_MAX_P <<= TX_MAX_P_REG_NUM_USB_PKT_SHIFT;
371 USB->ENDPOINT[ep_num].TX_MAX_P |= (max_pkt_size);
372 }
373 }
374 }
375
376 /*-------------------------------------------------------------------------*//**
377 TXCSRL register related APIs
378 */
379 static __INLINE void
MSS_USB_CIF_tx_ep_set_txpktrdy(mss_usb_ep_num_t ep_num)380 MSS_USB_CIF_tx_ep_set_txpktrdy
381 (
382 mss_usb_ep_num_t ep_num
383 )
384 {
385 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRL_REG_EPN_TX_PKT_RDY_MASK;
386 }
387
388 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_txpktrdy(mss_usb_ep_num_t ep_num)389 MSS_USB_CIF_tx_ep_is_txpktrdy
390 (
391 mss_usb_ep_num_t ep_num
392 )
393 {
394 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRL_REG_EPN_TX_PKT_RDY_MASK) ?
395 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
396 }
397
398 static __INLINE void
MSS_USB_CIF_tx_ep_set_send_stall_bit(mss_usb_ep_num_t ep_num)399 MSS_USB_CIF_tx_ep_set_send_stall_bit
400 (
401 mss_usb_ep_num_t ep_num
402 )
403 {
404 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRL_REG_EPN_SEND_STALL_MASK;
405 }
406
407 static __INLINE void
MSS_USB_CIF_tx_ep_clr_send_stall_bit(mss_usb_ep_num_t ep_num)408 MSS_USB_CIF_tx_ep_clr_send_stall_bit
409 (
410 mss_usb_ep_num_t ep_num
411 )
412 {
413 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRL_REG_EPN_SEND_STALL_MASK;
414 }
415
416 static __INLINE void
MSS_USB_CIF_tx_ep_clr_stall_sent_bit(mss_usb_ep_num_t ep_num)417 MSS_USB_CIF_tx_ep_clr_stall_sent_bit
418 (
419 mss_usb_ep_num_t ep_num
420 )
421 {
422 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRL_REG_EPN_STALL_SENT_MASK;
423 }
424
425 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_stall_sent_bit(mss_usb_ep_num_t ep_num)426 MSS_USB_CIF_tx_ep_is_stall_sent_bit
427 (
428 mss_usb_ep_num_t ep_num
429 )
430 {
431 return (uint8_t)(((USB->ENDPOINT[ep_num].TX_CSR & TxCSRL_REG_EPN_STALL_SENT_MASK) ?
432 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
433 }
434
435 static __INLINE void
MSS_USB_CIF_tx_ep_clr_data_tog(mss_usb_ep_num_t ep_num)436 MSS_USB_CIF_tx_ep_clr_data_tog
437 (
438 mss_usb_ep_num_t ep_num
439 )
440 {
441 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRL_REG_EPN_CLR_DATA_TOG_MASK;
442 }
443
444 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_isoincomp(mss_usb_ep_num_t ep_num)445 MSS_USB_CIF_tx_ep_is_isoincomp
446 (
447 mss_usb_ep_num_t ep_num
448 )
449 {
450 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRL_REG_EPN_ISO_INCOMP_TX_MASK) ?
451 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
452 }
453
454 /*-------------------------------------------------------------------------*//**
455 TXCSRH register related APIs
456 */
457 static __INLINE void
MSS_USB_CIF_tx_ep_set_dma_mode1(mss_usb_ep_num_t ep_num)458 MSS_USB_CIF_tx_ep_set_dma_mode1
459 (
460 mss_usb_ep_num_t ep_num
461 )
462 {
463 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_DMA_MODE_MASK;
464 }
465
466 static __INLINE void
MSS_USB_CIF_tx_ep_set_dma_mode0(mss_usb_ep_num_t ep_num)467 MSS_USB_CIF_tx_ep_set_dma_mode0
468 (
469 mss_usb_ep_num_t ep_num
470 )
471 {
472 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_DMA_MODE_MASK;
473 }
474
475 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_get_dma_mode(mss_usb_ep_num_t ep_num)476 MSS_USB_CIF_tx_ep_get_dma_mode
477 (
478 mss_usb_ep_num_t ep_num
479 )
480 {
481 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRH_REG_EPN_DMA_MODE_MASK) ?
482 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
483 }
484
485 static __INLINE void
MSS_USB_CIF_tx_ep_set_force_data_tog(mss_usb_ep_num_t ep_num)486 MSS_USB_CIF_tx_ep_set_force_data_tog
487 (
488 mss_usb_ep_num_t ep_num
489 )
490 {
491 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_FRC_DAT_TOG_MASK;
492 }
493
494 static __INLINE void
MSS_USB_CIF_tx_ep_clr_force_data_tog(mss_usb_ep_num_t ep_num)495 MSS_USB_CIF_tx_ep_clr_force_data_tog
496 (
497 mss_usb_ep_num_t ep_num
498 )
499 {
500 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_FRC_DAT_TOG_MASK;
501 }
502
503 static __INLINE void
MSS_USB_CIF_tx_ep_enable_dma(mss_usb_ep_num_t ep_num)504 MSS_USB_CIF_tx_ep_enable_dma
505 (
506 mss_usb_ep_num_t ep_num
507 )
508 {
509 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_ENABLE_DMA_MASK;
510 }
511
512 static __INLINE void
MSS_USB_CIF_tx_ep_disable_dma(mss_usb_ep_num_t ep_num)513 MSS_USB_CIF_tx_ep_disable_dma
514 (
515 mss_usb_ep_num_t ep_num
516 )
517 {
518 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_ENABLE_DMA_MASK;
519 }
520
521 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_dma_enabled(mss_usb_ep_num_t ep_num)522 MSS_USB_CIF_tx_ep_is_dma_enabled
523 (
524 mss_usb_ep_num_t ep_num
525 )
526 {
527 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRH_REG_EPN_ENABLE_DMA_MASK) ?
528 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
529 }
530
531 static __INLINE void
MSS_USB_CIF_tx_ep_set_tx_mode(mss_usb_ep_num_t ep_num)532 MSS_USB_CIF_tx_ep_set_tx_mode
533 (
534 mss_usb_ep_num_t ep_num
535 )
536 {
537 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_TXRX_MODE_MASK;
538 }
539 static __INLINE void
MSS_USB_CIF_tx_ep_set_rx_mode(mss_usb_ep_num_t ep_num)540 MSS_USB_CIF_tx_ep_set_rx_mode
541 (
542 mss_usb_ep_num_t ep_num
543 )
544 {
545 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_TXRX_MODE_MASK;
546 }
547
548 static __INLINE void
MSS_USB_CIF_tx_ep_enable_iso(mss_usb_ep_num_t ep_num)549 MSS_USB_CIF_tx_ep_enable_iso
550 (
551 mss_usb_ep_num_t ep_num
552 )
553 {
554 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_ENABLE_ISO_MASK;
555 }
556
557 static __INLINE void
MSS_USB_CIF_tx_ep_disable_iso(mss_usb_ep_num_t ep_num)558 MSS_USB_CIF_tx_ep_disable_iso
559 (
560 mss_usb_ep_num_t ep_num
561 )
562 {
563 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_ENABLE_ISO_MASK;
564 }
565
566 static __INLINE void
MSS_USB_CIF_tx_ep_set_autoset(mss_usb_ep_num_t ep_num)567 MSS_USB_CIF_tx_ep_set_autoset
568 (
569 mss_usb_ep_num_t ep_num
570 )
571 {
572 USB->ENDPOINT[ep_num].TX_CSR |= TxCSRH_REG_EPN_ENABLE_AUTOSET_MASK;
573 }
574 static __INLINE void
MSS_USB_CIF_tx_ep_clr_autoset(mss_usb_ep_num_t ep_num)575 MSS_USB_CIF_tx_ep_clr_autoset
576 (
577 mss_usb_ep_num_t ep_num
578 )
579 {
580 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRH_REG_EPN_ENABLE_AUTOSET_MASK;
581 }
582
583 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_autoset(mss_usb_ep_num_t ep_num)584 MSS_USB_CIF_tx_ep_is_autoset
585 (
586 mss_usb_ep_num_t ep_num
587 )
588 {
589 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRH_REG_EPN_ENABLE_AUTOSET_MASK) ?
590 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
591 }
592
593 static __INLINE uint8_t
MSS_USB_CIF_tx_ep_is_underrun(mss_usb_ep_num_t ep_num)594 MSS_USB_CIF_tx_ep_is_underrun
595 (
596 mss_usb_ep_num_t ep_num
597 )
598 {
599 return (((USB->ENDPOINT[ep_num].TX_CSR & TxCSRL_REG_EPN_UNDERRUN_MASK) ?
600 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
601 }
602
603 static __INLINE void
MSS_USB_CIF_tx_ep_clr_underrun(mss_usb_ep_num_t ep_num)604 MSS_USB_CIF_tx_ep_clr_underrun
605 (
606 mss_usb_ep_num_t ep_num
607 )
608 {
609 USB->ENDPOINT[ep_num].TX_CSR &= ~TxCSRL_REG_EPN_UNDERRUN_MASK;
610 }
611
612 static __INLINE void
MSS_USB_CIF_tx_ep_clr_csrreg(mss_usb_ep_num_t ep_num)613 MSS_USB_CIF_tx_ep_clr_csrreg
614 (
615 mss_usb_ep_num_t ep_num
616 )
617 {
618 USB->ENDPOINT[ep_num].TX_CSR = 0x0000U;
619 }
620
621 /*-------------------------------------------------------------------------*//**
622 RXMAXP register related APIs
623 */
624 static __INLINE void
MSS_USB_CIF_rx_ep_set_max_pkt(mss_usb_ep_num_t ep_num,mss_usb_xfr_type_t xfr_type,uint16_t max_pkt_size,uint8_t num_usb_pkt)625 MSS_USB_CIF_rx_ep_set_max_pkt
626 (
627 mss_usb_ep_num_t ep_num,
628 mss_usb_xfr_type_t xfr_type,
629 uint16_t max_pkt_size,
630 uint8_t num_usb_pkt
631 )
632 {
633 /* TODO:make sure that there is no data in FIFO before writing into the
634 maxP reg
635 */
636 if ((ep_num > MSS_USB_CEP) && (max_pkt_size > 0u) && ((max_pkt_size % 8) == 0u))
637 {
638 if ((num_usb_pkt > 31u))
639 {
640 /*not allowed*/
641 }
642 else
643 {
644 USB->ENDPOINT[ep_num].RX_MAX_P = 0u;
645 USB->ENDPOINT[ep_num].RX_MAX_P = num_usb_pkt - 1u;
646 USB->ENDPOINT[ep_num].RX_MAX_P <<= RX_MAX_P_REG_NUM_USB_PKT_SHIFT;
647 USB->ENDPOINT[ep_num].RX_MAX_P |= (max_pkt_size);
648 }
649 }
650 }
651
652 /*-------------------------------------------------------------------------*//**
653 RXCSRL register related APIs
654 */
655 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_rxpktrdy(mss_usb_ep_num_t ep_num)656 MSS_USB_CIF_rx_ep_is_rxpktrdy
657 (
658 mss_usb_ep_num_t ep_num
659 )
660 {
661 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_RX_PKT_RDY_MASK) ?
662 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
663 }
664
665 static __INLINE void
MSS_USB_CIF_rx_ep_clr_rxpktrdy(mss_usb_ep_num_t ep_num)666 MSS_USB_CIF_rx_ep_clr_rxpktrdy
667 (
668 mss_usb_ep_num_t ep_num
669 )
670 {
671 USB->ENDPOINT[ep_num].RX_CSR &= ~RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
672 }
673
674 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_overrun(mss_usb_ep_num_t ep_num)675 MSS_USB_CIF_rx_ep_is_overrun
676 (
677 mss_usb_ep_num_t ep_num
678 )
679 {
680 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_OVERRUN_MASK) ?
681 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
682 }
683
684 static __INLINE void
MSS_USB_CIF_rx_ep_clr_overrun(mss_usb_ep_num_t ep_num)685 MSS_USB_CIF_rx_ep_clr_overrun
686 (
687 mss_usb_ep_num_t ep_num
688 )
689 {
690 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
691
692 reg_val &= ~RxCSRL_REG_EPN_OVERRUN_MASK;
693 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
694 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
695 }
696
697 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_dataerr(mss_usb_ep_num_t ep_num)698 MSS_USB_CIF_rx_ep_is_dataerr
699 (
700 mss_usb_ep_num_t ep_num
701 )
702 {
703 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_DATA_ERR_MASK) ?
704 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
705 }
706
707 static __INLINE void
MSS_USB_CIF_rx_ep_set_send_stall_bit(mss_usb_ep_num_t ep_num)708 MSS_USB_CIF_rx_ep_set_send_stall_bit
709 (
710 mss_usb_ep_num_t ep_num
711 )
712 {
713 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_SEND_STALL_MASK |
714 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
715 }
716
717 static __INLINE void
MSS_USB_CIF_rx_ep_clr_send_stall_bit(mss_usb_ep_num_t ep_num)718 MSS_USB_CIF_rx_ep_clr_send_stall_bit
719 (
720 mss_usb_ep_num_t ep_num
721 )
722 {
723 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
724
725 reg_val &= ~RxCSRL_REG_EPN_SEND_STALL_MASK;
726 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
727 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
728 }
729
730 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_stall_sent_bit(mss_usb_ep_num_t ep_num)731 MSS_USB_CIF_rx_ep_is_stall_sent_bit
732 (
733 mss_usb_ep_num_t ep_num
734 )
735 {
736 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_STALL_SENT_MASK) ?
737 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
738 }
739
740 static __INLINE void
MSS_USB_CIF_rx_ep_clr_stall_sent_bit(mss_usb_ep_num_t ep_num)741 MSS_USB_CIF_rx_ep_clr_stall_sent_bit
742 (
743 mss_usb_ep_num_t ep_num
744 )
745 {
746 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
747
748 reg_val &= ~RxCSRL_REG_EPN_STALL_SENT_MASK;
749 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
750 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
751 }
752
753 static __INLINE void
MSS_USB_CIF_rx_ep_clr_data_tog(mss_usb_ep_num_t ep_num)754 MSS_USB_CIF_rx_ep_clr_data_tog
755 (
756 mss_usb_ep_num_t ep_num
757 )
758 {
759 /* setting CLR_DAT_TOG bit clears USB Data toggle bit */
760 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_CLR_DAT_TOG_MASK |
761 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
762 }
763
764 /*-------------------------------------------------------------------------*//**
765 RXCSRH register related APIs
766 */
767 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_isoincomp(mss_usb_ep_num_t ep_num)768 MSS_USB_CIF_rx_ep_is_isoincomp
769 (
770 mss_usb_ep_num_t ep_num
771 )
772 {
773 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_RX_ISO_INCOMP) ?
774 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
775 }
776
777 static __INLINE mss_usb_dma_mode_t
MSS_USB_CIF_rx_ep_get_dma_mode(mss_usb_ep_num_t ep_num)778 MSS_USB_CIF_rx_ep_get_dma_mode
779 (
780 mss_usb_ep_num_t ep_num
781 )
782 {
783 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_DMA_MODE_MASK) ?
784 MSS_USB_DMA_MODE1 : MSS_USB_DMA_MODE0));
785 }
786
787 static __INLINE void
MSS_USB_CIF_rx_ep_set_dma_mode1(mss_usb_ep_num_t ep_num)788 MSS_USB_CIF_rx_ep_set_dma_mode1
789 (
790 mss_usb_ep_num_t ep_num
791 )
792 {
793 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_DMA_MODE_MASK |
794 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
795 }
796
797 static __INLINE void
MSS_USB_CIF_rx_ep_set_dma_mode0(mss_usb_ep_num_t ep_num)798 MSS_USB_CIF_rx_ep_set_dma_mode0
799 (
800 mss_usb_ep_num_t ep_num
801 )
802 {
803 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
804
805 reg_val &= ~RxCSRL_REG_EPN_DMA_MODE_MASK;
806 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
807 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
808 }
809
810 static __INLINE void
MSS_USB_CIF_rx_ep_enable_dma(mss_usb_ep_num_t ep_num)811 MSS_USB_CIF_rx_ep_enable_dma
812 (
813 mss_usb_ep_num_t ep_num
814 )
815 {
816 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_ENABLE_DMA_MASK |
817 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
818 }
819
820 static __INLINE void
MSS_USB_CIF_rx_ep_disable_dma(mss_usb_ep_num_t ep_num)821 MSS_USB_CIF_rx_ep_disable_dma
822 (
823 mss_usb_ep_num_t ep_num
824 )
825 {
826 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
827
828 reg_val &= ~RxCSRL_REG_EPN_ENABLE_DMA_MASK;
829 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
830 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
831 }
832
833 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_dma_enabled(mss_usb_ep_num_t ep_num)834 MSS_USB_CIF_rx_ep_is_dma_enabled
835 (
836 mss_usb_ep_num_t ep_num
837 )
838 {
839 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_ENABLE_DMA_MASK) ?
840 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
841 }
842
843 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_piderr(mss_usb_ep_num_t ep_num)844 MSS_USB_CIF_rx_ep_is_piderr
845 (
846 mss_usb_ep_num_t ep_num
847 )
848 {
849 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_ISO_PID_ERR_MASK) ?
850 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
851 }
852
853 static __INLINE void
MSS_USB_CIF_rx_ep_disable_nyet(mss_usb_ep_num_t ep_num)854 MSS_USB_CIF_rx_ep_disable_nyet
855 (
856 mss_usb_ep_num_t ep_num
857 )
858 {
859 /* Setting BI_DIS_NYET mask disables NYET */
860 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_BI_DIS_NYET_MASK |
861 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
862 }
863
864 static __INLINE void
MSS_USB_CIF_rx_ep_enable_nyet(mss_usb_ep_num_t ep_num)865 MSS_USB_CIF_rx_ep_enable_nyet
866 (
867 mss_usb_ep_num_t ep_num
868 )
869 {
870 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
871
872 reg_val &= ~RxCSRL_REG_EPN_BI_DIS_NYET_MASK;
873 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
874 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
875 }
876
877 static __INLINE void
MSS_USB_CIF_rx_ep_disable_iso(mss_usb_ep_num_t ep_num)878 MSS_USB_CIF_rx_ep_disable_iso
879 (
880 mss_usb_ep_num_t ep_num
881 )
882 {
883 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
884
885 reg_val &= ~RxCSRL_REG_EPN_ENABLE_ISO_MASK;
886 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
887 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
888 }
889
890 static __INLINE void
MSS_USB_CIF_rx_ep_enable_iso(mss_usb_ep_num_t ep_num)891 MSS_USB_CIF_rx_ep_enable_iso
892 (
893 mss_usb_ep_num_t ep_num
894 )
895 {
896 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_ENABLE_ISO_MASK |
897 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
898 }
899
900 static __INLINE void
MSS_USB_CIF_rx_ep_set_autoclr(mss_usb_ep_num_t ep_num)901 MSS_USB_CIF_rx_ep_set_autoclr
902 (
903 mss_usb_ep_num_t ep_num
904 )
905 {
906 USB->ENDPOINT[ep_num].RX_CSR |= (RxCSRL_REG_EPN_ENABLE_AUTOCLR_MASK |
907 RxCSRL_REG_EPN_RX_PKT_RDY_MASK);
908 }
909
910 static __INLINE void
MSS_USB_CIF_rx_ep_clr_autoclr(mss_usb_ep_num_t ep_num)911 MSS_USB_CIF_rx_ep_clr_autoclr
912 (
913 mss_usb_ep_num_t ep_num
914 )
915 {
916 uint16_t reg_val = USB->ENDPOINT[ep_num].RX_CSR;
917
918 reg_val &= ~RxCSRL_REG_EPN_ENABLE_AUTOCLR_MASK;
919 reg_val |= RxCSRL_REG_EPN_RX_PKT_RDY_MASK;
920 USB->ENDPOINT[ep_num].RX_CSR = reg_val;
921 }
922
923 static __INLINE uint8_t
MSS_USB_CIF_rx_ep_is_autoclr(mss_usb_ep_num_t ep_num)924 MSS_USB_CIF_rx_ep_is_autoclr
925 (
926 mss_usb_ep_num_t ep_num
927 )
928 {
929 return (((USB->ENDPOINT[ep_num].RX_CSR & RxCSRL_REG_EPN_ENABLE_AUTOCLR_MASK) ?
930 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
931 }
932
933 static __INLINE void
MSS_USB_CIF_rx_ep_clr_csrreg(mss_usb_ep_num_t ep_num)934 MSS_USB_CIF_rx_ep_clr_csrreg
935 (
936 mss_usb_ep_num_t ep_num
937 )
938 {
939 USB->ENDPOINT[ep_num].RX_CSR = 0x0000U;
940 }
941
942 /*-------------------------------------------------------------------------*//**
943 RXCOUNT register related APIs
944 */
945 static __INLINE uint16_t
MSS_USB_CIF_rx_ep_read_count(mss_usb_ep_num_t ep_num)946 MSS_USB_CIF_rx_ep_read_count
947 (
948 mss_usb_ep_num_t ep_num
949 )
950 {
951 /* only valid when rxpktrdy is set */
952 return (USB->ENDPOINT[ep_num].RX_COUNT);
953 }
954
955 /*-------------------------------------------------------------------------*//**
956 FIFOx register related APIs
957 */
958 static __INLINE void
MSS_USB_CIF_load_tx_fifo(mss_usb_ep_num_t ep_num,void * in_data,uint32_t length)959 MSS_USB_CIF_load_tx_fifo
960 (
961 mss_usb_ep_num_t ep_num,
962 void * in_data,
963 uint32_t length
964 )
965 {
966 uint32_t idx;
967 uint32_t* temp;
968 uint8_t* temp_8bit;
969
970 uint16_t words = length / 4;
971 temp = in_data;
972 temp_8bit = in_data;
973
974 for(idx = 0u; idx < words; ++idx)
975 {
976 USB->FIFO[ep_num].WORD.VALUE = (uint32_t)temp[idx];
977 }
978
979 for(idx = (length - (length % 4)); idx < length; ++idx)
980 {
981 USB->FIFO[ep_num].BYTE.VALUE = (uint8_t)temp_8bit[idx];
982 }
983 }
984
985 static __INLINE void
MSS_USB_CIF_read_rx_fifo(mss_usb_ep_num_t ep_num,void * out_data,uint32_t length)986 MSS_USB_CIF_read_rx_fifo
987 (
988 mss_usb_ep_num_t ep_num,
989 void * out_data,
990 uint32_t length
991 )
992 {
993 uint32_t idx;
994 volatile uint32_t* temp;
995 uint8_t* temp_8bit;
996
997 uint16_t words = length / 4;
998 temp = out_data;
999 temp_8bit = out_data;
1000
1001 for(idx = 0u; idx < words; ++idx)
1002 {
1003 temp[idx] = USB->FIFO[ep_num].WORD.VALUE;
1004 }
1005
1006 for(idx = (length - (length % 4u)); idx < length; ++idx)
1007 {
1008 temp_8bit[idx] = USB->FIFO[ep_num].BYTE.VALUE;
1009 }
1010 }
1011
1012 static __INLINE uint8_t
MSS_USB_CIF_read_rx_fifo_byte(mss_usb_ep_num_t ep_num)1013 MSS_USB_CIF_read_rx_fifo_byte
1014 (
1015 mss_usb_ep_num_t ep_num
1016 )
1017 {
1018 return (uint8_t)(USB->FIFO[ep_num].BYTE.VALUE);
1019 }
1020
1021 static __INLINE uint16_t
MSS_USB_CIF_read_rx_fifo_halfword(mss_usb_ep_num_t ep_num)1022 MSS_USB_CIF_read_rx_fifo_halfword
1023 (
1024 mss_usb_ep_num_t ep_num
1025 )
1026 {
1027 return (uint16_t)(USB->FIFO[ep_num].HALFWORD.VALUE);
1028 }
1029
1030 static __INLINE uint32_t
MSS_USB_CIF_read_rx_fifo_word(mss_usb_ep_num_t ep_num)1031 MSS_USB_CIF_read_rx_fifo_word
1032 (
1033 mss_usb_ep_num_t ep_num
1034 )
1035 {
1036 return (uint32_t)(USB->FIFO[ep_num].WORD.VALUE);
1037 }
1038
1039 /*-------------------------------------------------------------------------*//**
1040 DynFIFOSIZE register related APIs
1041 */
1042 static __INLINE void
MSS_USB_CIF_tx_ep_set_fifo_size(mss_usb_ep_num_t ep_num,uint16_t fifo_size,uint8_t dpb)1043 MSS_USB_CIF_tx_ep_set_fifo_size
1044 (
1045 mss_usb_ep_num_t ep_num,
1046 uint16_t fifo_size,
1047 uint8_t dpb
1048 )
1049 {
1050 uint16_t temp;
1051 uint8_t i = 0;
1052
1053 /* Valid FIFO sizes are 8,16,32,64,128,512,1024,2048,4096 */
1054 if ((ep_num > MSS_USB_CEP) && (fifo_size >= MIN_EP_FIFO_SZ))
1055 {
1056 USB->INDEX = ep_num;
1057 temp = (fifo_size / MIN_EP_FIFO_SZ);
1058 while (!(temp & MSS_USB_WORD_BIT_0_MASK))
1059 {
1060 temp >>= 1u;
1061 i++;
1062 }
1063 USB->TX_FIFO_SIZE = ((dpb << TXFIFOSZ_REG_DPB_SHIFT) | i);
1064 }
1065 }
1066
1067 static __INLINE void
MSS_USB_CIF_rx_ep_set_fifo_size(mss_usb_ep_num_t ep_num,uint16_t fifo_size,uint8_t dpb)1068 MSS_USB_CIF_rx_ep_set_fifo_size
1069 (
1070 mss_usb_ep_num_t ep_num,
1071 uint16_t fifo_size,
1072 uint8_t dpb
1073 )
1074 {
1075 /* fifo_size is the size in terms of number of bytes.*/
1076 uint16_t temp;
1077 uint8_t i = 0u;
1078
1079 /* Valid FIFO sizes are 8,16,32,64,128,512,1024,2048,4096 */
1080 if ((ep_num > MSS_USB_CEP) && (fifo_size >= MIN_EP_FIFO_SZ))
1081 {
1082 USB->INDEX = ep_num;
1083 temp= (fifo_size / MIN_EP_FIFO_SZ);
1084 while (!(temp & MSS_USB_WORD_BIT_0_MASK))
1085 {
1086 temp >>= 1u;
1087 i++;
1088 }
1089 USB->RX_FIFO_SIZE = ((dpb << RXFIFOSZ_REG_DPB_SHIFT) | i);
1090 }
1091 }
1092
1093 /*-------------------------------------------------------------------------*//**
1094 DynFIFOAD register related APIs
1095 */
1096 static __INLINE void
MSS_USB_CIF_tx_ep_set_fifo_addr(mss_usb_ep_num_t ep_num,uint16_t addr)1097 MSS_USB_CIF_tx_ep_set_fifo_addr
1098 (
1099 mss_usb_ep_num_t ep_num,
1100 uint16_t addr
1101 )
1102 {
1103 /* Valid address values are from 0 to FFF8 in steps of 8 */
1104 if (ep_num > MSS_USB_CEP)
1105 {
1106 USB->INDEX = ep_num;
1107 USB->TX_FIFO_ADDR = (addr / EP_FIFO_ADDR_STEP);
1108 }
1109 }
1110
1111 static __INLINE void
MSS_USB_CIF_rx_ep_set_fifo_addr(mss_usb_ep_num_t ep_num,uint16_t addr)1112 MSS_USB_CIF_rx_ep_set_fifo_addr
1113 (
1114 mss_usb_ep_num_t ep_num,
1115 uint16_t addr
1116 )
1117 {
1118 /* Valid address values are from 0 to FFF8 in steps of 8 */
1119 if (ep_num > MSS_USB_CEP)
1120 {
1121 USB->INDEX = ep_num;
1122 USB->RX_FIFO_ADDR = (addr / EP_FIFO_ADDR_STEP);
1123 }
1124 }
1125
1126 /*-------------------------------------------------------------------------*//**
1127 RX_DPKTBUFDIS register related APIs
1128 */
1129 static __INLINE void
MSS_USB_CIF_disable_rx_ep_dpb(mss_usb_ep_num_t ep_num)1130 MSS_USB_CIF_disable_rx_ep_dpb
1131 (
1132 mss_usb_ep_num_t ep_num
1133 )
1134 {
1135 USB->RX_DPBUF_DIS |= (uint16_t)(MSS_USB_WORD_BIT_0_MASK << ep_num);
1136 }
1137
1138 static __INLINE void
MSS_USB_CIF_enable_rx_ep_dpb(mss_usb_ep_num_t ep_num)1139 MSS_USB_CIF_enable_rx_ep_dpb
1140 (
1141 mss_usb_ep_num_t ep_num
1142 )
1143 {
1144 USB->RX_DPBUF_DIS &= (uint16_t)(~(MSS_USB_WORD_BIT_0_MASK << ep_num));
1145 }
1146
1147 /*-------------------------------------------------------------------------*//**
1148 TX_DPKTBUFDIS register related APIs
1149 */
1150 static __INLINE void
MSS_USB_disable_tx_ep_dpb(mss_usb_ep_num_t ep_num)1151 MSS_USB_disable_tx_ep_dpb
1152 (
1153 mss_usb_ep_num_t ep_num
1154 )
1155 {
1156 USB->TX_DPBUF_DIS |= (uint16_t)(MSS_USB_WORD_BIT_0_MASK << ep_num);
1157 }
1158
1159 static __INLINE void
MSS_USB_enable_tx_ep_dpb(mss_usb_ep_num_t ep_num)1160 MSS_USB_enable_tx_ep_dpb
1161 (
1162 mss_usb_ep_num_t ep_num
1163 )
1164 {
1165 USB->TX_DPBUF_DIS &= (uint16_t)(~(MSS_USB_WORD_BIT_0_MASK << ep_num));
1166 }
1167
1168 /*-------------------------------------------------------------------------*//**
1169 DMA_INTR register related APIs
1170 */
1171 static __INLINE uint32_t
MSS_USB_CIF_dma_read_irq(void)1172 MSS_USB_CIF_dma_read_irq
1173 (
1174 void
1175 )
1176 {
1177 return (USB->DMA_CHANNEL[0].IRQ);
1178 }
1179
1180 /*-------------------------------------------------------------------------*//**
1181 * DMA_CNTL register related APIs
1182 */
1183 static __INLINE void
MSS_USB_CIF_dma_start_xfr(mss_usb_dma_channel_t dma_channel)1184 MSS_USB_CIF_dma_start_xfr
1185 (
1186 mss_usb_dma_channel_t dma_channel
1187 )
1188 {
1189 USB->DMA_CHANNEL[dma_channel].CNTL |= DMA_CNTL_REG_START_XFR_MASK;
1190 }
1191
1192 static __INLINE void
MSS_USB_CIF_dma_stop_xfr(mss_usb_dma_channel_t dma_channel)1193 MSS_USB_CIF_dma_stop_xfr
1194 (
1195 mss_usb_dma_channel_t dma_channel
1196 )
1197 {
1198 USB->DMA_CHANNEL[dma_channel].CNTL &= ~DMA_CNTL_REG_START_XFR_MASK;
1199 }
1200
1201 static __INLINE void
MSS_USB_CIF_dma_set_dir(mss_usb_dma_channel_t dma_channel,mss_usb_dma_dir_t dir)1202 MSS_USB_CIF_dma_set_dir
1203 (
1204 mss_usb_dma_channel_t dma_channel,
1205 mss_usb_dma_dir_t dir
1206 )
1207 {
1208 /*
1209 dir = 1 => DMA read (TX EP)
1210 dir = 0 => DMA write (RX EP)
1211 */
1212 USB->DMA_CHANNEL[dma_channel].CNTL |= (dir << DMA_CNTL_REG_DMA_DIR_SHIFT);
1213 }
1214
1215 static __INLINE mss_usb_dma_dir_t
MSS_USB_CIF_dma_get_dir(mss_usb_dma_channel_t dma_channel)1216 MSS_USB_CIF_dma_get_dir
1217 (
1218 mss_usb_dma_channel_t dma_channel
1219 )
1220 {
1221 return(((USB->DMA_CHANNEL[dma_channel].CNTL & DMA_CNTL_REG_DMA_DIR_MASK) ?
1222 MSS_USB_DMA_READ : MSS_USB_DMA_WRITE));
1223 }
1224
1225 static __INLINE void
MSS_USB_CIF_dma_set_mode(mss_usb_dma_channel_t dma_channel,mss_usb_dma_mode_t dma_mode)1226 MSS_USB_CIF_dma_set_mode
1227 (
1228 mss_usb_dma_channel_t dma_channel,
1229 mss_usb_dma_mode_t dma_mode
1230 )
1231 {
1232 USB->DMA_CHANNEL[dma_channel].CNTL |= (dma_mode << DMA_CNTL_REG_DMA_MODE_SHIFT);
1233 }
1234
1235 static __INLINE mss_usb_dma_mode_t
MSS_USB_CIF_dma_get_mode(mss_usb_dma_channel_t dma_channel)1236 MSS_USB_CIF_dma_get_mode
1237 (
1238 mss_usb_dma_channel_t dma_channel
1239 )
1240 {
1241 return (((USB->DMA_CHANNEL[dma_channel].CNTL & DMA_CNTL_REG_DMA_MODE_MASK) ?
1242 MSS_USB_DMA_MODE1: MSS_USB_DMA_MODE0));
1243 }
1244
1245 static __INLINE void
MSS_USB_CIF_dma_enable_irq(mss_usb_dma_channel_t dma_channel)1246 MSS_USB_CIF_dma_enable_irq
1247 (
1248 mss_usb_dma_channel_t dma_channel
1249 )
1250 {
1251 USB->DMA_CHANNEL[dma_channel].CNTL |= DMA_CNTL_REG_ENABLE_DMA_IRQ_MASK;
1252 }
1253
1254 static __INLINE void
MSS_USB_CIF_dma_disable_irq(mss_usb_dma_channel_t dma_channel)1255 MSS_USB_CIF_dma_disable_irq
1256 (
1257 mss_usb_dma_channel_t dma_channel
1258 )
1259 {
1260 USB->DMA_CHANNEL[dma_channel].CNTL &= ~DMA_CNTL_REG_ENABLE_DMA_IRQ_MASK;
1261 }
1262
1263 static __INLINE void
MSS_USB_CIF_dma_assign_to_epnum(mss_usb_dma_channel_t dma_channel,mss_usb_ep_num_t ep_num)1264 MSS_USB_CIF_dma_assign_to_epnum
1265 (
1266 mss_usb_dma_channel_t dma_channel,
1267 mss_usb_ep_num_t ep_num
1268 )
1269 {
1270 USB->DMA_CHANNEL[dma_channel].CNTL |=
1271 ((ep_num << DMA_CNTL_REG_DMA_EP_NUM_SHIFT) &
1272 DMA_CNTL_REG_DMA_EP_NUM_MASK);
1273 }
1274
1275 static __INLINE mss_usb_ep_num_t
MSS_USB_CIF_dma_get_epnum(mss_usb_dma_channel_t dma_channel)1276 MSS_USB_CIF_dma_get_epnum
1277 (
1278 mss_usb_dma_channel_t dma_channel
1279 )
1280 {
1281 /*
1282 This API will return numbers from 0 to 15, mss_usb_ep_num_t maps it to TX
1283 EP numbers. Using DMA DIR, CIF driver should correctly map it as TX EP or
1284 RX EP.
1285 */
1286 volatile uint8_t ep_num;
1287
1288 ep_num = (USB->DMA_CHANNEL[dma_channel].CNTL & DMA_CNTL_REG_DMA_EP_NUM_MASK);
1289
1290 return (mss_usb_ep_num_t)(ep_num >> DMA_CNTL_REG_DMA_EP_NUM_SHIFT);
1291 }
1292
1293 static __INLINE uint8_t
MSS_USB_CIF_dma_is_bus_err(mss_usb_dma_channel_t dma_channel)1294 MSS_USB_CIF_dma_is_bus_err
1295 (
1296 mss_usb_dma_channel_t dma_channel
1297 )
1298 {
1299 return (((USB->DMA_CHANNEL[dma_channel].CNTL & DMA_CNTL_REG_DMA_BUS_ERR_MASK) ?
1300 MSS_USB_BOOLEAN_TRUE : MSS_USB_BOOLEAN_FALSE));
1301 }
1302
1303 static __INLINE void
MSS_USB_CIF_dma_clr_bus_err(mss_usb_dma_channel_t dma_channel)1304 MSS_USB_CIF_dma_clr_bus_err
1305 (
1306 mss_usb_dma_channel_t dma_channel
1307 )
1308 {
1309 USB->DMA_CHANNEL[dma_channel].CNTL &= ~DMA_CNTL_REG_DMA_BUS_ERR_MASK;
1310 }
1311
1312 static __INLINE void
MSS_USB_CIF_dma_set_burst_mode(mss_usb_dma_channel_t dma_channel,mss_usb_dma_burst_mode_t burst_mode)1313 MSS_USB_CIF_dma_set_burst_mode
1314 (
1315 mss_usb_dma_channel_t dma_channel,
1316 mss_usb_dma_burst_mode_t
1317 burst_mode
1318 )
1319 {
1320 USB->DMA_CHANNEL[dma_channel].CNTL |=
1321 ((burst_mode << DMA_CNTL_REG_DMA_BURST_MODE_SHIFT) &
1322 DMA_CNTL_REG_DMA_BURST_MODE_MASK);
1323 }
1324
1325 static __INLINE mss_usb_dma_burst_mode_t
MSS_USB_CIF_dma_get_burst_mode(mss_usb_dma_channel_t dma_channel,mss_usb_dma_burst_mode_t burst_mode)1326 MSS_USB_CIF_dma_get_burst_mode
1327 (
1328 mss_usb_dma_channel_t dma_channel,
1329 mss_usb_dma_burst_mode_t burst_mode
1330 )
1331 {
1332 uint8_t mode;
1333 mode = (USB->DMA_CHANNEL[dma_channel].CNTL &
1334 DMA_CNTL_REG_DMA_BURST_MODE_MASK);
1335
1336 return (mss_usb_dma_burst_mode_t)(mode >> DMA_CNTL_REG_DMA_BURST_MODE_SHIFT);
1337 }
1338
1339 static __INLINE void
MSS_USB_CIF_dma_clr_ctrlreg(mss_usb_dma_channel_t dma_channel)1340 MSS_USB_CIF_dma_clr_ctrlreg
1341 (
1342 mss_usb_dma_channel_t dma_channel
1343 )
1344 {
1345 USB->DMA_CHANNEL[dma_channel].CNTL = 0x0000U;
1346 }
1347
1348 /*-------------------------------------------------------------------------*//**
1349 DMA_ADDR register related APIs
1350 */
1351 static __INLINE uint32_t
MSS_USB_CIF_dma_read_addr(mss_usb_dma_channel_t dma_channel)1352 MSS_USB_CIF_dma_read_addr
1353 (
1354 mss_usb_dma_channel_t dma_channel
1355 )
1356 {
1357 return (USB->DMA_CHANNEL[dma_channel].ADDR);
1358 }
1359
1360 static __INLINE void
MSS_USB_CIF_dma_write_addr(mss_usb_dma_channel_t dma_channel,uint32_t addr)1361 MSS_USB_CIF_dma_write_addr
1362 (
1363 mss_usb_dma_channel_t dma_channel,
1364 uint32_t addr
1365 )
1366 {
1367 USB->DMA_CHANNEL[dma_channel].ADDR = addr;
1368 }
1369
1370 /*-------------------------------------------------------------------------*//**
1371 DMA_COUNT register related APIs
1372 */
1373 static __INLINE uint32_t
MSS_USB_CIF_dma_read_count(mss_usb_dma_channel_t dma_channel)1374 MSS_USB_CIF_dma_read_count
1375 (
1376 mss_usb_dma_channel_t dma_channel
1377 )
1378 {
1379 return (USB->DMA_CHANNEL[dma_channel].COUNT);
1380 }
1381
1382 static __INLINE void
MSS_USB_CIF_dma_write_count(mss_usb_dma_channel_t dma_channel,uint32_t count)1383 MSS_USB_CIF_dma_write_count
1384 (
1385 mss_usb_dma_channel_t dma_channel,
1386 uint32_t count
1387 )
1388 {
1389 USB->DMA_CHANNEL[dma_channel].COUNT = count;
1390 }
1391
1392 #ifdef __cplusplus
1393 }
1394 #endif
1395
1396 #endif /* __MSS_USB_COMMON_REG_IO_H_ */
1397
