1 /******************************************************************************* 2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * PolarFire SoC MSS eMMC SD driver data structures. 7 * 8 * This eMMC Interface header file provides a subset of definitions from the eMMC 9 * protocol JESD84-B51 10 * 11 */ 12 13 #ifndef __MSS_MMC_TYPE_H 14 #define __MSS_MMC_TYPE_H 15 16 #ifdef __cplusplus 17 extern "C" 18 #endif 19 20 /***************************************************************************//** 21 * Macro Definitions 22 */ 23 24 /* MMC/SD/SDIO commands */ 25 26 #define MMC_CMD_15_GOTO_INACTIVE_STATE 15u /* No Rsp */ 27 #define MMC_CMD_4_SET_DSR 4u /* No Rsp */ 28 #define MMC_CMD_0_GO_IDLE_STATE 0u /* No Rsp */ 29 #define MMC_CMD_6_SWITCH 6u /* R1b Rsp */ 30 #define MMC_CMD_7_SELECT_DESELECT_CARD 7u /* R1/R1b Rsp */ 31 32 #define MMC_CMD_3_SET_RELATIVE_ADDR 3u /* R1 Rsp */ 33 #define MMC_CMD_17_READ_SINGLE_BLOCK 17u /* R1 Rsp */ 34 #define MMC_CMD_18_READ_MULTIPLE_BLOCK 18u /* R1 Rsp */ 35 #define MMC_CMD_24_WRITE_SINGLE_BLOCK 24u /* R1 Rsp */ 36 #define MMC_CMD_23_SET_BLOCK_COUNT 23u /* R1 Rsp */ 37 #define MMC_CMD_25_WRITE_MULTI_BLOCK 25u /* R1 Rsp */ 38 #define MMC_CMD_13_SEND_STATUS 13u /* R1 Rsp */ 39 #define MMC_CMD_12_STOP_TRANSMISSION 12u /* R1/R1b Rsp */ 40 #define MMC_CMD_8_SEND_EXT_CSD 8u /* R1 Rsp */ 41 #define MMC_CMD_21_SEND_TUNE_BLK 21u /* R1 Rsp */ 42 43 #define MMC_CMD_14_BUSTEST_R 14u /* R1 Rsp */ 44 #define MMC_CMD_19_BUSTEST_W 19u /* R1 Rsp */ 45 46 #define MMC_CMD_2_ALL_SEND_CID 2u /* R2 Rsp */ 47 #define MMC_CMD_9_SEND_CSD 9u /* R2 Rsp */ 48 #define MMC_CMD_10_SEND_CID 10u /* R2 Rsp */ 49 #define MMC_CMD_1_SEND_OP_COND 1u /* R3 Rsp */ 50 #define MMC_CMD_39_FAST_IO 39u /* R4 Rsp */ 51 #define MMC_CMD_40_GO_IRQ_STATE 40u /* R5 Rsp */ 52 53 #define SD_CMD_8_SEND_IF_COND 8u /* R7 Rsp */ 54 #define SD_ACMD_41_SEND_OP_COND 41u /* R3 Rsp */ 55 #define SD_ACMD_42_SET_CLR_CARD_DETECT 42u /* R1 Rsp */ 56 57 #define SD_CMD_11_VOLAGE_SWITCH 11u /* R1 Rsp */ 58 #define SD_CMD_19_SEND_TUNING_BLK 19u /* R1 Rsp */ 59 #define SD_CMD_55 55u 60 61 #define SD_CMD_5 5u /* R4 Rsp */ 62 #define SD_ACMD_6 6u /* R1 Rsp */ 63 #define SD_ACMD_51 51u /* R1 Rsp */ 64 #define SD_CMD_6 6u /* R1 Rsp */ 65 #define SD_CMD_16 16u /* R1 Rsp */ 66 67 #define SDIO_CMD_52_IO_RW_DIRECT 52u /*R5 Rsp */ 68 #define SDIO_CMD_53_IO_RW_EXTENDED 53u /*R5 Rsp */ 69 70 /* eMMC/SD Response Type */ 71 typedef enum 72 { 73 MSS_MMC_RESPONSE_NO_RESP = 0u, 74 MSS_MMC_RESPONSE_R1 = 1u, 75 MSS_MMC_RESPONSE_R1B = 2u, 76 MSS_MMC_RESPONSE_R2 = 3u, 77 MSS_MMC_RESPONSE_R3 = 4u, 78 MSS_MMC_RESPONSE_R4 = 5u, 79 MSS_MMC_RESPONSE_R5 = 6u, 80 MSS_MMC_RESPONSE_R5B = 7u, 81 MSS_MMC_RESPONSE_R6 = 8u, 82 MSS_MMC_RESPONSE_R7 = 9u, 83 MSS_MMC_RESPONSE_R1A = 10u 84 } MSS_MMC_response_type; 85 86 typedef enum 87 { 88 /* access mode - SDR12 default (CLK: max 25MHz, DT: max 12MB/s) */ 89 MSS_MMC_ACCESS_MODE_SDR12 = 0u, 90 /* access mode - SDR15 default (CLK: max 50MHz, DT: max 25MB/s) */ 91 MSS_MMC_ACCESS_MODE_SDR25 = 1u, 92 /* access mode - SDR50 default (CLK: max 100MHz, DT: max 50MB/s) */ 93 MSS_MMC_ACCESS_MODE_SDR50 = 2u, 94 /* access mode - SDR104 default (CLK: max 208MHz, DT: max 104MB/s) */ 95 MSS_MMC_ACCESS_MODE_SDR104 = 3u, 96 /* access mode - DDR50 default (CLK: max 50MHz, DT: max 50MB/s) */ 97 MSS_MMC_ACCESS_MODE_DDR50 = 4u, 98 /* access mode - ultra high speed II mode */ 99 MSS_MMC_ACCESS_MODE_UHSII = 5u, 100 /* MMC access mode - legacy mode (CLK: max 26MHz, DT: max 26MB/s) */ 101 MSS_MMC_ACCESS_MODE_MMC_LEGACY = 6u, 102 /* MMC access mode - high speed SDR mode (CLK: max 26MHz, DT: max 26MB/s) */ 103 MSS_MMC_ACCESS_MODE_HS_SDR = 7u, 104 /* MMC access mode - high speed DDR mode (CLK: max 52MHz, DT: max 104MB/s) */ 105 MSS_MMC_ACCESS_MODE_HS_DDR = 8u, 106 /* MMC access mode - HS200 mode (CLK: max 200MHz, DT: max 200MB/s) */ 107 MSS_MMC_ACCESS_MODE_HS_200 = 9u, 108 /* MMC access mode - HS400 mode (CLK: max 200MHz, DT: max 400MB/s) */ 109 MSS_MMC_ACCESS_MODE_HS_400 = 10u, 110 /* MMC access mode - HS400 using Enhanced Strobe (CLK: max 200MHz, DT: max 400MB/s) */ 111 MSS_MMC_ACCESS_MODE_HS_400_ES = 11u, 112 } MSS_MMC_speed_mode; 113 114 /* PHY configuration delay type */ 115 typedef enum 116 { 117 /* delay in the input path for High Speed work mode */ 118 MSS_MMC_PHY_DELAY_INPUT_HIGH_SPEED = 0u, 119 /* delay in the input path for Default Speed work mode */ 120 MSS_MMC_PHY_DELAY_INPUT_DEFAULT_SPEED = 1u, 121 /* delay in the input path for SDR12 work mode */ 122 MSS_MMC_PHY_DELAY_INPUT_SDR12 = 2u, 123 /* delay in the input path for SDR25 work mode */ 124 MSS_MMC_PHY_DELAY_INPUT_SDR25 = 3u, 125 /* delay in the input path for SDR50 work mode */ 126 MSS_MMC_PHY_DELAY_INPUT_SDR50 = 4u, 127 /* delay in the input path for DDR50 work mode */ 128 MSS_MMC_PHY_DELAY_INPUT_DDR50 = 5u, 129 /* delay in the input path for eMMC legacy work mode */ 130 MSS_MMC_PHY_DELAY_INPUT_MMC_LEGACY = 6u, 131 /* delay in the input path for eMMC SDR work mode */ 132 MSS_MMC_PHY_DELAY_INPUT_MMC_SDR = 7u, 133 /* delay in the input path for eMMC DDR work mode */ 134 MSS_MMC_PHY_DELAY_INPUT_MMC_DDR = 8u, 135 /* Value of the delay introduced on the sdclk output for all modes except 136 * HS200, HS400 and HS400_ES 137 */ 138 MSS_MMC_PHY_DELAY_DLL_SDCLK = 11u, 139 /* Value of the delay introduced on the sdclk output for HS200, HS400 and 140 * HS400_ES speed mode 141 */ 142 MSS_MMC_PHY_DELAY_DLL_HS_SDCLK = 12u, 143 /* Value of the delay introduced on the dat_strobe input used in 144 * HS400 / HS400_ES speed mode. 145 */ 146 MSS_MMC_PHY_DELAY_DLL_DAT_STROBE = 13u, 147 } MSS_MMC_phydelay; 148 149 /********************************************************************** 150 * Enumerations 151 **********************************************************************/ 152 /* CCCR card control registers definitions */ 153 typedef enum 154 { 155 /* CCCR version number and SDIO specification version number register */ 156 MSS_MMC_CCCR_SDIO_REV = 0u, 157 /* SD version number register */ 158 MSS_MMC_CCCR_SD_SPEC_REV = 1u, 159 /* IO enable function register */ 160 MSS_MMC_CCCR_IO_ENABLE = 2u, 161 /* IO ready function register */ 162 MSS_MMC_CCCR_IO_READY = 3u, 163 /* interrupt enable register */ 164 MSS_MMC_CCCR_INT_ENABLE = 4u, 165 /* interrupt pending register */ 166 MSS_MMC_CCCR_INT_PENDING = 5u, 167 /* IO Abort register. It used to stop a function transfer. */ 168 MSS_MMC_CCCR_ABORT = 6u, 169 /* Bus interface control register */ 170 MSS_MMC_CCCR_BUS_CONTROL = 7u, 171 /* Card capability register */ 172 MSS_MMC_CCCR_CARD_CAPABILITY = 8u, 173 /* Pointer to card's common Card Information Structure (CIS) */ 174 MSS_MMC_CCCR_CIS_POINTER = 9u, 175 /* Bus suspend register */ 176 MSS_MMC_CCCR_BUS_SUSPENDED = 12u, 177 /* Function select register */ 178 MSS_MMC_CCCR_FUNCTION_SELECT = 13u, 179 /* Exec flags register. The bits of this register are used by the host to 180 * determine the current execution status of all functions (1-7) and memory (0). 181 */ 182 MSS_MMC_CCCR_EXEC_FLAGS = 14u, 183 /* Ready flags register. The bits of this register tell the host the read 184 * or write busy status for functions (1-7) and memory (0). 185 */ 186 MSS_MMC_CCCR_READY_FLAGS = 15u, 187 /* I/O block size for Function 0 */ 188 MSS_MMC_CCCR_FN0_BLOCK_SIZE = 16u, 189 /* Power control register */ 190 MSS_MMC_CCCR_POWER_CONTROL = 18u, 191 /* Bus speed select */ 192 MSS_MMC_CCCR_HIGH_SPEED = 19u, 193 /* UHS-I support info */ 194 MSS_MMC_CCCR_UHSI_SUPPORT = 20u, 195 /* Driver Strength */ 196 MSS_MMC_CCCR_DRIVER_STRENGTH = 21u, 197 /* Interrupt extension */ 198 MSS_MMC_CCCR_INT_EXT = 22u, 199 } MSS_MMC_cccr_reg_addr; 200 201 /* FBR card control registers definitions */ 202 typedef enum 203 { 204 MSS_MMC_FBR_STD_SDIO_FN = 0u, 205 MSS_MMC_FBR_EXT_SDIO_FN = 1u, 206 MSS_MMC_FBR_POWER_SEL = 2u, 207 MSS_MMC_FBR_ADDR_CIS = 9u, 208 MSS_MMC_FBR_ADDR_CSA = 12u, 209 MSS_MMC_FBR_DATA_CSA = 15u, 210 MSS_MMC_FBR_BLOCK_SIZE = 16u, 211 } MSS_MMC_fbr_reg_addr; 212 213 /* Tuple names definitions of SDIO card */ 214 typedef enum 215 { 216 /* NULL tuple */ 217 MSS_MMC_TUPLE_CISTPL_NULL = 0u, 218 /* Checksum control */ 219 MSS_MMC_TUPLE_CISTPL_CHECKSUM = 16u, 220 /* Level 1 version/product information */ 221 MSS_MMC_TUPLE_CISTPL_VERS_1 = 21u, 222 /* Alternate language string tuple */ 223 MSS_MMC_TUPLE_CISTPL_ALTSTR = 22u, 224 /* Manufacturer identification string tuple */ 225 MSS_MMC_TUPLE_CISTPL_MANFID = 32u, 226 /* Function identification tuple */ 227 MSS_MMC_TUPLE_CISTPL_FUNCID = 33u, 228 /* Additional information for functions built to support application 229 * specifications for standard SDIO functions. 230 */ 231 MSS_MMC_TUPLE_CISTPL_SDIO_STD = 145u, 232 /* Reserved for future use with SDIO devices */ 233 MSS_MMC_TUPLE_CISTPL_SDIO_EXT = 146u, 234 /* The End-of-chain Tuple */ 235 MSS_MMC_TUPLE_CISTPL_END = 255u, 236 } MSS_MMC_tuple_code; 237 238 #ifdef __cplusplus 239 } 240 #endif 241 242 #endif /* __MSS_MMC_TYPE_H */ 243
