1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 /* 13 ************************* ESP32H2 Root Clock Source **************************** 14 * 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC in TRM and reg. description) 15 * 16 * This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK. 17 * 18 * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. 19 * 20 * 2) External 32MHz Crystal Clock: XTAL 21 * 22 * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as SOSC in TRM or reg. description) 23 * 24 * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock 25 * can be computed in runtime through calibration. 26 * 27 * 4) Internal 32kHz RC Oscillator: RC32K [NOT RECOMMENDED TO USE] 28 * 29 * The exact frequency of this clock can be computed in runtime through calibration. 30 * 31 * 5) External 32kHz Crystal Clock (optional): XTAL32K 32 * 33 * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N 34 * pins. 35 * 36 * XTAL32K_CLK can also be calibrated to get its exact frequency. 37 * 38 * 6) External Slow Clock (optional): OSC_SLOW 39 * 40 * A slow clock signal generated by an external circuit can be connected to GPIO13 to be the clock source for the 41 * RTC_SLOW_CLK. 42 * 43 * OSC_SLOW_CLK can also be calibrated to get its exact frequency. 44 */ 45 46 /* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */ 47 #define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ 48 #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ 49 #define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ 50 #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ 51 #define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ 52 53 // Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] 54 // {loc}: EXT, INT 55 // {type}: XTAL, RC 56 // [attr] - optional: [frequency], FAST, SLOW 57 /** 58 * @brief Root clock 59 */ 60 typedef enum { 61 SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8.5MHz RC oscillator */ 62 SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ 63 SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */ 64 SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ 65 SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ 66 SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin13 */ 67 } soc_root_clk_t; 68 69 /** 70 * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK 71 * @note Enum values are matched with the register field values on purpose 72 */ 73 typedef enum { 74 SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ 75 SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */ 76 SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ 77 SOC_CPU_CLK_SRC_FLASH_PLL = 3, /*!< Select FLASH_PLL_CLK as CPU_CLK source (FLASH_PLL_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */ 78 SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ 79 } soc_cpu_clk_src_t; 80 81 /** 82 * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK 83 * @note Enum values are matched with the register field values on purpose 84 */ 85 typedef enum { 86 SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ 87 SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ 88 SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ 89 SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ 90 SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ 91 } soc_rtc_slow_clk_src_t; 92 93 /** 94 * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK 95 * @note Enum values are matched with the register field values on purpose 96 */ 97 typedef enum { 98 SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ 99 SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ 100 SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ 101 SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/ 102 SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ 103 } soc_rtc_fast_clk_src_t; 104 105 /** 106 * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK 107 * @note Enum values are matched with the register field values on purpose 108 */ 109 typedef enum { 110 SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */ 111 SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */ 112 SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */ 113 } soc_lp_pll_clk_src_t; 114 115 // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] 116 // {[upstream]clock_name}: XTAL, (BB)PLL, etc. 117 // [attr] - optional: FAST, SLOW, D<divider>, F<freq> 118 /** 119 * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) 120 * 121 * @note enum starts from 1, to save 0 for special purpose 122 */ 123 typedef enum { 124 // For CPU domain 125 SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or PLL2 by configuring soc_cpu_clk_src_t */ 126 // For RTC domain 127 SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ 128 SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */ 129 // For digital domain: peripherals, WIFI, BLE 130 SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */ 131 SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */ 132 SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */ 133 SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ 134 SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ 135 SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */ 136 SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ 137 } soc_module_clk_t; 138 139 //////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// 140 141 /** 142 * @brief Type of SYSTIMER clock source 143 */ 144 typedef enum { 145 SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ 146 SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ 147 SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ 148 } soc_periph_systimer_clk_src_t; 149 150 //////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// 151 152 /** 153 * @brief Array initializer for all supported clock sources of GPTimer 154 * 155 * The following code can be used to iterate all possible clocks: 156 * @code{c} 157 * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; 158 * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { 159 * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; 160 * // Test GPTimer with the clock `clk` 161 * } 162 * @endcode 163 */ 164 #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} 165 166 /** 167 * @brief Type of GPTimer clock source 168 */ 169 typedef enum { 170 GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ 171 GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 172 GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 173 GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */ 174 } soc_periph_gptimer_clk_src_t; 175 176 /** 177 * @brief Type of Timer Group clock source, reserved for the legacy timer group driver 178 */ 179 typedef enum { 180 TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */ 181 TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ 182 TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */ 183 } soc_periph_tg_clk_src_legacy_t; 184 185 //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// 186 187 /** 188 * @brief Array initializer for all supported clock sources of RMT 189 */ 190 #define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 191 192 /** 193 * @brief Type of RMT clock source 194 */ 195 typedef enum { 196 RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 197 RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 198 RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ 199 } soc_periph_rmt_clk_src_t; 200 201 /** 202 * @brief Type of RMT clock source, reserved for the legacy RMT driver 203 */ 204 typedef enum { 205 RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ 206 RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */ 207 } soc_periph_rmt_clk_src_legacy_t; 208 209 //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// 210 211 /** 212 * @brief Array initializer for all supported clock sources of Temperature Sensor 213 */ 214 #define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 215 216 /** 217 * @brief Type of Temp Sensor clock source 218 */ 219 typedef enum { 220 TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 221 TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 222 TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ 223 } soc_periph_temperature_sensor_clk_src_t; 224 225 ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// 226 227 /** 228 * @brief Type of UART clock source, reserved for the legacy UART driver 229 */ 230 typedef enum { 231 UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */ 232 UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ 233 UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ 234 UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */ 235 } soc_periph_uart_clk_src_legacy_t; 236 237 //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// 238 239 /** 240 * @brief Array initializer for all supported clock sources of MCPWM Timer 241 */ 242 #define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} 243 244 /** 245 * @brief Type of MCPWM timer clock source 246 */ 247 typedef enum { 248 MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 249 MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 250 MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ 251 } soc_periph_mcpwm_timer_clk_src_t; 252 253 /** 254 * @brief Array initializer for all supported clock sources of MCPWM Capture Timer 255 */ 256 #define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} 257 258 /** 259 * @brief Type of MCPWM capture clock source 260 */ 261 typedef enum { 262 MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 263 MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 264 MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ 265 } soc_periph_mcpwm_capture_clk_src_t; 266 267 /** 268 * @brief Array initializer for all supported clock sources of MCPWM Carrier 269 */ 270 #define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL} 271 272 /** 273 * @brief Type of MCPWM carrier clock source 274 */ 275 typedef enum { 276 MCPWM_CARRIER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 277 MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 278 MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ 279 } soc_periph_mcpwm_carrier_clk_src_t; 280 281 ///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// 282 283 /** 284 * @brief Array initializer for all supported clock sources of I2S 285 */ 286 #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_XTAL} 287 288 /** 289 * @brief I2S clock source enum 290 */ 291 typedef enum { 292 I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */ 293 I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 294 I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ 295 I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 296 } soc_periph_i2s_clk_src_t; 297 298 /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// 299 300 /** 301 * @brief Array initializer for all supported clock sources of I2C 302 */ 303 #define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 304 305 /** 306 * @brief Type of I2C clock source. 307 */ 308 typedef enum { 309 I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 310 I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 311 I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ 312 } soc_periph_i2c_clk_src_t; 313 314 /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// 315 316 /** 317 * @brief Array initializer for all supported clock sources of SPI 318 */ 319 #define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M} 320 321 /** 322 * @brief Type of SPI clock source. 323 */ 324 typedef enum { 325 SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ 326 SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ 327 SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ 328 SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ 329 } soc_periph_spi_clk_src_t; 330 331 //////////////////////////////////////////////////SDM/////////////////////////////////////////////////////////////////// 332 333 /** 334 * @brief Array initializer for all supported clock sources of SDM 335 */ 336 #define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL} 337 338 /** 339 * @brief Sigma Delta Modulator clock source 340 */ 341 typedef enum { 342 SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ 343 SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */ 344 SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */ 345 } soc_periph_sdm_clk_src_t; 346 347 ///////////////////////////////////////////////////Analog Comparator//////////////////////////////////////////////////// 348 349 /** 350 * @brief Array initializer for all supported clock sources of Analog Comparator 351 */ 352 #define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL} 353 354 /** 355 * @brief Sigma Delta Modulator clock source 356 */ 357 typedef enum { 358 ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ 359 ANA_CMPR_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */ 360 ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */ 361 } soc_periph_ana_cmpr_clk_src_t; 362 363 //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// 364 365 /** 366 * @brief Array initializer for all supported clock sources of Glitch Filter 367 */ 368 #define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL} 369 370 /** 371 * @brief Glitch filter clock source 372 */ 373 374 typedef enum { 375 GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ 376 GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */ 377 GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */ 378 } soc_periph_glitch_filter_clk_src_t; 379 380 //////////////////////////////////////////////////TWAI///////////////////////////////////////////////////////////////// 381 382 /** 383 * @brief Array initializer for all supported clock sources of TWAI 384 */ 385 #define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} 386 387 /** 388 * @brief TWAI clock source 389 */ 390 typedef enum { 391 TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 392 TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ 393 } soc_periph_twai_clk_src_t; 394 395 //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// 396 397 /** 398 * @brief Array initializer for all supported clock sources of ADC digital controller 399 */ 400 #define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST} 401 402 /** 403 * @brief ADC digital controller clock source 404 */ 405 typedef enum { 406 ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 407 ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 408 ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 409 ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ 410 } soc_periph_adc_digi_clk_src_t; 411 412 //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// 413 414 /** 415 * @brief Array initializer for all supported clock sources of MWDT 416 */ 417 #define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST} 418 419 /** 420 * @brief MWDT clock source 421 */ 422 typedef enum { 423 MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 424 MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48 MHz as the source clock */ 425 MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ 426 MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL as the default clock choice */ 427 } soc_periph_mwdt_clk_src_t; 428 429 //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// 430 431 /** 432 * @brief Array initializer for all supported clock sources of LEDC 433 */ 434 #define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST} 435 436 /** 437 * @brief Type of LEDC clock source, reserved for the legacy LEDC driver 438 */ 439 typedef enum { 440 LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ 441 LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */ 442 LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 443 LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 444 445 LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ 446 } soc_periph_ledc_clk_src_legacy_t; 447 448 //////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// 449 450 /** 451 * @brief Array initializer for all supported clock sources of PARLIO 452 */ 453 #define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M} 454 455 /** 456 * @brief PARLIO clock source 457 */ 458 typedef enum { 459 PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 460 PARLIO_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ 461 PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ 462 } soc_periph_parlio_clk_src_t; 463 464 //////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// 465 /** 466 * @brief Array initializer for all supported clock sources of MSPI digital controller 467 */ 468 #define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} 469 /** 470 * @brief MSPI digital controller clock source 471 */ 472 typedef enum { 473 MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 474 MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 475 MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ 476 MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ 477 MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ 478 MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ 479 } soc_periph_mspi_clk_src_t; 480 481 #ifdef __cplusplus 482 } 483 #endif 484
