1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_EMI_V2_H 7 #define _MEC5_EMI_V2_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief EMI Embedded Microcontroller interface (MEC_EMI0) 15 */ 16 17 typedef struct mec_emi_regs { /*!< (@ 0x400F4000) MEC_EMI0 Structure */ 18 __IOM uint8_t RT_H2EMB; /*!< (@ 0x00000000) EMI Runtime: Host to EC mailbox */ 19 __IOM uint8_t RT_E2HMB; /*!< (@ 0x00000001) EMI Runtime: EC to Host mailbox */ 20 __IOM uint16_t RT_RGO; /*!< (@ 0x00000002) EMI Runtime: region and offset */ 21 __IOM uint32_t RT_DATA; /*!< (@ 0x00000004) EMI Runtime: Data. Access size should be size 22 specified in ACC_TYPE field of RT_RGO register */ 23 __IOM uint16_t RT_ISRC; /*!< (@ 0x00000008) EMI Runtime: interrupt source bitmap */ 24 __IOM uint16_t RT_IMASK; /*!< (@ 0x0000000A) EMI Runtime: interrupt source mask bitmap */ 25 __IOM uint8_t RT_AID; /*!< (@ 0x0000000C) EMI Runtime: application ID */ 26 __IM uint8_t RESERVED; 27 __IM uint16_t RESERVED1; 28 __IOM uint8_t RT_ASAID; /*!< (@ 0x00000010) EMI Runtime: application ID assignment */ 29 __IM uint8_t RESERVED2; 30 __IM uint16_t RESERVED3; 31 __IM uint32_t RESERVED4[59]; 32 __IOM uint8_t H2EMB; /*!< (@ 0x00000100) EMI EC-only: Host to EC mailbox */ 33 __IOM uint8_t E2HMB; /*!< (@ 0x00000101) EMI EC-only: EC to Host mailbox */ 34 __IM uint16_t RESERVED5; 35 __IOM uint32_t MR0B; /*!< (@ 0x00000104) EMI EC-only: EC SRAM memory region 0 base address 36 b[31:2]. Bits[1:0] forced to 0 */ 37 __IOM uint32_t MR0L; /*!< (@ 0x00000108) EMI EC-only: EC SRAM memory region 0 read/write 38 limits */ 39 __IOM uint32_t MR1B; /*!< (@ 0x0000010C) EMI EC-only: EC SRAM memory region 1 base address */ 40 __IOM uint32_t MR1L; /*!< (@ 0x00000110) EMI EC-only: EC SRAM memory region 1 read/write 41 limits */ 42 __IOM uint16_t ISEN; /*!< (@ 0x00000114) EMI EC-only: EC to Host interrupt source set */ 43 __IOM uint16_t IHCEN; /*!< (@ 0x00000116) EMI EC-only: EC to Host interrupt host clear 44 enable */ 45 __IM uint32_t RESERVED6[2]; 46 __IOM uint32_t AIDS[8]; /*!< (@ 0x00000120) EMI EC-only: Application ID status bitmaps */ 47 } MEC_EMI_Type; /*!< Size = 320 (0x140) */ 48 49 /** @} */ /* End of group Device_Peripheral_peripherals */ 50 51 /** @addtogroup PosMask_peripherals 52 * @{ 53 */ 54 /* ======================================================== RT_RGO ========================================================= */ 55 #define MEC_EMI_RT_RGO_ACC_TYPE_Pos (0UL) /*!< ACC_TYPE (Bit 0) */ 56 #define MEC_EMI_RT_RGO_ACC_TYPE_Msk (0x3UL) /*!< ACC_TYPE (Bitfield-Mask: 0x03) */ 57 #define MEC_EMI_RT_RGO_EC_ADDR_Pos (2UL) /*!< EC_ADDR (Bit 2) */ 58 #define MEC_EMI_RT_RGO_EC_ADDR_Msk (0x7ffcUL) /*!< EC_ADDR (Bitfield-Mask: 0x1fff) */ 59 #define MEC_EMI_RT_RGO_SEL_MEM1_Pos (15UL) /*!< SEL_MEM1 (Bit 15) */ 60 #define MEC_EMI_RT_RGO_SEL_MEM1_Msk (0x8000UL) /*!< SEL_MEM1 (Bitfield-Mask: 0x01) */ 61 /* ======================================================== RT_DATA ======================================================== */ 62 /* ======================================================== RT_ISRC ======================================================== */ 63 #define MEC_EMI_RT_ISRC_EC_WR_Pos (0UL) /*!< EC_WR (Bit 0) */ 64 #define MEC_EMI_RT_ISRC_EC_WR_Msk (0x1UL) /*!< EC_WR (Bitfield-Mask: 0x01) */ 65 #define MEC_EMI_RT_ISRC_EC_SWI_Pos (1UL) /*!< EC_SWI (Bit 1) */ 66 #define MEC_EMI_RT_ISRC_EC_SWI_Msk (0xfffeUL) /*!< EC_SWI (Bitfield-Mask: 0x7fff) */ 67 /* ======================================================= RT_IMASK ======================================================== */ 68 #define MEC_EMI_RT_IMASK_EC_SWI_EN_Pos (1UL) /*!< EC_SWI_EN (Bit 1) */ 69 #define MEC_EMI_RT_IMASK_EC_SWI_EN_Msk (0xfffeUL) /*!< EC_SWI_EN (Bitfield-Mask: 0x7fff) */ 70 /* ======================================================== RT_AID ========================================================= */ 71 /* ======================================================= RT_ASAID ======================================================== */ 72 /* ========================================================= H2EMB ========================================================= */ 73 /* ========================================================= E2HMB ========================================================= */ 74 /* ========================================================= MR0B ========================================================== */ 75 /* ========================================================= MR0L ========================================================== */ 76 #define MEC_EMI_MR0L_RD_LIM_Pos (2UL) /*!< RD_LIM (Bit 2) */ 77 #define MEC_EMI_MR0L_RD_LIM_Msk (0x7ffcUL) /*!< RD_LIM (Bitfield-Mask: 0x1fff) */ 78 #define MEC_EMI_MR0L_WR_LIM_Pos (18UL) /*!< WR_LIM (Bit 18) */ 79 #define MEC_EMI_MR0L_WR_LIM_Msk (0x7ffc0000UL) /*!< WR_LIM (Bitfield-Mask: 0x1fff) */ 80 /* ========================================================= MR1B ========================================================== */ 81 /* ========================================================= MR1L ========================================================== */ 82 #define MEC_EMI_MR1L_RD_LIM_Pos (2UL) /*!< RD_LIM (Bit 2) */ 83 #define MEC_EMI_MR1L_RD_LIM_Msk (0x7ffcUL) /*!< RD_LIM (Bitfield-Mask: 0x1fff) */ 84 #define MEC_EMI_MR1L_WR_LIM_Pos (18UL) /*!< WR_LIM (Bit 18) */ 85 #define MEC_EMI_MR1L_WR_LIM_Msk (0x7ffc0000UL) /*!< WR_LIM (Bitfield-Mask: 0x1fff) */ 86 /* ========================================================= ISEN ========================================================== */ 87 #define MEC_EMI_ISEN_EC_SWI_SET_Pos (1UL) /*!< EC_SWI_SET (Bit 1) */ 88 #define MEC_EMI_ISEN_EC_SWI_SET_Msk (0xfffeUL) /*!< EC_SWI_SET (Bitfield-Mask: 0x7fff) */ 89 /* ========================================================= IHCEN ========================================================= */ 90 #define MEC_EMI_IHCEN_HCLR_EN_Pos (1UL) /*!< HCLR_EN (Bit 1) */ 91 #define MEC_EMI_IHCEN_HCLR_EN_Msk (0xfffeUL) /*!< HCLR_EN (Bitfield-Mask: 0x7fff) */ 92 /* ========================================================= AIDS ========================================================== */ 93 94 /** @} */ /* End of group PosMask_peripherals */ 95 96 /** @addtogroup EnumValue_peripherals 97 * @{ 98 */ 99 /* ============================================ MEC_EMI0 RT_RGO ACC_TYPE [0..1] ============================================ */ 100 typedef enum { /*!< MEC_EMI0_RT_RGO_ACC_TYPE */ 101 MEC_EMI0_RT_RGO_ACC_TYPE_8BIT = 0, /*!< 8BIT : EC Data register accesses memory as 8-bit */ 102 MEC_EMI0_RT_RGO_ACC_TYPE_16BIT = 1, /*!< 16BIT : EC Data register accesses memory as 16-bit */ 103 MEC_EMI0_RT_RGO_ACC_TYPE_32BIT = 2, /*!< 32BIT : EC Data register accesses memory as 32-bit */ 104 MEC_EMI0_RT_RGO_ACC_TYPE_32BIT_AUTO_INC = 3, /*!< 32BIT_AUTO_INC : EC Data register accesses memory as 32-bit 105 and increments EC address by 4 */ 106 } MEC_EMI0_RT_RGO_ACC_TYPE_Enum; 107 108 /** @} */ /* End of group EnumValue_peripherals */ 109 110 #endif /* _MEC5_EMI_V2_H */ 111
