1 /* SPDX-License-Identifier: Apache-2.0
2  *
3  * Copyright (c) 2019 Lexmark International, Inc.
4  */
5 #ifndef ARCH_ARM_CORTEX_R_MPU_H
6 #define ARCH_ARM_CORTEX_R_MPU_H 1
7 
8 #define MPU_RBAR_ADDR_Msk               (~0x1f)
9 #define MPU_RASR_ENABLE_Msk             (1)
10 
11 #define MPU_RASR_SIZE_Pos               1U
12 #define MPU_RASR_SIZE_Msk               (0x1FUL << MPU_RASR_SIZE_Pos)
13 
14 #define MPU_TYPE_DREGION_Pos    8U
15 #define MPU_TYPE_DREGION_Msk    (0xFFUL << MPU_TYPE_DREGION_Pos)
16 
17 #define MPU_RASR_XN_Pos                 12
18 #define MPU_RASR_XN_Msk                 (1UL << MPU_RASR_XN_Pos)
19 
20 #define MPU_RASR_AP_Pos                 8
21 #define MPU_RASR_AP_Msk                 (0x7UL << MPU_RASR_AP_Pos)
22 
23 #define MPU_RASR_TEX_Pos                3
24 #define MPU_RASR_TEX_Msk                (0x7UL << MPU_RASR_TEX_Pos)
25 
26 #define MPU_RASR_S_Pos                  2
27 #define MPU_RASR_S_Msk                  (1UL << MPU_RASR_S_Pos)
28 
29 #define MPU_RASR_C_Pos                  1
30 #define MPU_RASR_C_Msk                  (1UL << MPU_RASR_C_Pos)
31 
32 #define MPU_RASR_B_Pos                  0
33 #define MPU_RASR_B_Msk                  (1UL << MPU_RASR_B_Pos)
34 
35 #if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5)
36 #define ARM_MPU_REGION_SIZE_32B         ((uint8_t)0x04U)
37 #define ARM_MPU_REGION_SIZE_64B         ((uint8_t)0x05U)
38 #define ARM_MPU_REGION_SIZE_128B        ((uint8_t)0x06U)
39 #endif
40 
41 #define ARM_MPU_REGION_SIZE_256B        ((uint8_t)0x07U)
42 #define ARM_MPU_REGION_SIZE_512B        ((uint8_t)0x08U)
43 #define ARM_MPU_REGION_SIZE_1KB         ((uint8_t)0x09U)
44 #define ARM_MPU_REGION_SIZE_2KB         ((uint8_t)0x0aU)
45 #define ARM_MPU_REGION_SIZE_4KB         ((uint8_t)0x0bU)
46 #define ARM_MPU_REGION_SIZE_8KB         ((uint8_t)0x0cU)
47 #define ARM_MPU_REGION_SIZE_16KB        ((uint8_t)0x0dU)
48 #define ARM_MPU_REGION_SIZE_32KB        ((uint8_t)0x0eU)
49 #define ARM_MPU_REGION_SIZE_64KB        ((uint8_t)0x0fU)
50 #define ARM_MPU_REGION_SIZE_128KB       ((uint8_t)0x10U)
51 #define ARM_MPU_REGION_SIZE_256KB       ((uint8_t)0x11U)
52 #define ARM_MPU_REGION_SIZE_512KB       ((uint8_t)0x12U)
53 #define ARM_MPU_REGION_SIZE_1MB         ((uint8_t)0x13U)
54 #define ARM_MPU_REGION_SIZE_2MB         ((uint8_t)0x14U)
55 #define ARM_MPU_REGION_SIZE_4MB         ((uint8_t)0x15U)
56 #define ARM_MPU_REGION_SIZE_8MB         ((uint8_t)0x16U)
57 #define ARM_MPU_REGION_SIZE_16MB        ((uint8_t)0x17U)
58 #define ARM_MPU_REGION_SIZE_32MB        ((uint8_t)0x18U)
59 #define ARM_MPU_REGION_SIZE_64MB        ((uint8_t)0x19U)
60 #define ARM_MPU_REGION_SIZE_128MB       ((uint8_t)0x1aU)
61 #define ARM_MPU_REGION_SIZE_256MB       ((uint8_t)0x1bU)
62 #define ARM_MPU_REGION_SIZE_512MB       ((uint8_t)0x1cU)
63 #define ARM_MPU_REGION_SIZE_1GB         ((uint8_t)0x1dU)
64 #define ARM_MPU_REGION_SIZE_2GB         ((uint8_t)0x1eU)
65 #define ARM_MPU_REGION_SIZE_4GB         ((uint8_t)0x1fU)
66 
67 #endif
68