1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM0PLUS_H_GENERIC
32 #define __CORE_CM0PLUS_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex-M0+
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM0+ definitions */
66
67 #define __CORTEX_M (0U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 This core does not support an FPU at all
71 */
72 #define __FPU_USED 0U
73
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
77 #endif
78
79 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
80 #if defined (__ARM_FP)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #endif
83
84 #elif defined (__ti__)
85 #if defined (__ARM_FP)
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
87 #endif
88
89 #elif defined ( __GNUC__ )
90 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
91 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #endif
93
94 #elif defined ( __ICCARM__ )
95 #if defined (__ARMVFP__)
96 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97 #endif
98
99 #elif defined ( __TI_ARM__ )
100 #if defined (__TI_VFP_SUPPORT__)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #endif
103
104 #elif defined ( __TASKING__ )
105 #if defined (__FPU_VFP__)
106 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #endif
108
109 #elif defined ( __CSMC__ )
110 #if ( __CSMC__ & 0x400U)
111 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114 #endif
115
116 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
117
118
119 #ifdef __cplusplus
120 }
121 #endif
122
123 #endif /* __CORE_CM0PLUS_H_GENERIC */
124
125 #ifndef __CMSIS_GENERIC
126
127 #ifndef __CORE_CM0PLUS_H_DEPENDANT
128 #define __CORE_CM0PLUS_H_DEPENDANT
129
130 #ifdef __cplusplus
131 extern "C" {
132 #endif
133
134 /* check device defines and use defaults */
135 #if defined __CHECK_DEVICE_DEFINES
136 #ifndef __CM0PLUS_REV
137 #define __CM0PLUS_REV 0x0000U
138 #warning "__CM0PLUS_REV not defined in device header file; using default!"
139 #endif
140
141 #ifndef __MPU_PRESENT
142 #define __MPU_PRESENT 0U
143 #warning "__MPU_PRESENT not defined in device header file; using default!"
144 #endif
145
146 #ifndef __VTOR_PRESENT
147 #define __VTOR_PRESENT 0U
148 #warning "__VTOR_PRESENT not defined in device header file; using default!"
149 #endif
150
151 #ifndef __NVIC_PRIO_BITS
152 #define __NVIC_PRIO_BITS 2U
153 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
154 #endif
155
156 #ifndef __Vendor_SysTickConfig
157 #define __Vendor_SysTickConfig 0U
158 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
159 #endif
160 #endif
161
162 /* IO definitions (access restrictions to peripheral registers) */
163 /**
164 \defgroup CMSIS_glob_defs CMSIS Global Defines
165
166 <strong>IO Type Qualifiers</strong> are used
167 \li to specify the access to peripheral variables.
168 \li for automatic generation of peripheral register debug information.
169 */
170 #ifdef __cplusplus
171 #define __I volatile /*!< Defines 'read only' permissions */
172 #else
173 #define __I volatile const /*!< Defines 'read only' permissions */
174 #endif
175 #define __O volatile /*!< Defines 'write only' permissions */
176 #define __IO volatile /*!< Defines 'read / write' permissions */
177
178 /* following defines should be used for structure members */
179 #define __IM volatile const /*! Defines 'read only' structure member permissions */
180 #define __OM volatile /*! Defines 'write only' structure member permissions */
181 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
182
183 /*@} end of group Cortex-M0+ */
184
185
186
187 /*******************************************************************************
188 * Register Abstraction
189 Core Register contain:
190 - Core Register
191 - Core NVIC Register
192 - Core SCB Register
193 - Core SysTick Register
194 - Core MPU Register
195 ******************************************************************************/
196 /**
197 \defgroup CMSIS_core_register Defines and Type Definitions
198 \brief Type definitions and defines for Cortex-M processor based devices.
199 */
200
201 /**
202 \ingroup CMSIS_core_register
203 \defgroup CMSIS_CORE Status and Control Registers
204 \brief Core Register type definitions.
205 @{
206 */
207
208 /**
209 \brief Union type to access the Application Program Status Register (APSR).
210 */
211 typedef union
212 {
213 struct
214 {
215 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
216 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
217 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
218 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
219 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
220 } b; /*!< Structure used for bit access */
221 uint32_t w; /*!< Type used for word access */
222 } APSR_Type;
223
224 /** \brief APSR Register Definitions */
225 #define APSR_N_Pos 31U /*!< APSR: N Position */
226 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
227
228 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
229 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
230
231 #define APSR_C_Pos 29U /*!< APSR: C Position */
232 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
233
234 #define APSR_V_Pos 28U /*!< APSR: V Position */
235 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
236
237
238 /**
239 \brief Union type to access the Interrupt Program Status Register (IPSR).
240 */
241 typedef union
242 {
243 struct
244 {
245 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
246 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
247 } b; /*!< Structure used for bit access */
248 uint32_t w; /*!< Type used for word access */
249 } IPSR_Type;
250
251 /** \brief IPSR Register Definitions */
252 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
253 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
254
255
256 /**
257 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
258 */
259 typedef union
260 {
261 struct
262 {
263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
264 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
265 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
266 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273 } xPSR_Type;
274
275 /** \brief xPSR Register Definitions */
276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
278
279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
281
282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
284
285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
287
288 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
289 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
290
291 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
292 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
293
294
295 /**
296 \brief Union type to access the Control Registers (CONTROL).
297 */
298 typedef union
299 {
300 struct
301 {
302 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
303 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
304 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
305 } b; /*!< Structure used for bit access */
306 uint32_t w; /*!< Type used for word access */
307 } CONTROL_Type;
308
309 /** \brief CONTROL Register Definitions */
310 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
311 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
312
313 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
314 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
315
316 /*@} end of group CMSIS_CORE */
317
318
319 /**
320 \ingroup CMSIS_core_register
321 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
322 \brief Type definitions for the NVIC Registers
323 @{
324 */
325
326 /**
327 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
328 */
329 typedef struct
330 {
331 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
332 uint32_t RESERVED0[31U];
333 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
334 uint32_t RESERVED1[31U];
335 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
336 uint32_t RESERVED2[31U];
337 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
338 uint32_t RESERVED3[31U];
339 uint32_t RESERVED4[64U];
340 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
341 } NVIC_Type;
342
343 /*@} end of group CMSIS_NVIC */
344
345
346 /**
347 \ingroup CMSIS_core_register
348 \defgroup CMSIS_SCB System Control Block (SCB)
349 \brief Type definitions for the System Control Block Registers
350 @{
351 */
352
353 /**
354 \brief Structure type to access the System Control Block (SCB).
355 */
356 typedef struct
357 {
358 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
359 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
360 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
361 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
362 #else
363 uint32_t RESERVED0;
364 #endif
365 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
366 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
367 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
368 uint32_t RESERVED1;
369 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
370 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
371 } SCB_Type;
372
373 /** \brief SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
376
377 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
379
380 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
382
383 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
385
386 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
387 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
388
389 /** \brief SCB Interrupt Control State Register Definitions */
390 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
392
393 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
395
396 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
398
399 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
401
402 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
404
405 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
407
408 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
410
411 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
413
414 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
415 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
416
417 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
418 /** \brief SCB Vector Table Offset Register Definitions */
419 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
420 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
421 #endif
422
423 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
424 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
425 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
426
427 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
428 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
429
430 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
431 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
432
433 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
434 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
435
436 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
437 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
438
439 /** \brief SCB System Control Register Definitions */
440 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
441 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
442
443 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
444 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
445
446 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
447 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
448
449 /** \brief SCB Configuration Control Register Definitions */
450 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
451 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
452
453 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
454 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
455
456 /** \brief SCB System Handler Control and State Register Definitions */
457 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
458 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
459
460 /*@} end of group CMSIS_SCB */
461
462
463 /**
464 \ingroup CMSIS_core_register
465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
466 \brief Type definitions for the System Timer Registers.
467 @{
468 */
469
470 /**
471 \brief Structure type to access the System Timer (SysTick).
472 */
473 typedef struct
474 {
475 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
476 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
477 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
478 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
479 } SysTick_Type;
480
481 /** \brief SysTick Control / Status Register Definitions */
482 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
483 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
484
485 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
486 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
487
488 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
489 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
490
491 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
492 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
493
494 /** \brief SysTick Reload Register Definitions */
495 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
496 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
497
498 /** \brief SysTick Current Register Definitions */
499 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
500 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
501
502 /** \brief SysTick Calibration Register Definitions */
503 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
504 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
505
506 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
507 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
508
509 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
510 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
511
512 /*@} end of group CMSIS_SysTick */
513
514 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
515 /**
516 \ingroup CMSIS_core_register
517 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
518 \brief Type definitions for the Memory Protection Unit (MPU)
519 @{
520 */
521
522 /**
523 \brief Structure type to access the Memory Protection Unit (MPU).
524 */
525 typedef struct
526 {
527 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
528 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
529 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
530 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
531 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
532 } MPU_Type;
533
534 #define MPU_TYPE_RALIASES 1U
535
536 /** \brief MPU Type Register Definitions */
537 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
538 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
539
540 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
541 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
542
543 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
544 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
545
546 /** \brief MPU Control Register Definitions */
547 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
548 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
549
550 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
551 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
552
553 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
554 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
555
556 /** \brief MPU Region Number Register Definitions */
557 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
558 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
559
560 /** \brief MPU Region Base Address Register Definitions */
561 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
562 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
563
564 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
565 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
566
567 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
568 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
569
570 /** \brief MPU Region Attribute and Size Register Definitions */
571 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
572 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
573
574 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
575 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
576
577 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
578 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
579
580 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
581 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
582
583 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
584 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
585
586 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
587 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
588
589 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
590 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
591
592 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
593 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
594
595 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
596 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
597
598 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
599 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
600
601 /*@} end of group CMSIS_MPU */
602 #endif
603
604
605 /**
606 \ingroup CMSIS_core_register
607 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
608 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
609 Therefore they are not covered by the Cortex-M0+ header file.
610 @{
611 */
612 /*@} end of group CMSIS_CoreDebug */
613
614
615 /**
616 \ingroup CMSIS_core_register
617 \defgroup CMSIS_core_bitfield Core register bit field macros
618 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
619 @{
620 */
621
622 /**
623 \brief Mask and shift a bit field value for use in a register bit range.
624 \param[in] field Name of the register bit field.
625 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
626 \return Masked and shifted value.
627 */
628 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
629
630 /**
631 \brief Mask and shift a register value to extract a bit filed value.
632 \param[in] field Name of the register bit field.
633 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
634 \return Masked and shifted bit field value.
635 */
636 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
637
638 /*@} end of group CMSIS_core_bitfield */
639
640
641 /**
642 \ingroup CMSIS_core_register
643 \defgroup CMSIS_core_base Core Definitions
644 \brief Definitions for base addresses, unions, and structures.
645 @{
646 */
647
648 /* Memory mapping of Core Hardware */
649 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
650 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
651 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
652 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
653
654 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
655 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
656 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
657
658 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
661 #endif
662
663 /*@} */
664
665
666 /**
667 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
668 \brief Alias definitions present for backwards compatibility for deprecated symbols.
669 @{
670 */
671
672 #ifndef CMSIS_DISABLE_DEPRECATED
673
674 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
675 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
676
677 #endif // CMSIS_DISABLE_DEPRECATED
678
679 /*@} */
680
681
682 /*******************************************************************************
683 * Hardware Abstraction Layer
684 Core Function Interface contains:
685 - Core NVIC Functions
686 - Core SysTick Functions
687 - Core Register Access Functions
688 ******************************************************************************/
689 /**
690 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
691 */
692
693
694
695 /* ########################## NVIC functions #################################### */
696 /**
697 \ingroup CMSIS_Core_FunctionInterface
698 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
699 \brief Functions that manage interrupts and exceptions via the NVIC.
700 @{
701 */
702
703 #ifdef CMSIS_NVIC_VIRTUAL
704 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
705 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
706 #endif
707 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
708 #else
709 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
710 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
711 #define NVIC_EnableIRQ __NVIC_EnableIRQ
712 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
713 #define NVIC_DisableIRQ __NVIC_DisableIRQ
714 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
715 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
716 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
717 /* NVIC_GetActive not available for Cortex-M0+ */
718 #define NVIC_SetPriority __NVIC_SetPriority
719 #define NVIC_GetPriority __NVIC_GetPriority
720 #define NVIC_SystemReset __NVIC_SystemReset
721 #endif /* CMSIS_NVIC_VIRTUAL */
722
723 #ifdef CMSIS_VECTAB_VIRTUAL
724 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
725 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
726 #endif
727 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
728 #else
729 #define NVIC_SetVector __NVIC_SetVector
730 #define NVIC_GetVector __NVIC_GetVector
731 #endif /* (CMSIS_VECTAB_VIRTUAL) */
732
733 #define NVIC_USER_IRQ_OFFSET 16
734
735
736 /* The following EXC_RETURN values are saved the LR on exception entry */
737 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
738 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
739 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
740
741
742 /* Interrupt Priorities are WORD accessible only under Armv6-M */
743 /* The following MACROS handle generation of the register offset and byte masks */
744 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
745 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
746 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
747
748 #define __NVIC_SetPriorityGrouping(X) (void)(X)
749 #define __NVIC_GetPriorityGrouping() (0U)
750
751 /**
752 \brief Enable Interrupt
753 \details Enables a device specific interrupt in the NVIC interrupt controller.
754 \param [in] IRQn Device specific interrupt number.
755 \note IRQn must not be negative.
756 */
__NVIC_EnableIRQ(IRQn_Type IRQn)757 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
758 {
759 if ((int32_t)(IRQn) >= 0)
760 {
761 __COMPILER_BARRIER();
762 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
763 __COMPILER_BARRIER();
764 }
765 }
766
767
768 /**
769 \brief Get Interrupt Enable status
770 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
771 \param [in] IRQn Device specific interrupt number.
772 \return 0 Interrupt is not enabled.
773 \return 1 Interrupt is enabled.
774 \note IRQn must not be negative.
775 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)776 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
777 {
778 if ((int32_t)(IRQn) >= 0)
779 {
780 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
781 }
782 else
783 {
784 return(0U);
785 }
786 }
787
788
789 /**
790 \brief Disable Interrupt
791 \details Disables a device specific interrupt in the NVIC interrupt controller.
792 \param [in] IRQn Device specific interrupt number.
793 \note IRQn must not be negative.
794 */
__NVIC_DisableIRQ(IRQn_Type IRQn)795 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
796 {
797 if ((int32_t)(IRQn) >= 0)
798 {
799 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800 __DSB();
801 __ISB();
802 }
803 }
804
805
806 /**
807 \brief Get Pending Interrupt
808 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
809 \param [in] IRQn Device specific interrupt number.
810 \return 0 Interrupt status is not pending.
811 \return 1 Interrupt status is pending.
812 \note IRQn must not be negative.
813 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)814 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
815 {
816 if ((int32_t)(IRQn) >= 0)
817 {
818 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
819 }
820 else
821 {
822 return(0U);
823 }
824 }
825
826
827 /**
828 \brief Set Pending Interrupt
829 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
830 \param [in] IRQn Device specific interrupt number.
831 \note IRQn must not be negative.
832 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)833 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
834 {
835 if ((int32_t)(IRQn) >= 0)
836 {
837 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
838 }
839 }
840
841
842 /**
843 \brief Clear Pending Interrupt
844 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
845 \param [in] IRQn Device specific interrupt number.
846 \note IRQn must not be negative.
847 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)848 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
849 {
850 if ((int32_t)(IRQn) >= 0)
851 {
852 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
853 }
854 }
855
856
857 /**
858 \brief Set Interrupt Priority
859 \details Sets the priority of a device specific interrupt or a processor exception.
860 The interrupt number can be positive to specify a device specific interrupt,
861 or negative to specify a processor exception.
862 \param [in] IRQn Interrupt number.
863 \param [in] priority Priority to set.
864 \note The priority cannot be set for every processor exception.
865 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)866 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
867 {
868 if ((int32_t)(IRQn) >= 0)
869 {
870 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
871 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
872 }
873 else
874 {
875 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
876 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
877 }
878 }
879
880
881 /**
882 \brief Get Interrupt Priority
883 \details Reads the priority of a device specific interrupt or a processor exception.
884 The interrupt number can be positive to specify a device specific interrupt,
885 or negative to specify a processor exception.
886 \param [in] IRQn Interrupt number.
887 \return Interrupt Priority.
888 Value is aligned automatically to the implemented priority bits of the microcontroller.
889 */
__NVIC_GetPriority(IRQn_Type IRQn)890 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
891 {
892
893 if ((int32_t)(IRQn) >= 0)
894 {
895 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
896 }
897 else
898 {
899 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
900 }
901 }
902
903
904 /**
905 \brief Encode Priority
906 \details Encodes the priority for an interrupt with the given priority group,
907 preemptive priority value, and subpriority value.
908 In case of a conflict between priority grouping and available
909 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
910 \param [in] PriorityGroup Used priority group.
911 \param [in] PreemptPriority Preemptive priority value (starting from 0).
912 \param [in] SubPriority Subpriority value (starting from 0).
913 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
914 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)915 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
916 {
917 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
918 uint32_t PreemptPriorityBits;
919 uint32_t SubPriorityBits;
920
921 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
922 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
923
924 return (
925 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
926 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
927 );
928 }
929
930
931 /**
932 \brief Decode Priority
933 \details Decodes an interrupt priority value with a given priority group to
934 preemptive priority value and subpriority value.
935 In case of a conflict between priority grouping and available
936 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
937 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
938 \param [in] PriorityGroup Used priority group.
939 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
940 \param [out] pSubPriority Subpriority value (starting from 0).
941 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)942 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
943 {
944 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
945 uint32_t PreemptPriorityBits;
946 uint32_t SubPriorityBits;
947
948 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
949 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
950
951 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
952 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
953 }
954
955
956 /**
957 \brief Set Interrupt Vector
958 \details Sets an interrupt vector in SRAM based interrupt vector table.
959 The interrupt number can be positive to specify a device specific interrupt,
960 or negative to specify a processor exception.
961 VTOR must been relocated to SRAM before.
962 If VTOR is not present address 0 must be mapped to SRAM.
963 \param [in] IRQn Interrupt number
964 \param [in] vector Address of interrupt handler function
965 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)966 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
967 {
968 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
969 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
970 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
971 #else
972 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
973 *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
974 #endif
975 /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
976 }
977
978
979 /**
980 \brief Get Interrupt Vector
981 \details Reads an interrupt vector from interrupt vector table.
982 The interrupt number can be positive to specify a device specific interrupt,
983 or negative to specify a processor exception.
984 \param [in] IRQn Interrupt number.
985 \return Address of interrupt handler function
986 */
__NVIC_GetVector(IRQn_Type IRQn)987 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
988 {
989 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
990 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
991 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
992 #else
993 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
994 return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
995 #endif
996 }
997
998
999 /**
1000 \brief System Reset
1001 \details Initiates a system reset request to reset the MCU.
1002 */
__NVIC_SystemReset(void)1003 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1004 {
1005 __DSB(); /* Ensure all outstanding memory accesses included
1006 buffered write are completed before reset */
1007 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1008 SCB_AIRCR_SYSRESETREQ_Msk);
1009 __DSB(); /* Ensure completion of memory access */
1010
1011 for(;;) /* wait until reset */
1012 {
1013 __NOP();
1014 }
1015 }
1016
1017 /*@} end of CMSIS_Core_NVICFunctions */
1018
1019 /* ########################## MPU functions #################################### */
1020
1021 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1022
1023 #include "m-profile/armv7m_mpu.h"
1024
1025 #endif
1026
1027 /* ########################## FPU functions #################################### */
1028 /**
1029 \ingroup CMSIS_Core_FunctionInterface
1030 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1031 \brief Function that provides FPU type.
1032 @{
1033 */
1034
1035 /**
1036 \brief get FPU type
1037 \details returns the FPU type
1038 \returns
1039 - \b 0: No FPU
1040 - \b 1: Single precision FPU
1041 - \b 2: Double + Single precision FPU
1042 */
SCB_GetFPUType(void)1043 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1044 {
1045 return 0U; /* No FPU */
1046 }
1047
1048
1049 /*@} end of CMSIS_Core_FpuFunctions */
1050
1051
1052
1053 /* ################################## SysTick function ############################################ */
1054 /**
1055 \ingroup CMSIS_Core_FunctionInterface
1056 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1057 \brief Functions that configure the System.
1058 @{
1059 */
1060
1061 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1062
1063 /**
1064 \brief System Tick Configuration
1065 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1066 Counter is in free running mode to generate periodic interrupts.
1067 \param [in] ticks Number of ticks between two interrupts.
1068 \return 0 Function succeeded.
1069 \return 1 Function failed.
1070 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1071 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1072 must contain a vendor-specific implementation of this function.
1073 */
SysTick_Config(uint32_t ticks)1074 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1075 {
1076 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1077 {
1078 return (1UL); /* Reload value impossible */
1079 }
1080
1081 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1082 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1083 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1084 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1085 SysTick_CTRL_TICKINT_Msk |
1086 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1087 return (0UL); /* Function successful */
1088 }
1089
1090 #endif
1091
1092 /*@} end of CMSIS_Core_SysTickFunctions */
1093
1094
1095
1096
1097 #ifdef __cplusplus
1098 }
1099 #endif
1100
1101 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
1102
1103 #endif /* __CMSIS_GENERIC */
1104
