1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32U5xx_HAL_CORTEX_H 21 #define __STM32U5xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @{ 45 */ 46 typedef struct 47 { 48 uint8_t Enable; /*!< Specifies the status of the region. 49 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 50 uint8_t Number; /*!< Specifies the index of the region to protect. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 52 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 53 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 54 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 55 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 56 uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter 57 can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 58 uint8_t DisableExec; /*!< Specifies the instruction access status. 59 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 60 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 61 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 62 } MPU_Region_InitTypeDef; 63 /** 64 * @} 65 */ 66 67 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes 68 * Initialization Structure Definition 69 * @{ 70 */ 71 typedef struct 72 { 73 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 74 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 75 76 uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter 77 can be a combination of @ref CORTEX_MPU_Attributes */ 78 79 } MPU_Attributes_InitTypeDef; 80 /** 81 * @} 82 */ 83 84 85 /** 86 * @} 87 */ 88 89 /* Exported constants --------------------------------------------------------*/ 90 91 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 92 * @{ 93 */ 94 95 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 96 * @{ 97 */ 98 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, 99 4 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, 101 3 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, 103 2 bits for subpriority */ 104 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, 105 1 bit for subpriority */ 106 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, 107 0 bit for subpriority */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 113 * @{ 114 */ 115 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ 116 #define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ 117 #define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ 118 #define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ 119 /** 120 * @} 121 */ 122 123 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 124 * @{ 125 */ 126 #define MPU_HFNMI_PRIVDEF_NONE 0U 127 #define MPU_HARDFAULT_NMI 2U 128 #define MPU_PRIVILEGED_DEFAULT 4U 129 #define MPU_HFNMI_PRIVDEF 6U 130 /** 131 * @} 132 */ 133 134 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 135 * @{ 136 */ 137 #define MPU_REGION_ENABLE 1U 138 #define MPU_REGION_DISABLE 0U 139 /** 140 * @} 141 */ 142 143 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 144 * @{ 145 */ 146 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 147 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 148 /** 149 * @} 150 */ 151 152 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 153 * @{ 154 */ 155 #define MPU_ACCESS_NOT_SHAREABLE 0U 156 #define MPU_ACCESS_OUTER_SHAREABLE 1U 157 #define MPU_ACCESS_INNER_SHAREABLE 3U 158 /** 159 * @} 160 */ 161 162 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 163 * @{ 164 */ 165 #define MPU_REGION_PRIV_RW 0U 166 #define MPU_REGION_ALL_RW 1U 167 #define MPU_REGION_PRIV_RO 2U 168 #define MPU_REGION_ALL_RO 3U 169 /** 170 * @} 171 */ 172 173 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 174 * @{ 175 */ 176 #define MPU_REGION_NUMBER0 0U 177 #define MPU_REGION_NUMBER1 1U 178 #define MPU_REGION_NUMBER2 2U 179 #define MPU_REGION_NUMBER3 3U 180 #define MPU_REGION_NUMBER4 4U 181 #define MPU_REGION_NUMBER5 5U 182 #define MPU_REGION_NUMBER6 6U 183 #define MPU_REGION_NUMBER7 7U 184 /** 185 * @} 186 */ 187 188 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 189 * @{ 190 */ 191 #define MPU_ATTRIBUTES_NUMBER0 0U 192 #define MPU_ATTRIBUTES_NUMBER1 1U 193 #define MPU_ATTRIBUTES_NUMBER2 2U 194 #define MPU_ATTRIBUTES_NUMBER3 3U 195 #define MPU_ATTRIBUTES_NUMBER4 4U 196 #define MPU_ATTRIBUTES_NUMBER5 5U 197 #define MPU_ATTRIBUTES_NUMBER6 6U 198 #define MPU_ATTRIBUTES_NUMBER7 7U 199 /** 200 * @} 201 */ 202 203 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 204 * @{ 205 */ 206 #define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ 207 #define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ 208 #define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ 209 #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ 210 211 #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ 212 #define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ 213 #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ 214 215 #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ 216 #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ 217 218 #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ 219 #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ 220 #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ 221 #define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ 222 223 /** 224 * @} 225 */ 226 227 /** 228 * @} 229 */ 230 231 /* Exported macros -----------------------------------------------------------*/ 232 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 233 * @{ 234 */ 235 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 236 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 237 238 /** 239 * @} 240 */ 241 242 /* Exported functions --------------------------------------------------------*/ 243 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 244 * @{ 245 */ 246 247 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 248 * @brief Initialization and Configuration functions 249 * @{ 250 */ 251 /* Initialization and Configuration functions *****************************/ 252 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 253 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 254 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 255 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 256 void HAL_NVIC_SystemReset(void); 257 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 258 /** 259 * @} 260 */ 261 262 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 263 * @brief Cortex control functions 264 * @{ 265 */ 266 /* Peripheral Control functions ***********************************************/ 267 uint32_t HAL_NVIC_GetPriorityGrouping(void); 268 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 269 uint32_t *const pSubPriority); 270 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 271 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 273 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 274 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 275 void HAL_SYSTICK_IRQHandler(void); 276 void HAL_SYSTICK_Callback(void); 277 278 void HAL_MPU_Enable(uint32_t MPU_Control); 279 void HAL_MPU_Disable(void); 280 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 281 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 282 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 283 /* MPU_NS Control functions ***********************************************/ 284 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 285 void HAL_MPU_Disable_NS(void); 286 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 287 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 288 #endif /* __ARM_FEATURE_CMSE */ 289 /** 290 * @} 291 */ 292 293 /** 294 * @} 295 */ 296 297 /* Private types -------------------------------------------------------------*/ 298 /* Private variables ---------------------------------------------------------*/ 299 /* Private constants ---------------------------------------------------------*/ 300 /* Private macros ------------------------------------------------------------*/ 301 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 302 * @{ 303 */ 304 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 305 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 306 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 307 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 308 ((GROUP) == NVIC_PRIORITYGROUP_4)) 309 310 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 311 312 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 313 314 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 315 316 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 317 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 318 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 319 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 320 321 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 322 #define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) 323 #endif /* __ARM_FEATURE_CMSE */ 324 325 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 326 ((STATE) == MPU_REGION_DISABLE)) 327 328 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 329 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 330 331 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 332 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 333 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 334 335 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 336 ((TYPE) == MPU_REGION_ALL_RW) || \ 337 ((TYPE) == MPU_REGION_PRIV_RO) || \ 338 ((TYPE) == MPU_REGION_ALL_RO)) 339 340 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 341 ((NUMBER) == MPU_REGION_NUMBER1) || \ 342 ((NUMBER) == MPU_REGION_NUMBER2) || \ 343 ((NUMBER) == MPU_REGION_NUMBER3) || \ 344 ((NUMBER) == MPU_REGION_NUMBER4) || \ 345 ((NUMBER) == MPU_REGION_NUMBER5) || \ 346 ((NUMBER) == MPU_REGION_NUMBER6) || \ 347 ((NUMBER) == MPU_REGION_NUMBER7)) 348 349 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 350 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 351 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 352 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 353 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 354 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 355 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 356 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 357 358 /** 359 * @} 360 */ 361 362 /* Private functions ---------------------------------------------------------*/ 363 364 /** 365 * @} 366 */ 367 368 /** 369 * @} 370 */ 371 372 #ifdef __cplusplus 373 } 374 #endif 375 376 #endif /* __STM32U5xx_HAL_CORTEX_H */ 377 378 379
