| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 2152 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 2378 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 2525 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 2545 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 2788 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 2767 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 2791 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 2769 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 2844 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 849 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 847 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 847 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 849 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 2926 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 849 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 847 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| D | MIMX8MN6_ca53.h | 876 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 2848 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 879 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 879 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ member
|
