1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * 12 * Platform definitions 13 * Version based on requirements of MPFS MSS 14 * 15 */ 16 /*========================================================================*//** 17 @mainpage Sample file detailing how mss_sw_config.h should be constructed for 18 the MPFS MSS 19 20 @section intro_sec Introduction 21 The mss_sw_config.h has the default software configuration settings for the 22 MPFS HAL and will be located at 23 <Project-Name>/src/platform/platform_config_reference folder of the bare 24 metal SoftConsole project. The platform_config_reference is provided as a 25 default reference configuration. 26 When you want to configure the MPFS HAL with required configuration for 27 your project, the mss_sw_config.h must be edited and be placed in the 28 following project directory: 29 <Project-Name>/src/boards/<your-board>/platform_config/mpfs_hal_config/ 30 31 @section 32 33 *//*==========================================================================*/ 34 35 36 #ifndef MSS_SW_CONFIG_H_ 37 #define MSS_SW_CONFIG_H_ 38 39 /* 40 * MPFS_HAL_FIRST_HART and MPFS_HAL_LAST_HART defines are used to specify which 41 * harts to actually start. The value and the actual hart it represents are 42 * listed below: 43 * value hart 44 * 0 E51 45 * 1 U54_1 46 * 2 U54_2 47 * 3 U54_3 48 * 4 U54_4 49 * Set MPFS_HAL_FIRST_HART to a value greater than 0 if you do not want your 50 * application to start and execute code on the harts represented by smaller 51 * value numbers. 52 * Set MPFS_HAL_LAST_HART to a value smaller than 4 if you do not wish to use 53 * all U54_x harts. 54 * Harts that are not started will remain in an infinite WFI loop unless used 55 * through some other method. 56 * The value of MPFS_HAL_FIRST_HART must always be less than MPFS_HAL_LAST_HART. 57 * The value of MPFS_HAL_LAST_HART must never be greater than 4. 58 * A typical use-case where you set MPFS_HAL_FIRST_HART = 1 and 59 * MPFS_HAL_LAST_HART = 1 is when 60 * your application is running on U54_1 and a bootloader running on E51 loads 61 * your application to the target memory and kicks-off U54_1 to run it. 62 */ 63 #ifndef MPFS_HAL_FIRST_HART 64 #define MPFS_HAL_FIRST_HART 0 65 #endif 66 67 #ifndef MPFS_HAL_LAST_HART 68 #define MPFS_HAL_LAST_HART 4 69 #endif 70 71 /* 72 * IMAGE_LOADED_BY_BOOTLOADER 73 * We set IMAGE_LOADED_BY_BOOTLOADER = 0 if the application image runs from 74 * non-volatile memory after reset. (No previous stage bootloader is used.) 75 * Set IMAGE_LOADED_BY_BOOTLOADER = 1 if the application image is loaded by a 76 * previous stage bootloader. 77 * 78 * MPFS_HAL_HW_CONFIG is defined if we are a boot-loader. This is a 79 * conditional compile switch is used to determine if MPFS HAL will perform the 80 * hardware configurations or not. 81 * Defined => This program acts as a First stage bootloader and performs 82 * hardware configurations. 83 * Not defined => This program assumes that the hardware configurations are 84 * already performed (Typically by a previous boot stage) 85 * 86 * List of items initialised when MPFS_HAL_HW_CONFIG is enabled 87 * - load virtual rom (see load_virtual_rom(void) in system_startup.c) 88 * - l2 cache config 89 * - Bus error unit config 90 * - MPU config 91 * - pmp config 92 * - I/O, clock and clock mux's, DDR and SGMII 93 * - will start other harts, see text describing MPFS_HAL_FIRST_HART, 94 * MPFS_HAL_LAST_HART above 95 * 96 */ 97 #define IMAGE_LOADED_BY_BOOTLOADER 0 98 #if (IMAGE_LOADED_BY_BOOTLOADER == 0) 99 #define MPFS_HAL_HW_CONFIG 100 #endif 101 102 103 /* 104 * If you are using common memory for sharing across harts, 105 * uncomment #define MPFS_HAL_SHARED_MEM_ENABLED 106 * make sure common memory is allocated in the linker script 107 * See app_hart_common mem section in the example platform 108 * linker scripts. 109 */ 110 111 #define MPFS_HAL_SHARED_MEM_ENABLED 112 113 114 /* define the required tick rate in Milliseconds */ 115 /* if this program is running on one hart only, only that particular hart value 116 * will be used */ 117 #define HART0_TICK_RATE_MS 5UL 118 #define HART1_TICK_RATE_MS 5UL 119 #define HART2_TICK_RATE_MS 5UL 120 #define HART3_TICK_RATE_MS 5UL 121 #define HART4_TICK_RATE_MS 5UL 122 123 /* 124 * Define the size of the Hart Local Storage (HLS). 125 * In the MPFS HAL, we are using HLS for debug data storage during the initial 126 * boot phase. 127 * This includes the flags which indicate the hart state regarding boot state. 128 * The HLS will take memory from top of each stack allocated at boot time. 129 * 130 */ 131 #define HLS_DEBUG_AREA_SIZE 64 132 133 /* 134 * Bus Error Unit (BEU) configurations 135 * BEU_ENABLE => Configures the events that the BEU can report. bit value 136 * 1= enabled, 0 = disabled. 137 * BEU_PLIC_INT => Configures which accrued events should generate an 138 * interrupt to the PLIC. 139 * BEU_LOCAL_INT => Configures which accrued events should generate a 140 * local interrupt to the hart on which the event accrued. 141 */ 142 #define BEU_ENABLE 0x0ULL 143 #define BEU_PLIC_INT 0x0ULL 144 #define BEU_LOCAL_INT 0x0ULL 145 146 /* 147 * Clear memory on startup 148 * 0 => do not clear DTIM and L2 149 * 1 => Clears memory 150 * Note: If you are the zero stage bootloader, set this to one. 151 */ 152 #ifndef MPFS_HAL_CLEAR_MEMORY 153 #define MPFS_HAL_CLEAR_MEMORY 1 154 #endif 155 156 /* 157 * Comment out the lines to disable the corresponding hardware support not required 158 * in your application. 159 * This is not necessary from an operational point of view as operation dictated 160 * by MSS configurator settings, and items are enabled/disabled by this method. 161 * The reason you may want to use below is to save code space. 162 */ 163 #define SGMII_SUPPORT 164 #define DDR_SUPPORT 165 #define MSSIO_SUPPORT 166 167 /* 168 * DDR software options 169 */ 170 171 /* 172 * Debug DDR startup through a UART 173 * Comment out in normal operation. May be useful for debug purposes in bring-up 174 * of a new board design. 175 * See the weakly linked function setup_ddr_debug_port(mss_uart_instance_t * uart) 176 * If you need to edit this function, make another copy of the function in your 177 * application without the weak linking attribute. This copy will then get linked. 178 * */ 179 //#define DEBUG_DDR_INIT 180 //#define DEBUG_DDR_RD_RW_FAIL 181 //#define DEBUG_DDR_RD_RW_PASS 182 //#define DEBUG_DDR_CFG_DDR_SGMII_PHY 183 //#define DEBUG_DDR_DDRCFG 184 185 186 /* 187 * The hardware configuration settings imported from Libero project get generated 188 * into <project_name>/src/boards/<your-board>/<fpga-design-config> folder. 189 * If you need to overwrite them for testing purposes, you can do so here. 190 * e.g. If you want change the default SEG registers configuration defined by 191 * LIBERO_SETTING_SEG0_0, define it here and it will take precedence. 192 * #define LIBERO_SETTING_SEG0_0 0x80007F80UL 193 * 194 */ 195 196 #endif /* USER_CONFIG_MSS_USER_CONFIG_H_ */ 197 198
