1 /* 2 * Copyright (c) 2017-2021 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __DEVICE_CFG_H__ 18 #define __DEVICE_CFG_H__ 19 20 /** 21 * \file device_cfg.h 22 * \brief Configuration file native driver re-targeting 23 * 24 * \details This file can be used to add native driver specific macro 25 * definitions to select which peripherals are available in the build. 26 * 27 * This is a default device configuration file with all peripherals enabled. 28 */ 29 30 /* ARM GPIO */ 31 #define GPIO0_CMSDK_S 32 33 /* ARM Memory Protection Controller (MPC) SIE 200 */ 34 #define MPC_ISRAM0_S 35 #define MPC_ISRAM1_S 36 #define MPC_ISRAM2_S 37 #define MPC_ISRAM3_S 38 #define MPC_CODE_SRAM_S 39 #define MPC_CODE_SRAM_NS 40 #define MPC_MRAM_S 41 #define MPC_MRAM_NS 42 43 /* ARM Peripheral Protection Controllers (PPC) */ 44 #define AHB_PPC0_S 45 #define AHB_PPCEXP0_S 46 47 #define APB_PPC0_S 48 #define APB_PPC1_S 49 #define APB_PPCEXP0_S 50 #define APB_PPCEXP1_S 51 52 /*ARM UART Controller PL011*/ 53 #define UART1_PL011_S 54 #define UART1_PL011_NS 55 56 /* CMSDK Timers */ 57 #define CMSDK_TIMER0_S 58 #define CMSDK_TIMER0_NS 59 #define CMSDK_TIMER1_S 60 #define CMSDK_TIMER1_NS 61 62 /* ARM SCC */ 63 #define MUSCA_S1_SCC_S 64 65 /* Cache */ 66 #define SSE_200_CACHE_S 67 68 /* Default UART baud rate */ 69 #define DEFAULT_UART_BAUDRATE 115200 70 71 /* Cadence QSPI Flash Controller */ 72 #define QSPI_IP6514E_S 73 74 /* MT25QL Flash memory library */ 75 #define MT25QL_S 76 77 #endif /* __DEVICE_CFG_H__ */ 78
