1 /* 2 * Copyright (c) 2017-2021 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_cfg.h" 27 #include "device_definition.h" 28 #include "platform_base_address.h" 29 30 /* ======= Peripheral configuration structure definitions ======= */ 31 32 /* CMSDK GPIO driver structures */ 33 #ifdef GPIO0_CMSDK_S 34 static const struct gpio_cmsdk_dev_cfg_t GPIO0_CMSDK_DEV_CFG_S = { 35 .base = MUSCA_S1_GPIO_S_BASE}; 36 struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_S = {&(GPIO0_CMSDK_DEV_CFG_S)}; 37 #endif 38 39 /* ARM PPC SSE 200 driver structures */ 40 #ifdef AHB_PPC0_S 41 static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = { 42 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 43 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 44 static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = { 45 .p_ns_ppc = 0, 46 .p_sp_ppc = 0, 47 .p_nsp_ppc = 0, 48 .int_bit_mask = 0, 49 .state = 0 }; 50 struct ppc_sse200_dev_t AHB_PPC0_DEV_S = { 51 &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S }; 52 #endif 53 54 #ifdef AHB_PPCEXP0_S 55 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = { 56 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 57 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 58 static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = { 59 .p_ns_ppc = 0, 60 .p_sp_ppc = 0, 61 .p_nsp_ppc = 0, 62 .int_bit_mask = 0, 63 .state = 0 }; 64 struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = { 65 &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S }; 66 #endif 67 68 #ifdef APB_PPC0_S 69 static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = { 70 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 71 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 72 static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = { 73 .p_ns_ppc = 0, 74 .p_sp_ppc = 0, 75 .p_nsp_ppc = 0, 76 .int_bit_mask = 0, 77 .state = 0 }; 78 struct ppc_sse200_dev_t APB_PPC0_DEV_S = { 79 &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S }; 80 #endif 81 82 #ifdef APB_PPC1_S 83 static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = { 84 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 85 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 86 static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = { 87 .p_ns_ppc = 0, 88 .p_sp_ppc = 0, 89 .p_nsp_ppc = 0, 90 .int_bit_mask = 0, 91 .state = 0 }; 92 struct ppc_sse200_dev_t APB_PPC1_DEV_S = { 93 &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S}; 94 #endif 95 96 #ifdef APB_PPCEXP0_S 97 static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = { 98 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 99 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 100 static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = { 101 .p_ns_ppc = 0, 102 .p_sp_ppc = 0, 103 .p_nsp_ppc = 0, 104 .int_bit_mask = 0, 105 .state = 0 }; 106 struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = { 107 &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S }; 108 #endif 109 110 #ifdef APB_PPCEXP1_S 111 static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = { 112 .spctrl_base = MUSCA_S1_SPCTRL_S_BASE, 113 .nspctrl_base = MUSCA_S1_NSPCTRL_NS_BASE }; 114 static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = { 115 .p_ns_ppc = 0, 116 .p_sp_ppc = 0, 117 .p_nsp_ppc = 0, 118 .int_bit_mask = 0, 119 .state = 0 }; 120 struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = { 121 &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S }; 122 #endif 123 124 /* ARM MPC SIE 200 driver structures */ 125 #ifdef MPC_ISRAM0_S 126 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { 127 .base = MUSCA_S1_MPC_SRAM0_S_BASE}; 128 static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = { 129 .range_list = 0, 130 .nbr_of_ranges = 0, 131 .state = 0, 132 .reserved = 0}; 133 struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = { 134 &(MPC_ISRAM0_DEV_CFG_S), 135 &(MPC_ISRAM0_DEV_DATA_S)}; 136 #endif 137 138 #ifdef MPC_ISRAM1_S 139 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { 140 .base = MUSCA_S1_MPC_SRAM1_S_BASE}; 141 static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = { 142 .range_list = 0, 143 .nbr_of_ranges = 0, 144 .state = 0, 145 .reserved = 0}; 146 struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = { 147 &(MPC_ISRAM1_DEV_CFG_S), 148 &(MPC_ISRAM1_DEV_DATA_S)}; 149 #endif 150 151 #ifdef MPC_ISRAM2_S 152 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = { 153 .base = MUSCA_S1_MPC_SRAM2_S_BASE}; 154 static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = { 155 .range_list = 0, 156 .nbr_of_ranges = 0, 157 .state = 0, 158 .reserved = 0}; 159 struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = { 160 &(MPC_ISRAM2_DEV_CFG_S), 161 &(MPC_ISRAM2_DEV_DATA_S)}; 162 #endif 163 164 #ifdef MPC_ISRAM3_S 165 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = { 166 .base = MUSCA_S1_MPC_SRAM3_S_BASE}; 167 static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = { 168 .range_list = 0, 169 .nbr_of_ranges = 0, 170 .state = 0, 171 .reserved = 0}; 172 struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = { 173 &(MPC_ISRAM3_DEV_CFG_S), 174 &(MPC_ISRAM3_DEV_DATA_S)}; 175 #endif 176 177 #ifdef MPC_CODE_SRAM_NS 178 static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM_DEV_CFG_NS = { 179 .base = MUSCA_S1_CODE_SRAM_MPC_NS_BASE}; 180 static struct mpc_sie200_dev_data_t MPC_CODE_SRAM_DEV_DATA_NS = { 181 .range_list = 0, 182 .nbr_of_ranges = 0, 183 .state = 0, 184 .reserved = 0}; 185 struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_NS = { 186 &(MPC_CODE_SRAM_DEV_CFG_NS), 187 &(MPC_CODE_SRAM_DEV_DATA_NS)}; 188 #endif 189 190 #ifdef MPC_CODE_SRAM_S 191 static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM_DEV_CFG_S = { 192 .base = MUSCA_S1_CODE_SRAM_MPC_S_BASE}; 193 static struct mpc_sie200_dev_data_t MPC_CODE_SRAM_DEV_DATA_S = { 194 .range_list = 0, 195 .nbr_of_ranges = 0, 196 .state = 0, 197 .reserved = 0}; 198 struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_S = { 199 &(MPC_CODE_SRAM_DEV_CFG_S), 200 &(MPC_CODE_SRAM_DEV_DATA_S)}; 201 #endif 202 203 #ifdef MPC_MRAM_S 204 static const struct mpc_sie200_dev_cfg_t MPC_MRAM_DEV_CFG_S = { 205 .base = MUSCA_S1_MRAM_MPC_S_BASE}; 206 static struct mpc_sie200_dev_data_t MPC_MRAM_DEV_DATA_S = { 207 .range_list = 0, 208 .nbr_of_ranges = 0, 209 .state = 0, 210 .reserved = 0}; 211 struct mpc_sie200_dev_t MPC_MRAM_DEV_S = { 212 &(MPC_MRAM_DEV_CFG_S), 213 &(MPC_MRAM_DEV_DATA_S)}; 214 #endif 215 216 #ifdef MPC_MRAM_NS 217 static const struct mpc_sie200_dev_cfg_t MPC_MRAM_DEV_CFG_NS = { 218 .base = MUSCA_S1_MRAM_MPC_NS_BASE}; 219 static struct mpc_sie200_dev_data_t MPC_MRAM_DEV_DATA_NS = { 220 .range_list = 0, 221 .nbr_of_ranges = 0, 222 .state = 0, 223 .reserved = 0}; 224 struct mpc_sie200_dev_t MPC_MRAM_DEV_NS = { 225 &(MPC_MRAM_DEV_CFG_NS), 226 &(MPC_MRAM_DEV_DATA_NS)}; 227 #endif 228 229 /* ARM MHU driver structures */ 230 #ifdef ARM_MHU0_S 231 static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU0_DEV_CFG_S = { 232 .base = MUSCA_S1_MHU0_S_BASE}; 233 struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_S = {&(ARM_MHU0_DEV_CFG_S)}; 234 #endif 235 #ifdef ARM_MHU0_NS 236 static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU0_DEV_CFG_NS = { 237 .base = MUSCA_S1_MHU0_NS_BASE}; 238 struct arm_mhu_sse_200_dev_t ARM_MHU0_DEV_NS = {&(ARM_MHU0_DEV_CFG_NS)}; 239 #endif 240 241 #ifdef ARM_MHU1_S 242 static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU1_DEV_CFG_S = { 243 .base = MUSCA_S1_MHU1_S_BASE}; 244 struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_S = {&(ARM_MHU1_DEV_CFG_S)}; 245 #endif 246 #ifdef ARM_MHU1_NS 247 static const struct arm_mhu_sse_200_dev_cfg_t ARM_MHU1_DEV_CFG_NS = { 248 .base = MUSCA_S1_MHU1_NS_BASE}; 249 struct arm_mhu_sse_200_dev_t ARM_MHU1_DEV_NS = {&(ARM_MHU1_DEV_CFG_NS)}; 250 #endif 251 252 /* I2C IP6510 driver structures */ 253 #ifdef I2C0_IP6510_S 254 static const struct i2c_ip6510_dev_cfg_t I2C0_IP6510_DEV_CFG_S = { 255 .base = MUSCA_S1_I2C0_S_BASE, 256 .default_mode = I2C_IP6510_MASTER_MODE, 257 .default_bus_speed = I2C_IP6510_SPEED_100KHZ}; 258 static struct i2c_ip6510_dev_data_t I2C0_IP6510_DEV_DATA_S = { 259 .state = 0, 260 .mode = 0, 261 .bus_speed = 0}; 262 struct i2c_ip6510_dev_t I2C0_IP6510_DEV_S = { 263 &(I2C0_IP6510_DEV_CFG_S), 264 &(I2C0_IP6510_DEV_DATA_S)}; 265 #endif 266 267 #ifdef I2C0_IP6510_NS 268 static const struct i2c_ip6510_dev_cfg_t I2C0_IP6510_DEV_CFG_NS = { 269 .base = MUSCA_S1_I2C0_NS_BASE, 270 .default_mode = I2C_IP6510_MASTER_MODE, 271 .default_bus_speed = I2C_IP6510_SPEED_100KHZ}; 272 static struct i2c_ip6510_dev_data_t I2C0_IP6510_DEV_DATA_NS = { 273 .state = 0, 274 .mode = 0, 275 .bus_speed = 0}; 276 struct i2c_ip6510_dev_t I2C0_IP6510_DEV_NS = { 277 &(I2C0_IP6510_DEV_CFG_NS), 278 &(I2C0_IP6510_DEV_DATA_NS)}; 279 #endif 280 281 #ifdef I2C1_IP6510_S 282 static const struct i2c_ip6510_dev_cfg_t I2C1_IP6510_DEV_CFG_S = { 283 .base = MUSCA_S1_I2C1_S_BASE, 284 .default_mode = I2C_IP6510_MASTER_MODE, 285 .default_bus_speed = I2C_IP6510_SPEED_100KHZ}; 286 static struct i2c_ip6510_dev_data_t I2C1_IP6510_DEV_DATA_S = { 287 .state = 0, 288 .mode = 0, 289 .bus_speed = 0}; 290 struct i2c_ip6510_dev_t I2C1_IP6510_DEV_S = { 291 &(I2C1_IP6510_DEV_CFG_S), 292 &(I2C1_IP6510_DEV_DATA_S)}; 293 #endif 294 295 #ifdef I2C1_IP6510_NS 296 static const struct i2c_ip6510_dev_cfg_t I2C1_IP6510_DEV_CFG_NS = { 297 .base = MUSCA_S1_I2C1_NS_BASE, 298 .default_mode = I2C_IP6510_MASTER_MODE, 299 .default_bus_speed = I2C_IP6510_SPEED_100KHZ}; 300 static struct i2c_ip6510_dev_data_t I2C1_IP6510_DEV_DATA_NS = { 301 .state = 0, 302 .mode = 0, 303 .bus_speed = 0}; 304 struct i2c_ip6510_dev_t I2C1_IP6510_DEV_NS = { 305 &(I2C1_IP6510_DEV_CFG_NS), 306 &(I2C1_IP6510_DEV_DATA_NS)}; 307 #endif 308 309 /* CMSDK Timers driver structures */ 310 #ifdef CMSDK_TIMER0_S 311 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = { 312 .base = MUSCA_S1_CMSDK_TIMER0_S_BASE}; 313 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = { 314 .is_initialized = 0}; 315 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S), 316 &(CMSDK_TIMER0_DEV_DATA_S)}; 317 #endif 318 #ifdef CMSDK_TIMER0_NS 319 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = { 320 .base = MUSCA_S1_CMSDK_TIMER0_NS_BASE}; 321 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = { 322 .is_initialized = 0}; 323 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS), 324 &(CMSDK_TIMER0_DEV_DATA_NS)}; 325 #endif 326 327 #ifdef CMSDK_TIMER1_S 328 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = { 329 .base = MUSCA_S1_CMSDK_TIMER1_S_BASE}; 330 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = { 331 .is_initialized = 0}; 332 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S), 333 &(CMSDK_TIMER1_DEV_DATA_S)}; 334 #endif 335 #ifdef CMSDK_TIMER1_NS 336 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = { 337 .base = MUSCA_S1_CMSDK_TIMER1_NS_BASE}; 338 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = { 339 .is_initialized = 0}; 340 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS), 341 &(CMSDK_TIMER1_DEV_DATA_NS)}; 342 #endif 343 344 /* CMSDK Dualtimer driver structures */ 345 #ifdef CMSDK_DUALTIMER_S 346 static const struct dualtimer_cmsdk_dev_cfg_t CMSDK_DUALTIMER_DEV_CFG_S = { 347 .base = MUSCA_S1_CMSDK_DUALTIMER_S_BASE}; 348 static struct dualtimer_cmsdk_dev_data_t CMSDK_DUALTIMER_DEV_DATA_S = { 349 .is_initialized = 0}; 350 351 struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_S = { 352 &(CMSDK_DUALTIMER_DEV_CFG_S), 353 &(CMSDK_DUALTIMER_DEV_DATA_S)}; 354 #endif 355 356 #ifdef CMSDK_DUALTIMER_NS 357 static const struct dualtimer_cmsdk_dev_cfg_t CMSDK_DUALTIMER_DEV_CFG_NS = { 358 .base = MUSCA_S1_CMSDK_DUALTIMER_NS_BASE}; 359 static struct dualtimer_cmsdk_dev_data_t CMSDK_DUALTIMER_DEV_DATA_NS = { 360 .is_initialized = 0}; 361 362 struct dualtimer_cmsdk_dev_t CMSDK_DUALTIMER_DEV_NS = { 363 &(CMSDK_DUALTIMER_DEV_CFG_NS), 364 &(CMSDK_DUALTIMER_DEV_DATA_NS)}; 365 #endif 366 367 /* General-Purpose Timer driver structures */ 368 #ifdef GP_TIMER_S 369 static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_S = { 370 .base = MUSCA_S1_TIMER_S_BASE}; 371 static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_S = { 372 .is_initialized = false, 373 .alarm0_init = 0, 374 .alarm1_init = 0}; 375 struct timer_gp_dev_t GP_TIMER_DEV_S = { 376 &(GP_TIMER_DEV_CFG_S), 377 &(GP_TIMER_DEV_DATA_S)}; 378 #endif 379 380 #ifdef GP_TIMER_NS 381 static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_NS = { 382 .base = MUSCA_S1_TIMER_NS_BASE}; 383 static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_NS = { 384 .is_initialized = false, 385 .alarm0_init = 0, 386 .alarm1_init = 0}; 387 struct timer_gp_dev_t GP_TIMER_DEV_NS = { 388 &(GP_TIMER_DEV_CFG_NS), 389 &(GP_TIMER_DEV_DATA_NS)}; 390 #endif 391 392 /* PL031 Real-Time Clock structure */ 393 #ifdef RTC_PL031_S 394 static const struct rtc_pl031_dev_cfg_t RTC_PL031_DEV_CFG_S = { 395 .base = MUSCA_S1_RTC_S_BASE}; 396 struct rtc_pl031_dev_t RTC_PL031_DEV_S = {&(RTC_PL031_DEV_CFG_S)}; 397 #endif 398 399 #ifdef RTC_PL031_NS 400 static const struct rtc_pl031_dev_cfg_t RTC_PL031_DEV_CFG_NS = { 401 .base = MUSCA_S1_RTC_NS_BASE}; 402 struct rtc_pl031_dev_t RTC_PL031_DEV_NS = {&(RTC_PL031_DEV_CFG_NS)}; 403 #endif 404 405 #ifdef UART0_PL011_S 406 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = { 407 .base = MUSCA_S1_UART0_S_BASE, 408 .def_baudrate = DEFAULT_UART_BAUDRATE, 409 .def_wlen = UART_PL011_WLEN_8, 410 .def_parity = UART_PL011_PARITY_DISABLED, 411 .def_stopbit = UART_PL011_STOPBIT_1}; 412 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_S = { 413 .state = 0, 414 .uart_clk = 0, 415 .baudrate = 0}; 416 struct uart_pl011_dev_t UART0_PL011_DEV_S = {&(UART0_PL011_DEV_CFG_S), 417 &(UART0_PL011_DEV_DATA_S)}; 418 #endif 419 420 #ifdef UART0_PL011_NS 421 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = { 422 .base = MUSCA_S1_UART0_NS_BASE, 423 .def_baudrate = DEFAULT_UART_BAUDRATE, 424 .def_wlen = UART_PL011_WLEN_8, 425 .def_parity = UART_PL011_PARITY_DISABLED, 426 .def_stopbit = UART_PL011_STOPBIT_1}; 427 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_NS = { 428 .state = 0, 429 .uart_clk = 0, 430 .baudrate = 0}; 431 struct uart_pl011_dev_t UART0_PL011_DEV_NS = {&(UART0_PL011_DEV_CFG_NS), 432 &(UART0_PL011_DEV_DATA_NS)}; 433 #endif 434 435 #ifdef UART1_PL011_S 436 static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_S = { 437 .base = MUSCA_S1_UART1_S_BASE, 438 .def_baudrate = DEFAULT_UART_BAUDRATE, 439 .def_wlen = UART_PL011_WLEN_8, 440 .def_parity = UART_PL011_PARITY_DISABLED, 441 .def_stopbit = UART_PL011_STOPBIT_1}; 442 static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_S = { 443 .state = UART_PL011_UNINITIALIZED, 444 .uart_clk = 0, 445 .baudrate = 0}; 446 struct uart_pl011_dev_t UART1_PL011_DEV_S = {&(UART1_PL011_DEV_CFG_S), 447 &(UART1_PL011_DEV_DATA_S)}; 448 #endif 449 450 #ifdef UART1_PL011_NS 451 static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_NS = { 452 .base = MUSCA_S1_UART1_NS_BASE, 453 .def_baudrate = DEFAULT_UART_BAUDRATE, 454 .def_wlen = UART_PL011_WLEN_8, 455 .def_parity = UART_PL011_PARITY_DISABLED, 456 .def_stopbit = UART_PL011_STOPBIT_1}; 457 static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_NS = { 458 .state = UART_PL011_UNINITIALIZED, 459 .uart_clk = 0, 460 .baudrate = 0}; 461 struct uart_pl011_dev_t UART1_PL011_DEV_NS = {&(UART1_PL011_DEV_CFG_NS), 462 &(UART1_PL011_DEV_DATA_NS)}; 463 #endif 464 465 /* SPI IP6524 driver structures */ 466 #ifdef SPI0_IP6524_S 467 static const struct spi_ip6524_dev_cfg_t SPI0_DEV_CFG_S = { 468 .base = MUSCA_S1_SPI0_S_BASE}; 469 static struct spi_ip6524_dev_data_t SPI0_DEV_DATA_S = { 470 .state = 0}; 471 struct spi_ip6524_dev_t SPI0_DEV_S = {&(SPI0_DEV_CFG_S), 472 &(SPI0_DEV_DATA_S)}; 473 #endif 474 475 #ifdef SPI0_IP6524_NS 476 static const struct spi_ip6524_dev_cfg_t SPI0_DEV_CFG_NS = { 477 .base = MUSCA_S1_SPI0_NS_BASE}; 478 static struct spi_ip6524_dev_data_t SPI0_DEV_DATA_NS = { 479 .state = 0}; 480 struct spi_ip6524_dev_t SPI0_DEV_NS = {&(SPI0_DEV_CFG_NS), 481 &(SPI0_DEV_DATA_NS)}; 482 #endif 483 484 /* MUSCA S1 SCC driver structures */ 485 #ifdef MUSCA_S1_SCC_S 486 static const struct musca_s1_scc_dev_cfg_t MUSCA_S1_SCC_DEV_CFG_S = { 487 .base = MUSCA_S1_SCC_S_BASE}; 488 struct musca_s1_scc_dev_t MUSCA_S1_SCC_DEV_S = {&(MUSCA_S1_SCC_DEV_CFG_S)}; 489 #endif 490 491 /* SSE-200 Cache driver structure */ 492 #ifdef SSE_200_CACHE_S 493 static const struct arm_cache_dev_cfg_t SSE_200_CACHE_CFG_S = { 494 .base = MUSCA_S1_CPU_ELEMENT_S_BASE}; 495 struct arm_cache_dev_t SSE_200_CACHE_DEV_S = {&(SSE_200_CACHE_CFG_S)}; 496 #endif 497 498 /* QSPI IP6514E driver structures */ 499 #ifdef QSPI_IP6514E_NS 500 static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_NS = { 501 .base = MUSCA_S1_QSPI_REG_NS_BASE, 502 .addr_mask = (1U << 25) - 1, 503 }; 504 struct qspi_ip6514e_dev_t QSPI_DEV_NS = { 505 &QSPI_DEV_CFG_NS 506 }; 507 #endif 508 509 #ifdef QSPI_IP6514E_S 510 static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_S = { 511 .base = MUSCA_S1_QSPI_REG_S_BASE, 512 .addr_mask = (1U << 25) - 1, 513 }; 514 struct qspi_ip6514e_dev_t QSPI_DEV_S = { 515 &QSPI_DEV_CFG_S 516 }; 517 #endif 518 519 /* ======= External peripheral configuration structure definitions ======= */ 520 521 /* MT25QL Flash memory library structures */ 522 #if (defined(MT25QL_NS) && defined(QSPI_IP6514E_NS)) 523 struct mt25ql_dev_t MT25QL_DEV_NS = { 524 .controller = &QSPI_DEV_NS, 525 .direct_access_start_addr = MUSCA_S1_QSPI_FLASH_NS_BASE, 526 .baud_rate_div = 4U, 527 .size = 0x02000000U, /* 32 MiB */ 528 .config_state = { MT25QL_FUNC_STATE_NOT_INITED }, 529 }; 530 #endif 531 532 #if (defined(MT25QL_S) && defined(QSPI_IP6514E_S)) 533 struct mt25ql_dev_t MT25QL_DEV_S = { 534 .controller = &QSPI_DEV_S, 535 .direct_access_start_addr = MUSCA_S1_QSPI_FLASH_S_BASE, 536 .baud_rate_div = 4U, 537 .size = 0x02000000U, /* 32 MiB */ 538 .config_state = { MT25QL_FUNC_STATE_NOT_INITED }, 539 }; 540 #endif 541
