1 /**************************************************************************//** 2 * @file core_common.h 3 * @brief CMSIS Cortex-A AArch64 Core Common Header File 4 * @version V1.0.0 5 * @date 06. Feb 2023 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2021 Arm Limited. All rights reserved. 9 * Copyright 2023 NXP 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #if defined ( __ICCARM__ ) 27 #pragma system_include /* treat file as system include file for MISRA check */ 28 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 29 #pragma clang system_header /* treat file as system include file */ 30 #endif 31 32 #ifndef __CORE_COMMON_H 33 #define __CORE_COMMON_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /******************************************************************************* 40 * Register Definitions 41 ******************************************************************************/ 42 43 #ifndef BIT 44 #define BIT(n) (1 << (n)) 45 #endif 46 47 /* DAIF Register */ 48 #define DAIF_F_BIT BIT(6) 49 #define DAIF_I_BIT BIT(7) 50 #define DAIF_A_BIT BIT(8) 51 #define DAIF_D_BIT BIT(9) 52 53 /* System Control Register */ 54 #define SCTLR_M_BIT BIT(0) 55 #define SCTLR_A_BIT BIT(1) 56 #define SCTLR_C_BIT BIT(2) 57 #define SCTLR_SA_BIT BIT(3) 58 #define SCTLR_I_BIT BIT(12) 59 60 /* Exception levels EL0-EL3 */ 61 #define MODE_EL_SHIFT (0x2) 62 #define MODE_EL_MASK (0x3) 63 64 #define MODE_EL3 (0x3) 65 #define MODE_EL2 (0x2) 66 #define MODE_EL1 (0x1) 67 #define MODE_EL0 (0x0) 68 69 #define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 70 71 /* MPIDR */ 72 #define MPIDR_AFFLVL_MASK (0xffULL) 73 #define MPIDR_AFF0_SHIFT (0) 74 #define MPIDR_AFF1_SHIFT (8) 75 #define MPIDR_AFF2_SHIFT (16) 76 #define MPIDR_AFF3_SHIFT (32) 77 #define MPIDR_MT_MASK (0x1) 78 #define MPIDR_MT_SHIFT (24) 79 80 #define MPIDR_SUPPORT_MT(mpidr) ((mpidr >> MPIDR_MT_SHIFT) & MPIDR_MT_MASK) 81 82 83 #define MPIDR_TO_AFF_LEVEL(mpidr, aff_level) \ 84 (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK) 85 86 #define MPIDR_AFFINITY_MASK \ 87 ((MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 88 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 89 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 90 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 91 92 /******************************************************************************* 93 * Cache Functions 94 ******************************************************************************/ 95 96 #if defined (__CACHE_PRESENT) && (__CACHE_PRESENT == 1U) 97 98 #include "cache_armv8a.h" 99 100 #endif 101 102 103 /******************************************************************************* 104 * GIC Functions 105 ******************************************************************************/ 106 107 #if defined (__GIC_PRESENT) && (__GIC_PRESENT == 1U) 108 109 #include "gic_v3.h" 110 111 #endif 112 113 114 /******************************************************************************* 115 * MMU Functions 116 ******************************************************************************/ 117 118 #if defined (__MMU_PRESENT) && (__MMU_PRESENT == 1U) 119 120 #include "mmu_armv8a.h" 121 122 #endif 123 124 125 /******************************************************************************* 126 * Timer Functions 127 ******************************************************************************/ 128 129 #if defined (__TIM_PRESENT) && (__TIM_PRESENT == 1U) 130 #include "timer_armv8a.h" 131 #endif 132 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #endif /* __CORE_COMMON_H */ 139
