1 /***************************************************************************//** 2 * \file cyip_pdm.h 3 * 4 * \brief 5 * PDM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PDM_H_ 28 #define _CYIP_PDM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PDM 34 *******************************************************************************/ 35 36 #define PDM_SECTION_SIZE 0x00001000UL 37 38 /** 39 * \brief PDM registers (PDM) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 43 __IM uint32_t RESERVED[3]; 44 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ 45 __IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */ 46 __IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */ 47 __IM uint32_t RESERVED1; 48 __IOM uint32_t CMD; /*!< 0x00000020 Command */ 49 __IM uint32_t RESERVED2[7]; 50 __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */ 51 __IM uint32_t RESERVED3[175]; 52 __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */ 53 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */ 54 __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */ 55 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */ 56 __IM uint32_t RESERVED4[764]; 57 __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */ 58 __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */ 59 __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */ 60 __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */ 61 } PDM_V1_Type; /*!< Size = 3856 (0xF10) */ 62 63 64 /* PDM.CTL */ 65 #define PDM_CTL_PGA_R_Pos 0UL 66 #define PDM_CTL_PGA_R_Msk 0xFUL 67 #define PDM_CTL_PGA_L_Pos 8UL 68 #define PDM_CTL_PGA_L_Msk 0xF00UL 69 #define PDM_CTL_SOFT_MUTE_Pos 16UL 70 #define PDM_CTL_SOFT_MUTE_Msk 0x10000UL 71 #define PDM_CTL_STEP_SEL_Pos 17UL 72 #define PDM_CTL_STEP_SEL_Msk 0x20000UL 73 #define PDM_CTL_ENABLED_Pos 31UL 74 #define PDM_CTL_ENABLED_Msk 0x80000000UL 75 /* PDM.CLOCK_CTL */ 76 #define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos 0UL 77 #define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk 0x3UL 78 #define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos 4UL 79 #define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk 0x30UL 80 #define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos 8UL 81 #define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk 0xF00UL 82 #define PDM_CLOCK_CTL_SINC_RATE_Pos 16UL 83 #define PDM_CLOCK_CTL_SINC_RATE_Msk 0x7F0000UL 84 /* PDM.MODE_CTL */ 85 #define PDM_MODE_CTL_PCM_CH_SET_Pos 0UL 86 #define PDM_MODE_CTL_PCM_CH_SET_Msk 0x3UL 87 #define PDM_MODE_CTL_SWAP_LR_Pos 2UL 88 #define PDM_MODE_CTL_SWAP_LR_Msk 0x4UL 89 #define PDM_MODE_CTL_S_CYCLES_Pos 8UL 90 #define PDM_MODE_CTL_S_CYCLES_Msk 0x700UL 91 #define PDM_MODE_CTL_CKO_DELAY_Pos 16UL 92 #define PDM_MODE_CTL_CKO_DELAY_Msk 0x70000UL 93 #define PDM_MODE_CTL_HPF_GAIN_Pos 24UL 94 #define PDM_MODE_CTL_HPF_GAIN_Msk 0xF000000UL 95 #define PDM_MODE_CTL_HPF_EN_N_Pos 28UL 96 #define PDM_MODE_CTL_HPF_EN_N_Msk 0x10000000UL 97 /* PDM.DATA_CTL */ 98 #define PDM_DATA_CTL_WORD_LEN_Pos 0UL 99 #define PDM_DATA_CTL_WORD_LEN_Msk 0x3UL 100 #define PDM_DATA_CTL_BIT_EXTENSION_Pos 8UL 101 #define PDM_DATA_CTL_BIT_EXTENSION_Msk 0x100UL 102 /* PDM.CMD */ 103 #define PDM_CMD_STREAM_EN_Pos 0UL 104 #define PDM_CMD_STREAM_EN_Msk 0x1UL 105 /* PDM.TR_CTL */ 106 #define PDM_TR_CTL_RX_REQ_EN_Pos 16UL 107 #define PDM_TR_CTL_RX_REQ_EN_Msk 0x10000UL 108 /* PDM.RX_FIFO_CTL */ 109 #define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 110 #define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL 111 #define PDM_RX_FIFO_CTL_CLEAR_Pos 16UL 112 #define PDM_RX_FIFO_CTL_CLEAR_Msk 0x10000UL 113 #define PDM_RX_FIFO_CTL_FREEZE_Pos 17UL 114 #define PDM_RX_FIFO_CTL_FREEZE_Msk 0x20000UL 115 /* PDM.RX_FIFO_STATUS */ 116 #define PDM_RX_FIFO_STATUS_USED_Pos 0UL 117 #define PDM_RX_FIFO_STATUS_USED_Msk 0xFFUL 118 #define PDM_RX_FIFO_STATUS_RD_PTR_Pos 16UL 119 #define PDM_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 120 #define PDM_RX_FIFO_STATUS_WR_PTR_Pos 24UL 121 #define PDM_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 122 /* PDM.RX_FIFO_RD */ 123 #define PDM_RX_FIFO_RD_DATA_Pos 0UL 124 #define PDM_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 125 /* PDM.RX_FIFO_RD_SILENT */ 126 #define PDM_RX_FIFO_RD_SILENT_DATA_Pos 0UL 127 #define PDM_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 128 /* PDM.INTR */ 129 #define PDM_INTR_RX_TRIGGER_Pos 16UL 130 #define PDM_INTR_RX_TRIGGER_Msk 0x10000UL 131 #define PDM_INTR_RX_NOT_EMPTY_Pos 18UL 132 #define PDM_INTR_RX_NOT_EMPTY_Msk 0x40000UL 133 #define PDM_INTR_RX_OVERFLOW_Pos 21UL 134 #define PDM_INTR_RX_OVERFLOW_Msk 0x200000UL 135 #define PDM_INTR_RX_UNDERFLOW_Pos 22UL 136 #define PDM_INTR_RX_UNDERFLOW_Msk 0x400000UL 137 /* PDM.INTR_SET */ 138 #define PDM_INTR_SET_RX_TRIGGER_Pos 16UL 139 #define PDM_INTR_SET_RX_TRIGGER_Msk 0x10000UL 140 #define PDM_INTR_SET_RX_NOT_EMPTY_Pos 18UL 141 #define PDM_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL 142 #define PDM_INTR_SET_RX_OVERFLOW_Pos 21UL 143 #define PDM_INTR_SET_RX_OVERFLOW_Msk 0x200000UL 144 #define PDM_INTR_SET_RX_UNDERFLOW_Pos 22UL 145 #define PDM_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL 146 /* PDM.INTR_MASK */ 147 #define PDM_INTR_MASK_RX_TRIGGER_Pos 16UL 148 #define PDM_INTR_MASK_RX_TRIGGER_Msk 0x10000UL 149 #define PDM_INTR_MASK_RX_NOT_EMPTY_Pos 18UL 150 #define PDM_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL 151 #define PDM_INTR_MASK_RX_OVERFLOW_Pos 21UL 152 #define PDM_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL 153 #define PDM_INTR_MASK_RX_UNDERFLOW_Pos 22UL 154 #define PDM_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL 155 /* PDM.INTR_MASKED */ 156 #define PDM_INTR_MASKED_RX_TRIGGER_Pos 16UL 157 #define PDM_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL 158 #define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL 159 #define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL 160 #define PDM_INTR_MASKED_RX_OVERFLOW_Pos 21UL 161 #define PDM_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL 162 #define PDM_INTR_MASKED_RX_UNDERFLOW_Pos 22UL 163 #define PDM_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL 164 165 166 #endif /* _CYIP_PDM_H_ */ 167 168 169 /* [] END OF FILE */ 170
