1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #ifndef __ASSEMBLER__ 10 #include <stdint.h> 11 #include "esp_assert.h" 12 #endif 13 14 #include "esp_bit_defs.h" 15 #include "reg_base.h" 16 #include "stubs.h" 17 18 #define PRO_CPU_NUM (0) 19 20 #define DR_REG_RTC_BLE_TIMER_BASE( i ) ( \ 21 ( (i) == 0 ) ? ( 0x6004E000 ) : \ 22 ( (i) == 1 ) ? ( 0x6004E100 ) : \ 23 ( (i) == 2 ) ? ( 0x6004E200 ) : \ 24 0 \ 25 ) 26 27 28 #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) 29 #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) 30 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) 31 #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) 32 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) 33 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) 34 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI 35 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) 36 37 //Registers Operation {{ 38 #define ETS_UNCACHED_ADDR(addr) (addr) 39 #define ETS_CACHED_ADDR(addr) (addr) 40 41 #ifndef __ASSEMBLER__ 42 43 //write value to register 44 #define REG_WRITE(_r, _v) do { \ 45 (*(volatile uint32_t *)(_r)) = (_v); \ 46 } while(0) 47 48 //read value from register 49 #define REG_READ(_r) ({ \ 50 (*(volatile uint32_t *)(_r)); \ 51 }) 52 53 //get bit or get bits from register 54 #define REG_GET_BIT(_r, _b) ({ \ 55 (*(volatile uint32_t*)(_r) & (_b)); \ 56 }) 57 58 //set bit or set bits to register 59 #define REG_SET_BIT(_r, _b) do { \ 60 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ 61 } while(0) 62 63 //clear bit or clear bits of register 64 #define REG_CLR_BIT(_r, _b) do { \ 65 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ 66 } while(0) 67 68 //set bits of register controlled by mask 69 #define REG_SET_BITS(_r, _b, _m) do { \ 70 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ 71 } while(0) 72 73 //get field from register, uses field _S & _V to determine mask 74 #define REG_GET_FIELD(_r, _f) ({ \ 75 ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ 76 }) 77 78 //set field of a register from variable, uses field _S & _V to determine mask 79 #define REG_SET_FIELD(_r, _f, _v) do { \ 80 REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ 81 } while(0) 82 83 //get field value from a variable, used when _f is not left shifted by _f##_S 84 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) 85 86 //get field value from a variable, used when _f is left shifted by _f##_S 87 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) 88 89 //set field value to a variable, used when _f is not left shifted by _f##_S 90 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) 91 92 //set field value to a variable, used when _f is left shifted by _f##_S 93 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) 94 95 //generate a value from a field value, used when _f is not left shifted by _f##_S 96 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) 97 98 //generate a value from a field value, used when _f is left shifted by _f##_S 99 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) 100 101 //read value from register 102 #define READ_PERI_REG(addr) ({ \ 103 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ 104 }) 105 106 //write value to register 107 #define WRITE_PERI_REG(addr, val) do { \ 108 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ 109 } while(0) 110 111 //clear bits of register controlled by mask 112 #define CLEAR_PERI_REG_MASK(reg, mask) do { \ 113 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ 114 } while(0) 115 116 //set bits of register controlled by mask 117 #define SET_PERI_REG_MASK(reg, mask) do { \ 118 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ 119 } while(0) 120 121 //get bits of register controlled by mask 122 #define GET_PERI_REG_MASK(reg, mask) ({ \ 123 (READ_PERI_REG(reg) & (mask)); \ 124 }) 125 126 //get bits of register controlled by highest bit and lowest bit 127 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ 128 ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ 129 }) 130 131 //set bits of register controlled by mask and shift 132 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ 133 WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ 134 } while(0) 135 136 //get field of register 137 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ 138 ((READ_PERI_REG(reg)>>(shift))&(mask)); \ 139 }) 140 141 #endif /* !__ASSEMBLER__ */ 142 //}} 143 144 //Periheral Clock {{ 145 #define APB_CLK_FREQ_ROM ( 40*1000000 ) 146 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM 147 #define EFUSE_CLK_FREQ_ROM ( 20*1000000) 148 #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration 149 #define CPU_CLK_FREQ APB_CLK_FREQ 150 #define APB_CLK_FREQ ( CONFIG_XTAL_FREQ * 1000000 ) 151 #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) 152 #define REF_CLK_FREQ ( 1000000 ) 153 #define UART_CLK_FREQ APB_CLK_FREQ 154 #define WDT_CLK_FREQ APB_CLK_FREQ 155 #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4 156 #define SPI_CLK_DIV 4 157 #define TICKS_PER_US_ROM 40 // CPU is 40MHz 158 #define GPIO_MATRIX_DELAY_NS 0 159 //}} 160 161 /* Overall memory map */ 162 #define SOC_DROM_LOW 0x3C000000 163 #define SOC_DROM_HIGH 0x3C400000 164 #define SOC_IROM_LOW 0x42000000 165 #define SOC_IROM_HIGH 0x42400000 166 #define SOC_IROM_MASK_LOW 0x40000000 167 #define SOC_IROM_MASK_HIGH 0x40090000 168 #define SOC_DROM_MASK_LOW 0x3FF00000 169 #define SOC_DROM_MASK_HIGH 0x3FF50000 170 #define SOC_IRAM_LOW 0x4037C000 171 #define SOC_IRAM_HIGH 0x403C0000 172 #define SOC_DRAM_LOW 0x3FCA0000 173 #define SOC_DRAM_HIGH 0x3FCE0000 174 175 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. 176 #define SOC_DIRAM_IRAM_LOW 0x40380000 177 #define SOC_DIRAM_IRAM_HIGH 0x403C0000 178 #define SOC_DIRAM_DRAM_LOW 0x3FCA0000 179 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 180 181 #define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 182 #define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) 183 #define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) 184 185 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). 186 #define SOC_DMA_LOW 0x3FCA0000 187 #define SOC_DMA_HIGH 0x3FCE0000 188 189 // Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). 190 #define SOC_BYTE_ACCESSIBLE_LOW 0x3FCA0000 191 #define SOC_BYTE_ACCESSIBLE_HIGH 0x3FCE0000 192 193 //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs 194 //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). 195 #define SOC_MEM_INTERNAL_LOW 0x3FCA0000 196 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 197 198 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space 199 200 // Region of address space that holds peripherals 201 #define SOC_PERIPHERAL_LOW 0x60000000 202 #define SOC_PERIPHERAL_HIGH 0x60100000 203 204 // Debug region, not used by software 205 #define SOC_DEBUG_LOW 0x20000000 206 #define SOC_DEBUG_HIGH 0x28000000 207 208 // Start (highest address) of ROM boot stack, only relevant during early boot 209 #define SOC_ROM_STACK_START 0x3fcdeb70 210 #define SOC_ROM_STACK_SIZE 0x2000 211 212 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. 213 //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. 214 215 //CPU0 Interrupt number reserved in riscv/vector.S, not touch this. 216 217 #define ETS_T0_WDT_INUM 24 218 #define ETS_CACHEERR_INUM 25 219 #define ETS_MEMPROT_ERR_INUM 26 220 #define ETS_DPORT_INUM 28 221 222 //CPU0 Max valid interrupt number 223 #define ETS_MAX_INUM 31 224 225 //CPU0 Interrupt number used in ROM, should be cancelled in SDK 226 #define ETS_SLC_INUM 1 227 #define ETS_UART0_INUM 5 228 #define ETS_UART1_INUM 5 229 #define ETS_SPI2_INUM 1 230 //CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. 231 #define ETS_GPIO_INUM 4 232 233 //Other interrupt number should be managed by the user 234 235 //Invalid interrupt for number interrupt matrix 236 #define ETS_INVALID_INUM 0 237 238 //Interrupt medium level, used for INT WDT for example 239 #define SOC_INTERRUPT_LEVEL_MEDIUM 4 240 241 // Interrupt number for the Interrupt watchdog 242 #define ETS_INT_WDT_INUM (ETS_T0_WDT_INUM) 243
