1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MMC_H 8 #define MMC_H 9 10 #include <stdint.h> 11 12 #include <lib/utils_def.h> 13 14 #define MMC_BLOCK_SIZE U(512) 15 #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1)) 16 #define MMC_BOOT_CLK_RATE (400 * 1000) 17 18 #define MMC_CMD(_x) U(_x) 19 20 #define MMC_ACMD(_x) U(_x) 21 22 #define OCR_POWERUP BIT(31) 23 #define OCR_HCS BIT(30) 24 #define OCR_BYTE_MODE (U(0) << 29) 25 #define OCR_SECTOR_MODE (U(2) << 29) 26 #define OCR_ACCESS_MODE_MASK (U(3) << 29) 27 #define OCR_3_5_3_6 BIT(23) 28 #define OCR_3_4_3_5 BIT(22) 29 #define OCR_3_3_3_4 BIT(21) 30 #define OCR_3_2_3_3 BIT(20) 31 #define OCR_3_1_3_2 BIT(19) 32 #define OCR_3_0_3_1 BIT(18) 33 #define OCR_2_9_3_0 BIT(17) 34 #define OCR_2_8_2_9 BIT(16) 35 #define OCR_2_7_2_8 BIT(15) 36 #define OCR_VDD_MIN_2V7 GENMASK(23, 15) 37 #define OCR_VDD_MIN_2V0 GENMASK(14, 8) 38 #define OCR_VDD_MIN_1V7 BIT(7) 39 40 #define MMC_RSP_48 BIT(0) 41 #define MMC_RSP_136 BIT(1) /* 136 bit response */ 42 #define MMC_RSP_CRC BIT(2) /* expect valid crc */ 43 #define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */ 44 #define MMC_RSP_BUSY BIT(4) /* device may be busy */ 45 46 /* JEDEC 4.51 chapter 6.12 */ 47 #define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC) 48 #define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY) 49 #define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC) 50 #define MMC_RESPONSE_R3 (MMC_RSP_48) 51 #define MMC_RESPONSE_R4 (MMC_RSP_48) 52 #define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 53 #define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 54 #define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 55 56 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 57 #define MMC_FIX_RCA 6 58 #define RCA_SHIFT_OFFSET 16 59 60 #define CMD_EXTCSD_PARTITION_CONFIG 179 61 #define CMD_EXTCSD_BUS_WIDTH 183 62 #define CMD_EXTCSD_HS_TIMING 185 63 #define CMD_EXTCSD_PART_SWITCH_TIME 199 64 #define CMD_EXTCSD_SEC_CNT 212 65 66 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0) 67 #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 68 #define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0) 69 #define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0) 70 #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3) 71 #define PART_CFG_BOOT_PART_EN_SHIFT 3 72 #define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \ 73 PART_CFG_BOOT_PART_EN_SHIFT) 74 75 /* Values in EXT CSD register */ 76 #define MMC_BUS_WIDTH_1 U(0) 77 #define MMC_BUS_WIDTH_4 U(1) 78 #define MMC_BUS_WIDTH_8 U(2) 79 #define MMC_BUS_WIDTH_DDR_4 U(5) 80 #define MMC_BUS_WIDTH_DDR_8 U(6) 81 #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 82 #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 83 #define MMC_BOOT_MODE_DDR (U(2) << 3) 84 85 #define EXTCSD_SET_CMD (U(0) << 24) 86 #define EXTCSD_SET_BITS (U(1) << 24) 87 #define EXTCSD_CLR_BITS (U(2) << 24) 88 #define EXTCSD_WRITE_BYTES (U(3) << 24) 89 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 90 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 91 #define EXTCSD_CMD_SET_NORMAL U(1) 92 93 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 94 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 95 #define CSD_TRAN_SPEED_MULT_SHIFT 3 96 97 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 98 #define STATUS_READY_FOR_DATA BIT(8) 99 #define STATUS_SWITCH_ERROR BIT(7) 100 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 101 #define MMC_STATE_IDLE 0 102 #define MMC_STATE_READY 1 103 #define MMC_STATE_IDENT 2 104 #define MMC_STATE_STBY 3 105 #define MMC_STATE_TRAN 4 106 #define MMC_STATE_DATA 5 107 #define MMC_STATE_RCV 6 108 #define MMC_STATE_PRG 7 109 #define MMC_STATE_DIS 8 110 #define MMC_STATE_BTST 9 111 #define MMC_STATE_SLP 10 112 113 #define MMC_FLAG_CMD23 (U(1) << 0) 114 115 #define CMD8_CHECK_PATTERN U(0xAA) 116 #define VHS_2_7_3_6_V BIT(8) 117 118 #define SD_SCR_BUS_WIDTH_1 BIT(8) 119 #define SD_SCR_BUS_WIDTH_4 BIT(10) 120 121 struct mmc_cmd { 122 unsigned int cmd_idx; 123 unsigned int cmd_arg; 124 unsigned int resp_type; 125 unsigned int resp_data[4]; 126 }; 127 128 struct mmc_ops { 129 void (*init)(void); 130 int (*send_cmd)(struct mmc_cmd *cmd); 131 int (*set_ios)(unsigned int clk, unsigned int width); 132 int (*prepare)(int lba, uintptr_t buf, size_t size); 133 int (*read)(int lba, uintptr_t buf, size_t size); 134 int (*write)(int lba, const uintptr_t buf, size_t size); 135 }; 136 137 struct mmc_csd_emmc { 138 unsigned int not_used: 1; 139 unsigned int crc: 7; 140 unsigned int ecc: 2; 141 unsigned int file_format: 2; 142 unsigned int tmp_write_protect: 1; 143 unsigned int perm_write_protect: 1; 144 unsigned int copy: 1; 145 unsigned int file_format_grp: 1; 146 147 unsigned int reserved_1: 5; 148 unsigned int write_bl_partial: 1; 149 unsigned int write_bl_len: 4; 150 unsigned int r2w_factor: 3; 151 unsigned int default_ecc: 2; 152 unsigned int wp_grp_enable: 1; 153 154 unsigned int wp_grp_size: 5; 155 unsigned int erase_grp_mult: 5; 156 unsigned int erase_grp_size: 5; 157 unsigned int c_size_mult: 3; 158 unsigned int vdd_w_curr_max: 3; 159 unsigned int vdd_w_curr_min: 3; 160 unsigned int vdd_r_curr_max: 3; 161 unsigned int vdd_r_curr_min: 3; 162 unsigned int c_size_low: 2; 163 164 unsigned int c_size_high: 10; 165 unsigned int reserved_2: 2; 166 unsigned int dsr_imp: 1; 167 unsigned int read_blk_misalign: 1; 168 unsigned int write_blk_misalign: 1; 169 unsigned int read_bl_partial: 1; 170 unsigned int read_bl_len: 4; 171 unsigned int ccc: 12; 172 173 unsigned int tran_speed: 8; 174 unsigned int nsac: 8; 175 unsigned int taac: 8; 176 unsigned int reserved_3: 2; 177 unsigned int spec_vers: 4; 178 unsigned int csd_structure: 2; 179 }; 180 181 struct mmc_csd_sd_v2 { 182 unsigned int not_used: 1; 183 unsigned int crc: 7; 184 unsigned int reserved_1: 2; 185 unsigned int file_format: 2; 186 unsigned int tmp_write_protect: 1; 187 unsigned int perm_write_protect: 1; 188 unsigned int copy: 1; 189 unsigned int file_format_grp: 1; 190 191 unsigned int reserved_2: 5; 192 unsigned int write_bl_partial: 1; 193 unsigned int write_bl_len: 4; 194 unsigned int r2w_factor: 3; 195 unsigned int reserved_3: 2; 196 unsigned int wp_grp_enable: 1; 197 198 unsigned int wp_grp_size: 7; 199 unsigned int sector_size: 7; 200 unsigned int erase_block_en: 1; 201 unsigned int reserved_4: 1; 202 unsigned int c_size_low: 16; 203 204 unsigned int c_size_high: 6; 205 unsigned int reserved_5: 6; 206 unsigned int dsr_imp: 1; 207 unsigned int read_blk_misalign: 1; 208 unsigned int write_blk_misalign: 1; 209 unsigned int read_bl_partial: 1; 210 unsigned int read_bl_len: 4; 211 unsigned int ccc: 12; 212 213 unsigned int tran_speed: 8; 214 unsigned int nsac: 8; 215 unsigned int taac: 8; 216 unsigned int reserved_6: 6; 217 unsigned int csd_structure: 2; 218 }; 219 220 enum mmc_device_type { 221 MMC_IS_EMMC, 222 MMC_IS_SD, 223 MMC_IS_SD_HC, 224 }; 225 226 struct mmc_device_info { 227 unsigned long long device_size; /* Size of device in bytes */ 228 unsigned int block_size; /* Block size in bytes */ 229 unsigned int max_bus_freq; /* Max bus freq in Hz */ 230 unsigned int ocr_voltage; /* OCR voltage */ 231 enum mmc_device_type mmc_dev_type; /* Type of MMC */ 232 }; 233 234 size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size); 235 size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size); 236 size_t mmc_erase_blocks(int lba, size_t size); 237 int mmc_part_switch_current_boot(void); 238 int mmc_part_switch_user(void); 239 size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size); 240 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, 241 unsigned int width, unsigned int flags, 242 struct mmc_device_info *device_info); 243 244 #endif /* MMC_H */ 245
