1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef MMA865x_H_ 9 #define MMA865x_H_ 10 11 /** 12 ** 13 ** MMA865x Sensor Internal Registers 14 */ 15 enum { 16 MMA865x_STATUS = 0x00, 17 MMA865x_F_STATUS = 0x00, 18 MMA865x_OUT_X_MSB = 0x01, 19 MMA865x_OUT_X_LSB = 0x02, 20 MMA865x_OUT_Y_MSB = 0x03, 21 MMA865x_OUT_Y_LSB = 0x04, 22 MMA865x_OUT_Z_MSB = 0x05, 23 MMA865x_OUT_Z_LSB = 0x06, 24 MMA865x_F_SETUP = 0x09, 25 MMA865x_TRIG_CFG = 0x0A, 26 MMA865x_SYSMOD = 0x0B, 27 MMA865x_INT_SOURCE = 0x0C, 28 MMA865x_WHO_AM_I = 0x0D, 29 MMA865x_XYZ_DATA_CFG = 0x0E, 30 MMA865x_HP_FILTER_CUTOFF = 0x0F, 31 MMA865x_PL_STATUS = 0x10, 32 MMA865x_PL_CFG = 0x11, 33 MMA865x_PL_COUNT = 0x12, 34 MMA865x_PL_BF_ZCOMP = 0x13, 35 MMA865x_P_L_THS_REG = 0x14, 36 MMA865x_FF_MT_CFG = 0x15, 37 MMA865x_FF_MT_SRC = 0x16, 38 MMA865x_FF_MT_THS = 0x17, 39 MMA865x_FF_MT_COUNT = 0x18, 40 MMA865x_TRANSIENT_CFG = 0x1D, 41 MMA865x_TRANSIENT_SRC = 0x1E, 42 MMA865x_TRANSIENT_THS = 0x1F, 43 MMA865x_TRANSIENT_COUNT = 0x20, 44 MMA865x_PULSE_CFG = 0x21, 45 MMA865x_PULSE_SRC = 0x22, 46 MMA865x_PULSE_THSX = 0x23, 47 MMA865x_PULSE_THSY = 0x24, 48 MMA865x_PULSE_THSZ = 0x25, 49 MMA865x_PULSE_TMLT = 0x26, 50 MMA865x_PULSE_LTCY = 0x27, 51 MMA865x_PULSE_WIND = 0x28, 52 MMA865x_ASLP_COUNT = 0x29, 53 MMA865x_CTRL_REG1 = 0x2A, 54 MMA865x_CTRL_REG2 = 0x2B, 55 MMA865x_CTRL_REG3 = 0x2C, 56 MMA865x_CTRL_REG4 = 0x2D, 57 MMA865x_CTRL_REG5 = 0x2E, 58 MMA865x_OFF_X = 0x2F, 59 MMA865x_OFF_Y = 0x30, 60 MMA865x_OFF_Z = 0x31, 61 }; 62 63 64 #define MMA865x_I2C_ADDRESS (0x1D) /* MMA865x I2C Slave Address. */ 65 #define MMA8652_WHOAMI_VALUE (0x4A) /* MMA8652 Who_Am_I Value. */ 66 #define MMA8653_WHOAMI_VALUE (0x5A) /* MMA8653 Who_Am_I Value. */ 67 68 69 70 /*-------------------------------- 71 ** Register: STATUS 72 ** Enum: MMA865x_STATUS 73 ** -- 74 ** Offset : 0x00 - Data Status register (F_MODE = 00) 75 ** ------------------------------*/ 76 typedef union { 77 struct { 78 uint8_t xdr : 1; /* - X-Axis new Data Available. */ 79 80 uint8_t ydr : 1; /* - Y-Axis new data available. */ 81 82 uint8_t zdr : 1; /* - Z-Axis new data available. */ 83 84 uint8_t zyxdr : 1; /* - X or Y or Z-Axis new data available. */ 85 86 uint8_t xow : 1; /* - X-Axis data overwrite. */ 87 88 uint8_t yow : 1; /* - Y-Axis data overwrite. */ 89 90 uint8_t zow : 1; /* - Z-Axis data overwrite. */ 91 92 uint8_t zyxow : 1; /* - X, Y, Z-Axis data overwrite. */ 93 94 } b; 95 uint8_t w; 96 } MMA865x_STATUS_t; 97 98 99 /* 100 ** STATUS - Bit field mask definitions 101 */ 102 #define MMA865x_STATUS_XDR_MASK ((uint8_t) 0x01) 103 #define MMA865x_STATUS_XDR_SHIFT ((uint8_t) 0) 104 105 #define MMA865x_STATUS_YDR_MASK ((uint8_t) 0x02) 106 #define MMA865x_STATUS_YDR_SHIFT ((uint8_t) 1) 107 108 #define MMA865x_STATUS_ZDR_MASK ((uint8_t) 0x04) 109 #define MMA865x_STATUS_ZDR_SHIFT ((uint8_t) 2) 110 111 #define MMA865x_STATUS_ZYXDR_MASK ((uint8_t) 0x08) 112 #define MMA865x_STATUS_ZYXDR_SHIFT ((uint8_t) 3) 113 114 #define MMA865x_STATUS_XOW_MASK ((uint8_t) 0x10) 115 #define MMA865x_STATUS_XOW_SHIFT ((uint8_t) 4) 116 117 #define MMA865x_STATUS_YOW_MASK ((uint8_t) 0x20) 118 #define MMA865x_STATUS_YOW_SHIFT ((uint8_t) 5) 119 120 #define MMA865x_STATUS_ZOW_MASK ((uint8_t) 0x40) 121 #define MMA865x_STATUS_ZOW_SHIFT ((uint8_t) 6) 122 123 #define MMA865x_STATUS_ZYXOW_MASK ((uint8_t) 0x80) 124 #define MMA865x_STATUS_ZYXOW_SHIFT ((uint8_t) 7) 125 126 127 /* 128 ** STATUS - Bit field value definitions 129 */ 130 #define MMA865x_STATUS_XDR_DRDY ((uint8_t) 0x01) /* - Set to 1 whenever new X-axis data acquisition is */ 131 /* completed. XDR is cleared any time OUT_X_MSB register */ 132 /* is read. */ 133 #define MMA865x_STATUS_YDR_DRDY ((uint8_t) 0x02) /* - Set to 1 whenever new Y-axis data acquisition is */ 134 /* completed. YDR is cleared any time OUT_Y_MSB register */ 135 /* is read. */ 136 #define MMA865x_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* - Set to 1 whenever new Z-axis data acquisition is */ 137 /* completed. ZDR is cleared any time OUT_Z_MSB register */ 138 /* is read. */ 139 #define MMA865x_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* - Signals that new acquisition for any of the enabled */ 140 /* channels is available. ZYXDR is cleared when the */ 141 /* high-bytes of the data (OUT_X_MSB, OUT_Y_MSB, */ 142 /* OUT_Z_MSB) of all the enabled channels are read. */ 143 #define MMA865x_STATUS_XOW_OWR ((uint8_t) 0x10) /* - Set to 1 whenever new X-axis acquisition is */ 144 /* completed before the retrieval of the previous data. */ 145 /* When this occurs the previous data is overwritten. XOW */ 146 /* is cleared any time OUT_X_MSB register is read. */ 147 #define MMA865x_STATUS_YOW_OWR ((uint8_t) 0x20) /* - Set to 1 whenever new Y-axis acquisition is */ 148 /* completed before the retrieval of the previous data. */ 149 /* When this occurs the previous data is overwritten. YOW */ 150 /* is cleared any time OUT_Y_MSB register is read. */ 151 #define MMA865x_STATUS_ZOW_OWR ((uint8_t) 0x40) /* - Set to 1 whenever new Z-axis acquisition is */ 152 /* completed before the retrieval of the previous data. */ 153 /* When this occurs the previous data is overwritten. ZOW */ 154 /* is cleared any time OUT_Z_MSB register is read. */ 155 #define MMA865x_STATUS_ZYXOW_OWR ((uint8_t) 0x80) /* - Set to 1 whenever new data is acquired before */ 156 /* completing the retrieval of the previous set. This */ 157 /* event occurs when the content of at least one data */ 158 /* register (i.e. OUT_X, OUT_Y, OUT_Z) has been */ 159 /* overwritten. ZYXOW is cleared when the highbytes of */ 160 /* the data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all */ 161 /* active channels are read. */ 162 /*------------------------------*/ 163 164 165 166 167 /*-------------------------------- 168 ** Register: F_STATUS 169 ** Enum: MMA865x_F_STATUS 170 ** -- 171 ** Offset : 0x00 - FIFO Status register (F_MODE > 0) 172 ** ------------------------------*/ 173 typedef union { 174 struct { 175 uint8_t f_cnt : 6; /* - FIFO sample counter; indicates the number of samples currently stored in */ 176 /* the FIFO. */ 177 178 uint8_t f_wmkf : 1; /* - FIFO sample count greater than or equal to the watermark count (F_SETUP */ 179 /* :: F_WMRK) has been detected. */ 180 181 uint8_t f_ovf : 1; /* - FIFO overflow event, such as when F_CNT = 32 and a new sample arrives, */ 182 /* asserts the F_OVF flag. */ 183 184 } b; 185 uint8_t w; 186 } MMA865x_F_STATUS_t; 187 188 189 /* 190 ** F_STATUS - Bit field mask definitions 191 */ 192 #define MMA865x_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F) 193 #define MMA865x_F_STATUS_F_CNT_SHIFT ((uint8_t) 0) 194 195 #define MMA865x_F_STATUS_F_WMKF_MASK ((uint8_t) 0x40) 196 #define MMA865x_F_STATUS_F_WMKF_SHIFT ((uint8_t) 6) 197 198 #define MMA865x_F_STATUS_F_OVF_MASK ((uint8_t) 0x80) 199 #define MMA865x_F_STATUS_F_OVF_SHIFT ((uint8_t) 7) 200 201 202 /* 203 ** F_STATUS - Bit field value definitions 204 */ 205 #define MMA865x_F_STATUS_F_WMKF_NONE ((uint8_t) 0x00) /* - FIFO Watermark event has NOT been detected. */ 206 #define MMA865x_F_STATUS_F_WMKF_DETECTED ((uint8_t) 0x40) /* - FIFO Watermark event has been detected. */ 207 #define MMA865x_F_STATUS_F_OVF_NONE ((uint8_t) 0x00) /* - FIFO Overflow event has NOT been detected. */ 208 #define MMA865x_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* - FIFO Overflow event has been detected. */ 209 /*------------------------------*/ 210 211 212 213 214 /*-------------------------------- 215 ** Register: OUT_X_MSB 216 ** Enum: MMA865x_OUT_X_MSB 217 ** -- 218 ** Offset : 0x01 - Bits 8-15 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 219 ** ------------------------------*/ 220 typedef uint8_t MMA865x_OUT_X_MSB_t; 221 222 223 /*-------------------------------- 224 ** Register: OUT_X_LSB 225 ** Enum: MMA865x_OUT_X_LSB 226 ** -- 227 ** Offset : 0x02 - Bits 0-7 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 228 ** ------------------------------*/ 229 typedef uint8_t MMA865x_OUT_X_LSB_t; 230 231 232 /*-------------------------------- 233 ** Register: OUT_Y_MSB 234 ** Enum: MMA865x_OUT_Y_MSB 235 ** -- 236 ** Offset : 0x03 - Bits 8-15 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 237 ** ------------------------------*/ 238 typedef uint8_t MMA865x_OUT_Y_MSB_t; 239 240 241 /*-------------------------------- 242 ** Register: OUT_Y_LSB 243 ** Enum: MMA865x_OUT_Y_LSB 244 ** -- 245 ** Offset : 0x04 - Bits 0-7 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 246 ** ------------------------------*/ 247 typedef uint8_t MMA865x_OUT_Y_LSB_t; 248 249 250 /*-------------------------------- 251 ** Register: OUT_Z_MSB 252 ** Enum: MMA865x_OUT_Z_MSB 253 ** -- 254 ** Offset : 0x05 - Bits 8-15 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 255 ** ------------------------------*/ 256 typedef uint8_t MMA865x_OUT_Z_MSB_t; 257 258 259 /*-------------------------------- 260 ** Register: OUT_Z_LSB 261 ** Enum: MMA865x_OUT_Z_LSB 262 ** -- 263 ** Offset : 0x06 - Bits 0-7 of 12-bit real-time Magnetic Field Strength sample expressed as signed 2's complement numbers. 264 ** ------------------------------*/ 265 typedef uint8_t MMA865x_OUT_Z_LSB_t; 266 267 268 269 270 /*-------------------------------- 271 ** Register: F_SETUP 272 ** Enum: MMA865x_F_SETUP 273 ** -- 274 ** Offset : 0x09 - FIFO configuration 275 ** ------------------------------*/ 276 typedef union { 277 struct { 278 uint8_t f_wmrk : 6; /* - FIFO sample count watermark setting. */ 279 280 uint8_t f_mode : 2; /* - FIFO operating mode selection. */ 281 282 } b; 283 uint8_t w; 284 } MMA865x_F_SETUP_t; 285 286 287 /* 288 ** F_SETUP - Bit field mask definitions 289 */ 290 #define MMA865x_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F) 291 #define MMA865x_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0) 292 293 #define MMA865x_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0) 294 #define MMA865x_F_SETUP_F_MODE_SHIFT ((uint8_t) 6) 295 296 297 /* 298 ** F_SETUP - Bit field value definitions 299 */ 300 #define MMA865x_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* - FIFO is disabled. */ 301 #define MMA865x_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* - FIFO is in Circular Buffer mode. */ 302 #define MMA865x_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* - FIFO is in Stop mode. */ 303 #define MMA865x_F_SETUP_F_MODE_TRIG_MODE ((uint8_t) 0xc0) /* - FIFO is in Trigger mode. The FIFO will be in a */ 304 /* circular mode until the trigger event occurs, after */ 305 /* which the FIFO will continue to accept samples for */ 306 /* WMRK samples and then stop receiving further samples. */ 307 /*------------------------------*/ 308 309 310 311 312 /*-------------------------------- 313 ** Register: TRIG_CFG 314 ** Enum: MMA865x_TRIG_CFG 315 ** -- 316 ** Offset : 0x0A - Trigger Configuration register 317 ** ------------------------------*/ 318 typedef union { 319 struct { 320 uint8_t _reserved_ : 2; 321 uint8_t trig_ff_mt : 1; /* - Freefall/Motion Trigger. */ 322 323 uint8_t trig_pulse : 1; /* - Pulse Interrupt Trigger. */ 324 325 uint8_t trig_lndprt : 1; /* - Landscape/Portrait Orientation Interrupt Trigger. */ 326 327 uint8_t trig_trans : 1; /* - Transient Interrupt Trigger. */ 328 329 } b; 330 uint8_t w; 331 } MMA865x_TRIG_CFG_t; 332 333 334 /* 335 ** TRIG_CFG - Bit field mask definitions 336 */ 337 #define MMA865x_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04) 338 #define MMA865x_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2) 339 340 #define MMA865x_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08) 341 #define MMA865x_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3) 342 343 #define MMA865x_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10) 344 #define MMA865x_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4) 345 346 #define MMA865x_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20) 347 #define MMA865x_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5) 348 349 350 /* 351 ** TRIG_CFG - Bit field value definitions 352 */ 353 #define MMA865x_TRIG_CFG_TRIG_TRANS_EN ((uint8_t) 0x20) /* - This function can trigger the FIFO at its (the */ 354 /* function�s) interrupt. */ 355 #define MMA865x_TRIG_CFG_TRIG_TRANS_DISABLED ((uint8_t) 0x00) /* - This function has not asserted its interrupt. */ 356 #define MMA865x_TRIG_CFG_TRIG_LNDPRT_EN ((uint8_t) 0x10) /* - This function can trigger the FIFO at its (the */ 357 /* function�s) interrupt. */ 358 #define MMA865x_TRIG_CFG_TRIG_LNDPRT_DISABLED ((uint8_t) 0x00) /* - This function has not asserted its interrupt. */ 359 #define MMA865x_TRIG_CFG_TRIG_PULSE_EN ((uint8_t) 0x08) /* - This function can trigger the FIFO at its (the */ 360 /* function�s) interrupt. */ 361 #define MMA865x_TRIG_CFG_TRIG_PULSE_DISABLED ((uint8_t) 0x00) /* - This function has not asserted its interrupt. */ 362 #define MMA865x_TRIG_CFG_TRIG_FF_MT_EN ((uint8_t) 0x04) /* - This function can trigger the FIFO at its (the */ 363 /* function�s) interrupt. */ 364 #define MMA865x_TRIG_CFG_TRIG_FF_MT_DISABLED ((uint8_t) 0x00) /* - This function has not asserted its interrupt. */ 365 /*------------------------------*/ 366 367 368 369 370 /*-------------------------------- 371 ** Register: SYSMOD 372 ** Enum: MMA865x_SYSMOD 373 ** -- 374 ** Offset : 0x0B - System Mode register (Read-Only) 375 ** ------------------------------*/ 376 typedef union { 377 struct { 378 uint8_t sysmod : 2; /* - System mode data bits 0-1. */ 379 380 uint8_t fgt : 5; /* - Number of ODR time units since FGERR was asserted. */ 381 382 uint8_t fgerr : 1; /* - FIFO Gate Error. */ 383 384 } b; 385 uint8_t w; 386 } MMA865x_SYSMOD_t; 387 388 389 /* 390 ** SYSMOD - Bit field mask definitions 391 */ 392 #define MMA865x_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03) 393 #define MMA865x_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0) 394 395 #define MMA865x_SYSMOD_FGT_MASK ((uint8_t) 0x7C) 396 #define MMA865x_SYSMOD_FGT_SHIFT ((uint8_t) 2) 397 398 #define MMA865x_SYSMOD_FGERR_MASK ((uint8_t) 0x80) 399 #define MMA865x_SYSMOD_FGERR_SHIFT ((uint8_t) 7) 400 401 402 /* 403 ** SYSMOD - Bit field value definitions 404 */ 405 #define MMA865x_SYSMOD_FGERR_NONE ((uint8_t) 0x00) /* - No FIFO Gate Error detected. */ 406 #define MMA865x_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* - FIFO Gate Error was detected. */ 407 #define MMA865x_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* - STANDBY Mode. */ 408 #define MMA865x_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* - WAKE Mode. */ 409 #define MMA865x_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* - SLEEP Mode. */ 410 /*------------------------------*/ 411 412 413 414 415 /*-------------------------------- 416 ** Register: INT_SOURCE 417 ** Enum: MMA865x_INT_SOURCE 418 ** -- 419 ** Offset : 0x0C - Interrupt source status 420 ** ------------------------------*/ 421 typedef union { 422 struct { 423 uint8_t src_drdy : 1; /* - Data Ready Interrupt bit status bit */ 424 425 uint8_t _reserved_ : 1; 426 uint8_t src_ff_mt : 1; /* - Freefall/Motion interrupt status bit */ 427 428 uint8_t src_pulse : 1; /* - Pulse interrupt status bit */ 429 430 uint8_t src_lndprt : 1; /* - Landscape/Portrait Orientation interrupt status bit. */ 431 432 uint8_t src_trans : 1; /* - Transient interrupt status bit. */ 433 434 uint8_t src_fifo : 1; /* - FIFO interrupt status bit. */ 435 436 uint8_t src_aslp : 1; /* - Auto-SLEEP/WAKE interrupt status bit. */ 437 438 } b; 439 uint8_t w; 440 } MMA865x_INT_SOURCE_t; 441 442 443 /* 444 ** INT_SOURCE - Bit field mask definitions 445 */ 446 #define MMA865x_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01) 447 #define MMA865x_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0) 448 449 #define MMA865x_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04) 450 #define MMA865x_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2) 451 452 #define MMA865x_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08) 453 #define MMA865x_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3) 454 455 #define MMA865x_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10) 456 #define MMA865x_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4) 457 458 #define MMA865x_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20) 459 #define MMA865x_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5) 460 461 #define MMA865x_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40) 462 #define MMA865x_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6) 463 464 #define MMA865x_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80) 465 #define MMA865x_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7) 466 467 468 /* 469 ** INT_SOURCE - Bit field value definitions 470 */ 471 #define MMA865x_INT_SOURCE_SRC_ASLP_READY ((uint8_t) 0x80) /* - An interrupt event that can cause a */ 472 /* WAKE-to-SLEEP or SLEEP-to-WAKE system mode */ 473 /* transition has occurred. */ 474 #define MMA865x_INT_SOURCE_SRC_ASLP_INACTIVE ((uint8_t) 0x00) /* - No WAKE-to-SLEEP or SLEEP-to-WAKE system mode */ 475 /* transition interrupt event has occurred. */ 476 #define MMA865x_INT_SOURCE_SRC_FIFO_READY ((uint8_t) 0x40) /* - A FIFO interrupt event (such as an overflow */ 477 /* event or watermark) has occurred. */ 478 #define MMA865x_INT_SOURCE_SRC_FIFO_INACTIVE ((uint8_t) 0x00) /* - No FIFO interrupt event has occurred. */ 479 #define MMA865x_INT_SOURCE_SRC_TRANS_READY ((uint8_t) 0x20) /* - An acceleration transient value greater than */ 480 /* user-specified threshold has occurred. */ 481 #define MMA865x_INT_SOURCE_SRC_TRANS_INACTIVE ((uint8_t) 0x00) /* - No transient event has occurred. */ 482 #define MMA865x_INT_SOURCE_SRC_LNDPRT_READY ((uint8_t) 0x10) /* - An interrupt was generated due to a change in */ 483 /* the device orientation status. */ 484 #define MMA865x_INT_SOURCE_SRC_LNDPRT_INACTIVE ((uint8_t) 0x00) /* - No change in orientation status was detected. */ 485 #define MMA865x_INT_SOURCE_SRC_PULSE_READY ((uint8_t) 0x08) /* - An interrupt was generated due to single and/or */ 486 /* double pulse event. */ 487 #define MMA865x_INT_SOURCE_SRC_PULSE_INACTIVE ((uint8_t) 0x00) /* - No pulse event was detected. */ 488 #define MMA865x_INT_SOURCE_SRC_FF_MT_READY ((uint8_t) 0x04) /* - The Freefall/Motion function interrupt is */ 489 /* active. */ 490 #define MMA865x_INT_SOURCE_SRC_FF_MT_INACTIVE ((uint8_t) 0x00) /* - No Freefall or Motion event was detected. */ 491 #define MMA865x_INT_SOURCE_SRC_DRDY_READY ((uint8_t) 0x01) /* - The X, Y, Z data ready interrupt is active. */ 492 #define MMA865x_INT_SOURCE_SRC_DRDY_INACTIVE ((uint8_t) 0x00) /* - The X, Y, Z interrupt is not active. */ 493 /*------------------------------*/ 494 495 496 497 498 /*-------------------------------- 499 ** Register: WHO_AM_I 500 ** Enum: MMA865x_WHO_AM_I 501 ** -- 502 ** Offset : 0x0D - Device identification register containing Fixed Device ID Number 503 ** ------------------------------*/ 504 typedef uint8_t MMA865x_WHO_AM_I_t; 505 506 507 508 509 /*-------------------------------- 510 ** Register: XYZ_DATA_CFG 511 ** Enum: MMA865x_XYZ_DATA_CFG 512 ** -- 513 ** Offset : 0x0E - Sets the dynamic range and sets the high-pass filter for the output data 514 ** ------------------------------*/ 515 typedef union { 516 struct { 517 uint8_t fs : 2; /* - Full-scale range selection. */ 518 519 uint8_t _reserved_ : 2; 520 uint8_t hpf_out : 1; /* - Enable high-pass output data. */ 521 522 } b; 523 uint8_t w; 524 } MMA865x_XYZ_DATA_CFG_t; 525 526 527 /* 528 ** XYZ_DATA_CFG - Bit field mask definitions 529 */ 530 #define MMA865x_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03) 531 #define MMA865x_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0) 532 533 #define MMA865x_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10) 534 #define MMA865x_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4) 535 536 537 /* 538 ** XYZ_DATA_CFG - Bit field value definitions 539 */ 540 #define MMA865x_XYZ_DATA_CFG_HPF_OUT_ENABLE ((uint8_t) 0x10) /* - Output data is high-pass filtered. */ 541 #define MMA865x_XYZ_DATA_CFG_HPF_OUT_DISABLE ((uint8_t) 0x00) /* - Output data is not high-pass filtered. */ 542 #define MMA865x_XYZ_DATA_CFG_FS_2G ((uint8_t) 0x00) /* - �2 g. */ 543 #define MMA865x_XYZ_DATA_CFG_FS_4G ((uint8_t) 0x01) /* - �4 g. */ 544 #define MMA865x_XYZ_DATA_CFG_FS_8G ((uint8_t) 0x02) /* - �8 g. */ 545 /*------------------------------*/ 546 547 548 549 550 /*-------------------------------- 551 ** Register: HP_FILTER_CUTOFF 552 ** Enum: MMA865x_HP_FILTER_CUTOFF 553 ** -- 554 ** Offset : 0x0F - High-Pass Filter register 555 ** ------------------------------*/ 556 typedef union { 557 struct { 558 uint8_t sel : 2; /* - HPF cutoff frequency selection. This value depends on the OSR and ODR */ 559 /* (refer to Table 33 of data sheet for more details). */ 560 561 uint8_t _reserved_ : 2; 562 uint8_t pulse_lpf_en : 1; /* - Enable Low-Pass Filter (LPF) for pulse processing function. */ 563 564 uint8_t pulse_hpf_byp : 1; /* - Bypass High-Pass Filter (HPF) for pulse processing function. */ 565 566 } b; 567 uint8_t w; 568 } MMA865x_HP_FILTER_CUTOFF_t; 569 570 571 /* 572 ** HP_FILTER_CUTOFF - Bit field mask definitions 573 */ 574 #define MMA865x_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03) 575 #define MMA865x_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0) 576 577 #define MMA865x_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10) 578 #define MMA865x_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4) 579 580 #define MMA865x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20) 581 #define MMA865x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5) 582 583 584 /* 585 ** HP_FILTER_CUTOFF - Bit field value definitions 586 */ 587 #define MMA865x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x00) /* - HPF is enabled for pulse processing. */ 588 #define MMA865x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_BYPASSED ((uint8_t) 0x20) /* - HPF is bypassed for pulse processing. */ 589 #define MMA865x_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* - LPF is disabled for pulse processing. */ 590 #define MMA865x_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* - LPF is enabled for pulse processing. */ 591 #define MMA865x_HP_FILTER_CUTOFF_SEL_VAL_0 ((uint8_t) 0x00) /* - Select 0 0 */ 592 #define MMA865x_HP_FILTER_CUTOFF_SEL_VAL_1 ((uint8_t) 0x00) /* - Select 0 1 */ 593 #define MMA865x_HP_FILTER_CUTOFF_SEL_VAL_2 ((uint8_t) 0x00) /* - Select 1 0 */ 594 #define MMA865x_HP_FILTER_CUTOFF_SEL_VAL_3 ((uint8_t) 0x00) /* - Select 1 1 */ 595 /*------------------------------*/ 596 597 598 599 600 /*-------------------------------- 601 ** Register: PL_STATUS 602 ** Enum: MMA865x_PL_STATUS 603 ** -- 604 ** Offset : 0x10 - Portrait/Landscape Status register 605 ** ------------------------------*/ 606 typedef union { 607 struct { 608 uint8_t bafro : 1; /* - Back or Front orientation. */ 609 610 uint8_t lapo : 2; /* - Landscape/Portrait orientation. */ 611 612 uint8_t _reserved_ : 3; 613 uint8_t lo : 1; /* - Z-Tilt Angle Lockout. */ 614 615 uint8_t newlp : 1; /* - Landscape/Portrait status change flag. */ 616 617 } b; 618 uint8_t w; 619 } MMA865x_PL_STATUS_t; 620 621 622 /* 623 ** PL_STATUS - Bit field mask definitions 624 */ 625 #define MMA865x_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01) 626 #define MMA865x_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0) 627 628 #define MMA865x_PL_STATUS_LAPO_MASK ((uint8_t) 0x06) 629 #define MMA865x_PL_STATUS_LAPO_SHIFT ((uint8_t) 1) 630 631 #define MMA865x_PL_STATUS_LO_MASK ((uint8_t) 0x40) 632 #define MMA865x_PL_STATUS_LO_SHIFT ((uint8_t) 6) 633 634 #define MMA865x_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80) 635 #define MMA865x_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7) 636 637 638 /* 639 ** PL_STATUS - Bit field value definitions 640 */ 641 #define MMA865x_PL_STATUS_NEWLP_NO_CHANGE ((uint8_t) 0x00) /* - No change. */ 642 #define MMA865x_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* - BAFRO and/or LAPO and/or Z-Tilt lockout value has */ 643 /* changed. */ 644 #define MMA865x_PL_STATUS_LO_NOT_DETECTED ((uint8_t) 0x00) /* - Lockout condition has not been detected. */ 645 #define MMA865x_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* - Z-Tilt lockout trip angle has been exceeded. */ 646 /* Lockout has been detected. */ 647 #define MMA865x_PL_STATUS_LAPO_PORTRAIT_UP ((uint8_t) 0x00) /* - Portrait Up: Equipment standing vertically in the */ 648 /* normal orientation. */ 649 #define MMA865x_PL_STATUS_LAPO_PORTRAIT_DOWN ((uint8_t) 0x02) /* - Portrait Down: Equipment standing vertically in */ 650 /* the inverted orientation. */ 651 #define MMA865x_PL_STATUS_LAPO_LANDSCAPE_UP ((uint8_t) 0x04) /* - Landscape Right: Equipment is in landscape mode */ 652 /* to the right. */ 653 #define MMA865x_PL_STATUS_LAPO_LANDSCAPE_DOWN ((uint8_t) 0x06) /* - Landscape Left: Equipment is in landscape mode to */ 654 /* the left. */ 655 #define MMA865x_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* - Front: Equipment is in the front-facing */ 656 /* orientation. */ 657 #define MMA865x_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* - Back: Equipment is in the back-facing */ 658 /* orientation. */ 659 /*------------------------------*/ 660 661 662 663 664 /*-------------------------------- 665 ** Register: PL_CFG 666 ** Enum: MMA865x_PL_CFG 667 ** -- 668 ** Offset : 0x11 - Portrait/Landscape Configuration register 669 ** ------------------------------*/ 670 typedef union { 671 struct { 672 uint8_t _reserved_ : 6; 673 uint8_t pl_en : 1; /* - Portrait/Landscape detection enable. */ 674 675 uint8_t dbcntm : 1; /* - Debounce counter mode selection. */ 676 677 } b; 678 uint8_t w; 679 } MMA865x_PL_CFG_t; 680 681 682 /* 683 ** PL_CFG - Bit field mask definitions 684 */ 685 #define MMA865x_PL_CFG_PL_EN_MASK ((uint8_t) 0x40) 686 #define MMA865x_PL_CFG_PL_EN_SHIFT ((uint8_t) 6) 687 688 #define MMA865x_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80) 689 #define MMA865x_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7) 690 691 692 /* 693 ** PL_CFG - Bit field value definitions 694 */ 695 #define MMA865x_PL_CFG_DBCNTM_DECREMENT ((uint8_t) 0x00) /* - Decrements debounce whenever the condition of */ 696 /* interest is no longer valid. */ 697 #define MMA865x_PL_CFG_DBCNTM_CLEAR ((uint8_t) 0x80) /* - Clears the counter whenever the condition of */ 698 /* interest is no longer valid. */ 699 #define MMA865x_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* - Portrait/Landscape Detection is disabled. */ 700 #define MMA865x_PL_CFG_PL_EN_EN ((uint8_t) 0x40) /* - Portrait/Landscape Detection is enabled. */ 701 /*------------------------------*/ 702 703 704 705 706 /*-------------------------------- 707 ** Register: PL_COUNT 708 ** Enum: MMA865x_PL_COUNT 709 ** -- 710 ** Offset : 0x12 - Portrait/Landscape Debounce register 711 ** ------------------------------*/ 712 typedef uint8_t MMA865x_PL_COUNT_t; 713 714 715 716 717 /*-------------------------------- 718 ** Register: PL_BF_ZCOMP 719 ** Enum: MMA865x_PL_BF_ZCOMP 720 ** -- 721 ** Offset : 0x13 - Back/Front and Z Compensation register 722 ** ------------------------------*/ 723 typedef union { 724 struct { 725 uint8_t zlock : 3; /* - Z-lock angle threshold (Step size is 4 and Range is from 14 to 43). */ 726 727 uint8_t _reserved_ : 3; 728 uint8_t bkfr : 2; /* - Back/Front trip angle threshold (Step size = 5 and Range = (65 to 80)). */ 729 730 } b; 731 uint8_t w; 732 } MMA865x_PL_BF_ZCOMP_t; 733 734 735 /* 736 ** PL_BF_ZCOMP - Bit field mask definitions 737 */ 738 #define MMA865x_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07) 739 #define MMA865x_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0) 740 741 #define MMA865x_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0) 742 #define MMA865x_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6) 743 744 745 /* 746 ** PL_BF_ZCOMP - Bit field value definitions 747 */ 748 #define MMA865x_PL_BF_ZCOMP_BKFR_VAL_0 ((uint8_t) 0x00) /* - Back/Front Transition : 00 Z < 80� or Z > 280� */ 749 /* and Front/Back Transition : Z > 100� and Z < 260�. */ 750 #define MMA865x_PL_BF_ZCOMP_BKFR_VAL_1 ((uint8_t) 0x40) /* - Back/Front Transition : 01 Z < 75� or Z > 285� */ 751 /* and Front/Back Transition : Z > 105� and Z < 255�. */ 752 #define MMA865x_PL_BF_ZCOMP_BKFR_VAL_2 ((uint8_t) 0x80) /* - Back/Front Transition : 10 Z < 70� or Z > 290� */ 753 /* and Front/Back Transition : Z > 110� and Z < 250�. */ 754 #define MMA865x_PL_BF_ZCOMP_BKFR_VAL_3 ((uint8_t) 0xc0) /* - Back/Front Transition : 11 Z < 65� or Z > 295� */ 755 /* and Front/Back Transition : Z > 115� and Z < 245�. */ 756 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_14 ((uint8_t) 0x00) /* - Threshold Angle = 14�. */ 757 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_18 ((uint8_t) 0x01) /* - Threshold Angle = 18�. */ 758 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_21 ((uint8_t) 0x02) /* - Threshold Angle = 21�. */ 759 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_25 ((uint8_t) 0x03) /* - Threshold Angle = 25�. */ 760 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_29 ((uint8_t) 0x04) /* - Threshold Angle = 29�. */ 761 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_33 ((uint8_t) 0x05) /* - Threshold Angle = 33�. */ 762 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_37 ((uint8_t) 0x06) /* - Threshold Angle = 37�. */ 763 #define MMA865x_PL_BF_ZCOMP_ZLOCK_VAL_42 ((uint8_t) 0x07) /* - Threshold Angle = 42�. */ 764 /*------------------------------*/ 765 766 767 768 769 /*-------------------------------- 770 ** Register: P_L_THS_REG 771 ** Enum: MMA865x_P_L_THS_REG 772 ** -- 773 ** Offset : 0x14 - Portrait/Landscape Threshold and Hysteresis register 774 ** ------------------------------*/ 775 typedef union { 776 struct { 777 uint8_t hys : 3; /* - Hysteresis value : This angle is added to the threshold angle, for a */ 778 /* smoother transition from portrait to landscape and landscape to portrait. */ 779 /* This angle ranges from 0 to 24. */ 780 781 uint8_t p_l_ths : 5; /* - Portrait/Landscape trip threshold angle (from 15 to 75). */ 782 783 } b; 784 uint8_t w; 785 } MMA865x_P_L_THS_REG_t; 786 787 788 /* 789 ** P_L_THS_REG - Bit field mask definitions 790 */ 791 #define MMA865x_P_L_THS_REG_HYS_MASK ((uint8_t) 0x07) 792 #define MMA865x_P_L_THS_REG_HYS_SHIFT ((uint8_t) 0) 793 794 #define MMA865x_P_L_THS_REG_P_L_THS_MASK ((uint8_t) 0xF8) 795 #define MMA865x_P_L_THS_REG_P_L_THS_SHIFT ((uint8_t) 3) 796 797 798 /* 799 ** P_L_THS_REG - Bit field value definitions 800 */ 801 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_15 ((uint8_t) 0x38) /* - Threshold Angle = 15� */ 802 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_20 ((uint8_t) 0x48) /* - Threshold Angle = 20� */ 803 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_30 ((uint8_t) 0x60) /* - Threshold Angle = 30� */ 804 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_35 ((uint8_t) 0x68) /* - Threshold Angle = 35� */ 805 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_40 ((uint8_t) 0x78) /* - Threshold Angle = 40� */ 806 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_45 ((uint8_t) 0x80) /* - Threshold Angle = 45� */ 807 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_55 ((uint8_t) 0x98) /* - Threshold Angle = 55� */ 808 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_60 ((uint8_t) 0xa0) /* - Threshold Angle = 60� */ 809 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_70 ((uint8_t) 0xb8) /* - Threshold Angle = 70� */ 810 #define MMA865x_P_L_THS_REG_P_L_THS_VAL_75 ((uint8_t) 0xc8) /* - Threshold Angle = 75� */ 811 #define MMA865x_P_L_THS_REG_HYS_VAL_0 ((uint8_t) 0x00) /* - Hysteresis � Angle Range = �0 */ 812 #define MMA865x_P_L_THS_REG_HYS_VAL_1 ((uint8_t) 0x01) /* - Hysteresis � Angle Range = �4 */ 813 #define MMA865x_P_L_THS_REG_HYS_VAL_2 ((uint8_t) 0x02) /* - Hysteresis � Angle Range = �7 */ 814 #define MMA865x_P_L_THS_REG_HYS_VAL_3 ((uint8_t) 0x03) /* - Hysteresis � Angle Range = �11 */ 815 #define MMA865x_P_L_THS_REG_HYS_VAL_4 ((uint8_t) 0x04) /* - Hysteresis � Angle Range = �14 */ 816 #define MMA865x_P_L_THS_REG_HYS_VAL_5 ((uint8_t) 0x05) /* - Hysteresis � Angle Range = �17 */ 817 #define MMA865x_P_L_THS_REG_HYS_VAL_6 ((uint8_t) 0x06) /* - Hysteresis � Angle Range = �21 */ 818 #define MMA865x_P_L_THS_REG_HYS_VAL_7 ((uint8_t) 0x07) /* - Hysteresis � Angle Range = �24 */ 819 /*------------------------------*/ 820 821 822 823 824 /*-------------------------------- 825 ** Register: FF_MT_CFG 826 ** Enum: MMA865x_FF_MT_CFG 827 ** -- 828 ** Offset : 0x15 - Freefall/Motion Configuration register 829 ** ------------------------------*/ 830 typedef union { 831 struct { 832 uint8_t _reserved_ : 3; 833 uint8_t xefe : 1; /* - Event flag enable on X event. */ 834 835 uint8_t yefe : 1; /* - Event flag enable on Y event. */ 836 837 uint8_t zefe : 1; /* - Event flag enable on Z. */ 838 839 uint8_t oae : 1; /* - Motion detect / Freefall detect flag selection. */ 840 841 uint8_t ele : 1; /* - Event Latch Enable: Event flags are latched into FF_MT_SRC register. */ 842 843 } b; 844 uint8_t w; 845 } MMA865x_FF_MT_CFG_t; 846 847 848 /* 849 ** FF_MT_CFG - Bit field mask definitions 850 */ 851 #define MMA865x_FF_MT_CFG_XEFE_MASK ((uint8_t) 0x08) 852 #define MMA865x_FF_MT_CFG_XEFE_SHIFT ((uint8_t) 3) 853 854 #define MMA865x_FF_MT_CFG_YEFE_MASK ((uint8_t) 0x10) 855 #define MMA865x_FF_MT_CFG_YEFE_SHIFT ((uint8_t) 4) 856 857 #define MMA865x_FF_MT_CFG_ZEFE_MASK ((uint8_t) 0x20) 858 #define MMA865x_FF_MT_CFG_ZEFE_SHIFT ((uint8_t) 5) 859 860 #define MMA865x_FF_MT_CFG_OAE_MASK ((uint8_t) 0x40) 861 #define MMA865x_FF_MT_CFG_OAE_SHIFT ((uint8_t) 6) 862 863 #define MMA865x_FF_MT_CFG_ELE_MASK ((uint8_t) 0x80) 864 #define MMA865x_FF_MT_CFG_ELE_SHIFT ((uint8_t) 7) 865 866 867 /* 868 ** FF_MT_CFG - Bit field value definitions 869 */ 870 #define MMA865x_FF_MT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* - Event flag latch disabled. */ 871 #define MMA865x_FF_MT_CFG_ELE_EN ((uint8_t) 0x80) /* - Event flag latch enabled. */ 872 #define MMA865x_FF_MT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* - Freefall flag (Logical AND combination). */ 873 #define MMA865x_FF_MT_CFG_OAE_MOTION ((uint8_t) 0x40) /* - Motion flag (Logical OR combination). */ 874 #define MMA865x_FF_MT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 875 #define MMA865x_FF_MT_CFG_ZEFE_EN ((uint8_t) 0x20) /* - Raise event flag on measured acceleration value */ 876 /* beyond preset threshold. */ 877 #define MMA865x_FF_MT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 878 #define MMA865x_FF_MT_CFG_YEFE_EN ((uint8_t) 0x10) /* - Raise event flag on measured acceleration value */ 879 /* beyond preset threshold. */ 880 #define MMA865x_FF_MT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 881 #define MMA865x_FF_MT_CFG_XEFE_EN ((uint8_t) 0x08) /* - Raise event flag on measured acceleration value */ 882 /* beyond preset threshold. */ 883 /*------------------------------*/ 884 885 886 887 888 /*-------------------------------- 889 ** Register: FF_MT_SRC 890 ** Enum: MMA865x_FF_MT_SRC 891 ** -- 892 ** Offset : 0x16 - Freefall/Motion Source register 893 ** ------------------------------*/ 894 typedef union { 895 struct { 896 uint8_t xhp : 1; /* - X-Motion Polarity Flag. */ 897 898 uint8_t xhe : 1; /* - X-Motion Flag. */ 899 900 uint8_t yhp : 1; /* - Y-Motion Polarity Flag. */ 901 902 uint8_t yhe : 1; /* - Y-Motion Flag. */ 903 904 uint8_t zhp : 1; /* - Z-Motion Polarity Flag. */ 905 906 uint8_t zhe : 1; /* - Z-Motion flag. */ 907 908 uint8_t _reserved_ : 1; 909 uint8_t ea : 1; /* - Event Active flag. */ 910 911 } b; 912 uint8_t w; 913 } MMA865x_FF_MT_SRC_t; 914 915 916 /* 917 ** FF_MT_SRC - Bit field mask definitions 918 */ 919 #define MMA865x_FF_MT_SRC_XHP_MASK ((uint8_t) 0x01) 920 #define MMA865x_FF_MT_SRC_XHP_SHIFT ((uint8_t) 0) 921 922 #define MMA865x_FF_MT_SRC_XHE_MASK ((uint8_t) 0x02) 923 #define MMA865x_FF_MT_SRC_XHE_SHIFT ((uint8_t) 1) 924 925 #define MMA865x_FF_MT_SRC_YHP_MASK ((uint8_t) 0x04) 926 #define MMA865x_FF_MT_SRC_YHP_SHIFT ((uint8_t) 2) 927 928 #define MMA865x_FF_MT_SRC_YHE_MASK ((uint8_t) 0x08) 929 #define MMA865x_FF_MT_SRC_YHE_SHIFT ((uint8_t) 3) 930 931 #define MMA865x_FF_MT_SRC_ZHP_MASK ((uint8_t) 0x10) 932 #define MMA865x_FF_MT_SRC_ZHP_SHIFT ((uint8_t) 4) 933 934 #define MMA865x_FF_MT_SRC_ZHE_MASK ((uint8_t) 0x20) 935 #define MMA865x_FF_MT_SRC_ZHE_SHIFT ((uint8_t) 5) 936 937 #define MMA865x_FF_MT_SRC_EA_MASK ((uint8_t) 0x80) 938 #define MMA865x_FF_MT_SRC_EA_SHIFT ((uint8_t) 7) 939 940 941 /* 942 ** FF_MT_SRC - Bit field value definitions 943 */ 944 #define MMA865x_FF_MT_SRC_EA_NONE ((uint8_t) 0x00) /* - No event flag has been asserted. */ 945 #define MMA865x_FF_MT_SRC_EA_DETECTED ((uint8_t) 0x80) /* - One or more event flags has been asserted. */ 946 #define MMA865x_FF_MT_SRC_ZHE_NONE ((uint8_t) 0x00) /* - No Z motion event detected. */ 947 #define MMA865x_FF_MT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* - Z motion has been detected. */ 948 #define MMA865x_FF_MT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* - Z event was positive g. */ 949 #define MMA865x_FF_MT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* - Z event was negative g. */ 950 #define MMA865x_FF_MT_SRC_YHE_NONE ((uint8_t) 0x00) /* - No Y motion event detected. */ 951 #define MMA865x_FF_MT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* - Y motion has been detected. */ 952 #define MMA865x_FF_MT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* - Y event detected was positive g. */ 953 #define MMA865x_FF_MT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* - Y event was negative g. */ 954 #define MMA865x_FF_MT_SRC_XHE_NONE ((uint8_t) 0x00) /* - No X motion event detected. */ 955 #define MMA865x_FF_MT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* - X motion has been detected. */ 956 #define MMA865x_FF_MT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* - X event was positive g. */ 957 #define MMA865x_FF_MT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* - X event was negative g. */ 958 /*------------------------------*/ 959 960 961 962 963 /*-------------------------------- 964 ** Register: FF_MT_THS 965 ** Enum: MMA865x_FF_MT_THS 966 ** -- 967 ** Offset : 0x17 - Freefall and Motion Threshold register 968 ** ------------------------------*/ 969 typedef union { 970 struct { 971 uint8_t ths : 7; /* - Freefall /Motion Threshold. */ 972 973 uint8_t dbcntm : 1; /* - Debounce counter mode selection. */ 974 975 } b; 976 uint8_t w; 977 } MMA865x_FF_MT_THS_t; 978 979 980 /* 981 ** FF_MT_THS - Bit field mask definitions 982 */ 983 #define MMA865x_FF_MT_THS_THS_MASK ((uint8_t) 0x7F) 984 #define MMA865x_FF_MT_THS_THS_SHIFT ((uint8_t) 0) 985 986 #define MMA865x_FF_MT_THS_DBCNTM_MASK ((uint8_t) 0x80) 987 #define MMA865x_FF_MT_THS_DBCNTM_SHIFT ((uint8_t) 7) 988 989 990 /* 991 ** FF_MT_THS - Bit field value definitions 992 */ 993 #define MMA865x_FF_MT_THS_DBCNTM_INC_DEC ((uint8_t) 0x00) /* - Increments or decrements debounce. */ 994 #define MMA865x_FF_MT_THS_DBCNTM_INC_CLR ((uint8_t) 0x80) /* - Increments or clears counter. */ 995 /*------------------------------*/ 996 997 998 999 1000 /*-------------------------------- 1001 ** Register: FF_MT_COUNT 1002 ** Enum: MMA865x_FF_MT_COUNT 1003 ** -- 1004 ** Offset : 0x18 - Debounce register 1005 ** ------------------------------*/ 1006 typedef uint8_t MMA865x_FF_MT_COUNT_t; 1007 1008 1009 1010 1011 /*-------------------------------- 1012 ** Register: TRANSIENT_CFG 1013 ** Enum: MMA865x_TRANSIENT_CFG 1014 ** -- 1015 ** Offset : 0x1D - Transient Configuration register 1016 ** ------------------------------*/ 1017 typedef union { 1018 struct { 1019 uint8_t hpf_byp : 1; /* - Bypass high-pass filter. */ 1020 1021 uint8_t xtefe : 1; /* - Event flag enable for X-transient acceleration greater than a transient */ 1022 /* threshold event. */ 1023 1024 uint8_t ytefe : 1; /* - Event flag enable for Y-transient acceleration greater than a transient */ 1025 /* threshold event. */ 1026 1027 uint8_t ztefe : 1; /* - Event flag enable for Z-transient acceleration greater than a transient */ 1028 /* threshold event. */ 1029 1030 uint8_t ele : 1; /* - Transient event flags are latched into the TRANSIENT_SRC register. */ 1031 1032 } b; 1033 uint8_t w; 1034 } MMA865x_TRANSIENT_CFG_t; 1035 1036 1037 /* 1038 ** TRANSIENT_CFG - Bit field mask definitions 1039 */ 1040 #define MMA865x_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01) 1041 #define MMA865x_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0) 1042 1043 #define MMA865x_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02) 1044 #define MMA865x_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1) 1045 1046 #define MMA865x_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04) 1047 #define MMA865x_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2) 1048 1049 #define MMA865x_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08) 1050 #define MMA865x_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3) 1051 1052 #define MMA865x_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10) 1053 #define MMA865x_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4) 1054 1055 1056 /* 1057 ** TRANSIENT_CFG - Bit field value definitions 1058 */ 1059 #define MMA865x_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* - Event flag latch disabled. */ 1060 #define MMA865x_TRANSIENT_CFG_ELE_EN ((uint8_t) 0x10) /* - Event flag latch enabled. */ 1061 #define MMA865x_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 1062 #define MMA865x_TRANSIENT_CFG_ZTEFE_EN ((uint8_t) 0x08) /* - Raise event flag on measured acceleration */ 1063 /* delta value that is greater than a transient */ 1064 /* threshold. */ 1065 #define MMA865x_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 1066 #define MMA865x_TRANSIENT_CFG_YTEFE_EN ((uint8_t) 0x04) /* - Raise event flag on measured acceleration */ 1067 /* delta value that is greater than a transient */ 1068 /* threshold. */ 1069 #define MMA865x_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* - Event detection disabled. */ 1070 #define MMA865x_TRANSIENT_CFG_XTEFE_EN ((uint8_t) 0x02) /* - Raise event flag on measured acceleration */ 1071 /* delta value that is greater than a transient */ 1072 /* threshold. */ 1073 #define MMA865x_TRANSIENT_CFG_HPF_BYP_THROUGH_HPF ((uint8_t) 0x00) /* - Data to transient acceleration detection */ 1074 /* block is through HPF. */ 1075 #define MMA865x_TRANSIENT_CFG_HPF_BYP_NOT_HPF ((uint8_t) 0x01) /* - Data to transient acceleration detection */ 1076 /* block is NOT Through HPF. */ 1077 /*------------------------------*/ 1078 1079 1080 1081 1082 /*-------------------------------- 1083 ** Register: TRANSIENT_SRC 1084 ** Enum: MMA865x_TRANSIENT_SRC 1085 ** -- 1086 ** Offset : 0x1E - Transient Source register 1087 ** ------------------------------*/ 1088 typedef union { 1089 struct { 1090 uint8_t x_trans_pol : 1; /* - Polarity of X-Transient Event that triggered the interrupt. */ 1091 1092 uint8_t xtranse : 1; /* - X-transient event. */ 1093 1094 uint8_t y_trans_pol : 1; /* - Polarity of Y-Transient Event that triggered the interrupt. */ 1095 1096 uint8_t ytranse : 1; /* - Y-transient event. */ 1097 1098 uint8_t z_trans_pol : 1; /* - Polarity of Z-Transient Event that triggered the interrupt. */ 1099 1100 uint8_t ztranse : 1; /* - Z-transient event. */ 1101 1102 uint8_t ea : 1; /* - Event Active Flag. */ 1103 1104 } b; 1105 uint8_t w; 1106 } MMA865x_TRANSIENT_SRC_t; 1107 1108 1109 /* 1110 ** TRANSIENT_SRC - Bit field mask definitions 1111 */ 1112 #define MMA865x_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01) 1113 #define MMA865x_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0) 1114 1115 #define MMA865x_TRANSIENT_SRC_XTRANSE_MASK ((uint8_t) 0x02) 1116 #define MMA865x_TRANSIENT_SRC_XTRANSE_SHIFT ((uint8_t) 1) 1117 1118 #define MMA865x_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04) 1119 #define MMA865x_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2) 1120 1121 #define MMA865x_TRANSIENT_SRC_YTRANSE_MASK ((uint8_t) 0x08) 1122 #define MMA865x_TRANSIENT_SRC_YTRANSE_SHIFT ((uint8_t) 3) 1123 1124 #define MMA865x_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10) 1125 #define MMA865x_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4) 1126 1127 #define MMA865x_TRANSIENT_SRC_ZTRANSE_MASK ((uint8_t) 0x20) 1128 #define MMA865x_TRANSIENT_SRC_ZTRANSE_SHIFT ((uint8_t) 5) 1129 1130 #define MMA865x_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40) 1131 #define MMA865x_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6) 1132 1133 1134 /* 1135 ** TRANSIENT_SRC - Bit field value definitions 1136 */ 1137 #define MMA865x_TRANSIENT_SRC_EA_NONE ((uint8_t) 0x00) /* - No event flag has been asserted. */ 1138 #define MMA865x_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* - One or more event flags has been asserted. */ 1139 #define MMA865x_TRANSIENT_SRC_ZTRANSE_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1140 #define MMA865x_TRANSIENT_SRC_ZTRANSE_DETECTED ((uint8_t) 0x20) /* - Z-transient acceleration greater than the */ 1141 /* value of TRANSIENT_THS event has occurred. */ 1142 #define MMA865x_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* - Z-event was positive g. */ 1143 #define MMA865x_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* - Z-event was negative g. */ 1144 #define MMA865x_TRANSIENT_SRC_YTRANSE_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1145 #define MMA865x_TRANSIENT_SRC_YTRANSE_DETECTED ((uint8_t) 0x08) /* - Y-transient acceleration greater than the */ 1146 /* value of TRANSIENT_THS event has occurred. */ 1147 #define MMA865x_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* - Y-event was Positive g. */ 1148 #define MMA865x_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* - Y-event was Negative g. */ 1149 #define MMA865x_TRANSIENT_SRC_XTRANSE_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1150 #define MMA865x_TRANSIENT_SRC_XTRANSE_DETECTED ((uint8_t) 0x02) /* - X-transient acceleration greater than the */ 1151 /* value of TRANSIENT_THS event has occurred. */ 1152 #define MMA865x_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* - X-event was Positive g. */ 1153 #define MMA865x_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* - X-event was Negative g. */ 1154 /*------------------------------*/ 1155 1156 1157 1158 1159 /*-------------------------------- 1160 ** Register: TRANSIENT_THS 1161 ** Enum: MMA865x_TRANSIENT_THS 1162 ** -- 1163 ** Offset : 0x1F - Transient threshold register 1164 ** ------------------------------*/ 1165 typedef union { 1166 struct { 1167 uint8_t ths : 7; /* - Transient Threshold (A 7-bit unsigned number, with 0.063 g/LSB. The */ 1168 /* maximum threshold is 8 g). */ 1169 1170 uint8_t dbcntm : 1; /* - Debounce counter mode selection. */ 1171 1172 } b; 1173 uint8_t w; 1174 } MMA865x_TRANSIENT_THS_t; 1175 1176 1177 /* 1178 ** TRANSIENT_THS - Bit field mask definitions 1179 */ 1180 #define MMA865x_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F) 1181 #define MMA865x_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0) 1182 1183 #define MMA865x_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80) 1184 #define MMA865x_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7) 1185 1186 1187 /* 1188 ** TRANSIENT_THS - Bit field value definitions 1189 */ 1190 #define MMA865x_TRANSIENT_THS_DBCNTM_INC_DEC ((uint8_t) 0x00) /* - Increments or decrements debounce. */ 1191 #define MMA865x_TRANSIENT_THS_DBCNTM_INC_CLR ((uint8_t) 0x80) /* - Increments or clears counter. */ 1192 /*------------------------------*/ 1193 1194 1195 1196 1197 /*-------------------------------- 1198 ** Register: TRANSIENT_COUNT 1199 ** Enum: MMA865x_TRANSIENT_COUNT 1200 ** -- 1201 ** Offset : 0x20 - Transient count register 1202 ** ------------------------------*/ 1203 typedef uint8_t MMA865x_TRANSIENT_COUNT_t; 1204 1205 1206 1207 1208 /*-------------------------------- 1209 ** Register: PULSE_CFG 1210 ** Enum: MMA865x_PULSE_CFG 1211 ** -- 1212 ** Offset : 0x21 - Pulse configuration register 1213 ** ------------------------------*/ 1214 typedef union { 1215 struct { 1216 uint8_t xspefe : 1; /* - Event flag enable for a single pulse event on X-axis. */ 1217 1218 uint8_t xdpefe : 1; /* - Event flag enable for a double pulse event on X-axis. */ 1219 1220 uint8_t yspefe : 1; /* - Event flag enable for a single pulse event on Y-axis. */ 1221 1222 uint8_t ydpefe : 1; /* - Event flag enable for a double pulse event on Y-axis. */ 1223 1224 uint8_t zspefe : 1; /* - Event flag enable for a single pulse event on Z-axis. */ 1225 1226 uint8_t zdpefe : 1; /* - Event flag enable for a double pulse event on Z-axis. */ 1227 1228 uint8_t ele : 1; /* - Pulse event flags are latched into the PULSE_SRC register. */ 1229 1230 uint8_t dpa : 1; /* - Double Pulse Abort. */ 1231 1232 } b; 1233 uint8_t w; 1234 } MMA865x_PULSE_CFG_t; 1235 1236 1237 /* 1238 ** PULSE_CFG - Bit field mask definitions 1239 */ 1240 #define MMA865x_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01) 1241 #define MMA865x_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0) 1242 1243 #define MMA865x_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02) 1244 #define MMA865x_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1) 1245 1246 #define MMA865x_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04) 1247 #define MMA865x_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2) 1248 1249 #define MMA865x_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08) 1250 #define MMA865x_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3) 1251 1252 #define MMA865x_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10) 1253 #define MMA865x_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4) 1254 1255 #define MMA865x_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20) 1256 #define MMA865x_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5) 1257 1258 #define MMA865x_PULSE_CFG_ELE_MASK ((uint8_t) 0x40) 1259 #define MMA865x_PULSE_CFG_ELE_SHIFT ((uint8_t) 6) 1260 1261 #define MMA865x_PULSE_CFG_DPA_MASK ((uint8_t) 0x80) 1262 #define MMA865x_PULSE_CFG_DPA_SHIFT ((uint8_t) 7) 1263 1264 1265 /* 1266 ** PULSE_CFG - Bit field value definitions 1267 */ 1268 #define MMA865x_PULSE_CFG_DPA_NOT_ABORTED ((uint8_t) 0x00) /* - Double Pulse detection is not aborted if the */ 1269 /* start of a pulse is detected during the time period */ 1270 /* specified by the PULSE_LTCY register. */ 1271 #define MMA865x_PULSE_CFG_DPA_SUSPENDED ((uint8_t) 0x80) /* - Setting the DPA bit momentarily suspends the */ 1272 /* double tap detection if the start of a pulse is */ 1273 /* detected during the time period specified by the */ 1274 /* PULSE_LTCY register, and the pulse ends before the */ 1275 /* end of the time period specified by the PULSE_LTCY */ 1276 /* register. */ 1277 #define MMA865x_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1278 #define MMA865x_PULSE_CFG_ELE_EN ((uint8_t) 0x40) /* - Event detection is enabled. */ 1279 #define MMA865x_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1280 #define MMA865x_PULSE_CFG_ZDPEFE_EN ((uint8_t) 0x20) /* - Event detection is enabled. */ 1281 #define MMA865x_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1282 #define MMA865x_PULSE_CFG_ZSPEFE_EN ((uint8_t) 0x10) /* - Event detection is enabled. */ 1283 #define MMA865x_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1284 #define MMA865x_PULSE_CFG_YDPEFE_EN ((uint8_t) 0x08) /* - Event detection is enabled. */ 1285 #define MMA865x_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1286 #define MMA865x_PULSE_CFG_YSPEFE_EN ((uint8_t) 0x04) /* - Event detection is enabled. */ 1287 #define MMA865x_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1288 #define MMA865x_PULSE_CFG_XDPEFE_EN ((uint8_t) 0x02) /* - Event detection is enabled. */ 1289 #define MMA865x_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* - Event detection is disabled. */ 1290 #define MMA865x_PULSE_CFG_XSPEFE_EN ((uint8_t) 0x01) /* - Event detection is enabled. */ 1291 /*------------------------------*/ 1292 1293 1294 1295 1296 /*-------------------------------- 1297 ** Register: PULSE_SRC 1298 ** Enum: MMA865x_PULSE_SRC 1299 ** -- 1300 ** Offset : 0x22 - Pulse source register 1301 ** ------------------------------*/ 1302 typedef union { 1303 struct { 1304 uint8_t pol_x : 1; /* - Pulse polarity of X-axis event. */ 1305 1306 uint8_t pol_y : 1; /* - Pulse polarity of Y-axis event. */ 1307 1308 uint8_t pol_z : 1; /* - Pulse polarity of Z-axis event. */ 1309 1310 uint8_t dpe : 1; /* - Double pulse on first event. */ 1311 1312 uint8_t axx : 1; /* - X-axis event. */ 1313 1314 uint8_t axy : 1; /* - Y-axis event. */ 1315 1316 uint8_t axz : 1; /* - Z-axis event. */ 1317 1318 uint8_t ea : 1; /* - Event Active Flag. */ 1319 1320 } b; 1321 uint8_t w; 1322 } MMA865x_PULSE_SRC_t; 1323 1324 1325 /* 1326 ** PULSE_SRC - Bit field mask definitions 1327 */ 1328 #define MMA865x_PULSE_SRC_POL_X_MASK ((uint8_t) 0x01) 1329 #define MMA865x_PULSE_SRC_POL_X_SHIFT ((uint8_t) 0) 1330 1331 #define MMA865x_PULSE_SRC_POL_Y_MASK ((uint8_t) 0x02) 1332 #define MMA865x_PULSE_SRC_POL_Y_SHIFT ((uint8_t) 1) 1333 1334 #define MMA865x_PULSE_SRC_POL_Z_MASK ((uint8_t) 0x04) 1335 #define MMA865x_PULSE_SRC_POL_Z_SHIFT ((uint8_t) 2) 1336 1337 #define MMA865x_PULSE_SRC_DPE_MASK ((uint8_t) 0x08) 1338 #define MMA865x_PULSE_SRC_DPE_SHIFT ((uint8_t) 3) 1339 1340 #define MMA865x_PULSE_SRC_AXX_MASK ((uint8_t) 0x10) 1341 #define MMA865x_PULSE_SRC_AXX_SHIFT ((uint8_t) 4) 1342 1343 #define MMA865x_PULSE_SRC_AXY_MASK ((uint8_t) 0x20) 1344 #define MMA865x_PULSE_SRC_AXY_SHIFT ((uint8_t) 5) 1345 1346 #define MMA865x_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40) 1347 #define MMA865x_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6) 1348 1349 #define MMA865x_PULSE_SRC_EA_MASK ((uint8_t) 0x80) 1350 #define MMA865x_PULSE_SRC_EA_SHIFT ((uint8_t) 7) 1351 1352 1353 /* 1354 ** PULSE_SRC - Bit field value definitions 1355 */ 1356 #define MMA865x_PULSE_SRC_EA_NONE ((uint8_t) 0x00) /* - No interrupt has been generated. */ 1357 #define MMA865x_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* - One or more interrupt events have been generated. */ 1358 #define MMA865x_PULSE_SRC_AXZ_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1359 #define MMA865x_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* - Z-axis event has occurred. */ 1360 #define MMA865x_PULSE_SRC_AXY_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1361 #define MMA865x_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* - Y-axis event has occurred. */ 1362 #define MMA865x_PULSE_SRC_AXX_NONE ((uint8_t) 0x00) /* - No interrupt. */ 1363 #define MMA865x_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* - X-axis event has occurred. */ 1364 #define MMA865x_PULSE_SRC_DPE_SINGLE ((uint8_t) 0x00) /* - Single pulse event triggered interrupt. */ 1365 #define MMA865x_PULSE_SRC_DPE_DOUBLE ((uint8_t) 0x08) /* - Double pulse event triggered interrupt. */ 1366 #define MMA865x_PULSE_SRC_POL_Z_POSITIVE ((uint8_t) 0x00) /* - Pulse event that triggered interrupt was */ 1367 /* positive. */ 1368 #define MMA865x_PULSE_SRC_POL_Z_NEGATIVE ((uint8_t) 0x04) /* - Pulse event that triggered interrupt was */ 1369 /* negative. */ 1370 #define MMA865x_PULSE_SRC_POL_Y_POSITIVE ((uint8_t) 0x00) /* - Pulse event that triggered interrupt was */ 1371 /* positive. */ 1372 #define MMA865x_PULSE_SRC_POL_Y_NEGATIVE ((uint8_t) 0x02) /* - Pulse event that triggered interrupt was */ 1373 /* negative. */ 1374 #define MMA865x_PULSE_SRC_POL_X_POSITIVE ((uint8_t) 0x00) /* - Pulse event that triggered interrupt was */ 1375 /* positive. */ 1376 #define MMA865x_PULSE_SRC_POL_X_NEGATIVE ((uint8_t) 0x01) /* - Pulse event that triggered interrupt was */ 1377 /* negative. */ 1378 /*------------------------------*/ 1379 1380 1381 1382 1383 /*-------------------------------- 1384 ** Register: PULSE_THSX 1385 ** Enum: MMA865x_PULSE_THSX 1386 ** -- 1387 ** Offset : 0x23 - Pulse threshold for X-axes register 1388 ** ------------------------------*/ 1389 typedef union { 1390 struct { 1391 uint8_t thsx : 7; /* - Pulse threshold on X-axis. */ 1392 1393 } b; 1394 uint8_t w; 1395 } MMA865x_PULSE_THSX_t; 1396 1397 1398 /* 1399 ** PULSE_THSX - Bit field mask definitions 1400 */ 1401 #define MMA865x_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F) 1402 #define MMA865x_PULSE_THSX_THSX_SHIFT ((uint8_t) 0) 1403 1404 1405 /*------------------------------*/ 1406 1407 1408 1409 1410 /*-------------------------------- 1411 ** Register: PULSE_THSY 1412 ** Enum: MMA865x_PULSE_THSY 1413 ** -- 1414 ** Offset : 0x24 - Pulse threshold for Y-axes register 1415 ** ------------------------------*/ 1416 typedef union { 1417 struct { 1418 uint8_t thsy : 7; /* - Pulse threshold on Y-axis. */ 1419 1420 } b; 1421 uint8_t w; 1422 } MMA865x_PULSE_THSY_t; 1423 1424 1425 /* 1426 ** PULSE_THSY - Bit field mask definitions 1427 */ 1428 #define MMA865x_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F) 1429 #define MMA865x_PULSE_THSY_THSY_SHIFT ((uint8_t) 0) 1430 1431 1432 /*------------------------------*/ 1433 1434 1435 1436 1437 /*-------------------------------- 1438 ** Register: PULSE_THSZ 1439 ** Enum: MMA865x_PULSE_THSZ 1440 ** -- 1441 ** Offset : 0x25 - Pulse threshold for Z-axes register 1442 ** ------------------------------*/ 1443 typedef union { 1444 struct { 1445 uint8_t thsz : 7; /* - Pulse threshold on Z-axis. */ 1446 1447 } b; 1448 uint8_t w; 1449 } MMA865x_PULSE_THSZ_t; 1450 1451 1452 /* 1453 ** PULSE_THSZ - Bit field mask definitions 1454 */ 1455 #define MMA865x_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F) 1456 #define MMA865x_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0) 1457 1458 1459 /*------------------------------*/ 1460 1461 1462 1463 1464 /*-------------------------------- 1465 ** Register: PULSE_TMLT 1466 ** Enum: MMA865x_PULSE_TMLT 1467 ** -- 1468 ** Offset : 0x26 - First Pulse Time Window register 1469 ** ------------------------------*/ 1470 typedef uint8_t MMA865x_PULSE_TMLT_t; 1471 1472 1473 /*-------------------------------- 1474 ** Register: PULSE_LTCY 1475 ** Enum: MMA865x_PULSE_LTCY 1476 ** -- 1477 ** Offset : 0x27 - Pulse Latency Timer register 1478 ** ------------------------------*/ 1479 typedef uint8_t MMA865x_PULSE_LTCY_t; 1480 1481 1482 /*-------------------------------- 1483 ** Register: PULSE_WIND 1484 ** Enum: MMA865x_PULSE_WIND 1485 ** -- 1486 ** Offset : 0x28 - Second Pulse Time Window register 1487 ** ------------------------------*/ 1488 typedef uint8_t MMA865x_PULSE_WIND_t; 1489 1490 1491 /*-------------------------------- 1492 ** Register: ASLP_COUNT 1493 ** Enum: MMA865x_ASLP_COUNT 1494 ** -- 1495 ** Offset : 0x29 - Auto-WAKE/SLEEP Detection register 1496 ** ------------------------------*/ 1497 typedef uint8_t MMA865x_ASLP_COUNT_t; 1498 1499 1500 1501 1502 /*-------------------------------- 1503 ** Register: CTRL_REG1 1504 ** Enum: MMA865x_CTRL_REG1 1505 ** -- 1506 ** Offset : 0x2A - System Control 1 register 1507 ** ------------------------------*/ 1508 typedef union { 1509 struct { 1510 uint8_t active : 1; /* - Full-scale selection. */ 1511 1512 uint8_t f_read : 1; /* - Fast-read mode: Data format is limited to single byte. */ 1513 1514 uint8_t _reserved_ : 1; 1515 uint8_t dr : 3; /* - Data rate selection. */ 1516 1517 uint8_t aslp_rate : 2; /* - Configures the Auto-WAKE sample frequency when the device is in SLEEP */ 1518 /* Mode. */ 1519 1520 } b; 1521 uint8_t w; 1522 } MMA865x_CTRL_REG1_t; 1523 1524 1525 /* 1526 ** CTRL_REG1 - Bit field mask definitions 1527 */ 1528 #define MMA865x_CTRL_REG1_ACTIVE_MASK ((uint8_t) 0x01) 1529 #define MMA865x_CTRL_REG1_ACTIVE_SHIFT ((uint8_t) 0) 1530 1531 #define MMA865x_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02) 1532 #define MMA865x_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1) 1533 1534 #define MMA865x_CTRL_REG1_DR_MASK ((uint8_t) 0x38) 1535 #define MMA865x_CTRL_REG1_DR_SHIFT ((uint8_t) 3) 1536 1537 #define MMA865x_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0) 1538 #define MMA865x_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6) 1539 1540 1541 /* 1542 ** CTRL_REG1 - Bit field value definitions 1543 */ 1544 #define MMA865x_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* - Frequency = 50Hz */ 1545 #define MMA865x_CTRL_REG1_ASLP_RATE_12_5HZ ((uint8_t) 0x40) /* - Frequency = 12.5Hz */ 1546 #define MMA865x_CTRL_REG1_ASLP_RATE_6_25HZ ((uint8_t) 0x80) /* - Frequency = 6.25Hz */ 1547 #define MMA865x_CTRL_REG1_ASLP_RATE_1_56HZ ((uint8_t) 0xc0) /* - Frequency = 1.56Hz */ 1548 #define MMA865x_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* - ODR = 800Hz. */ 1549 #define MMA865x_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* - ODR = 400Hz. */ 1550 #define MMA865x_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* - ODR = 200Hz. */ 1551 #define MMA865x_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* - ODR = 100Hz. */ 1552 #define MMA865x_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* - ODR = 50Hz. */ 1553 #define MMA865x_CTRL_REG1_DR_12_5HZ ((uint8_t) 0x28) /* - ODR = 12.5Hz. */ 1554 #define MMA865x_CTRL_REG1_DR_6_25HZ ((uint8_t) 0x30) /* - ODR = 6.25Hz. */ 1555 #define MMA865x_CTRL_REG1_DR_1_56HZ ((uint8_t) 0x38) /* - ODR = 1.56Hz. */ 1556 #define MMA865x_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* - Normal Mode. */ 1557 #define MMA865x_CTRL_REG1_F_READ_FAST ((uint8_t) 0x02) /* - Fast Read Mode. */ 1558 #define MMA865x_CTRL_REG1_ACTIVE_STANDBY ((uint8_t) 0x00) /* - STANDBY mode. */ 1559 #define MMA865x_CTRL_REG1_ACTIVE_ACTIVATED ((uint8_t) 0x01) /* - ACTIVE mode. */ 1560 /*------------------------------*/ 1561 1562 1563 1564 1565 /*-------------------------------- 1566 ** Register: CTRL_REG2 1567 ** Enum: MMA865x_CTRL_REG2 1568 ** -- 1569 ** Offset : 0x2B - System Control 2 register 1570 ** ------------------------------*/ 1571 typedef union { 1572 struct { 1573 uint8_t mods : 2; /* - ACTIVE mode power scheme selection. */ 1574 1575 uint8_t slpe : 1; /* - Auto-SLEEP enable. */ 1576 1577 uint8_t smods : 2; /* - SLEEP mode power scheme selection. */ 1578 1579 uint8_t _reserved_ : 1; 1580 uint8_t rst : 1; /* - Software Reset. */ 1581 1582 uint8_t st : 1; /* - Self-Test Enable. */ 1583 1584 } b; 1585 uint8_t w; 1586 } MMA865x_CTRL_REG2_t; 1587 1588 1589 /* 1590 ** CTRL_REG2 - Bit field mask definitions 1591 */ 1592 #define MMA865x_CTRL_REG2_MODS_MASK ((uint8_t) 0x03) 1593 #define MMA865x_CTRL_REG2_MODS_SHIFT ((uint8_t) 0) 1594 1595 #define MMA865x_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04) 1596 #define MMA865x_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2) 1597 1598 #define MMA865x_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18) 1599 #define MMA865x_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3) 1600 1601 #define MMA865x_CTRL_REG2_RST_MASK ((uint8_t) 0x40) 1602 #define MMA865x_CTRL_REG2_RST_SHIFT ((uint8_t) 6) 1603 1604 #define MMA865x_CTRL_REG2_ST_MASK ((uint8_t) 0x80) 1605 #define MMA865x_CTRL_REG2_ST_SHIFT ((uint8_t) 7) 1606 1607 1608 /* 1609 ** CTRL_REG2 - Bit field value definitions 1610 */ 1611 #define MMA865x_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* - Self-Test disabled. */ 1612 #define MMA865x_CTRL_REG2_ST_EN ((uint8_t) 0x80) /* - Self-Test enabled. */ 1613 #define MMA865x_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* - Device reset disabled. */ 1614 #define MMA865x_CTRL_REG2_RST_EN ((uint8_t) 0x40) /* - Device reset enabled. */ 1615 #define MMA865x_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* - Normal Mode. */ 1616 #define MMA865x_CTRL_REG2_SMODS_LNLP ((uint8_t) 0x08) /* - Low Noise Low Power Mode. */ 1617 #define MMA865x_CTRL_REG2_SMODS_HR ((uint8_t) 0x10) /* - High Resolution Mode. */ 1618 #define MMA865x_CTRL_REG2_SMODS_LP ((uint8_t) 0x18) /* - Low Power Mode. */ 1619 #define MMA865x_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* - Auto-SLEEP is not enabled. */ 1620 #define MMA865x_CTRL_REG2_SLPE_EN ((uint8_t) 0x04) /* - Auto-SLEEP is enabled. */ 1621 #define MMA865x_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* - Normal Mode. */ 1622 #define MMA865x_CTRL_REG2_MODS_LNLP ((uint8_t) 0x01) /* - Low Noise Low Power Mode. */ 1623 #define MMA865x_CTRL_REG2_MODS_HR ((uint8_t) 0x02) /* - High Resolution Mode. */ 1624 #define MMA865x_CTRL_REG2_MODS_LP ((uint8_t) 0x03) /* - Low Power Mode. */ 1625 /*------------------------------*/ 1626 1627 1628 1629 1630 /*-------------------------------- 1631 ** Register: CTRL_REG3 1632 ** Enum: MMA865x_CTRL_REG3 1633 ** -- 1634 ** Offset : 0x2C - Interrupt Control register 1635 ** ------------------------------*/ 1636 typedef union { 1637 struct { 1638 uint8_t pp_od : 1; /* - Configures the interrupt pins to Push-Pull or to Open-Drain mode. */ 1639 1640 uint8_t ipol : 1; /* - Selects the polarity of the interrupt signals. */ 1641 1642 uint8_t _reserved_ : 1; 1643 uint8_t wake_ff_mt : 1; /* - Wake from Freefall/Motion interrupt. */ 1644 1645 uint8_t wake_pulse : 1; /* - Wake from Pulse interrupt. */ 1646 1647 uint8_t wake_lndprt : 1; /* - Wake from Orientation interrupt. */ 1648 1649 uint8_t wake_trans : 1; /* - Wake from Transient interrupt. */ 1650 1651 uint8_t fifo_gate : 1; /* - FIFO Gate */ 1652 1653 } b; 1654 uint8_t w; 1655 } MMA865x_CTRL_REG3_t; 1656 1657 1658 /* 1659 ** CTRL_REG3 - Bit field mask definitions 1660 */ 1661 #define MMA865x_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01) 1662 #define MMA865x_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0) 1663 1664 #define MMA865x_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02) 1665 #define MMA865x_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1) 1666 1667 #define MMA865x_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08) 1668 #define MMA865x_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3) 1669 1670 #define MMA865x_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10) 1671 #define MMA865x_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4) 1672 1673 #define MMA865x_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20) 1674 #define MMA865x_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5) 1675 1676 #define MMA865x_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40) 1677 #define MMA865x_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6) 1678 1679 #define MMA865x_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80) 1680 #define MMA865x_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7) 1681 1682 1683 /* 1684 ** CTRL_REG3 - Bit field value definitions 1685 */ 1686 #define MMA865x_CTRL_REG3_FIFO_GATE_BYPASSED ((uint8_t) 0x00) /* - FIFO gate is bypassed. */ 1687 #define MMA865x_CTRL_REG3_FIFO_GATE_BLOCKED ((uint8_t) 0x80) /* - The FIFO input buffer is blocked when */ 1688 /* transitioning from WAKE to SLEEP mode or from SLEEP */ 1689 /* to WAKE mode, until the FIFO is flushed. */ 1690 #define MMA865x_CTRL_REG3_WAKE_TRANS_BYPASSED ((uint8_t) 0x00) /* - Transient function is bypassed in SLEEP mode. */ 1691 #define MMA865x_CTRL_REG3_WAKE_TRANS_EN ((uint8_t) 0x40) /* - Transient function interrupt can wake up system. */ 1692 #define MMA865x_CTRL_REG3_WAKE_LNDPRT_BYPASSED ((uint8_t) 0x00) /* - Orientation function is bypassed in SLEEP mode. */ 1693 #define MMA865x_CTRL_REG3_WAKE_LNDPRT_EN ((uint8_t) 0x20) /* - Orientation function interrupt can wake up */ 1694 /* system. */ 1695 #define MMA865x_CTRL_REG3_WAKE_PULSE_BYPASSED ((uint8_t) 0x00) /* - Pulse function is bypassed in SLEEP mode. */ 1696 #define MMA865x_CTRL_REG3_WAKE_PULSE_EN ((uint8_t) 0x10) /* - Pulse function interrupt can wake up system. */ 1697 #define MMA865x_CTRL_REG3_WAKE_FF_MT_BYPASSED ((uint8_t) 0x00) /* - Freefall/Motion function is bypassed in SLEEP */ 1698 /* mode. */ 1699 #define MMA865x_CTRL_REG3_WAKE_FF_MT_EN ((uint8_t) 0x08) /* - Freefall/Motion function interrupt can wake up. */ 1700 #define MMA865x_CTRL_REG3_IPOL_ACTIVE_LOW ((uint8_t) 0x00) /* - ACTIVE low. */ 1701 #define MMA865x_CTRL_REG3_IPOL_ACTIVE_HIGH ((uint8_t) 0x02) /* - ACTIVE high. */ 1702 #define MMA865x_CTRL_REG3_PP_OD_PUSH_PULL ((uint8_t) 0x00) /* - Push-Pull. */ 1703 #define MMA865x_CTRL_REG3_PP_OD_OPEN_DRAIN ((uint8_t) 0x01) /* - Open Drain. */ 1704 /*------------------------------*/ 1705 1706 1707 1708 1709 /*-------------------------------- 1710 ** Register: CTRL_REG4 1711 ** Enum: MMA865x_CTRL_REG4 1712 ** -- 1713 ** Offset : 0x2D - Interrupt Enable register 1714 ** ------------------------------*/ 1715 typedef union { 1716 struct { 1717 uint8_t int_en_drdy : 1; /* - Data Ready Interrupt Enable. */ 1718 1719 uint8_t _reserved_ : 1; 1720 uint8_t int_en_ff_mt : 1; /* - Freefall/Motion Interrupt Enable. */ 1721 1722 uint8_t int_en_pulse : 1; /* - Pulse Detection Interrupt Enable. */ 1723 1724 uint8_t int_en_lndprt : 1; /* - Orientation (Landscape/Portrait) Interrupt Enable. */ 1725 1726 uint8_t int_en_trans : 1; /* - Transient Interrupt Enable. */ 1727 1728 uint8_t int_en_fifo : 1; /* - FIFO Interrupt Enable. */ 1729 1730 uint8_t int_en_aslp : 1; /* - Auto-SLEEP/WAKE Interrupt Enable. */ 1731 1732 } b; 1733 uint8_t w; 1734 } MMA865x_CTRL_REG4_t; 1735 1736 1737 /* 1738 ** CTRL_REG4 - Bit field mask definitions 1739 */ 1740 #define MMA865x_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01) 1741 #define MMA865x_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0) 1742 1743 #define MMA865x_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04) 1744 #define MMA865x_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2) 1745 1746 #define MMA865x_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08) 1747 #define MMA865x_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3) 1748 1749 #define MMA865x_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10) 1750 #define MMA865x_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4) 1751 1752 #define MMA865x_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20) 1753 #define MMA865x_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5) 1754 1755 #define MMA865x_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40) 1756 #define MMA865x_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6) 1757 1758 #define MMA865x_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80) 1759 #define MMA865x_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7) 1760 1761 1762 /* 1763 ** CTRL_REG4 - Bit field value definitions 1764 */ 1765 #define MMA865x_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1766 #define MMA865x_CTRL_REG4_INT_EN_ASLP_EN ((uint8_t) 0x80) /* - Interrupt is enabled. */ 1767 #define MMA865x_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1768 #define MMA865x_CTRL_REG4_INT_EN_FIFO_EN ((uint8_t) 0x40) /* - Interrupt is enabled. */ 1769 #define MMA865x_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1770 #define MMA865x_CTRL_REG4_INT_EN_TRANS_EN ((uint8_t) 0x20) /* - Interrupt is enabled. */ 1771 #define MMA865x_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1772 #define MMA865x_CTRL_REG4_INT_EN_LNDPRT_EN ((uint8_t) 0x10) /* - Interrupt is enabled. */ 1773 #define MMA865x_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1774 #define MMA865x_CTRL_REG4_INT_EN_PULSE_EN ((uint8_t) 0x08) /* - Interrupt is enabled. */ 1775 #define MMA865x_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1776 #define MMA865x_CTRL_REG4_INT_EN_FF_MT_EN ((uint8_t) 0x04) /* - Interrupt is enabled. */ 1777 #define MMA865x_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* - Interrupt is disabled. */ 1778 #define MMA865x_CTRL_REG4_INT_EN_DRDY_EN ((uint8_t) 0x01) /* - Interrupt is enabled. */ 1779 /*------------------------------*/ 1780 1781 1782 1783 1784 /*-------------------------------- 1785 ** Register: CTRL_REG5 1786 ** Enum: MMA865x_CTRL_REG5 1787 ** -- 1788 ** Offset : 0x2E - Interrupt Configuration register 1789 ** ------------------------------*/ 1790 typedef union { 1791 struct { 1792 uint8_t int_cfg_drdy : 1; /* - Data Ready INT1/INT2 Configuration. */ 1793 1794 uint8_t _reserved_ : 1; 1795 uint8_t int_cfg_ff_mt : 1; /* - Freefall/Motion INT1/INT2 Configuration. */ 1796 1797 uint8_t int_cfg_pulse : 1; /* - Pulse INT1/INT2 Configuration. */ 1798 1799 uint8_t int_cfg_lndprt : 1; /* - Orientation INT1/INT2 Configuration. */ 1800 1801 uint8_t int_cfg_trans : 1; /* - Transient INT1/INT2 Configuration. */ 1802 1803 uint8_t int_cfg_fifo : 1; /* - FIFO INT1/INT2 Configuration. */ 1804 1805 uint8_t int_cfg_aslp : 1; /* - Auto-SLEEP/WAKE INT1/INT2 Configuration. */ 1806 1807 } b; 1808 uint8_t w; 1809 } MMA865x_CTRL_REG5_t; 1810 1811 1812 /* 1813 ** CTRL_REG5 - Bit field mask definitions 1814 */ 1815 #define MMA865x_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01) 1816 #define MMA865x_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0) 1817 1818 #define MMA865x_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04) 1819 #define MMA865x_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2) 1820 1821 #define MMA865x_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08) 1822 #define MMA865x_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3) 1823 1824 #define MMA865x_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10) 1825 #define MMA865x_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4) 1826 1827 #define MMA865x_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20) 1828 #define MMA865x_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5) 1829 1830 #define MMA865x_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40) 1831 #define MMA865x_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6) 1832 1833 #define MMA865x_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80) 1834 #define MMA865x_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7) 1835 1836 1837 /* 1838 ** CTRL_REG5 - Bit field value definitions 1839 */ 1840 #define MMA865x_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1841 #define MMA865x_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* - Interrupt is routed to INT1 pin. */ 1842 #define MMA865x_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1843 #define MMA865x_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* - Interrupt is routed to INT1 pin. */ 1844 #define MMA865x_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1845 #define MMA865x_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* - Interrupt is routed to INT1 pin. */ 1846 #define MMA865x_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1847 #define MMA865x_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* - Interrupt is routed to INT1 pin. */ 1848 #define MMA865x_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1849 #define MMA865x_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* - Interrupt is routed to INT1 pin. */ 1850 #define MMA865x_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1851 #define MMA865x_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* - Interrupt is routed to INT1 pin. */ 1852 #define MMA865x_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* - Interrupt is routed to INT2 pin. */ 1853 #define MMA865x_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* - Interrupt is routed to INT1 pin. */ 1854 /*------------------------------*/ 1855 1856 1857 1858 1859 /*-------------------------------- 1860 ** Register: OFF_X 1861 ** Enum: MMA865x_OFF_X 1862 ** -- 1863 ** Offset : 0x2F - Offset Correction X register 1864 ** ------------------------------*/ 1865 typedef uint8_t MMA865x_OFF_X_t; 1866 1867 1868 /*-------------------------------- 1869 ** Register: OFF_Y 1870 ** Enum: MMA865x_OFF_Y 1871 ** -- 1872 ** Offset : 0x30 - Offset Correction Y register 1873 ** ------------------------------*/ 1874 typedef uint8_t MMA865x_OFF_Y_t; 1875 1876 1877 /*-------------------------------- 1878 ** Register: OFF_Z 1879 ** Enum: MMA865x_OFF_Z 1880 ** -- 1881 ** Offset : 0x31 - Offset Correction Z register 1882 ** ------------------------------*/ 1883 typedef uint8_t MMA865x_OFF_Z_t; 1884 1885 1886 1887 #endif /* MMA865x_H_ */ 1888
