1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ 9 10 /** 11 * @brief MIPI-DBI driver APIs 12 * @defgroup mipi_dbi_interface MIPI-DBI driver APIs 13 * @ingroup io_interfaces 14 * @{ 15 */ 16 17 /** 18 * SPI 3 wire (Type C1). Uses 9 write clocks to send a byte of data. 19 * The bit sent on the 9th clock indicates whether the byte is a 20 * command or data byte 21 * 22 * 23 * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .- 24 * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' 25 * 26 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- 27 * DOUT |D/C| D7| D6| D5| D4| D3| D2| D1| D0|D/C| D7| D6| D5| D4|...| 28 * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- 29 * | Word 1 | Word n 30 * 31 * -. .- 32 * CS '-----------------------------------------------------------' 33 */ 34 #define MIPI_DBI_MODE_SPI_3WIRE 0x1 35 /** 36 * SPI 4 wire (Type C3). Uses 8 write clocks to send a byte of data. 37 * an additional C/D pin will be use to indicate whether the byte is a 38 * command or data byte 39 * 40 * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. 41 * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '--- 42 * 43 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- 44 * DOUT | D7| D6| D5| D4| D3| D2| D1| D0| D7| D6| D5| D4| D3| D2| D1| D0| 45 * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- 46 * | Word 1 | Word n 47 * 48 * -. .- 49 * CS '---------------------------------------------------------------' 50 * 51 * -.-------------------------------.-------------------------------.- 52 * CD | D/C | D/C | 53 * -'-------------------------------'-------------------------------'- 54 */ 55 #define MIPI_DBI_MODE_SPI_4WIRE 0x2 56 /** 57 * Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus. 58 * 59 * -. .--------. .------------------------ 60 * CS '---' '---' 61 * 62 * ------------------------------------------- 63 * RESX 64 * 65 * .-------------------------------- 66 * D/CX ----------' 67 * 68 * 69 * R/WX ------------------------------------------- 70 * 71 * ------------------------------------------- 72 * E 73 * 74 * .--------. .--------------------------. 75 * D[15:0]/ -| COMMAND|---| DATA | 76 * D[8:0]/ '--------' '--------------------------' 77 * D[7:0] 78 * 79 * Please refer to the MIPI DBI specification for a detailed cycle diagram. 80 */ 81 #define MIPI_DBI_MODE_6800_BUS_16_BIT 0x3 82 #define MIPI_DBI_MODE_6800_BUS_9_BIT 0x4 83 #define MIPI_DBI_MODE_6800_BUS_8_BIT 0x5 84 /** 85 * Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus. 86 * 87 * -. .- 88 * CS '---------------------------------------' 89 * 90 * ------------------------------------------- 91 * RESX 92 * 93 * --. .---------------------------- 94 * D/CX '-----------' 95 * 96 * ---. .--------. .---------------------- 97 * WRX '---' '---' 98 * 99 * ------------------------------------------- 100 * RDX 101 * 102 * .--------. .--------------------------. 103 * D[15:0]/ ---| COMMAND|---| DATA | 104 * D[8:0]/ '--------' '--------------------------' 105 * D[7:0] 106 * 107 * Please refer to the MIPI DBI specification for a detailed cycle diagram. 108 */ 109 #define MIPI_DBI_MODE_8080_BUS_16_BIT 0x6 110 #define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 111 #define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 112 113 /** MIPI DBI tearing enable synchronization is disabled. */ 114 #define MIPI_DBI_TE_NO_EDGE 0x0 115 116 /** 117 * MIPI DBI tearing enable synchronization on rising edge of TE signal. 118 * The controller will only send display write data on a rising edge of TE. 119 * This should be used when the controller can send a frame worth of data 120 * data to the display panel faster than the display panel can read a frame 121 * from its RAM 122 * 123 * .------. .------. 124 * TE -----' '------------------------' '------------- 125 * -----. .----------------------. 126 * CS '--------' '-------------------- 127 */ 128 #define MIPI_DBI_TE_RISING_EDGE 0x1 129 130 /** 131 * MIPI DBI tearing enable synchronization on falling edge of TE signal. 132 * The controller will only send display write data on a falling edge of TE. 133 * This should be used when the controller sends a frame worth of data 134 * data to the display panel slower than the display panel can read a frame 135 * from its RAM. TE synchronization in this mode will only work if the 136 * controller can complete the write before the display panel completes 2 137 * read cycles, otherwise the read pointer will "catch up" with the write 138 * pointer. 139 * 140 * .------. .------. 141 * TE -----' '------------------------' '------------- 142 * ------------. .----- 143 * CS '---------------------------------------' 144 */ 145 #define MIPI_DBI_TE_FALLING_EDGE 0x2 146 147 /** 148 * SPI transfer of DBI commands as 8-bit blocks, the default behaviour in 149 * SPI 4 wire (Type C3) mode. The clocking diagram corresponds exactly to 150 * the illustration of Type C3. 151 */ 152 #define MIPI_DBI_SPI_XFR_8BIT 8 153 /** 154 * SPI transfer of DBI commands as 16-bit blocks, a rare and seldom behaviour 155 * in SPI 4 wire (Type C3) mode. The corresponding clocking diagram is slightly 156 * different to the illustration of Type C3. 157 * 158 * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. 159 * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '--- 160 * 161 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- 162 * DOUT |D15|D14|D13|D12|D11|D10| D9| D8| D7| D6| D5| D4| D3| D2| D1| D0| 163 * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- 164 * | Word 1 (stuffing) : (byte) | 165 * 166 * -. .- 167 * CS '---------------------------------------------------------------' 168 * 169 * -.---------------------------------------------------------------.- 170 * CD | D/C | 171 * -'---------------------------------------------------------------'- 172 */ 173 #define MIPI_DBI_SPI_XFR_16BIT 16 174 175 /** 176 * @} 177 */ 178 179 180 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ */ 181
