1 /*
2 * Copyright (c) 2022 ITE.
3 * Copyright 2022 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_it6161.h"
9 #include "mipi_rx.h"
10 #include "hdmi_tx.h"
11 #include "fsl_debug_console.h"
12
13 static uint32_t RxRCLK = 0U;
14 uint32_t MCLK = 0U;
15 uint32_t RxPCLK = 0U;
16 static uint32_t MHFP, MHSW, MHBP, MHDEW, MHVR2nd;
17 static uint32_t MVFP, MVSW, MVBP, MVDEW, MVFP2nd;
18 static uint32_t PHFP, PHSW, PHBP, PHDEW, PHVR2nd;
19 static uint32_t PVFP, PVSW, PVBP, PVDEW, PVFP2nd;
20 uint32_t MHBlank, MVTotal, PHTotal, PVTotal;
21
MIPIRX_DumpRegs(display_handle_t * handle)22 void MIPIRX_DumpRegs(display_handle_t *handle)
23 {
24 #if (DEBUG_DUMP_MIPIRX_REGISTER == 0x01U)
25 int i = 0;
26 int j = 0;
27 uint8_t value = 0U;
28
29 PRINTF("\r\n---------------------------------------------------------------------------\r\n");
30 PRINTF("\r\nMIPIRX Reg\r\n");
31 PRINTF(" ");
32 for (j = 0; j < 16; j++)
33 {
34 PRINTF(" %02X", (int)j);
35 if ((j == 3) || (j == 7) || (j == 11))
36 {
37 PRINTF(" ");
38 }
39 }
40 PRINTF("\r\n---------------------------------------------------------------------------\r\n");
41
42 for (i = 0; i < 0x100; i += 16)
43 {
44 PRINTF("[%3X] ", i);
45 for (j = 0; j < 16; j++)
46 {
47 MIPIRX_ReadI2C_Byte(handle, ((i + j) & 0xFF), &value);
48 PRINTF(" %02X", value);
49 if ((j == 3) || (j == 7) || (j == 11))
50 {
51 PRINTF(" -");
52 }
53 }
54 PRINTF("\r\n");
55 if ((i % 0x40) == 0x30)
56 {
57 PRINTF("-----------------------------------------------------\r\n");
58 }
59 }
60 PRINTF("-------------------------------------------------------------\r\n");
61 #endif // DEBUG_DUMP_MIPIRX_REGISTER
62 }
63
MIPIRX_CalRclk(display_handle_t * handle)64 void MIPIRX_CalRclk(display_handle_t *handle)
65 {
66 uint8_t i = 0U;
67 uint32_t t10usint = 0U;
68 uint32_t sum = 0U;
69 uint8_t retry = 5U;
70
71 for (i = 0U; i < retry; i++)
72 {
73 MIPIRX_SetI2C_Byte(handle, 0x94, 0x80, 0x80); // Enable RCLK 100ms count
74 delay1ms(100);
75 MIPIRX_SetI2C_Byte(handle, 0x94, 0x80, 0x00); // Disable RCLK 100ms count
76
77 MIPIRX_ReadI2C_Byte(handle, 0x97, &RxRCLK);
78 RxRCLK <<= 8;
79 MIPIRX_ReadI2C_Byte(handle, 0x96, &RxRCLK);
80 RxRCLK <<= 8;
81 MIPIRX_ReadI2C_Byte(handle, 0x95, &RxRCLK);
82 sum += RxRCLK;
83 }
84 sum /= retry;
85
86 RxRCLK = sum / 108U;
87 t10usint = RxRCLK;
88 MIPIRX_DEBUG_PRINTF("RxRCLK = %d,%03d,%03d\r\n", (sum * 10) / 1000000, ((sum * 10) % 1000000) / 1000,
89 ((sum * 10) % 100));
90 MIPIRX_DEBUG_PRINTF("T10usInt=0x%03X\r\n", (int)t10usint);
91 MIPIRX_WriteI2C_Byte(handle, 0x91, t10usint & 0xFFU);
92 }
93
94 #define MAX_SUPPORT_LANES_CNT (0x03U) /* Support 1, 2, 4 lanes number, so maximum supported lanes count is 3 */
95 static uint8_t MIPIRX_REG80_SETUP_LANES[][MAX_SUPPORT_LANES_CNT] = {
96 {
97 0x02U, /* MIPIRX PCLKSel = 1; 4-lane, MCLK = 1/1 PCLK */
98 0x05U, /* MPPCLKSel = 6; 2-lane : MCLK = 1/1 PCLK */
99 0x08U, /* MPPCLKSel = 8; 1-lane : MCLK = 3/4 PCLK */
100 }, /* for data type RGB_18b */
101 {
102 0x02U, /* MPPCLKSel = 1; 4-lane : MCLK = 3/4 PCLK */
103 0x05U, /* MPPCLKSel = 3; 2-lane : MCLK = 3/4 PCLK */
104 0x0BU, /* MPPCLKSel = 5; 1-lane : MCLK = 3/4 PCLK */
105 }, /* for other data type */
106 };
107
MIPIRX_AfeCfg(display_handle_t * handle)108 void MIPIRX_AfeCfg(display_handle_t *handle)
109 {
110 /* reference: MIPI Alliance Specification for DSI Ch8.7 Table 16 Data Types for Processor-sourced Packets */
111 uint8_t dataType = 0U;
112 uint8_t MIPIRX_LaneNum = 0U;
113 uint8_t dataTypeIdx = 0U;
114
115 MIPIRX_ReadI2C_Byte(handle, 0x28, &dataType);
116 MIPIRX_LaneNum = it6161.mipi_rx.lanes - 1U;
117 dataTypeIdx = (int8_t)dataType == RGB_18b ? (0x00U) : (0x01U);
118
119 MIPIRX_DEBUG_PRINTF("mipi receive video format: 0x%02x\r\n", dataType);
120 MIPIRX_SetI2C_Byte(handle, 0x80, 0x1F, MIPIRX_REG80_SETUP_LANES[dataTypeIdx][MIPIRX_LaneNum]);
121 }
122
MIPIRX_CalMclk(display_handle_t * handle)123 void MIPIRX_CalMclk(display_handle_t *handle)
124 {
125 uint8_t i;
126 uint32_t rddata = 0U;
127 uint32_t sum = 0U;
128 uint8_t retry = 3U;
129 uint8_t value = 0U;
130
131 for (i = 0U; i < retry; i++)
132 {
133 MIPIRX_SetI2C_Byte(handle, 0x9B, 0x80, 0x80);
134 delay1ms(5);
135 MIPIRX_SetI2C_Byte(handle, 0x9B, 0x80, 0x00);
136
137 MIPIRX_ReadI2C_Byte(handle, 0x9A, &value);
138 rddata = value;
139 MIPIRX_ReadI2C_Byte(handle, 0x9B, &value);
140 rddata = (((uint32_t)value & 0x0FU) << 8) + rddata;
141
142 sum += rddata;
143 }
144
145 sum /= retry;
146
147 MCLK = RxRCLK * 2048U / sum;
148 MIPIRX_DEBUG_PRINTF("MCLK = %d,%03d MHz\r\n", (MCLK) / 1000, MCLK % 1000);
149 }
150
MIPIRX_CalPclk(display_handle_t * handle)151 void MIPIRX_CalPclk(display_handle_t *handle)
152 {
153 uint8_t i;
154 uint32_t rddata = 0U;
155 uint32_t sum = 0U;
156 uint8_t retry = 3U;
157 uint8_t value = 0U;
158
159 MIPIRX_SetI2C_Byte(handle, 0x99, 0x80, 0x00);
160 for (i = 0U; i < retry; i++)
161 {
162 MIPIRX_SetI2C_Byte(handle, 0x99, 0x80, 0x80);
163 delay1ms(5);
164 MIPIRX_SetI2C_Byte(handle, 0x99, 0x80, 0x00);
165
166 MIPIRX_ReadI2C_Byte(handle, 0x98, &value);
167 rddata = value;
168 MIPIRX_ReadI2C_Byte(handle, 0x99, &value);
169 rddata = (((uint32_t)value & 0x0FU) << 8) + rddata;
170
171 sum += rddata;
172 }
173
174 sum /= retry;
175
176 RxPCLK = (RxRCLK * 2048U) / sum;
177 MIPIRX_DEBUG_PRINTF("RxPCLK = %d,%03d MHz\r\n", (RxPCLK) / 1000U, (RxPCLK % 1000U));
178 }
179
MIPIRX_ShowMRec(display_handle_t * handle)180 void MIPIRX_ShowMRec(display_handle_t *handle)
181 {
182 uint8_t value = 0U;
183
184 MIPIRX_ReadI2C_Byte(handle, 0x52, &value);
185 MHSW = value;
186 MIPIRX_ReadI2C_Byte(handle, 0x53, &value);
187 MHSW += ((uint32_t)value & 0x3FU) << 8;
188
189 MIPIRX_ReadI2C_Byte(handle, 0x50, &value);
190 MHFP = value;
191 MIPIRX_ReadI2C_Byte(handle, 0x51, &value);
192 MHFP += ((uint32_t)value & 0x3FU) << 8;
193
194 MIPIRX_ReadI2C_Byte(handle, 0x54, &value);
195 MHBP = value;
196 MIPIRX_ReadI2C_Byte(handle, 0x55, &value);
197 MHBP += ((uint32_t)value & 0x3FU) << 8;
198
199 MIPIRX_ReadI2C_Byte(handle, 0x56, &value);
200 MHDEW = value;
201 MIPIRX_ReadI2C_Byte(handle, 0x57, &value);
202 MHDEW += ((uint32_t)value & 0x3FU) << 8;
203
204 MIPIRX_ReadI2C_Byte(handle, 0x58, &value);
205 MHVR2nd = value;
206 MIPIRX_ReadI2C_Byte(handle, 0x59, &value);
207 MHVR2nd += ((uint32_t)value & 0x3FU) << 8;
208
209 MHBlank = MHFP + MHSW + MHBP;
210
211 MIPIRX_ReadI2C_Byte(handle, 0x5C, &value);
212 MVSW = value;
213 MIPIRX_ReadI2C_Byte(handle, 0x5D, &value);
214 MVSW += ((uint32_t)value & 0x3FU) << 8;
215
216 MIPIRX_ReadI2C_Byte(handle, 0x5A, &value);
217 MVFP = value;
218 MIPIRX_ReadI2C_Byte(handle, 0x5B, &value);
219 MVFP += ((uint32_t)value & 0x3FU) << 8;
220
221 MIPIRX_ReadI2C_Byte(handle, 0x5E, &value);
222 MVBP = value;
223 MIPIRX_ReadI2C_Byte(handle, 0x5F, &value);
224 MVBP += ((uint32_t)value & 0x3FU) << 8;
225
226 MIPIRX_ReadI2C_Byte(handle, 0x60, &value);
227 MVDEW = value;
228 MIPIRX_ReadI2C_Byte(handle, 0x61, &value);
229 MVDEW += ((uint32_t)value & 0x3FU) << 8;
230
231 MIPIRX_ReadI2C_Byte(handle, 0x62, &value);
232 MVFP2nd = value;
233 MIPIRX_ReadI2C_Byte(handle, 0x63, &value);
234 MVFP2nd += ((uint32_t)value & 0x3FU) << 8;
235
236 MVTotal = MVFP + MVSW + MVBP + MVDEW;
237
238 MIPIRX_DEBUG_PRINTF("MHFP = %d\r\n", MHFP);
239 MIPIRX_DEBUG_PRINTF("MHSW = %d\r\n", MHSW);
240 MIPIRX_DEBUG_PRINTF("MHBP = %d\r\n", MHBP);
241 MIPIRX_DEBUG_PRINTF("MHDEW = %d\r\n", MHDEW);
242 MIPIRX_DEBUG_PRINTF("MHVR2nd = %d\r\n", MHVR2nd);
243 MIPIRX_DEBUG_PRINTF("MHBlank = %d\r\n", MHBlank);
244
245 MIPIRX_DEBUG_PRINTF("MVFP = %d\r\n", MVFP);
246 MIPIRX_DEBUG_PRINTF("MVSW = %d\r\n", MVSW);
247 MIPIRX_DEBUG_PRINTF("MVBP = %d\r\n", MVBP);
248 MIPIRX_DEBUG_PRINTF("MVDEW = %d\r\n", MVDEW);
249 MIPIRX_DEBUG_PRINTF("MVFP2nd = %d\r\n", MVFP2nd);
250 MIPIRX_DEBUG_PRINTF("MVTotal = %d\r\n", MVTotal);
251
252 MIPIRX_DEBUG_PRINTF("\r\n");
253 }
254
MIPIRX_ResetPDomain(display_handle_t * handle)255 void MIPIRX_ResetPDomain(display_handle_t *handle)
256 {
257 /* P Clock Domain Reset */
258 MIPIRX_SetI2C_Byte(handle, MIPI_RX_SOFT_RESET_REG05, MIPI_RX_SOFT_RESET_REG05_RegMPSoftPRst_MASK,
259 MIPI_RX_SOFT_RESET_REG05_RegMPSoftPRst(0x01U));
260 /* Release Video Clock Domain Reset */
261 MIPIRX_SetI2C_Byte(handle, MIPI_RX_SOFT_RESET_REG05, MIPI_RX_SOFT_RESET_REG05_RegMPSoftPRst_MASK,
262 MIPI_RX_SOFT_RESET_REG05_RegMPSoftPRst(0x00U));
263 }
264
HDMITX_GenerateBlankTiming(display_handle_t * handle)265 void HDMITX_GenerateBlankTiming(display_handle_t *handle)
266 {
267 uint32_t hsync_start, hsync_end, vsync_start, vsync_end, htotal, hde_start, vtotal;
268 uint32_t vsync_start_2nd = 0x00U, vsync_end_2nd = 0x00U, vsync_rising_at_h_2nd;
269
270 hsync_start = (uint32_t)it6161.hdmi_tx.mode.hsync_start - (uint32_t)it6161.hdmi_tx.mode.hdisplay - 0x01U;
271 hsync_end = hsync_start + ((uint32_t)it6161.hdmi_tx.mode.hsync_end - (uint32_t)it6161.hdmi_tx.mode.hsync_start);
272 vsync_rising_at_h_2nd = hsync_start + ((uint32_t)it6161.hdmi_tx.mode.htotal / 0x02U);
273 hde_start = (uint32_t)it6161.hdmi_tx.mode.htotal - (uint32_t)it6161.hdmi_tx.mode.hsync_start;
274 htotal = (uint32_t)it6161.hdmi_tx.mode.htotal - 0x01U;
275
276 vsync_start = (uint32_t)it6161.hdmi_tx.mode.vsync_start - (uint32_t)it6161.hdmi_tx.mode.vdisplay;
277 vsync_end = (uint32_t)it6161.hdmi_tx.mode.vsync_end - (uint32_t)it6161.hdmi_tx.mode.vdisplay;
278 /* Force tx clk/vid stable */
279 HDMITX_SetI2C_Byte(
280 handle, HDMI_TX_HDMI_CONTROL_REGD1,
281 HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_MASK |
282 HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_MASK,
283 HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable((uint32_t)it6161.hdmi_tx.tx_clk_stable) |
284 HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable((uint32_t)it6161.hdmi_tx.tx_vid_stable));
285
286 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_GENERATOR_REGA9, HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_MASK,
287 HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM((uint32_t)it6161.hdmi_tx.hdmitx_bypass_mode));
288 HDMITX_SetI2C_Byte(
289 handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_MASK,
290 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE((uint32_t)it6161.hdmi_tx.de_generation_enable));
291
292 /* Setup pattern generation horizontal total */
293 HDMITX_SetI2C_Byte(
294 handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_MASK,
295 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal((vsync_rising_at_h_2nd & 0x0FF0U) >> 0x04U));
296 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90,
297 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_MASK,
298 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(vsync_rising_at_h_2nd & 0x000FU));
299 /* Setup polarity */
300 HDMITX_SetI2C_Byte(
301 handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90,
302 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_MASK | HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_MASK,
303 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol((uint32_t)it6161.hdmi_tx.vertical_sync_polarity) |
304 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol((uint32_t)it6161.hdmi_tx.horizontal_sync_polarity));
305
306 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95,
307 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_MASK,
308 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS(hsync_start & 0xFFU));
309 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96,
310 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_MASK,
311 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE(hsync_end & 0xFFU));
312 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97,
313 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_MASK |
314 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_MASK,
315 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE((hsync_end & 0x0F00U) >> 0x08U) |
316 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS((hsync_start & 0x0F00U) >> 0x08U));
317
318 if (it6161.mipi_rx.interlaced_mode == 0x0U)
319 {
320 vsync_start_2nd = 0x0FFFU;
321 vsync_end_2nd = 0x3FU;
322 vtotal = (uint32_t)it6161.hdmi_tx.mode.vtotal - 0x01U;
323 }
324 else
325 {
326 vtotal = (uint32_t)it6161.hdmi_tx.mode.vtotal * 2U;
327 }
328
329 HDMITX_SetI2C_Byte(
330 handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5,
331 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_MASK,
332 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced((uint32_t)it6161.mipi_rx.interlaced_mode));
333 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0,
334 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_MASK,
335 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS((uint32_t)vsync_start));
336 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1,
337 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_MASK |
338 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_MASK,
339 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS((vsync_start & 0xF00U) >> 0x08U) |
340 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE(vsync_end & 0x0FU));
341 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2,
342 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_MASK,
343 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd((uint32_t)vsync_start_2nd));
344 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6,
345 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_MASK |
346 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_MASK,
347 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd((vsync_end_2nd & 0x00F0U) >> 0x04U) |
348 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE((vsync_end & 0x00F0U) >> 0x04U));
349 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3,
350 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_MASK |
351 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_MASK,
352 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd(vsync_end_2nd & 0x000FU) |
353 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd(vsync_start_2nd & 0xFF00U >> 0x08U));
354 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4,
355 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_MASK,
356 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise((uint32_t)vsync_rising_at_h_2nd));
357
358 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_GENERATOR_REGB1,
359 HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_MASK | HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_MASK |
360 HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_MASK,
361 HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE((hsync_end & 0x1000U) >> 12) |
362 HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS((hsync_start & 0x1000U) >> 12) |
363 HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES((hde_start & 0x1000U) >> 12));
364 HDMITX_SetI2C_Byte(
365 handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5,
366 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_MASK |
367 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_MASK,
368 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn((uint32_t)it6161.hdmi_tx.de_only_in) |
369 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise((vsync_rising_at_h_2nd & 0x0F00U) >> 8));
370
371 HDMITX_SetI2C_Byte(
372 handle, HDMI_TX_PATTERN_GENERATOR_REGB2,
373 HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_MASK | HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_MASK,
374 HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise((vsync_rising_at_h_2nd & 0x1000U) >> 12) |
375 HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal((vsync_rising_at_h_2nd & 0x1000U) >> 12));
376
377 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90,
378 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_MASK,
379 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(htotal & 0x000FU));
380 HDMITX_WriteI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91,
381 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal((htotal & 0x0FF0U) >> 0x04U));
382 HDMITX_SetI2C_Byte(handle, HDMI_TX_PATTERN_GENERATOR_REGB2, HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_MASK,
383 HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal((htotal & 0x1000U) >> 12));
384 HDMITX_WriteI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98,
385 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal(vtotal & 0x0FFU));
386 HDMITX_WriteI2C_Byte(handle, HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99,
387 HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal((vtotal & 0xF00U) >> 0x08U));
388 }
389
MIPIRX_ShowPrec(display_handle_t * handle)390 void MIPIRX_ShowPrec(display_handle_t *handle)
391 {
392 uint8_t value = 0U;
393
394 MIPIRX_ReadI2C_Byte(handle, 0x30, &value);
395 PHFP = value;
396 MIPIRX_ReadI2C_Byte(handle, 0x31, &value);
397 PHFP += ((uint32_t)value & 0x3FU) << 8;
398
399 MIPIRX_ReadI2C_Byte(handle, 0x32, &value);
400 PHSW = value;
401 MIPIRX_ReadI2C_Byte(handle, 0x33, &value);
402 PHSW += ((uint32_t)value & 0x3FU) << 8;
403
404 MIPIRX_ReadI2C_Byte(handle, 0x34, &value);
405 PHBP = value;
406 MIPIRX_ReadI2C_Byte(handle, 0x35, &value);
407 PHBP += ((uint32_t)value & 0x3FU) << 8;
408
409 MIPIRX_ReadI2C_Byte(handle, 0x36, &value);
410 PHDEW = value;
411 MIPIRX_ReadI2C_Byte(handle, 0x37, &value);
412 PHDEW += ((uint32_t)value & 0x3FU) << 8;
413
414 MIPIRX_ReadI2C_Byte(handle, 0x38, &value);
415 PHVR2nd = value;
416 MIPIRX_ReadI2C_Byte(handle, 0x39, &value);
417 PHVR2nd += ((uint32_t)value & 0x3FU) << 8;
418
419 PHTotal = PHFP + PHSW + PHBP + PHDEW;
420
421 MIPIRX_ReadI2C_Byte(handle, 0x3A, &value);
422 PVFP = value;
423 MIPIRX_ReadI2C_Byte(handle, 0x3B, &value);
424 PVFP += ((uint32_t)value & 0x3FU) << 8;
425
426 MIPIRX_ReadI2C_Byte(handle, 0x3C, &value);
427 PVSW = value;
428 MIPIRX_ReadI2C_Byte(handle, 0x3D, &value);
429 PVSW += ((uint32_t)value & 0x3FU) << 8;
430
431 MIPIRX_ReadI2C_Byte(handle, 0x3E, &value);
432 PVBP = value;
433 MIPIRX_ReadI2C_Byte(handle, 0x3F, &value);
434 PVBP += ((uint32_t)value & 0x3FU) << 8;
435
436 MIPIRX_ReadI2C_Byte(handle, 0x40, &value);
437 PVDEW = value;
438 MIPIRX_ReadI2C_Byte(handle, 0x41, &value);
439 PVDEW += ((uint32_t)value & 0x3FU) << 8;
440
441 MIPIRX_ReadI2C_Byte(handle, 0x42, &value);
442 PVFP2nd = value;
443 MIPIRX_ReadI2C_Byte(handle, 0x43, &value);
444 PVFP2nd += ((uint32_t)value & 0x3FU) << 8;
445
446 PVTotal = PVFP + PVSW + PVBP + PVDEW;
447
448 MIPIRX_DEBUG_PRINTF("PHFP = %d\r\n", PHFP);
449 MIPIRX_DEBUG_PRINTF("PHSW = %d\r\n", PHSW);
450 MIPIRX_DEBUG_PRINTF("PHBP = %d\r\n", PHBP);
451 MIPIRX_DEBUG_PRINTF("PHDEW = %d\r\n", PHDEW);
452 MIPIRX_DEBUG_PRINTF("PHVR2nd = %d\r\n", PHVR2nd);
453 MIPIRX_DEBUG_PRINTF("PHTotal = %d\r\n", PHTotal);
454
455 MIPIRX_DEBUG_PRINTF("PVFP = %d\r\n", PVFP);
456 MIPIRX_DEBUG_PRINTF("PVSW = %d\r\n", PVSW);
457 MIPIRX_DEBUG_PRINTF("PVBP = %d\r\n", PVBP);
458 MIPIRX_DEBUG_PRINTF("PVDEW = %d\r\n", PVDEW);
459 MIPIRX_DEBUG_PRINTF("PVFP2nd = %d\r\n", PVFP2nd);
460 MIPIRX_DEBUG_PRINTF("PVTotal = %d\r\n", PVTotal);
461 MIPIRX_DEBUG_PRINTF("\r\n");
462 }
463
MIPIRX_Reg06_Process(display_handle_t * handle,uint8_t Reg06)464 void MIPIRX_Reg06_Process(display_handle_t *handle, uint8_t Reg06)
465 {
466 uint8_t value = 0U;
467
468 // Interrupt Reg06
469 MIPIRX_ReadI2C_Byte(handle, 0x0D, &value);
470 if ((Reg06 & 0x01U) != 0x0U)
471 {
472 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x01);
473 MIPIRX_DEBUG_PRINTF("PPS MVidStb Change Interrupt ...reg0D %x\r\n", value);
474
475 if ((value & 0x10U) != 0x0U)
476 {
477 MIPIRX_DEBUG_PRINTF("MVidStb Change to HIGH,\r\n");
478 MIPIRX_CalRclk(handle);
479 MIPIRX_CalMclk(handle);
480 MIPIRX_ShowMRec(handle);
481 MIPIRX_AfeCfg(handle);
482 MIPIRX_ResetPDomain(handle);
483 }
484 else
485 {
486 MIPIRX_DEBUG_PRINTF("MVidStb Change to LOW ...\r\n");
487 }
488 }
489
490 if ((Reg06 & 0x02U) != 0x0U)
491 {
492 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x02);
493 }
494 #if (!EnMBPM)
495 if ((Reg06 & 0x04U) != 0x0U)
496 {
497 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x04);
498 MIPIRX_DEBUG_PRINTF("PPS MHDE Error Interrupt !!!\r\n");
499 }
500 #endif // #if (EnMBPM == false)
501
502 if ((Reg06 & 0x08U) != 0x0U)
503 {
504 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x08);
505 MIPIRX_DEBUG_PRINTF("PPS MVSync Error Interrupt !!!\r\n");
506 }
507
508 if ((Reg06 & 0x10U) != 0x0U)
509 {
510 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x10);
511 MIPIRX_DEBUG_PRINTF("PPS PVidStb Change Interrupt ...\r\n");
512 if ((value & 0x30U) != 0x0U)
513 {
514 MIPIRX_DEBUG_PRINTF("PVidStb Change to HIGH, ");
515 MIPIRX_CalRclk(handle);
516 MIPIRX_CalPclk(handle);
517 MIPIRX_ShowPrec(handle);
518 MIPIRX_WriteI2C_Byte(handle, MIPI_RX_CRC_REGC0,
519 MIPI_RX_CRC_REGC0_RegEnTTLTxCRC((uint32_t)it6161.mipi_rx.enable_ttl_tx_crc) +
520 MIPI_RX_CRC_REGC0_RegTTLTxCRCNum((uint16_t)it6161.mipi_rx.crc_frame_number));
521 // Setup 1 sec timer interrupt
522 MIPIRX_SetI2C_Byte(handle, 0x0b, 0x40, 0x40);
523 if (it6161.hdmi_tx.hdmitx_bypass_mode != 0x0U)
524 {
525 HDMITX_SetI2C_Byte(
526 handle, HDMI_TX_PATTERN_GENERATOR_REGA9, HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_MASK,
527 HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM((uint32_t)it6161.hdmi_tx.hdmitx_bypass_mode));
528 }
529 else
530 {
531 HDMITX_GenerateBlankTiming(handle);
532 }
533 HDMITX_VideoReset(handle);
534 }
535 else
536 {
537 MIPIRX_DEBUG_PRINTF("PVidStb Change to LOW ...\r\n");
538 }
539 }
540
541 if ((Reg06 & 0x20U) != 0x0U)
542 {
543 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x20);
544 #if (!DisPHSyncErr)
545 MIPIRX_DEBUG_PRINTF("PPS PHSync Error Interrupt !!!\r\n");
546 #endif // #if (DisPHSyncErr == false)
547 }
548
549 #if (!EnMBPM)
550 if ((Reg06 & 0x40U) != 0x0U)
551 {
552 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x40);
553 MIPIRX_DEBUG_PRINTF("PPS PHDE Error Interrupt !!!\r\n");
554 }
555
556 if ((Reg06 & 0x80U) != 0x0U)
557 {
558 MIPIRX_WriteI2C_Byte(handle, 0x06, 0x80);
559 MIPIRX_DEBUG_PRINTF("PPS MVDE Error Interrupt !!!\r\n");
560 }
561 #endif // #if (EnMBPM == false)
562 }
563
MIPIRX_Reg07_Process(display_handle_t * handle,uint8_t Reg07)564 void MIPIRX_Reg07_Process(display_handle_t *handle, uint8_t Reg07)
565 {
566 // Interrupt Reg07
567 if ((Reg07 & 0x01U) != 0x0U)
568 {
569 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x01);
570 MIPIRX_DEBUG_PRINTF("PatGen PPGVidStb change Interrupt !!!\r\n");
571 }
572 if ((Reg07 & 0x02U) != 0x0U)
573 {
574 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x02);
575 MIPIRX_DEBUG_PRINTF("PPS Data Byte Error Interrupt !!!\r\n");
576 }
577
578 if ((Reg07 & 0x04U) != 0x0U)
579 {
580 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x04);
581 MIPIRX_DEBUG_PRINTF("PPS CMOff Interrupt !!!\r\n");
582 }
583
584 if ((Reg07 & 0x08U) != 0x0U)
585 {
586 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x08);
587 MIPIRX_DEBUG_PRINTF("PPS CMOn Interrupt !!!\r\n");
588 }
589
590 if ((Reg07 & 0x10U) != 0x0U)
591 {
592 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x10);
593 MIPIRX_DEBUG_PRINTF("PPS ShutDone cmd Interrupt !!!\r\n");
594 }
595
596 if ((Reg07 & 0x20U) != 0x0U)
597 {
598 MIPIRX_WriteI2C_Byte(handle, 0x07, 0x20);
599 MIPIRX_DEBUG_PRINTF("PPS TurnOn Interrupt !!!\r\n");
600 }
601
602 if ((Reg07 & 0x40U) != 0x0U || (Reg07 & 0x80U) != 0x0U)
603 {
604 if ((Reg07 & 0x40U) != 0x0U)
605 {
606 MIPIRX_DEBUG_PRINTF("PPS FIFO over read Interrupt !!!\r\n");
607 MIPIRX_SetI2C_Byte(handle, 0x0a, 0x40, 0x40);
608 }
609 if ((Reg07 & 0x80U) != 0x0U)
610 {
611 MIPIRX_DEBUG_PRINTF("PPS FIFO over write Interrupt !!!\r\n");
612 MIPIRX_SetI2C_Byte(handle, 0x0a, 0x80, 0x80);
613 }
614 MIPIRX_DEBUG_PRINTF("----------------------------------------------------\r\n");
615 }
616 }
617
MIPIRX_Reg08_Process(display_handle_t * handle,uint8_t Reg08)618 void MIPIRX_Reg08_Process(display_handle_t *handle, uint8_t Reg08)
619 {
620 uint8_t value = 0U;
621
622 // Interrupt Reg08
623 if ((Reg08 & 0x01U) != 0x0U)
624 {
625 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x01);
626 #if (!DisECCErr)
627 MIPIRX_DEBUG_PRINTF("ECC 1-bit Error Interrupt !!!\r\n");
628 #endif // #if (DisECCErr == false)
629 }
630
631 if ((Reg08 & 0x02U) != 0x0U)
632 {
633 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x02);
634 #if (!DisECCErr)
635 MIPIRX_DEBUG_PRINTF("ECC 2-bit Error Interrupt !!!\r\n");
636 #endif // #if (DisECCErr == false)
637 }
638
639 if ((Reg08 & 0x04U) != 0x0U)
640 {
641 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x04);
642 MIPIRX_DEBUG_PRINTF("LM FIFO Error Interrupt !!!\r\n");
643 }
644
645 if ((Reg08 & 0x08U) != 0x0U)
646 {
647 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x08);
648 MIPIRX_DEBUG_PRINTF("CRC Error Interrupt !!!\r\n");
649 }
650
651 if ((Reg08 & 0x10U) != 0x0U)
652 {
653 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x10);
654 MIPIRX_DEBUG_PRINTF("MCLK Off Interrupt !!!\r\n");
655 }
656
657 if ((Reg08 & 0x20U) != 0x0U)
658 {
659 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x20);
660 MIPIRX_DEBUG_PRINTF("PPI FIFO OverWrite Interrupt !!!\r\n");
661 }
662
663 if ((Reg08 & 0x40U) != 0x0U)
664 {
665 MIPIRX_WriteI2C_Byte(handle, 0x08, 0x40);
666
667 MIPIRX_DEBUG_PRINTF("FW Timer Interrupt !!!\r\n");
668 MIPIRX_SetI2C_Byte(handle, 0x0b, 0x40, 0x00);
669 MIPIRX_ReadI2C_Byte(handle, 0xC1, &value);
670 if ((value & 0x03U) == 0x03U)
671 {
672 MIPIRX_DEBUG_PRINTF("CRC Fail !!!\r\n");
673 }
674 if ((value & 0x05U) == 0x05U)
675 {
676 MIPIRX_DEBUG_PRINTF("CRC Pass !!!\r\n");
677 MIPIRX_DEBUG_PRINTF("CRCR = 0x%02X !!!\r\n", MIPIRX_ReadI2C_Byte(handle, 0xC2, &value));
678 MIPIRX_DEBUG_PRINTF("CRCG = 0x%02X !!!\r\n", MIPIRX_ReadI2C_Byte(handle, 0xC3, &value));
679 MIPIRX_DEBUG_PRINTF("CRCR = 0x%02X !!!\r\n", MIPIRX_ReadI2C_Byte(handle, 0xC4, &value));
680 }
681 }
682 }
683
MIPIRX_DevLoopProc(display_handle_t * handle)684 void MIPIRX_DevLoopProc(display_handle_t *handle) // mipirx_irq
685 {
686 uint8_t Reg06 = 0U, Reg07 = 0U, Reg08 = 0U;
687
688 MIPIRX_ReadI2C_Byte(handle, 0x06, &Reg06);
689 MIPIRX_ReadI2C_Byte(handle, 0x07, &Reg07);
690 MIPIRX_ReadI2C_Byte(handle, 0x08, &Reg08);
691 if (Reg06 == 0x00U && Reg07 == 0x00U && Reg08 == 0x00U)
692 {
693 return;
694 }
695
696 MIPIRX_Reg08_Process(handle, Reg08);
697 MIPIRX_Reg06_Process(handle, Reg06);
698 MIPIRX_Reg07_Process(handle, Reg07);
699 MIPIRX_DumpRegs(handle);
700 }
701
