Home
last modified time | relevance | path

Searched defs:MINTSET (Results 1 – 25 of 34) sorted by relevance

12

/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h110 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC864/
DLPC864.h4691 …__IO uint32_t MINTSET; /**< Controller Interrupt Set Register, offset: 0… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC865/
DLPC865.h4693 …__IO uint32_t MINTSET; /**< Controller Interrupt Set Register, offset: 0… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10241 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
DMIMXRT685S_cm33.h16982 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h16982 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h21981 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19794 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
DMIMXRT595S_cm33.h26753 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h21981 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h26752 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26749 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h21980 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h34273 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
DMCXN946_cm33_core1.h34273 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core1.h33846 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
DMCXN547_cm33_core0.h33846 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h33846 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
DMCXN546_cm33_core1.h33846 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core0.h34273 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
DMCXN947_cm33_core1.h34273 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h40893 __IO uint32_t MINTSET; /**< Master Interrupt Set, offset: 0x90 */ member
DMIMX9352_ca55.h36183 __IO uint32_t MINTSET; /**< Master Interrupt Set, offset: 0x90 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h19414 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h19414 …__IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 … member

12