1 /* 2 * Copyright (c) 2016 Piotr Mienkowski 3 * Copyright 2022 NXP 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /** @file 9 * @brief Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_NET_MII_H_ 13 #define ZEPHYR_INCLUDE_NET_MII_H_ 14 15 /** 16 * @brief Ethernet MII (media independent interface) functions 17 * @defgroup ethernet_mii Ethernet MII Support Functions 18 * @since 1.7 19 * @version 0.8.0 20 * @ingroup ethernet 21 * @{ 22 */ 23 24 /* MII management registers */ 25 /** Basic Mode Control Register */ 26 #define MII_BMCR 0x0 27 /** Basic Mode Status Register */ 28 #define MII_BMSR 0x1 29 /** PHY ID 1 Register */ 30 #define MII_PHYID1R 0x2 31 /** PHY ID 2 Register */ 32 #define MII_PHYID2R 0x3 33 /** Auto-Negotiation Advertisement Register */ 34 #define MII_ANAR 0x4 35 /** Auto-Negotiation Link Partner Ability Reg */ 36 #define MII_ANLPAR 0x5 37 /** Auto-Negotiation Expansion Register */ 38 #define MII_ANER 0x6 39 /** Auto-Negotiation Next Page Transmit Register */ 40 #define MII_ANNPTR 0x7 41 /** Auto-Negotiation Link Partner Received Next Page Reg */ 42 #define MII_ANLPRNPR 0x8 43 /** 1000BASE-T Control Register */ 44 #define MII_1KTCR 0x9 45 /** 1000BASE-T Status Register */ 46 #define MII_1KSTSR 0xa 47 /** MMD Access Control Register */ 48 #define MII_MMD_ACR 0xd 49 /** MMD Access Address Data Register */ 50 #define MII_MMD_AADR 0xe 51 /** Extended Status Register */ 52 #define MII_ESTAT 0xf 53 54 /* Basic Mode Control Register (BMCR) bit definitions */ 55 /** PHY reset */ 56 #define MII_BMCR_RESET (1 << 15) 57 /** enable loopback mode */ 58 #define MII_BMCR_LOOPBACK (1 << 14) 59 /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ 60 #define MII_BMCR_SPEED_LSB (1 << 13) 61 /** Auto-Negotiation enable */ 62 #define MII_BMCR_AUTONEG_ENABLE (1 << 12) 63 /** power down mode */ 64 #define MII_BMCR_POWER_DOWN (1 << 11) 65 /** isolate electrically PHY from MII */ 66 #define MII_BMCR_ISOLATE (1 << 10) 67 /** restart auto-negotiation */ 68 #define MII_BMCR_AUTONEG_RESTART (1 << 9) 69 /** full duplex mode */ 70 #define MII_BMCR_DUPLEX_MODE (1 << 8) 71 /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ 72 #define MII_BMCR_SPEED_MSB (1 << 6) 73 /** Link Speed Field */ 74 #define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13) 75 /** select speed 10 Mb/s */ 76 #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13) 77 /** select speed 100 Mb/s */ 78 #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13) 79 /** select speed 1000 Mb/s */ 80 #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13) 81 82 /* Basic Mode Status Register (BMSR) bit definitions */ 83 /** 100BASE-T4 capable */ 84 #define MII_BMSR_100BASE_T4 (1 << 15) 85 /** 100BASE-X full duplex capable */ 86 #define MII_BMSR_100BASE_X_FULL (1 << 14) 87 /** 100BASE-X half duplex capable */ 88 #define MII_BMSR_100BASE_X_HALF (1 << 13) 89 /** 10 Mb/s full duplex capable */ 90 #define MII_BMSR_10_FULL (1 << 12) 91 /** 10 Mb/s half duplex capable */ 92 #define MII_BMSR_10_HALF (1 << 11) 93 /** 100BASE-T2 full duplex capable */ 94 #define MII_BMSR_100BASE_T2_FULL (1 << 10) 95 /** 100BASE-T2 half duplex capable */ 96 #define MII_BMSR_100BASE_T2_HALF (1 << 9) 97 /** extend status information in reg 15 */ 98 #define MII_BMSR_EXTEND_STATUS (1 << 8) 99 /** PHY accepts management frames with preamble suppressed */ 100 #define MII_BMSR_MF_PREAMB_SUPPR (1 << 6) 101 /** Auto-negotiation process completed */ 102 #define MII_BMSR_AUTONEG_COMPLETE (1 << 5) 103 /** remote fault detected */ 104 #define MII_BMSR_REMOTE_FAULT (1 << 4) 105 /** PHY is able to perform Auto-Negotiation */ 106 #define MII_BMSR_AUTONEG_ABILITY (1 << 3) 107 /** link is up */ 108 #define MII_BMSR_LINK_STATUS (1 << 2) 109 /** jabber condition detected */ 110 #define MII_BMSR_JABBER_DETECT (1 << 1) 111 /** extended register capabilities */ 112 #define MII_BMSR_EXTEND_CAPAB (1 << 0) 113 114 /* Auto-negotiation Advertisement Register (ANAR) bit definitions */ 115 /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */ 116 /** next page */ 117 #define MII_ADVERTISE_NEXT_PAGE (1 << 15) 118 /** link partner acknowledge response */ 119 #define MII_ADVERTISE_LPACK (1 << 14) 120 /** remote fault */ 121 #define MII_ADVERTISE_REMOTE_FAULT (1 << 13) 122 /** try for asymmetric pause */ 123 #define MII_ADVERTISE_ASYM_PAUSE (1 << 11) 124 /** try for pause */ 125 #define MII_ADVERTISE_PAUSE (1 << 10) 126 /** try for 100BASE-T4 support */ 127 #define MII_ADVERTISE_100BASE_T4 (1 << 9) 128 /** try for 100BASE-X full duplex support */ 129 #define MII_ADVERTISE_100_FULL (1 << 8) 130 /** try for 100BASE-X support */ 131 #define MII_ADVERTISE_100_HALF (1 << 7) 132 /** try for 10 Mb/s full duplex support */ 133 #define MII_ADVERTISE_10_FULL (1 << 6) 134 /** try for 10 Mb/s half duplex support */ 135 #define MII_ADVERTISE_10_HALF (1 << 5) 136 /** Selector Field Mask */ 137 #define MII_ADVERTISE_SEL_MASK (0x1F << 0) 138 /** Selector Field */ 139 #define MII_ADVERTISE_SEL_IEEE_802_3 0x01 140 141 /* 1000BASE-T Control Register bit definitions */ 142 /** try for 1000BASE-T full duplex support */ 143 #define MII_ADVERTISE_1000_FULL (1 << 9) 144 /** try for 1000BASE-T half duplex support */ 145 #define MII_ADVERTISE_1000_HALF (1 << 8) 146 147 /** Advertise all speeds */ 148 #define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\ 149 MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\ 150 MII_ADVERTISE_SEL_IEEE_802_3) 151 152 /* Extended Status Register bit definitions */ 153 /** 1000BASE-X full-duplex capable */ 154 #define MII_ESTAT_1000BASE_X_FULL (1 << 15) 155 /** 1000BASE-X half-duplex capable */ 156 #define MII_ESTAT_1000BASE_X_HALF (1 << 14) 157 /** 1000BASE-T full-duplex capable */ 158 #define MII_ESTAT_1000BASE_T_FULL (1 << 13) 159 /** 1000BASE-T half-duplex capable */ 160 #define MII_ESTAT_1000BASE_T_HALF (1 << 12) 161 162 /** 163 * @} 164 */ 165 166 #endif /* ZEPHYR_INCLUDE_NET_MII_H_ */ 167
